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r8169: TSO fixes.
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
1da177e4 29
99f252b0 30#include <asm/system.h>
1da177e4
LT		 31#include <asm/io.h>
32#include <asm/irq.h>
33
865c652d 34#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 35#define MODULENAME "r8169"
36#define PFX MODULENAME ": "
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 42#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 43
1da177e4
LT		 44#ifdef RTL8169_DEBUG
45#define assert(expr) \
5b0384f4
FR		 46 if (!(expr)) { \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 48 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 49 }
06fa7358
JP		 50#define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 52#else
53#define assert(expr) do {} while (0)
54#define dprintk(fmt, args...) do {} while (0)
55#endif /* RTL8169_DEBUG */
56
b57b7e5a 57#define R8169_MSG_DEFAULT \
f0e837d9 58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 59
1da177e4
LT		 60#define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 65static const int multicast_filter_limit = 32;
1da177e4
LT		 66
67/* MAC address length */
68#define MAC_ADDR_LEN 6
69
9c14ceaf 70#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 71#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
f21b75e9 101 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 102 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 107 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 108 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 112 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 113 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 121 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 122 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 123 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 124 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 125 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 126 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 128 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
5a5e4443
HW		 130 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
4804b3b3 132 RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
01dc7fec 133 RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134 RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
1da177e4
LT		 135};
136
2b7b4318
FR		 137enum rtl_tx_desc_version {
138 RTL_TD_0 = 0,
139 RTL_TD_1 = 1,
140};
141
142#define _R(NAME,MAC,TD) \
143 { .name = NAME, .mac_version = MAC, .txd_version = TD }
1da177e4 144
3c6bee1d 145static const struct {
1da177e4
LT		 146 const char *name;
147 u8 mac_version;
2b7b4318 148 enum rtl_tx_desc_version txd_version;
1da177e4 149} rtl_chip_info[] = {
2b7b4318
FR		 150 _R("RTL8169", RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151 _R("RTL8169s", RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152 _R("RTL8110s", RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156 _R("RTL8102e", RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157 _R("RTL8102e", RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158 _R("RTL8102e", RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159 _R("RTL8101e", RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162 _R("RTL8101e", RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163 _R("RTL8100e", RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164 _R("RTL8100e", RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166 _R("RTL8101e", RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178 _R("RTL8105e", RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179 _R("RTL8105e", RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, RTL_TD_1) // PCI-E
1da177e4
LT		 183};
184#undef _R
185
bcf0bf90
FR		 186enum cfg_version {
187 RTL_CFG_0 = 0x00,
188 RTL_CFG_1,
189 RTL_CFG_2
190};
191
07ce4064
FR		 192static void rtl_hw_start_8169(struct net_device *);
193static void rtl_hw_start_8168(struct net_device *);
194static void rtl_hw_start_8101(struct net_device *);
195
a3aa1884 196static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 197 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 198 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 199 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 200 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 201 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
202 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 203 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 204 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
205 { PCI_VENDOR_ID_LINKSYS, 0x1032,
206 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 207 { 0x0001, 0x8168,
208 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 209 {0,},
210};
211
212MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
213
6f0333b8 214static int rx_buf_sz = 16383;
4300e8c7 215static int use_dac;
b57b7e5a
SH		 216static struct {
217 u32 msg_enable;
218} debug = { -1 };
1da177e4 219
07d3f51f
FR		 220enum rtl_registers {
221 MAC0 = 0, /* Ethernet hardware address. */
773d2021 222 MAC4 = 4,
07d3f51f
FR		 223 MAR0 = 8, /* Multicast filter. */
224 CounterAddrLow = 0x10,
225 CounterAddrHigh = 0x14,
226 TxDescStartAddrLow = 0x20,
227 TxDescStartAddrHigh = 0x24,
228 TxHDescStartAddrLow = 0x28,
229 TxHDescStartAddrHigh = 0x2c,
230 FLASH = 0x30,
231 ERSR = 0x36,
232 ChipCmd = 0x37,
233 TxPoll = 0x38,
234 IntrMask = 0x3c,
235 IntrStatus = 0x3e,
236 TxConfig = 0x40,
237 RxConfig = 0x44,
2b7b4318
FR		 238
239#define RTL_RX_CONFIG_MASK 0xff7e1880u
240
07d3f51f
FR		 241 RxMissed = 0x4c,
242 Cfg9346 = 0x50,
243 Config0 = 0x51,
244 Config1 = 0x52,
245 Config2 = 0x53,
246 Config3 = 0x54,
247 Config4 = 0x55,
248 Config5 = 0x56,
249 MultiIntr = 0x5c,
250 PHYAR = 0x60,
07d3f51f
FR		 251 PHYstatus = 0x6c,
252 RxMaxSize = 0xda,
253 CPlusCmd = 0xe0,
254 IntrMitigate = 0xe2,
255 RxDescAddrLow = 0xe4,
256 RxDescAddrHigh = 0xe8,
f0298f81 257 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
258
259#define NoEarlyTx 0x3f /* Max value : no early transmit. */
260
261 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
262
263#define TxPacketMax (8064 >> 7)
264
07d3f51f
FR		 265 FuncEvent = 0xf0,
266 FuncEventMask = 0xf4,
267 FuncPresetState = 0xf8,
268 FuncForceEvent = 0xfc,
1da177e4
LT		 269};
270
f162a5d1
FR		 271enum rtl8110_registers {
272 TBICSR = 0x64,
273 TBI_ANAR = 0x68,
274 TBI_LPAR = 0x6a,
275};
276
277enum rtl8168_8101_registers {
278 CSIDR = 0x64,
279 CSIAR = 0x68,
280#define CSIAR_FLAG 0x80000000
281#define CSIAR_WRITE_CMD 0x80000000
282#define CSIAR_BYTE_ENABLE 0x0f
283#define CSIAR_BYTE_ENABLE_SHIFT 12
284#define CSIAR_ADDR_MASK 0x0fff
065c27c1 285 PMCH = 0x6f,
f162a5d1
FR		 286 EPHYAR = 0x80,
287#define EPHYAR_FLAG 0x80000000
288#define EPHYAR_WRITE_CMD 0x80000000
289#define EPHYAR_REG_MASK 0x1f
290#define EPHYAR_REG_SHIFT 16
291#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 292 DLLPR = 0xd0,
293#define PM_SWITCH (1 << 6)
f162a5d1
FR		 294 DBG_REG = 0xd1,
295#define FIX_NAK_1 (1 << 4)
296#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 297 TWSI = 0xd2,
298 MCU = 0xd3,
299#define EN_NDP (1 << 3)
300#define EN_OOB_RESET (1 << 2)
daf9df6d 301 EFUSEAR = 0xdc,
302#define EFUSEAR_FLAG 0x80000000
303#define EFUSEAR_WRITE_CMD 0x80000000
304#define EFUSEAR_READ_CMD 0x00000000
305#define EFUSEAR_REG_MASK 0x03ff
306#define EFUSEAR_REG_SHIFT 8
307#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 308};
309
c0e45c1c 310enum rtl8168_registers {
b646d900 311 ERIDR = 0x70,
312 ERIAR = 0x74,
313#define ERIAR_FLAG 0x80000000
314#define ERIAR_WRITE_CMD 0x80000000
315#define ERIAR_READ_CMD 0x00000000
316#define ERIAR_ADDR_BYTE_ALIGN 4
317#define ERIAR_EXGMAC 0
318#define ERIAR_MSIX 1
319#define ERIAR_ASF 2
320#define ERIAR_TYPE_SHIFT 16
321#define ERIAR_BYTEEN 0x0f
322#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 323 EPHY_RXER_NUM = 0x7c,
324 OCPDR = 0xb0, /* OCP GPHY access */
325#define OCPDR_WRITE_CMD 0x80000000
326#define OCPDR_READ_CMD 0x00000000
327#define OCPDR_REG_MASK 0x7f
328#define OCPDR_GPHY_REG_SHIFT 16
329#define OCPDR_DATA_MASK 0xffff
330 OCPAR = 0xb4,
331#define OCPAR_FLAG 0x80000000
332#define OCPAR_GPHY_WRITE_CMD 0x8000f060
333#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 334 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
335 MISC = 0xf0, /* 8168e only. */
336 txpla_rst = (1 << 29)
c0e45c1c 337};
338
07d3f51f 339enum rtl_register_content {
1da177e4 340 /* InterruptStatusBits */
07d3f51f
FR		 341 SYSErr = 0x8000,
342 PCSTimeout = 0x4000,
343 SWInt = 0x0100,
344 TxDescUnavail = 0x0080,
345 RxFIFOOver = 0x0040,
346 LinkChg = 0x0020,
347 RxOverflow = 0x0010,
348 TxErr = 0x0008,
349 TxOK = 0x0004,
350 RxErr = 0x0002,
351 RxOK = 0x0001,
1da177e4
LT		 352
353 /* RxStatusDesc */
9dccf611
FR		 354 RxFOVF = (1 << 23),
355 RxRWT = (1 << 22),
356 RxRES = (1 << 21),
357 RxRUNT = (1 << 20),
358 RxCRC = (1 << 19),
1da177e4
LT		 359
360 /* ChipCmdBits */
07d3f51f
FR		 361 CmdReset = 0x10,
362 CmdRxEnb = 0x08,
363 CmdTxEnb = 0x04,
364 RxBufEmpty = 0x01,
1da177e4 365
275391a4
FR		 366 /* TXPoll register p.5 */
367 HPQ = 0x80, /* Poll cmd on the high prio queue */
368 NPQ = 0x40, /* Poll cmd on the low prio queue */
369 FSWInt = 0x01, /* Forced software interrupt */
370
1da177e4 371 /* Cfg9346Bits */
07d3f51f
FR		 372 Cfg9346_Lock = 0x00,
373 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 374
375 /* rx_mode_bits */
07d3f51f
FR		 376 AcceptErr = 0x20,
377 AcceptRunt = 0x10,
378 AcceptBroadcast = 0x08,
379 AcceptMulticast = 0x04,
380 AcceptMyPhys = 0x02,
381 AcceptAllPhys = 0x01,
1da177e4
LT		 382
383 /* RxConfigBits */
07d3f51f
FR		 384 RxCfgFIFOShift = 13,
385 RxCfgDMAShift = 8,
1da177e4
LT		 386
387 /* TxConfigBits */
388 TxInterFrameGapShift = 24,
389 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
390
5d06a99f 391 /* Config1 register p.24 */
f162a5d1
FR		 392 LEDS1 = (1 << 7),
393 LEDS0 = (1 << 6),
fbac58fc 394 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 395 Speed_down = (1 << 4),
396 MEMMAP = (1 << 3),
397 IOMAP = (1 << 2),
398 VPD = (1 << 1),
5d06a99f
FR		 399 PMEnable = (1 << 0), /* Power Management Enable */
400
6dccd16b
FR		 401 /* Config2 register p. 25 */
402 PCI_Clock_66MHz = 0x01,
403 PCI_Clock_33MHz = 0x00,
404
61a4dcc2
FR		 405 /* Config3 register p.25 */
406 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
407 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 408 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 409
5d06a99f 410 /* Config5 register p.27 */
61a4dcc2
FR		 411 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
412 MWF = (1 << 5), /* Accept Multicast wakeup frame */
413 UWF = (1 << 4), /* Accept Unicast wakeup frame */
01dc7fec 414 spi_en = (1 << 3),
61a4dcc2 415 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 416 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
417
1da177e4
LT		 418 /* TBICSR p.28 */
419 TBIReset = 0x80000000,
420 TBILoopback = 0x40000000,
421 TBINwEnable = 0x20000000,
422 TBINwRestart = 0x10000000,
423 TBILinkOk = 0x02000000,
424 TBINwComplete = 0x01000000,
425
426 /* CPlusCmd p.31 */
f162a5d1
FR		 427 EnableBist = (1 << 15), // 8168 8101
428 Mac_dbgo_oe = (1 << 14), // 8168 8101
429 Normal_mode = (1 << 13), // unused
430 Force_half_dup = (1 << 12), // 8168 8101
431 Force_rxflow_en = (1 << 11), // 8168 8101
432 Force_txflow_en = (1 << 10), // 8168 8101
433 Cxpl_dbg_sel = (1 << 9), // 8168 8101
434 ASF = (1 << 8), // 8168 8101
435 PktCntrDisable = (1 << 7), // 8168 8101
436 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 437 RxVlan = (1 << 6),
438 RxChkSum = (1 << 5),
439 PCIDAC = (1 << 4),
440 PCIMulRW = (1 << 3),
0e485150
FR		 441 INTT_0 = 0x0000, // 8168
442 INTT_1 = 0x0001, // 8168
443 INTT_2 = 0x0002, // 8168
444 INTT_3 = 0x0003, // 8168
1da177e4
LT		 445
446 /* rtl8169_PHYstatus */
07d3f51f
FR		 447 TBI_Enable = 0x80,
448 TxFlowCtrl = 0x40,
449 RxFlowCtrl = 0x20,
450 _1000bpsF = 0x10,
451 _100bps = 0x08,
452 _10bps = 0x04,
453 LinkStatus = 0x02,
454 FullDup = 0x01,
1da177e4 455
1da177e4 456 /* _TBICSRBit */
07d3f51f 457 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 458
459 /* DumpCounterCommand */
07d3f51f 460 CounterDump = 0x8,
1da177e4
LT		 461};
462
2b7b4318
FR		 463enum rtl_desc_bit {
464 /* First doubleword. */
1da177e4
LT		 465 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
466 RingEnd = (1 << 30), /* End of descriptor ring */
467 FirstFrag = (1 << 29), /* First segment of a packet */
468 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 469};
470
471/* Generic case. */
472enum rtl_tx_desc_bit {
473 /* First doubleword. */
474 TD_LSO = (1 << 27), /* Large Send Offload */
475#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 476
2b7b4318
FR		 477 /* Second doubleword. */
478 TxVlanTag = (1 << 17), /* Add VLAN tag */
479};
480
481/* 8169, 8168b and 810x except 8102e. */
482enum rtl_tx_desc_bit_0 {
483 /* First doubleword. */
484#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
485 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
486 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
487 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
488};
489
490/* 8102e, 8168c and beyond. */
491enum rtl_tx_desc_bit_1 {
492 /* Second doubleword. */
493#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
494 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
495 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
496 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
497};
1da177e4 498
2b7b4318
FR		 499static const struct rtl_tx_desc_info {
500 struct {
501 u32 udp;
502 u32 tcp;
503 } checksum;
504 u16 mss_shift;
505 u16 opts_offset;
506} tx_desc_info [] = {
507 [RTL_TD_0] = {
508 .checksum = {
509 .udp = TD0_IP_CS | TD0_UDP_CS,
510 .tcp = TD0_IP_CS | TD0_TCP_CS
511 },
512 .mss_shift = TD0_MSS_SHIFT,
513 .opts_offset = 0
514 },
515 [RTL_TD_1] = {
516 .checksum = {
517 .udp = TD1_IP_CS | TD1_UDP_CS,
518 .tcp = TD1_IP_CS | TD1_TCP_CS
519 },
520 .mss_shift = TD1_MSS_SHIFT,
521 .opts_offset = 1
522 }
523};
524
525enum rtl_rx_desc_bit {
1da177e4
LT		 526 /* Rx private */
527 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
528 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
529
530#define RxProtoUDP (PID1)
531#define RxProtoTCP (PID0)
532#define RxProtoIP (PID1 | PID0)
533#define RxProtoMask RxProtoIP
534
535 IPFail = (1 << 16), /* IP checksum failed */
536 UDPFail = (1 << 15), /* UDP/IP checksum failed */
537 TCPFail = (1 << 14), /* TCP/IP checksum failed */
538 RxVlanTag = (1 << 16), /* VLAN tag available */
539};
540
541#define RsvdMask 0x3fffc000
542
543struct TxDesc {
6cccd6e7
REB		 544 __le32 opts1;
545 __le32 opts2;
546 __le64 addr;
1da177e4
LT		 547};
548
549struct RxDesc {
6cccd6e7
REB		 550 __le32 opts1;
551 __le32 opts2;
552 __le64 addr;
1da177e4
LT		 553};
554
555struct ring_info {
556 struct sk_buff *skb;
557 u32 len;
558 u8 __pad[sizeof(void *) - sizeof(u32)];
559};
560
f23e7fda 561enum features {
ccdffb9a
FR		 562 RTL_FEATURE_WOL = (1 << 0),
563 RTL_FEATURE_MSI = (1 << 1),
564 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 565};
566
355423d0
IV		 567struct rtl8169_counters {
568 __le64 tx_packets;
569 __le64 rx_packets;
570 __le64 tx_errors;
571 __le32 rx_errors;
572 __le16 rx_missed;
573 __le16 align_errors;
574 __le32 tx_one_collision;
575 __le32 tx_multi_collision;
576 __le64 rx_unicast;
577 __le64 rx_broadcast;
578 __le32 rx_multicast;
579 __le16 tx_aborted;
580 __le16 tx_underun;
581};
582
1da177e4
LT		 583struct rtl8169_private {
584 void __iomem *mmio_addr; /* memory map physical address */
585 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 586 struct net_device *dev;
bea3348e 587 struct napi_struct napi;
1da177e4 588 spinlock_t lock; /* spin lock flag */
b57b7e5a 589 u32 msg_enable;
2b7b4318
FR		 590 u16 txd_version;
591 u16 mac_version;
1da177e4
LT		 592 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
593 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
594 u32 dirty_rx;
595 u32 dirty_tx;
596 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
597 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
598 dma_addr_t TxPhyAddr;
599 dma_addr_t RxPhyAddr;
6f0333b8 600 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 601 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 602 struct timer_list timer;
603 u16 cp_cmd;
0e485150
FR		 604 u16 intr_event;
605 u16 napi_event;
1da177e4 606 u16 intr_mask;
1da177e4 607 int phy_1000_ctrl_reg;
c0e45c1c 608
609 struct mdio_ops {
610 void (*write)(void __iomem *, int, int);
611 int (*read)(void __iomem *, int);
612 } mdio_ops;
613
065c27c1 614 struct pll_power_ops {
615 void (*down)(struct rtl8169_private *);
616 void (*up)(struct rtl8169_private *);
617 } pll_power_ops;
618
54405cde 619 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 620 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 621 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 622 void (*hw_start)(struct net_device *);
4da19633 623 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 624 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 625 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 626 int pcie_cap;
c4028958 627 struct delayed_work task;
f23e7fda 628 unsigned features;
ccdffb9a
FR		 629
630 struct mii_if_info mii;
355423d0 631 struct rtl8169_counters counters;
e1759441 632 u32 saved_wolopts;
f1e02ed1 633
634 const struct firmware *fw;
1da177e4
LT		 635};
636
979b6c13 637MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 638MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 639module_param(use_dac, int, 0);
4300e8c7 640MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 641module_param_named(debug, debug.msg_enable, int, 0);
642MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 643MODULE_LICENSE("GPL");
644MODULE_VERSION(RTL8169_VERSION);
bca03d5f 645MODULE_FIRMWARE(FIRMWARE_8168D_1);
646MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 647MODULE_FIRMWARE(FIRMWARE_8168E_1);
648MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 649MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 650
651static int rtl8169_open(struct net_device *dev);
61357325
SH		 652static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
653 struct net_device *dev);
7d12e780 654static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 655static int rtl8169_init_ring(struct net_device *dev);
07ce4064 656static void rtl_hw_start(struct net_device *dev);
1da177e4 657static int rtl8169_close(struct net_device *dev);
07ce4064 658static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 659static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 660static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 661static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 662 void __iomem *, u32 budget);
4dcb7d33 663static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 664static void rtl8169_down(struct net_device *dev);
99f252b0 665static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 666static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 667
1da177e4 668static const unsigned int rtl8169_rx_config =
5b0384f4 669 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 670
b646d900 671static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
672{
673 void __iomem *ioaddr = tp->mmio_addr;
674 int i;
675
676 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
677 for (i = 0; i < 20; i++) {
678 udelay(100);
679 if (RTL_R32(OCPAR) & OCPAR_FLAG)
680 break;
681 }
682 return RTL_R32(OCPDR);
683}
684
685static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
686{
687 void __iomem *ioaddr = tp->mmio_addr;
688 int i;
689
690 RTL_W32(OCPDR, data);
691 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
692 for (i = 0; i < 20; i++) {
693 udelay(100);
694 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
695 break;
696 }
697}
698
fac5b3ca 699static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 700{
fac5b3ca 701 void __iomem *ioaddr = tp->mmio_addr;
b646d900 702 int i;
703
704 RTL_W8(ERIDR, cmd);
705 RTL_W32(ERIAR, 0x800010e8);
706 msleep(2);
707 for (i = 0; i < 5; i++) {
708 udelay(100);
709 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
710 break;
711 }
712
fac5b3ca 713 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 714}
715
716#define OOB_CMD_RESET 0x00
717#define OOB_CMD_DRIVER_START 0x05
718#define OOB_CMD_DRIVER_STOP 0x06
719
720static void rtl8168_driver_start(struct rtl8169_private *tp)
721{
722 int i;
4804b3b3 723 u32 reg;
b646d900 724
725 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
726
4804b3b3 727 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
728 reg = 0xb8;
729 else
730 reg = 0x10;
731
b646d900 732 for (i = 0; i < 10; i++) {
733 msleep(10);
4804b3b3 734 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 735 break;
736 }
737}
738
739static void rtl8168_driver_stop(struct rtl8169_private *tp)
740{
741 int i;
4804b3b3 742 u32 reg;
b646d900 743
744 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
745
4804b3b3 746 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
747 reg = 0xb8;
748 else
749 reg = 0x10;
750
b646d900 751 for (i = 0; i < 10; i++) {
752 msleep(10);
4804b3b3 753 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 754 break;
755 }
756}
757
4804b3b3 758static int r8168dp_check_dash(struct rtl8169_private *tp)
759{
760 u32 reg;
761
762 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
763 reg = 0xb8;
764 else
765 reg = 0x10;
766
767 if (ocp_read(tp, 0xF, reg) & 0x00008000)
768 return 1;
769 else
770 return 0;
771}
b646d900 772
4da19633 773static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 774{
775 int i;
776
a6baf3af 777 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 778
2371408c 779 for (i = 20; i > 0; i--) {
07d3f51f
FR		 780 /*
781 * Check if the RTL8169 has completed writing to the specified
782 * MII register.
783 */
5b0384f4 784 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 785 break;
2371408c 786 udelay(25);
1da177e4 787 }
024a07ba 788 /*
81a95f04
TT		 789 * According to hardware specs a 20us delay is required after write
790 * complete indication, but before sending next command.
024a07ba 791 */
81a95f04 792 udelay(20);
1da177e4
LT		 793}
794
4da19633 795static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 796{
797 int i, value = -1;
798
a6baf3af 799 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 800
2371408c 801 for (i = 20; i > 0; i--) {
07d3f51f
FR		 802 /*
803 * Check if the RTL8169 has completed retrieving data from
804 * the specified MII register.
805 */
1da177e4 806 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 807 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 808 break;
809 }
2371408c 810 udelay(25);
1da177e4 811 }
81a95f04
TT		 812 /*
813 * According to hardware specs a 20us delay is required after read
814 * complete indication, but before sending next command.
815 */
816 udelay(20);
817
1da177e4
LT		 818 return value;
819}
820
c0e45c1c 821static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
822{
823 int i;
824
825 RTL_W32(OCPDR, data |
826 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
827 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
828 RTL_W32(EPHY_RXER_NUM, 0);
829
830 for (i = 0; i < 100; i++) {
831 mdelay(1);
832 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
833 break;
834 }
835}
836
837static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
838{
839 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
840 (value & OCPDR_DATA_MASK));
841}
842
843static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
844{
845 int i;
846
847 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
848
849 mdelay(1);
850 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
851 RTL_W32(EPHY_RXER_NUM, 0);
852
853 for (i = 0; i < 100; i++) {
854 mdelay(1);
855 if (RTL_R32(OCPAR) & OCPAR_FLAG)
856 break;
857 }
858
859 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
860}
861
e6de30d6 862#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
863
864static void r8168dp_2_mdio_start(void __iomem *ioaddr)
865{
866 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
867}
868
869static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
870{
871 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
872}
873
874static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
875{
876 r8168dp_2_mdio_start(ioaddr);
877
878 r8169_mdio_write(ioaddr, reg_addr, value);
879
880 r8168dp_2_mdio_stop(ioaddr);
881}
882
883static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
884{
885 int value;
886
887 r8168dp_2_mdio_start(ioaddr);
888
889 value = r8169_mdio_read(ioaddr, reg_addr);
890
891 r8168dp_2_mdio_stop(ioaddr);
892
893 return value;
894}
895
4da19633 896static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 897{
c0e45c1c 898 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 899}
900
4da19633 901static int rtl_readphy(struct rtl8169_private *tp, int location)
902{
c0e45c1c 903 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 904}
905
906static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
907{
908 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
909}
910
911static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 912{
913 int val;
914
4da19633 915 val = rtl_readphy(tp, reg_addr);
916 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 917}
918
ccdffb9a
FR		 919static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
920 int val)
921{
922 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 923
4da19633 924 rtl_writephy(tp, location, val);
ccdffb9a
FR		 925}
926
927static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
928{
929 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 930
4da19633 931 return rtl_readphy(tp, location);
ccdffb9a
FR		 932}
933
dacf8154
FR		 934static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
935{
936 unsigned int i;
937
938 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
939 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
940
941 for (i = 0; i < 100; i++) {
942 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
943 break;
944 udelay(10);
945 }
946}
947
948static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
949{
950 u16 value = 0xffff;
951 unsigned int i;
952
953 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
954
955 for (i = 0; i < 100; i++) {
956 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
957 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
958 break;
959 }
960 udelay(10);
961 }
962
963 return value;
964}
965
966static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
967{
968 unsigned int i;
969
970 RTL_W32(CSIDR, value);
971 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
972 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
973
974 for (i = 0; i < 100; i++) {
975 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
976 break;
977 udelay(10);
978 }
979}
980
981static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
982{
983 u32 value = ~0x00;
984 unsigned int i;
985
986 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
987 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
988
989 for (i = 0; i < 100; i++) {
990 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
991 value = RTL_R32(CSIDR);
992 break;
993 }
994 udelay(10);
995 }
996
997 return value;
998}
999
daf9df6d 1000static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1001{
1002 u8 value = 0xff;
1003 unsigned int i;
1004
1005 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1006
1007 for (i = 0; i < 300; i++) {
1008 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1009 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1010 break;
1011 }
1012 udelay(100);
1013 }
1014
1015 return value;
1016}
1017
1da177e4
LT		 1018static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1019{
1020 RTL_W16(IntrMask, 0x0000);
1021
1022 RTL_W16(IntrStatus, 0xffff);
1023}
1024
1025static void rtl8169_asic_down(void __iomem *ioaddr)
1026{
1027 RTL_W8(ChipCmd, 0x00);
1028 rtl8169_irq_mask_and_ack(ioaddr);
1029 RTL_R16(CPlusCmd);
1030}
1031
4da19633 1032static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1033{
4da19633 1034 void __iomem *ioaddr = tp->mmio_addr;
1035
1da177e4
LT		 1036 return RTL_R32(TBICSR) & TBIReset;
1037}
1038
4da19633 1039static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1040{
4da19633 1041 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1042}
1043
1044static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1045{
1046 return RTL_R32(TBICSR) & TBILinkOk;
1047}
1048
1049static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1050{
1051 return RTL_R8(PHYstatus) & LinkStatus;
1052}
1053
4da19633 1054static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1055{
4da19633 1056 void __iomem *ioaddr = tp->mmio_addr;
1057
1da177e4
LT		 1058 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1059}
1060
4da19633 1061static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1062{
1063 unsigned int val;
1064
4da19633 1065 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1066 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1067}
1068
e4fbce74 1069static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 1070 struct rtl8169_private *tp,
e4fbce74
RW		 1071 void __iomem *ioaddr,
1072 bool pm)
1da177e4
LT		 1073{
1074 unsigned long flags;
1075
1076 spin_lock_irqsave(&tp->lock, flags);
1077 if (tp->link_ok(ioaddr)) {
e1759441 1078 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1079 if (pm)
1080 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1081 netif_carrier_on(dev);
1519e57f
FR		 1082 if (net_ratelimit())
1083 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1084 } else {
1da177e4 1085 netif_carrier_off(dev);
bf82c189 1086 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1087 if (pm)
1088 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1089 }
1da177e4
LT		 1090 spin_unlock_irqrestore(&tp->lock, flags);
1091}
1092
e4fbce74
RW		 1093static void rtl8169_check_link_status(struct net_device *dev,
1094 struct rtl8169_private *tp,
1095 void __iomem *ioaddr)
1096{
1097 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1098}
1099
e1759441
RW		 1100#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1101
1102static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1103{
61a4dcc2
FR		 1104 void __iomem *ioaddr = tp->mmio_addr;
1105 u8 options;
e1759441 1106 u32 wolopts = 0;
61a4dcc2
FR		 1107
1108 options = RTL_R8(Config1);
1109 if (!(options & PMEnable))
e1759441 1110 return 0;
61a4dcc2
FR		 1111
1112 options = RTL_R8(Config3);
1113 if (options & LinkUp)
e1759441 1114 wolopts |= WAKE_PHY;
61a4dcc2 1115 if (options & MagicPacket)
e1759441 1116 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1117
1118 options = RTL_R8(Config5);
1119 if (options & UWF)
e1759441 1120 wolopts |= WAKE_UCAST;
61a4dcc2 1121 if (options & BWF)
e1759441 1122 wolopts |= WAKE_BCAST;
61a4dcc2 1123 if (options & MWF)
e1759441 1124 wolopts |= WAKE_MCAST;
61a4dcc2 1125
e1759441 1126 return wolopts;
61a4dcc2
FR		 1127}
1128
e1759441 1129static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1130{
1131 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1132
1133 spin_lock_irq(&tp->lock);
1134
1135 wol->supported = WAKE_ANY;
1136 wol->wolopts = __rtl8169_get_wol(tp);
1137
1138 spin_unlock_irq(&tp->lock);
1139}
1140
1141static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1142{
61a4dcc2 1143 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1144 unsigned int i;
350f7596 1145 static const struct {
61a4dcc2
FR		 1146 u32 opt;
1147 u16 reg;
1148 u8 mask;
1149 } cfg[] = {
1150 { WAKE_ANY, Config1, PMEnable },
1151 { WAKE_PHY, Config3, LinkUp },
1152 { WAKE_MAGIC, Config3, MagicPacket },
1153 { WAKE_UCAST, Config5, UWF },
1154 { WAKE_BCAST, Config5, BWF },
1155 { WAKE_MCAST, Config5, MWF },
1156 { WAKE_ANY, Config5, LanWake }
1157 };
1158
61a4dcc2
FR		 1159 RTL_W8(Cfg9346, Cfg9346_Unlock);
1160
1161 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1162 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1163 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1164 options |= cfg[i].mask;
1165 RTL_W8(cfg[i].reg, options);
1166 }
1167
1168 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1169}
1170
1171static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1172{
1173 struct rtl8169_private *tp = netdev_priv(dev);
1174
1175 spin_lock_irq(&tp->lock);
61a4dcc2 1176
f23e7fda
FR		 1177 if (wol->wolopts)
1178 tp->features |= RTL_FEATURE_WOL;
1179 else
1180 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1181 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1182 spin_unlock_irq(&tp->lock);
1183
ea80907f 1184 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1185
61a4dcc2
FR		 1186 return 0;
1187}
1188
1da177e4
LT		 1189static void rtl8169_get_drvinfo(struct net_device *dev,
1190 struct ethtool_drvinfo *info)
1191{
1192 struct rtl8169_private *tp = netdev_priv(dev);
1193
1194 strcpy(info->driver, MODULENAME);
1195 strcpy(info->version, RTL8169_VERSION);
1196 strcpy(info->bus_info, pci_name(tp->pci_dev));
1197}
1198
1199static int rtl8169_get_regs_len(struct net_device *dev)
1200{
1201 return R8169_REGS_SIZE;
1202}
1203
1204static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1205 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1206{
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208 void __iomem *ioaddr = tp->mmio_addr;
1209 int ret = 0;
1210 u32 reg;
1211
1212 reg = RTL_R32(TBICSR);
1213 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1214 (duplex == DUPLEX_FULL)) {
1215 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1216 } else if (autoneg == AUTONEG_ENABLE)
1217 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1218 else {
bf82c189
JP		 1219 netif_warn(tp, link, dev,
1220 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1221 ret = -EOPNOTSUPP;
1222 }
1223
1224 return ret;
1225}
1226
1227static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1228 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1229{
1230 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1231 int giga_ctrl, bmcr;
54405cde 1232 int rc = -EINVAL;
1da177e4 1233
716b50a3 1234 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1235
1236 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1237 int auto_nego;
1238
4da19633 1239 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1240 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1241 ADVERTISE_100HALF | ADVERTISE_100FULL);
1242
1243 if (adv & ADVERTISED_10baseT_Half)
1244 auto_nego |= ADVERTISE_10HALF;
1245 if (adv & ADVERTISED_10baseT_Full)
1246 auto_nego |= ADVERTISE_10FULL;
1247 if (adv & ADVERTISED_100baseT_Half)
1248 auto_nego |= ADVERTISE_100HALF;
1249 if (adv & ADVERTISED_100baseT_Full)
1250 auto_nego |= ADVERTISE_100FULL;
1251
3577aa1b 1252 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1253
4da19633 1254 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1255 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1256
3577aa1b 1257 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1258 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1259 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1260 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1261 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1262 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1263 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1264 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
5a5e4443
HW		 1265 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1266 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1267 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
54405cde
ON		 1268 if (adv & ADVERTISED_1000baseT_Half)
1269 giga_ctrl |= ADVERTISE_1000HALF;
1270 if (adv & ADVERTISED_1000baseT_Full)
1271 giga_ctrl |= ADVERTISE_1000FULL;
1272 } else if (adv & (ADVERTISED_1000baseT_Half |
1273 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1274 netif_info(tp, link, dev,
1275 "PHY does not support 1000Mbps\n");
54405cde 1276 goto out;
bcf0bf90 1277 }
1da177e4 1278
3577aa1b 1279 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1280
4da19633 1281 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1282 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1283 } else {
1284 giga_ctrl = 0;
1285
1286 if (speed == SPEED_10)
1287 bmcr = 0;
1288 else if (speed == SPEED_100)
1289 bmcr = BMCR_SPEED100;
1290 else
54405cde 1291 goto out;
3577aa1b 1292
1293 if (duplex == DUPLEX_FULL)
1294 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1295 }
1296
1da177e4
LT		 1297 tp->phy_1000_ctrl_reg = giga_ctrl;
1298
4da19633 1299 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1300
1301 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1302 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1303 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1304 rtl_writephy(tp, 0x17, 0x2138);
1305 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1306 } else {
4da19633 1307 rtl_writephy(tp, 0x17, 0x2108);
1308 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1309 }
1310 }
1311
54405cde
ON		 1312 rc = 0;
1313out:
1314 return rc;
1da177e4
LT		 1315}
1316
1317static int rtl8169_set_speed(struct net_device *dev,
54405cde 1318 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1319{
1320 struct rtl8169_private *tp = netdev_priv(dev);
1321 int ret;
1322
54405cde 1323 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1da177e4 1324
64e4bfb4 1325 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1326 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1327
1328 return ret;
1329}
1330
1331static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1332{
1333 struct rtl8169_private *tp = netdev_priv(dev);
1334 unsigned long flags;
1335 int ret;
1336
1337 spin_lock_irqsave(&tp->lock, flags);
54405cde
ON		 1338 ret = rtl8169_set_speed(dev,
1339 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1da177e4 1340 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1341
1da177e4
LT		 1342 return ret;
1343}
1344
350fb32a 1345static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1346{
2b7b4318 1347 if (dev->mtu > TD_MSS_MAX)
350fb32a 1348 features &= ~NETIF_F_ALL_TSO;
1da177e4 1349
350fb32a 1350 return features;
1da177e4
LT		 1351}
1352
350fb32a 1353static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1354{
1355 struct rtl8169_private *tp = netdev_priv(dev);
1356 void __iomem *ioaddr = tp->mmio_addr;
1357 unsigned long flags;
1358
1359 spin_lock_irqsave(&tp->lock, flags);
1360
350fb32a 1361 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1362 tp->cp_cmd |= RxChkSum;
1363 else
1364 tp->cp_cmd &= ~RxChkSum;
1365
350fb32a
MM		 1366 if (dev->features & NETIF_F_HW_VLAN_RX)
1367 tp->cp_cmd |= RxVlan;
1368 else
1369 tp->cp_cmd &= ~RxVlan;
1370
1da177e4
LT		 1371 RTL_W16(CPlusCmd, tp->cp_cmd);
1372 RTL_R16(CPlusCmd);
1373
1374 spin_unlock_irqrestore(&tp->lock, flags);
1375
1376 return 0;
1377}
1378
1da177e4
LT		 1379static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1380 struct sk_buff *skb)
1381{
eab6d18d 1382 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1383 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1384}
1385
7a8fc77b 1386static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1387{
1388 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1389
7a8fc77b
FR		 1390 if (opts2 & RxVlanTag)
1391 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1392
1da177e4 1393 desc->opts2 = 0;
1da177e4
LT		 1394}
1395
ccdffb9a 1396static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1397{
1398 struct rtl8169_private *tp = netdev_priv(dev);
1399 void __iomem *ioaddr = tp->mmio_addr;
1400 u32 status;
1401
1402 cmd->supported =
1403 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1404 cmd->port = PORT_FIBRE;
1405 cmd->transceiver = XCVR_INTERNAL;
1406
1407 status = RTL_R32(TBICSR);
1408 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1409 cmd->autoneg = !!(status & TBINwEnable);
1410
1411 cmd->speed = SPEED_1000;
1412 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1413
1414 return 0;
1da177e4
LT		 1415}
1416
ccdffb9a 1417static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1418{
1419 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1420
1421 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1422}
1423
1424static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1425{
1426 struct rtl8169_private *tp = netdev_priv(dev);
1427 unsigned long flags;
ccdffb9a 1428 int rc;
1da177e4
LT		 1429
1430 spin_lock_irqsave(&tp->lock, flags);
1431
ccdffb9a 1432 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1433
1434 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1435 return rc;
1da177e4
LT		 1436}
1437
1438static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1439 void *p)
1440{
5b0384f4
FR		 1441 struct rtl8169_private *tp = netdev_priv(dev);
1442 unsigned long flags;
1da177e4 1443
5b0384f4
FR		 1444 if (regs->len > R8169_REGS_SIZE)
1445 regs->len = R8169_REGS_SIZE;
1da177e4 1446
5b0384f4
FR		 1447 spin_lock_irqsave(&tp->lock, flags);
1448 memcpy_fromio(p, tp->mmio_addr, regs->len);
1449 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1450}
1451
b57b7e5a
SH		 1452static u32 rtl8169_get_msglevel(struct net_device *dev)
1453{
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455
1456 return tp->msg_enable;
1457}
1458
1459static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1460{
1461 struct rtl8169_private *tp = netdev_priv(dev);
1462
1463 tp->msg_enable = value;
1464}
1465
d4a3a0fc
SH		 1466static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1467 "tx_packets",
1468 "rx_packets",
1469 "tx_errors",
1470 "rx_errors",
1471 "rx_missed",
1472 "align_errors",
1473 "tx_single_collisions",
1474 "tx_multi_collisions",
1475 "unicast",
1476 "broadcast",
1477 "multicast",
1478 "tx_aborted",
1479 "tx_underrun",
1480};
1481
b9f2c044 1482static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1483{
b9f2c044
JG		 1484 switch (sset) {
1485 case ETH_SS_STATS:
1486 return ARRAY_SIZE(rtl8169_gstrings);
1487 default:
1488 return -EOPNOTSUPP;
1489 }
d4a3a0fc
SH		 1490}
1491
355423d0 1492static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1493{
1494 struct rtl8169_private *tp = netdev_priv(dev);
1495 void __iomem *ioaddr = tp->mmio_addr;
1496 struct rtl8169_counters *counters;
1497 dma_addr_t paddr;
1498 u32 cmd;
355423d0 1499 int wait = 1000;
48addcc9 1500 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1501
355423d0
IV		 1502 /*
1503 * Some chips are unable to dump tally counters when the receiver
1504 * is disabled.
1505 */
1506 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1507 return;
d4a3a0fc 1508
48addcc9 1509 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1510 if (!counters)
1511 return;
1512
1513 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1514 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1515 RTL_W32(CounterAddrLow, cmd);
1516 RTL_W32(CounterAddrLow, cmd | CounterDump);
1517
355423d0
IV		 1518 while (wait--) {
1519 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1520 /* copy updated counters */
1521 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1522 break;
355423d0
IV		 1523 }
1524 udelay(10);
d4a3a0fc
SH		 1525 }
1526
1527 RTL_W32(CounterAddrLow, 0);
1528 RTL_W32(CounterAddrHigh, 0);
1529
48addcc9 1530 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1531}
1532
355423d0
IV		 1533static void rtl8169_get_ethtool_stats(struct net_device *dev,
1534 struct ethtool_stats *stats, u64 *data)
1535{
1536 struct rtl8169_private *tp = netdev_priv(dev);
1537
1538 ASSERT_RTNL();
1539
1540 rtl8169_update_counters(dev);
1541
1542 data[0] = le64_to_cpu(tp->counters.tx_packets);
1543 data[1] = le64_to_cpu(tp->counters.rx_packets);
1544 data[2] = le64_to_cpu(tp->counters.tx_errors);
1545 data[3] = le32_to_cpu(tp->counters.rx_errors);
1546 data[4] = le16_to_cpu(tp->counters.rx_missed);
1547 data[5] = le16_to_cpu(tp->counters.align_errors);
1548 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1549 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1550 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1551 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1552 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1553 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1554 data[12] = le16_to_cpu(tp->counters.tx_underun);
1555}
1556
d4a3a0fc
SH		 1557static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1558{
1559 switch(stringset) {
1560 case ETH_SS_STATS:
1561 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1562 break;
1563 }
1564}
1565
7282d491 1566static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1567 .get_drvinfo = rtl8169_get_drvinfo,
1568 .get_regs_len = rtl8169_get_regs_len,
1569 .get_link = ethtool_op_get_link,
1570 .get_settings = rtl8169_get_settings,
1571 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1572 .get_msglevel = rtl8169_get_msglevel,
1573 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1574 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1575 .get_wol = rtl8169_get_wol,
1576 .set_wol = rtl8169_set_wol,
d4a3a0fc 1577 .get_strings = rtl8169_get_strings,
b9f2c044 1578 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1579 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1580};
1581
07d3f51f
FR		 1582static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1583 void __iomem *ioaddr)
1da177e4 1584{
0e485150
FR		 1585 /*
1586 * The driver currently handles the 8168Bf and the 8168Be identically
1587 * but they can be identified more specifically through the test below
1588 * if needed:
1589 *
1590 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1591 *
1592 * Same thing for the 8101Eb and the 8101Ec:
1593 *
1594 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1595 */
350f7596 1596 static const struct {
1da177e4 1597 u32 mask;
e3cf0cc0 1598 u32 val;
1da177e4
LT		 1599 int mac_version;
1600 } mac_info[] = {
01dc7fec 1601 /* 8168E family. */
1602 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1603 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1604 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1605
5b538df9 1606 /* 8168D family. */
daf9df6d 1607 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1608 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1609 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1610
e6de30d6 1611 /* 8168DP family. */
1612 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1613 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1614 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1615
ef808d50 1616 /* 8168C family. */
17c99297 1617 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1618 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1619 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1620 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1621 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1622 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1623 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1624 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1625 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1626
1627 /* 8168B family. */
1628 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1629 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1630 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1631 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1632
1633 /* 8101 family. */
36a0e6c2 1634 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1635 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1636 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1637 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1638 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1639 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1640 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1641 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1642 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1643 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1644 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1645 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1646 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1647 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1648 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1649 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1650 /* FIXME: where did these entries come from ? -- FR */
1651 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1652 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1653
1654 /* 8110 family. */
1655 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1656 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1657 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1658 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1659 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1660 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1661
f21b75e9
JD		 1662 /* Catch-all */
1663 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1664 }, *p = mac_info;
1665 u32 reg;
1666
e3cf0cc0
FR		 1667 reg = RTL_R32(TxConfig);
1668 while ((reg & p->mask) != p->val)
1da177e4
LT		 1669 p++;
1670 tp->mac_version = p->mac_version;
1671}
1672
1673static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1674{
bcf0bf90 1675 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1676}
1677
867763c1
FR		 1678struct phy_reg {
1679 u16 reg;
1680 u16 val;
1681};
1682
4da19633 1683static void rtl_writephy_batch(struct rtl8169_private *tp,
1684 const struct phy_reg *regs, int len)
867763c1
FR		 1685{
1686 while (len-- > 0) {
4da19633 1687 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1688 regs++;
1689 }
1690}
1691
bca03d5f 1692#define PHY_READ 0x00000000
1693#define PHY_DATA_OR 0x10000000
1694#define PHY_DATA_AND 0x20000000
1695#define PHY_BJMPN 0x30000000
1696#define PHY_READ_EFUSE 0x40000000
1697#define PHY_READ_MAC_BYTE 0x50000000
1698#define PHY_WRITE_MAC_BYTE 0x60000000
1699#define PHY_CLEAR_READCOUNT 0x70000000
1700#define PHY_WRITE 0x80000000
1701#define PHY_READCOUNT_EQ_SKIP 0x90000000
1702#define PHY_COMP_EQ_SKIPN 0xa0000000
1703#define PHY_COMP_NEQ_SKIPN 0xb0000000
1704#define PHY_WRITE_PREVIOUS 0xc0000000
1705#define PHY_SKIPN 0xd0000000
1706#define PHY_DELAY_MS 0xe0000000
1707#define PHY_WRITE_ERI_WORD 0xf0000000
1708
1709static void
1710rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1711{
bca03d5f 1712 __le32 *phytable = (__le32 *)fw->data;
1713 struct net_device *dev = tp->dev;
42b82dc1 1714 size_t index, fw_size = fw->size / sizeof(*phytable);
1715 u32 predata, count;
bca03d5f 1716
1717 if (fw->size % sizeof(*phytable)) {
1718 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1719 return;
1720 }
1721
42b82dc1 1722 for (index = 0; index < fw_size; index++) {
1723 u32 action = le32_to_cpu(phytable[index]);
1724 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1725
42b82dc1 1726 switch(action & 0xf0000000) {
1727 case PHY_READ:
1728 case PHY_DATA_OR:
1729 case PHY_DATA_AND:
1730 case PHY_READ_EFUSE:
1731 case PHY_CLEAR_READCOUNT:
1732 case PHY_WRITE:
1733 case PHY_WRITE_PREVIOUS:
1734 case PHY_DELAY_MS:
1735 break;
1736
1737 case PHY_BJMPN:
1738 if (regno > index) {
1739 netif_err(tp, probe, tp->dev,
1740 "Out of range of firmware\n");
1741 return;
1742 }
1743 break;
1744 case PHY_READCOUNT_EQ_SKIP:
1745 if (index + 2 >= fw_size) {
1746 netif_err(tp, probe, tp->dev,
1747 "Out of range of firmware\n");
1748 return;
1749 }
1750 break;
1751 case PHY_COMP_EQ_SKIPN:
1752 case PHY_COMP_NEQ_SKIPN:
1753 case PHY_SKIPN:
1754 if (index + 1 + regno >= fw_size) {
1755 netif_err(tp, probe, tp->dev,
1756 "Out of range of firmware\n");
1757 return;
1758 }
bca03d5f 1759 break;
1760
42b82dc1 1761 case PHY_READ_MAC_BYTE:
1762 case PHY_WRITE_MAC_BYTE:
1763 case PHY_WRITE_ERI_WORD:
1764 default:
1765 netif_err(tp, probe, tp->dev,
1766 "Invalid action 0x%08x\n", action);
bca03d5f 1767 return;
1768 }
1769 }
1770
42b82dc1 1771 predata = 0;
1772 count = 0;
1773
1774 for (index = 0; index < fw_size; ) {
1775 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1776 u32 data = action & 0x0000ffff;
42b82dc1 1777 u32 regno = (action & 0x0fff0000) >> 16;
1778
1779 if (!action)
1780 break;
bca03d5f 1781
1782 switch(action & 0xf0000000) {
42b82dc1 1783 case PHY_READ:
1784 predata = rtl_readphy(tp, regno);
1785 count++;
1786 index++;
1787 break;
1788 case PHY_DATA_OR:
1789 predata |= data;
1790 index++;
1791 break;
1792 case PHY_DATA_AND:
1793 predata &= data;
1794 index++;
1795 break;
1796 case PHY_BJMPN:
1797 index -= regno;
1798 break;
1799 case PHY_READ_EFUSE:
1800 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1801 index++;
1802 break;
1803 case PHY_CLEAR_READCOUNT:
1804 count = 0;
1805 index++;
1806 break;
bca03d5f 1807 case PHY_WRITE:
42b82dc1 1808 rtl_writephy(tp, regno, data);
1809 index++;
1810 break;
1811 case PHY_READCOUNT_EQ_SKIP:
1812 if (count == data)
1813 index += 2;
1814 else
1815 index += 1;
bca03d5f 1816 break;
42b82dc1 1817 case PHY_COMP_EQ_SKIPN:
1818 if (predata == data)
1819 index += regno;
1820 index++;
1821 break;
1822 case PHY_COMP_NEQ_SKIPN:
1823 if (predata != data)
1824 index += regno;
1825 index++;
1826 break;
1827 case PHY_WRITE_PREVIOUS:
1828 rtl_writephy(tp, regno, predata);
1829 index++;
1830 break;
1831 case PHY_SKIPN:
1832 index += regno + 1;
1833 break;
1834 case PHY_DELAY_MS:
1835 mdelay(data);
1836 index++;
1837 break;
1838
1839 case PHY_READ_MAC_BYTE:
1840 case PHY_WRITE_MAC_BYTE:
1841 case PHY_WRITE_ERI_WORD:
bca03d5f 1842 default:
1843 BUG();
1844 }
1845 }
1846}
1847
f1e02ed1 1848static void rtl_release_firmware(struct rtl8169_private *tp)
1849{
1850 release_firmware(tp->fw);
1851 tp->fw = NULL;
1852}
1853
1854static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1855{
1856 const struct firmware **fw = &tp->fw;
1857 int rc = !*fw;
1858
1859 if (rc) {
1860 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1861 if (rc < 0)
1862 goto out;
1863 }
1864
1865 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1866 rtl_phy_write_fw(tp, *fw);
1867out:
1868 return rc;
1869}
1870
4da19633 1871static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1872{
350f7596 1873 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1874 { 0x1f, 0x0001 },
1875 { 0x06, 0x006e },
1876 { 0x08, 0x0708 },
1877 { 0x15, 0x4000 },
1878 { 0x18, 0x65c7 },
1da177e4 1879
0b9b571d 1880 { 0x1f, 0x0001 },
1881 { 0x03, 0x00a1 },
1882 { 0x02, 0x0008 },
1883 { 0x01, 0x0120 },
1884 { 0x00, 0x1000 },
1885 { 0x04, 0x0800 },
1886 { 0x04, 0x0000 },
1da177e4 1887
0b9b571d 1888 { 0x03, 0xff41 },
1889 { 0x02, 0xdf60 },
1890 { 0x01, 0x0140 },
1891 { 0x00, 0x0077 },
1892 { 0x04, 0x7800 },
1893 { 0x04, 0x7000 },
1894
1895 { 0x03, 0x802f },
1896 { 0x02, 0x4f02 },
1897 { 0x01, 0x0409 },
1898 { 0x00, 0xf0f9 },
1899 { 0x04, 0x9800 },
1900 { 0x04, 0x9000 },
1901
1902 { 0x03, 0xdf01 },
1903 { 0x02, 0xdf20 },
1904 { 0x01, 0xff95 },
1905 { 0x00, 0xba00 },
1906 { 0x04, 0xa800 },
1907 { 0x04, 0xa000 },
1908
1909 { 0x03, 0xff41 },
1910 { 0x02, 0xdf20 },
1911 { 0x01, 0x0140 },
1912 { 0x00, 0x00bb },
1913 { 0x04, 0xb800 },
1914 { 0x04, 0xb000 },
1915
1916 { 0x03, 0xdf41 },
1917 { 0x02, 0xdc60 },
1918 { 0x01, 0x6340 },
1919 { 0x00, 0x007d },
1920 { 0x04, 0xd800 },
1921 { 0x04, 0xd000 },
1922
1923 { 0x03, 0xdf01 },
1924 { 0x02, 0xdf20 },
1925 { 0x01, 0x100a },
1926 { 0x00, 0xa0ff },
1927 { 0x04, 0xf800 },
1928 { 0x04, 0xf000 },
1929
1930 { 0x1f, 0x0000 },
1931 { 0x0b, 0x0000 },
1932 { 0x00, 0x9200 }
1933 };
1da177e4 1934
4da19633 1935 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1936}
1937
4da19633 1938static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1939{
350f7596 1940 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1941 { 0x1f, 0x0002 },
1942 { 0x01, 0x90d0 },
1943 { 0x1f, 0x0000 }
1944 };
1945
4da19633 1946 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1947}
1948
4da19633 1949static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1950{
1951 struct pci_dev *pdev = tp->pci_dev;
1952 u16 vendor_id, device_id;
1953
1954 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1955 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1956
1957 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1958 return;
1959
4da19633 1960 rtl_writephy(tp, 0x1f, 0x0001);
1961 rtl_writephy(tp, 0x10, 0xf01b);
1962 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1963}
1964
4da19633 1965static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1966{
350f7596 1967 static const struct phy_reg phy_reg_init[] = {
2e955856 1968 { 0x1f, 0x0001 },
1969 { 0x04, 0x0000 },
1970 { 0x03, 0x00a1 },
1971 { 0x02, 0x0008 },
1972 { 0x01, 0x0120 },
1973 { 0x00, 0x1000 },
1974 { 0x04, 0x0800 },
1975 { 0x04, 0x9000 },
1976 { 0x03, 0x802f },
1977 { 0x02, 0x4f02 },
1978 { 0x01, 0x0409 },
1979 { 0x00, 0xf099 },
1980 { 0x04, 0x9800 },
1981 { 0x04, 0xa000 },
1982 { 0x03, 0xdf01 },
1983 { 0x02, 0xdf20 },
1984 { 0x01, 0xff95 },
1985 { 0x00, 0xba00 },
1986 { 0x04, 0xa800 },
1987 { 0x04, 0xf000 },
1988 { 0x03, 0xdf01 },
1989 { 0x02, 0xdf20 },
1990 { 0x01, 0x101a },
1991 { 0x00, 0xa0ff },
1992 { 0x04, 0xf800 },
1993 { 0x04, 0x0000 },
1994 { 0x1f, 0x0000 },
1995
1996 { 0x1f, 0x0001 },
1997 { 0x10, 0xf41b },
1998 { 0x14, 0xfb54 },
1999 { 0x18, 0xf5c7 },
2000 { 0x1f, 0x0000 },
2001
2002 { 0x1f, 0x0001 },
2003 { 0x17, 0x0cc0 },
2004 { 0x1f, 0x0000 }
2005 };
2006
4da19633 2007 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2008
4da19633 2009 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2010}
2011
4da19633 2012static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2013{
350f7596 2014 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2015 { 0x1f, 0x0001 },
2016 { 0x04, 0x0000 },
2017 { 0x03, 0x00a1 },
2018 { 0x02, 0x0008 },
2019 { 0x01, 0x0120 },
2020 { 0x00, 0x1000 },
2021 { 0x04, 0x0800 },
2022 { 0x04, 0x9000 },
2023 { 0x03, 0x802f },
2024 { 0x02, 0x4f02 },
2025 { 0x01, 0x0409 },
2026 { 0x00, 0xf099 },
2027 { 0x04, 0x9800 },
2028 { 0x04, 0xa000 },
2029 { 0x03, 0xdf01 },
2030 { 0x02, 0xdf20 },
2031 { 0x01, 0xff95 },
2032 { 0x00, 0xba00 },
2033 { 0x04, 0xa800 },
2034 { 0x04, 0xf000 },
2035 { 0x03, 0xdf01 },
2036 { 0x02, 0xdf20 },
2037 { 0x01, 0x101a },
2038 { 0x00, 0xa0ff },
2039 { 0x04, 0xf800 },
2040 { 0x04, 0x0000 },
2041 { 0x1f, 0x0000 },
2042
2043 { 0x1f, 0x0001 },
2044 { 0x0b, 0x8480 },
2045 { 0x1f, 0x0000 },
2046
2047 { 0x1f, 0x0001 },
2048 { 0x18, 0x67c7 },
2049 { 0x04, 0x2000 },
2050 { 0x03, 0x002f },
2051 { 0x02, 0x4360 },
2052 { 0x01, 0x0109 },
2053 { 0x00, 0x3022 },
2054 { 0x04, 0x2800 },
2055 { 0x1f, 0x0000 },
2056
2057 { 0x1f, 0x0001 },
2058 { 0x17, 0x0cc0 },
2059 { 0x1f, 0x0000 }
2060 };
2061
4da19633 2062 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2063}
2064
4da19633 2065static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2066{
350f7596 2067 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2068 { 0x10, 0xf41b },
2069 { 0x1f, 0x0000 }
2070 };
2071
4da19633 2072 rtl_writephy(tp, 0x1f, 0x0001);
2073 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2074
4da19633 2075 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2076}
2077
4da19633 2078static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2079{
350f7596 2080 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2081 { 0x1f, 0x0001 },
2082 { 0x10, 0xf41b },
2083 { 0x1f, 0x0000 }
2084 };
2085
4da19633 2086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2087}
2088
4da19633 2089static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2090{
350f7596 2091 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2092 { 0x1f, 0x0000 },
2093 { 0x1d, 0x0f00 },
2094 { 0x1f, 0x0002 },
2095 { 0x0c, 0x1ec8 },
2096 { 0x1f, 0x0000 }
2097 };
2098
4da19633 2099 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2100}
2101
4da19633 2102static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2103{
350f7596 2104 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2105 { 0x1f, 0x0001 },
2106 { 0x1d, 0x3d98 },
2107 { 0x1f, 0x0000 }
2108 };
2109
4da19633 2110 rtl_writephy(tp, 0x1f, 0x0000);
2111 rtl_patchphy(tp, 0x14, 1 << 5);
2112 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2113
4da19633 2114 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2115}
2116
4da19633 2117static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2118{
350f7596 2119 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2120 { 0x1f, 0x0001 },
2121 { 0x12, 0x2300 },
867763c1
FR		 2122 { 0x1f, 0x0002 },
2123 { 0x00, 0x88d4 },
2124 { 0x01, 0x82b1 },
2125 { 0x03, 0x7002 },
2126 { 0x08, 0x9e30 },
2127 { 0x09, 0x01f0 },
2128 { 0x0a, 0x5500 },
2129 { 0x0c, 0x00c8 },
2130 { 0x1f, 0x0003 },
2131 { 0x12, 0xc096 },
2132 { 0x16, 0x000a },
f50d4275
FR		 2133 { 0x1f, 0x0000 },
2134 { 0x1f, 0x0000 },
2135 { 0x09, 0x2000 },
2136 { 0x09, 0x0000 }
867763c1
FR		 2137 };
2138
4da19633 2139 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2140
4da19633 2141 rtl_patchphy(tp, 0x14, 1 << 5);
2142 rtl_patchphy(tp, 0x0d, 1 << 5);
2143 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2144}
2145
4da19633 2146static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2147{
350f7596 2148 static const struct phy_reg phy_reg_init[] = {
f50d4275 2149 { 0x1f, 0x0001 },
7da97ec9 2150 { 0x12, 0x2300 },
f50d4275
FR		 2151 { 0x03, 0x802f },
2152 { 0x02, 0x4f02 },
2153 { 0x01, 0x0409 },
2154 { 0x00, 0xf099 },
2155 { 0x04, 0x9800 },
2156 { 0x04, 0x9000 },
2157 { 0x1d, 0x3d98 },
7da97ec9
FR		 2158 { 0x1f, 0x0002 },
2159 { 0x0c, 0x7eb8 },
f50d4275
FR		 2160 { 0x06, 0x0761 },
2161 { 0x1f, 0x0003 },
2162 { 0x16, 0x0f0a },
7da97ec9
FR		 2163 { 0x1f, 0x0000 }
2164 };
2165
4da19633 2166 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2167
4da19633 2168 rtl_patchphy(tp, 0x16, 1 << 0);
2169 rtl_patchphy(tp, 0x14, 1 << 5);
2170 rtl_patchphy(tp, 0x0d, 1 << 5);
2171 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2172}
2173
4da19633 2174static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2175{
350f7596 2176 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2177 { 0x1f, 0x0001 },
2178 { 0x12, 0x2300 },
2179 { 0x1d, 0x3d98 },
2180 { 0x1f, 0x0002 },
2181 { 0x0c, 0x7eb8 },
2182 { 0x06, 0x5461 },
2183 { 0x1f, 0x0003 },
2184 { 0x16, 0x0f0a },
2185 { 0x1f, 0x0000 }
2186 };
2187
4da19633 2188 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2189
4da19633 2190 rtl_patchphy(tp, 0x16, 1 << 0);
2191 rtl_patchphy(tp, 0x14, 1 << 5);
2192 rtl_patchphy(tp, 0x0d, 1 << 5);
2193 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2194}
2195
4da19633 2196static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2197{
4da19633 2198 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2199}
2200
bca03d5f 2201static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2202{
350f7596 2203 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2204 /* Channel Estimation */
5b538df9 2205 { 0x1f, 0x0001 },
daf9df6d 2206 { 0x06, 0x4064 },
2207 { 0x07, 0x2863 },
2208 { 0x08, 0x059c },
2209 { 0x09, 0x26b4 },
2210 { 0x0a, 0x6a19 },
2211 { 0x0b, 0xdcc8 },
2212 { 0x10, 0xf06d },
2213 { 0x14, 0x7f68 },
2214 { 0x18, 0x7fd9 },
2215 { 0x1c, 0xf0ff },
2216 { 0x1d, 0x3d9c },
5b538df9 2217 { 0x1f, 0x0003 },
daf9df6d 2218 { 0x12, 0xf49f },
2219 { 0x13, 0x070b },
2220 { 0x1a, 0x05ad },
bca03d5f 2221 { 0x14, 0x94c0 },
2222
2223 /*
2224 * Tx Error Issue
2225 * enhance line driver power
2226 */
5b538df9 2227 { 0x1f, 0x0002 },
daf9df6d 2228 { 0x06, 0x5561 },
2229 { 0x1f, 0x0005 },
2230 { 0x05, 0x8332 },
bca03d5f 2231 { 0x06, 0x5561 },
2232
2233 /*
2234 * Can not link to 1Gbps with bad cable
2235 * Decrease SNR threshold form 21.07dB to 19.04dB
2236 */
2237 { 0x1f, 0x0001 },
2238 { 0x17, 0x0cc0 },
daf9df6d 2239
5b538df9 2240 { 0x1f, 0x0000 },
bca03d5f 2241 { 0x0d, 0xf880 }
daf9df6d 2242 };
bca03d5f 2243 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2244
4da19633 2245 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2246
bca03d5f 2247 /*
2248 * Rx Error Issue
2249 * Fine Tune Switching regulator parameter
2250 */
4da19633 2251 rtl_writephy(tp, 0x1f, 0x0002);
2252 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2253 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2254
daf9df6d 2255 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2256 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2257 { 0x1f, 0x0002 },
2258 { 0x05, 0x669a },
2259 { 0x1f, 0x0005 },
2260 { 0x05, 0x8330 },
2261 { 0x06, 0x669a },
2262 { 0x1f, 0x0002 }
2263 };
2264 int val;
2265
4da19633 2266 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2267
4da19633 2268 val = rtl_readphy(tp, 0x0d);
daf9df6d 2269
2270 if ((val & 0x00ff) != 0x006c) {
350f7596 2271 static const u32 set[] = {
daf9df6d 2272 0x0065, 0x0066, 0x0067, 0x0068,
2273 0x0069, 0x006a, 0x006b, 0x006c
2274 };
2275 int i;
2276
4da19633 2277 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2278
2279 val &= 0xff00;
2280 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2281 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2282 }
2283 } else {
350f7596 2284 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2285 { 0x1f, 0x0002 },
2286 { 0x05, 0x6662 },
2287 { 0x1f, 0x0005 },
2288 { 0x05, 0x8330 },
2289 { 0x06, 0x6662 }
2290 };
2291
4da19633 2292 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2293 }
2294
bca03d5f 2295 /* RSET couple improve */
4da19633 2296 rtl_writephy(tp, 0x1f, 0x0002);
2297 rtl_patchphy(tp, 0x0d, 0x0300);
2298 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2299
bca03d5f 2300 /* Fine tune PLL performance */
4da19633 2301 rtl_writephy(tp, 0x1f, 0x0002);
2302 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2303 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2304
4da19633 2305 rtl_writephy(tp, 0x1f, 0x0005);
2306 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2307 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2308 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
bca03d5f 2309 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2310 }
2311
4da19633 2312 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2313}
2314
bca03d5f 2315static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2316{
350f7596 2317 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2318 /* Channel Estimation */
daf9df6d 2319 { 0x1f, 0x0001 },
2320 { 0x06, 0x4064 },
2321 { 0x07, 0x2863 },
2322 { 0x08, 0x059c },
2323 { 0x09, 0x26b4 },
2324 { 0x0a, 0x6a19 },
2325 { 0x0b, 0xdcc8 },
2326 { 0x10, 0xf06d },
2327 { 0x14, 0x7f68 },
2328 { 0x18, 0x7fd9 },
2329 { 0x1c, 0xf0ff },
2330 { 0x1d, 0x3d9c },
2331 { 0x1f, 0x0003 },
2332 { 0x12, 0xf49f },
2333 { 0x13, 0x070b },
2334 { 0x1a, 0x05ad },
2335 { 0x14, 0x94c0 },
2336
bca03d5f 2337 /*
2338 * Tx Error Issue
2339 * enhance line driver power
2340 */
daf9df6d 2341 { 0x1f, 0x0002 },
2342 { 0x06, 0x5561 },
2343 { 0x1f, 0x0005 },
2344 { 0x05, 0x8332 },
bca03d5f 2345 { 0x06, 0x5561 },
2346
2347 /*
2348 * Can not link to 1Gbps with bad cable
2349 * Decrease SNR threshold form 21.07dB to 19.04dB
2350 */
2351 { 0x1f, 0x0001 },
2352 { 0x17, 0x0cc0 },
daf9df6d 2353
2354 { 0x1f, 0x0000 },
bca03d5f 2355 { 0x0d, 0xf880 }
5b538df9 2356 };
bca03d5f 2357 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2358
4da19633 2359 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2360
daf9df6d 2361 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2362 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2363 { 0x1f, 0x0002 },
2364 { 0x05, 0x669a },
5b538df9 2365 { 0x1f, 0x0005 },
daf9df6d 2366 { 0x05, 0x8330 },
2367 { 0x06, 0x669a },
2368
2369 { 0x1f, 0x0002 }
2370 };
2371 int val;
2372
4da19633 2373 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2374
4da19633 2375 val = rtl_readphy(tp, 0x0d);
daf9df6d 2376 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2377 static const u32 set[] = {
daf9df6d 2378 0x0065, 0x0066, 0x0067, 0x0068,
2379 0x0069, 0x006a, 0x006b, 0x006c
2380 };
2381 int i;
2382
4da19633 2383 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2384
2385 val &= 0xff00;
2386 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2387 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2388 }
2389 } else {
350f7596 2390 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2391 { 0x1f, 0x0002 },
2392 { 0x05, 0x2642 },
5b538df9 2393 { 0x1f, 0x0005 },
daf9df6d 2394 { 0x05, 0x8330 },
2395 { 0x06, 0x2642 }
5b538df9
FR		 2396 };
2397
4da19633 2398 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2399 }
2400
bca03d5f 2401 /* Fine tune PLL performance */
4da19633 2402 rtl_writephy(tp, 0x1f, 0x0002);
2403 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2404 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2405
bca03d5f 2406 /* Switching regulator Slew rate */
4da19633 2407 rtl_writephy(tp, 0x1f, 0x0002);
2408 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2409
4da19633 2410 rtl_writephy(tp, 0x1f, 0x0005);
2411 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2412 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2413 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
bca03d5f 2414 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2415 }
2416
4da19633 2417 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2418}
2419
4da19633 2420static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2421{
350f7596 2422 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2423 { 0x1f, 0x0002 },
2424 { 0x10, 0x0008 },
2425 { 0x0d, 0x006c },
2426
2427 { 0x1f, 0x0000 },
2428 { 0x0d, 0xf880 },
2429
2430 { 0x1f, 0x0001 },
2431 { 0x17, 0x0cc0 },
2432
2433 { 0x1f, 0x0001 },
2434 { 0x0b, 0xa4d8 },
2435 { 0x09, 0x281c },
2436 { 0x07, 0x2883 },
2437 { 0x0a, 0x6b35 },
2438 { 0x1d, 0x3da4 },
2439 { 0x1c, 0xeffd },
2440 { 0x14, 0x7f52 },
2441 { 0x18, 0x7fc6 },
2442 { 0x08, 0x0601 },
2443 { 0x06, 0x4063 },
2444 { 0x10, 0xf074 },
2445 { 0x1f, 0x0003 },
2446 { 0x13, 0x0789 },
2447 { 0x12, 0xf4bd },
2448 { 0x1a, 0x04fd },
2449 { 0x14, 0x84b0 },
2450 { 0x1f, 0x0000 },
2451 { 0x00, 0x9200 },
2452
2453 { 0x1f, 0x0005 },
2454 { 0x01, 0x0340 },
2455 { 0x1f, 0x0001 },
2456 { 0x04, 0x4000 },
2457 { 0x03, 0x1d21 },
2458 { 0x02, 0x0c32 },
2459 { 0x01, 0x0200 },
2460 { 0x00, 0x5554 },
2461 { 0x04, 0x4800 },
2462 { 0x04, 0x4000 },
2463 { 0x04, 0xf000 },
2464 { 0x03, 0xdf01 },
2465 { 0x02, 0xdf20 },
2466 { 0x01, 0x101a },
2467 { 0x00, 0xa0ff },
2468 { 0x04, 0xf800 },
2469 { 0x04, 0xf000 },
2470 { 0x1f, 0x0000 },
2471
2472 { 0x1f, 0x0007 },
2473 { 0x1e, 0x0023 },
2474 { 0x16, 0x0000 },
2475 { 0x1f, 0x0000 }
2476 };
2477
4da19633 2478 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2479}
2480
e6de30d6 2481static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2482{
2483 static const struct phy_reg phy_reg_init[] = {
2484 { 0x1f, 0x0001 },
2485 { 0x17, 0x0cc0 },
2486
2487 { 0x1f, 0x0007 },
2488 { 0x1e, 0x002d },
2489 { 0x18, 0x0040 },
2490 { 0x1f, 0x0000 }
2491 };
2492
2493 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2494 rtl_patchphy(tp, 0x0d, 1 << 5);
2495}
2496
01dc7fec 2497static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2498{
2499 static const struct phy_reg phy_reg_init[] = {
2500 /* Enable Delay cap */
2501 { 0x1f, 0x0005 },
2502 { 0x05, 0x8b80 },
2503 { 0x06, 0xc896 },
2504 { 0x1f, 0x0000 },
2505
2506 /* Channel estimation fine tune */
2507 { 0x1f, 0x0001 },
2508 { 0x0b, 0x6c20 },
2509 { 0x07, 0x2872 },
2510 { 0x1c, 0xefff },
2511 { 0x1f, 0x0003 },
2512 { 0x14, 0x6420 },
2513 { 0x1f, 0x0000 },
2514
2515 /* Update PFM & 10M TX idle timer */
2516 { 0x1f, 0x0007 },
2517 { 0x1e, 0x002f },
2518 { 0x15, 0x1919 },
2519 { 0x1f, 0x0000 },
2520
2521 { 0x1f, 0x0007 },
2522 { 0x1e, 0x00ac },
2523 { 0x18, 0x0006 },
2524 { 0x1f, 0x0000 }
2525 };
2526
2527 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2528
2529 /* DCO enable for 10M IDLE Power */
2530 rtl_writephy(tp, 0x1f, 0x0007);
2531 rtl_writephy(tp, 0x1e, 0x0023);
2532 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2533 rtl_writephy(tp, 0x1f, 0x0000);
2534
2535 /* For impedance matching */
2536 rtl_writephy(tp, 0x1f, 0x0002);
2537 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2538 rtl_writephy(tp, 0x1F, 0x0000);
2539
2540 /* PHY auto speed down */
2541 rtl_writephy(tp, 0x1f, 0x0007);
2542 rtl_writephy(tp, 0x1e, 0x002d);
2543 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2544 rtl_writephy(tp, 0x1f, 0x0000);
2545 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2546
2547 rtl_writephy(tp, 0x1f, 0x0005);
2548 rtl_writephy(tp, 0x05, 0x8b86);
2549 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2550 rtl_writephy(tp, 0x1f, 0x0000);
2551
2552 rtl_writephy(tp, 0x1f, 0x0005);
2553 rtl_writephy(tp, 0x05, 0x8b85);
2554 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2555 rtl_writephy(tp, 0x1f, 0x0007);
2556 rtl_writephy(tp, 0x1e, 0x0020);
2557 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2558 rtl_writephy(tp, 0x1f, 0x0006);
2559 rtl_writephy(tp, 0x00, 0x5a00);
2560 rtl_writephy(tp, 0x1f, 0x0000);
2561 rtl_writephy(tp, 0x0d, 0x0007);
2562 rtl_writephy(tp, 0x0e, 0x003c);
2563 rtl_writephy(tp, 0x0d, 0x4007);
2564 rtl_writephy(tp, 0x0e, 0x0000);
2565 rtl_writephy(tp, 0x0d, 0x0000);
2566}
2567
2568static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2569{
2570 if (rtl_apply_firmware(tp, FIRMWARE_8168E_1) < 0)
2571 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2572
2573 rtl8168e_hw_phy_config(tp);
2574}
2575
2576static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2577{
2578 if (rtl_apply_firmware(tp, FIRMWARE_8168E_2) < 0)
2579 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2580
2581 rtl8168e_hw_phy_config(tp);
2582}
2583
4da19633 2584static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2585{
350f7596 2586 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2587 { 0x1f, 0x0003 },
2588 { 0x08, 0x441d },
2589 { 0x01, 0x9100 },
2590 { 0x1f, 0x0000 }
2591 };
2592
4da19633 2593 rtl_writephy(tp, 0x1f, 0x0000);
2594 rtl_patchphy(tp, 0x11, 1 << 12);
2595 rtl_patchphy(tp, 0x19, 1 << 13);
2596 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2597
4da19633 2598 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2599}
2600
5a5e4443
HW		 2601static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2602{
2603 static const struct phy_reg phy_reg_init[] = {
2604 { 0x1f, 0x0005 },
2605 { 0x1a, 0x0000 },
2606 { 0x1f, 0x0000 },
2607
2608 { 0x1f, 0x0004 },
2609 { 0x1c, 0x0000 },
2610 { 0x1f, 0x0000 },
2611
2612 { 0x1f, 0x0001 },
2613 { 0x15, 0x7701 },
2614 { 0x1f, 0x0000 }
2615 };
2616
2617 /* Disable ALDPS before ram code */
2618 rtl_writephy(tp, 0x1f, 0x0000);
2619 rtl_writephy(tp, 0x18, 0x0310);
2620 msleep(100);
2621
2622 if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2623 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2624
2625 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2626}
2627
5615d9f1
FR		 2628static void rtl_hw_phy_config(struct net_device *dev)
2629{
2630 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2631
2632 rtl8169_print_mac_version(tp);
2633
2634 switch (tp->mac_version) {
2635 case RTL_GIGA_MAC_VER_01:
2636 break;
2637 case RTL_GIGA_MAC_VER_02:
2638 case RTL_GIGA_MAC_VER_03:
4da19633 2639 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2640 break;
2641 case RTL_GIGA_MAC_VER_04:
4da19633 2642 rtl8169sb_hw_phy_config(tp);
5615d9f1 2643 break;
2e955856 2644 case RTL_GIGA_MAC_VER_05:
4da19633 2645 rtl8169scd_hw_phy_config(tp);
2e955856 2646 break;
8c7006aa 2647 case RTL_GIGA_MAC_VER_06:
4da19633 2648 rtl8169sce_hw_phy_config(tp);
8c7006aa 2649 break;
2857ffb7
FR		 2650 case RTL_GIGA_MAC_VER_07:
2651 case RTL_GIGA_MAC_VER_08:
2652 case RTL_GIGA_MAC_VER_09:
4da19633 2653 rtl8102e_hw_phy_config(tp);
2857ffb7 2654 break;
236b8082 2655 case RTL_GIGA_MAC_VER_11:
4da19633 2656 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2657 break;
2658 case RTL_GIGA_MAC_VER_12:
4da19633 2659 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2660 break;
2661 case RTL_GIGA_MAC_VER_17:
4da19633 2662 rtl8168bef_hw_phy_config(tp);
236b8082 2663 break;
867763c1 2664 case RTL_GIGA_MAC_VER_18:
4da19633 2665 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2666 break;
2667 case RTL_GIGA_MAC_VER_19:
4da19633 2668 rtl8168c_1_hw_phy_config(tp);
867763c1 2669 break;
7da97ec9 2670 case RTL_GIGA_MAC_VER_20:
4da19633 2671 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2672 break;
197ff761 2673 case RTL_GIGA_MAC_VER_21:
4da19633 2674 rtl8168c_3_hw_phy_config(tp);
197ff761 2675 break;
6fb07058 2676 case RTL_GIGA_MAC_VER_22:
4da19633 2677 rtl8168c_4_hw_phy_config(tp);
6fb07058 2678 break;
ef3386f0 2679 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2680 case RTL_GIGA_MAC_VER_24:
4da19633 2681 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2682 break;
5b538df9 2683 case RTL_GIGA_MAC_VER_25:
bca03d5f 2684 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2685 break;
2686 case RTL_GIGA_MAC_VER_26:
bca03d5f 2687 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2688 break;
2689 case RTL_GIGA_MAC_VER_27:
4da19633 2690 rtl8168d_3_hw_phy_config(tp);
5b538df9 2691 break;
e6de30d6 2692 case RTL_GIGA_MAC_VER_28:
2693 rtl8168d_4_hw_phy_config(tp);
2694 break;
5a5e4443
HW		 2695 case RTL_GIGA_MAC_VER_29:
2696 case RTL_GIGA_MAC_VER_30:
2697 rtl8105e_hw_phy_config(tp);
2698 break;
01dc7fec 2699 case RTL_GIGA_MAC_VER_32:
2700 rtl8168e_1_hw_phy_config(tp);
2701 break;
2702 case RTL_GIGA_MAC_VER_33:
2703 rtl8168e_2_hw_phy_config(tp);
2704 break;
ef3386f0 2705
5615d9f1
FR		 2706 default:
2707 break;
2708 }
2709}
2710
1da177e4
LT		 2711static void rtl8169_phy_timer(unsigned long __opaque)
2712{
2713 struct net_device *dev = (struct net_device *)__opaque;
2714 struct rtl8169_private *tp = netdev_priv(dev);
2715 struct timer_list *timer = &tp->timer;
2716 void __iomem *ioaddr = tp->mmio_addr;
2717 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2718
bcf0bf90 2719 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2720
64e4bfb4 2721 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2722 return;
2723
2724 spin_lock_irq(&tp->lock);
2725
4da19633 2726 if (tp->phy_reset_pending(tp)) {
5b0384f4 2727 /*
1da177e4
LT		 2728 * A busy loop could burn quite a few cycles on nowadays CPU.
2729 * Let's delay the execution of the timer for a few ticks.
2730 */
2731 timeout = HZ/10;
2732 goto out_mod_timer;
2733 }
2734
2735 if (tp->link_ok(ioaddr))
2736 goto out_unlock;
2737
bf82c189 2738 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2739
4da19633 2740 tp->phy_reset_enable(tp);
1da177e4
LT		 2741
2742out_mod_timer:
2743 mod_timer(timer, jiffies + timeout);
2744out_unlock:
2745 spin_unlock_irq(&tp->lock);
2746}
2747
2748static inline void rtl8169_delete_timer(struct net_device *dev)
2749{
2750 struct rtl8169_private *tp = netdev_priv(dev);
2751 struct timer_list *timer = &tp->timer;
2752
e179bb7b 2753 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2754 return;
2755
2756 del_timer_sync(timer);
2757}
2758
2759static inline void rtl8169_request_timer(struct net_device *dev)
2760{
2761 struct rtl8169_private *tp = netdev_priv(dev);
2762 struct timer_list *timer = &tp->timer;
2763
e179bb7b 2764 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2765 return;
2766
2efa53f3 2767 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2768}
2769
2770#ifdef CONFIG_NET_POLL_CONTROLLER
2771/*
2772 * Polling 'interrupt' - used by things like netconsole to send skbs
2773 * without having to re-enable interrupts. It's not called while
2774 * the interrupt routine is executing.
2775 */
2776static void rtl8169_netpoll(struct net_device *dev)
2777{
2778 struct rtl8169_private *tp = netdev_priv(dev);
2779 struct pci_dev *pdev = tp->pci_dev;
2780
2781 disable_irq(pdev->irq);
7d12e780 2782 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2783 enable_irq(pdev->irq);
2784}
2785#endif
2786
2787static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2788 void __iomem *ioaddr)
2789{
2790 iounmap(ioaddr);
2791 pci_release_regions(pdev);
87aeec76 2792 pci_clear_mwi(pdev);
1da177e4
LT		 2793 pci_disable_device(pdev);
2794 free_netdev(dev);
2795}
2796
bf793295
FR		 2797static void rtl8169_phy_reset(struct net_device *dev,
2798 struct rtl8169_private *tp)
2799{
07d3f51f 2800 unsigned int i;
bf793295 2801
4da19633 2802 tp->phy_reset_enable(tp);
bf793295 2803 for (i = 0; i < 100; i++) {
4da19633 2804 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2805 return;
2806 msleep(1);
2807 }
bf82c189 2808 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2809}
2810
4ff96fa6
FR		 2811static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2812{
2813 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2814
5615d9f1 2815 rtl_hw_phy_config(dev);
4ff96fa6 2816
77332894
MS		 2817 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2818 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2819 RTL_W8(0x82, 0x01);
2820 }
4ff96fa6 2821
6dccd16b
FR		 2822 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2823
2824 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2825 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2826
bcf0bf90 2827 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2828 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2829 RTL_W8(0x82, 0x01);
2830 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2831 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2832 }
2833
bf793295
FR		 2834 rtl8169_phy_reset(dev, tp);
2835
54405cde
ON		 2836 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2837 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2838 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
db552b33 2839 (tp->mii.supports_gmii ?
54405cde 2840 ADVERTISED_1000baseT_Half |
db552b33 2841 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2842
bf82c189
JP		 2843 if (RTL_R8(PHYstatus) & TBI_Enable)
2844 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2845}
2846
773d2021
FR		 2847static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2848{
2849 void __iomem *ioaddr = tp->mmio_addr;
2850 u32 high;
2851 u32 low;
2852
2853 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2854 high = addr[4] | (addr[5] << 8);
2855
2856 spin_lock_irq(&tp->lock);
2857
2858 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2859
773d2021 2860 RTL_W32(MAC4, high);
908ba2bf 2861 RTL_R32(MAC4);
2862
78f1cd02 2863 RTL_W32(MAC0, low);
908ba2bf 2864 RTL_R32(MAC0);
2865
773d2021
FR		 2866 RTL_W8(Cfg9346, Cfg9346_Lock);
2867
2868 spin_unlock_irq(&tp->lock);
2869}
2870
2871static int rtl_set_mac_address(struct net_device *dev, void *p)
2872{
2873 struct rtl8169_private *tp = netdev_priv(dev);
2874 struct sockaddr *addr = p;
2875
2876 if (!is_valid_ether_addr(addr->sa_data))
2877 return -EADDRNOTAVAIL;
2878
2879 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2880
2881 rtl_rar_set(tp, dev->dev_addr);
2882
2883 return 0;
2884}
2885
5f787a1a
FR		 2886static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2887{
2888 struct rtl8169_private *tp = netdev_priv(dev);
2889 struct mii_ioctl_data *data = if_mii(ifr);
2890
8b4ab28d
FR		 2891 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2892}
5f787a1a 2893
8b4ab28d
FR		 2894static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2895{
5f787a1a
FR		 2896 switch (cmd) {
2897 case SIOCGMIIPHY:
2898 data->phy_id = 32; /* Internal PHY */
2899 return 0;
2900
2901 case SIOCGMIIREG:
4da19633 2902 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2903 return 0;
2904
2905 case SIOCSMIIREG:
4da19633 2906 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2907 return 0;
2908 }
2909 return -EOPNOTSUPP;
2910}
2911
8b4ab28d
FR		 2912static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2913{
2914 return -EOPNOTSUPP;
2915}
2916
0e485150
FR		 2917static const struct rtl_cfg_info {
2918 void (*hw_start)(struct net_device *);
2919 unsigned int region;
2920 unsigned int align;
2921 u16 intr_event;
2922 u16 napi_event;
ccdffb9a 2923 unsigned features;
f21b75e9 2924 u8 default_ver;
0e485150
FR		 2925} rtl_cfg_infos [] = {
2926 [RTL_CFG_0] = {
2927 .hw_start = rtl_hw_start_8169,
2928 .region = 1,
e9f63f30 2929 .align = 0,
0e485150
FR		 2930 .intr_event = SYSErr | LinkChg | RxOverflow |
2931 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2932 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2933 .features = RTL_FEATURE_GMII,
2934 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2935 },
2936 [RTL_CFG_1] = {
2937 .hw_start = rtl_hw_start_8168,
2938 .region = 2,
2939 .align = 8,
53f57357 2940 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2941 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2942 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2943 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2944 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2945 },
2946 [RTL_CFG_2] = {
2947 .hw_start = rtl_hw_start_8101,
2948 .region = 2,
2949 .align = 8,
2950 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2951 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2952 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2953 .features = RTL_FEATURE_MSI,
2954 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2955 }
2956};
2957
fbac58fc
FR		 2958/* Cfg9346_Unlock assumed. */
2959static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2960 const struct rtl_cfg_info *cfg)
2961{
2962 unsigned msi = 0;
2963 u8 cfg2;
2964
2965 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2966 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2967 if (pci_enable_msi(pdev)) {
2968 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2969 } else {
2970 cfg2 |= MSIEnable;
2971 msi = RTL_FEATURE_MSI;
2972 }
2973 }
2974 RTL_W8(Config2, cfg2);
2975 return msi;
2976}
2977
2978static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2979{
2980 if (tp->features & RTL_FEATURE_MSI) {
2981 pci_disable_msi(pdev);
2982 tp->features &= ~RTL_FEATURE_MSI;
2983 }
2984}
2985
8b4ab28d
FR		 2986static const struct net_device_ops rtl8169_netdev_ops = {
2987 .ndo_open = rtl8169_open,
2988 .ndo_stop = rtl8169_close,
2989 .ndo_get_stats = rtl8169_get_stats,
00829823 2990 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2991 .ndo_tx_timeout = rtl8169_tx_timeout,
2992 .ndo_validate_addr = eth_validate_addr,
2993 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2994 .ndo_fix_features = rtl8169_fix_features,
2995 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2996 .ndo_set_mac_address = rtl_set_mac_address,
2997 .ndo_do_ioctl = rtl8169_ioctl,
2998 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2999#ifdef CONFIG_NET_POLL_CONTROLLER
3000 .ndo_poll_controller = rtl8169_netpoll,
3001#endif
3002
3003};
3004
c0e45c1c 3005static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3006{
3007 struct mdio_ops *ops = &tp->mdio_ops;
3008
3009 switch (tp->mac_version) {
3010 case RTL_GIGA_MAC_VER_27:
3011 ops->write = r8168dp_1_mdio_write;
3012 ops->read = r8168dp_1_mdio_read;
3013 break;
e6de30d6 3014 case RTL_GIGA_MAC_VER_28:
4804b3b3 3015 case RTL_GIGA_MAC_VER_31:
e6de30d6 3016 ops->write = r8168dp_2_mdio_write;
3017 ops->read = r8168dp_2_mdio_read;
3018 break;
c0e45c1c 3019 default:
3020 ops->write = r8169_mdio_write;
3021 ops->read = r8169_mdio_read;
3022 break;
3023 }
3024}
3025
065c27c1 3026static void r810x_phy_power_down(struct rtl8169_private *tp)
3027{
3028 rtl_writephy(tp, 0x1f, 0x0000);
3029 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3030}
3031
3032static void r810x_phy_power_up(struct rtl8169_private *tp)
3033{
3034 rtl_writephy(tp, 0x1f, 0x0000);
3035 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3036}
3037
3038static void r810x_pll_power_down(struct rtl8169_private *tp)
3039{
3040 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3041 rtl_writephy(tp, 0x1f, 0x0000);
3042 rtl_writephy(tp, MII_BMCR, 0x0000);
3043 return;
3044 }
3045
3046 r810x_phy_power_down(tp);
3047}
3048
3049static void r810x_pll_power_up(struct rtl8169_private *tp)
3050{
3051 r810x_phy_power_up(tp);
3052}
3053
3054static void r8168_phy_power_up(struct rtl8169_private *tp)
3055{
3056 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3057 switch (tp->mac_version) {
3058 case RTL_GIGA_MAC_VER_11:
3059 case RTL_GIGA_MAC_VER_12:
3060 case RTL_GIGA_MAC_VER_17:
3061 case RTL_GIGA_MAC_VER_18:
3062 case RTL_GIGA_MAC_VER_19:
3063 case RTL_GIGA_MAC_VER_20:
3064 case RTL_GIGA_MAC_VER_21:
3065 case RTL_GIGA_MAC_VER_22:
3066 case RTL_GIGA_MAC_VER_23:
3067 case RTL_GIGA_MAC_VER_24:
3068 case RTL_GIGA_MAC_VER_25:
3069 case RTL_GIGA_MAC_VER_26:
3070 case RTL_GIGA_MAC_VER_27:
3071 case RTL_GIGA_MAC_VER_28:
3072 case RTL_GIGA_MAC_VER_31:
3073 rtl_writephy(tp, 0x0e, 0x0000);
3074 break;
3075 default:
3076 break;
3077 }
065c27c1 3078 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3079}
3080
3081static void r8168_phy_power_down(struct rtl8169_private *tp)
3082{
3083 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3084 switch (tp->mac_version) {
3085 case RTL_GIGA_MAC_VER_32:
3086 case RTL_GIGA_MAC_VER_33:
3087 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3088 break;
3089
3090 case RTL_GIGA_MAC_VER_11:
3091 case RTL_GIGA_MAC_VER_12:
3092 case RTL_GIGA_MAC_VER_17:
3093 case RTL_GIGA_MAC_VER_18:
3094 case RTL_GIGA_MAC_VER_19:
3095 case RTL_GIGA_MAC_VER_20:
3096 case RTL_GIGA_MAC_VER_21:
3097 case RTL_GIGA_MAC_VER_22:
3098 case RTL_GIGA_MAC_VER_23:
3099 case RTL_GIGA_MAC_VER_24:
3100 case RTL_GIGA_MAC_VER_25:
3101 case RTL_GIGA_MAC_VER_26:
3102 case RTL_GIGA_MAC_VER_27:
3103 case RTL_GIGA_MAC_VER_28:
3104 case RTL_GIGA_MAC_VER_31:
3105 rtl_writephy(tp, 0x0e, 0x0200);
3106 default:
3107 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3108 break;
3109 }
065c27c1 3110}
3111
3112static void r8168_pll_power_down(struct rtl8169_private *tp)
3113{
3114 void __iomem *ioaddr = tp->mmio_addr;
3115
5d2e1957 3116 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3117 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3118 (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3119 r8168dp_check_dash(tp)) {
065c27c1 3120 return;
5d2e1957 3121 }
065c27c1 3122
3123 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
3124 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
3125 (RTL_R16(CPlusCmd) & ASF)) {
3126 return;
3127 }
3128
01dc7fec 3129 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3130 tp->mac_version == RTL_GIGA_MAC_VER_33)
3131 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3132
065c27c1 3133 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3134 rtl_writephy(tp, 0x1f, 0x0000);
3135 rtl_writephy(tp, MII_BMCR, 0x0000);
3136
3137 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3138 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3139 return;
3140 }
3141
3142 r8168_phy_power_down(tp);
3143
3144 switch (tp->mac_version) {
3145 case RTL_GIGA_MAC_VER_25:
3146 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3147 case RTL_GIGA_MAC_VER_27:
3148 case RTL_GIGA_MAC_VER_28:
4804b3b3 3149 case RTL_GIGA_MAC_VER_31:
01dc7fec 3150 case RTL_GIGA_MAC_VER_32:
3151 case RTL_GIGA_MAC_VER_33:
065c27c1 3152 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3153 break;
3154 }
3155}
3156
3157static void r8168_pll_power_up(struct rtl8169_private *tp)
3158{
3159 void __iomem *ioaddr = tp->mmio_addr;
3160
5d2e1957 3161 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3162 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3163 (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3164 r8168dp_check_dash(tp)) {
065c27c1 3165 return;
5d2e1957 3166 }
065c27c1 3167
3168 switch (tp->mac_version) {
3169 case RTL_GIGA_MAC_VER_25:
3170 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3171 case RTL_GIGA_MAC_VER_27:
3172 case RTL_GIGA_MAC_VER_28:
4804b3b3 3173 case RTL_GIGA_MAC_VER_31:
01dc7fec 3174 case RTL_GIGA_MAC_VER_32:
3175 case RTL_GIGA_MAC_VER_33:
065c27c1 3176 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3177 break;
3178 }
3179
3180 r8168_phy_power_up(tp);
3181}
3182
3183static void rtl_pll_power_op(struct rtl8169_private *tp,
3184 void (*op)(struct rtl8169_private *))
3185{
3186 if (op)
3187 op(tp);
3188}
3189
3190static void rtl_pll_power_down(struct rtl8169_private *tp)
3191{
3192 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3193}
3194
3195static void rtl_pll_power_up(struct rtl8169_private *tp)
3196{
3197 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3198}
3199
3200static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3201{
3202 struct pll_power_ops *ops = &tp->pll_power_ops;
3203
3204 switch (tp->mac_version) {
3205 case RTL_GIGA_MAC_VER_07:
3206 case RTL_GIGA_MAC_VER_08:
3207 case RTL_GIGA_MAC_VER_09:
3208 case RTL_GIGA_MAC_VER_10:
3209 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3210 case RTL_GIGA_MAC_VER_29:
3211 case RTL_GIGA_MAC_VER_30:
065c27c1 3212 ops->down = r810x_pll_power_down;
3213 ops->up = r810x_pll_power_up;
3214 break;
3215
3216 case RTL_GIGA_MAC_VER_11:
3217 case RTL_GIGA_MAC_VER_12:
3218 case RTL_GIGA_MAC_VER_17:
3219 case RTL_GIGA_MAC_VER_18:
3220 case RTL_GIGA_MAC_VER_19:
3221 case RTL_GIGA_MAC_VER_20:
3222 case RTL_GIGA_MAC_VER_21:
3223 case RTL_GIGA_MAC_VER_22:
3224 case RTL_GIGA_MAC_VER_23:
3225 case RTL_GIGA_MAC_VER_24:
3226 case RTL_GIGA_MAC_VER_25:
3227 case RTL_GIGA_MAC_VER_26:
3228 case RTL_GIGA_MAC_VER_27:
e6de30d6 3229 case RTL_GIGA_MAC_VER_28:
4804b3b3 3230 case RTL_GIGA_MAC_VER_31:
01dc7fec 3231 case RTL_GIGA_MAC_VER_32:
3232 case RTL_GIGA_MAC_VER_33:
065c27c1 3233 ops->down = r8168_pll_power_down;
3234 ops->up = r8168_pll_power_up;
3235 break;
3236
3237 default:
3238 ops->down = NULL;
3239 ops->up = NULL;
3240 break;
3241 }
3242}
3243
1da177e4 3244static int __devinit
4ff96fa6 3245rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3246{
0e485150
FR		 3247 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3248 const unsigned int region = cfg->region;
1da177e4 3249 struct rtl8169_private *tp;
ccdffb9a 3250 struct mii_if_info *mii;
4ff96fa6
FR		 3251 struct net_device *dev;
3252 void __iomem *ioaddr;
2b7b4318 3253 int chipset, i;
07d3f51f 3254 int rc;
1da177e4 3255
4ff96fa6
FR		 3256 if (netif_msg_drv(&debug)) {
3257 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3258 MODULENAME, RTL8169_VERSION);
3259 }
1da177e4 3260
1da177e4 3261 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3262 if (!dev) {
b57b7e5a 3263 if (netif_msg_drv(&debug))
9b91cf9d 3264 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3265 rc = -ENOMEM;
3266 goto out;
1da177e4
LT		 3267 }
3268
1da177e4 3269 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3270 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3271 tp = netdev_priv(dev);
c4028958 3272 tp->dev = dev;
21e197f2 3273 tp->pci_dev = pdev;
b57b7e5a 3274 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3275
ccdffb9a
FR		 3276 mii = &tp->mii;
3277 mii->dev = dev;
3278 mii->mdio_read = rtl_mdio_read;
3279 mii->mdio_write = rtl_mdio_write;
3280 mii->phy_id_mask = 0x1f;
3281 mii->reg_num_mask = 0x1f;
3282 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3283
ba04c7c9
SG		 3284 /* disable ASPM completely as that cause random device stop working
3285 * problems as well as full system hangs for some PCIe devices users */
3286 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3287 PCIE_LINK_STATE_CLKPM);
3288
1da177e4
LT		 3289 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3290 rc = pci_enable_device(pdev);
b57b7e5a 3291 if (rc < 0) {
bf82c189 3292 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3293 goto err_out_free_dev_1;
1da177e4
LT		 3294 }
3295
87aeec76 3296 if (pci_set_mwi(pdev) < 0)
3297 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3298
1da177e4 3299 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3300 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3301 netif_err(tp, probe, dev,
3302 "region #%d not an MMIO resource, aborting\n",
3303 region);
1da177e4 3304 rc = -ENODEV;
87aeec76 3305 goto err_out_mwi_2;
1da177e4 3306 }
4ff96fa6 3307
1da177e4 3308 /* check for weird/broken PCI region reporting */
bcf0bf90 3309 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3310 netif_err(tp, probe, dev,
3311 "Invalid PCI region size(s), aborting\n");
1da177e4 3312 rc = -ENODEV;
87aeec76 3313 goto err_out_mwi_2;
1da177e4
LT		 3314 }
3315
3316 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3317 if (rc < 0) {
bf82c189 3318 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3319 goto err_out_mwi_2;
1da177e4
LT		 3320 }
3321
d24e9aaf 3322 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3323
3324 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3325 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3326 tp->cp_cmd |= PCIDAC;
3327 dev->features |= NETIF_F_HIGHDMA;
3328 } else {
284901a9 3329 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3330 if (rc < 0) {
bf82c189 3331 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3332 goto err_out_free_res_3;
1da177e4
LT		 3333 }
3334 }
3335
1da177e4 3336 /* ioremap MMIO region */
bcf0bf90 3337 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3338 if (!ioaddr) {
bf82c189 3339 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3340 rc = -EIO;
87aeec76 3341 goto err_out_free_res_3;
1da177e4
LT		 3342 }
3343
4300e8c7
DM		 3344 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3345 if (!tp->pcie_cap)
3346 netif_info(tp, probe, dev, "no PCI Express capability\n");
3347
d78ad8cb 3348 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3349
3350 /* Soft reset the chip. */
3351 RTL_W8(ChipCmd, CmdReset);
3352
3353 /* Check that the chip has finished the reset. */
07d3f51f 3354 for (i = 0; i < 100; i++) {
1da177e4
LT		 3355 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3356 break;
b518fa8e 3357 msleep_interruptible(1);
1da177e4
LT		 3358 }
3359
d78ad8cb
KW		 3360 RTL_W16(IntrStatus, 0xffff);
3361
ca52efd5 3362 pci_set_master(pdev);
3363
1da177e4
LT		 3364 /* Identify chip attached to board */
3365 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3366
7a8fc77b
FR		 3367 /*
3368 * Pretend we are using VLANs; This bypasses a nasty bug where
3369 * Interrupts stop flowing on high load on 8110SCd controllers.
3370 */
3371 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3372 tp->cp_cmd |= RxVlan;
3373
c0e45c1c 3374 rtl_init_mdio_ops(tp);
065c27c1 3375 rtl_init_pll_power_ops(tp);
c0e45c1c 3376
f21b75e9
JD		 3377 /* Use appropriate default if unknown */
3378 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3379 netif_notice(tp, probe, dev,
3380 "unknown MAC, using family default\n");
f21b75e9
JD		 3381 tp->mac_version = cfg->default_ver;
3382 }
3383
1da177e4 3384 rtl8169_print_mac_version(tp);
1da177e4 3385
cee60c37 3386 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3387 if (tp->mac_version == rtl_chip_info[i].mac_version)
3388 break;
3389 }
cee60c37 3390 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3391 dev_err(&pdev->dev,
3392 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3393 goto err_out_msi_4;
1da177e4 3394 }
2b7b4318
FR		 3395 chipset = i;
3396 tp->txd_version = rtl_chip_info[chipset].txd_version;
1da177e4 3397
5d06a99f
FR		 3398 RTL_W8(Cfg9346, Cfg9346_Unlock);
3399 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3400 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3401 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3402 tp->features |= RTL_FEATURE_WOL;
3403 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3404 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3405 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3406 RTL_W8(Cfg9346, Cfg9346_Lock);
3407
66ec5d4f
FR		 3408 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3409 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3410 tp->set_speed = rtl8169_set_speed_tbi;
3411 tp->get_settings = rtl8169_gset_tbi;
3412 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3413 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3414 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3415 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3416
64e4bfb4 3417 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3418 } else {
3419 tp->set_speed = rtl8169_set_speed_xmii;
3420 tp->get_settings = rtl8169_gset_xmii;
3421 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3422 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3423 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3424 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3425 }
3426
df58ef51
FR		 3427 spin_lock_init(&tp->lock);
3428
738e1e69
PV		 3429 tp->mmio_addr = ioaddr;
3430
7bf6bf48 3431 /* Get MAC address */
1da177e4
LT		 3432 for (i = 0; i < MAC_ADDR_LEN; i++)
3433 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3434 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3435
1da177e4 3436 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3437 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3438 dev->irq = pdev->irq;
3439 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3440
bea3348e 3441 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3442
350fb32a
MM		 3443 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3444 * properly for all devices */
3445 dev->features |= NETIF_F_RXCSUM |
3446 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3447
3448 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3449 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3450 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3451 NETIF_F_HIGHDMA;
3452
3453 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3454 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3455 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3456
3457 tp->intr_mask = 0xffff;
0e485150
FR		 3458 tp->hw_start = cfg->hw_start;
3459 tp->intr_event = cfg->intr_event;
3460 tp->napi_event = cfg->napi_event;
1da177e4 3461
2efa53f3
FR		 3462 init_timer(&tp->timer);
3463 tp->timer.data = (unsigned long) dev;
3464 tp->timer.function = rtl8169_phy_timer;
3465
1da177e4 3466 rc = register_netdev(dev);
4ff96fa6 3467 if (rc < 0)
87aeec76 3468 goto err_out_msi_4;
1da177e4
LT		 3469
3470 pci_set_drvdata(pdev, dev);
3471
bf82c189 3472 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2b7b4318 3473 rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3474 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3475
e6de30d6 3476 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3477 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3478 (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
b646d900 3479 rtl8168_driver_start(tp);
e6de30d6 3480 }
b646d900 3481
8b76ab39 3482 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3483
f3ec4f87
AS		 3484 if (pci_dev_run_wake(pdev))
3485 pm_runtime_put_noidle(&pdev->dev);
e1759441 3486
0d672e9f
IV		 3487 netif_carrier_off(dev);
3488
4ff96fa6
FR		 3489out:
3490 return rc;
1da177e4 3491
87aeec76 3492err_out_msi_4:
fbac58fc 3493 rtl_disable_msi(pdev, tp);
4ff96fa6 3494 iounmap(ioaddr);
87aeec76 3495err_out_free_res_3:
4ff96fa6 3496 pci_release_regions(pdev);
87aeec76 3497err_out_mwi_2:
4ff96fa6 3498 pci_clear_mwi(pdev);
4ff96fa6
FR		 3499 pci_disable_device(pdev);
3500err_out_free_dev_1:
3501 free_netdev(dev);
3502 goto out;
1da177e4
LT		 3503}
3504
07d3f51f 3505static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3506{
3507 struct net_device *dev = pci_get_drvdata(pdev);
3508 struct rtl8169_private *tp = netdev_priv(dev);
3509
e6de30d6 3510 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3511 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3512 (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
b646d900 3513 rtl8168_driver_stop(tp);
e6de30d6 3514 }
b646d900 3515
23f333a2 3516 cancel_delayed_work_sync(&tp->task);
eb2a021c 3517
f1e02ed1 3518 rtl_release_firmware(tp);
3519
1da177e4 3520 unregister_netdev(dev);
cc098dc7 3521
f3ec4f87
AS		 3522 if (pci_dev_run_wake(pdev))
3523 pm_runtime_get_noresume(&pdev->dev);
e1759441 3524
cc098dc7
IV		 3525 /* restore original MAC address */
3526 rtl_rar_set(tp, dev->perm_addr);
3527
fbac58fc 3528 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3529 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3530 pci_set_drvdata(pdev, NULL);
3531}
3532
1da177e4
LT		 3533static int rtl8169_open(struct net_device *dev)
3534{
3535 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3536 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3537 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3538 int retval = -ENOMEM;
1da177e4 3539
e1759441 3540 pm_runtime_get_sync(&pdev->dev);
1da177e4 3541
1da177e4
LT		 3542 /*
3543 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3544 * dma_alloc_coherent provides more.
1da177e4 3545 */
82553bb6
SG		 3546 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3547 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3548 if (!tp->TxDescArray)
e1759441 3549 goto err_pm_runtime_put;
1da177e4 3550
82553bb6
SG		 3551 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3552 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3553 if (!tp->RxDescArray)
99f252b0 3554 goto err_free_tx_0;
1da177e4
LT		 3555
3556 retval = rtl8169_init_ring(dev);
3557 if (retval < 0)
99f252b0 3558 goto err_free_rx_1;
1da177e4 3559
c4028958 3560 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3561
99f252b0
FR		 3562 smp_mb();
3563
fbac58fc
FR		 3564 retval = request_irq(dev->irq, rtl8169_interrupt,
3565 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3566 dev->name, dev);
3567 if (retval < 0)
3568 goto err_release_ring_2;
3569
bea3348e 3570 napi_enable(&tp->napi);
bea3348e 3571
eee3a96c 3572 rtl8169_init_phy(dev, tp);
3573
350fb32a 3574 rtl8169_set_features(dev, dev->features);
eee3a96c 3575
065c27c1 3576 rtl_pll_power_up(tp);
3577
07ce4064 3578 rtl_hw_start(dev);
1da177e4
LT		 3579
3580 rtl8169_request_timer(dev);
3581
e1759441
RW		 3582 tp->saved_wolopts = 0;
3583 pm_runtime_put_noidle(&pdev->dev);
3584
eee3a96c 3585 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3586out:
3587 return retval;
3588
99f252b0
FR		 3589err_release_ring_2:
3590 rtl8169_rx_clear(tp);
3591err_free_rx_1:
82553bb6
SG		 3592 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3593 tp->RxPhyAddr);
e1759441 3594 tp->RxDescArray = NULL;
99f252b0 3595err_free_tx_0:
82553bb6
SG		 3596 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3597 tp->TxPhyAddr);
e1759441
RW		 3598 tp->TxDescArray = NULL;
3599err_pm_runtime_put:
3600 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3601 goto out;
3602}
3603
e6de30d6 3604static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3605{
e6de30d6 3606 void __iomem *ioaddr = tp->mmio_addr;
3607
1da177e4
LT		 3608 /* Disable interrupts */
3609 rtl8169_irq_mask_and_ack(ioaddr);
3610
5d2e1957 3611 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3612 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3613 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3614 while (RTL_R8(TxPoll) & NPQ)
3615 udelay(20);
3616
3617 }
3618
1da177e4
LT		 3619 /* Reset the chipset */
3620 RTL_W8(ChipCmd, CmdReset);
3621
3622 /* PCI commit */
3623 RTL_R8(ChipCmd);
3624}
3625
7f796d83 3626static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3627{
3628 void __iomem *ioaddr = tp->mmio_addr;
3629 u32 cfg = rtl8169_rx_config;
3630
2b7b4318 3631 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3632 RTL_W32(RxConfig, cfg);
3633
3634 /* Set DMA burst size and Interframe Gap Time */
3635 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3636 (InterFrameGap << TxInterFrameGapShift));
3637}
3638
07ce4064 3639static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3640{
3641 struct rtl8169_private *tp = netdev_priv(dev);
3642 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3643 unsigned int i;
1da177e4
LT		 3644
3645 /* Soft reset the chip. */
3646 RTL_W8(ChipCmd, CmdReset);
3647
3648 /* Check that the chip has finished the reset. */
07d3f51f 3649 for (i = 0; i < 100; i++) {
1da177e4
LT		 3650 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3651 break;
b518fa8e 3652 msleep_interruptible(1);
1da177e4
LT		 3653 }
3654
07ce4064
FR		 3655 tp->hw_start(dev);
3656
07ce4064
FR		 3657 netif_start_queue(dev);
3658}
3659
3660
7f796d83
FR		 3661static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3662 void __iomem *ioaddr)
3663{
3664 /*
3665 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3666 * register to be written before TxDescAddrLow to work.
3667 * Switching from MMIO to I/O access fixes the issue as well.
3668 */
3669 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3670 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3671 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3672 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3673}
3674
3675static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3676{
3677 u16 cmd;
3678
3679 cmd = RTL_R16(CPlusCmd);
3680 RTL_W16(CPlusCmd, cmd);
3681 return cmd;
3682}
3683
fdd7b4c3 3684static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3685{
3686 /* Low hurts. Let's disable the filtering. */
207d6e87 3687 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3688}
3689
6dccd16b
FR		 3690static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3691{
350f7596 3692 static const struct {
6dccd16b
FR		 3693 u32 mac_version;
3694 u32 clk;
3695 u32 val;
3696 } cfg2_info [] = {
3697 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3698 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3699 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3700 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3701 }, *p = cfg2_info;
3702 unsigned int i;
3703 u32 clk;
3704
3705 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3706 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3707 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3708 RTL_W32(0x7c, p->val);
3709 break;
3710 }
3711 }
3712}
3713
07ce4064
FR		 3714static void rtl_hw_start_8169(struct net_device *dev)
3715{
3716 struct rtl8169_private *tp = netdev_priv(dev);
3717 void __iomem *ioaddr = tp->mmio_addr;
3718 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3719
9cb427b6
FR		 3720 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3721 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3722 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3723 }
3724
1da177e4 3725 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3726 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3727 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3728 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3729 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3730 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3731
f0298f81 3732 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3733
6f0333b8 3734 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3735
c946b304
FR		 3736 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3737 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3738 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3739 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3740 rtl_set_rx_tx_config_registers(tp);
1da177e4 3741
7f796d83 3742 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3743
bcf0bf90
FR		 3744 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3745 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3746 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3747 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3748 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3749 }
3750
bcf0bf90
FR		 3751 RTL_W16(CPlusCmd, tp->cp_cmd);
3752
6dccd16b
FR		 3753 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3754
1da177e4
LT		 3755 /*
3756 * Undocumented corner. Supposedly:
3757 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3758 */
3759 RTL_W16(IntrMitigate, 0x0000);
3760
7f796d83 3761 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3762
c946b304
FR		 3763 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3764 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3765 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3766 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3767 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3768 rtl_set_rx_tx_config_registers(tp);
3769 }
3770
1da177e4 3771 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3772
3773 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3774 RTL_R8(IntrMask);
1da177e4
LT		 3775
3776 RTL_W32(RxMissed, 0);
3777
07ce4064 3778 rtl_set_rx_mode(dev);
1da177e4
LT		 3779
3780 /* no early-rx interrupts */
3781 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3782
3783 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3784 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3785}
1da177e4 3786
9c14ceaf 3787static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3788{
9c14ceaf
FR		 3789 struct net_device *dev = pci_get_drvdata(pdev);
3790 struct rtl8169_private *tp = netdev_priv(dev);
3791 int cap = tp->pcie_cap;
3792
3793 if (cap) {
3794 u16 ctl;
458a9f61 3795
9c14ceaf
FR		 3796 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3797 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3798 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3799 }
458a9f61
FR		 3800}
3801
650e8d5d 3802static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3803{
3804 u32 csi;
3805
3806 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3807 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3808}
3809
e6de30d6 3810static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3811{
3812 rtl_csi_access_enable(ioaddr, 0x17000000);
3813}
3814
650e8d5d 3815static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3816{
3817 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3818}
3819
3820struct ephy_info {
3821 unsigned int offset;
3822 u16 mask;
3823 u16 bits;
3824};
3825
350f7596 3826static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3827{
3828 u16 w;
3829
3830 while (len-- > 0) {
3831 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3832 rtl_ephy_write(ioaddr, e->offset, w);
3833 e++;
3834 }
3835}
3836
b726e493
FR		 3837static void rtl_disable_clock_request(struct pci_dev *pdev)
3838{
3839 struct net_device *dev = pci_get_drvdata(pdev);
3840 struct rtl8169_private *tp = netdev_priv(dev);
3841 int cap = tp->pcie_cap;
3842
3843 if (cap) {
3844 u16 ctl;
3845
3846 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3847 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3848 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3849 }
3850}
3851
e6de30d6 3852static void rtl_enable_clock_request(struct pci_dev *pdev)
3853{
3854 struct net_device *dev = pci_get_drvdata(pdev);
3855 struct rtl8169_private *tp = netdev_priv(dev);
3856 int cap = tp->pcie_cap;
3857
3858 if (cap) {
3859 u16 ctl;
3860
3861 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3862 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3863 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3864 }
3865}
3866
b726e493
FR		 3867#define R8168_CPCMD_QUIRK_MASK (\
3868 EnableBist | \
3869 Mac_dbgo_oe | \
3870 Force_half_dup | \
3871 Force_rxflow_en | \
3872 Force_txflow_en | \
3873 Cxpl_dbg_sel | \
3874 ASF | \
3875 PktCntrDisable | \
3876 Mac_dbgo_sel)
3877
219a1e9d
FR		 3878static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3879{
b726e493
FR		 3880 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3881
3882 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3883
2e68ae44
FR		 3884 rtl_tx_performance_tweak(pdev,
3885 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3886}
3887
3888static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3889{
3890 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3891
f0298f81 3892 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3893
3894 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3895}
3896
3897static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3898{
b726e493
FR		 3899 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3900
3901 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3902
219a1e9d 3903 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3904
3905 rtl_disable_clock_request(pdev);
3906
3907 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3908}
3909
ef3386f0 3910static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3911{
350f7596 3912 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3913 { 0x01, 0, 0x0001 },
3914 { 0x02, 0x0800, 0x1000 },
3915 { 0x03, 0, 0x0042 },
3916 { 0x06, 0x0080, 0x0000 },
3917 { 0x07, 0, 0x2000 }
3918 };
3919
650e8d5d 3920 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3921
3922 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3923
219a1e9d
FR		 3924 __rtl_hw_start_8168cp(ioaddr, pdev);
3925}
3926
ef3386f0
FR		 3927static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3928{
650e8d5d 3929 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3930
3931 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3932
3933 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3934
3935 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3936}
3937
7f3e3d3a
FR		 3938static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3939{
650e8d5d 3940 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3941
3942 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3943
3944 /* Magic. */
3945 RTL_W8(DBG_REG, 0x20);
3946
f0298f81 3947 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3948
3949 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3950
3951 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3952}
3953
219a1e9d
FR		 3954static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3955{
350f7596 3956 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3957 { 0x02, 0x0800, 0x1000 },
3958 { 0x03, 0, 0x0002 },
3959 { 0x06, 0x0080, 0x0000 }
3960 };
3961
650e8d5d 3962 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3963
3964 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3965
3966 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3967
219a1e9d
FR		 3968 __rtl_hw_start_8168cp(ioaddr, pdev);
3969}
3970
3971static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3972{
350f7596 3973 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3974 { 0x01, 0, 0x0001 },
3975 { 0x03, 0x0400, 0x0220 }
3976 };
3977
650e8d5d 3978 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3979
3980 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3981
219a1e9d
FR		 3982 __rtl_hw_start_8168cp(ioaddr, pdev);
3983}
3984
197ff761
FR		 3985static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3986{
3987 rtl_hw_start_8168c_2(ioaddr, pdev);
3988}
3989
6fb07058
FR		 3990static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3991{
650e8d5d 3992 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3993
3994 __rtl_hw_start_8168cp(ioaddr, pdev);
3995}
3996
5b538df9
FR		 3997static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3998{
650e8d5d 3999 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4000
4001 rtl_disable_clock_request(pdev);
4002
f0298f81 4003 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4004
4005 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4006
4007 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4008}
4009
4804b3b3 4010static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4011{
4012 rtl_csi_access_enable_1(ioaddr);
4013
4014 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4015
4016 RTL_W8(MaxTxPacketSize, TxPacketMax);
4017
4018 rtl_disable_clock_request(pdev);
4019}
4020
e6de30d6 4021static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4022{
4023 static const struct ephy_info e_info_8168d_4[] = {
4024 { 0x0b, ~0, 0x48 },
4025 { 0x19, 0x20, 0x50 },
4026 { 0x0c, ~0, 0x20 }
4027 };
4028 int i;
4029
4030 rtl_csi_access_enable_1(ioaddr);
4031
4032 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4033
4034 RTL_W8(MaxTxPacketSize, TxPacketMax);
4035
4036 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4037 const struct ephy_info *e = e_info_8168d_4 + i;
4038 u16 w;
4039
4040 w = rtl_ephy_read(ioaddr, e->offset);
4041 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4042 }
4043
4044 rtl_enable_clock_request(pdev);
4045}
4046
01dc7fec 4047static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4048{
4049 static const struct ephy_info e_info_8168e[] = {
4050 { 0x00, 0x0200, 0x0100 },
4051 { 0x00, 0x0000, 0x0004 },
4052 { 0x06, 0x0002, 0x0001 },
4053 { 0x06, 0x0000, 0x0030 },
4054 { 0x07, 0x0000, 0x2000 },
4055 { 0x00, 0x0000, 0x0020 },
4056 { 0x03, 0x5800, 0x2000 },
4057 { 0x03, 0x0000, 0x0001 },
4058 { 0x01, 0x0800, 0x1000 },
4059 { 0x07, 0x0000, 0x4000 },
4060 { 0x1e, 0x0000, 0x2000 },
4061 { 0x19, 0xffff, 0xfe6c },
4062 { 0x0a, 0x0000, 0x0040 }
4063 };
4064
4065 rtl_csi_access_enable_2(ioaddr);
4066
4067 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4068
4069 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4070
4071 RTL_W8(MaxTxPacketSize, TxPacketMax);
4072
4073 rtl_disable_clock_request(pdev);
4074
4075 /* Reset tx FIFO pointer */
4076 RTL_W32(MISC, RTL_R32(MISC) | txpla_rst);
4077 RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst);
4078
4079 RTL_W8(Config5, RTL_R8(Config5) & ~spi_en);
4080}
4081
07ce4064
FR		 4082static void rtl_hw_start_8168(struct net_device *dev)
4083{
2dd99530
FR		 4084 struct rtl8169_private *tp = netdev_priv(dev);
4085 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4086 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4087
4088 RTL_W8(Cfg9346, Cfg9346_Unlock);
4089
f0298f81 4090 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4091
6f0333b8 4092 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4093
0e485150 4094 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4095
4096 RTL_W16(CPlusCmd, tp->cp_cmd);
4097
0e485150 4098 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4099
0e485150 4100 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4101 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4102 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4103 tp->intr_event |= RxFIFOOver | PCSTimeout;
4104 tp->intr_event &= ~RxOverflow;
4105 }
4106
4107 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4108
b8363901
FR		 4109 rtl_set_rx_mode(dev);
4110
4111 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4112 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4113
4114 RTL_R8(IntrMask);
4115
219a1e9d
FR		 4116 switch (tp->mac_version) {
4117 case RTL_GIGA_MAC_VER_11:
4118 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4119 break;
219a1e9d
FR		 4120
4121 case RTL_GIGA_MAC_VER_12:
4122 case RTL_GIGA_MAC_VER_17:
4123 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4124 break;
219a1e9d
FR		 4125
4126 case RTL_GIGA_MAC_VER_18:
ef3386f0 4127 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4128 break;
219a1e9d
FR		 4129
4130 case RTL_GIGA_MAC_VER_19:
4131 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4132 break;
219a1e9d
FR		 4133
4134 case RTL_GIGA_MAC_VER_20:
4135 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4136 break;
219a1e9d 4137
197ff761
FR		 4138 case RTL_GIGA_MAC_VER_21:
4139 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4140 break;
197ff761 4141
6fb07058
FR		 4142 case RTL_GIGA_MAC_VER_22:
4143 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4144 break;
6fb07058 4145
ef3386f0
FR		 4146 case RTL_GIGA_MAC_VER_23:
4147 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4148 break;
ef3386f0 4149
7f3e3d3a
FR		 4150 case RTL_GIGA_MAC_VER_24:
4151 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4152 break;
7f3e3d3a 4153
5b538df9 4154 case RTL_GIGA_MAC_VER_25:
daf9df6d 4155 case RTL_GIGA_MAC_VER_26:
4156 case RTL_GIGA_MAC_VER_27:
5b538df9 4157 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4158 break;
5b538df9 4159
e6de30d6 4160 case RTL_GIGA_MAC_VER_28:
4161 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4162 break;
4163 case RTL_GIGA_MAC_VER_31:
4164 rtl_hw_start_8168dp(ioaddr, pdev);
4165 break;
4166
01dc7fec 4167 case RTL_GIGA_MAC_VER_32:
4168 case RTL_GIGA_MAC_VER_33:
4169 rtl_hw_start_8168e(ioaddr, pdev);
4170 break;
e6de30d6 4171
219a1e9d
FR		 4172 default:
4173 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4174 dev->name, tp->mac_version);
4804b3b3 4175 break;
219a1e9d 4176 }
2dd99530 4177
0e485150
FR		 4178 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4179
b8363901
FR		 4180 RTL_W8(Cfg9346, Cfg9346_Lock);
4181
2dd99530 4182 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4183
0e485150 4184 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4185}
1da177e4 4186
2857ffb7
FR		 4187#define R810X_CPCMD_QUIRK_MASK (\
4188 EnableBist | \
4189 Mac_dbgo_oe | \
4190 Force_half_dup | \
5edcc537 4191 Force_rxflow_en | \
2857ffb7
FR		 4192 Force_txflow_en | \
4193 Cxpl_dbg_sel | \
4194 ASF | \
4195 PktCntrDisable | \
d24e9aaf 4196 Mac_dbgo_sel)
2857ffb7
FR		 4197
4198static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4199{
350f7596 4200 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4201 { 0x01, 0, 0x6e65 },
4202 { 0x02, 0, 0x091f },
4203 { 0x03, 0, 0xc2f9 },
4204 { 0x06, 0, 0xafb5 },
4205 { 0x07, 0, 0x0e00 },
4206 { 0x19, 0, 0xec80 },
4207 { 0x01, 0, 0x2e65 },
4208 { 0x01, 0, 0x6e65 }
4209 };
4210 u8 cfg1;
4211
650e8d5d 4212 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4213
4214 RTL_W8(DBG_REG, FIX_NAK_1);
4215
4216 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4217
4218 RTL_W8(Config1,
4219 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4220 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4221
4222 cfg1 = RTL_R8(Config1);
4223 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4224 RTL_W8(Config1, cfg1 & ~LEDS0);
4225
2857ffb7
FR		 4226 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4227}
4228
4229static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4230{
650e8d5d 4231 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4232
4233 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4234
4235 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4236 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4237}
4238
4239static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4240{
4241 rtl_hw_start_8102e_2(ioaddr, pdev);
4242
4243 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4244}
4245
5a5e4443
HW		 4246static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4247{
4248 static const struct ephy_info e_info_8105e_1[] = {
4249 { 0x07, 0, 0x4000 },
4250 { 0x19, 0, 0x0200 },
4251 { 0x19, 0, 0x0020 },
4252 { 0x1e, 0, 0x2000 },
4253 { 0x03, 0, 0x0001 },
4254 { 0x19, 0, 0x0100 },
4255 { 0x19, 0, 0x0004 },
4256 { 0x0a, 0, 0x0020 }
4257 };
4258
4259 /* Force LAN exit from ASPM if Rx/Tx are not idel */
4260 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4261
4262 /* disable Early Tally Counter */
4263 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4264
4265 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4266 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4267
4268 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4269}
4270
4271static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4272{
4273 rtl_hw_start_8105e_1(ioaddr, pdev);
4274 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4275}
4276
07ce4064
FR		 4277static void rtl_hw_start_8101(struct net_device *dev)
4278{
cdf1a608
FR		 4279 struct rtl8169_private *tp = netdev_priv(dev);
4280 void __iomem *ioaddr = tp->mmio_addr;
4281 struct pci_dev *pdev = tp->pci_dev;
4282
e3cf0cc0
FR		 4283 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4284 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 4285 int cap = tp->pcie_cap;
4286
4287 if (cap) {
4288 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4289 PCI_EXP_DEVCTL_NOSNOOP_EN);
4290 }
cdf1a608
FR		 4291 }
4292
d24e9aaf
HW		 4293 RTL_W8(Cfg9346, Cfg9346_Unlock);
4294
2857ffb7
FR		 4295 switch (tp->mac_version) {
4296 case RTL_GIGA_MAC_VER_07:
4297 rtl_hw_start_8102e_1(ioaddr, pdev);
4298 break;
4299
4300 case RTL_GIGA_MAC_VER_08:
4301 rtl_hw_start_8102e_3(ioaddr, pdev);
4302 break;
4303
4304 case RTL_GIGA_MAC_VER_09:
4305 rtl_hw_start_8102e_2(ioaddr, pdev);
4306 break;
5a5e4443
HW		 4307
4308 case RTL_GIGA_MAC_VER_29:
4309 rtl_hw_start_8105e_1(ioaddr, pdev);
4310 break;
4311 case RTL_GIGA_MAC_VER_30:
4312 rtl_hw_start_8105e_2(ioaddr, pdev);
4313 break;
cdf1a608
FR		 4314 }
4315
d24e9aaf 4316 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4317
f0298f81 4318 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4319
6f0333b8 4320 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4321
d24e9aaf 4322 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4323 RTL_W16(CPlusCmd, tp->cp_cmd);
4324
4325 RTL_W16(IntrMitigate, 0x0000);
4326
4327 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4328
4329 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4330 rtl_set_rx_tx_config_registers(tp);
4331
cdf1a608
FR		 4332 RTL_R8(IntrMask);
4333
cdf1a608
FR		 4334 rtl_set_rx_mode(dev);
4335
4336 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4337
0e485150 4338 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4339}
4340
4341static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4342{
1da177e4
LT		 4343 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4344 return -EINVAL;
4345
4346 dev->mtu = new_mtu;
350fb32a
MM		 4347 netdev_update_features(dev);
4348
323bb685 4349 return 0;
1da177e4
LT		 4350}
4351
4352static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4353{
95e0918d 4354 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4355 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4356}
4357
6f0333b8
ED		 4358static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4359 void **data_buff, struct RxDesc *desc)
1da177e4 4360{
48addcc9 4361 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4362 DMA_FROM_DEVICE);
48addcc9 4363
6f0333b8
ED		 4364 kfree(*data_buff);
4365 *data_buff = NULL;
1da177e4
LT		 4366 rtl8169_make_unusable_by_asic(desc);
4367}
4368
4369static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4370{
4371 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4372
4373 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4374}
4375
4376static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4377 u32 rx_buf_sz)
4378{
4379 desc->addr = cpu_to_le64(mapping);
4380 wmb();
4381 rtl8169_mark_to_asic(desc, rx_buf_sz);
4382}
4383
6f0333b8
ED		 4384static inline void *rtl8169_align(void *data)
4385{
4386 return (void *)ALIGN((long)data, 16);
4387}
4388
0ecbe1ca
SG		 4389static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4390 struct RxDesc *desc)
1da177e4 4391{
6f0333b8 4392 void *data;
1da177e4 4393 dma_addr_t mapping;
48addcc9 4394 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4395 struct net_device *dev = tp->dev;
6f0333b8 4396 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4397
6f0333b8
ED		 4398 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4399 if (!data)
4400 return NULL;
e9f63f30 4401
6f0333b8
ED		 4402 if (rtl8169_align(data) != data) {
4403 kfree(data);
4404 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4405 if (!data)
4406 return NULL;
4407 }
3eafe507 4408
48addcc9 4409 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4410 DMA_FROM_DEVICE);
d827d86b
SG		 4411 if (unlikely(dma_mapping_error(d, mapping))) {
4412 if (net_ratelimit())
4413 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4414 goto err_out;
d827d86b 4415 }
1da177e4
LT		 4416
4417 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4418 return data;
3eafe507
SG		 4419
4420err_out:
4421 kfree(data);
4422 return NULL;
1da177e4
LT		 4423}
4424
4425static void rtl8169_rx_clear(struct rtl8169_private *tp)
4426{
07d3f51f 4427 unsigned int i;
1da177e4
LT		 4428
4429 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4430 if (tp->Rx_databuff[i]) {
4431 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4432 tp->RxDescArray + i);
4433 }
4434 }
4435}
4436
0ecbe1ca 4437static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4438{
0ecbe1ca
SG		 4439 desc->opts1 |= cpu_to_le32(RingEnd);
4440}
5b0384f4 4441
0ecbe1ca
SG		 4442static int rtl8169_rx_fill(struct rtl8169_private *tp)
4443{
4444 unsigned int i;
1da177e4 4445
0ecbe1ca
SG		 4446 for (i = 0; i < NUM_RX_DESC; i++) {
4447 void *data;
4ae47c2d 4448
6f0333b8 4449 if (tp->Rx_databuff[i])
1da177e4 4450 continue;
bcf0bf90 4451
0ecbe1ca 4452 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4453 if (!data) {
4454 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4455 goto err_out;
6f0333b8
ED		 4456 }
4457 tp->Rx_databuff[i] = data;
1da177e4 4458 }
1da177e4 4459
0ecbe1ca
SG		 4460 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4461 return 0;
4462
4463err_out:
4464 rtl8169_rx_clear(tp);
4465 return -ENOMEM;
1da177e4
LT		 4466}
4467
4468static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4469{
4470 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4471}
4472
4473static int rtl8169_init_ring(struct net_device *dev)
4474{
4475 struct rtl8169_private *tp = netdev_priv(dev);
4476
4477 rtl8169_init_ring_indexes(tp);
4478
4479 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4480 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4481
0ecbe1ca 4482 return rtl8169_rx_fill(tp);
1da177e4
LT		 4483}
4484
48addcc9 4485static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4486 struct TxDesc *desc)
4487{
4488 unsigned int len = tx_skb->len;
4489
48addcc9
SG		 4490 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4491
1da177e4
LT		 4492 desc->opts1 = 0x00;
4493 desc->opts2 = 0x00;
4494 desc->addr = 0x00;
4495 tx_skb->len = 0;
4496}
4497
3eafe507
SG		 4498static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4499 unsigned int n)
1da177e4
LT		 4500{
4501 unsigned int i;
4502
3eafe507
SG		 4503 for (i = 0; i < n; i++) {
4504 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4505 struct ring_info *tx_skb = tp->tx_skb + entry;
4506 unsigned int len = tx_skb->len;
4507
4508 if (len) {
4509 struct sk_buff *skb = tx_skb->skb;
4510
48addcc9 4511 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4512 tp->TxDescArray + entry);
4513 if (skb) {
cac4b22f 4514 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4515 dev_kfree_skb(skb);
4516 tx_skb->skb = NULL;
4517 }
1da177e4
LT		 4518 }
4519 }
3eafe507
SG		 4520}
4521
4522static void rtl8169_tx_clear(struct rtl8169_private *tp)
4523{
4524 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4525 tp->cur_tx = tp->dirty_tx = 0;
4526}
4527
c4028958 4528static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4529{
4530 struct rtl8169_private *tp = netdev_priv(dev);
4531
c4028958 4532 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4533 schedule_delayed_work(&tp->task, 4);
4534}
4535
4536static void rtl8169_wait_for_quiescence(struct net_device *dev)
4537{
4538 struct rtl8169_private *tp = netdev_priv(dev);
4539 void __iomem *ioaddr = tp->mmio_addr;
4540
4541 synchronize_irq(dev->irq);
4542
4543 /* Wait for any pending NAPI task to complete */
bea3348e 4544 napi_disable(&tp->napi);
1da177e4
LT		 4545
4546 rtl8169_irq_mask_and_ack(ioaddr);
4547
d1d08d12
DM		 4548 tp->intr_mask = 0xffff;
4549 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4550 napi_enable(&tp->napi);
1da177e4
LT		 4551}
4552
c4028958 4553static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4554{
c4028958
DH		 4555 struct rtl8169_private *tp =
4556 container_of(work, struct rtl8169_private, task.work);
4557 struct net_device *dev = tp->dev;
1da177e4
LT		 4558 int ret;
4559
eb2a021c
FR		 4560 rtnl_lock();
4561
4562 if (!netif_running(dev))
4563 goto out_unlock;
4564
4565 rtl8169_wait_for_quiescence(dev);
4566 rtl8169_close(dev);
1da177e4
LT		 4567
4568 ret = rtl8169_open(dev);
4569 if (unlikely(ret < 0)) {
bf82c189
JP		 4570 if (net_ratelimit())
4571 netif_err(tp, drv, dev,
4572 "reinit failure (status = %d). Rescheduling\n",
4573 ret);
1da177e4
LT		 4574 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4575 }
eb2a021c
FR		 4576
4577out_unlock:
4578 rtnl_unlock();
1da177e4
LT		 4579}
4580
c4028958 4581static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4582{
c4028958
DH		 4583 struct rtl8169_private *tp =
4584 container_of(work, struct rtl8169_private, task.work);
4585 struct net_device *dev = tp->dev;
1da177e4 4586
eb2a021c
FR		 4587 rtnl_lock();
4588
1da177e4 4589 if (!netif_running(dev))
eb2a021c 4590 goto out_unlock;
1da177e4
LT		 4591
4592 rtl8169_wait_for_quiescence(dev);
4593
bea3348e 4594 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4595 rtl8169_tx_clear(tp);
4596
4597 if (tp->dirty_rx == tp->cur_rx) {
4598 rtl8169_init_ring_indexes(tp);
07ce4064 4599 rtl_hw_start(dev);
1da177e4 4600 netif_wake_queue(dev);
cebf8cc7 4601 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4602 } else {
bf82c189
JP		 4603 if (net_ratelimit())
4604 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4605 rtl8169_schedule_work(dev, rtl8169_reset_task);
4606 }
eb2a021c
FR		 4607
4608out_unlock:
4609 rtnl_unlock();
1da177e4
LT		 4610}
4611
4612static void rtl8169_tx_timeout(struct net_device *dev)
4613{
4614 struct rtl8169_private *tp = netdev_priv(dev);
4615
e6de30d6 4616 rtl8169_hw_reset(tp);
1da177e4
LT		 4617
4618 /* Let's wait a bit while any (async) irq lands on */
4619 rtl8169_schedule_work(dev, rtl8169_reset_task);
4620}
4621
4622static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4623 u32 *opts)
1da177e4
LT		 4624{
4625 struct skb_shared_info *info = skb_shinfo(skb);
4626 unsigned int cur_frag, entry;
a6343afb 4627 struct TxDesc * uninitialized_var(txd);
48addcc9 4628 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4629
4630 entry = tp->cur_tx;
4631 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4632 skb_frag_t *frag = info->frags + cur_frag;
4633 dma_addr_t mapping;
4634 u32 status, len;
4635 void *addr;
4636
4637 entry = (entry + 1) % NUM_TX_DESC;
4638
4639 txd = tp->TxDescArray + entry;
4640 len = frag->size;
4641 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4642 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4643 if (unlikely(dma_mapping_error(d, mapping))) {
4644 if (net_ratelimit())
4645 netif_err(tp, drv, tp->dev,
4646 "Failed to map TX fragments DMA!\n");
3eafe507 4647 goto err_out;
d827d86b 4648 }
1da177e4
LT		 4649
4650 /* anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4651 status = opts[0] | len |
4652 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4653
4654 txd->opts1 = cpu_to_le32(status);
2b7b4318 4655 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4656 txd->addr = cpu_to_le64(mapping);
4657
4658 tp->tx_skb[entry].len = len;
4659 }
4660
4661 if (cur_frag) {
4662 tp->tx_skb[entry].skb = skb;
4663 txd->opts1 |= cpu_to_le32(LastFrag);
4664 }
4665
4666 return cur_frag;
3eafe507
SG		 4667
4668err_out:
4669 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4670 return -EIO;
1da177e4
LT		 4671}
4672
2b7b4318
FR		 4673static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4674 struct sk_buff *skb, u32 *opts)
1da177e4 4675{
2b7b4318 4676 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4677 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4678 int offset = info->opts_offset;
350fb32a 4679
2b7b4318
FR		 4680 if (mss) {
4681 opts[0] |= TD_LSO;
4682 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4683 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4684 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4685
4686 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4687 opts[offset] |= info->checksum.tcp;
1da177e4 4688 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4689 opts[offset] |= info->checksum.udp;
4690 else
4691 WARN_ON_ONCE(1);
1da177e4 4692 }
1da177e4
LT		 4693}
4694
61357325
SH		 4695static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4696 struct net_device *dev)
1da177e4
LT		 4697{
4698 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4699 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4700 struct TxDesc *txd = tp->TxDescArray + entry;
4701 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4702 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4703 dma_addr_t mapping;
4704 u32 status, len;
2b7b4318 4705 u32 opts[2];
3eafe507 4706 int frags;
5b0384f4 4707
1da177e4 4708 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4709 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4710 goto err_stop_0;
1da177e4
LT		 4711 }
4712
4713 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4714 goto err_stop_0;
4715
4716 len = skb_headlen(skb);
48addcc9 4717 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4718 if (unlikely(dma_mapping_error(d, mapping))) {
4719 if (net_ratelimit())
4720 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4721 goto err_dma_0;
d827d86b 4722 }
3eafe507
SG		 4723
4724 tp->tx_skb[entry].len = len;
4725 txd->addr = cpu_to_le64(mapping);
1da177e4 4726
2b7b4318
FR		 4727 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4728 opts[0] = DescOwn;
1da177e4 4729
2b7b4318
FR		 4730 rtl8169_tso_csum(tp, skb, opts);
4731
4732 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4733 if (frags < 0)
4734 goto err_dma_1;
4735 else if (frags)
2b7b4318 4736 opts[0] |= FirstFrag;
3eafe507 4737 else {
2b7b4318 4738 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4739 tp->tx_skb[entry].skb = skb;
4740 }
4741
2b7b4318
FR		 4742 txd->opts2 = cpu_to_le32(opts[1]);
4743
1da177e4
LT		 4744 wmb();
4745
4746 /* anti gcc 2.95.3 bugware (sic) */
2b7b4318 4747 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4748 txd->opts1 = cpu_to_le32(status);
4749
1da177e4
LT		 4750 tp->cur_tx += frags + 1;
4751
4c020a96 4752 wmb();
1da177e4 4753
275391a4 4754 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4755
4756 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4757 netif_stop_queue(dev);
4758 smp_rmb();
4759 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4760 netif_wake_queue(dev);
4761 }
4762
61357325 4763 return NETDEV_TX_OK;
1da177e4 4764
3eafe507 4765err_dma_1:
48addcc9 4766 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4767err_dma_0:
4768 dev_kfree_skb(skb);
4769 dev->stats.tx_dropped++;
4770 return NETDEV_TX_OK;
4771
4772err_stop_0:
1da177e4 4773 netif_stop_queue(dev);
cebf8cc7 4774 dev->stats.tx_dropped++;
61357325 4775 return NETDEV_TX_BUSY;
1da177e4
LT		 4776}
4777
4778static void rtl8169_pcierr_interrupt(struct net_device *dev)
4779{
4780 struct rtl8169_private *tp = netdev_priv(dev);
4781 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4782 u16 pci_status, pci_cmd;
4783
4784 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4785 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4786
bf82c189
JP		 4787 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4788 pci_cmd, pci_status);
1da177e4
LT		 4789
4790 /*
4791 * The recovery sequence below admits a very elaborated explanation:
4792 * - it seems to work;
d03902b8
FR		 4793 * - I did not see what else could be done;
4794 * - it makes iop3xx happy.
1da177e4
LT		 4795 *
4796 * Feel free to adjust to your needs.
4797 */
a27993f3 4798 if (pdev->broken_parity_status)
d03902b8
FR		 4799 pci_cmd &= ~PCI_COMMAND_PARITY;
4800 else
4801 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4802
4803 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4804
4805 pci_write_config_word(pdev, PCI_STATUS,
4806 pci_status & (PCI_STATUS_DETECTED_PARITY |
4807 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4808 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4809
4810 /* The infamous DAC f*ckup only happens at boot time */
4811 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4812 void __iomem *ioaddr = tp->mmio_addr;
4813
bf82c189 4814 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4815 tp->cp_cmd &= ~PCIDAC;
4816 RTL_W16(CPlusCmd, tp->cp_cmd);
4817 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4818 }
4819
e6de30d6 4820 rtl8169_hw_reset(tp);
d03902b8
FR		 4821
4822 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4823}
4824
07d3f51f
FR		 4825static void rtl8169_tx_interrupt(struct net_device *dev,
4826 struct rtl8169_private *tp,
4827 void __iomem *ioaddr)
1da177e4
LT		 4828{
4829 unsigned int dirty_tx, tx_left;
4830
1da177e4
LT		 4831 dirty_tx = tp->dirty_tx;
4832 smp_rmb();
4833 tx_left = tp->cur_tx - dirty_tx;
4834
4835 while (tx_left > 0) {
4836 unsigned int entry = dirty_tx % NUM_TX_DESC;
4837 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4838 u32 status;
4839
4840 rmb();
4841 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4842 if (status & DescOwn)
4843 break;
4844
48addcc9
SG		 4845 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4846 tp->TxDescArray + entry);
1da177e4 4847 if (status & LastFrag) {
cac4b22f
SG		 4848 dev->stats.tx_packets++;
4849 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4850 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4851 tx_skb->skb = NULL;
4852 }
4853 dirty_tx++;
4854 tx_left--;
4855 }
4856
4857 if (tp->dirty_tx != dirty_tx) {
4858 tp->dirty_tx = dirty_tx;
4859 smp_wmb();
4860 if (netif_queue_stopped(dev) &&
4861 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4862 netif_wake_queue(dev);
4863 }
d78ae2dc
FR		 4864 /*
4865 * 8168 hack: TxPoll requests are lost when the Tx packets are
4866 * too close. Let's kick an extra TxPoll request when a burst
4867 * of start_xmit activity is detected (if it is not detected,
4868 * it is slow enough). -- FR
4869 */
4870 smp_rmb();
4871 if (tp->cur_tx != dirty_tx)
4872 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4873 }
4874}
4875
126fa4b9
FR		 4876static inline int rtl8169_fragmented_frame(u32 status)
4877{
4878 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4879}
4880
adea1ac7 4881static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4882{
1da177e4
LT		 4883 u32 status = opts1 & RxProtoMask;
4884
4885 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4886 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4887 skb->ip_summed = CHECKSUM_UNNECESSARY;
4888 else
bc8acf2c 4889 skb_checksum_none_assert(skb);
1da177e4
LT		 4890}
4891
6f0333b8
ED		 4892static struct sk_buff *rtl8169_try_rx_copy(void *data,
4893 struct rtl8169_private *tp,
4894 int pkt_size,
4895 dma_addr_t addr)
1da177e4 4896{
b449655f 4897 struct sk_buff *skb;
48addcc9 4898 struct device *d = &tp->pci_dev->dev;
b449655f 4899
6f0333b8 4900 data = rtl8169_align(data);
48addcc9 4901 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4902 prefetch(data);
4903 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4904 if (skb)
4905 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4906 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4907
6f0333b8 4908 return skb;
1da177e4
LT		 4909}
4910
630b943c
ED		 4911/*
4912 * Warning : rtl8169_rx_interrupt() might be called :
4913 * 1) from NAPI (softirq) context
4914 * (polling = 1 : we should call netif_receive_skb())
4915 * 2) from process context (rtl8169_reset_task())
4916 * (polling = 0 : we must call netif_rx() instead)
4917 */
07d3f51f
FR		 4918static int rtl8169_rx_interrupt(struct net_device *dev,
4919 struct rtl8169_private *tp,
bea3348e 4920 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4921{
4922 unsigned int cur_rx, rx_left;
6f0333b8 4923 unsigned int count;
630b943c 4924 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4925
1da177e4
LT		 4926 cur_rx = tp->cur_rx;
4927 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4928 rx_left = min(rx_left, budget);
1da177e4 4929
4dcb7d33 4930 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4931 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4932 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4933 u32 status;
4934
4935 rmb();
126fa4b9 4936 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4937
4938 if (status & DescOwn)
4939 break;
4dcb7d33 4940 if (unlikely(status & RxRES)) {
bf82c189
JP		 4941 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4942 status);
cebf8cc7 4943 dev->stats.rx_errors++;
1da177e4 4944 if (status & (RxRWT | RxRUNT))
cebf8cc7 4945 dev->stats.rx_length_errors++;
1da177e4 4946 if (status & RxCRC)
cebf8cc7 4947 dev->stats.rx_crc_errors++;
9dccf611
FR		 4948 if (status & RxFOVF) {
4949 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4950 dev->stats.rx_fifo_errors++;
9dccf611 4951 }
6f0333b8 4952 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4953 } else {
6f0333b8 4954 struct sk_buff *skb;
b449655f 4955 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4956 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4957
126fa4b9
FR		 4958 /*
4959 * The driver does not support incoming fragmented
4960 * frames. They are seen as a symptom of over-mtu
4961 * sized frames.
4962 */
4963 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4964 dev->stats.rx_dropped++;
4965 dev->stats.rx_length_errors++;
6f0333b8 4966 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4967 continue;
126fa4b9
FR		 4968 }
4969
6f0333b8
ED		 4970 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4971 tp, pkt_size, addr);
4972 rtl8169_mark_to_asic(desc, rx_buf_sz);
4973 if (!skb) {
4974 dev->stats.rx_dropped++;
4975 continue;
1da177e4
LT		 4976 }
4977
adea1ac7 4978 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4979 skb_put(skb, pkt_size);
4980 skb->protocol = eth_type_trans(skb, dev);
4981
7a8fc77b
FR		 4982 rtl8169_rx_vlan_tag(desc, skb);
4983
4984 if (likely(polling))
4985 napi_gro_receive(&tp->napi, skb);
4986 else
4987 netif_rx(skb);
1da177e4 4988
cebf8cc7
FR		 4989 dev->stats.rx_bytes += pkt_size;
4990 dev->stats.rx_packets++;
1da177e4 4991 }
6dccd16b
FR		 4992
4993 /* Work around for AMD plateform. */
95e0918d 4994 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4995 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4996 desc->opts2 = 0;
4997 cur_rx++;
4998 }
1da177e4
LT		 4999 }
5000
5001 count = cur_rx - tp->cur_rx;
5002 tp->cur_rx = cur_rx;
5003
6f0333b8 5004 tp->dirty_rx += count;
1da177e4
LT		 5005
5006 return count;
5007}
5008
07d3f51f 5009static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5010{
07d3f51f 5011 struct net_device *dev = dev_instance;
1da177e4 5012 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5013 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5014 int handled = 0;
865c652d 5015 int status;
1da177e4 5016
f11a377b
DD		 5017 /* loop handling interrupts until we have no new ones or
5018 * we hit a invalid/hotplug case.
5019 */
865c652d 5020 status = RTL_R16(IntrStatus);
f11a377b
DD		 5021 while (status && status != 0xffff) {
5022 handled = 1;
1da177e4 5023
f11a377b
DD		 5024 /* Handle all of the error cases first. These will reset
5025 * the chip, so just exit the loop.
5026 */
5027 if (unlikely(!netif_running(dev))) {
5028 rtl8169_asic_down(ioaddr);
5029 break;
5030 }
1da177e4 5031
1519e57f
FR		 5032 if (unlikely(status & RxFIFOOver)) {
5033 switch (tp->mac_version) {
5034 /* Work around for rx fifo overflow */
5035 case RTL_GIGA_MAC_VER_11:
5036 case RTL_GIGA_MAC_VER_22:
5037 case RTL_GIGA_MAC_VER_26:
5038 netif_stop_queue(dev);
5039 rtl8169_tx_timeout(dev);
5040 goto done;
f60ac8e7
FR		 5041 /* Testers needed. */
5042 case RTL_GIGA_MAC_VER_17:
5043 case RTL_GIGA_MAC_VER_19:
5044 case RTL_GIGA_MAC_VER_20:
5045 case RTL_GIGA_MAC_VER_21:
5046 case RTL_GIGA_MAC_VER_23:
5047 case RTL_GIGA_MAC_VER_24:
5048 case RTL_GIGA_MAC_VER_27:
5049 case RTL_GIGA_MAC_VER_28:
4804b3b3 5050 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5051 /* Experimental science. Pktgen proof. */
5052 case RTL_GIGA_MAC_VER_12:
5053 case RTL_GIGA_MAC_VER_25:
5054 if (status == RxFIFOOver)
5055 goto done;
5056 break;
5057 default:
5058 break;
5059 }
f11a377b 5060 }
1da177e4 5061
f11a377b
DD		 5062 if (unlikely(status & SYSErr)) {
5063 rtl8169_pcierr_interrupt(dev);
5064 break;
5065 }
1da177e4 5066
f11a377b 5067 if (status & LinkChg)
e4fbce74 5068 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5069
f11a377b
DD		 5070 /* We need to see the lastest version of tp->intr_mask to
5071 * avoid ignoring an MSI interrupt and having to wait for
5072 * another event which may never come.
5073 */
5074 smp_rmb();
5075 if (status & tp->intr_mask & tp->napi_event) {
5076 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5077 tp->intr_mask = ~tp->napi_event;
5078
5079 if (likely(napi_schedule_prep(&tp->napi)))
5080 __napi_schedule(&tp->napi);
bf82c189
JP		 5081 else
5082 netif_info(tp, intr, dev,
5083 "interrupt %04x in poll\n", status);
f11a377b 5084 }
1da177e4 5085
f11a377b
DD		 5086 /* We only get a new MSI interrupt when all active irq
5087 * sources on the chip have been acknowledged. So, ack
5088 * everything we've seen and check if new sources have become
5089 * active to avoid blocking all interrupts from the chip.
5090 */
5091 RTL_W16(IntrStatus,
5092 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5093 status = RTL_R16(IntrStatus);
865c652d 5094 }
1519e57f 5095done:
1da177e4
LT		 5096 return IRQ_RETVAL(handled);
5097}
5098
bea3348e 5099static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5100{
bea3348e
SH		 5101 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5102 struct net_device *dev = tp->dev;
1da177e4 5103 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5104 int work_done;
1da177e4 5105
bea3348e 5106 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5107 rtl8169_tx_interrupt(dev, tp, ioaddr);
5108
bea3348e 5109 if (work_done < budget) {
288379f0 5110 napi_complete(napi);
f11a377b
DD		 5111
5112 /* We need for force the visibility of tp->intr_mask
5113 * for other CPUs, as we can loose an MSI interrupt
5114 * and potentially wait for a retransmit timeout if we don't.
5115 * The posted write to IntrMask is safe, as it will
5116 * eventually make it to the chip and we won't loose anything
5117 * until it does.
1da177e4 5118 */
f11a377b 5119 tp->intr_mask = 0xffff;
4c020a96 5120 wmb();
0e485150 5121 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5122 }
5123
bea3348e 5124 return work_done;
1da177e4 5125}
1da177e4 5126
523a6094
FR		 5127static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5128{
5129 struct rtl8169_private *tp = netdev_priv(dev);
5130
5131 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5132 return;
5133
5134 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5135 RTL_W32(RxMissed, 0);
5136}
5137
1da177e4
LT		 5138static void rtl8169_down(struct net_device *dev)
5139{
5140 struct rtl8169_private *tp = netdev_priv(dev);
5141 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 5142
5143 rtl8169_delete_timer(dev);
5144
5145 netif_stop_queue(dev);
5146
93dd79e8 5147 napi_disable(&tp->napi);
93dd79e8 5148
1da177e4
LT		 5149 spin_lock_irq(&tp->lock);
5150
5151 rtl8169_asic_down(ioaddr);
323bb685
SG		 5152 /*
5153 * At this point device interrupts can not be enabled in any function,
5154 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5155 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5156 */
523a6094 5157 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5158
5159 spin_unlock_irq(&tp->lock);
5160
5161 synchronize_irq(dev->irq);
5162
1da177e4 5163 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5164 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5165
1da177e4
LT		 5166 rtl8169_tx_clear(tp);
5167
5168 rtl8169_rx_clear(tp);
065c27c1 5169
5170 rtl_pll_power_down(tp);
1da177e4
LT		 5171}
5172
5173static int rtl8169_close(struct net_device *dev)
5174{
5175 struct rtl8169_private *tp = netdev_priv(dev);
5176 struct pci_dev *pdev = tp->pci_dev;
5177
e1759441
RW		 5178 pm_runtime_get_sync(&pdev->dev);
5179
355423d0
IV		 5180 /* update counters before going down */
5181 rtl8169_update_counters(dev);
5182
1da177e4
LT		 5183 rtl8169_down(dev);
5184
5185 free_irq(dev->irq, dev);
5186
82553bb6
SG		 5187 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5188 tp->RxPhyAddr);
5189 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5190 tp->TxPhyAddr);
1da177e4
LT		 5191 tp->TxDescArray = NULL;
5192 tp->RxDescArray = NULL;
5193
e1759441
RW		 5194 pm_runtime_put_sync(&pdev->dev);
5195
1da177e4
LT		 5196 return 0;
5197}
5198
07ce4064 5199static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5200{
5201 struct rtl8169_private *tp = netdev_priv(dev);
5202 void __iomem *ioaddr = tp->mmio_addr;
5203 unsigned long flags;
5204 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5205 int rx_mode;
1da177e4
LT		 5206 u32 tmp = 0;
5207
5208 if (dev->flags & IFF_PROMISC) {
5209 /* Unconditionally log net taps. */
bf82c189 5210 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5211 rx_mode =
5212 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5213 AcceptAllPhys;
5214 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5215 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5216 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5217 /* Too many to filter perfectly -- accept all multicasts. */
5218 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5219 mc_filter[1] = mc_filter[0] = 0xffffffff;
5220 } else {
22bedad3 5221 struct netdev_hw_addr *ha;
07d3f51f 5222
1da177e4
LT		 5223 rx_mode = AcceptBroadcast | AcceptMyPhys;
5224 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5225 netdev_for_each_mc_addr(ha, dev) {
5226 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5227 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5228 rx_mode |= AcceptMulticast;
5229 }
5230 }
5231
5232 spin_lock_irqsave(&tp->lock, flags);
5233
5234 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5235 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5236
f887cce8 5237 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5238 u32 data = mc_filter[0];
5239
5240 mc_filter[0] = swab32(mc_filter[1]);
5241 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5242 }
5243
1da177e4 5244 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5245 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5246
57a9f236
FR		 5247 RTL_W32(RxConfig, tmp);
5248
1da177e4
LT		 5249 spin_unlock_irqrestore(&tp->lock, flags);
5250}
5251
5252/**
5253 * rtl8169_get_stats - Get rtl8169 read/write statistics
5254 * @dev: The Ethernet Device to get statistics for
5255 *
5256 * Get TX/RX statistics for rtl8169
5257 */
5258static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5259{
5260 struct rtl8169_private *tp = netdev_priv(dev);
5261 void __iomem *ioaddr = tp->mmio_addr;
5262 unsigned long flags;
5263
5264 if (netif_running(dev)) {
5265 spin_lock_irqsave(&tp->lock, flags);
523a6094 5266 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5267 spin_unlock_irqrestore(&tp->lock, flags);
5268 }
5b0384f4 5269
cebf8cc7 5270 return &dev->stats;
1da177e4
LT		 5271}
5272
861ab440 5273static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5274{
065c27c1 5275 struct rtl8169_private *tp = netdev_priv(dev);
5276
5d06a99f 5277 if (!netif_running(dev))
861ab440 5278 return;
5d06a99f 5279
065c27c1 5280 rtl_pll_power_down(tp);
5281
5d06a99f
FR		 5282 netif_device_detach(dev);
5283 netif_stop_queue(dev);
861ab440
RW		 5284}
5285
5286#ifdef CONFIG_PM
5287
5288static int rtl8169_suspend(struct device *device)
5289{
5290 struct pci_dev *pdev = to_pci_dev(device);
5291 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5292
861ab440 5293 rtl8169_net_suspend(dev);
1371fa6d 5294
5d06a99f
FR		 5295 return 0;
5296}
5297
e1759441
RW		 5298static void __rtl8169_resume(struct net_device *dev)
5299{
065c27c1 5300 struct rtl8169_private *tp = netdev_priv(dev);
5301
e1759441 5302 netif_device_attach(dev);
065c27c1 5303
5304 rtl_pll_power_up(tp);
5305
e1759441
RW		 5306 rtl8169_schedule_work(dev, rtl8169_reset_task);
5307}
5308
861ab440 5309static int rtl8169_resume(struct device *device)
5d06a99f 5310{
861ab440 5311 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5312 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5313 struct rtl8169_private *tp = netdev_priv(dev);
5314
5315 rtl8169_init_phy(dev, tp);
5d06a99f 5316
e1759441
RW		 5317 if (netif_running(dev))
5318 __rtl8169_resume(dev);
5d06a99f 5319
e1759441
RW		 5320 return 0;
5321}
5322
5323static int rtl8169_runtime_suspend(struct device *device)
5324{
5325 struct pci_dev *pdev = to_pci_dev(device);
5326 struct net_device *dev = pci_get_drvdata(pdev);
5327 struct rtl8169_private *tp = netdev_priv(dev);
5328
5329 if (!tp->TxDescArray)
5330 return 0;
5331
5332 spin_lock_irq(&tp->lock);
5333 tp->saved_wolopts = __rtl8169_get_wol(tp);
5334 __rtl8169_set_wol(tp, WAKE_ANY);
5335 spin_unlock_irq(&tp->lock);
5336
5337 rtl8169_net_suspend(dev);
5338
5339 return 0;
5340}
5341
5342static int rtl8169_runtime_resume(struct device *device)
5343{
5344 struct pci_dev *pdev = to_pci_dev(device);
5345 struct net_device *dev = pci_get_drvdata(pdev);
5346 struct rtl8169_private *tp = netdev_priv(dev);
5347
5348 if (!tp->TxDescArray)
5349 return 0;
5350
5351 spin_lock_irq(&tp->lock);
5352 __rtl8169_set_wol(tp, tp->saved_wolopts);
5353 tp->saved_wolopts = 0;
5354 spin_unlock_irq(&tp->lock);
5355
fccec10b
SG		 5356 rtl8169_init_phy(dev, tp);
5357
e1759441 5358 __rtl8169_resume(dev);
5d06a99f 5359
5d06a99f
FR		 5360 return 0;
5361}
5362
e1759441
RW		 5363static int rtl8169_runtime_idle(struct device *device)
5364{
5365 struct pci_dev *pdev = to_pci_dev(device);
5366 struct net_device *dev = pci_get_drvdata(pdev);
5367 struct rtl8169_private *tp = netdev_priv(dev);
5368
e4fbce74 5369 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5370}
5371
47145210 5372static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 5373 .suspend = rtl8169_suspend,
5374 .resume = rtl8169_resume,
5375 .freeze = rtl8169_suspend,
5376 .thaw = rtl8169_resume,
5377 .poweroff = rtl8169_suspend,
5378 .restore = rtl8169_resume,
e1759441
RW		 5379 .runtime_suspend = rtl8169_runtime_suspend,
5380 .runtime_resume = rtl8169_runtime_resume,
5381 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5382};
5383
5384#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5385
5386#else /* !CONFIG_PM */
5387
5388#define RTL8169_PM_OPS NULL
5389
5390#endif /* !CONFIG_PM */
5391
1765f95d
FR		 5392static void rtl_shutdown(struct pci_dev *pdev)
5393{
861ab440 5394 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5395 struct rtl8169_private *tp = netdev_priv(dev);
5396 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5397
5398 rtl8169_net_suspend(dev);
1765f95d 5399
cc098dc7
IV		 5400 /* restore original MAC address */
5401 rtl_rar_set(tp, dev->perm_addr);
5402
4bb3f522 5403 spin_lock_irq(&tp->lock);
5404
5405 rtl8169_asic_down(ioaddr);
5406
5407 spin_unlock_irq(&tp->lock);
5408
861ab440 5409 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5410 /* WoL fails with some 8168 when the receiver is disabled. */
5411 if (tp->features & RTL_FEATURE_WOL) {
5412 pci_clear_master(pdev);
5413
5414 RTL_W8(ChipCmd, CmdRxEnb);
5415 /* PCI commit */
5416 RTL_R8(ChipCmd);
5417 }
5418
861ab440
RW		 5419 pci_wake_from_d3(pdev, true);
5420 pci_set_power_state(pdev, PCI_D3hot);
5421 }
5422}
5d06a99f 5423
1da177e4
LT		 5424static struct pci_driver rtl8169_pci_driver = {
5425 .name = MODULENAME,
5426 .id_table = rtl8169_pci_tbl,
5427 .probe = rtl8169_init_one,
5428 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5429 .shutdown = rtl_shutdown,
861ab440 5430 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5431};
5432
07d3f51f 5433static int __init rtl8169_init_module(void)
1da177e4 5434{
29917620 5435 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5436}
5437
07d3f51f 5438static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5439{
5440 pci_unregister_driver(&rtl8169_pci_driver);
5441}
5442
5443module_init(rtl8169_init_module);
5444module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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