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r8169: provide some firmware information via ethtool.
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
1da177e4 29
99f252b0 30#include <asm/system.h>
1da177e4
LT		 31#include <asm/io.h>
32#include <asm/irq.h>
33
865c652d 34#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 35#define MODULENAME "r8169"
36#define PFX MODULENAME ": "
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 42#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 43
1da177e4
LT		 44#ifdef RTL8169_DEBUG
45#define assert(expr) \
5b0384f4
FR		 46 if (!(expr)) { \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 48 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 49 }
06fa7358
JP		 50#define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 52#else
53#define assert(expr) do {} while (0)
54#define dprintk(fmt, args...) do {} while (0)
55#endif /* RTL8169_DEBUG */
56
b57b7e5a 57#define R8169_MSG_DEFAULT \
f0e837d9 58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 59
1da177e4
LT		 60#define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 65static const int multicast_filter_limit = 32;
1da177e4
LT		 66
67/* MAC address length */
68#define MAC_ADDR_LEN 6
69
9c14ceaf 70#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 71#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
f21b75e9 101 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 102 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 107 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 108 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 112 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 113 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 121 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 122 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 123 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 124 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 125 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 126 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 128 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
5a5e4443
HW		 130 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
4804b3b3 132 RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
01dc7fec 133 RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134 RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
1da177e4
LT		 135};
136
2b7b4318
FR		 137enum rtl_tx_desc_version {
138 RTL_TD_0 = 0,
139 RTL_TD_1 = 1,
140};
141
142#define _R(NAME,MAC,TD) \
143 { .name = NAME, .mac_version = MAC, .txd_version = TD }
1da177e4 144
3c6bee1d 145static const struct {
1da177e4
LT		 146 const char *name;
147 u8 mac_version;
2b7b4318 148 enum rtl_tx_desc_version txd_version;
1da177e4 149} rtl_chip_info[] = {
2b7b4318
FR		 150 _R("RTL8169", RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151 _R("RTL8169s", RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152 _R("RTL8110s", RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156 _R("RTL8102e", RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157 _R("RTL8102e", RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158 _R("RTL8102e", RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159 _R("RTL8101e", RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162 _R("RTL8101e", RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163 _R("RTL8100e", RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164 _R("RTL8100e", RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166 _R("RTL8101e", RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178 _R("RTL8105e", RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179 _R("RTL8105e", RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, RTL_TD_1) // PCI-E
1da177e4
LT		 183};
184#undef _R
185
953a12cc
FR		 186static const struct rtl_firmware_info {
187 int mac_version;
188 const char *fw_name;
189} rtl_firmware_infos[] = {
190 { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
191 { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
192 { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
2bd93d7a 193 { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
15ecd039
FR		 194 { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_1 },
195 { .mac_version = RTL_GIGA_MAC_VER_33, .fw_name = FIRMWARE_8168E_2 }
953a12cc
FR		 196};
197
bcf0bf90
FR		 198enum cfg_version {
199 RTL_CFG_0 = 0x00,
200 RTL_CFG_1,
201 RTL_CFG_2
202};
203
07ce4064
FR		 204static void rtl_hw_start_8169(struct net_device *);
205static void rtl_hw_start_8168(struct net_device *);
206static void rtl_hw_start_8101(struct net_device *);
207
a3aa1884 208static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 209 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
214 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 215 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 216 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
217 { PCI_VENDOR_ID_LINKSYS, 0x1032,
218 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 219 { 0x0001, 0x8168,
220 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 221 {0,},
222};
223
224MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
6f0333b8 226static int rx_buf_sz = 16383;
4300e8c7 227static int use_dac;
b57b7e5a
SH		 228static struct {
229 u32 msg_enable;
230} debug = { -1 };
1da177e4 231
07d3f51f
FR		 232enum rtl_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
773d2021 234 MAC4 = 4,
07d3f51f
FR		 235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3c,
247 IntrStatus = 0x3e,
248 TxConfig = 0x40,
249 RxConfig = 0x44,
2b7b4318
FR		 250
251#define RTL_RX_CONFIG_MASK 0xff7e1880u
252
07d3f51f
FR		 253 RxMissed = 0x4c,
254 Cfg9346 = 0x50,
255 Config0 = 0x51,
256 Config1 = 0x52,
257 Config2 = 0x53,
258 Config3 = 0x54,
259 Config4 = 0x55,
260 Config5 = 0x56,
261 MultiIntr = 0x5c,
262 PHYAR = 0x60,
07d3f51f
FR		 263 PHYstatus = 0x6c,
264 RxMaxSize = 0xda,
265 CPlusCmd = 0xe0,
266 IntrMitigate = 0xe2,
267 RxDescAddrLow = 0xe4,
268 RxDescAddrHigh = 0xe8,
f0298f81 269 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
270
271#define NoEarlyTx 0x3f /* Max value : no early transmit. */
272
273 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
274
275#define TxPacketMax (8064 >> 7)
276
07d3f51f
FR		 277 FuncEvent = 0xf0,
278 FuncEventMask = 0xf4,
279 FuncPresetState = 0xf8,
280 FuncForceEvent = 0xfc,
1da177e4
LT		 281};
282
f162a5d1
FR		 283enum rtl8110_registers {
284 TBICSR = 0x64,
285 TBI_ANAR = 0x68,
286 TBI_LPAR = 0x6a,
287};
288
289enum rtl8168_8101_registers {
290 CSIDR = 0x64,
291 CSIAR = 0x68,
292#define CSIAR_FLAG 0x80000000
293#define CSIAR_WRITE_CMD 0x80000000
294#define CSIAR_BYTE_ENABLE 0x0f
295#define CSIAR_BYTE_ENABLE_SHIFT 12
296#define CSIAR_ADDR_MASK 0x0fff
065c27c1 297 PMCH = 0x6f,
f162a5d1
FR		 298 EPHYAR = 0x80,
299#define EPHYAR_FLAG 0x80000000
300#define EPHYAR_WRITE_CMD 0x80000000
301#define EPHYAR_REG_MASK 0x1f
302#define EPHYAR_REG_SHIFT 16
303#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 304 DLLPR = 0xd0,
305#define PM_SWITCH (1 << 6)
f162a5d1
FR		 306 DBG_REG = 0xd1,
307#define FIX_NAK_1 (1 << 4)
308#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 309 TWSI = 0xd2,
310 MCU = 0xd3,
311#define EN_NDP (1 << 3)
312#define EN_OOB_RESET (1 << 2)
daf9df6d 313 EFUSEAR = 0xdc,
314#define EFUSEAR_FLAG 0x80000000
315#define EFUSEAR_WRITE_CMD 0x80000000
316#define EFUSEAR_READ_CMD 0x00000000
317#define EFUSEAR_REG_MASK 0x03ff
318#define EFUSEAR_REG_SHIFT 8
319#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 320};
321
c0e45c1c 322enum rtl8168_registers {
b646d900 323 ERIDR = 0x70,
324 ERIAR = 0x74,
325#define ERIAR_FLAG 0x80000000
326#define ERIAR_WRITE_CMD 0x80000000
327#define ERIAR_READ_CMD 0x00000000
328#define ERIAR_ADDR_BYTE_ALIGN 4
329#define ERIAR_EXGMAC 0
330#define ERIAR_MSIX 1
331#define ERIAR_ASF 2
332#define ERIAR_TYPE_SHIFT 16
333#define ERIAR_BYTEEN 0x0f
334#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 335 EPHY_RXER_NUM = 0x7c,
336 OCPDR = 0xb0, /* OCP GPHY access */
337#define OCPDR_WRITE_CMD 0x80000000
338#define OCPDR_READ_CMD 0x00000000
339#define OCPDR_REG_MASK 0x7f
340#define OCPDR_GPHY_REG_SHIFT 16
341#define OCPDR_DATA_MASK 0xffff
342 OCPAR = 0xb4,
343#define OCPAR_FLAG 0x80000000
344#define OCPAR_GPHY_WRITE_CMD 0x8000f060
345#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 346 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
347 MISC = 0xf0, /* 8168e only. */
cecb5fd7 348#define TXPLA_RST (1 << 29)
c0e45c1c 349};
350
07d3f51f 351enum rtl_register_content {
1da177e4 352 /* InterruptStatusBits */
07d3f51f
FR		 353 SYSErr = 0x8000,
354 PCSTimeout = 0x4000,
355 SWInt = 0x0100,
356 TxDescUnavail = 0x0080,
357 RxFIFOOver = 0x0040,
358 LinkChg = 0x0020,
359 RxOverflow = 0x0010,
360 TxErr = 0x0008,
361 TxOK = 0x0004,
362 RxErr = 0x0002,
363 RxOK = 0x0001,
1da177e4
LT		 364
365 /* RxStatusDesc */
9dccf611
FR		 366 RxFOVF = (1 << 23),
367 RxRWT = (1 << 22),
368 RxRES = (1 << 21),
369 RxRUNT = (1 << 20),
370 RxCRC = (1 << 19),
1da177e4
LT		 371
372 /* ChipCmdBits */
07d3f51f
FR		 373 CmdReset = 0x10,
374 CmdRxEnb = 0x08,
375 CmdTxEnb = 0x04,
376 RxBufEmpty = 0x01,
1da177e4 377
275391a4
FR		 378 /* TXPoll register p.5 */
379 HPQ = 0x80, /* Poll cmd on the high prio queue */
380 NPQ = 0x40, /* Poll cmd on the low prio queue */
381 FSWInt = 0x01, /* Forced software interrupt */
382
1da177e4 383 /* Cfg9346Bits */
07d3f51f
FR		 384 Cfg9346_Lock = 0x00,
385 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 386
387 /* rx_mode_bits */
07d3f51f
FR		 388 AcceptErr = 0x20,
389 AcceptRunt = 0x10,
390 AcceptBroadcast = 0x08,
391 AcceptMulticast = 0x04,
392 AcceptMyPhys = 0x02,
393 AcceptAllPhys = 0x01,
1da177e4
LT		 394
395 /* RxConfigBits */
07d3f51f
FR		 396 RxCfgFIFOShift = 13,
397 RxCfgDMAShift = 8,
1da177e4
LT		 398
399 /* TxConfigBits */
400 TxInterFrameGapShift = 24,
401 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
402
5d06a99f 403 /* Config1 register p.24 */
f162a5d1
FR		 404 LEDS1 = (1 << 7),
405 LEDS0 = (1 << 6),
fbac58fc 406 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 407 Speed_down = (1 << 4),
408 MEMMAP = (1 << 3),
409 IOMAP = (1 << 2),
410 VPD = (1 << 1),
5d06a99f
FR		 411 PMEnable = (1 << 0), /* Power Management Enable */
412
6dccd16b
FR		 413 /* Config2 register p. 25 */
414 PCI_Clock_66MHz = 0x01,
415 PCI_Clock_33MHz = 0x00,
416
61a4dcc2
FR		 417 /* Config3 register p.25 */
418 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
419 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 420 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 421
5d06a99f 422 /* Config5 register p.27 */
61a4dcc2
FR		 423 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
424 MWF = (1 << 5), /* Accept Multicast wakeup frame */
425 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 426 Spi_en = (1 << 3),
61a4dcc2 427 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 428 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
429
1da177e4
LT		 430 /* TBICSR p.28 */
431 TBIReset = 0x80000000,
432 TBILoopback = 0x40000000,
433 TBINwEnable = 0x20000000,
434 TBINwRestart = 0x10000000,
435 TBILinkOk = 0x02000000,
436 TBINwComplete = 0x01000000,
437
438 /* CPlusCmd p.31 */
f162a5d1
FR		 439 EnableBist = (1 << 15), // 8168 8101
440 Mac_dbgo_oe = (1 << 14), // 8168 8101
441 Normal_mode = (1 << 13), // unused
442 Force_half_dup = (1 << 12), // 8168 8101
443 Force_rxflow_en = (1 << 11), // 8168 8101
444 Force_txflow_en = (1 << 10), // 8168 8101
445 Cxpl_dbg_sel = (1 << 9), // 8168 8101
446 ASF = (1 << 8), // 8168 8101
447 PktCntrDisable = (1 << 7), // 8168 8101
448 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 449 RxVlan = (1 << 6),
450 RxChkSum = (1 << 5),
451 PCIDAC = (1 << 4),
452 PCIMulRW = (1 << 3),
0e485150
FR		 453 INTT_0 = 0x0000, // 8168
454 INTT_1 = 0x0001, // 8168
455 INTT_2 = 0x0002, // 8168
456 INTT_3 = 0x0003, // 8168
1da177e4
LT		 457
458 /* rtl8169_PHYstatus */
07d3f51f
FR		 459 TBI_Enable = 0x80,
460 TxFlowCtrl = 0x40,
461 RxFlowCtrl = 0x20,
462 _1000bpsF = 0x10,
463 _100bps = 0x08,
464 _10bps = 0x04,
465 LinkStatus = 0x02,
466 FullDup = 0x01,
1da177e4 467
1da177e4 468 /* _TBICSRBit */
07d3f51f 469 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 470
471 /* DumpCounterCommand */
07d3f51f 472 CounterDump = 0x8,
1da177e4
LT		 473};
474
2b7b4318
FR		 475enum rtl_desc_bit {
476 /* First doubleword. */
1da177e4
LT		 477 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
478 RingEnd = (1 << 30), /* End of descriptor ring */
479 FirstFrag = (1 << 29), /* First segment of a packet */
480 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 481};
482
483/* Generic case. */
484enum rtl_tx_desc_bit {
485 /* First doubleword. */
486 TD_LSO = (1 << 27), /* Large Send Offload */
487#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 488
2b7b4318
FR		 489 /* Second doubleword. */
490 TxVlanTag = (1 << 17), /* Add VLAN tag */
491};
492
493/* 8169, 8168b and 810x except 8102e. */
494enum rtl_tx_desc_bit_0 {
495 /* First doubleword. */
496#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
497 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
498 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
499 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
500};
501
502/* 8102e, 8168c and beyond. */
503enum rtl_tx_desc_bit_1 {
504 /* Second doubleword. */
505#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
506 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
509};
1da177e4 510
2b7b4318
FR		 511static const struct rtl_tx_desc_info {
512 struct {
513 u32 udp;
514 u32 tcp;
515 } checksum;
516 u16 mss_shift;
517 u16 opts_offset;
518} tx_desc_info [] = {
519 [RTL_TD_0] = {
520 .checksum = {
521 .udp = TD0_IP_CS | TD0_UDP_CS,
522 .tcp = TD0_IP_CS | TD0_TCP_CS
523 },
524 .mss_shift = TD0_MSS_SHIFT,
525 .opts_offset = 0
526 },
527 [RTL_TD_1] = {
528 .checksum = {
529 .udp = TD1_IP_CS | TD1_UDP_CS,
530 .tcp = TD1_IP_CS | TD1_TCP_CS
531 },
532 .mss_shift = TD1_MSS_SHIFT,
533 .opts_offset = 1
534 }
535};
536
537enum rtl_rx_desc_bit {
1da177e4
LT		 538 /* Rx private */
539 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
540 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
541
542#define RxProtoUDP (PID1)
543#define RxProtoTCP (PID0)
544#define RxProtoIP (PID1 | PID0)
545#define RxProtoMask RxProtoIP
546
547 IPFail = (1 << 16), /* IP checksum failed */
548 UDPFail = (1 << 15), /* UDP/IP checksum failed */
549 TCPFail = (1 << 14), /* TCP/IP checksum failed */
550 RxVlanTag = (1 << 16), /* VLAN tag available */
551};
552
553#define RsvdMask 0x3fffc000
554
555struct TxDesc {
6cccd6e7
REB		 556 __le32 opts1;
557 __le32 opts2;
558 __le64 addr;
1da177e4
LT		 559};
560
561struct RxDesc {
6cccd6e7
REB		 562 __le32 opts1;
563 __le32 opts2;
564 __le64 addr;
1da177e4
LT		 565};
566
567struct ring_info {
568 struct sk_buff *skb;
569 u32 len;
570 u8 __pad[sizeof(void *) - sizeof(u32)];
571};
572
f23e7fda 573enum features {
ccdffb9a
FR		 574 RTL_FEATURE_WOL = (1 << 0),
575 RTL_FEATURE_MSI = (1 << 1),
576 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 577};
578
355423d0
IV		 579struct rtl8169_counters {
580 __le64 tx_packets;
581 __le64 rx_packets;
582 __le64 tx_errors;
583 __le32 rx_errors;
584 __le16 rx_missed;
585 __le16 align_errors;
586 __le32 tx_one_collision;
587 __le32 tx_multi_collision;
588 __le64 rx_unicast;
589 __le64 rx_broadcast;
590 __le32 rx_multicast;
591 __le16 tx_aborted;
592 __le16 tx_underun;
593};
594
1da177e4
LT		 595struct rtl8169_private {
596 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 597 struct pci_dev *pci_dev;
c4028958 598 struct net_device *dev;
bea3348e 599 struct napi_struct napi;
cecb5fd7 600 spinlock_t lock;
b57b7e5a 601 u32 msg_enable;
2b7b4318
FR		 602 u16 txd_version;
603 u16 mac_version;
1da177e4
LT		 604 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
605 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
606 u32 dirty_rx;
607 u32 dirty_tx;
608 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
609 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
610 dma_addr_t TxPhyAddr;
611 dma_addr_t RxPhyAddr;
6f0333b8 612 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 613 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 614 struct timer_list timer;
615 u16 cp_cmd;
0e485150
FR		 616 u16 intr_event;
617 u16 napi_event;
1da177e4 618 u16 intr_mask;
c0e45c1c 619
620 struct mdio_ops {
621 void (*write)(void __iomem *, int, int);
622 int (*read)(void __iomem *, int);
623 } mdio_ops;
624
065c27c1 625 struct pll_power_ops {
626 void (*down)(struct rtl8169_private *);
627 void (*up)(struct rtl8169_private *);
628 } pll_power_ops;
629
54405cde 630 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 631 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 632 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 633 void (*hw_start)(struct net_device *);
4da19633 634 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 635 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 636 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 637 int pcie_cap;
c4028958 638 struct delayed_work task;
f23e7fda 639 unsigned features;
ccdffb9a
FR		 640
641 struct mii_if_info mii;
355423d0 642 struct rtl8169_counters counters;
e1759441 643 u32 saved_wolopts;
f1e02ed1 644
645 const struct firmware *fw;
953a12cc 646#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 647};
648
979b6c13 649MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 650MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 651module_param(use_dac, int, 0);
4300e8c7 652MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 653module_param_named(debug, debug.msg_enable, int, 0);
654MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 655MODULE_LICENSE("GPL");
656MODULE_VERSION(RTL8169_VERSION);
bca03d5f 657MODULE_FIRMWARE(FIRMWARE_8168D_1);
658MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 659MODULE_FIRMWARE(FIRMWARE_8168E_1);
660MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 661MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 662
663static int rtl8169_open(struct net_device *dev);
61357325
SH		 664static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
665 struct net_device *dev);
7d12e780 666static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 667static int rtl8169_init_ring(struct net_device *dev);
07ce4064 668static void rtl_hw_start(struct net_device *dev);
1da177e4 669static int rtl8169_close(struct net_device *dev);
07ce4064 670static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 671static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 672static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 673static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 674 void __iomem *, u32 budget);
4dcb7d33 675static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 676static void rtl8169_down(struct net_device *dev);
99f252b0 677static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 678static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 679
1da177e4 680static const unsigned int rtl8169_rx_config =
5b0384f4 681 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 682
b646d900 683static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
684{
685 void __iomem *ioaddr = tp->mmio_addr;
686 int i;
687
688 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
689 for (i = 0; i < 20; i++) {
690 udelay(100);
691 if (RTL_R32(OCPAR) & OCPAR_FLAG)
692 break;
693 }
694 return RTL_R32(OCPDR);
695}
696
697static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
698{
699 void __iomem *ioaddr = tp->mmio_addr;
700 int i;
701
702 RTL_W32(OCPDR, data);
703 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
704 for (i = 0; i < 20; i++) {
705 udelay(100);
706 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
707 break;
708 }
709}
710
fac5b3ca 711static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 712{
fac5b3ca 713 void __iomem *ioaddr = tp->mmio_addr;
b646d900 714 int i;
715
716 RTL_W8(ERIDR, cmd);
717 RTL_W32(ERIAR, 0x800010e8);
718 msleep(2);
719 for (i = 0; i < 5; i++) {
720 udelay(100);
721 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
722 break;
723 }
724
fac5b3ca 725 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 726}
727
728#define OOB_CMD_RESET 0x00
729#define OOB_CMD_DRIVER_START 0x05
730#define OOB_CMD_DRIVER_STOP 0x06
731
cecb5fd7
FR		 732static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
733{
734 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
735}
736
b646d900 737static void rtl8168_driver_start(struct rtl8169_private *tp)
738{
cecb5fd7 739 u16 reg;
b646d900 740 int i;
741
742 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
743
cecb5fd7 744 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 745
b646d900 746 for (i = 0; i < 10; i++) {
747 msleep(10);
4804b3b3 748 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 749 break;
750 }
751}
752
753static void rtl8168_driver_stop(struct rtl8169_private *tp)
754{
cecb5fd7 755 u16 reg;
b646d900 756 int i;
757
758 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
759
cecb5fd7 760 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 761
b646d900 762 for (i = 0; i < 10; i++) {
763 msleep(10);
4804b3b3 764 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 765 break;
766 }
767}
768
4804b3b3 769static int r8168dp_check_dash(struct rtl8169_private *tp)
770{
cecb5fd7 771 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 772
cecb5fd7 773 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 774}
b646d900 775
4da19633 776static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 777{
778 int i;
779
a6baf3af 780 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 781
2371408c 782 for (i = 20; i > 0; i--) {
07d3f51f
FR		 783 /*
784 * Check if the RTL8169 has completed writing to the specified
785 * MII register.
786 */
5b0384f4 787 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 788 break;
2371408c 789 udelay(25);
1da177e4 790 }
024a07ba 791 /*
81a95f04
TT		 792 * According to hardware specs a 20us delay is required after write
793 * complete indication, but before sending next command.
024a07ba 794 */
81a95f04 795 udelay(20);
1da177e4
LT		 796}
797
4da19633 798static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 799{
800 int i, value = -1;
801
a6baf3af 802 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 803
2371408c 804 for (i = 20; i > 0; i--) {
07d3f51f
FR		 805 /*
806 * Check if the RTL8169 has completed retrieving data from
807 * the specified MII register.
808 */
1da177e4 809 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 810 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 811 break;
812 }
2371408c 813 udelay(25);
1da177e4 814 }
81a95f04
TT		 815 /*
816 * According to hardware specs a 20us delay is required after read
817 * complete indication, but before sending next command.
818 */
819 udelay(20);
820
1da177e4
LT		 821 return value;
822}
823
c0e45c1c 824static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
825{
826 int i;
827
828 RTL_W32(OCPDR, data |
829 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
830 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
831 RTL_W32(EPHY_RXER_NUM, 0);
832
833 for (i = 0; i < 100; i++) {
834 mdelay(1);
835 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
836 break;
837 }
838}
839
840static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
841{
842 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
843 (value & OCPDR_DATA_MASK));
844}
845
846static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
847{
848 int i;
849
850 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
851
852 mdelay(1);
853 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
854 RTL_W32(EPHY_RXER_NUM, 0);
855
856 for (i = 0; i < 100; i++) {
857 mdelay(1);
858 if (RTL_R32(OCPAR) & OCPAR_FLAG)
859 break;
860 }
861
862 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
863}
864
e6de30d6 865#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
866
867static void r8168dp_2_mdio_start(void __iomem *ioaddr)
868{
869 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
870}
871
872static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
873{
874 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
875}
876
877static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
878{
879 r8168dp_2_mdio_start(ioaddr);
880
881 r8169_mdio_write(ioaddr, reg_addr, value);
882
883 r8168dp_2_mdio_stop(ioaddr);
884}
885
886static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
887{
888 int value;
889
890 r8168dp_2_mdio_start(ioaddr);
891
892 value = r8169_mdio_read(ioaddr, reg_addr);
893
894 r8168dp_2_mdio_stop(ioaddr);
895
896 return value;
897}
898
4da19633 899static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 900{
c0e45c1c 901 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 902}
903
4da19633 904static int rtl_readphy(struct rtl8169_private *tp, int location)
905{
c0e45c1c 906 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 907}
908
909static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
910{
911 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
912}
913
914static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 915{
916 int val;
917
4da19633 918 val = rtl_readphy(tp, reg_addr);
919 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 920}
921
ccdffb9a
FR		 922static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
923 int val)
924{
925 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 926
4da19633 927 rtl_writephy(tp, location, val);
ccdffb9a
FR		 928}
929
930static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
931{
932 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 933
4da19633 934 return rtl_readphy(tp, location);
ccdffb9a
FR		 935}
936
dacf8154
FR		 937static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
938{
939 unsigned int i;
940
941 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
942 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
943
944 for (i = 0; i < 100; i++) {
945 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
946 break;
947 udelay(10);
948 }
949}
950
951static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
952{
953 u16 value = 0xffff;
954 unsigned int i;
955
956 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
957
958 for (i = 0; i < 100; i++) {
959 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
960 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
961 break;
962 }
963 udelay(10);
964 }
965
966 return value;
967}
968
969static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
970{
971 unsigned int i;
972
973 RTL_W32(CSIDR, value);
974 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
975 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
976
977 for (i = 0; i < 100; i++) {
978 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
979 break;
980 udelay(10);
981 }
982}
983
984static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
985{
986 u32 value = ~0x00;
987 unsigned int i;
988
989 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
990 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
991
992 for (i = 0; i < 100; i++) {
993 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
994 value = RTL_R32(CSIDR);
995 break;
996 }
997 udelay(10);
998 }
999
1000 return value;
1001}
1002
daf9df6d 1003static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1004{
1005 u8 value = 0xff;
1006 unsigned int i;
1007
1008 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1009
1010 for (i = 0; i < 300; i++) {
1011 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1012 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1013 break;
1014 }
1015 udelay(100);
1016 }
1017
1018 return value;
1019}
1020
1da177e4
LT		 1021static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1022{
1023 RTL_W16(IntrMask, 0x0000);
1024
1025 RTL_W16(IntrStatus, 0xffff);
1026}
1027
1028static void rtl8169_asic_down(void __iomem *ioaddr)
1029{
1030 RTL_W8(ChipCmd, 0x00);
1031 rtl8169_irq_mask_and_ack(ioaddr);
1032 RTL_R16(CPlusCmd);
1033}
1034
4da19633 1035static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1036{
4da19633 1037 void __iomem *ioaddr = tp->mmio_addr;
1038
1da177e4
LT		 1039 return RTL_R32(TBICSR) & TBIReset;
1040}
1041
4da19633 1042static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1043{
4da19633 1044 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1045}
1046
1047static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1048{
1049 return RTL_R32(TBICSR) & TBILinkOk;
1050}
1051
1052static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1053{
1054 return RTL_R8(PHYstatus) & LinkStatus;
1055}
1056
4da19633 1057static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1058{
4da19633 1059 void __iomem *ioaddr = tp->mmio_addr;
1060
1da177e4
LT		 1061 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1062}
1063
4da19633 1064static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1065{
1066 unsigned int val;
1067
4da19633 1068 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1069 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1070}
1071
e4fbce74 1072static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1073 struct rtl8169_private *tp,
1074 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1075{
1076 unsigned long flags;
1077
1078 spin_lock_irqsave(&tp->lock, flags);
1079 if (tp->link_ok(ioaddr)) {
e1759441 1080 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1081 if (pm)
1082 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1083 netif_carrier_on(dev);
1519e57f
FR		 1084 if (net_ratelimit())
1085 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1086 } else {
1da177e4 1087 netif_carrier_off(dev);
bf82c189 1088 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1089 if (pm)
1090 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1091 }
1da177e4
LT		 1092 spin_unlock_irqrestore(&tp->lock, flags);
1093}
1094
e4fbce74
RW		 1095static void rtl8169_check_link_status(struct net_device *dev,
1096 struct rtl8169_private *tp,
1097 void __iomem *ioaddr)
1098{
1099 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1100}
1101
e1759441
RW		 1102#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1103
1104static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1105{
61a4dcc2
FR		 1106 void __iomem *ioaddr = tp->mmio_addr;
1107 u8 options;
e1759441 1108 u32 wolopts = 0;
61a4dcc2
FR		 1109
1110 options = RTL_R8(Config1);
1111 if (!(options & PMEnable))
e1759441 1112 return 0;
61a4dcc2
FR		 1113
1114 options = RTL_R8(Config3);
1115 if (options & LinkUp)
e1759441 1116 wolopts |= WAKE_PHY;
61a4dcc2 1117 if (options & MagicPacket)
e1759441 1118 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1119
1120 options = RTL_R8(Config5);
1121 if (options & UWF)
e1759441 1122 wolopts |= WAKE_UCAST;
61a4dcc2 1123 if (options & BWF)
e1759441 1124 wolopts |= WAKE_BCAST;
61a4dcc2 1125 if (options & MWF)
e1759441 1126 wolopts |= WAKE_MCAST;
61a4dcc2 1127
e1759441 1128 return wolopts;
61a4dcc2
FR		 1129}
1130
e1759441 1131static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1132{
1133 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1134
1135 spin_lock_irq(&tp->lock);
1136
1137 wol->supported = WAKE_ANY;
1138 wol->wolopts = __rtl8169_get_wol(tp);
1139
1140 spin_unlock_irq(&tp->lock);
1141}
1142
1143static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1144{
61a4dcc2 1145 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1146 unsigned int i;
350f7596 1147 static const struct {
61a4dcc2
FR		 1148 u32 opt;
1149 u16 reg;
1150 u8 mask;
1151 } cfg[] = {
1152 { WAKE_ANY, Config1, PMEnable },
1153 { WAKE_PHY, Config3, LinkUp },
1154 { WAKE_MAGIC, Config3, MagicPacket },
1155 { WAKE_UCAST, Config5, UWF },
1156 { WAKE_BCAST, Config5, BWF },
1157 { WAKE_MCAST, Config5, MWF },
1158 { WAKE_ANY, Config5, LanWake }
1159 };
1160
61a4dcc2
FR		 1161 RTL_W8(Cfg9346, Cfg9346_Unlock);
1162
1163 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1164 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1165 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1166 options |= cfg[i].mask;
1167 RTL_W8(cfg[i].reg, options);
1168 }
1169
1170 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1171}
1172
1173static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1174{
1175 struct rtl8169_private *tp = netdev_priv(dev);
1176
1177 spin_lock_irq(&tp->lock);
61a4dcc2 1178
f23e7fda
FR		 1179 if (wol->wolopts)
1180 tp->features |= RTL_FEATURE_WOL;
1181 else
1182 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1183 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1184 spin_unlock_irq(&tp->lock);
1185
ea80907f 1186 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1187
61a4dcc2
FR		 1188 return 0;
1189}
1190
31bd204f
FR		 1191static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1192{
1193 int i;
1194
1195 for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
1196 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
1197
1198 if (info->mac_version == tp->mac_version)
1199 return info->fw_name;
1200 }
1201 return NULL;
1202}
1203
1da177e4
LT		 1204static void rtl8169_get_drvinfo(struct net_device *dev,
1205 struct ethtool_drvinfo *info)
1206{
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208
1209 strcpy(info->driver, MODULENAME);
1210 strcpy(info->version, RTL8169_VERSION);
1211 strcpy(info->bus_info, pci_name(tp->pci_dev));
31bd204f
FR		 1212 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1213 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1da177e4
LT		 1214}
1215
1216static int rtl8169_get_regs_len(struct net_device *dev)
1217{
1218 return R8169_REGS_SIZE;
1219}
1220
1221static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1222 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1223{
1224 struct rtl8169_private *tp = netdev_priv(dev);
1225 void __iomem *ioaddr = tp->mmio_addr;
1226 int ret = 0;
1227 u32 reg;
1228
1229 reg = RTL_R32(TBICSR);
1230 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1231 (duplex == DUPLEX_FULL)) {
1232 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1233 } else if (autoneg == AUTONEG_ENABLE)
1234 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1235 else {
bf82c189
JP		 1236 netif_warn(tp, link, dev,
1237 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1238 ret = -EOPNOTSUPP;
1239 }
1240
1241 return ret;
1242}
1243
1244static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1245 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1246{
1247 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1248 int giga_ctrl, bmcr;
54405cde 1249 int rc = -EINVAL;
1da177e4 1250
716b50a3 1251 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1252
1253 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1254 int auto_nego;
1255
4da19633 1256 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1257 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1258 ADVERTISE_100HALF | ADVERTISE_100FULL);
1259
1260 if (adv & ADVERTISED_10baseT_Half)
1261 auto_nego |= ADVERTISE_10HALF;
1262 if (adv & ADVERTISED_10baseT_Full)
1263 auto_nego |= ADVERTISE_10FULL;
1264 if (adv & ADVERTISED_100baseT_Half)
1265 auto_nego |= ADVERTISE_100HALF;
1266 if (adv & ADVERTISED_100baseT_Full)
1267 auto_nego |= ADVERTISE_100FULL;
1268
3577aa1b 1269 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1270
4da19633 1271 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1272 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1273
3577aa1b 1274 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1275 if (tp->mii.supports_gmii) {
54405cde
ON		 1276 if (adv & ADVERTISED_1000baseT_Half)
1277 giga_ctrl |= ADVERTISE_1000HALF;
1278 if (adv & ADVERTISED_1000baseT_Full)
1279 giga_ctrl |= ADVERTISE_1000FULL;
1280 } else if (adv & (ADVERTISED_1000baseT_Half |
1281 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1282 netif_info(tp, link, dev,
1283 "PHY does not support 1000Mbps\n");
54405cde 1284 goto out;
bcf0bf90 1285 }
1da177e4 1286
3577aa1b 1287 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1288
4da19633 1289 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1290 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1291 } else {
1292 giga_ctrl = 0;
1293
1294 if (speed == SPEED_10)
1295 bmcr = 0;
1296 else if (speed == SPEED_100)
1297 bmcr = BMCR_SPEED100;
1298 else
54405cde 1299 goto out;
3577aa1b 1300
1301 if (duplex == DUPLEX_FULL)
1302 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1303 }
1304
4da19633 1305 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1306
cecb5fd7
FR		 1307 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1308 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1309 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1310 rtl_writephy(tp, 0x17, 0x2138);
1311 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1312 } else {
4da19633 1313 rtl_writephy(tp, 0x17, 0x2108);
1314 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1315 }
1316 }
1317
54405cde
ON		 1318 rc = 0;
1319out:
1320 return rc;
1da177e4
LT		 1321}
1322
1323static int rtl8169_set_speed(struct net_device *dev,
54405cde 1324 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1325{
1326 struct rtl8169_private *tp = netdev_priv(dev);
1327 int ret;
1328
54405cde 1329 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1330 if (ret < 0)
1331 goto out;
1da177e4 1332
4876cc1e
FR		 1333 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1334 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1335 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1336 }
1337out:
1da177e4
LT		 1338 return ret;
1339}
1340
1341static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1342{
1343 struct rtl8169_private *tp = netdev_priv(dev);
1344 unsigned long flags;
1345 int ret;
1346
4876cc1e
FR		 1347 del_timer_sync(&tp->timer);
1348
1da177e4 1349 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1350 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1351 cmd->duplex, cmd->advertising);
1da177e4 1352 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1353
1da177e4
LT		 1354 return ret;
1355}
1356
350fb32a 1357static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1358{
2b7b4318 1359 if (dev->mtu > TD_MSS_MAX)
350fb32a 1360 features &= ~NETIF_F_ALL_TSO;
1da177e4 1361
350fb32a 1362 return features;
1da177e4
LT		 1363}
1364
350fb32a 1365static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1366{
1367 struct rtl8169_private *tp = netdev_priv(dev);
1368 void __iomem *ioaddr = tp->mmio_addr;
1369 unsigned long flags;
1370
1371 spin_lock_irqsave(&tp->lock, flags);
1372
350fb32a 1373 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1374 tp->cp_cmd |= RxChkSum;
1375 else
1376 tp->cp_cmd &= ~RxChkSum;
1377
350fb32a
MM		 1378 if (dev->features & NETIF_F_HW_VLAN_RX)
1379 tp->cp_cmd |= RxVlan;
1380 else
1381 tp->cp_cmd &= ~RxVlan;
1382
1da177e4
LT		 1383 RTL_W16(CPlusCmd, tp->cp_cmd);
1384 RTL_R16(CPlusCmd);
1385
1386 spin_unlock_irqrestore(&tp->lock, flags);
1387
1388 return 0;
1389}
1390
1da177e4
LT		 1391static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1392 struct sk_buff *skb)
1393{
eab6d18d 1394 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1395 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1396}
1397
7a8fc77b 1398static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1399{
1400 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1401
7a8fc77b
FR		 1402 if (opts2 & RxVlanTag)
1403 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1404
1da177e4 1405 desc->opts2 = 0;
1da177e4
LT		 1406}
1407
ccdffb9a 1408static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1409{
1410 struct rtl8169_private *tp = netdev_priv(dev);
1411 void __iomem *ioaddr = tp->mmio_addr;
1412 u32 status;
1413
1414 cmd->supported =
1415 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1416 cmd->port = PORT_FIBRE;
1417 cmd->transceiver = XCVR_INTERNAL;
1418
1419 status = RTL_R32(TBICSR);
1420 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1421 cmd->autoneg = !!(status & TBINwEnable);
1422
70739497 1423 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1424 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1425
1426 return 0;
1da177e4
LT		 1427}
1428
ccdffb9a 1429static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1430{
1431 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1432
1433 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1434}
1435
1436static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1437{
1438 struct rtl8169_private *tp = netdev_priv(dev);
1439 unsigned long flags;
ccdffb9a 1440 int rc;
1da177e4
LT		 1441
1442 spin_lock_irqsave(&tp->lock, flags);
1443
ccdffb9a 1444 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1445
1446 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1447 return rc;
1da177e4
LT		 1448}
1449
1450static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1451 void *p)
1452{
5b0384f4
FR		 1453 struct rtl8169_private *tp = netdev_priv(dev);
1454 unsigned long flags;
1da177e4 1455
5b0384f4
FR		 1456 if (regs->len > R8169_REGS_SIZE)
1457 regs->len = R8169_REGS_SIZE;
1da177e4 1458
5b0384f4
FR		 1459 spin_lock_irqsave(&tp->lock, flags);
1460 memcpy_fromio(p, tp->mmio_addr, regs->len);
1461 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1462}
1463
b57b7e5a
SH		 1464static u32 rtl8169_get_msglevel(struct net_device *dev)
1465{
1466 struct rtl8169_private *tp = netdev_priv(dev);
1467
1468 return tp->msg_enable;
1469}
1470
1471static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1472{
1473 struct rtl8169_private *tp = netdev_priv(dev);
1474
1475 tp->msg_enable = value;
1476}
1477
d4a3a0fc
SH		 1478static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1479 "tx_packets",
1480 "rx_packets",
1481 "tx_errors",
1482 "rx_errors",
1483 "rx_missed",
1484 "align_errors",
1485 "tx_single_collisions",
1486 "tx_multi_collisions",
1487 "unicast",
1488 "broadcast",
1489 "multicast",
1490 "tx_aborted",
1491 "tx_underrun",
1492};
1493
b9f2c044 1494static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1495{
b9f2c044
JG		 1496 switch (sset) {
1497 case ETH_SS_STATS:
1498 return ARRAY_SIZE(rtl8169_gstrings);
1499 default:
1500 return -EOPNOTSUPP;
1501 }
d4a3a0fc
SH		 1502}
1503
355423d0 1504static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1505{
1506 struct rtl8169_private *tp = netdev_priv(dev);
1507 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1508 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1509 struct rtl8169_counters *counters;
1510 dma_addr_t paddr;
1511 u32 cmd;
355423d0 1512 int wait = 1000;
d4a3a0fc 1513
355423d0
IV		 1514 /*
1515 * Some chips are unable to dump tally counters when the receiver
1516 * is disabled.
1517 */
1518 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1519 return;
d4a3a0fc 1520
48addcc9 1521 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1522 if (!counters)
1523 return;
1524
1525 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1526 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1527 RTL_W32(CounterAddrLow, cmd);
1528 RTL_W32(CounterAddrLow, cmd | CounterDump);
1529
355423d0
IV		 1530 while (wait--) {
1531 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1532 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1533 break;
355423d0
IV		 1534 }
1535 udelay(10);
d4a3a0fc
SH		 1536 }
1537
1538 RTL_W32(CounterAddrLow, 0);
1539 RTL_W32(CounterAddrHigh, 0);
1540
48addcc9 1541 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1542}
1543
355423d0
IV		 1544static void rtl8169_get_ethtool_stats(struct net_device *dev,
1545 struct ethtool_stats *stats, u64 *data)
1546{
1547 struct rtl8169_private *tp = netdev_priv(dev);
1548
1549 ASSERT_RTNL();
1550
1551 rtl8169_update_counters(dev);
1552
1553 data[0] = le64_to_cpu(tp->counters.tx_packets);
1554 data[1] = le64_to_cpu(tp->counters.rx_packets);
1555 data[2] = le64_to_cpu(tp->counters.tx_errors);
1556 data[3] = le32_to_cpu(tp->counters.rx_errors);
1557 data[4] = le16_to_cpu(tp->counters.rx_missed);
1558 data[5] = le16_to_cpu(tp->counters.align_errors);
1559 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1560 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1561 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1562 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1563 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1564 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1565 data[12] = le16_to_cpu(tp->counters.tx_underun);
1566}
1567
d4a3a0fc
SH		 1568static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1569{
1570 switch(stringset) {
1571 case ETH_SS_STATS:
1572 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1573 break;
1574 }
1575}
1576
7282d491 1577static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1578 .get_drvinfo = rtl8169_get_drvinfo,
1579 .get_regs_len = rtl8169_get_regs_len,
1580 .get_link = ethtool_op_get_link,
1581 .get_settings = rtl8169_get_settings,
1582 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1583 .get_msglevel = rtl8169_get_msglevel,
1584 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1585 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1586 .get_wol = rtl8169_get_wol,
1587 .set_wol = rtl8169_set_wol,
d4a3a0fc 1588 .get_strings = rtl8169_get_strings,
b9f2c044 1589 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1590 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1591};
1592
07d3f51f
FR		 1593static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1594 void __iomem *ioaddr)
1da177e4 1595{
0e485150
FR		 1596 /*
1597 * The driver currently handles the 8168Bf and the 8168Be identically
1598 * but they can be identified more specifically through the test below
1599 * if needed:
1600 *
1601 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1602 *
1603 * Same thing for the 8101Eb and the 8101Ec:
1604 *
1605 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1606 */
350f7596 1607 static const struct {
1da177e4 1608 u32 mask;
e3cf0cc0 1609 u32 val;
1da177e4
LT		 1610 int mac_version;
1611 } mac_info[] = {
01dc7fec 1612 /* 8168E family. */
1613 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1614 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1615 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1616
5b538df9 1617 /* 8168D family. */
daf9df6d 1618 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1619 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1620 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1621
e6de30d6 1622 /* 8168DP family. */
1623 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1624 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1625 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1626
ef808d50 1627 /* 8168C family. */
17c99297 1628 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1629 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1630 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1631 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1632 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1633 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1634 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1635 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1636 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1637
1638 /* 8168B family. */
1639 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1640 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1641 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1642 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1643
1644 /* 8101 family. */
36a0e6c2 1645 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1646 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1647 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1648 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1649 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1650 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1651 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1652 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1653 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1654 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1655 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1656 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1657 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1658 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1659 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1660 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1661 /* FIXME: where did these entries come from ? -- FR */
1662 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1663 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1664
1665 /* 8110 family. */
1666 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1667 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1668 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1669 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1670 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1671 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1672
f21b75e9
JD		 1673 /* Catch-all */
1674 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1675 }, *p = mac_info;
1676 u32 reg;
1677
e3cf0cc0
FR		 1678 reg = RTL_R32(TxConfig);
1679 while ((reg & p->mask) != p->val)
1da177e4
LT		 1680 p++;
1681 tp->mac_version = p->mac_version;
1682}
1683
1684static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1685{
bcf0bf90 1686 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1687}
1688
867763c1
FR		 1689struct phy_reg {
1690 u16 reg;
1691 u16 val;
1692};
1693
4da19633 1694static void rtl_writephy_batch(struct rtl8169_private *tp,
1695 const struct phy_reg *regs, int len)
867763c1
FR		 1696{
1697 while (len-- > 0) {
4da19633 1698 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1699 regs++;
1700 }
1701}
1702
bca03d5f 1703#define PHY_READ 0x00000000
1704#define PHY_DATA_OR 0x10000000
1705#define PHY_DATA_AND 0x20000000
1706#define PHY_BJMPN 0x30000000
1707#define PHY_READ_EFUSE 0x40000000
1708#define PHY_READ_MAC_BYTE 0x50000000
1709#define PHY_WRITE_MAC_BYTE 0x60000000
1710#define PHY_CLEAR_READCOUNT 0x70000000
1711#define PHY_WRITE 0x80000000
1712#define PHY_READCOUNT_EQ_SKIP 0x90000000
1713#define PHY_COMP_EQ_SKIPN 0xa0000000
1714#define PHY_COMP_NEQ_SKIPN 0xb0000000
1715#define PHY_WRITE_PREVIOUS 0xc0000000
1716#define PHY_SKIPN 0xd0000000
1717#define PHY_DELAY_MS 0xe0000000
1718#define PHY_WRITE_ERI_WORD 0xf0000000
1719
1720static void
1721rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1722{
bca03d5f 1723 __le32 *phytable = (__le32 *)fw->data;
1724 struct net_device *dev = tp->dev;
42b82dc1 1725 size_t index, fw_size = fw->size / sizeof(*phytable);
1726 u32 predata, count;
bca03d5f 1727
1728 if (fw->size % sizeof(*phytable)) {
1729 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1730 return;
1731 }
1732
42b82dc1 1733 for (index = 0; index < fw_size; index++) {
1734 u32 action = le32_to_cpu(phytable[index]);
1735 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1736
42b82dc1 1737 switch(action & 0xf0000000) {
1738 case PHY_READ:
1739 case PHY_DATA_OR:
1740 case PHY_DATA_AND:
1741 case PHY_READ_EFUSE:
1742 case PHY_CLEAR_READCOUNT:
1743 case PHY_WRITE:
1744 case PHY_WRITE_PREVIOUS:
1745 case PHY_DELAY_MS:
1746 break;
1747
1748 case PHY_BJMPN:
1749 if (regno > index) {
1750 netif_err(tp, probe, tp->dev,
cecb5fd7 1751 "Out of range of firmware\n");
42b82dc1 1752 return;
1753 }
1754 break;
1755 case PHY_READCOUNT_EQ_SKIP:
1756 if (index + 2 >= fw_size) {
1757 netif_err(tp, probe, tp->dev,
cecb5fd7 1758 "Out of range of firmware\n");
42b82dc1 1759 return;
1760 }
1761 break;
1762 case PHY_COMP_EQ_SKIPN:
1763 case PHY_COMP_NEQ_SKIPN:
1764 case PHY_SKIPN:
1765 if (index + 1 + regno >= fw_size) {
1766 netif_err(tp, probe, tp->dev,
cecb5fd7 1767 "Out of range of firmware\n");
42b82dc1 1768 return;
1769 }
bca03d5f 1770 break;
1771
42b82dc1 1772 case PHY_READ_MAC_BYTE:
1773 case PHY_WRITE_MAC_BYTE:
1774 case PHY_WRITE_ERI_WORD:
1775 default:
1776 netif_err(tp, probe, tp->dev,
1777 "Invalid action 0x%08x\n", action);
bca03d5f 1778 return;
1779 }
1780 }
1781
42b82dc1 1782 predata = 0;
1783 count = 0;
1784
1785 for (index = 0; index < fw_size; ) {
1786 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1787 u32 data = action & 0x0000ffff;
42b82dc1 1788 u32 regno = (action & 0x0fff0000) >> 16;
1789
1790 if (!action)
1791 break;
bca03d5f 1792
1793 switch(action & 0xf0000000) {
42b82dc1 1794 case PHY_READ:
1795 predata = rtl_readphy(tp, regno);
1796 count++;
1797 index++;
1798 break;
1799 case PHY_DATA_OR:
1800 predata |= data;
1801 index++;
1802 break;
1803 case PHY_DATA_AND:
1804 predata &= data;
1805 index++;
1806 break;
1807 case PHY_BJMPN:
1808 index -= regno;
1809 break;
1810 case PHY_READ_EFUSE:
1811 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1812 index++;
1813 break;
1814 case PHY_CLEAR_READCOUNT:
1815 count = 0;
1816 index++;
1817 break;
bca03d5f 1818 case PHY_WRITE:
42b82dc1 1819 rtl_writephy(tp, regno, data);
1820 index++;
1821 break;
1822 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 1823 index += (count == data) ? 2 : 1;
bca03d5f 1824 break;
42b82dc1 1825 case PHY_COMP_EQ_SKIPN:
1826 if (predata == data)
1827 index += regno;
1828 index++;
1829 break;
1830 case PHY_COMP_NEQ_SKIPN:
1831 if (predata != data)
1832 index += regno;
1833 index++;
1834 break;
1835 case PHY_WRITE_PREVIOUS:
1836 rtl_writephy(tp, regno, predata);
1837 index++;
1838 break;
1839 case PHY_SKIPN:
1840 index += regno + 1;
1841 break;
1842 case PHY_DELAY_MS:
1843 mdelay(data);
1844 index++;
1845 break;
1846
1847 case PHY_READ_MAC_BYTE:
1848 case PHY_WRITE_MAC_BYTE:
1849 case PHY_WRITE_ERI_WORD:
bca03d5f 1850 default:
1851 BUG();
1852 }
1853 }
1854}
1855
f1e02ed1 1856static void rtl_release_firmware(struct rtl8169_private *tp)
1857{
953a12cc
FR		 1858 if (!IS_ERR_OR_NULL(tp->fw))
1859 release_firmware(tp->fw);
1860 tp->fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1861}
1862
953a12cc 1863static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1864{
953a12cc 1865 const struct firmware *fw = tp->fw;
f1e02ed1 1866
1867 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
953a12cc
FR		 1868 if (!IS_ERR_OR_NULL(fw))
1869 rtl_phy_write_fw(tp, fw);
1870}
1871
1872static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1873{
1874 if (rtl_readphy(tp, reg) != val)
1875 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1876 else
1877 rtl_apply_firmware(tp);
f1e02ed1 1878}
1879
4da19633 1880static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1881{
350f7596 1882 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1883 { 0x1f, 0x0001 },
1884 { 0x06, 0x006e },
1885 { 0x08, 0x0708 },
1886 { 0x15, 0x4000 },
1887 { 0x18, 0x65c7 },
1da177e4 1888
0b9b571d 1889 { 0x1f, 0x0001 },
1890 { 0x03, 0x00a1 },
1891 { 0x02, 0x0008 },
1892 { 0x01, 0x0120 },
1893 { 0x00, 0x1000 },
1894 { 0x04, 0x0800 },
1895 { 0x04, 0x0000 },
1da177e4 1896
0b9b571d 1897 { 0x03, 0xff41 },
1898 { 0x02, 0xdf60 },
1899 { 0x01, 0x0140 },
1900 { 0x00, 0x0077 },
1901 { 0x04, 0x7800 },
1902 { 0x04, 0x7000 },
1903
1904 { 0x03, 0x802f },
1905 { 0x02, 0x4f02 },
1906 { 0x01, 0x0409 },
1907 { 0x00, 0xf0f9 },
1908 { 0x04, 0x9800 },
1909 { 0x04, 0x9000 },
1910
1911 { 0x03, 0xdf01 },
1912 { 0x02, 0xdf20 },
1913 { 0x01, 0xff95 },
1914 { 0x00, 0xba00 },
1915 { 0x04, 0xa800 },
1916 { 0x04, 0xa000 },
1917
1918 { 0x03, 0xff41 },
1919 { 0x02, 0xdf20 },
1920 { 0x01, 0x0140 },
1921 { 0x00, 0x00bb },
1922 { 0x04, 0xb800 },
1923 { 0x04, 0xb000 },
1924
1925 { 0x03, 0xdf41 },
1926 { 0x02, 0xdc60 },
1927 { 0x01, 0x6340 },
1928 { 0x00, 0x007d },
1929 { 0x04, 0xd800 },
1930 { 0x04, 0xd000 },
1931
1932 { 0x03, 0xdf01 },
1933 { 0x02, 0xdf20 },
1934 { 0x01, 0x100a },
1935 { 0x00, 0xa0ff },
1936 { 0x04, 0xf800 },
1937 { 0x04, 0xf000 },
1938
1939 { 0x1f, 0x0000 },
1940 { 0x0b, 0x0000 },
1941 { 0x00, 0x9200 }
1942 };
1da177e4 1943
4da19633 1944 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1945}
1946
4da19633 1947static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1948{
350f7596 1949 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1950 { 0x1f, 0x0002 },
1951 { 0x01, 0x90d0 },
1952 { 0x1f, 0x0000 }
1953 };
1954
4da19633 1955 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1956}
1957
4da19633 1958static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1959{
1960 struct pci_dev *pdev = tp->pci_dev;
1961 u16 vendor_id, device_id;
1962
1963 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1964 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1965
1966 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1967 return;
1968
4da19633 1969 rtl_writephy(tp, 0x1f, 0x0001);
1970 rtl_writephy(tp, 0x10, 0xf01b);
1971 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1972}
1973
4da19633 1974static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1975{
350f7596 1976 static const struct phy_reg phy_reg_init[] = {
2e955856 1977 { 0x1f, 0x0001 },
1978 { 0x04, 0x0000 },
1979 { 0x03, 0x00a1 },
1980 { 0x02, 0x0008 },
1981 { 0x01, 0x0120 },
1982 { 0x00, 0x1000 },
1983 { 0x04, 0x0800 },
1984 { 0x04, 0x9000 },
1985 { 0x03, 0x802f },
1986 { 0x02, 0x4f02 },
1987 { 0x01, 0x0409 },
1988 { 0x00, 0xf099 },
1989 { 0x04, 0x9800 },
1990 { 0x04, 0xa000 },
1991 { 0x03, 0xdf01 },
1992 { 0x02, 0xdf20 },
1993 { 0x01, 0xff95 },
1994 { 0x00, 0xba00 },
1995 { 0x04, 0xa800 },
1996 { 0x04, 0xf000 },
1997 { 0x03, 0xdf01 },
1998 { 0x02, 0xdf20 },
1999 { 0x01, 0x101a },
2000 { 0x00, 0xa0ff },
2001 { 0x04, 0xf800 },
2002 { 0x04, 0x0000 },
2003 { 0x1f, 0x0000 },
2004
2005 { 0x1f, 0x0001 },
2006 { 0x10, 0xf41b },
2007 { 0x14, 0xfb54 },
2008 { 0x18, 0xf5c7 },
2009 { 0x1f, 0x0000 },
2010
2011 { 0x1f, 0x0001 },
2012 { 0x17, 0x0cc0 },
2013 { 0x1f, 0x0000 }
2014 };
2015
4da19633 2016 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2017
4da19633 2018 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2019}
2020
4da19633 2021static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2022{
350f7596 2023 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2024 { 0x1f, 0x0001 },
2025 { 0x04, 0x0000 },
2026 { 0x03, 0x00a1 },
2027 { 0x02, 0x0008 },
2028 { 0x01, 0x0120 },
2029 { 0x00, 0x1000 },
2030 { 0x04, 0x0800 },
2031 { 0x04, 0x9000 },
2032 { 0x03, 0x802f },
2033 { 0x02, 0x4f02 },
2034 { 0x01, 0x0409 },
2035 { 0x00, 0xf099 },
2036 { 0x04, 0x9800 },
2037 { 0x04, 0xa000 },
2038 { 0x03, 0xdf01 },
2039 { 0x02, 0xdf20 },
2040 { 0x01, 0xff95 },
2041 { 0x00, 0xba00 },
2042 { 0x04, 0xa800 },
2043 { 0x04, 0xf000 },
2044 { 0x03, 0xdf01 },
2045 { 0x02, 0xdf20 },
2046 { 0x01, 0x101a },
2047 { 0x00, 0xa0ff },
2048 { 0x04, 0xf800 },
2049 { 0x04, 0x0000 },
2050 { 0x1f, 0x0000 },
2051
2052 { 0x1f, 0x0001 },
2053 { 0x0b, 0x8480 },
2054 { 0x1f, 0x0000 },
2055
2056 { 0x1f, 0x0001 },
2057 { 0x18, 0x67c7 },
2058 { 0x04, 0x2000 },
2059 { 0x03, 0x002f },
2060 { 0x02, 0x4360 },
2061 { 0x01, 0x0109 },
2062 { 0x00, 0x3022 },
2063 { 0x04, 0x2800 },
2064 { 0x1f, 0x0000 },
2065
2066 { 0x1f, 0x0001 },
2067 { 0x17, 0x0cc0 },
2068 { 0x1f, 0x0000 }
2069 };
2070
4da19633 2071 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2072}
2073
4da19633 2074static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2075{
350f7596 2076 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2077 { 0x10, 0xf41b },
2078 { 0x1f, 0x0000 }
2079 };
2080
4da19633 2081 rtl_writephy(tp, 0x1f, 0x0001);
2082 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2083
4da19633 2084 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2085}
2086
4da19633 2087static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2088{
350f7596 2089 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2090 { 0x1f, 0x0001 },
2091 { 0x10, 0xf41b },
2092 { 0x1f, 0x0000 }
2093 };
2094
4da19633 2095 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2096}
2097
4da19633 2098static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2099{
350f7596 2100 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2101 { 0x1f, 0x0000 },
2102 { 0x1d, 0x0f00 },
2103 { 0x1f, 0x0002 },
2104 { 0x0c, 0x1ec8 },
2105 { 0x1f, 0x0000 }
2106 };
2107
4da19633 2108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2109}
2110
4da19633 2111static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2112{
350f7596 2113 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2114 { 0x1f, 0x0001 },
2115 { 0x1d, 0x3d98 },
2116 { 0x1f, 0x0000 }
2117 };
2118
4da19633 2119 rtl_writephy(tp, 0x1f, 0x0000);
2120 rtl_patchphy(tp, 0x14, 1 << 5);
2121 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2122
4da19633 2123 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2124}
2125
4da19633 2126static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2127{
350f7596 2128 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2129 { 0x1f, 0x0001 },
2130 { 0x12, 0x2300 },
867763c1
FR		 2131 { 0x1f, 0x0002 },
2132 { 0x00, 0x88d4 },
2133 { 0x01, 0x82b1 },
2134 { 0x03, 0x7002 },
2135 { 0x08, 0x9e30 },
2136 { 0x09, 0x01f0 },
2137 { 0x0a, 0x5500 },
2138 { 0x0c, 0x00c8 },
2139 { 0x1f, 0x0003 },
2140 { 0x12, 0xc096 },
2141 { 0x16, 0x000a },
f50d4275
FR		 2142 { 0x1f, 0x0000 },
2143 { 0x1f, 0x0000 },
2144 { 0x09, 0x2000 },
2145 { 0x09, 0x0000 }
867763c1
FR		 2146 };
2147
4da19633 2148 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2149
4da19633 2150 rtl_patchphy(tp, 0x14, 1 << 5);
2151 rtl_patchphy(tp, 0x0d, 1 << 5);
2152 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2153}
2154
4da19633 2155static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2156{
350f7596 2157 static const struct phy_reg phy_reg_init[] = {
f50d4275 2158 { 0x1f, 0x0001 },
7da97ec9 2159 { 0x12, 0x2300 },
f50d4275
FR		 2160 { 0x03, 0x802f },
2161 { 0x02, 0x4f02 },
2162 { 0x01, 0x0409 },
2163 { 0x00, 0xf099 },
2164 { 0x04, 0x9800 },
2165 { 0x04, 0x9000 },
2166 { 0x1d, 0x3d98 },
7da97ec9
FR		 2167 { 0x1f, 0x0002 },
2168 { 0x0c, 0x7eb8 },
f50d4275
FR		 2169 { 0x06, 0x0761 },
2170 { 0x1f, 0x0003 },
2171 { 0x16, 0x0f0a },
7da97ec9
FR		 2172 { 0x1f, 0x0000 }
2173 };
2174
4da19633 2175 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2176
4da19633 2177 rtl_patchphy(tp, 0x16, 1 << 0);
2178 rtl_patchphy(tp, 0x14, 1 << 5);
2179 rtl_patchphy(tp, 0x0d, 1 << 5);
2180 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2181}
2182
4da19633 2183static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2184{
350f7596 2185 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2186 { 0x1f, 0x0001 },
2187 { 0x12, 0x2300 },
2188 { 0x1d, 0x3d98 },
2189 { 0x1f, 0x0002 },
2190 { 0x0c, 0x7eb8 },
2191 { 0x06, 0x5461 },
2192 { 0x1f, 0x0003 },
2193 { 0x16, 0x0f0a },
2194 { 0x1f, 0x0000 }
2195 };
2196
4da19633 2197 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2198
4da19633 2199 rtl_patchphy(tp, 0x16, 1 << 0);
2200 rtl_patchphy(tp, 0x14, 1 << 5);
2201 rtl_patchphy(tp, 0x0d, 1 << 5);
2202 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2203}
2204
4da19633 2205static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2206{
4da19633 2207 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2208}
2209
bca03d5f 2210static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2211{
350f7596 2212 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2213 /* Channel Estimation */
5b538df9 2214 { 0x1f, 0x0001 },
daf9df6d 2215 { 0x06, 0x4064 },
2216 { 0x07, 0x2863 },
2217 { 0x08, 0x059c },
2218 { 0x09, 0x26b4 },
2219 { 0x0a, 0x6a19 },
2220 { 0x0b, 0xdcc8 },
2221 { 0x10, 0xf06d },
2222 { 0x14, 0x7f68 },
2223 { 0x18, 0x7fd9 },
2224 { 0x1c, 0xf0ff },
2225 { 0x1d, 0x3d9c },
5b538df9 2226 { 0x1f, 0x0003 },
daf9df6d 2227 { 0x12, 0xf49f },
2228 { 0x13, 0x070b },
2229 { 0x1a, 0x05ad },
bca03d5f 2230 { 0x14, 0x94c0 },
2231
2232 /*
2233 * Tx Error Issue
cecb5fd7 2234 * Enhance line driver power
bca03d5f 2235 */
5b538df9 2236 { 0x1f, 0x0002 },
daf9df6d 2237 { 0x06, 0x5561 },
2238 { 0x1f, 0x0005 },
2239 { 0x05, 0x8332 },
bca03d5f 2240 { 0x06, 0x5561 },
2241
2242 /*
2243 * Can not link to 1Gbps with bad cable
2244 * Decrease SNR threshold form 21.07dB to 19.04dB
2245 */
2246 { 0x1f, 0x0001 },
2247 { 0x17, 0x0cc0 },
daf9df6d 2248
5b538df9 2249 { 0x1f, 0x0000 },
bca03d5f 2250 { 0x0d, 0xf880 }
daf9df6d 2251 };
bca03d5f 2252 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2253
4da19633 2254 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2255
bca03d5f 2256 /*
2257 * Rx Error Issue
2258 * Fine Tune Switching regulator parameter
2259 */
4da19633 2260 rtl_writephy(tp, 0x1f, 0x0002);
2261 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2262 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2263
daf9df6d 2264 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2265 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2266 { 0x1f, 0x0002 },
2267 { 0x05, 0x669a },
2268 { 0x1f, 0x0005 },
2269 { 0x05, 0x8330 },
2270 { 0x06, 0x669a },
2271 { 0x1f, 0x0002 }
2272 };
2273 int val;
2274
4da19633 2275 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2276
4da19633 2277 val = rtl_readphy(tp, 0x0d);
daf9df6d 2278
2279 if ((val & 0x00ff) != 0x006c) {
350f7596 2280 static const u32 set[] = {
daf9df6d 2281 0x0065, 0x0066, 0x0067, 0x0068,
2282 0x0069, 0x006a, 0x006b, 0x006c
2283 };
2284 int i;
2285
4da19633 2286 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2287
2288 val &= 0xff00;
2289 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2290 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2291 }
2292 } else {
350f7596 2293 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2294 { 0x1f, 0x0002 },
2295 { 0x05, 0x6662 },
2296 { 0x1f, 0x0005 },
2297 { 0x05, 0x8330 },
2298 { 0x06, 0x6662 }
2299 };
2300
4da19633 2301 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2302 }
2303
bca03d5f 2304 /* RSET couple improve */
4da19633 2305 rtl_writephy(tp, 0x1f, 0x0002);
2306 rtl_patchphy(tp, 0x0d, 0x0300);
2307 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2308
bca03d5f 2309 /* Fine tune PLL performance */
4da19633 2310 rtl_writephy(tp, 0x1f, 0x0002);
2311 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2312 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2313
4da19633 2314 rtl_writephy(tp, 0x1f, 0x0005);
2315 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2316
2317 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2318
4da19633 2319 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2320}
2321
bca03d5f 2322static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2323{
350f7596 2324 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2325 /* Channel Estimation */
daf9df6d 2326 { 0x1f, 0x0001 },
2327 { 0x06, 0x4064 },
2328 { 0x07, 0x2863 },
2329 { 0x08, 0x059c },
2330 { 0x09, 0x26b4 },
2331 { 0x0a, 0x6a19 },
2332 { 0x0b, 0xdcc8 },
2333 { 0x10, 0xf06d },
2334 { 0x14, 0x7f68 },
2335 { 0x18, 0x7fd9 },
2336 { 0x1c, 0xf0ff },
2337 { 0x1d, 0x3d9c },
2338 { 0x1f, 0x0003 },
2339 { 0x12, 0xf49f },
2340 { 0x13, 0x070b },
2341 { 0x1a, 0x05ad },
2342 { 0x14, 0x94c0 },
2343
bca03d5f 2344 /*
2345 * Tx Error Issue
cecb5fd7 2346 * Enhance line driver power
bca03d5f 2347 */
daf9df6d 2348 { 0x1f, 0x0002 },
2349 { 0x06, 0x5561 },
2350 { 0x1f, 0x0005 },
2351 { 0x05, 0x8332 },
bca03d5f 2352 { 0x06, 0x5561 },
2353
2354 /*
2355 * Can not link to 1Gbps with bad cable
2356 * Decrease SNR threshold form 21.07dB to 19.04dB
2357 */
2358 { 0x1f, 0x0001 },
2359 { 0x17, 0x0cc0 },
daf9df6d 2360
2361 { 0x1f, 0x0000 },
bca03d5f 2362 { 0x0d, 0xf880 }
5b538df9 2363 };
bca03d5f 2364 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2365
4da19633 2366 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2367
daf9df6d 2368 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2369 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2370 { 0x1f, 0x0002 },
2371 { 0x05, 0x669a },
5b538df9 2372 { 0x1f, 0x0005 },
daf9df6d 2373 { 0x05, 0x8330 },
2374 { 0x06, 0x669a },
2375
2376 { 0x1f, 0x0002 }
2377 };
2378 int val;
2379
4da19633 2380 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2381
4da19633 2382 val = rtl_readphy(tp, 0x0d);
daf9df6d 2383 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2384 static const u32 set[] = {
daf9df6d 2385 0x0065, 0x0066, 0x0067, 0x0068,
2386 0x0069, 0x006a, 0x006b, 0x006c
2387 };
2388 int i;
2389
4da19633 2390 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2391
2392 val &= 0xff00;
2393 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2394 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2395 }
2396 } else {
350f7596 2397 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2398 { 0x1f, 0x0002 },
2399 { 0x05, 0x2642 },
5b538df9 2400 { 0x1f, 0x0005 },
daf9df6d 2401 { 0x05, 0x8330 },
2402 { 0x06, 0x2642 }
5b538df9
FR		 2403 };
2404
4da19633 2405 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2406 }
2407
bca03d5f 2408 /* Fine tune PLL performance */
4da19633 2409 rtl_writephy(tp, 0x1f, 0x0002);
2410 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2411 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2412
bca03d5f 2413 /* Switching regulator Slew rate */
4da19633 2414 rtl_writephy(tp, 0x1f, 0x0002);
2415 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2416
4da19633 2417 rtl_writephy(tp, 0x1f, 0x0005);
2418 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2419
2420 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2421
4da19633 2422 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2423}
2424
4da19633 2425static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2426{
350f7596 2427 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2428 { 0x1f, 0x0002 },
2429 { 0x10, 0x0008 },
2430 { 0x0d, 0x006c },
2431
2432 { 0x1f, 0x0000 },
2433 { 0x0d, 0xf880 },
2434
2435 { 0x1f, 0x0001 },
2436 { 0x17, 0x0cc0 },
2437
2438 { 0x1f, 0x0001 },
2439 { 0x0b, 0xa4d8 },
2440 { 0x09, 0x281c },
2441 { 0x07, 0x2883 },
2442 { 0x0a, 0x6b35 },
2443 { 0x1d, 0x3da4 },
2444 { 0x1c, 0xeffd },
2445 { 0x14, 0x7f52 },
2446 { 0x18, 0x7fc6 },
2447 { 0x08, 0x0601 },
2448 { 0x06, 0x4063 },
2449 { 0x10, 0xf074 },
2450 { 0x1f, 0x0003 },
2451 { 0x13, 0x0789 },
2452 { 0x12, 0xf4bd },
2453 { 0x1a, 0x04fd },
2454 { 0x14, 0x84b0 },
2455 { 0x1f, 0x0000 },
2456 { 0x00, 0x9200 },
2457
2458 { 0x1f, 0x0005 },
2459 { 0x01, 0x0340 },
2460 { 0x1f, 0x0001 },
2461 { 0x04, 0x4000 },
2462 { 0x03, 0x1d21 },
2463 { 0x02, 0x0c32 },
2464 { 0x01, 0x0200 },
2465 { 0x00, 0x5554 },
2466 { 0x04, 0x4800 },
2467 { 0x04, 0x4000 },
2468 { 0x04, 0xf000 },
2469 { 0x03, 0xdf01 },
2470 { 0x02, 0xdf20 },
2471 { 0x01, 0x101a },
2472 { 0x00, 0xa0ff },
2473 { 0x04, 0xf800 },
2474 { 0x04, 0xf000 },
2475 { 0x1f, 0x0000 },
2476
2477 { 0x1f, 0x0007 },
2478 { 0x1e, 0x0023 },
2479 { 0x16, 0x0000 },
2480 { 0x1f, 0x0000 }
2481 };
2482
4da19633 2483 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2484}
2485
e6de30d6 2486static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2487{
2488 static const struct phy_reg phy_reg_init[] = {
2489 { 0x1f, 0x0001 },
2490 { 0x17, 0x0cc0 },
2491
2492 { 0x1f, 0x0007 },
2493 { 0x1e, 0x002d },
2494 { 0x18, 0x0040 },
2495 { 0x1f, 0x0000 }
2496 };
2497
2498 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2499 rtl_patchphy(tp, 0x0d, 1 << 5);
2500}
2501
01dc7fec 2502static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2503{
2504 static const struct phy_reg phy_reg_init[] = {
2505 /* Enable Delay cap */
2506 { 0x1f, 0x0005 },
2507 { 0x05, 0x8b80 },
2508 { 0x06, 0xc896 },
2509 { 0x1f, 0x0000 },
2510
2511 /* Channel estimation fine tune */
2512 { 0x1f, 0x0001 },
2513 { 0x0b, 0x6c20 },
2514 { 0x07, 0x2872 },
2515 { 0x1c, 0xefff },
2516 { 0x1f, 0x0003 },
2517 { 0x14, 0x6420 },
2518 { 0x1f, 0x0000 },
2519
2520 /* Update PFM & 10M TX idle timer */
2521 { 0x1f, 0x0007 },
2522 { 0x1e, 0x002f },
2523 { 0x15, 0x1919 },
2524 { 0x1f, 0x0000 },
2525
2526 { 0x1f, 0x0007 },
2527 { 0x1e, 0x00ac },
2528 { 0x18, 0x0006 },
2529 { 0x1f, 0x0000 }
2530 };
2531
15ecd039
FR		 2532 rtl_apply_firmware(tp);
2533
01dc7fec 2534 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2535
2536 /* DCO enable for 10M IDLE Power */
2537 rtl_writephy(tp, 0x1f, 0x0007);
2538 rtl_writephy(tp, 0x1e, 0x0023);
2539 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2540 rtl_writephy(tp, 0x1f, 0x0000);
2541
2542 /* For impedance matching */
2543 rtl_writephy(tp, 0x1f, 0x0002);
2544 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2545 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2546
2547 /* PHY auto speed down */
2548 rtl_writephy(tp, 0x1f, 0x0007);
2549 rtl_writephy(tp, 0x1e, 0x002d);
2550 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2551 rtl_writephy(tp, 0x1f, 0x0000);
2552 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2553
2554 rtl_writephy(tp, 0x1f, 0x0005);
2555 rtl_writephy(tp, 0x05, 0x8b86);
2556 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2557 rtl_writephy(tp, 0x1f, 0x0000);
2558
2559 rtl_writephy(tp, 0x1f, 0x0005);
2560 rtl_writephy(tp, 0x05, 0x8b85);
2561 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2562 rtl_writephy(tp, 0x1f, 0x0007);
2563 rtl_writephy(tp, 0x1e, 0x0020);
2564 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2565 rtl_writephy(tp, 0x1f, 0x0006);
2566 rtl_writephy(tp, 0x00, 0x5a00);
2567 rtl_writephy(tp, 0x1f, 0x0000);
2568 rtl_writephy(tp, 0x0d, 0x0007);
2569 rtl_writephy(tp, 0x0e, 0x003c);
2570 rtl_writephy(tp, 0x0d, 0x4007);
2571 rtl_writephy(tp, 0x0e, 0x0000);
2572 rtl_writephy(tp, 0x0d, 0x0000);
2573}
2574
4da19633 2575static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2576{
350f7596 2577 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2578 { 0x1f, 0x0003 },
2579 { 0x08, 0x441d },
2580 { 0x01, 0x9100 },
2581 { 0x1f, 0x0000 }
2582 };
2583
4da19633 2584 rtl_writephy(tp, 0x1f, 0x0000);
2585 rtl_patchphy(tp, 0x11, 1 << 12);
2586 rtl_patchphy(tp, 0x19, 1 << 13);
2587 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2588
4da19633 2589 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2590}
2591
5a5e4443
HW		 2592static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2593{
2594 static const struct phy_reg phy_reg_init[] = {
2595 { 0x1f, 0x0005 },
2596 { 0x1a, 0x0000 },
2597 { 0x1f, 0x0000 },
2598
2599 { 0x1f, 0x0004 },
2600 { 0x1c, 0x0000 },
2601 { 0x1f, 0x0000 },
2602
2603 { 0x1f, 0x0001 },
2604 { 0x15, 0x7701 },
2605 { 0x1f, 0x0000 }
2606 };
2607
2608 /* Disable ALDPS before ram code */
2609 rtl_writephy(tp, 0x1f, 0x0000);
2610 rtl_writephy(tp, 0x18, 0x0310);
2611 msleep(100);
2612
953a12cc 2613 rtl_apply_firmware(tp);
5a5e4443
HW		 2614
2615 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2616}
2617
5615d9f1
FR		 2618static void rtl_hw_phy_config(struct net_device *dev)
2619{
2620 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2621
2622 rtl8169_print_mac_version(tp);
2623
2624 switch (tp->mac_version) {
2625 case RTL_GIGA_MAC_VER_01:
2626 break;
2627 case RTL_GIGA_MAC_VER_02:
2628 case RTL_GIGA_MAC_VER_03:
4da19633 2629 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2630 break;
2631 case RTL_GIGA_MAC_VER_04:
4da19633 2632 rtl8169sb_hw_phy_config(tp);
5615d9f1 2633 break;
2e955856 2634 case RTL_GIGA_MAC_VER_05:
4da19633 2635 rtl8169scd_hw_phy_config(tp);
2e955856 2636 break;
8c7006aa 2637 case RTL_GIGA_MAC_VER_06:
4da19633 2638 rtl8169sce_hw_phy_config(tp);
8c7006aa 2639 break;
2857ffb7
FR		 2640 case RTL_GIGA_MAC_VER_07:
2641 case RTL_GIGA_MAC_VER_08:
2642 case RTL_GIGA_MAC_VER_09:
4da19633 2643 rtl8102e_hw_phy_config(tp);
2857ffb7 2644 break;
236b8082 2645 case RTL_GIGA_MAC_VER_11:
4da19633 2646 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2647 break;
2648 case RTL_GIGA_MAC_VER_12:
4da19633 2649 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2650 break;
2651 case RTL_GIGA_MAC_VER_17:
4da19633 2652 rtl8168bef_hw_phy_config(tp);
236b8082 2653 break;
867763c1 2654 case RTL_GIGA_MAC_VER_18:
4da19633 2655 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2656 break;
2657 case RTL_GIGA_MAC_VER_19:
4da19633 2658 rtl8168c_1_hw_phy_config(tp);
867763c1 2659 break;
7da97ec9 2660 case RTL_GIGA_MAC_VER_20:
4da19633 2661 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2662 break;
197ff761 2663 case RTL_GIGA_MAC_VER_21:
4da19633 2664 rtl8168c_3_hw_phy_config(tp);
197ff761 2665 break;
6fb07058 2666 case RTL_GIGA_MAC_VER_22:
4da19633 2667 rtl8168c_4_hw_phy_config(tp);
6fb07058 2668 break;
ef3386f0 2669 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2670 case RTL_GIGA_MAC_VER_24:
4da19633 2671 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2672 break;
5b538df9 2673 case RTL_GIGA_MAC_VER_25:
bca03d5f 2674 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2675 break;
2676 case RTL_GIGA_MAC_VER_26:
bca03d5f 2677 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2678 break;
2679 case RTL_GIGA_MAC_VER_27:
4da19633 2680 rtl8168d_3_hw_phy_config(tp);
5b538df9 2681 break;
e6de30d6 2682 case RTL_GIGA_MAC_VER_28:
2683 rtl8168d_4_hw_phy_config(tp);
2684 break;
5a5e4443
HW		 2685 case RTL_GIGA_MAC_VER_29:
2686 case RTL_GIGA_MAC_VER_30:
2687 rtl8105e_hw_phy_config(tp);
2688 break;
cecb5fd7
FR		 2689 case RTL_GIGA_MAC_VER_31:
2690 /* None. */
2691 break;
01dc7fec 2692 case RTL_GIGA_MAC_VER_32:
01dc7fec 2693 case RTL_GIGA_MAC_VER_33:
15ecd039 2694 rtl8168e_hw_phy_config(tp);
01dc7fec 2695 break;
ef3386f0 2696
5615d9f1
FR		 2697 default:
2698 break;
2699 }
2700}
2701
1da177e4
LT		 2702static void rtl8169_phy_timer(unsigned long __opaque)
2703{
2704 struct net_device *dev = (struct net_device *)__opaque;
2705 struct rtl8169_private *tp = netdev_priv(dev);
2706 struct timer_list *timer = &tp->timer;
2707 void __iomem *ioaddr = tp->mmio_addr;
2708 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2709
bcf0bf90 2710 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2711
1da177e4
LT		 2712 spin_lock_irq(&tp->lock);
2713
4da19633 2714 if (tp->phy_reset_pending(tp)) {
5b0384f4 2715 /*
1da177e4
LT		 2716 * A busy loop could burn quite a few cycles on nowadays CPU.
2717 * Let's delay the execution of the timer for a few ticks.
2718 */
2719 timeout = HZ/10;
2720 goto out_mod_timer;
2721 }
2722
2723 if (tp->link_ok(ioaddr))
2724 goto out_unlock;
2725
bf82c189 2726 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2727
4da19633 2728 tp->phy_reset_enable(tp);
1da177e4
LT		 2729
2730out_mod_timer:
2731 mod_timer(timer, jiffies + timeout);
2732out_unlock:
2733 spin_unlock_irq(&tp->lock);
2734}
2735
1da177e4
LT		 2736#ifdef CONFIG_NET_POLL_CONTROLLER
2737/*
2738 * Polling 'interrupt' - used by things like netconsole to send skbs
2739 * without having to re-enable interrupts. It's not called while
2740 * the interrupt routine is executing.
2741 */
2742static void rtl8169_netpoll(struct net_device *dev)
2743{
2744 struct rtl8169_private *tp = netdev_priv(dev);
2745 struct pci_dev *pdev = tp->pci_dev;
2746
2747 disable_irq(pdev->irq);
7d12e780 2748 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2749 enable_irq(pdev->irq);
2750}
2751#endif
2752
2753static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2754 void __iomem *ioaddr)
2755{
2756 iounmap(ioaddr);
2757 pci_release_regions(pdev);
87aeec76 2758 pci_clear_mwi(pdev);
1da177e4
LT		 2759 pci_disable_device(pdev);
2760 free_netdev(dev);
2761}
2762
bf793295
FR		 2763static void rtl8169_phy_reset(struct net_device *dev,
2764 struct rtl8169_private *tp)
2765{
07d3f51f 2766 unsigned int i;
bf793295 2767
4da19633 2768 tp->phy_reset_enable(tp);
bf793295 2769 for (i = 0; i < 100; i++) {
4da19633 2770 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2771 return;
2772 msleep(1);
2773 }
bf82c189 2774 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2775}
2776
4ff96fa6
FR		 2777static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2778{
2779 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2780
5615d9f1 2781 rtl_hw_phy_config(dev);
4ff96fa6 2782
77332894
MS		 2783 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2784 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2785 RTL_W8(0x82, 0x01);
2786 }
4ff96fa6 2787
6dccd16b
FR		 2788 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2789
2790 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2791 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2792
bcf0bf90 2793 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2794 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2795 RTL_W8(0x82, 0x01);
2796 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2797 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2798 }
2799
bf793295
FR		 2800 rtl8169_phy_reset(dev, tp);
2801
54405cde 2802 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 2803 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2804 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2805 (tp->mii.supports_gmii ?
2806 ADVERTISED_1000baseT_Half |
2807 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2808
bf82c189
JP		 2809 if (RTL_R8(PHYstatus) & TBI_Enable)
2810 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2811}
2812
773d2021
FR		 2813static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2814{
2815 void __iomem *ioaddr = tp->mmio_addr;
2816 u32 high;
2817 u32 low;
2818
2819 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2820 high = addr[4] | (addr[5] << 8);
2821
2822 spin_lock_irq(&tp->lock);
2823
2824 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2825
773d2021 2826 RTL_W32(MAC4, high);
908ba2bf 2827 RTL_R32(MAC4);
2828
78f1cd02 2829 RTL_W32(MAC0, low);
908ba2bf 2830 RTL_R32(MAC0);
2831
773d2021
FR		 2832 RTL_W8(Cfg9346, Cfg9346_Lock);
2833
2834 spin_unlock_irq(&tp->lock);
2835}
2836
2837static int rtl_set_mac_address(struct net_device *dev, void *p)
2838{
2839 struct rtl8169_private *tp = netdev_priv(dev);
2840 struct sockaddr *addr = p;
2841
2842 if (!is_valid_ether_addr(addr->sa_data))
2843 return -EADDRNOTAVAIL;
2844
2845 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2846
2847 rtl_rar_set(tp, dev->dev_addr);
2848
2849 return 0;
2850}
2851
5f787a1a
FR		 2852static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2853{
2854 struct rtl8169_private *tp = netdev_priv(dev);
2855 struct mii_ioctl_data *data = if_mii(ifr);
2856
8b4ab28d
FR		 2857 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2858}
5f787a1a 2859
cecb5fd7
FR		 2860static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2861 struct mii_ioctl_data *data, int cmd)
8b4ab28d 2862{
5f787a1a
FR		 2863 switch (cmd) {
2864 case SIOCGMIIPHY:
2865 data->phy_id = 32; /* Internal PHY */
2866 return 0;
2867
2868 case SIOCGMIIREG:
4da19633 2869 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2870 return 0;
2871
2872 case SIOCSMIIREG:
4da19633 2873 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2874 return 0;
2875 }
2876 return -EOPNOTSUPP;
2877}
2878
8b4ab28d
FR		 2879static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2880{
2881 return -EOPNOTSUPP;
2882}
2883
0e485150
FR		 2884static const struct rtl_cfg_info {
2885 void (*hw_start)(struct net_device *);
2886 unsigned int region;
2887 unsigned int align;
2888 u16 intr_event;
2889 u16 napi_event;
ccdffb9a 2890 unsigned features;
f21b75e9 2891 u8 default_ver;
0e485150
FR		 2892} rtl_cfg_infos [] = {
2893 [RTL_CFG_0] = {
2894 .hw_start = rtl_hw_start_8169,
2895 .region = 1,
e9f63f30 2896 .align = 0,
0e485150
FR		 2897 .intr_event = SYSErr | LinkChg | RxOverflow |
2898 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2899 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2900 .features = RTL_FEATURE_GMII,
2901 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2902 },
2903 [RTL_CFG_1] = {
2904 .hw_start = rtl_hw_start_8168,
2905 .region = 2,
2906 .align = 8,
53f57357 2907 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2908 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2909 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2910 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2911 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2912 },
2913 [RTL_CFG_2] = {
2914 .hw_start = rtl_hw_start_8101,
2915 .region = 2,
2916 .align = 8,
2917 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2918 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2919 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2920 .features = RTL_FEATURE_MSI,
2921 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2922 }
2923};
2924
fbac58fc
FR		 2925/* Cfg9346_Unlock assumed. */
2926static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2927 const struct rtl_cfg_info *cfg)
2928{
2929 unsigned msi = 0;
2930 u8 cfg2;
2931
2932 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2933 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2934 if (pci_enable_msi(pdev)) {
2935 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2936 } else {
2937 cfg2 |= MSIEnable;
2938 msi = RTL_FEATURE_MSI;
2939 }
2940 }
2941 RTL_W8(Config2, cfg2);
2942 return msi;
2943}
2944
2945static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2946{
2947 if (tp->features & RTL_FEATURE_MSI) {
2948 pci_disable_msi(pdev);
2949 tp->features &= ~RTL_FEATURE_MSI;
2950 }
2951}
2952
8b4ab28d
FR		 2953static const struct net_device_ops rtl8169_netdev_ops = {
2954 .ndo_open = rtl8169_open,
2955 .ndo_stop = rtl8169_close,
2956 .ndo_get_stats = rtl8169_get_stats,
00829823 2957 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2958 .ndo_tx_timeout = rtl8169_tx_timeout,
2959 .ndo_validate_addr = eth_validate_addr,
2960 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2961 .ndo_fix_features = rtl8169_fix_features,
2962 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2963 .ndo_set_mac_address = rtl_set_mac_address,
2964 .ndo_do_ioctl = rtl8169_ioctl,
2965 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2966#ifdef CONFIG_NET_POLL_CONTROLLER
2967 .ndo_poll_controller = rtl8169_netpoll,
2968#endif
2969
2970};
2971
c0e45c1c 2972static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2973{
2974 struct mdio_ops *ops = &tp->mdio_ops;
2975
2976 switch (tp->mac_version) {
2977 case RTL_GIGA_MAC_VER_27:
2978 ops->write = r8168dp_1_mdio_write;
2979 ops->read = r8168dp_1_mdio_read;
2980 break;
e6de30d6 2981 case RTL_GIGA_MAC_VER_28:
4804b3b3 2982 case RTL_GIGA_MAC_VER_31:
e6de30d6 2983 ops->write = r8168dp_2_mdio_write;
2984 ops->read = r8168dp_2_mdio_read;
2985 break;
c0e45c1c 2986 default:
2987 ops->write = r8169_mdio_write;
2988 ops->read = r8169_mdio_read;
2989 break;
2990 }
2991}
2992
065c27c1 2993static void r810x_phy_power_down(struct rtl8169_private *tp)
2994{
2995 rtl_writephy(tp, 0x1f, 0x0000);
2996 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2997}
2998
2999static void r810x_phy_power_up(struct rtl8169_private *tp)
3000{
3001 rtl_writephy(tp, 0x1f, 0x0000);
3002 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3003}
3004
3005static void r810x_pll_power_down(struct rtl8169_private *tp)
3006{
3007 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3008 rtl_writephy(tp, 0x1f, 0x0000);
3009 rtl_writephy(tp, MII_BMCR, 0x0000);
3010 return;
3011 }
3012
3013 r810x_phy_power_down(tp);
3014}
3015
3016static void r810x_pll_power_up(struct rtl8169_private *tp)
3017{
3018 r810x_phy_power_up(tp);
3019}
3020
3021static void r8168_phy_power_up(struct rtl8169_private *tp)
3022{
3023 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3024 switch (tp->mac_version) {
3025 case RTL_GIGA_MAC_VER_11:
3026 case RTL_GIGA_MAC_VER_12:
3027 case RTL_GIGA_MAC_VER_17:
3028 case RTL_GIGA_MAC_VER_18:
3029 case RTL_GIGA_MAC_VER_19:
3030 case RTL_GIGA_MAC_VER_20:
3031 case RTL_GIGA_MAC_VER_21:
3032 case RTL_GIGA_MAC_VER_22:
3033 case RTL_GIGA_MAC_VER_23:
3034 case RTL_GIGA_MAC_VER_24:
3035 case RTL_GIGA_MAC_VER_25:
3036 case RTL_GIGA_MAC_VER_26:
3037 case RTL_GIGA_MAC_VER_27:
3038 case RTL_GIGA_MAC_VER_28:
3039 case RTL_GIGA_MAC_VER_31:
3040 rtl_writephy(tp, 0x0e, 0x0000);
3041 break;
3042 default:
3043 break;
3044 }
065c27c1 3045 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3046}
3047
3048static void r8168_phy_power_down(struct rtl8169_private *tp)
3049{
3050 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3051 switch (tp->mac_version) {
3052 case RTL_GIGA_MAC_VER_32:
3053 case RTL_GIGA_MAC_VER_33:
3054 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3055 break;
3056
3057 case RTL_GIGA_MAC_VER_11:
3058 case RTL_GIGA_MAC_VER_12:
3059 case RTL_GIGA_MAC_VER_17:
3060 case RTL_GIGA_MAC_VER_18:
3061 case RTL_GIGA_MAC_VER_19:
3062 case RTL_GIGA_MAC_VER_20:
3063 case RTL_GIGA_MAC_VER_21:
3064 case RTL_GIGA_MAC_VER_22:
3065 case RTL_GIGA_MAC_VER_23:
3066 case RTL_GIGA_MAC_VER_24:
3067 case RTL_GIGA_MAC_VER_25:
3068 case RTL_GIGA_MAC_VER_26:
3069 case RTL_GIGA_MAC_VER_27:
3070 case RTL_GIGA_MAC_VER_28:
3071 case RTL_GIGA_MAC_VER_31:
3072 rtl_writephy(tp, 0x0e, 0x0200);
3073 default:
3074 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3075 break;
3076 }
065c27c1 3077}
3078
3079static void r8168_pll_power_down(struct rtl8169_private *tp)
3080{
3081 void __iomem *ioaddr = tp->mmio_addr;
3082
cecb5fd7
FR		 3083 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3084 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3085 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3086 r8168dp_check_dash(tp)) {
065c27c1 3087 return;
5d2e1957 3088 }
065c27c1 3089
cecb5fd7
FR		 3090 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3091 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3092 (RTL_R16(CPlusCmd) & ASF)) {
3093 return;
3094 }
3095
01dc7fec 3096 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3097 tp->mac_version == RTL_GIGA_MAC_VER_33)
3098 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3099
065c27c1 3100 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3101 rtl_writephy(tp, 0x1f, 0x0000);
3102 rtl_writephy(tp, MII_BMCR, 0x0000);
3103
3104 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3105 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3106 return;
3107 }
3108
3109 r8168_phy_power_down(tp);
3110
3111 switch (tp->mac_version) {
3112 case RTL_GIGA_MAC_VER_25:
3113 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3114 case RTL_GIGA_MAC_VER_27:
3115 case RTL_GIGA_MAC_VER_28:
4804b3b3 3116 case RTL_GIGA_MAC_VER_31:
01dc7fec 3117 case RTL_GIGA_MAC_VER_32:
3118 case RTL_GIGA_MAC_VER_33:
065c27c1 3119 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3120 break;
3121 }
3122}
3123
3124static void r8168_pll_power_up(struct rtl8169_private *tp)
3125{
3126 void __iomem *ioaddr = tp->mmio_addr;
3127
cecb5fd7
FR		 3128 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3129 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3130 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3131 r8168dp_check_dash(tp)) {
065c27c1 3132 return;
5d2e1957 3133 }
065c27c1 3134
3135 switch (tp->mac_version) {
3136 case RTL_GIGA_MAC_VER_25:
3137 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3138 case RTL_GIGA_MAC_VER_27:
3139 case RTL_GIGA_MAC_VER_28:
4804b3b3 3140 case RTL_GIGA_MAC_VER_31:
01dc7fec 3141 case RTL_GIGA_MAC_VER_32:
3142 case RTL_GIGA_MAC_VER_33:
065c27c1 3143 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3144 break;
3145 }
3146
3147 r8168_phy_power_up(tp);
3148}
3149
3150static void rtl_pll_power_op(struct rtl8169_private *tp,
3151 void (*op)(struct rtl8169_private *))
3152{
3153 if (op)
3154 op(tp);
3155}
3156
3157static void rtl_pll_power_down(struct rtl8169_private *tp)
3158{
3159 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3160}
3161
3162static void rtl_pll_power_up(struct rtl8169_private *tp)
3163{
3164 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3165}
3166
3167static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3168{
3169 struct pll_power_ops *ops = &tp->pll_power_ops;
3170
3171 switch (tp->mac_version) {
3172 case RTL_GIGA_MAC_VER_07:
3173 case RTL_GIGA_MAC_VER_08:
3174 case RTL_GIGA_MAC_VER_09:
3175 case RTL_GIGA_MAC_VER_10:
3176 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3177 case RTL_GIGA_MAC_VER_29:
3178 case RTL_GIGA_MAC_VER_30:
065c27c1 3179 ops->down = r810x_pll_power_down;
3180 ops->up = r810x_pll_power_up;
3181 break;
3182
3183 case RTL_GIGA_MAC_VER_11:
3184 case RTL_GIGA_MAC_VER_12:
3185 case RTL_GIGA_MAC_VER_17:
3186 case RTL_GIGA_MAC_VER_18:
3187 case RTL_GIGA_MAC_VER_19:
3188 case RTL_GIGA_MAC_VER_20:
3189 case RTL_GIGA_MAC_VER_21:
3190 case RTL_GIGA_MAC_VER_22:
3191 case RTL_GIGA_MAC_VER_23:
3192 case RTL_GIGA_MAC_VER_24:
3193 case RTL_GIGA_MAC_VER_25:
3194 case RTL_GIGA_MAC_VER_26:
3195 case RTL_GIGA_MAC_VER_27:
e6de30d6 3196 case RTL_GIGA_MAC_VER_28:
4804b3b3 3197 case RTL_GIGA_MAC_VER_31:
01dc7fec 3198 case RTL_GIGA_MAC_VER_32:
3199 case RTL_GIGA_MAC_VER_33:
065c27c1 3200 ops->down = r8168_pll_power_down;
3201 ops->up = r8168_pll_power_up;
3202 break;
3203
3204 default:
3205 ops->down = NULL;
3206 ops->up = NULL;
3207 break;
3208 }
3209}
3210
6f43adc8
FR		 3211static void rtl_hw_reset(struct rtl8169_private *tp)
3212{
3213 void __iomem *ioaddr = tp->mmio_addr;
3214 int i;
3215
3216 /* Soft reset the chip. */
3217 RTL_W8(ChipCmd, CmdReset);
3218
3219 /* Check that the chip has finished the reset. */
3220 for (i = 0; i < 100; i++) {
3221 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3222 break;
3223 msleep_interruptible(1);
3224 }
3225}
3226
1da177e4 3227static int __devinit
4ff96fa6 3228rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3229{
0e485150
FR		 3230 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3231 const unsigned int region = cfg->region;
1da177e4 3232 struct rtl8169_private *tp;
ccdffb9a 3233 struct mii_if_info *mii;
4ff96fa6
FR		 3234 struct net_device *dev;
3235 void __iomem *ioaddr;
2b7b4318 3236 int chipset, i;
07d3f51f 3237 int rc;
1da177e4 3238
4ff96fa6
FR		 3239 if (netif_msg_drv(&debug)) {
3240 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3241 MODULENAME, RTL8169_VERSION);
3242 }
1da177e4 3243
1da177e4 3244 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3245 if (!dev) {
b57b7e5a 3246 if (netif_msg_drv(&debug))
9b91cf9d 3247 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3248 rc = -ENOMEM;
3249 goto out;
1da177e4
LT		 3250 }
3251
1da177e4 3252 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3253 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3254 tp = netdev_priv(dev);
c4028958 3255 tp->dev = dev;
21e197f2 3256 tp->pci_dev = pdev;
b57b7e5a 3257 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3258
ccdffb9a
FR		 3259 mii = &tp->mii;
3260 mii->dev = dev;
3261 mii->mdio_read = rtl_mdio_read;
3262 mii->mdio_write = rtl_mdio_write;
3263 mii->phy_id_mask = 0x1f;
3264 mii->reg_num_mask = 0x1f;
3265 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3266
ba04c7c9
SG		 3267 /* disable ASPM completely as that cause random device stop working
3268 * problems as well as full system hangs for some PCIe devices users */
3269 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3270 PCIE_LINK_STATE_CLKPM);
3271
1da177e4
LT		 3272 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3273 rc = pci_enable_device(pdev);
b57b7e5a 3274 if (rc < 0) {
bf82c189 3275 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3276 goto err_out_free_dev_1;
1da177e4
LT		 3277 }
3278
87aeec76 3279 if (pci_set_mwi(pdev) < 0)
3280 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3281
1da177e4 3282 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3283 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3284 netif_err(tp, probe, dev,
3285 "region #%d not an MMIO resource, aborting\n",
3286 region);
1da177e4 3287 rc = -ENODEV;
87aeec76 3288 goto err_out_mwi_2;
1da177e4 3289 }
4ff96fa6 3290
1da177e4 3291 /* check for weird/broken PCI region reporting */
bcf0bf90 3292 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3293 netif_err(tp, probe, dev,
3294 "Invalid PCI region size(s), aborting\n");
1da177e4 3295 rc = -ENODEV;
87aeec76 3296 goto err_out_mwi_2;
1da177e4
LT		 3297 }
3298
3299 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3300 if (rc < 0) {
bf82c189 3301 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3302 goto err_out_mwi_2;
1da177e4
LT		 3303 }
3304
d24e9aaf 3305 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3306
3307 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3308 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3309 tp->cp_cmd |= PCIDAC;
3310 dev->features |= NETIF_F_HIGHDMA;
3311 } else {
284901a9 3312 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3313 if (rc < 0) {
bf82c189 3314 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3315 goto err_out_free_res_3;
1da177e4
LT		 3316 }
3317 }
3318
1da177e4 3319 /* ioremap MMIO region */
bcf0bf90 3320 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3321 if (!ioaddr) {
bf82c189 3322 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3323 rc = -EIO;
87aeec76 3324 goto err_out_free_res_3;
1da177e4 3325 }
6f43adc8 3326 tp->mmio_addr = ioaddr;
1da177e4 3327
4300e8c7
DM		 3328 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3329 if (!tp->pcie_cap)
3330 netif_info(tp, probe, dev, "no PCI Express capability\n");
3331
d78ad8cb 3332 RTL_W16(IntrMask, 0x0000);
1da177e4 3333
6f43adc8 3334 rtl_hw_reset(tp);
1da177e4 3335
d78ad8cb
KW		 3336 RTL_W16(IntrStatus, 0xffff);
3337
ca52efd5 3338 pci_set_master(pdev);
3339
1da177e4
LT		 3340 /* Identify chip attached to board */
3341 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3342
7a8fc77b
FR		 3343 /*
3344 * Pretend we are using VLANs; This bypasses a nasty bug where
3345 * Interrupts stop flowing on high load on 8110SCd controllers.
3346 */
3347 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3348 tp->cp_cmd |= RxVlan;
3349
c0e45c1c 3350 rtl_init_mdio_ops(tp);
065c27c1 3351 rtl_init_pll_power_ops(tp);
c0e45c1c 3352
f21b75e9
JD		 3353 /* Use appropriate default if unknown */
3354 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3355 netif_notice(tp, probe, dev,
3356 "unknown MAC, using family default\n");
f21b75e9
JD		 3357 tp->mac_version = cfg->default_ver;
3358 }
3359
1da177e4 3360 rtl8169_print_mac_version(tp);
1da177e4 3361
cee60c37 3362 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3363 if (tp->mac_version == rtl_chip_info[i].mac_version)
3364 break;
3365 }
cee60c37 3366 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3367 dev_err(&pdev->dev,
3368 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3369 goto err_out_msi_4;
1da177e4 3370 }
2b7b4318
FR		 3371 chipset = i;
3372 tp->txd_version = rtl_chip_info[chipset].txd_version;
1da177e4 3373
5d06a99f
FR		 3374 RTL_W8(Cfg9346, Cfg9346_Unlock);
3375 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3376 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3377 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3378 tp->features |= RTL_FEATURE_WOL;
3379 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3380 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3381 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3382 RTL_W8(Cfg9346, Cfg9346_Lock);
3383
66ec5d4f
FR		 3384 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3385 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3386 tp->set_speed = rtl8169_set_speed_tbi;
3387 tp->get_settings = rtl8169_gset_tbi;
3388 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3389 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3390 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3391 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3392 } else {
3393 tp->set_speed = rtl8169_set_speed_xmii;
3394 tp->get_settings = rtl8169_gset_xmii;
3395 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3396 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3397 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3398 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3399 }
3400
df58ef51
FR		 3401 spin_lock_init(&tp->lock);
3402
7bf6bf48 3403 /* Get MAC address */
1da177e4
LT		 3404 for (i = 0; i < MAC_ADDR_LEN; i++)
3405 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3406 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3407
1da177e4 3408 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3409 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3410 dev->irq = pdev->irq;
3411 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3412
bea3348e 3413 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3414
350fb32a
MM		 3415 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3416 * properly for all devices */
3417 dev->features |= NETIF_F_RXCSUM |
3418 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3419
3420 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3421 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3422 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3423 NETIF_F_HIGHDMA;
3424
3425 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3426 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3427 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3428
3429 tp->intr_mask = 0xffff;
0e485150
FR		 3430 tp->hw_start = cfg->hw_start;
3431 tp->intr_event = cfg->intr_event;
3432 tp->napi_event = cfg->napi_event;
1da177e4 3433
2efa53f3
FR		 3434 init_timer(&tp->timer);
3435 tp->timer.data = (unsigned long) dev;
3436 tp->timer.function = rtl8169_phy_timer;
3437
953a12cc
FR		 3438 tp->fw = RTL_FIRMWARE_UNKNOWN;
3439
1da177e4 3440 rc = register_netdev(dev);
4ff96fa6 3441 if (rc < 0)
87aeec76 3442 goto err_out_msi_4;
1da177e4
LT		 3443
3444 pci_set_drvdata(pdev, dev);
3445
bf82c189 3446 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2b7b4318 3447 rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3448 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3449
cecb5fd7
FR		 3450 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3451 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3452 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3453 rtl8168_driver_start(tp);
e6de30d6 3454 }
b646d900 3455
8b76ab39 3456 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3457
f3ec4f87
AS		 3458 if (pci_dev_run_wake(pdev))
3459 pm_runtime_put_noidle(&pdev->dev);
e1759441 3460
0d672e9f
IV		 3461 netif_carrier_off(dev);
3462
4ff96fa6
FR		 3463out:
3464 return rc;
1da177e4 3465
87aeec76 3466err_out_msi_4:
fbac58fc 3467 rtl_disable_msi(pdev, tp);
4ff96fa6 3468 iounmap(ioaddr);
87aeec76 3469err_out_free_res_3:
4ff96fa6 3470 pci_release_regions(pdev);
87aeec76 3471err_out_mwi_2:
4ff96fa6 3472 pci_clear_mwi(pdev);
4ff96fa6
FR		 3473 pci_disable_device(pdev);
3474err_out_free_dev_1:
3475 free_netdev(dev);
3476 goto out;
1da177e4
LT		 3477}
3478
07d3f51f 3479static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3480{
3481 struct net_device *dev = pci_get_drvdata(pdev);
3482 struct rtl8169_private *tp = netdev_priv(dev);
3483
cecb5fd7
FR		 3484 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3485 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3486 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3487 rtl8168_driver_stop(tp);
e6de30d6 3488 }
b646d900 3489
23f333a2 3490 cancel_delayed_work_sync(&tp->task);
eb2a021c 3491
1da177e4 3492 unregister_netdev(dev);
cc098dc7 3493
953a12cc
FR		 3494 rtl_release_firmware(tp);
3495
f3ec4f87
AS		 3496 if (pci_dev_run_wake(pdev))
3497 pm_runtime_get_noresume(&pdev->dev);
e1759441 3498
cc098dc7
IV		 3499 /* restore original MAC address */
3500 rtl_rar_set(tp, dev->perm_addr);
3501
fbac58fc 3502 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3503 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3504 pci_set_drvdata(pdev, NULL);
3505}
3506
953a12cc
FR		 3507static void rtl_request_firmware(struct rtl8169_private *tp)
3508{
953a12cc 3509 /* Return early if the firmware is already loaded / cached. */
31bd204f
FR		 3510 if (IS_ERR(tp->fw)) {
3511 const char *name;
953a12cc 3512
31bd204f
FR		 3513 name = rtl_lookup_firmware_name(tp);
3514 if (name) {
953a12cc
FR		 3515 int rc;
3516
3517 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
31bd204f
FR		 3518 if (rc >= 0)
3519 return;
3520
3521 netif_warn(tp, ifup, tp->dev, "unable to load "
3522 "firmware patch %s (%d)\n", name, rc);
953a12cc 3523 }
31bd204f 3524 tp->fw = NULL;
953a12cc 3525 }
953a12cc
FR		 3526}
3527
1da177e4
LT		 3528static int rtl8169_open(struct net_device *dev)
3529{
3530 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3531 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3532 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3533 int retval = -ENOMEM;
1da177e4 3534
e1759441 3535 pm_runtime_get_sync(&pdev->dev);
1da177e4 3536
1da177e4
LT		 3537 /*
3538 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3539 * dma_alloc_coherent provides more.
1da177e4 3540 */
82553bb6
SG		 3541 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3542 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3543 if (!tp->TxDescArray)
e1759441 3544 goto err_pm_runtime_put;
1da177e4 3545
82553bb6
SG		 3546 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3547 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3548 if (!tp->RxDescArray)
99f252b0 3549 goto err_free_tx_0;
1da177e4
LT		 3550
3551 retval = rtl8169_init_ring(dev);
3552 if (retval < 0)
99f252b0 3553 goto err_free_rx_1;
1da177e4 3554
c4028958 3555 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3556
99f252b0
FR		 3557 smp_mb();
3558
953a12cc
FR		 3559 rtl_request_firmware(tp);
3560
fbac58fc
FR		 3561 retval = request_irq(dev->irq, rtl8169_interrupt,
3562 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3563 dev->name, dev);
3564 if (retval < 0)
953a12cc 3565 goto err_release_fw_2;
99f252b0 3566
bea3348e 3567 napi_enable(&tp->napi);
bea3348e 3568
eee3a96c 3569 rtl8169_init_phy(dev, tp);
3570
350fb32a 3571 rtl8169_set_features(dev, dev->features);
eee3a96c 3572
065c27c1 3573 rtl_pll_power_up(tp);
3574
07ce4064 3575 rtl_hw_start(dev);
1da177e4 3576
e1759441
RW		 3577 tp->saved_wolopts = 0;
3578 pm_runtime_put_noidle(&pdev->dev);
3579
eee3a96c 3580 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3581out:
3582 return retval;
3583
953a12cc
FR		 3584err_release_fw_2:
3585 rtl_release_firmware(tp);
99f252b0
FR		 3586 rtl8169_rx_clear(tp);
3587err_free_rx_1:
82553bb6
SG		 3588 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3589 tp->RxPhyAddr);
e1759441 3590 tp->RxDescArray = NULL;
99f252b0 3591err_free_tx_0:
82553bb6
SG		 3592 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3593 tp->TxPhyAddr);
e1759441
RW		 3594 tp->TxDescArray = NULL;
3595err_pm_runtime_put:
3596 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3597 goto out;
3598}
3599
e6de30d6 3600static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3601{
e6de30d6 3602 void __iomem *ioaddr = tp->mmio_addr;
3603
1da177e4
LT		 3604 /* Disable interrupts */
3605 rtl8169_irq_mask_and_ack(ioaddr);
3606
5d2e1957 3607 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3608 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3609 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3610 while (RTL_R8(TxPoll) & NPQ)
3611 udelay(20);
3612
3613 }
3614
1da177e4
LT		 3615 /* Reset the chipset */
3616 RTL_W8(ChipCmd, CmdReset);
3617
3618 /* PCI commit */
3619 RTL_R8(ChipCmd);
3620}
3621
7f796d83 3622static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3623{
3624 void __iomem *ioaddr = tp->mmio_addr;
3625 u32 cfg = rtl8169_rx_config;
3626
2b7b4318 3627 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3628 RTL_W32(RxConfig, cfg);
3629
3630 /* Set DMA burst size and Interframe Gap Time */
3631 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3632 (InterFrameGap << TxInterFrameGapShift));
3633}
3634
07ce4064 3635static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3636{
3637 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3638
6f43adc8 3639 rtl_hw_reset(tp);
1da177e4 3640
07ce4064
FR		 3641 tp->hw_start(dev);
3642
07ce4064
FR		 3643 netif_start_queue(dev);
3644}
3645
7f796d83
FR		 3646static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3647 void __iomem *ioaddr)
3648{
3649 /*
3650 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3651 * register to be written before TxDescAddrLow to work.
3652 * Switching from MMIO to I/O access fixes the issue as well.
3653 */
3654 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3655 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3656 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3657 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3658}
3659
3660static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3661{
3662 u16 cmd;
3663
3664 cmd = RTL_R16(CPlusCmd);
3665 RTL_W16(CPlusCmd, cmd);
3666 return cmd;
3667}
3668
fdd7b4c3 3669static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3670{
3671 /* Low hurts. Let's disable the filtering. */
207d6e87 3672 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3673}
3674
6dccd16b
FR		 3675static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3676{
350f7596 3677 static const struct {
6dccd16b
FR		 3678 u32 mac_version;
3679 u32 clk;
3680 u32 val;
3681 } cfg2_info [] = {
3682 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3683 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3684 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3685 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3686 }, *p = cfg2_info;
3687 unsigned int i;
3688 u32 clk;
3689
3690 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3691 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3692 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3693 RTL_W32(0x7c, p->val);
3694 break;
3695 }
3696 }
3697}
3698
07ce4064
FR		 3699static void rtl_hw_start_8169(struct net_device *dev)
3700{
3701 struct rtl8169_private *tp = netdev_priv(dev);
3702 void __iomem *ioaddr = tp->mmio_addr;
3703 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3704
9cb427b6
FR		 3705 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3706 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3707 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3708 }
3709
1da177e4 3710 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 3711 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3712 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3713 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3714 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 3715 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3716
f0298f81 3717 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3718
6f0333b8 3719 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3720
cecb5fd7
FR		 3721 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3722 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3723 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3724 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 3725 rtl_set_rx_tx_config_registers(tp);
1da177e4 3726
7f796d83 3727 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3728
cecb5fd7
FR		 3729 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3730 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 3731 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3732 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3733 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3734 }
3735
bcf0bf90
FR		 3736 RTL_W16(CPlusCmd, tp->cp_cmd);
3737
6dccd16b
FR		 3738 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3739
1da177e4
LT		 3740 /*
3741 * Undocumented corner. Supposedly:
3742 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3743 */
3744 RTL_W16(IntrMitigate, 0x0000);
3745
7f796d83 3746 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3747
cecb5fd7
FR		 3748 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3749 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3750 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3751 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 3752 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3753 rtl_set_rx_tx_config_registers(tp);
3754 }
3755
1da177e4 3756 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3757
3758 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3759 RTL_R8(IntrMask);
1da177e4
LT		 3760
3761 RTL_W32(RxMissed, 0);
3762
07ce4064 3763 rtl_set_rx_mode(dev);
1da177e4
LT		 3764
3765 /* no early-rx interrupts */
3766 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3767
3768 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3769 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3770}
1da177e4 3771
9c14ceaf 3772static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3773{
9c14ceaf
FR		 3774 struct net_device *dev = pci_get_drvdata(pdev);
3775 struct rtl8169_private *tp = netdev_priv(dev);
3776 int cap = tp->pcie_cap;
3777
3778 if (cap) {
3779 u16 ctl;
458a9f61 3780
9c14ceaf
FR		 3781 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3782 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3783 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3784 }
458a9f61
FR		 3785}
3786
650e8d5d 3787static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3788{
3789 u32 csi;
3790
3791 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3792 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3793}
3794
e6de30d6 3795static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3796{
3797 rtl_csi_access_enable(ioaddr, 0x17000000);
3798}
3799
650e8d5d 3800static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3801{
3802 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3803}
3804
3805struct ephy_info {
3806 unsigned int offset;
3807 u16 mask;
3808 u16 bits;
3809};
3810
350f7596 3811static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3812{
3813 u16 w;
3814
3815 while (len-- > 0) {
3816 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3817 rtl_ephy_write(ioaddr, e->offset, w);
3818 e++;
3819 }
3820}
3821
b726e493
FR		 3822static void rtl_disable_clock_request(struct pci_dev *pdev)
3823{
3824 struct net_device *dev = pci_get_drvdata(pdev);
3825 struct rtl8169_private *tp = netdev_priv(dev);
3826 int cap = tp->pcie_cap;
3827
3828 if (cap) {
3829 u16 ctl;
3830
3831 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3832 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3833 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3834 }
3835}
3836
e6de30d6 3837static void rtl_enable_clock_request(struct pci_dev *pdev)
3838{
3839 struct net_device *dev = pci_get_drvdata(pdev);
3840 struct rtl8169_private *tp = netdev_priv(dev);
3841 int cap = tp->pcie_cap;
3842
3843 if (cap) {
3844 u16 ctl;
3845
3846 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3847 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3848 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3849 }
3850}
3851
b726e493
FR		 3852#define R8168_CPCMD_QUIRK_MASK (\
3853 EnableBist | \
3854 Mac_dbgo_oe | \
3855 Force_half_dup | \
3856 Force_rxflow_en | \
3857 Force_txflow_en | \
3858 Cxpl_dbg_sel | \
3859 ASF | \
3860 PktCntrDisable | \
3861 Mac_dbgo_sel)
3862
219a1e9d
FR		 3863static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3864{
b726e493
FR		 3865 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3866
3867 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3868
2e68ae44
FR		 3869 rtl_tx_performance_tweak(pdev,
3870 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3871}
3872
3873static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3874{
3875 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3876
f0298f81 3877 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3878
3879 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3880}
3881
3882static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3883{
b726e493
FR		 3884 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3885
3886 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3887
219a1e9d 3888 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3889
3890 rtl_disable_clock_request(pdev);
3891
3892 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3893}
3894
ef3386f0 3895static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3896{
350f7596 3897 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3898 { 0x01, 0, 0x0001 },
3899 { 0x02, 0x0800, 0x1000 },
3900 { 0x03, 0, 0x0042 },
3901 { 0x06, 0x0080, 0x0000 },
3902 { 0x07, 0, 0x2000 }
3903 };
3904
650e8d5d 3905 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3906
3907 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3908
219a1e9d
FR		 3909 __rtl_hw_start_8168cp(ioaddr, pdev);
3910}
3911
ef3386f0
FR		 3912static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3913{
650e8d5d 3914 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3915
3916 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3917
3918 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3919
3920 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3921}
3922
7f3e3d3a
FR		 3923static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3924{
650e8d5d 3925 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3926
3927 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3928
3929 /* Magic. */
3930 RTL_W8(DBG_REG, 0x20);
3931
f0298f81 3932 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3933
3934 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3935
3936 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3937}
3938
219a1e9d
FR		 3939static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3940{
350f7596 3941 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3942 { 0x02, 0x0800, 0x1000 },
3943 { 0x03, 0, 0x0002 },
3944 { 0x06, 0x0080, 0x0000 }
3945 };
3946
650e8d5d 3947 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3948
3949 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3950
3951 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3952
219a1e9d
FR		 3953 __rtl_hw_start_8168cp(ioaddr, pdev);
3954}
3955
3956static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3957{
350f7596 3958 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3959 { 0x01, 0, 0x0001 },
3960 { 0x03, 0x0400, 0x0220 }
3961 };
3962
650e8d5d 3963 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3964
3965 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3966
219a1e9d
FR		 3967 __rtl_hw_start_8168cp(ioaddr, pdev);
3968}
3969
197ff761
FR		 3970static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3971{
3972 rtl_hw_start_8168c_2(ioaddr, pdev);
3973}
3974
6fb07058
FR		 3975static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3976{
650e8d5d 3977 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3978
3979 __rtl_hw_start_8168cp(ioaddr, pdev);
3980}
3981
5b538df9
FR		 3982static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3983{
650e8d5d 3984 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3985
3986 rtl_disable_clock_request(pdev);
3987
f0298f81 3988 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3989
3990 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3991
3992 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3993}
3994
4804b3b3 3995static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
3996{
3997 rtl_csi_access_enable_1(ioaddr);
3998
3999 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4000
4001 RTL_W8(MaxTxPacketSize, TxPacketMax);
4002
4003 rtl_disable_clock_request(pdev);
4004}
4005
e6de30d6 4006static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4007{
4008 static const struct ephy_info e_info_8168d_4[] = {
4009 { 0x0b, ~0, 0x48 },
4010 { 0x19, 0x20, 0x50 },
4011 { 0x0c, ~0, 0x20 }
4012 };
4013 int i;
4014
4015 rtl_csi_access_enable_1(ioaddr);
4016
4017 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4018
4019 RTL_W8(MaxTxPacketSize, TxPacketMax);
4020
4021 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4022 const struct ephy_info *e = e_info_8168d_4 + i;
4023 u16 w;
4024
4025 w = rtl_ephy_read(ioaddr, e->offset);
4026 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4027 }
4028
4029 rtl_enable_clock_request(pdev);
4030}
4031
01dc7fec 4032static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4033{
4034 static const struct ephy_info e_info_8168e[] = {
4035 { 0x00, 0x0200, 0x0100 },
4036 { 0x00, 0x0000, 0x0004 },
4037 { 0x06, 0x0002, 0x0001 },
4038 { 0x06, 0x0000, 0x0030 },
4039 { 0x07, 0x0000, 0x2000 },
4040 { 0x00, 0x0000, 0x0020 },
4041 { 0x03, 0x5800, 0x2000 },
4042 { 0x03, 0x0000, 0x0001 },
4043 { 0x01, 0x0800, 0x1000 },
4044 { 0x07, 0x0000, 0x4000 },
4045 { 0x1e, 0x0000, 0x2000 },
4046 { 0x19, 0xffff, 0xfe6c },
4047 { 0x0a, 0x0000, 0x0040 }
4048 };
4049
4050 rtl_csi_access_enable_2(ioaddr);
4051
4052 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4053
4054 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4055
4056 RTL_W8(MaxTxPacketSize, TxPacketMax);
4057
4058 rtl_disable_clock_request(pdev);
4059
4060 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4061 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4062 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4063
cecb5fd7 4064 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4065}
4066
07ce4064
FR		 4067static void rtl_hw_start_8168(struct net_device *dev)
4068{
2dd99530
FR		 4069 struct rtl8169_private *tp = netdev_priv(dev);
4070 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4071 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4072
4073 RTL_W8(Cfg9346, Cfg9346_Unlock);
4074
f0298f81 4075 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4076
6f0333b8 4077 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4078
0e485150 4079 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4080
4081 RTL_W16(CPlusCmd, tp->cp_cmd);
4082
0e485150 4083 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4084
0e485150 4085 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4086 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4087 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4088 tp->intr_event |= RxFIFOOver | PCSTimeout;
4089 tp->intr_event &= ~RxOverflow;
4090 }
4091
4092 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4093
b8363901
FR		 4094 rtl_set_rx_mode(dev);
4095
4096 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4097 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4098
4099 RTL_R8(IntrMask);
4100
219a1e9d
FR		 4101 switch (tp->mac_version) {
4102 case RTL_GIGA_MAC_VER_11:
4103 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4104 break;
219a1e9d
FR		 4105
4106 case RTL_GIGA_MAC_VER_12:
4107 case RTL_GIGA_MAC_VER_17:
4108 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4109 break;
219a1e9d
FR		 4110
4111 case RTL_GIGA_MAC_VER_18:
ef3386f0 4112 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4113 break;
219a1e9d
FR		 4114
4115 case RTL_GIGA_MAC_VER_19:
4116 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4117 break;
219a1e9d
FR		 4118
4119 case RTL_GIGA_MAC_VER_20:
4120 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4121 break;
219a1e9d 4122
197ff761
FR		 4123 case RTL_GIGA_MAC_VER_21:
4124 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4125 break;
197ff761 4126
6fb07058
FR		 4127 case RTL_GIGA_MAC_VER_22:
4128 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4129 break;
6fb07058 4130
ef3386f0
FR		 4131 case RTL_GIGA_MAC_VER_23:
4132 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4133 break;
ef3386f0 4134
7f3e3d3a
FR		 4135 case RTL_GIGA_MAC_VER_24:
4136 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4137 break;
7f3e3d3a 4138
5b538df9 4139 case RTL_GIGA_MAC_VER_25:
daf9df6d 4140 case RTL_GIGA_MAC_VER_26:
4141 case RTL_GIGA_MAC_VER_27:
5b538df9 4142 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4143 break;
5b538df9 4144
e6de30d6 4145 case RTL_GIGA_MAC_VER_28:
4146 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4147 break;
cecb5fd7 4148
4804b3b3 4149 case RTL_GIGA_MAC_VER_31:
4150 rtl_hw_start_8168dp(ioaddr, pdev);
4151 break;
4152
01dc7fec 4153 case RTL_GIGA_MAC_VER_32:
4154 case RTL_GIGA_MAC_VER_33:
4155 rtl_hw_start_8168e(ioaddr, pdev);
4156 break;
e6de30d6 4157
219a1e9d
FR		 4158 default:
4159 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4160 dev->name, tp->mac_version);
4804b3b3 4161 break;
219a1e9d 4162 }
2dd99530 4163
0e485150
FR		 4164 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4165
b8363901
FR		 4166 RTL_W8(Cfg9346, Cfg9346_Lock);
4167
2dd99530 4168 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4169
0e485150 4170 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4171}
1da177e4 4172
2857ffb7
FR		 4173#define R810X_CPCMD_QUIRK_MASK (\
4174 EnableBist | \
4175 Mac_dbgo_oe | \
4176 Force_half_dup | \
5edcc537 4177 Force_rxflow_en | \
2857ffb7
FR		 4178 Force_txflow_en | \
4179 Cxpl_dbg_sel | \
4180 ASF | \
4181 PktCntrDisable | \
d24e9aaf 4182 Mac_dbgo_sel)
2857ffb7
FR		 4183
4184static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4185{
350f7596 4186 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4187 { 0x01, 0, 0x6e65 },
4188 { 0x02, 0, 0x091f },
4189 { 0x03, 0, 0xc2f9 },
4190 { 0x06, 0, 0xafb5 },
4191 { 0x07, 0, 0x0e00 },
4192 { 0x19, 0, 0xec80 },
4193 { 0x01, 0, 0x2e65 },
4194 { 0x01, 0, 0x6e65 }
4195 };
4196 u8 cfg1;
4197
650e8d5d 4198 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4199
4200 RTL_W8(DBG_REG, FIX_NAK_1);
4201
4202 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4203
4204 RTL_W8(Config1,
4205 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4206 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4207
4208 cfg1 = RTL_R8(Config1);
4209 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4210 RTL_W8(Config1, cfg1 & ~LEDS0);
4211
2857ffb7
FR		 4212 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4213}
4214
4215static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4216{
650e8d5d 4217 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4218
4219 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4220
4221 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4222 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4223}
4224
4225static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4226{
4227 rtl_hw_start_8102e_2(ioaddr, pdev);
4228
4229 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4230}
4231
5a5e4443
HW		 4232static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4233{
4234 static const struct ephy_info e_info_8105e_1[] = {
4235 { 0x07, 0, 0x4000 },
4236 { 0x19, 0, 0x0200 },
4237 { 0x19, 0, 0x0020 },
4238 { 0x1e, 0, 0x2000 },
4239 { 0x03, 0, 0x0001 },
4240 { 0x19, 0, 0x0100 },
4241 { 0x19, 0, 0x0004 },
4242 { 0x0a, 0, 0x0020 }
4243 };
4244
cecb5fd7 4245 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4246 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4247
cecb5fd7 4248 /* Disable Early Tally Counter */
5a5e4443
HW		 4249 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4250
4251 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4252 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4253
4254 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4255}
4256
4257static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4258{
4259 rtl_hw_start_8105e_1(ioaddr, pdev);
4260 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4261}
4262
07ce4064
FR		 4263static void rtl_hw_start_8101(struct net_device *dev)
4264{
cdf1a608
FR		 4265 struct rtl8169_private *tp = netdev_priv(dev);
4266 void __iomem *ioaddr = tp->mmio_addr;
4267 struct pci_dev *pdev = tp->pci_dev;
4268
cecb5fd7
FR		 4269 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4270 tp->mac_version == RTL_GIGA_MAC_VER_16) {
9c14ceaf
FR		 4271 int cap = tp->pcie_cap;
4272
4273 if (cap) {
4274 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4275 PCI_EXP_DEVCTL_NOSNOOP_EN);
4276 }
cdf1a608
FR		 4277 }
4278
d24e9aaf
HW		 4279 RTL_W8(Cfg9346, Cfg9346_Unlock);
4280
2857ffb7
FR		 4281 switch (tp->mac_version) {
4282 case RTL_GIGA_MAC_VER_07:
4283 rtl_hw_start_8102e_1(ioaddr, pdev);
4284 break;
4285
4286 case RTL_GIGA_MAC_VER_08:
4287 rtl_hw_start_8102e_3(ioaddr, pdev);
4288 break;
4289
4290 case RTL_GIGA_MAC_VER_09:
4291 rtl_hw_start_8102e_2(ioaddr, pdev);
4292 break;
5a5e4443
HW		 4293
4294 case RTL_GIGA_MAC_VER_29:
4295 rtl_hw_start_8105e_1(ioaddr, pdev);
4296 break;
4297 case RTL_GIGA_MAC_VER_30:
4298 rtl_hw_start_8105e_2(ioaddr, pdev);
4299 break;
cdf1a608
FR		 4300 }
4301
d24e9aaf 4302 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4303
f0298f81 4304 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4305
6f0333b8 4306 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4307
d24e9aaf 4308 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4309 RTL_W16(CPlusCmd, tp->cp_cmd);
4310
4311 RTL_W16(IntrMitigate, 0x0000);
4312
4313 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4314
4315 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4316 rtl_set_rx_tx_config_registers(tp);
4317
cdf1a608
FR		 4318 RTL_R8(IntrMask);
4319
cdf1a608
FR		 4320 rtl_set_rx_mode(dev);
4321
4322 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4323
0e485150 4324 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4325}
4326
4327static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4328{
1da177e4
LT		 4329 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4330 return -EINVAL;
4331
4332 dev->mtu = new_mtu;
350fb32a
MM		 4333 netdev_update_features(dev);
4334
323bb685 4335 return 0;
1da177e4
LT		 4336}
4337
4338static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4339{
95e0918d 4340 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4341 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4342}
4343
6f0333b8
ED		 4344static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4345 void **data_buff, struct RxDesc *desc)
1da177e4 4346{
48addcc9 4347 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4348 DMA_FROM_DEVICE);
48addcc9 4349
6f0333b8
ED		 4350 kfree(*data_buff);
4351 *data_buff = NULL;
1da177e4
LT		 4352 rtl8169_make_unusable_by_asic(desc);
4353}
4354
4355static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4356{
4357 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4358
4359 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4360}
4361
4362static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4363 u32 rx_buf_sz)
4364{
4365 desc->addr = cpu_to_le64(mapping);
4366 wmb();
4367 rtl8169_mark_to_asic(desc, rx_buf_sz);
4368}
4369
6f0333b8
ED		 4370static inline void *rtl8169_align(void *data)
4371{
4372 return (void *)ALIGN((long)data, 16);
4373}
4374
0ecbe1ca
SG		 4375static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4376 struct RxDesc *desc)
1da177e4 4377{
6f0333b8 4378 void *data;
1da177e4 4379 dma_addr_t mapping;
48addcc9 4380 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4381 struct net_device *dev = tp->dev;
6f0333b8 4382 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4383
6f0333b8
ED		 4384 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4385 if (!data)
4386 return NULL;
e9f63f30 4387
6f0333b8
ED		 4388 if (rtl8169_align(data) != data) {
4389 kfree(data);
4390 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4391 if (!data)
4392 return NULL;
4393 }
3eafe507 4394
48addcc9 4395 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4396 DMA_FROM_DEVICE);
d827d86b
SG		 4397 if (unlikely(dma_mapping_error(d, mapping))) {
4398 if (net_ratelimit())
4399 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4400 goto err_out;
d827d86b 4401 }
1da177e4
LT		 4402
4403 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4404 return data;
3eafe507
SG		 4405
4406err_out:
4407 kfree(data);
4408 return NULL;
1da177e4
LT		 4409}
4410
4411static void rtl8169_rx_clear(struct rtl8169_private *tp)
4412{
07d3f51f 4413 unsigned int i;
1da177e4
LT		 4414
4415 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4416 if (tp->Rx_databuff[i]) {
4417 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4418 tp->RxDescArray + i);
4419 }
4420 }
4421}
4422
0ecbe1ca 4423static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4424{
0ecbe1ca
SG		 4425 desc->opts1 |= cpu_to_le32(RingEnd);
4426}
5b0384f4 4427
0ecbe1ca
SG		 4428static int rtl8169_rx_fill(struct rtl8169_private *tp)
4429{
4430 unsigned int i;
1da177e4 4431
0ecbe1ca
SG		 4432 for (i = 0; i < NUM_RX_DESC; i++) {
4433 void *data;
4ae47c2d 4434
6f0333b8 4435 if (tp->Rx_databuff[i])
1da177e4 4436 continue;
bcf0bf90 4437
0ecbe1ca 4438 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4439 if (!data) {
4440 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4441 goto err_out;
6f0333b8
ED		 4442 }
4443 tp->Rx_databuff[i] = data;
1da177e4 4444 }
1da177e4 4445
0ecbe1ca
SG		 4446 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4447 return 0;
4448
4449err_out:
4450 rtl8169_rx_clear(tp);
4451 return -ENOMEM;
1da177e4
LT		 4452}
4453
4454static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4455{
4456 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4457}
4458
4459static int rtl8169_init_ring(struct net_device *dev)
4460{
4461 struct rtl8169_private *tp = netdev_priv(dev);
4462
4463 rtl8169_init_ring_indexes(tp);
4464
4465 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4466 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4467
0ecbe1ca 4468 return rtl8169_rx_fill(tp);
1da177e4
LT		 4469}
4470
48addcc9 4471static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4472 struct TxDesc *desc)
4473{
4474 unsigned int len = tx_skb->len;
4475
48addcc9
SG		 4476 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4477
1da177e4
LT		 4478 desc->opts1 = 0x00;
4479 desc->opts2 = 0x00;
4480 desc->addr = 0x00;
4481 tx_skb->len = 0;
4482}
4483
3eafe507
SG		 4484static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4485 unsigned int n)
1da177e4
LT		 4486{
4487 unsigned int i;
4488
3eafe507
SG		 4489 for (i = 0; i < n; i++) {
4490 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4491 struct ring_info *tx_skb = tp->tx_skb + entry;
4492 unsigned int len = tx_skb->len;
4493
4494 if (len) {
4495 struct sk_buff *skb = tx_skb->skb;
4496
48addcc9 4497 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4498 tp->TxDescArray + entry);
4499 if (skb) {
cac4b22f 4500 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4501 dev_kfree_skb(skb);
4502 tx_skb->skb = NULL;
4503 }
1da177e4
LT		 4504 }
4505 }
3eafe507
SG		 4506}
4507
4508static void rtl8169_tx_clear(struct rtl8169_private *tp)
4509{
4510 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4511 tp->cur_tx = tp->dirty_tx = 0;
4512}
4513
c4028958 4514static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4515{
4516 struct rtl8169_private *tp = netdev_priv(dev);
4517
c4028958 4518 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4519 schedule_delayed_work(&tp->task, 4);
4520}
4521
4522static void rtl8169_wait_for_quiescence(struct net_device *dev)
4523{
4524 struct rtl8169_private *tp = netdev_priv(dev);
4525 void __iomem *ioaddr = tp->mmio_addr;
4526
4527 synchronize_irq(dev->irq);
4528
4529 /* Wait for any pending NAPI task to complete */
bea3348e 4530 napi_disable(&tp->napi);
1da177e4
LT		 4531
4532 rtl8169_irq_mask_and_ack(ioaddr);
4533
d1d08d12
DM		 4534 tp->intr_mask = 0xffff;
4535 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4536 napi_enable(&tp->napi);
1da177e4
LT		 4537}
4538
c4028958 4539static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4540{
c4028958
DH		 4541 struct rtl8169_private *tp =
4542 container_of(work, struct rtl8169_private, task.work);
4543 struct net_device *dev = tp->dev;
1da177e4
LT		 4544 int ret;
4545
eb2a021c
FR		 4546 rtnl_lock();
4547
4548 if (!netif_running(dev))
4549 goto out_unlock;
4550
4551 rtl8169_wait_for_quiescence(dev);
4552 rtl8169_close(dev);
1da177e4
LT		 4553
4554 ret = rtl8169_open(dev);
4555 if (unlikely(ret < 0)) {
bf82c189
JP		 4556 if (net_ratelimit())
4557 netif_err(tp, drv, dev,
4558 "reinit failure (status = %d). Rescheduling\n",
4559 ret);
1da177e4
LT		 4560 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4561 }
eb2a021c
FR		 4562
4563out_unlock:
4564 rtnl_unlock();
1da177e4
LT		 4565}
4566
c4028958 4567static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4568{
c4028958
DH		 4569 struct rtl8169_private *tp =
4570 container_of(work, struct rtl8169_private, task.work);
4571 struct net_device *dev = tp->dev;
56de414c 4572 int i;
1da177e4 4573
eb2a021c
FR		 4574 rtnl_lock();
4575
1da177e4 4576 if (!netif_running(dev))
eb2a021c 4577 goto out_unlock;
1da177e4
LT		 4578
4579 rtl8169_wait_for_quiescence(dev);
4580
56de414c
FR		 4581 for (i = 0; i < NUM_RX_DESC; i++)
4582 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4583
1da177e4
LT		 4584 rtl8169_tx_clear(tp);
4585
56de414c
FR		 4586 rtl8169_init_ring_indexes(tp);
4587 rtl_hw_start(dev);
4588 netif_wake_queue(dev);
4589 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4590
4591out_unlock:
4592 rtnl_unlock();
1da177e4
LT		 4593}
4594
4595static void rtl8169_tx_timeout(struct net_device *dev)
4596{
4597 struct rtl8169_private *tp = netdev_priv(dev);
4598
e6de30d6 4599 rtl8169_hw_reset(tp);
1da177e4
LT		 4600
4601 /* Let's wait a bit while any (async) irq lands on */
4602 rtl8169_schedule_work(dev, rtl8169_reset_task);
4603}
4604
4605static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4606 u32 *opts)
1da177e4
LT		 4607{
4608 struct skb_shared_info *info = skb_shinfo(skb);
4609 unsigned int cur_frag, entry;
a6343afb 4610 struct TxDesc * uninitialized_var(txd);
48addcc9 4611 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4612
4613 entry = tp->cur_tx;
4614 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4615 skb_frag_t *frag = info->frags + cur_frag;
4616 dma_addr_t mapping;
4617 u32 status, len;
4618 void *addr;
4619
4620 entry = (entry + 1) % NUM_TX_DESC;
4621
4622 txd = tp->TxDescArray + entry;
4623 len = frag->size;
4624 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4625 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4626 if (unlikely(dma_mapping_error(d, mapping))) {
4627 if (net_ratelimit())
4628 netif_err(tp, drv, tp->dev,
4629 "Failed to map TX fragments DMA!\n");
3eafe507 4630 goto err_out;
d827d86b 4631 }
1da177e4 4632
cecb5fd7 4633 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4634 status = opts[0] | len |
4635 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4636
4637 txd->opts1 = cpu_to_le32(status);
2b7b4318 4638 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4639 txd->addr = cpu_to_le64(mapping);
4640
4641 tp->tx_skb[entry].len = len;
4642 }
4643
4644 if (cur_frag) {
4645 tp->tx_skb[entry].skb = skb;
4646 txd->opts1 |= cpu_to_le32(LastFrag);
4647 }
4648
4649 return cur_frag;
3eafe507
SG		 4650
4651err_out:
4652 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4653 return -EIO;
1da177e4
LT		 4654}
4655
2b7b4318
FR		 4656static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4657 struct sk_buff *skb, u32 *opts)
1da177e4 4658{
2b7b4318 4659 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4660 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4661 int offset = info->opts_offset;
350fb32a 4662
2b7b4318
FR		 4663 if (mss) {
4664 opts[0] |= TD_LSO;
4665 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4666 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4667 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4668
4669 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4670 opts[offset] |= info->checksum.tcp;
1da177e4 4671 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4672 opts[offset] |= info->checksum.udp;
4673 else
4674 WARN_ON_ONCE(1);
1da177e4 4675 }
1da177e4
LT		 4676}
4677
61357325
SH		 4678static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4679 struct net_device *dev)
1da177e4
LT		 4680{
4681 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4682 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4683 struct TxDesc *txd = tp->TxDescArray + entry;
4684 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4685 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4686 dma_addr_t mapping;
4687 u32 status, len;
2b7b4318 4688 u32 opts[2];
3eafe507 4689 int frags;
5b0384f4 4690
1da177e4 4691 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4692 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4693 goto err_stop_0;
1da177e4
LT		 4694 }
4695
4696 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4697 goto err_stop_0;
4698
4699 len = skb_headlen(skb);
48addcc9 4700 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4701 if (unlikely(dma_mapping_error(d, mapping))) {
4702 if (net_ratelimit())
4703 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4704 goto err_dma_0;
d827d86b 4705 }
3eafe507
SG		 4706
4707 tp->tx_skb[entry].len = len;
4708 txd->addr = cpu_to_le64(mapping);
1da177e4 4709
2b7b4318
FR		 4710 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4711 opts[0] = DescOwn;
1da177e4 4712
2b7b4318
FR		 4713 rtl8169_tso_csum(tp, skb, opts);
4714
4715 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4716 if (frags < 0)
4717 goto err_dma_1;
4718 else if (frags)
2b7b4318 4719 opts[0] |= FirstFrag;
3eafe507 4720 else {
2b7b4318 4721 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4722 tp->tx_skb[entry].skb = skb;
4723 }
4724
2b7b4318
FR		 4725 txd->opts2 = cpu_to_le32(opts[1]);
4726
1da177e4
LT		 4727 wmb();
4728
cecb5fd7 4729 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 4730 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4731 txd->opts1 = cpu_to_le32(status);
4732
1da177e4
LT		 4733 tp->cur_tx += frags + 1;
4734
4c020a96 4735 wmb();
1da177e4 4736
cecb5fd7 4737 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4738
4739 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4740 netif_stop_queue(dev);
4741 smp_rmb();
4742 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4743 netif_wake_queue(dev);
4744 }
4745
61357325 4746 return NETDEV_TX_OK;
1da177e4 4747
3eafe507 4748err_dma_1:
48addcc9 4749 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4750err_dma_0:
4751 dev_kfree_skb(skb);
4752 dev->stats.tx_dropped++;
4753 return NETDEV_TX_OK;
4754
4755err_stop_0:
1da177e4 4756 netif_stop_queue(dev);
cebf8cc7 4757 dev->stats.tx_dropped++;
61357325 4758 return NETDEV_TX_BUSY;
1da177e4
LT		 4759}
4760
4761static void rtl8169_pcierr_interrupt(struct net_device *dev)
4762{
4763 struct rtl8169_private *tp = netdev_priv(dev);
4764 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4765 u16 pci_status, pci_cmd;
4766
4767 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4768 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4769
bf82c189
JP		 4770 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4771 pci_cmd, pci_status);
1da177e4
LT		 4772
4773 /*
4774 * The recovery sequence below admits a very elaborated explanation:
4775 * - it seems to work;
d03902b8
FR		 4776 * - I did not see what else could be done;
4777 * - it makes iop3xx happy.
1da177e4
LT		 4778 *
4779 * Feel free to adjust to your needs.
4780 */
a27993f3 4781 if (pdev->broken_parity_status)
d03902b8
FR		 4782 pci_cmd &= ~PCI_COMMAND_PARITY;
4783 else
4784 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4785
4786 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4787
4788 pci_write_config_word(pdev, PCI_STATUS,
4789 pci_status & (PCI_STATUS_DETECTED_PARITY |
4790 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4791 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4792
4793 /* The infamous DAC f*ckup only happens at boot time */
4794 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4795 void __iomem *ioaddr = tp->mmio_addr;
4796
bf82c189 4797 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4798 tp->cp_cmd &= ~PCIDAC;
4799 RTL_W16(CPlusCmd, tp->cp_cmd);
4800 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4801 }
4802
e6de30d6 4803 rtl8169_hw_reset(tp);
d03902b8
FR		 4804
4805 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4806}
4807
07d3f51f
FR		 4808static void rtl8169_tx_interrupt(struct net_device *dev,
4809 struct rtl8169_private *tp,
4810 void __iomem *ioaddr)
1da177e4
LT		 4811{
4812 unsigned int dirty_tx, tx_left;
4813
1da177e4
LT		 4814 dirty_tx = tp->dirty_tx;
4815 smp_rmb();
4816 tx_left = tp->cur_tx - dirty_tx;
4817
4818 while (tx_left > 0) {
4819 unsigned int entry = dirty_tx % NUM_TX_DESC;
4820 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4821 u32 status;
4822
4823 rmb();
4824 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4825 if (status & DescOwn)
4826 break;
4827
48addcc9
SG		 4828 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4829 tp->TxDescArray + entry);
1da177e4 4830 if (status & LastFrag) {
cac4b22f
SG		 4831 dev->stats.tx_packets++;
4832 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4833 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4834 tx_skb->skb = NULL;
4835 }
4836 dirty_tx++;
4837 tx_left--;
4838 }
4839
4840 if (tp->dirty_tx != dirty_tx) {
4841 tp->dirty_tx = dirty_tx;
4842 smp_wmb();
4843 if (netif_queue_stopped(dev) &&
4844 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4845 netif_wake_queue(dev);
4846 }
d78ae2dc
FR		 4847 /*
4848 * 8168 hack: TxPoll requests are lost when the Tx packets are
4849 * too close. Let's kick an extra TxPoll request when a burst
4850 * of start_xmit activity is detected (if it is not detected,
4851 * it is slow enough). -- FR
4852 */
4853 smp_rmb();
4854 if (tp->cur_tx != dirty_tx)
4855 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4856 }
4857}
4858
126fa4b9
FR		 4859static inline int rtl8169_fragmented_frame(u32 status)
4860{
4861 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4862}
4863
adea1ac7 4864static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4865{
1da177e4
LT		 4866 u32 status = opts1 & RxProtoMask;
4867
4868 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4869 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4870 skb->ip_summed = CHECKSUM_UNNECESSARY;
4871 else
bc8acf2c 4872 skb_checksum_none_assert(skb);
1da177e4
LT		 4873}
4874
6f0333b8
ED		 4875static struct sk_buff *rtl8169_try_rx_copy(void *data,
4876 struct rtl8169_private *tp,
4877 int pkt_size,
4878 dma_addr_t addr)
1da177e4 4879{
b449655f 4880 struct sk_buff *skb;
48addcc9 4881 struct device *d = &tp->pci_dev->dev;
b449655f 4882
6f0333b8 4883 data = rtl8169_align(data);
48addcc9 4884 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4885 prefetch(data);
4886 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4887 if (skb)
4888 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4889 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4890
6f0333b8 4891 return skb;
1da177e4
LT		 4892}
4893
07d3f51f
FR		 4894static int rtl8169_rx_interrupt(struct net_device *dev,
4895 struct rtl8169_private *tp,
bea3348e 4896 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4897{
4898 unsigned int cur_rx, rx_left;
6f0333b8 4899 unsigned int count;
1da177e4 4900
1da177e4
LT		 4901 cur_rx = tp->cur_rx;
4902 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4903 rx_left = min(rx_left, budget);
1da177e4 4904
4dcb7d33 4905 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4906 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4907 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4908 u32 status;
4909
4910 rmb();
126fa4b9 4911 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4912
4913 if (status & DescOwn)
4914 break;
4dcb7d33 4915 if (unlikely(status & RxRES)) {
bf82c189
JP		 4916 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4917 status);
cebf8cc7 4918 dev->stats.rx_errors++;
1da177e4 4919 if (status & (RxRWT | RxRUNT))
cebf8cc7 4920 dev->stats.rx_length_errors++;
1da177e4 4921 if (status & RxCRC)
cebf8cc7 4922 dev->stats.rx_crc_errors++;
9dccf611
FR		 4923 if (status & RxFOVF) {
4924 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4925 dev->stats.rx_fifo_errors++;
9dccf611 4926 }
6f0333b8 4927 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4928 } else {
6f0333b8 4929 struct sk_buff *skb;
b449655f 4930 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4931 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4932
126fa4b9
FR		 4933 /*
4934 * The driver does not support incoming fragmented
4935 * frames. They are seen as a symptom of over-mtu
4936 * sized frames.
4937 */
4938 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4939 dev->stats.rx_dropped++;
4940 dev->stats.rx_length_errors++;
6f0333b8 4941 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4942 continue;
126fa4b9
FR		 4943 }
4944
6f0333b8
ED		 4945 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4946 tp, pkt_size, addr);
4947 rtl8169_mark_to_asic(desc, rx_buf_sz);
4948 if (!skb) {
4949 dev->stats.rx_dropped++;
4950 continue;
1da177e4
LT		 4951 }
4952
adea1ac7 4953 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4954 skb_put(skb, pkt_size);
4955 skb->protocol = eth_type_trans(skb, dev);
4956
7a8fc77b
FR		 4957 rtl8169_rx_vlan_tag(desc, skb);
4958
56de414c 4959 napi_gro_receive(&tp->napi, skb);
1da177e4 4960
cebf8cc7
FR		 4961 dev->stats.rx_bytes += pkt_size;
4962 dev->stats.rx_packets++;
1da177e4 4963 }
6dccd16b
FR		 4964
4965 /* Work around for AMD plateform. */
95e0918d 4966 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4967 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4968 desc->opts2 = 0;
4969 cur_rx++;
4970 }
1da177e4
LT		 4971 }
4972
4973 count = cur_rx - tp->cur_rx;
4974 tp->cur_rx = cur_rx;
4975
6f0333b8 4976 tp->dirty_rx += count;
1da177e4
LT		 4977
4978 return count;
4979}
4980
07d3f51f 4981static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4982{
07d3f51f 4983 struct net_device *dev = dev_instance;
1da177e4 4984 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4985 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4986 int handled = 0;
865c652d 4987 int status;
1da177e4 4988
f11a377b
DD		 4989 /* loop handling interrupts until we have no new ones or
4990 * we hit a invalid/hotplug case.
4991 */
865c652d 4992 status = RTL_R16(IntrStatus);
f11a377b
DD		 4993 while (status && status != 0xffff) {
4994 handled = 1;
1da177e4 4995
f11a377b
DD		 4996 /* Handle all of the error cases first. These will reset
4997 * the chip, so just exit the loop.
4998 */
4999 if (unlikely(!netif_running(dev))) {
5000 rtl8169_asic_down(ioaddr);
5001 break;
5002 }
1da177e4 5003
1519e57f
FR		 5004 if (unlikely(status & RxFIFOOver)) {
5005 switch (tp->mac_version) {
5006 /* Work around for rx fifo overflow */
5007 case RTL_GIGA_MAC_VER_11:
5008 case RTL_GIGA_MAC_VER_22:
5009 case RTL_GIGA_MAC_VER_26:
5010 netif_stop_queue(dev);
5011 rtl8169_tx_timeout(dev);
5012 goto done;
f60ac8e7
FR		 5013 /* Testers needed. */
5014 case RTL_GIGA_MAC_VER_17:
5015 case RTL_GIGA_MAC_VER_19:
5016 case RTL_GIGA_MAC_VER_20:
5017 case RTL_GIGA_MAC_VER_21:
5018 case RTL_GIGA_MAC_VER_23:
5019 case RTL_GIGA_MAC_VER_24:
5020 case RTL_GIGA_MAC_VER_27:
5021 case RTL_GIGA_MAC_VER_28:
4804b3b3 5022 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5023 /* Experimental science. Pktgen proof. */
5024 case RTL_GIGA_MAC_VER_12:
5025 case RTL_GIGA_MAC_VER_25:
5026 if (status == RxFIFOOver)
5027 goto done;
5028 break;
5029 default:
5030 break;
5031 }
f11a377b 5032 }
1da177e4 5033
f11a377b
DD		 5034 if (unlikely(status & SYSErr)) {
5035 rtl8169_pcierr_interrupt(dev);
5036 break;
5037 }
1da177e4 5038
f11a377b 5039 if (status & LinkChg)
e4fbce74 5040 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5041
f11a377b
DD		 5042 /* We need to see the lastest version of tp->intr_mask to
5043 * avoid ignoring an MSI interrupt and having to wait for
5044 * another event which may never come.
5045 */
5046 smp_rmb();
5047 if (status & tp->intr_mask & tp->napi_event) {
5048 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5049 tp->intr_mask = ~tp->napi_event;
5050
5051 if (likely(napi_schedule_prep(&tp->napi)))
5052 __napi_schedule(&tp->napi);
bf82c189
JP		 5053 else
5054 netif_info(tp, intr, dev,
5055 "interrupt %04x in poll\n", status);
f11a377b 5056 }
1da177e4 5057
f11a377b
DD		 5058 /* We only get a new MSI interrupt when all active irq
5059 * sources on the chip have been acknowledged. So, ack
5060 * everything we've seen and check if new sources have become
5061 * active to avoid blocking all interrupts from the chip.
5062 */
5063 RTL_W16(IntrStatus,
5064 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5065 status = RTL_R16(IntrStatus);
865c652d 5066 }
1519e57f 5067done:
1da177e4
LT		 5068 return IRQ_RETVAL(handled);
5069}
5070
bea3348e 5071static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5072{
bea3348e
SH		 5073 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5074 struct net_device *dev = tp->dev;
1da177e4 5075 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5076 int work_done;
1da177e4 5077
bea3348e 5078 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5079 rtl8169_tx_interrupt(dev, tp, ioaddr);
5080
bea3348e 5081 if (work_done < budget) {
288379f0 5082 napi_complete(napi);
f11a377b
DD		 5083
5084 /* We need for force the visibility of tp->intr_mask
5085 * for other CPUs, as we can loose an MSI interrupt
5086 * and potentially wait for a retransmit timeout if we don't.
5087 * The posted write to IntrMask is safe, as it will
5088 * eventually make it to the chip and we won't loose anything
5089 * until it does.
1da177e4 5090 */
f11a377b 5091 tp->intr_mask = 0xffff;
4c020a96 5092 wmb();
0e485150 5093 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5094 }
5095
bea3348e 5096 return work_done;
1da177e4 5097}
1da177e4 5098
523a6094
FR		 5099static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5100{
5101 struct rtl8169_private *tp = netdev_priv(dev);
5102
5103 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5104 return;
5105
5106 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5107 RTL_W32(RxMissed, 0);
5108}
5109
1da177e4
LT		 5110static void rtl8169_down(struct net_device *dev)
5111{
5112 struct rtl8169_private *tp = netdev_priv(dev);
5113 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5114
4876cc1e 5115 del_timer_sync(&tp->timer);
1da177e4
LT		 5116
5117 netif_stop_queue(dev);
5118
93dd79e8 5119 napi_disable(&tp->napi);
93dd79e8 5120
1da177e4
LT		 5121 spin_lock_irq(&tp->lock);
5122
5123 rtl8169_asic_down(ioaddr);
323bb685
SG		 5124 /*
5125 * At this point device interrupts can not be enabled in any function,
5126 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5127 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5128 */
523a6094 5129 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5130
5131 spin_unlock_irq(&tp->lock);
5132
5133 synchronize_irq(dev->irq);
5134
1da177e4 5135 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5136 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5137
1da177e4
LT		 5138 rtl8169_tx_clear(tp);
5139
5140 rtl8169_rx_clear(tp);
065c27c1 5141
5142 rtl_pll_power_down(tp);
1da177e4
LT		 5143}
5144
5145static int rtl8169_close(struct net_device *dev)
5146{
5147 struct rtl8169_private *tp = netdev_priv(dev);
5148 struct pci_dev *pdev = tp->pci_dev;
5149
e1759441
RW		 5150 pm_runtime_get_sync(&pdev->dev);
5151
cecb5fd7 5152 /* Update counters before going down */
355423d0
IV		 5153 rtl8169_update_counters(dev);
5154
1da177e4
LT		 5155 rtl8169_down(dev);
5156
5157 free_irq(dev->irq, dev);
5158
82553bb6
SG		 5159 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5160 tp->RxPhyAddr);
5161 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5162 tp->TxPhyAddr);
1da177e4
LT		 5163 tp->TxDescArray = NULL;
5164 tp->RxDescArray = NULL;
5165
e1759441
RW		 5166 pm_runtime_put_sync(&pdev->dev);
5167
1da177e4
LT		 5168 return 0;
5169}
5170
07ce4064 5171static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5172{
5173 struct rtl8169_private *tp = netdev_priv(dev);
5174 void __iomem *ioaddr = tp->mmio_addr;
5175 unsigned long flags;
5176 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5177 int rx_mode;
1da177e4
LT		 5178 u32 tmp = 0;
5179
5180 if (dev->flags & IFF_PROMISC) {
5181 /* Unconditionally log net taps. */
bf82c189 5182 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5183 rx_mode =
5184 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5185 AcceptAllPhys;
5186 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5187 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5188 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5189 /* Too many to filter perfectly -- accept all multicasts. */
5190 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5191 mc_filter[1] = mc_filter[0] = 0xffffffff;
5192 } else {
22bedad3 5193 struct netdev_hw_addr *ha;
07d3f51f 5194
1da177e4
LT		 5195 rx_mode = AcceptBroadcast | AcceptMyPhys;
5196 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5197 netdev_for_each_mc_addr(ha, dev) {
5198 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5199 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5200 rx_mode |= AcceptMulticast;
5201 }
5202 }
5203
5204 spin_lock_irqsave(&tp->lock, flags);
5205
5206 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5207 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5208
f887cce8 5209 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5210 u32 data = mc_filter[0];
5211
5212 mc_filter[0] = swab32(mc_filter[1]);
5213 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5214 }
5215
1da177e4 5216 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5217 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5218
57a9f236
FR		 5219 RTL_W32(RxConfig, tmp);
5220
1da177e4
LT		 5221 spin_unlock_irqrestore(&tp->lock, flags);
5222}
5223
5224/**
5225 * rtl8169_get_stats - Get rtl8169 read/write statistics
5226 * @dev: The Ethernet Device to get statistics for
5227 *
5228 * Get TX/RX statistics for rtl8169
5229 */
5230static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5231{
5232 struct rtl8169_private *tp = netdev_priv(dev);
5233 void __iomem *ioaddr = tp->mmio_addr;
5234 unsigned long flags;
5235
5236 if (netif_running(dev)) {
5237 spin_lock_irqsave(&tp->lock, flags);
523a6094 5238 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5239 spin_unlock_irqrestore(&tp->lock, flags);
5240 }
5b0384f4 5241
cebf8cc7 5242 return &dev->stats;
1da177e4
LT		 5243}
5244
861ab440 5245static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5246{
065c27c1 5247 struct rtl8169_private *tp = netdev_priv(dev);
5248
5d06a99f 5249 if (!netif_running(dev))
861ab440 5250 return;
5d06a99f 5251
065c27c1 5252 rtl_pll_power_down(tp);
5253
5d06a99f
FR		 5254 netif_device_detach(dev);
5255 netif_stop_queue(dev);
861ab440
RW		 5256}
5257
5258#ifdef CONFIG_PM
5259
5260static int rtl8169_suspend(struct device *device)
5261{
5262 struct pci_dev *pdev = to_pci_dev(device);
5263 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5264
861ab440 5265 rtl8169_net_suspend(dev);
1371fa6d 5266
5d06a99f
FR		 5267 return 0;
5268}
5269
e1759441
RW		 5270static void __rtl8169_resume(struct net_device *dev)
5271{
065c27c1 5272 struct rtl8169_private *tp = netdev_priv(dev);
5273
e1759441 5274 netif_device_attach(dev);
065c27c1 5275
5276 rtl_pll_power_up(tp);
5277
e1759441
RW		 5278 rtl8169_schedule_work(dev, rtl8169_reset_task);
5279}
5280
861ab440 5281static int rtl8169_resume(struct device *device)
5d06a99f 5282{
861ab440 5283 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5284 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5285 struct rtl8169_private *tp = netdev_priv(dev);
5286
5287 rtl8169_init_phy(dev, tp);
5d06a99f 5288
e1759441
RW		 5289 if (netif_running(dev))
5290 __rtl8169_resume(dev);
5d06a99f 5291
e1759441
RW		 5292 return 0;
5293}
5294
5295static int rtl8169_runtime_suspend(struct device *device)
5296{
5297 struct pci_dev *pdev = to_pci_dev(device);
5298 struct net_device *dev = pci_get_drvdata(pdev);
5299 struct rtl8169_private *tp = netdev_priv(dev);
5300
5301 if (!tp->TxDescArray)
5302 return 0;
5303
5304 spin_lock_irq(&tp->lock);
5305 tp->saved_wolopts = __rtl8169_get_wol(tp);
5306 __rtl8169_set_wol(tp, WAKE_ANY);
5307 spin_unlock_irq(&tp->lock);
5308
5309 rtl8169_net_suspend(dev);
5310
5311 return 0;
5312}
5313
5314static int rtl8169_runtime_resume(struct device *device)
5315{
5316 struct pci_dev *pdev = to_pci_dev(device);
5317 struct net_device *dev = pci_get_drvdata(pdev);
5318 struct rtl8169_private *tp = netdev_priv(dev);
5319
5320 if (!tp->TxDescArray)
5321 return 0;
5322
5323 spin_lock_irq(&tp->lock);
5324 __rtl8169_set_wol(tp, tp->saved_wolopts);
5325 tp->saved_wolopts = 0;
5326 spin_unlock_irq(&tp->lock);
5327
fccec10b
SG		 5328 rtl8169_init_phy(dev, tp);
5329
e1759441 5330 __rtl8169_resume(dev);
5d06a99f 5331
5d06a99f
FR		 5332 return 0;
5333}
5334
e1759441
RW		 5335static int rtl8169_runtime_idle(struct device *device)
5336{
5337 struct pci_dev *pdev = to_pci_dev(device);
5338 struct net_device *dev = pci_get_drvdata(pdev);
5339 struct rtl8169_private *tp = netdev_priv(dev);
5340
e4fbce74 5341 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5342}
5343
47145210 5344static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5345 .suspend = rtl8169_suspend,
5346 .resume = rtl8169_resume,
5347 .freeze = rtl8169_suspend,
5348 .thaw = rtl8169_resume,
5349 .poweroff = rtl8169_suspend,
5350 .restore = rtl8169_resume,
5351 .runtime_suspend = rtl8169_runtime_suspend,
5352 .runtime_resume = rtl8169_runtime_resume,
5353 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5354};
5355
5356#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5357
5358#else /* !CONFIG_PM */
5359
5360#define RTL8169_PM_OPS NULL
5361
5362#endif /* !CONFIG_PM */
5363
1765f95d
FR		 5364static void rtl_shutdown(struct pci_dev *pdev)
5365{
861ab440 5366 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5367 struct rtl8169_private *tp = netdev_priv(dev);
5368 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5369
5370 rtl8169_net_suspend(dev);
1765f95d 5371
cecb5fd7 5372 /* Restore original MAC address */
cc098dc7
IV		 5373 rtl_rar_set(tp, dev->perm_addr);
5374
4bb3f522 5375 spin_lock_irq(&tp->lock);
5376
5377 rtl8169_asic_down(ioaddr);
5378
5379 spin_unlock_irq(&tp->lock);
5380
861ab440 5381 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5382 /* WoL fails with some 8168 when the receiver is disabled. */
5383 if (tp->features & RTL_FEATURE_WOL) {
5384 pci_clear_master(pdev);
5385
5386 RTL_W8(ChipCmd, CmdRxEnb);
5387 /* PCI commit */
5388 RTL_R8(ChipCmd);
5389 }
5390
861ab440
RW		 5391 pci_wake_from_d3(pdev, true);
5392 pci_set_power_state(pdev, PCI_D3hot);
5393 }
5394}
5d06a99f 5395
1da177e4
LT		 5396static struct pci_driver rtl8169_pci_driver = {
5397 .name = MODULENAME,
5398 .id_table = rtl8169_pci_tbl,
5399 .probe = rtl8169_init_one,
5400 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5401 .shutdown = rtl_shutdown,
861ab440 5402 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5403};
5404
07d3f51f 5405static int __init rtl8169_init_module(void)
1da177e4 5406{
29917620 5407 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5408}
5409
07d3f51f 5410static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5411{
5412 pci_unregister_driver(&rtl8169_pci_driver);
5413}
5414
5415module_init(rtl8169_init_module);
5416module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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