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include/net/genetlink.h: Allow genlmsg_cancel to accept a NULL argument
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
1da177e4
LT		 40#ifdef RTL8169_DEBUG
41#define assert(expr) \
5b0384f4
FR		 42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 44 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 45 }
06fa7358
JP		 46#define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4
LT		 62
63/* MAC address length */
64#define MAC_ADDR_LEN 6
65
9c14ceaf 66#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 67#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 94#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 95
96enum mac_version {
f21b75e9 97 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
1da177e4
LT		 126};
127
1da177e4
LT		 128#define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
3c6bee1d 131static const struct {
1da177e4
LT		 132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135} rtl_chip_info[] = {
ba6eb6ee
FR		 136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
e6de30d6 162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
1da177e4
LT		 164};
165#undef _R
166
bcf0bf90
FR		 167enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171};
172
07ce4064
FR		 173static void rtl_hw_start_8169(struct net_device *);
174static void rtl_hw_start_8168(struct net_device *);
175static void rtl_hw_start_8101(struct net_device *);
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
6f0333b8 195static int rx_buf_sz = 16383;
4300e8c7 196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4 200
07d3f51f
FR		 201enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
773d2021 203 MAC4 = 4,
07d3f51f
FR		 204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
07d3f51f
FR		 229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
f0298f81 235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237#define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241#define TxPacketMax (8064 >> 7)
242
07d3f51f
FR		 243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
1da177e4
LT		 247};
248
f162a5d1
FR		 249enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253};
254
255enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258#define CSIAR_FLAG 0x80000000
259#define CSIAR_WRITE_CMD 0x80000000
260#define CSIAR_BYTE_ENABLE 0x0f
261#define CSIAR_BYTE_ENABLE_SHIFT 12
262#define CSIAR_ADDR_MASK 0x0fff
065c27c1 263 PMCH = 0x6f,
f162a5d1
FR		 264 EPHYAR = 0x80,
265#define EPHYAR_FLAG 0x80000000
266#define EPHYAR_WRITE_CMD 0x80000000
267#define EPHYAR_REG_MASK 0x1f
268#define EPHYAR_REG_SHIFT 16
269#define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271#define FIX_NAK_1 (1 << 4)
272#define FIX_NAK_2 (1 << 3)
daf9df6d 273 EFUSEAR = 0xdc,
274#define EFUSEAR_FLAG 0x80000000
275#define EFUSEAR_WRITE_CMD 0x80000000
276#define EFUSEAR_READ_CMD 0x00000000
277#define EFUSEAR_REG_MASK 0x03ff
278#define EFUSEAR_REG_SHIFT 8
279#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 280};
281
c0e45c1c 282enum rtl8168_registers {
b646d900 283 ERIDR = 0x70,
284 ERIAR = 0x74,
285#define ERIAR_FLAG 0x80000000
286#define ERIAR_WRITE_CMD 0x80000000
287#define ERIAR_READ_CMD 0x00000000
288#define ERIAR_ADDR_BYTE_ALIGN 4
289#define ERIAR_EXGMAC 0
290#define ERIAR_MSIX 1
291#define ERIAR_ASF 2
292#define ERIAR_TYPE_SHIFT 16
293#define ERIAR_BYTEEN 0x0f
294#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297#define OCPDR_WRITE_CMD 0x80000000
298#define OCPDR_READ_CMD 0x00000000
299#define OCPDR_REG_MASK 0x7f
300#define OCPDR_GPHY_REG_SHIFT 16
301#define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303#define OCPAR_FLAG 0x80000000
304#define OCPAR_GPHY_WRITE_CMD 0x8000f060
305#define OCPAR_GPHY_READ_CMD 0x0000f060
e6de30d6 306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
c0e45c1c 307};
308
07d3f51f 309enum rtl_register_content {
1da177e4 310 /* InterruptStatusBits */
07d3f51f
FR		 311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
1da177e4
LT		 322
323 /* RxStatusDesc */
9dccf611
FR		 324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
1da177e4
LT		 329
330 /* ChipCmdBits */
07d3f51f
FR		 331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
1da177e4 335
275391a4
FR		 336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
1da177e4 341 /* Cfg9346Bits */
07d3f51f
FR		 342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 344
345 /* rx_mode_bits */
07d3f51f
FR		 346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
1da177e4
LT		 352
353 /* RxConfigBits */
07d3f51f
FR		 354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
1da177e4
LT		 356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
5d06a99f 361 /* Config1 register p.24 */
f162a5d1
FR		 362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
fbac58fc 364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
5d06a99f
FR		 369 PMEnable = (1 << 0), /* Power Management Enable */
370
6dccd16b
FR		 371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
61a4dcc2
FR		 375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 379
5d06a99f 380 /* Config5 register p.27 */
61a4dcc2
FR		 381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
1da177e4
LT		 387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
f162a5d1
FR		 396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
0e485150
FR		 410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
1da177e4
LT		 414
415 /* rtl8169_PHYstatus */
07d3f51f
FR		 416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
1da177e4 424
1da177e4 425 /* _TBICSRBit */
07d3f51f 426 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 427
428 /* DumpCounterCommand */
07d3f51f 429 CounterDump = 0x8,
1da177e4
LT		 430};
431
07d3f51f 432enum desc_status_bit {
1da177e4
LT		 433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451#define RxProtoUDP (PID1)
452#define RxProtoTCP (PID0)
453#define RxProtoIP (PID1 | PID0)
454#define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460};
461
462#define RsvdMask 0x3fffc000
463
464struct TxDesc {
6cccd6e7
REB		 465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
1da177e4
LT		 468};
469
470struct RxDesc {
6cccd6e7
REB		 471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
1da177e4
LT		 474};
475
476struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480};
481
f23e7fda 482enum features {
ccdffb9a
FR		 483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 486};
487
355423d0
IV		 488struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502};
503
1da177e4
LT		 504struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 507 struct net_device *dev;
bea3348e 508 struct napi_struct napi;
1da177e4 509 spinlock_t lock; /* spin lock flag */
b57b7e5a 510 u32 msg_enable;
1da177e4
LT		 511 int chipset;
512 int mac_version;
1da177e4
LT		 513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
6f0333b8 521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 523 struct timer_list timer;
524 u16 cp_cmd;
0e485150
FR		 525 u16 intr_event;
526 u16 napi_event;
1da177e4 527 u16 intr_mask;
1da177e4
LT		 528 int phy_1000_ctrl_reg;
529#ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531#endif
c0e45c1c 532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
065c27c1 538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
1da177e4 543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 545 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 546 void (*hw_start)(struct net_device *);
4da19633 547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 548 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 550 int pcie_cap;
c4028958 551 struct delayed_work task;
f23e7fda 552 unsigned features;
ccdffb9a
FR		 553
554 struct mii_if_info mii;
355423d0 555 struct rtl8169_counters counters;
e1759441 556 u32 saved_wolopts;
f1e02ed1 557
558 const struct firmware *fw;
1da177e4
LT		 559};
560
979b6c13 561MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 562MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 563module_param(use_dac, int, 0);
4300e8c7 564MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 565module_param_named(debug, debug.msg_enable, int, 0);
566MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 567MODULE_LICENSE("GPL");
568MODULE_VERSION(RTL8169_VERSION);
bca03d5f 569MODULE_FIRMWARE(FIRMWARE_8168D_1);
570MODULE_FIRMWARE(FIRMWARE_8168D_2);
1da177e4
LT		 571
572static int rtl8169_open(struct net_device *dev);
61357325
SH		 573static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
574 struct net_device *dev);
7d12e780 575static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 576static int rtl8169_init_ring(struct net_device *dev);
07ce4064 577static void rtl_hw_start(struct net_device *dev);
1da177e4 578static int rtl8169_close(struct net_device *dev);
07ce4064 579static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 580static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 581static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 582static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 583 void __iomem *, u32 budget);
4dcb7d33 584static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 585static void rtl8169_down(struct net_device *dev);
99f252b0 586static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 587static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 588
1da177e4 589static const unsigned int rtl8169_rx_config =
5b0384f4 590 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 591
b646d900 592static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
593{
594 void __iomem *ioaddr = tp->mmio_addr;
595 int i;
596
597 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
598 for (i = 0; i < 20; i++) {
599 udelay(100);
600 if (RTL_R32(OCPAR) & OCPAR_FLAG)
601 break;
602 }
603 return RTL_R32(OCPDR);
604}
605
606static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
607{
608 void __iomem *ioaddr = tp->mmio_addr;
609 int i;
610
611 RTL_W32(OCPDR, data);
612 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
613 for (i = 0; i < 20; i++) {
614 udelay(100);
615 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
616 break;
617 }
618}
619
620static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
621{
622 int i;
623
624 RTL_W8(ERIDR, cmd);
625 RTL_W32(ERIAR, 0x800010e8);
626 msleep(2);
627 for (i = 0; i < 5; i++) {
628 udelay(100);
629 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
630 break;
631 }
632
633 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
634}
635
636#define OOB_CMD_RESET 0x00
637#define OOB_CMD_DRIVER_START 0x05
638#define OOB_CMD_DRIVER_STOP 0x06
639
640static void rtl8168_driver_start(struct rtl8169_private *tp)
641{
642 int i;
643
644 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
645
646 for (i = 0; i < 10; i++) {
647 msleep(10);
648 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
649 break;
650 }
651}
652
653static void rtl8168_driver_stop(struct rtl8169_private *tp)
654{
655 int i;
656
657 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
658
659 for (i = 0; i < 10; i++) {
660 msleep(10);
661 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
662 break;
663 }
664}
665
666
4da19633 667static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 668{
669 int i;
670
a6baf3af 671 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 672
2371408c 673 for (i = 20; i > 0; i--) {
07d3f51f
FR		 674 /*
675 * Check if the RTL8169 has completed writing to the specified
676 * MII register.
677 */
5b0384f4 678 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 679 break;
2371408c 680 udelay(25);
1da177e4 681 }
024a07ba 682 /*
81a95f04
TT		 683 * According to hardware specs a 20us delay is required after write
684 * complete indication, but before sending next command.
024a07ba 685 */
81a95f04 686 udelay(20);
1da177e4
LT		 687}
688
4da19633 689static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 690{
691 int i, value = -1;
692
a6baf3af 693 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 694
2371408c 695 for (i = 20; i > 0; i--) {
07d3f51f
FR		 696 /*
697 * Check if the RTL8169 has completed retrieving data from
698 * the specified MII register.
699 */
1da177e4 700 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 701 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 702 break;
703 }
2371408c 704 udelay(25);
1da177e4 705 }
81a95f04
TT		 706 /*
707 * According to hardware specs a 20us delay is required after read
708 * complete indication, but before sending next command.
709 */
710 udelay(20);
711
1da177e4
LT		 712 return value;
713}
714
c0e45c1c 715static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
716{
717 int i;
718
719 RTL_W32(OCPDR, data |
720 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
721 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
722 RTL_W32(EPHY_RXER_NUM, 0);
723
724 for (i = 0; i < 100; i++) {
725 mdelay(1);
726 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
727 break;
728 }
729}
730
731static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
732{
733 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
734 (value & OCPDR_DATA_MASK));
735}
736
737static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
738{
739 int i;
740
741 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
742
743 mdelay(1);
744 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
745 RTL_W32(EPHY_RXER_NUM, 0);
746
747 for (i = 0; i < 100; i++) {
748 mdelay(1);
749 if (RTL_R32(OCPAR) & OCPAR_FLAG)
750 break;
751 }
752
753 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
754}
755
e6de30d6 756#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
757
758static void r8168dp_2_mdio_start(void __iomem *ioaddr)
759{
760 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
761}
762
763static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
764{
765 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
766}
767
768static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
769{
770 r8168dp_2_mdio_start(ioaddr);
771
772 r8169_mdio_write(ioaddr, reg_addr, value);
773
774 r8168dp_2_mdio_stop(ioaddr);
775}
776
777static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
778{
779 int value;
780
781 r8168dp_2_mdio_start(ioaddr);
782
783 value = r8169_mdio_read(ioaddr, reg_addr);
784
785 r8168dp_2_mdio_stop(ioaddr);
786
787 return value;
788}
789
4da19633 790static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 791{
c0e45c1c 792 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 793}
794
4da19633 795static int rtl_readphy(struct rtl8169_private *tp, int location)
796{
c0e45c1c 797 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 798}
799
800static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
801{
802 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
803}
804
805static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 806{
807 int val;
808
4da19633 809 val = rtl_readphy(tp, reg_addr);
810 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 811}
812
ccdffb9a
FR		 813static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
814 int val)
815{
816 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 817
4da19633 818 rtl_writephy(tp, location, val);
ccdffb9a
FR		 819}
820
821static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
822{
823 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 824
4da19633 825 return rtl_readphy(tp, location);
ccdffb9a
FR		 826}
827
dacf8154
FR		 828static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
829{
830 unsigned int i;
831
832 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
833 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
834
835 for (i = 0; i < 100; i++) {
836 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
837 break;
838 udelay(10);
839 }
840}
841
842static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
843{
844 u16 value = 0xffff;
845 unsigned int i;
846
847 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
848
849 for (i = 0; i < 100; i++) {
850 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
851 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
852 break;
853 }
854 udelay(10);
855 }
856
857 return value;
858}
859
860static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
861{
862 unsigned int i;
863
864 RTL_W32(CSIDR, value);
865 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
866 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
867
868 for (i = 0; i < 100; i++) {
869 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
870 break;
871 udelay(10);
872 }
873}
874
875static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
876{
877 u32 value = ~0x00;
878 unsigned int i;
879
880 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
881 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
882
883 for (i = 0; i < 100; i++) {
884 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
885 value = RTL_R32(CSIDR);
886 break;
887 }
888 udelay(10);
889 }
890
891 return value;
892}
893
daf9df6d 894static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
895{
896 u8 value = 0xff;
897 unsigned int i;
898
899 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
900
901 for (i = 0; i < 300; i++) {
902 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
903 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
904 break;
905 }
906 udelay(100);
907 }
908
909 return value;
910}
911
1da177e4
LT		 912static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
913{
914 RTL_W16(IntrMask, 0x0000);
915
916 RTL_W16(IntrStatus, 0xffff);
917}
918
919static void rtl8169_asic_down(void __iomem *ioaddr)
920{
921 RTL_W8(ChipCmd, 0x00);
922 rtl8169_irq_mask_and_ack(ioaddr);
923 RTL_R16(CPlusCmd);
924}
925
4da19633 926static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 927{
4da19633 928 void __iomem *ioaddr = tp->mmio_addr;
929
1da177e4
LT		 930 return RTL_R32(TBICSR) & TBIReset;
931}
932
4da19633 933static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 934{
4da19633 935 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 936}
937
938static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
939{
940 return RTL_R32(TBICSR) & TBILinkOk;
941}
942
943static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
944{
945 return RTL_R8(PHYstatus) & LinkStatus;
946}
947
4da19633 948static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 949{
4da19633 950 void __iomem *ioaddr = tp->mmio_addr;
951
1da177e4
LT		 952 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
953}
954
4da19633 955static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 956{
957 unsigned int val;
958
4da19633 959 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
960 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 961}
962
e4fbce74 963static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 964 struct rtl8169_private *tp,
e4fbce74
RW		 965 void __iomem *ioaddr,
966 bool pm)
1da177e4
LT		 967{
968 unsigned long flags;
969
970 spin_lock_irqsave(&tp->lock, flags);
971 if (tp->link_ok(ioaddr)) {
e1759441 972 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 973 if (pm)
974 pm_request_resume(&tp->pci_dev->dev);
1da177e4 975 netif_carrier_on(dev);
bf82c189 976 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 977 } else {
1da177e4 978 netif_carrier_off(dev);
bf82c189 979 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 980 if (pm)
981 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 982 }
1da177e4
LT		 983 spin_unlock_irqrestore(&tp->lock, flags);
984}
985
e4fbce74
RW		 986static void rtl8169_check_link_status(struct net_device *dev,
987 struct rtl8169_private *tp,
988 void __iomem *ioaddr)
989{
990 __rtl8169_check_link_status(dev, tp, ioaddr, false);
991}
992
e1759441
RW		 993#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
994
995static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 996{
61a4dcc2
FR		 997 void __iomem *ioaddr = tp->mmio_addr;
998 u8 options;
e1759441 999 u32 wolopts = 0;
61a4dcc2
FR		 1000
1001 options = RTL_R8(Config1);
1002 if (!(options & PMEnable))
e1759441 1003 return 0;
61a4dcc2
FR		 1004
1005 options = RTL_R8(Config3);
1006 if (options & LinkUp)
e1759441 1007 wolopts |= WAKE_PHY;
61a4dcc2 1008 if (options & MagicPacket)
e1759441 1009 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1010
1011 options = RTL_R8(Config5);
1012 if (options & UWF)
e1759441 1013 wolopts |= WAKE_UCAST;
61a4dcc2 1014 if (options & BWF)
e1759441 1015 wolopts |= WAKE_BCAST;
61a4dcc2 1016 if (options & MWF)
e1759441 1017 wolopts |= WAKE_MCAST;
61a4dcc2 1018
e1759441 1019 return wolopts;
61a4dcc2
FR		 1020}
1021
e1759441 1022static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1023{
1024 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1025
1026 spin_lock_irq(&tp->lock);
1027
1028 wol->supported = WAKE_ANY;
1029 wol->wolopts = __rtl8169_get_wol(tp);
1030
1031 spin_unlock_irq(&tp->lock);
1032}
1033
1034static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1035{
61a4dcc2 1036 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1037 unsigned int i;
350f7596 1038 static const struct {
61a4dcc2
FR		 1039 u32 opt;
1040 u16 reg;
1041 u8 mask;
1042 } cfg[] = {
1043 { WAKE_ANY, Config1, PMEnable },
1044 { WAKE_PHY, Config3, LinkUp },
1045 { WAKE_MAGIC, Config3, MagicPacket },
1046 { WAKE_UCAST, Config5, UWF },
1047 { WAKE_BCAST, Config5, BWF },
1048 { WAKE_MCAST, Config5, MWF },
1049 { WAKE_ANY, Config5, LanWake }
1050 };
1051
61a4dcc2
FR		 1052 RTL_W8(Cfg9346, Cfg9346_Unlock);
1053
1054 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1055 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1056 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1057 options |= cfg[i].mask;
1058 RTL_W8(cfg[i].reg, options);
1059 }
1060
1061 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1062}
1063
1064static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1065{
1066 struct rtl8169_private *tp = netdev_priv(dev);
1067
1068 spin_lock_irq(&tp->lock);
61a4dcc2 1069
f23e7fda
FR		 1070 if (wol->wolopts)
1071 tp->features |= RTL_FEATURE_WOL;
1072 else
1073 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1074 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1075 spin_unlock_irq(&tp->lock);
1076
ea80907f 1077 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1078
61a4dcc2
FR		 1079 return 0;
1080}
1081
1da177e4
LT		 1082static void rtl8169_get_drvinfo(struct net_device *dev,
1083 struct ethtool_drvinfo *info)
1084{
1085 struct rtl8169_private *tp = netdev_priv(dev);
1086
1087 strcpy(info->driver, MODULENAME);
1088 strcpy(info->version, RTL8169_VERSION);
1089 strcpy(info->bus_info, pci_name(tp->pci_dev));
1090}
1091
1092static int rtl8169_get_regs_len(struct net_device *dev)
1093{
1094 return R8169_REGS_SIZE;
1095}
1096
1097static int rtl8169_set_speed_tbi(struct net_device *dev,
1098 u8 autoneg, u16 speed, u8 duplex)
1099{
1100 struct rtl8169_private *tp = netdev_priv(dev);
1101 void __iomem *ioaddr = tp->mmio_addr;
1102 int ret = 0;
1103 u32 reg;
1104
1105 reg = RTL_R32(TBICSR);
1106 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1107 (duplex == DUPLEX_FULL)) {
1108 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1109 } else if (autoneg == AUTONEG_ENABLE)
1110 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1111 else {
bf82c189
JP		 1112 netif_warn(tp, link, dev,
1113 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1114 ret = -EOPNOTSUPP;
1115 }
1116
1117 return ret;
1118}
1119
1120static int rtl8169_set_speed_xmii(struct net_device *dev,
1121 u8 autoneg, u16 speed, u8 duplex)
1122{
1123 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1124 int giga_ctrl, bmcr;
1da177e4
LT		 1125
1126 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1127 int auto_nego;
1128
4da19633 1129 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
64e4bfb4
FR		 1130 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1131 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 1132 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1133
4da19633 1134 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1135 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1136
3577aa1b 1137 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1138 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1139 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1140 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1144 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1145 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1146 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 1147 } else {
1148 netif_info(tp, link, dev,
1149 "PHY does not support 1000Mbps\n");
bcf0bf90 1150 }
1da177e4 1151
3577aa1b 1152 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1153
1154 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1155 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1156 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1157 /*
1158 * Wake up the PHY.
1159 * Vendor specific (0x1f) and reserved (0x0e) MII
1160 * registers.
1161 */
4da19633 1162 rtl_writephy(tp, 0x1f, 0x0000);
1163 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1164 }
1165
4da19633 1166 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1167 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1168 } else {
1169 giga_ctrl = 0;
1170
1171 if (speed == SPEED_10)
1172 bmcr = 0;
1173 else if (speed == SPEED_100)
1174 bmcr = BMCR_SPEED100;
1175 else
1176 return -EINVAL;
1177
1178 if (duplex == DUPLEX_FULL)
1179 bmcr |= BMCR_FULLDPLX;
623a1593 1180
4da19633 1181 rtl_writephy(tp, 0x1f, 0x0000);
2584fbc3
RS		 1182 }
1183
1da177e4
LT		 1184 tp->phy_1000_ctrl_reg = giga_ctrl;
1185
4da19633 1186 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1187
1188 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1189 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1190 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1191 rtl_writephy(tp, 0x17, 0x2138);
1192 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1193 } else {
4da19633 1194 rtl_writephy(tp, 0x17, 0x2108);
1195 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1196 }
1197 }
1198
1da177e4
LT		 1199 return 0;
1200}
1201
1202static int rtl8169_set_speed(struct net_device *dev,
1203 u8 autoneg, u16 speed, u8 duplex)
1204{
1205 struct rtl8169_private *tp = netdev_priv(dev);
1206 int ret;
1207
1208 ret = tp->set_speed(dev, autoneg, speed, duplex);
1209
64e4bfb4 1210 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1211 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1212
1213 return ret;
1214}
1215
1216static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1217{
1218 struct rtl8169_private *tp = netdev_priv(dev);
1219 unsigned long flags;
1220 int ret;
1221
1222 spin_lock_irqsave(&tp->lock, flags);
1223 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1224 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1225
1da177e4
LT		 1226 return ret;
1227}
1228
1229static u32 rtl8169_get_rx_csum(struct net_device *dev)
1230{
1231 struct rtl8169_private *tp = netdev_priv(dev);
1232
1233 return tp->cp_cmd & RxChkSum;
1234}
1235
1236static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1237{
1238 struct rtl8169_private *tp = netdev_priv(dev);
1239 void __iomem *ioaddr = tp->mmio_addr;
1240 unsigned long flags;
1241
1242 spin_lock_irqsave(&tp->lock, flags);
1243
1244 if (data)
1245 tp->cp_cmd |= RxChkSum;
1246 else
1247 tp->cp_cmd &= ~RxChkSum;
1248
1249 RTL_W16(CPlusCmd, tp->cp_cmd);
1250 RTL_R16(CPlusCmd);
1251
1252 spin_unlock_irqrestore(&tp->lock, flags);
1253
1254 return 0;
1255}
1256
1257#ifdef CONFIG_R8169_VLAN
1258
1259static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1260 struct sk_buff *skb)
1261{
eab6d18d 1262 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1263 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1264}
1265
1266static void rtl8169_vlan_rx_register(struct net_device *dev,
1267 struct vlan_group *grp)
1268{
1269 struct rtl8169_private *tp = netdev_priv(dev);
1270 void __iomem *ioaddr = tp->mmio_addr;
1271 unsigned long flags;
1272
1273 spin_lock_irqsave(&tp->lock, flags);
1274 tp->vlgrp = grp;
05af2142
SW		 1275 /*
1276 * Do not disable RxVlan on 8110SCd.
1277 */
1278 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1279 tp->cp_cmd |= RxVlan;
1280 else
1281 tp->cp_cmd &= ~RxVlan;
1282 RTL_W16(CPlusCmd, tp->cp_cmd);
1283 RTL_R16(CPlusCmd);
1284 spin_unlock_irqrestore(&tp->lock, flags);
1285}
1286
1da177e4 1287static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1288 struct sk_buff *skb, int polling)
1da177e4
LT		 1289{
1290 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1291 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1292 int ret;
1293
865c652d 1294 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1295 u16 vtag = swab16(opts2 & 0xffff);
1296
1297 if (likely(polling))
1298 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1299 else
1300 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1301 ret = 0;
1302 } else
1303 ret = -1;
1304 desc->opts2 = 0;
1305 return ret;
1306}
1307
1308#else /* !CONFIG_R8169_VLAN */
1309
1310static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1311 struct sk_buff *skb)
1312{
1313 return 0;
1314}
1315
1316static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1317 struct sk_buff *skb, int polling)
1da177e4
LT		 1318{
1319 return -1;
1320}
1321
1322#endif
1323
ccdffb9a 1324static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1325{
1326 struct rtl8169_private *tp = netdev_priv(dev);
1327 void __iomem *ioaddr = tp->mmio_addr;
1328 u32 status;
1329
1330 cmd->supported =
1331 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1332 cmd->port = PORT_FIBRE;
1333 cmd->transceiver = XCVR_INTERNAL;
1334
1335 status = RTL_R32(TBICSR);
1336 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1337 cmd->autoneg = !!(status & TBINwEnable);
1338
1339 cmd->speed = SPEED_1000;
1340 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1341
1342 return 0;
1da177e4
LT		 1343}
1344
ccdffb9a 1345static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1346{
1347 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1348
1349 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1350}
1351
1352static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1353{
1354 struct rtl8169_private *tp = netdev_priv(dev);
1355 unsigned long flags;
ccdffb9a 1356 int rc;
1da177e4
LT		 1357
1358 spin_lock_irqsave(&tp->lock, flags);
1359
ccdffb9a 1360 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1361
1362 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1363 return rc;
1da177e4
LT		 1364}
1365
1366static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1367 void *p)
1368{
5b0384f4
FR		 1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 unsigned long flags;
1da177e4 1371
5b0384f4
FR		 1372 if (regs->len > R8169_REGS_SIZE)
1373 regs->len = R8169_REGS_SIZE;
1da177e4 1374
5b0384f4
FR		 1375 spin_lock_irqsave(&tp->lock, flags);
1376 memcpy_fromio(p, tp->mmio_addr, regs->len);
1377 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1378}
1379
b57b7e5a
SH		 1380static u32 rtl8169_get_msglevel(struct net_device *dev)
1381{
1382 struct rtl8169_private *tp = netdev_priv(dev);
1383
1384 return tp->msg_enable;
1385}
1386
1387static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1388{
1389 struct rtl8169_private *tp = netdev_priv(dev);
1390
1391 tp->msg_enable = value;
1392}
1393
d4a3a0fc
SH		 1394static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1395 "tx_packets",
1396 "rx_packets",
1397 "tx_errors",
1398 "rx_errors",
1399 "rx_missed",
1400 "align_errors",
1401 "tx_single_collisions",
1402 "tx_multi_collisions",
1403 "unicast",
1404 "broadcast",
1405 "multicast",
1406 "tx_aborted",
1407 "tx_underrun",
1408};
1409
b9f2c044 1410static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1411{
b9f2c044
JG		 1412 switch (sset) {
1413 case ETH_SS_STATS:
1414 return ARRAY_SIZE(rtl8169_gstrings);
1415 default:
1416 return -EOPNOTSUPP;
1417 }
d4a3a0fc
SH		 1418}
1419
355423d0 1420static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1421{
1422 struct rtl8169_private *tp = netdev_priv(dev);
1423 void __iomem *ioaddr = tp->mmio_addr;
1424 struct rtl8169_counters *counters;
1425 dma_addr_t paddr;
1426 u32 cmd;
355423d0 1427 int wait = 1000;
48addcc9 1428 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1429
355423d0
IV		 1430 /*
1431 * Some chips are unable to dump tally counters when the receiver
1432 * is disabled.
1433 */
1434 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1435 return;
d4a3a0fc 1436
48addcc9 1437 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1438 if (!counters)
1439 return;
1440
1441 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1442 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1443 RTL_W32(CounterAddrLow, cmd);
1444 RTL_W32(CounterAddrLow, cmd | CounterDump);
1445
355423d0
IV		 1446 while (wait--) {
1447 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1448 /* copy updated counters */
1449 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1450 break;
355423d0
IV		 1451 }
1452 udelay(10);
d4a3a0fc
SH		 1453 }
1454
1455 RTL_W32(CounterAddrLow, 0);
1456 RTL_W32(CounterAddrHigh, 0);
1457
48addcc9 1458 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1459}
1460
355423d0
IV		 1461static void rtl8169_get_ethtool_stats(struct net_device *dev,
1462 struct ethtool_stats *stats, u64 *data)
1463{
1464 struct rtl8169_private *tp = netdev_priv(dev);
1465
1466 ASSERT_RTNL();
1467
1468 rtl8169_update_counters(dev);
1469
1470 data[0] = le64_to_cpu(tp->counters.tx_packets);
1471 data[1] = le64_to_cpu(tp->counters.rx_packets);
1472 data[2] = le64_to_cpu(tp->counters.tx_errors);
1473 data[3] = le32_to_cpu(tp->counters.rx_errors);
1474 data[4] = le16_to_cpu(tp->counters.rx_missed);
1475 data[5] = le16_to_cpu(tp->counters.align_errors);
1476 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1477 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1478 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1479 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1480 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1481 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1482 data[12] = le16_to_cpu(tp->counters.tx_underun);
1483}
1484
d4a3a0fc
SH		 1485static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1486{
1487 switch(stringset) {
1488 case ETH_SS_STATS:
1489 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1490 break;
1491 }
1492}
1493
7282d491 1494static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1495 .get_drvinfo = rtl8169_get_drvinfo,
1496 .get_regs_len = rtl8169_get_regs_len,
1497 .get_link = ethtool_op_get_link,
1498 .get_settings = rtl8169_get_settings,
1499 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1500 .get_msglevel = rtl8169_get_msglevel,
1501 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1502 .get_rx_csum = rtl8169_get_rx_csum,
1503 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1504 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1505 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1506 .set_tso = ethtool_op_set_tso,
1507 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1508 .get_wol = rtl8169_get_wol,
1509 .set_wol = rtl8169_set_wol,
d4a3a0fc 1510 .get_strings = rtl8169_get_strings,
b9f2c044 1511 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1512 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1513};
1514
07d3f51f
FR		 1515static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1516 void __iomem *ioaddr)
1da177e4 1517{
0e485150
FR		 1518 /*
1519 * The driver currently handles the 8168Bf and the 8168Be identically
1520 * but they can be identified more specifically through the test below
1521 * if needed:
1522 *
1523 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1524 *
1525 * Same thing for the 8101Eb and the 8101Ec:
1526 *
1527 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1528 */
350f7596 1529 static const struct {
1da177e4 1530 u32 mask;
e3cf0cc0 1531 u32 val;
1da177e4
LT		 1532 int mac_version;
1533 } mac_info[] = {
5b538df9 1534 /* 8168D family. */
daf9df6d 1535 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1536 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1537 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1538
e6de30d6 1539 /* 8168DP family. */
1540 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1541 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1542
ef808d50 1543 /* 8168C family. */
17c99297 1544 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1545 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1546 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1547 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1548 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1549 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1550 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1551 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1552 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1553
1554 /* 8168B family. */
1555 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1556 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1557 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1558 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1559
1560 /* 8101 family. */
2857ffb7
FR		 1561 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1562 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1563 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1564 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1565 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1566 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1567 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1568 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1569 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1570 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1571 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1572 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1573 /* FIXME: where did these entries come from ? -- FR */
1574 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1575 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1576
1577 /* 8110 family. */
1578 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1579 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1580 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1581 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1582 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1583 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1584
f21b75e9
JD		 1585 /* Catch-all */
1586 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1587 }, *p = mac_info;
1588 u32 reg;
1589
e3cf0cc0
FR		 1590 reg = RTL_R32(TxConfig);
1591 while ((reg & p->mask) != p->val)
1da177e4
LT		 1592 p++;
1593 tp->mac_version = p->mac_version;
1594}
1595
1596static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1597{
bcf0bf90 1598 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1599}
1600
867763c1
FR		 1601struct phy_reg {
1602 u16 reg;
1603 u16 val;
1604};
1605
4da19633 1606static void rtl_writephy_batch(struct rtl8169_private *tp,
1607 const struct phy_reg *regs, int len)
867763c1
FR		 1608{
1609 while (len-- > 0) {
4da19633 1610 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1611 regs++;
1612 }
1613}
1614
bca03d5f 1615#define PHY_READ 0x00000000
1616#define PHY_DATA_OR 0x10000000
1617#define PHY_DATA_AND 0x20000000
1618#define PHY_BJMPN 0x30000000
1619#define PHY_READ_EFUSE 0x40000000
1620#define PHY_READ_MAC_BYTE 0x50000000
1621#define PHY_WRITE_MAC_BYTE 0x60000000
1622#define PHY_CLEAR_READCOUNT 0x70000000
1623#define PHY_WRITE 0x80000000
1624#define PHY_READCOUNT_EQ_SKIP 0x90000000
1625#define PHY_COMP_EQ_SKIPN 0xa0000000
1626#define PHY_COMP_NEQ_SKIPN 0xb0000000
1627#define PHY_WRITE_PREVIOUS 0xc0000000
1628#define PHY_SKIPN 0xd0000000
1629#define PHY_DELAY_MS 0xe0000000
1630#define PHY_WRITE_ERI_WORD 0xf0000000
1631
1632static void
1633rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1634{
bca03d5f 1635 __le32 *phytable = (__le32 *)fw->data;
1636 struct net_device *dev = tp->dev;
42b82dc1 1637 size_t index, fw_size = fw->size / sizeof(*phytable);
1638 u32 predata, count;
bca03d5f 1639
1640 if (fw->size % sizeof(*phytable)) {
1641 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1642 return;
1643 }
1644
42b82dc1 1645 for (index = 0; index < fw_size; index++) {
1646 u32 action = le32_to_cpu(phytable[index]);
1647 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1648
42b82dc1 1649 switch(action & 0xf0000000) {
1650 case PHY_READ:
1651 case PHY_DATA_OR:
1652 case PHY_DATA_AND:
1653 case PHY_READ_EFUSE:
1654 case PHY_CLEAR_READCOUNT:
1655 case PHY_WRITE:
1656 case PHY_WRITE_PREVIOUS:
1657 case PHY_DELAY_MS:
1658 break;
1659
1660 case PHY_BJMPN:
1661 if (regno > index) {
1662 netif_err(tp, probe, tp->dev,
1663 "Out of range of firmware\n");
1664 return;
1665 }
1666 break;
1667 case PHY_READCOUNT_EQ_SKIP:
1668 if (index + 2 >= fw_size) {
1669 netif_err(tp, probe, tp->dev,
1670 "Out of range of firmware\n");
1671 return;
1672 }
1673 break;
1674 case PHY_COMP_EQ_SKIPN:
1675 case PHY_COMP_NEQ_SKIPN:
1676 case PHY_SKIPN:
1677 if (index + 1 + regno >= fw_size) {
1678 netif_err(tp, probe, tp->dev,
1679 "Out of range of firmware\n");
1680 return;
1681 }
bca03d5f 1682 break;
1683
42b82dc1 1684 case PHY_READ_MAC_BYTE:
1685 case PHY_WRITE_MAC_BYTE:
1686 case PHY_WRITE_ERI_WORD:
1687 default:
1688 netif_err(tp, probe, tp->dev,
1689 "Invalid action 0x%08x\n", action);
bca03d5f 1690 return;
1691 }
1692 }
1693
42b82dc1 1694 predata = 0;
1695 count = 0;
1696
1697 for (index = 0; index < fw_size; ) {
1698 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1699 u32 data = action & 0x0000ffff;
42b82dc1 1700 u32 regno = (action & 0x0fff0000) >> 16;
1701
1702 if (!action)
1703 break;
bca03d5f 1704
1705 switch(action & 0xf0000000) {
42b82dc1 1706 case PHY_READ:
1707 predata = rtl_readphy(tp, regno);
1708 count++;
1709 index++;
1710 break;
1711 case PHY_DATA_OR:
1712 predata |= data;
1713 index++;
1714 break;
1715 case PHY_DATA_AND:
1716 predata &= data;
1717 index++;
1718 break;
1719 case PHY_BJMPN:
1720 index -= regno;
1721 break;
1722 case PHY_READ_EFUSE:
1723 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1724 index++;
1725 break;
1726 case PHY_CLEAR_READCOUNT:
1727 count = 0;
1728 index++;
1729 break;
bca03d5f 1730 case PHY_WRITE:
42b82dc1 1731 rtl_writephy(tp, regno, data);
1732 index++;
1733 break;
1734 case PHY_READCOUNT_EQ_SKIP:
1735 if (count == data)
1736 index += 2;
1737 else
1738 index += 1;
bca03d5f 1739 break;
42b82dc1 1740 case PHY_COMP_EQ_SKIPN:
1741 if (predata == data)
1742 index += regno;
1743 index++;
1744 break;
1745 case PHY_COMP_NEQ_SKIPN:
1746 if (predata != data)
1747 index += regno;
1748 index++;
1749 break;
1750 case PHY_WRITE_PREVIOUS:
1751 rtl_writephy(tp, regno, predata);
1752 index++;
1753 break;
1754 case PHY_SKIPN:
1755 index += regno + 1;
1756 break;
1757 case PHY_DELAY_MS:
1758 mdelay(data);
1759 index++;
1760 break;
1761
1762 case PHY_READ_MAC_BYTE:
1763 case PHY_WRITE_MAC_BYTE:
1764 case PHY_WRITE_ERI_WORD:
bca03d5f 1765 default:
1766 BUG();
1767 }
1768 }
1769}
1770
f1e02ed1 1771static void rtl_release_firmware(struct rtl8169_private *tp)
1772{
1773 release_firmware(tp->fw);
1774 tp->fw = NULL;
1775}
1776
1777static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1778{
1779 const struct firmware **fw = &tp->fw;
1780 int rc = !*fw;
1781
1782 if (rc) {
1783 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1784 if (rc < 0)
1785 goto out;
1786 }
1787
1788 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1789 rtl_phy_write_fw(tp, *fw);
1790out:
1791 return rc;
1792}
1793
4da19633 1794static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1795{
350f7596 1796 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1797 { 0x1f, 0x0001 },
1798 { 0x06, 0x006e },
1799 { 0x08, 0x0708 },
1800 { 0x15, 0x4000 },
1801 { 0x18, 0x65c7 },
1da177e4 1802
0b9b571d 1803 { 0x1f, 0x0001 },
1804 { 0x03, 0x00a1 },
1805 { 0x02, 0x0008 },
1806 { 0x01, 0x0120 },
1807 { 0x00, 0x1000 },
1808 { 0x04, 0x0800 },
1809 { 0x04, 0x0000 },
1da177e4 1810
0b9b571d 1811 { 0x03, 0xff41 },
1812 { 0x02, 0xdf60 },
1813 { 0x01, 0x0140 },
1814 { 0x00, 0x0077 },
1815 { 0x04, 0x7800 },
1816 { 0x04, 0x7000 },
1817
1818 { 0x03, 0x802f },
1819 { 0x02, 0x4f02 },
1820 { 0x01, 0x0409 },
1821 { 0x00, 0xf0f9 },
1822 { 0x04, 0x9800 },
1823 { 0x04, 0x9000 },
1824
1825 { 0x03, 0xdf01 },
1826 { 0x02, 0xdf20 },
1827 { 0x01, 0xff95 },
1828 { 0x00, 0xba00 },
1829 { 0x04, 0xa800 },
1830 { 0x04, 0xa000 },
1831
1832 { 0x03, 0xff41 },
1833 { 0x02, 0xdf20 },
1834 { 0x01, 0x0140 },
1835 { 0x00, 0x00bb },
1836 { 0x04, 0xb800 },
1837 { 0x04, 0xb000 },
1838
1839 { 0x03, 0xdf41 },
1840 { 0x02, 0xdc60 },
1841 { 0x01, 0x6340 },
1842 { 0x00, 0x007d },
1843 { 0x04, 0xd800 },
1844 { 0x04, 0xd000 },
1845
1846 { 0x03, 0xdf01 },
1847 { 0x02, 0xdf20 },
1848 { 0x01, 0x100a },
1849 { 0x00, 0xa0ff },
1850 { 0x04, 0xf800 },
1851 { 0x04, 0xf000 },
1852
1853 { 0x1f, 0x0000 },
1854 { 0x0b, 0x0000 },
1855 { 0x00, 0x9200 }
1856 };
1da177e4 1857
4da19633 1858 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1859}
1860
4da19633 1861static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1862{
350f7596 1863 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1864 { 0x1f, 0x0002 },
1865 { 0x01, 0x90d0 },
1866 { 0x1f, 0x0000 }
1867 };
1868
4da19633 1869 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1870}
1871
4da19633 1872static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1873{
1874 struct pci_dev *pdev = tp->pci_dev;
1875 u16 vendor_id, device_id;
1876
1877 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1878 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1879
1880 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1881 return;
1882
4da19633 1883 rtl_writephy(tp, 0x1f, 0x0001);
1884 rtl_writephy(tp, 0x10, 0xf01b);
1885 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1886}
1887
4da19633 1888static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1889{
350f7596 1890 static const struct phy_reg phy_reg_init[] = {
2e955856 1891 { 0x1f, 0x0001 },
1892 { 0x04, 0x0000 },
1893 { 0x03, 0x00a1 },
1894 { 0x02, 0x0008 },
1895 { 0x01, 0x0120 },
1896 { 0x00, 0x1000 },
1897 { 0x04, 0x0800 },
1898 { 0x04, 0x9000 },
1899 { 0x03, 0x802f },
1900 { 0x02, 0x4f02 },
1901 { 0x01, 0x0409 },
1902 { 0x00, 0xf099 },
1903 { 0x04, 0x9800 },
1904 { 0x04, 0xa000 },
1905 { 0x03, 0xdf01 },
1906 { 0x02, 0xdf20 },
1907 { 0x01, 0xff95 },
1908 { 0x00, 0xba00 },
1909 { 0x04, 0xa800 },
1910 { 0x04, 0xf000 },
1911 { 0x03, 0xdf01 },
1912 { 0x02, 0xdf20 },
1913 { 0x01, 0x101a },
1914 { 0x00, 0xa0ff },
1915 { 0x04, 0xf800 },
1916 { 0x04, 0x0000 },
1917 { 0x1f, 0x0000 },
1918
1919 { 0x1f, 0x0001 },
1920 { 0x10, 0xf41b },
1921 { 0x14, 0xfb54 },
1922 { 0x18, 0xf5c7 },
1923 { 0x1f, 0x0000 },
1924
1925 { 0x1f, 0x0001 },
1926 { 0x17, 0x0cc0 },
1927 { 0x1f, 0x0000 }
1928 };
1929
4da19633 1930 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1931
4da19633 1932 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1933}
1934
4da19633 1935static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1936{
350f7596 1937 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1938 { 0x1f, 0x0001 },
1939 { 0x04, 0x0000 },
1940 { 0x03, 0x00a1 },
1941 { 0x02, 0x0008 },
1942 { 0x01, 0x0120 },
1943 { 0x00, 0x1000 },
1944 { 0x04, 0x0800 },
1945 { 0x04, 0x9000 },
1946 { 0x03, 0x802f },
1947 { 0x02, 0x4f02 },
1948 { 0x01, 0x0409 },
1949 { 0x00, 0xf099 },
1950 { 0x04, 0x9800 },
1951 { 0x04, 0xa000 },
1952 { 0x03, 0xdf01 },
1953 { 0x02, 0xdf20 },
1954 { 0x01, 0xff95 },
1955 { 0x00, 0xba00 },
1956 { 0x04, 0xa800 },
1957 { 0x04, 0xf000 },
1958 { 0x03, 0xdf01 },
1959 { 0x02, 0xdf20 },
1960 { 0x01, 0x101a },
1961 { 0x00, 0xa0ff },
1962 { 0x04, 0xf800 },
1963 { 0x04, 0x0000 },
1964 { 0x1f, 0x0000 },
1965
1966 { 0x1f, 0x0001 },
1967 { 0x0b, 0x8480 },
1968 { 0x1f, 0x0000 },
1969
1970 { 0x1f, 0x0001 },
1971 { 0x18, 0x67c7 },
1972 { 0x04, 0x2000 },
1973 { 0x03, 0x002f },
1974 { 0x02, 0x4360 },
1975 { 0x01, 0x0109 },
1976 { 0x00, 0x3022 },
1977 { 0x04, 0x2800 },
1978 { 0x1f, 0x0000 },
1979
1980 { 0x1f, 0x0001 },
1981 { 0x17, 0x0cc0 },
1982 { 0x1f, 0x0000 }
1983 };
1984
4da19633 1985 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 1986}
1987
4da19633 1988static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 1989{
350f7596 1990 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1991 { 0x10, 0xf41b },
1992 { 0x1f, 0x0000 }
1993 };
1994
4da19633 1995 rtl_writephy(tp, 0x1f, 0x0001);
1996 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 1997
4da19633 1998 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1999}
2000
4da19633 2001static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2002{
350f7596 2003 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2004 { 0x1f, 0x0001 },
2005 { 0x10, 0xf41b },
2006 { 0x1f, 0x0000 }
2007 };
2008
4da19633 2009 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2010}
2011
4da19633 2012static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2013{
350f7596 2014 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2015 { 0x1f, 0x0000 },
2016 { 0x1d, 0x0f00 },
2017 { 0x1f, 0x0002 },
2018 { 0x0c, 0x1ec8 },
2019 { 0x1f, 0x0000 }
2020 };
2021
4da19633 2022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2023}
2024
4da19633 2025static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2026{
350f7596 2027 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2028 { 0x1f, 0x0001 },
2029 { 0x1d, 0x3d98 },
2030 { 0x1f, 0x0000 }
2031 };
2032
4da19633 2033 rtl_writephy(tp, 0x1f, 0x0000);
2034 rtl_patchphy(tp, 0x14, 1 << 5);
2035 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2036
4da19633 2037 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2038}
2039
4da19633 2040static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2041{
350f7596 2042 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2043 { 0x1f, 0x0001 },
2044 { 0x12, 0x2300 },
867763c1
FR		 2045 { 0x1f, 0x0002 },
2046 { 0x00, 0x88d4 },
2047 { 0x01, 0x82b1 },
2048 { 0x03, 0x7002 },
2049 { 0x08, 0x9e30 },
2050 { 0x09, 0x01f0 },
2051 { 0x0a, 0x5500 },
2052 { 0x0c, 0x00c8 },
2053 { 0x1f, 0x0003 },
2054 { 0x12, 0xc096 },
2055 { 0x16, 0x000a },
f50d4275
FR		 2056 { 0x1f, 0x0000 },
2057 { 0x1f, 0x0000 },
2058 { 0x09, 0x2000 },
2059 { 0x09, 0x0000 }
867763c1
FR		 2060 };
2061
4da19633 2062 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2063
4da19633 2064 rtl_patchphy(tp, 0x14, 1 << 5);
2065 rtl_patchphy(tp, 0x0d, 1 << 5);
2066 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2067}
2068
4da19633 2069static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2070{
350f7596 2071 static const struct phy_reg phy_reg_init[] = {
f50d4275 2072 { 0x1f, 0x0001 },
7da97ec9 2073 { 0x12, 0x2300 },
f50d4275
FR		 2074 { 0x03, 0x802f },
2075 { 0x02, 0x4f02 },
2076 { 0x01, 0x0409 },
2077 { 0x00, 0xf099 },
2078 { 0x04, 0x9800 },
2079 { 0x04, 0x9000 },
2080 { 0x1d, 0x3d98 },
7da97ec9
FR		 2081 { 0x1f, 0x0002 },
2082 { 0x0c, 0x7eb8 },
f50d4275
FR		 2083 { 0x06, 0x0761 },
2084 { 0x1f, 0x0003 },
2085 { 0x16, 0x0f0a },
7da97ec9
FR		 2086 { 0x1f, 0x0000 }
2087 };
2088
4da19633 2089 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2090
4da19633 2091 rtl_patchphy(tp, 0x16, 1 << 0);
2092 rtl_patchphy(tp, 0x14, 1 << 5);
2093 rtl_patchphy(tp, 0x0d, 1 << 5);
2094 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2095}
2096
4da19633 2097static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2098{
350f7596 2099 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2100 { 0x1f, 0x0001 },
2101 { 0x12, 0x2300 },
2102 { 0x1d, 0x3d98 },
2103 { 0x1f, 0x0002 },
2104 { 0x0c, 0x7eb8 },
2105 { 0x06, 0x5461 },
2106 { 0x1f, 0x0003 },
2107 { 0x16, 0x0f0a },
2108 { 0x1f, 0x0000 }
2109 };
2110
4da19633 2111 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2112
4da19633 2113 rtl_patchphy(tp, 0x16, 1 << 0);
2114 rtl_patchphy(tp, 0x14, 1 << 5);
2115 rtl_patchphy(tp, 0x0d, 1 << 5);
2116 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2117}
2118
4da19633 2119static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2120{
4da19633 2121 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2122}
2123
bca03d5f 2124static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2125{
350f7596 2126 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2127 /* Channel Estimation */
5b538df9 2128 { 0x1f, 0x0001 },
daf9df6d 2129 { 0x06, 0x4064 },
2130 { 0x07, 0x2863 },
2131 { 0x08, 0x059c },
2132 { 0x09, 0x26b4 },
2133 { 0x0a, 0x6a19 },
2134 { 0x0b, 0xdcc8 },
2135 { 0x10, 0xf06d },
2136 { 0x14, 0x7f68 },
2137 { 0x18, 0x7fd9 },
2138 { 0x1c, 0xf0ff },
2139 { 0x1d, 0x3d9c },
5b538df9 2140 { 0x1f, 0x0003 },
daf9df6d 2141 { 0x12, 0xf49f },
2142 { 0x13, 0x070b },
2143 { 0x1a, 0x05ad },
bca03d5f 2144 { 0x14, 0x94c0 },
2145
2146 /*
2147 * Tx Error Issue
2148 * enhance line driver power
2149 */
5b538df9 2150 { 0x1f, 0x0002 },
daf9df6d 2151 { 0x06, 0x5561 },
2152 { 0x1f, 0x0005 },
2153 { 0x05, 0x8332 },
bca03d5f 2154 { 0x06, 0x5561 },
2155
2156 /*
2157 * Can not link to 1Gbps with bad cable
2158 * Decrease SNR threshold form 21.07dB to 19.04dB
2159 */
2160 { 0x1f, 0x0001 },
2161 { 0x17, 0x0cc0 },
daf9df6d 2162
5b538df9 2163 { 0x1f, 0x0000 },
bca03d5f 2164 { 0x0d, 0xf880 }
daf9df6d 2165 };
bca03d5f 2166 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2167
4da19633 2168 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2169
bca03d5f 2170 /*
2171 * Rx Error Issue
2172 * Fine Tune Switching regulator parameter
2173 */
4da19633 2174 rtl_writephy(tp, 0x1f, 0x0002);
2175 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2176 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2177
daf9df6d 2178 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2179 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2180 { 0x1f, 0x0002 },
2181 { 0x05, 0x669a },
2182 { 0x1f, 0x0005 },
2183 { 0x05, 0x8330 },
2184 { 0x06, 0x669a },
2185 { 0x1f, 0x0002 }
2186 };
2187 int val;
2188
4da19633 2189 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2190
4da19633 2191 val = rtl_readphy(tp, 0x0d);
daf9df6d 2192
2193 if ((val & 0x00ff) != 0x006c) {
350f7596 2194 static const u32 set[] = {
daf9df6d 2195 0x0065, 0x0066, 0x0067, 0x0068,
2196 0x0069, 0x006a, 0x006b, 0x006c
2197 };
2198 int i;
2199
4da19633 2200 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2201
2202 val &= 0xff00;
2203 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2204 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2205 }
2206 } else {
350f7596 2207 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2208 { 0x1f, 0x0002 },
2209 { 0x05, 0x6662 },
2210 { 0x1f, 0x0005 },
2211 { 0x05, 0x8330 },
2212 { 0x06, 0x6662 }
2213 };
2214
4da19633 2215 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2216 }
2217
bca03d5f 2218 /* RSET couple improve */
4da19633 2219 rtl_writephy(tp, 0x1f, 0x0002);
2220 rtl_patchphy(tp, 0x0d, 0x0300);
2221 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2222
bca03d5f 2223 /* Fine tune PLL performance */
4da19633 2224 rtl_writephy(tp, 0x1f, 0x0002);
2225 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2226 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2227
4da19633 2228 rtl_writephy(tp, 0x1f, 0x0005);
2229 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2230 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2231 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
bca03d5f 2232 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2233 }
2234
4da19633 2235 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2236}
2237
bca03d5f 2238static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2239{
350f7596 2240 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2241 /* Channel Estimation */
daf9df6d 2242 { 0x1f, 0x0001 },
2243 { 0x06, 0x4064 },
2244 { 0x07, 0x2863 },
2245 { 0x08, 0x059c },
2246 { 0x09, 0x26b4 },
2247 { 0x0a, 0x6a19 },
2248 { 0x0b, 0xdcc8 },
2249 { 0x10, 0xf06d },
2250 { 0x14, 0x7f68 },
2251 { 0x18, 0x7fd9 },
2252 { 0x1c, 0xf0ff },
2253 { 0x1d, 0x3d9c },
2254 { 0x1f, 0x0003 },
2255 { 0x12, 0xf49f },
2256 { 0x13, 0x070b },
2257 { 0x1a, 0x05ad },
2258 { 0x14, 0x94c0 },
2259
bca03d5f 2260 /*
2261 * Tx Error Issue
2262 * enhance line driver power
2263 */
daf9df6d 2264 { 0x1f, 0x0002 },
2265 { 0x06, 0x5561 },
2266 { 0x1f, 0x0005 },
2267 { 0x05, 0x8332 },
bca03d5f 2268 { 0x06, 0x5561 },
2269
2270 /*
2271 * Can not link to 1Gbps with bad cable
2272 * Decrease SNR threshold form 21.07dB to 19.04dB
2273 */
2274 { 0x1f, 0x0001 },
2275 { 0x17, 0x0cc0 },
daf9df6d 2276
2277 { 0x1f, 0x0000 },
bca03d5f 2278 { 0x0d, 0xf880 }
5b538df9 2279 };
bca03d5f 2280 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2281
4da19633 2282 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2283
daf9df6d 2284 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2285 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2286 { 0x1f, 0x0002 },
2287 { 0x05, 0x669a },
5b538df9 2288 { 0x1f, 0x0005 },
daf9df6d 2289 { 0x05, 0x8330 },
2290 { 0x06, 0x669a },
2291
2292 { 0x1f, 0x0002 }
2293 };
2294 int val;
2295
4da19633 2296 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2297
4da19633 2298 val = rtl_readphy(tp, 0x0d);
daf9df6d 2299 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2300 static const u32 set[] = {
daf9df6d 2301 0x0065, 0x0066, 0x0067, 0x0068,
2302 0x0069, 0x006a, 0x006b, 0x006c
2303 };
2304 int i;
2305
4da19633 2306 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2307
2308 val &= 0xff00;
2309 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2310 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2311 }
2312 } else {
350f7596 2313 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2314 { 0x1f, 0x0002 },
2315 { 0x05, 0x2642 },
5b538df9 2316 { 0x1f, 0x0005 },
daf9df6d 2317 { 0x05, 0x8330 },
2318 { 0x06, 0x2642 }
5b538df9
FR		 2319 };
2320
4da19633 2321 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2322 }
2323
bca03d5f 2324 /* Fine tune PLL performance */
4da19633 2325 rtl_writephy(tp, 0x1f, 0x0002);
2326 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2327 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2328
bca03d5f 2329 /* Switching regulator Slew rate */
4da19633 2330 rtl_writephy(tp, 0x1f, 0x0002);
2331 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2332
4da19633 2333 rtl_writephy(tp, 0x1f, 0x0005);
2334 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2335 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2336 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
bca03d5f 2337 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2338 }
2339
4da19633 2340 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2341}
2342
4da19633 2343static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2344{
350f7596 2345 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2346 { 0x1f, 0x0002 },
2347 { 0x10, 0x0008 },
2348 { 0x0d, 0x006c },
2349
2350 { 0x1f, 0x0000 },
2351 { 0x0d, 0xf880 },
2352
2353 { 0x1f, 0x0001 },
2354 { 0x17, 0x0cc0 },
2355
2356 { 0x1f, 0x0001 },
2357 { 0x0b, 0xa4d8 },
2358 { 0x09, 0x281c },
2359 { 0x07, 0x2883 },
2360 { 0x0a, 0x6b35 },
2361 { 0x1d, 0x3da4 },
2362 { 0x1c, 0xeffd },
2363 { 0x14, 0x7f52 },
2364 { 0x18, 0x7fc6 },
2365 { 0x08, 0x0601 },
2366 { 0x06, 0x4063 },
2367 { 0x10, 0xf074 },
2368 { 0x1f, 0x0003 },
2369 { 0x13, 0x0789 },
2370 { 0x12, 0xf4bd },
2371 { 0x1a, 0x04fd },
2372 { 0x14, 0x84b0 },
2373 { 0x1f, 0x0000 },
2374 { 0x00, 0x9200 },
2375
2376 { 0x1f, 0x0005 },
2377 { 0x01, 0x0340 },
2378 { 0x1f, 0x0001 },
2379 { 0x04, 0x4000 },
2380 { 0x03, 0x1d21 },
2381 { 0x02, 0x0c32 },
2382 { 0x01, 0x0200 },
2383 { 0x00, 0x5554 },
2384 { 0x04, 0x4800 },
2385 { 0x04, 0x4000 },
2386 { 0x04, 0xf000 },
2387 { 0x03, 0xdf01 },
2388 { 0x02, 0xdf20 },
2389 { 0x01, 0x101a },
2390 { 0x00, 0xa0ff },
2391 { 0x04, 0xf800 },
2392 { 0x04, 0xf000 },
2393 { 0x1f, 0x0000 },
2394
2395 { 0x1f, 0x0007 },
2396 { 0x1e, 0x0023 },
2397 { 0x16, 0x0000 },
2398 { 0x1f, 0x0000 }
2399 };
2400
4da19633 2401 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2402}
2403
e6de30d6 2404static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2405{
2406 static const struct phy_reg phy_reg_init[] = {
2407 { 0x1f, 0x0001 },
2408 { 0x17, 0x0cc0 },
2409
2410 { 0x1f, 0x0007 },
2411 { 0x1e, 0x002d },
2412 { 0x18, 0x0040 },
2413 { 0x1f, 0x0000 }
2414 };
2415
2416 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2417 rtl_patchphy(tp, 0x0d, 1 << 5);
2418}
2419
4da19633 2420static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2421{
350f7596 2422 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2423 { 0x1f, 0x0003 },
2424 { 0x08, 0x441d },
2425 { 0x01, 0x9100 },
2426 { 0x1f, 0x0000 }
2427 };
2428
4da19633 2429 rtl_writephy(tp, 0x1f, 0x0000);
2430 rtl_patchphy(tp, 0x11, 1 << 12);
2431 rtl_patchphy(tp, 0x19, 1 << 13);
2432 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2433
4da19633 2434 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2435}
2436
5615d9f1
FR		 2437static void rtl_hw_phy_config(struct net_device *dev)
2438{
2439 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2440
2441 rtl8169_print_mac_version(tp);
2442
2443 switch (tp->mac_version) {
2444 case RTL_GIGA_MAC_VER_01:
2445 break;
2446 case RTL_GIGA_MAC_VER_02:
2447 case RTL_GIGA_MAC_VER_03:
4da19633 2448 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2449 break;
2450 case RTL_GIGA_MAC_VER_04:
4da19633 2451 rtl8169sb_hw_phy_config(tp);
5615d9f1 2452 break;
2e955856 2453 case RTL_GIGA_MAC_VER_05:
4da19633 2454 rtl8169scd_hw_phy_config(tp);
2e955856 2455 break;
8c7006aa 2456 case RTL_GIGA_MAC_VER_06:
4da19633 2457 rtl8169sce_hw_phy_config(tp);
8c7006aa 2458 break;
2857ffb7
FR		 2459 case RTL_GIGA_MAC_VER_07:
2460 case RTL_GIGA_MAC_VER_08:
2461 case RTL_GIGA_MAC_VER_09:
4da19633 2462 rtl8102e_hw_phy_config(tp);
2857ffb7 2463 break;
236b8082 2464 case RTL_GIGA_MAC_VER_11:
4da19633 2465 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2466 break;
2467 case RTL_GIGA_MAC_VER_12:
4da19633 2468 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2469 break;
2470 case RTL_GIGA_MAC_VER_17:
4da19633 2471 rtl8168bef_hw_phy_config(tp);
236b8082 2472 break;
867763c1 2473 case RTL_GIGA_MAC_VER_18:
4da19633 2474 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2475 break;
2476 case RTL_GIGA_MAC_VER_19:
4da19633 2477 rtl8168c_1_hw_phy_config(tp);
867763c1 2478 break;
7da97ec9 2479 case RTL_GIGA_MAC_VER_20:
4da19633 2480 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2481 break;
197ff761 2482 case RTL_GIGA_MAC_VER_21:
4da19633 2483 rtl8168c_3_hw_phy_config(tp);
197ff761 2484 break;
6fb07058 2485 case RTL_GIGA_MAC_VER_22:
4da19633 2486 rtl8168c_4_hw_phy_config(tp);
6fb07058 2487 break;
ef3386f0 2488 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2489 case RTL_GIGA_MAC_VER_24:
4da19633 2490 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2491 break;
5b538df9 2492 case RTL_GIGA_MAC_VER_25:
bca03d5f 2493 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2494 break;
2495 case RTL_GIGA_MAC_VER_26:
bca03d5f 2496 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2497 break;
2498 case RTL_GIGA_MAC_VER_27:
4da19633 2499 rtl8168d_3_hw_phy_config(tp);
5b538df9 2500 break;
e6de30d6 2501 case RTL_GIGA_MAC_VER_28:
2502 rtl8168d_4_hw_phy_config(tp);
2503 break;
ef3386f0 2504
5615d9f1
FR		 2505 default:
2506 break;
2507 }
2508}
2509
1da177e4
LT		 2510static void rtl8169_phy_timer(unsigned long __opaque)
2511{
2512 struct net_device *dev = (struct net_device *)__opaque;
2513 struct rtl8169_private *tp = netdev_priv(dev);
2514 struct timer_list *timer = &tp->timer;
2515 void __iomem *ioaddr = tp->mmio_addr;
2516 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2517
bcf0bf90 2518 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2519
64e4bfb4 2520 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2521 return;
2522
2523 spin_lock_irq(&tp->lock);
2524
4da19633 2525 if (tp->phy_reset_pending(tp)) {
5b0384f4 2526 /*
1da177e4
LT		 2527 * A busy loop could burn quite a few cycles on nowadays CPU.
2528 * Let's delay the execution of the timer for a few ticks.
2529 */
2530 timeout = HZ/10;
2531 goto out_mod_timer;
2532 }
2533
2534 if (tp->link_ok(ioaddr))
2535 goto out_unlock;
2536
bf82c189 2537 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2538
4da19633 2539 tp->phy_reset_enable(tp);
1da177e4
LT		 2540
2541out_mod_timer:
2542 mod_timer(timer, jiffies + timeout);
2543out_unlock:
2544 spin_unlock_irq(&tp->lock);
2545}
2546
2547static inline void rtl8169_delete_timer(struct net_device *dev)
2548{
2549 struct rtl8169_private *tp = netdev_priv(dev);
2550 struct timer_list *timer = &tp->timer;
2551
e179bb7b 2552 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2553 return;
2554
2555 del_timer_sync(timer);
2556}
2557
2558static inline void rtl8169_request_timer(struct net_device *dev)
2559{
2560 struct rtl8169_private *tp = netdev_priv(dev);
2561 struct timer_list *timer = &tp->timer;
2562
e179bb7b 2563 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2564 return;
2565
2efa53f3 2566 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2567}
2568
2569#ifdef CONFIG_NET_POLL_CONTROLLER
2570/*
2571 * Polling 'interrupt' - used by things like netconsole to send skbs
2572 * without having to re-enable interrupts. It's not called while
2573 * the interrupt routine is executing.
2574 */
2575static void rtl8169_netpoll(struct net_device *dev)
2576{
2577 struct rtl8169_private *tp = netdev_priv(dev);
2578 struct pci_dev *pdev = tp->pci_dev;
2579
2580 disable_irq(pdev->irq);
7d12e780 2581 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2582 enable_irq(pdev->irq);
2583}
2584#endif
2585
2586static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2587 void __iomem *ioaddr)
2588{
2589 iounmap(ioaddr);
2590 pci_release_regions(pdev);
87aeec76 2591 pci_clear_mwi(pdev);
1da177e4
LT		 2592 pci_disable_device(pdev);
2593 free_netdev(dev);
2594}
2595
bf793295
FR		 2596static void rtl8169_phy_reset(struct net_device *dev,
2597 struct rtl8169_private *tp)
2598{
07d3f51f 2599 unsigned int i;
bf793295 2600
4da19633 2601 tp->phy_reset_enable(tp);
bf793295 2602 for (i = 0; i < 100; i++) {
4da19633 2603 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2604 return;
2605 msleep(1);
2606 }
bf82c189 2607 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2608}
2609
4ff96fa6
FR		 2610static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2611{
2612 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2613
5615d9f1 2614 rtl_hw_phy_config(dev);
4ff96fa6 2615
77332894
MS		 2616 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2617 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2618 RTL_W8(0x82, 0x01);
2619 }
4ff96fa6 2620
6dccd16b
FR		 2621 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2622
2623 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2624 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2625
bcf0bf90 2626 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2627 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2628 RTL_W8(0x82, 0x01);
2629 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2630 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2631 }
2632
bf793295
FR		 2633 rtl8169_phy_reset(dev, tp);
2634
901dda2b
FR		 2635 /*
2636 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2637 * only 8101. Don't panic.
2638 */
2639 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2640
bf82c189
JP		 2641 if (RTL_R8(PHYstatus) & TBI_Enable)
2642 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2643}
2644
773d2021
FR		 2645static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2646{
2647 void __iomem *ioaddr = tp->mmio_addr;
2648 u32 high;
2649 u32 low;
2650
2651 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2652 high = addr[4] | (addr[5] << 8);
2653
2654 spin_lock_irq(&tp->lock);
2655
2656 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2657
773d2021 2658 RTL_W32(MAC4, high);
908ba2bf 2659 RTL_R32(MAC4);
2660
78f1cd02 2661 RTL_W32(MAC0, low);
908ba2bf 2662 RTL_R32(MAC0);
2663
773d2021
FR		 2664 RTL_W8(Cfg9346, Cfg9346_Lock);
2665
2666 spin_unlock_irq(&tp->lock);
2667}
2668
2669static int rtl_set_mac_address(struct net_device *dev, void *p)
2670{
2671 struct rtl8169_private *tp = netdev_priv(dev);
2672 struct sockaddr *addr = p;
2673
2674 if (!is_valid_ether_addr(addr->sa_data))
2675 return -EADDRNOTAVAIL;
2676
2677 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2678
2679 rtl_rar_set(tp, dev->dev_addr);
2680
2681 return 0;
2682}
2683
5f787a1a
FR		 2684static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2685{
2686 struct rtl8169_private *tp = netdev_priv(dev);
2687 struct mii_ioctl_data *data = if_mii(ifr);
2688
8b4ab28d
FR		 2689 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2690}
5f787a1a 2691
8b4ab28d
FR		 2692static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2693{
5f787a1a
FR		 2694 switch (cmd) {
2695 case SIOCGMIIPHY:
2696 data->phy_id = 32; /* Internal PHY */
2697 return 0;
2698
2699 case SIOCGMIIREG:
4da19633 2700 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2701 return 0;
2702
2703 case SIOCSMIIREG:
4da19633 2704 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2705 return 0;
2706 }
2707 return -EOPNOTSUPP;
2708}
2709
8b4ab28d
FR		 2710static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2711{
2712 return -EOPNOTSUPP;
2713}
2714
0e485150
FR		 2715static const struct rtl_cfg_info {
2716 void (*hw_start)(struct net_device *);
2717 unsigned int region;
2718 unsigned int align;
2719 u16 intr_event;
2720 u16 napi_event;
ccdffb9a 2721 unsigned features;
f21b75e9 2722 u8 default_ver;
0e485150
FR		 2723} rtl_cfg_infos [] = {
2724 [RTL_CFG_0] = {
2725 .hw_start = rtl_hw_start_8169,
2726 .region = 1,
e9f63f30 2727 .align = 0,
0e485150
FR		 2728 .intr_event = SYSErr | LinkChg | RxOverflow |
2729 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2730 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2731 .features = RTL_FEATURE_GMII,
2732 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2733 },
2734 [RTL_CFG_1] = {
2735 .hw_start = rtl_hw_start_8168,
2736 .region = 2,
2737 .align = 8,
53f57357 2738 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2739 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2740 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2741 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2742 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2743 },
2744 [RTL_CFG_2] = {
2745 .hw_start = rtl_hw_start_8101,
2746 .region = 2,
2747 .align = 8,
2748 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2749 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2750 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2751 .features = RTL_FEATURE_MSI,
2752 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2753 }
2754};
2755
fbac58fc
FR		 2756/* Cfg9346_Unlock assumed. */
2757static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2758 const struct rtl_cfg_info *cfg)
2759{
2760 unsigned msi = 0;
2761 u8 cfg2;
2762
2763 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2764 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2765 if (pci_enable_msi(pdev)) {
2766 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2767 } else {
2768 cfg2 |= MSIEnable;
2769 msi = RTL_FEATURE_MSI;
2770 }
2771 }
2772 RTL_W8(Config2, cfg2);
2773 return msi;
2774}
2775
2776static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2777{
2778 if (tp->features & RTL_FEATURE_MSI) {
2779 pci_disable_msi(pdev);
2780 tp->features &= ~RTL_FEATURE_MSI;
2781 }
2782}
2783
8b4ab28d
FR		 2784static const struct net_device_ops rtl8169_netdev_ops = {
2785 .ndo_open = rtl8169_open,
2786 .ndo_stop = rtl8169_close,
2787 .ndo_get_stats = rtl8169_get_stats,
00829823 2788 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2789 .ndo_tx_timeout = rtl8169_tx_timeout,
2790 .ndo_validate_addr = eth_validate_addr,
2791 .ndo_change_mtu = rtl8169_change_mtu,
2792 .ndo_set_mac_address = rtl_set_mac_address,
2793 .ndo_do_ioctl = rtl8169_ioctl,
2794 .ndo_set_multicast_list = rtl_set_rx_mode,
2795#ifdef CONFIG_R8169_VLAN
2796 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2797#endif
2798#ifdef CONFIG_NET_POLL_CONTROLLER
2799 .ndo_poll_controller = rtl8169_netpoll,
2800#endif
2801
2802};
2803
c0e45c1c 2804static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2805{
2806 struct mdio_ops *ops = &tp->mdio_ops;
2807
2808 switch (tp->mac_version) {
2809 case RTL_GIGA_MAC_VER_27:
2810 ops->write = r8168dp_1_mdio_write;
2811 ops->read = r8168dp_1_mdio_read;
2812 break;
e6de30d6 2813 case RTL_GIGA_MAC_VER_28:
2814 ops->write = r8168dp_2_mdio_write;
2815 ops->read = r8168dp_2_mdio_read;
2816 break;
c0e45c1c 2817 default:
2818 ops->write = r8169_mdio_write;
2819 ops->read = r8169_mdio_read;
2820 break;
2821 }
2822}
2823
065c27c1 2824static void r810x_phy_power_down(struct rtl8169_private *tp)
2825{
2826 rtl_writephy(tp, 0x1f, 0x0000);
2827 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2828}
2829
2830static void r810x_phy_power_up(struct rtl8169_private *tp)
2831{
2832 rtl_writephy(tp, 0x1f, 0x0000);
2833 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2834}
2835
2836static void r810x_pll_power_down(struct rtl8169_private *tp)
2837{
2838 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2839 rtl_writephy(tp, 0x1f, 0x0000);
2840 rtl_writephy(tp, MII_BMCR, 0x0000);
2841 return;
2842 }
2843
2844 r810x_phy_power_down(tp);
2845}
2846
2847static void r810x_pll_power_up(struct rtl8169_private *tp)
2848{
2849 r810x_phy_power_up(tp);
2850}
2851
2852static void r8168_phy_power_up(struct rtl8169_private *tp)
2853{
2854 rtl_writephy(tp, 0x1f, 0x0000);
2855 rtl_writephy(tp, 0x0e, 0x0000);
2856 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2857}
2858
2859static void r8168_phy_power_down(struct rtl8169_private *tp)
2860{
2861 rtl_writephy(tp, 0x1f, 0x0000);
2862 rtl_writephy(tp, 0x0e, 0x0200);
2863 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2864}
2865
2866static void r8168_pll_power_down(struct rtl8169_private *tp)
2867{
2868 void __iomem *ioaddr = tp->mmio_addr;
2869
2870 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2871 return;
2872
2873 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2874 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2875 (RTL_R16(CPlusCmd) & ASF)) {
2876 return;
2877 }
2878
2879 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2880 rtl_writephy(tp, 0x1f, 0x0000);
2881 rtl_writephy(tp, MII_BMCR, 0x0000);
2882
2883 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2884 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2885 return;
2886 }
2887
2888 r8168_phy_power_down(tp);
2889
2890 switch (tp->mac_version) {
2891 case RTL_GIGA_MAC_VER_25:
2892 case RTL_GIGA_MAC_VER_26:
2893 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2894 break;
2895 }
2896}
2897
2898static void r8168_pll_power_up(struct rtl8169_private *tp)
2899{
2900 void __iomem *ioaddr = tp->mmio_addr;
2901
2902 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2903 return;
2904
2905 switch (tp->mac_version) {
2906 case RTL_GIGA_MAC_VER_25:
2907 case RTL_GIGA_MAC_VER_26:
2908 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2909 break;
2910 }
2911
2912 r8168_phy_power_up(tp);
2913}
2914
2915static void rtl_pll_power_op(struct rtl8169_private *tp,
2916 void (*op)(struct rtl8169_private *))
2917{
2918 if (op)
2919 op(tp);
2920}
2921
2922static void rtl_pll_power_down(struct rtl8169_private *tp)
2923{
2924 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2925}
2926
2927static void rtl_pll_power_up(struct rtl8169_private *tp)
2928{
2929 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2930}
2931
2932static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2933{
2934 struct pll_power_ops *ops = &tp->pll_power_ops;
2935
2936 switch (tp->mac_version) {
2937 case RTL_GIGA_MAC_VER_07:
2938 case RTL_GIGA_MAC_VER_08:
2939 case RTL_GIGA_MAC_VER_09:
2940 case RTL_GIGA_MAC_VER_10:
2941 case RTL_GIGA_MAC_VER_16:
2942 ops->down = r810x_pll_power_down;
2943 ops->up = r810x_pll_power_up;
2944 break;
2945
2946 case RTL_GIGA_MAC_VER_11:
2947 case RTL_GIGA_MAC_VER_12:
2948 case RTL_GIGA_MAC_VER_17:
2949 case RTL_GIGA_MAC_VER_18:
2950 case RTL_GIGA_MAC_VER_19:
2951 case RTL_GIGA_MAC_VER_20:
2952 case RTL_GIGA_MAC_VER_21:
2953 case RTL_GIGA_MAC_VER_22:
2954 case RTL_GIGA_MAC_VER_23:
2955 case RTL_GIGA_MAC_VER_24:
2956 case RTL_GIGA_MAC_VER_25:
2957 case RTL_GIGA_MAC_VER_26:
2958 case RTL_GIGA_MAC_VER_27:
e6de30d6 2959 case RTL_GIGA_MAC_VER_28:
065c27c1 2960 ops->down = r8168_pll_power_down;
2961 ops->up = r8168_pll_power_up;
2962 break;
2963
2964 default:
2965 ops->down = NULL;
2966 ops->up = NULL;
2967 break;
2968 }
2969}
2970
1da177e4 2971static int __devinit
4ff96fa6 2972rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2973{
0e485150
FR		 2974 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2975 const unsigned int region = cfg->region;
1da177e4 2976 struct rtl8169_private *tp;
ccdffb9a 2977 struct mii_if_info *mii;
4ff96fa6
FR		 2978 struct net_device *dev;
2979 void __iomem *ioaddr;
07d3f51f
FR		 2980 unsigned int i;
2981 int rc;
1da177e4 2982
4ff96fa6
FR		 2983 if (netif_msg_drv(&debug)) {
2984 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2985 MODULENAME, RTL8169_VERSION);
2986 }
1da177e4 2987
1da177e4 2988 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2989 if (!dev) {
b57b7e5a 2990 if (netif_msg_drv(&debug))
9b91cf9d 2991 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2992 rc = -ENOMEM;
2993 goto out;
1da177e4
LT		 2994 }
2995
1da177e4 2996 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2997 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2998 tp = netdev_priv(dev);
c4028958 2999 tp->dev = dev;
21e197f2 3000 tp->pci_dev = pdev;
b57b7e5a 3001 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3002
ccdffb9a
FR		 3003 mii = &tp->mii;
3004 mii->dev = dev;
3005 mii->mdio_read = rtl_mdio_read;
3006 mii->mdio_write = rtl_mdio_write;
3007 mii->phy_id_mask = 0x1f;
3008 mii->reg_num_mask = 0x1f;
3009 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3010
1da177e4
LT		 3011 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3012 rc = pci_enable_device(pdev);
b57b7e5a 3013 if (rc < 0) {
bf82c189 3014 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3015 goto err_out_free_dev_1;
1da177e4
LT		 3016 }
3017
87aeec76 3018 if (pci_set_mwi(pdev) < 0)
3019 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3020
1da177e4 3021 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3022 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3023 netif_err(tp, probe, dev,
3024 "region #%d not an MMIO resource, aborting\n",
3025 region);
1da177e4 3026 rc = -ENODEV;
87aeec76 3027 goto err_out_mwi_2;
1da177e4 3028 }
4ff96fa6 3029
1da177e4 3030 /* check for weird/broken PCI region reporting */
bcf0bf90 3031 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3032 netif_err(tp, probe, dev,
3033 "Invalid PCI region size(s), aborting\n");
1da177e4 3034 rc = -ENODEV;
87aeec76 3035 goto err_out_mwi_2;
1da177e4
LT		 3036 }
3037
3038 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3039 if (rc < 0) {
bf82c189 3040 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3041 goto err_out_mwi_2;
1da177e4
LT		 3042 }
3043
3044 tp->cp_cmd = PCIMulRW | RxChkSum;
3045
3046 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3047 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3048 tp->cp_cmd |= PCIDAC;
3049 dev->features |= NETIF_F_HIGHDMA;
3050 } else {
284901a9 3051 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3052 if (rc < 0) {
bf82c189 3053 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3054 goto err_out_free_res_3;
1da177e4
LT		 3055 }
3056 }
3057
1da177e4 3058 /* ioremap MMIO region */
bcf0bf90 3059 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3060 if (!ioaddr) {
bf82c189 3061 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3062 rc = -EIO;
87aeec76 3063 goto err_out_free_res_3;
1da177e4
LT		 3064 }
3065
4300e8c7
DM		 3066 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3067 if (!tp->pcie_cap)
3068 netif_info(tp, probe, dev, "no PCI Express capability\n");
3069
d78ad8cb 3070 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3071
3072 /* Soft reset the chip. */
3073 RTL_W8(ChipCmd, CmdReset);
3074
3075 /* Check that the chip has finished the reset. */
07d3f51f 3076 for (i = 0; i < 100; i++) {
1da177e4
LT		 3077 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3078 break;
b518fa8e 3079 msleep_interruptible(1);
1da177e4
LT		 3080 }
3081
d78ad8cb
KW		 3082 RTL_W16(IntrStatus, 0xffff);
3083
ca52efd5 3084 pci_set_master(pdev);
3085
1da177e4
LT		 3086 /* Identify chip attached to board */
3087 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3088
c0e45c1c 3089 rtl_init_mdio_ops(tp);
065c27c1 3090 rtl_init_pll_power_ops(tp);
c0e45c1c 3091
f21b75e9
JD		 3092 /* Use appropriate default if unknown */
3093 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3094 netif_notice(tp, probe, dev,
3095 "unknown MAC, using family default\n");
f21b75e9
JD		 3096 tp->mac_version = cfg->default_ver;
3097 }
3098
1da177e4 3099 rtl8169_print_mac_version(tp);
1da177e4 3100
cee60c37 3101 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3102 if (tp->mac_version == rtl_chip_info[i].mac_version)
3103 break;
3104 }
cee60c37 3105 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3106 dev_err(&pdev->dev,
3107 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3108 goto err_out_msi_4;
1da177e4
LT		 3109 }
3110 tp->chipset = i;
3111
5d06a99f
FR		 3112 RTL_W8(Cfg9346, Cfg9346_Unlock);
3113 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3114 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3115 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3116 tp->features |= RTL_FEATURE_WOL;
3117 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3118 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3119 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3120 RTL_W8(Cfg9346, Cfg9346_Lock);
3121
66ec5d4f
FR		 3122 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3123 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3124 tp->set_speed = rtl8169_set_speed_tbi;
3125 tp->get_settings = rtl8169_gset_tbi;
3126 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3127 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3128 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3129 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3130
64e4bfb4 3131 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3132 } else {
3133 tp->set_speed = rtl8169_set_speed_xmii;
3134 tp->get_settings = rtl8169_gset_xmii;
3135 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3136 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3137 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3138 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3139 }
3140
df58ef51
FR		 3141 spin_lock_init(&tp->lock);
3142
738e1e69
PV		 3143 tp->mmio_addr = ioaddr;
3144
7bf6bf48 3145 /* Get MAC address */
1da177e4
LT		 3146 for (i = 0; i < MAC_ADDR_LEN; i++)
3147 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3148 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3149
1da177e4 3150 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3151 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3152 dev->irq = pdev->irq;
3153 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3154
bea3348e 3155 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3156
3157#ifdef CONFIG_R8169_VLAN
3158 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3159#endif
2edae08e 3160 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3161
3162 tp->intr_mask = 0xffff;
0e485150
FR		 3163 tp->hw_start = cfg->hw_start;
3164 tp->intr_event = cfg->intr_event;
3165 tp->napi_event = cfg->napi_event;
1da177e4 3166
2efa53f3
FR		 3167 init_timer(&tp->timer);
3168 tp->timer.data = (unsigned long) dev;
3169 tp->timer.function = rtl8169_phy_timer;
3170
1da177e4 3171 rc = register_netdev(dev);
4ff96fa6 3172 if (rc < 0)
87aeec76 3173 goto err_out_msi_4;
1da177e4
LT		 3174
3175 pci_set_drvdata(pdev, dev);
3176
bf82c189
JP		 3177 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3178 rtl_chip_info[tp->chipset].name,
3179 dev->base_addr, dev->dev_addr,
3180 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3181
e6de30d6 3182 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3183 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3184 rtl8168_driver_start(tp);
e6de30d6 3185 }
b646d900 3186
8b76ab39 3187 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3188
f3ec4f87
AS		 3189 if (pci_dev_run_wake(pdev))
3190 pm_runtime_put_noidle(&pdev->dev);
e1759441 3191
4ff96fa6
FR		 3192out:
3193 return rc;
1da177e4 3194
87aeec76 3195err_out_msi_4:
fbac58fc 3196 rtl_disable_msi(pdev, tp);
4ff96fa6 3197 iounmap(ioaddr);
87aeec76 3198err_out_free_res_3:
4ff96fa6 3199 pci_release_regions(pdev);
87aeec76 3200err_out_mwi_2:
4ff96fa6 3201 pci_clear_mwi(pdev);
4ff96fa6
FR		 3202 pci_disable_device(pdev);
3203err_out_free_dev_1:
3204 free_netdev(dev);
3205 goto out;
1da177e4
LT		 3206}
3207
07d3f51f 3208static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3209{
3210 struct net_device *dev = pci_get_drvdata(pdev);
3211 struct rtl8169_private *tp = netdev_priv(dev);
3212
e6de30d6 3213 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3214 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3215 rtl8168_driver_stop(tp);
e6de30d6 3216 }
b646d900 3217
23f333a2 3218 cancel_delayed_work_sync(&tp->task);
eb2a021c 3219
f1e02ed1 3220 rtl_release_firmware(tp);
3221
1da177e4 3222 unregister_netdev(dev);
cc098dc7 3223
f3ec4f87
AS		 3224 if (pci_dev_run_wake(pdev))
3225 pm_runtime_get_noresume(&pdev->dev);
e1759441 3226
cc098dc7
IV		 3227 /* restore original MAC address */
3228 rtl_rar_set(tp, dev->perm_addr);
3229
fbac58fc 3230 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3231 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3232 pci_set_drvdata(pdev, NULL);
3233}
3234
1da177e4
LT		 3235static int rtl8169_open(struct net_device *dev)
3236{
3237 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3238 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3239 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3240 int retval = -ENOMEM;
1da177e4 3241
e1759441 3242 pm_runtime_get_sync(&pdev->dev);
1da177e4 3243
1da177e4
LT		 3244 /*
3245 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3246 * dma_alloc_coherent provides more.
1da177e4 3247 */
82553bb6
SG		 3248 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3249 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3250 if (!tp->TxDescArray)
e1759441 3251 goto err_pm_runtime_put;
1da177e4 3252
82553bb6
SG		 3253 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3254 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3255 if (!tp->RxDescArray)
99f252b0 3256 goto err_free_tx_0;
1da177e4
LT		 3257
3258 retval = rtl8169_init_ring(dev);
3259 if (retval < 0)
99f252b0 3260 goto err_free_rx_1;
1da177e4 3261
c4028958 3262 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3263
99f252b0
FR		 3264 smp_mb();
3265
fbac58fc
FR		 3266 retval = request_irq(dev->irq, rtl8169_interrupt,
3267 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3268 dev->name, dev);
3269 if (retval < 0)
3270 goto err_release_ring_2;
3271
bea3348e 3272 napi_enable(&tp->napi);
bea3348e 3273
eee3a96c 3274 rtl8169_init_phy(dev, tp);
3275
3276 /*
3277 * Pretend we are using VLANs; This bypasses a nasty bug where
3278 * Interrupts stop flowing on high load on 8110SCd controllers.
3279 */
3280 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3281 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3282
065c27c1 3283 rtl_pll_power_up(tp);
3284
07ce4064 3285 rtl_hw_start(dev);
1da177e4
LT		 3286
3287 rtl8169_request_timer(dev);
3288
e1759441
RW		 3289 tp->saved_wolopts = 0;
3290 pm_runtime_put_noidle(&pdev->dev);
3291
eee3a96c 3292 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3293out:
3294 return retval;
3295
99f252b0
FR		 3296err_release_ring_2:
3297 rtl8169_rx_clear(tp);
3298err_free_rx_1:
82553bb6
SG		 3299 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3300 tp->RxPhyAddr);
e1759441 3301 tp->RxDescArray = NULL;
99f252b0 3302err_free_tx_0:
82553bb6
SG		 3303 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3304 tp->TxPhyAddr);
e1759441
RW		 3305 tp->TxDescArray = NULL;
3306err_pm_runtime_put:
3307 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3308 goto out;
3309}
3310
e6de30d6 3311static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3312{
e6de30d6 3313 void __iomem *ioaddr = tp->mmio_addr;
3314
1da177e4
LT		 3315 /* Disable interrupts */
3316 rtl8169_irq_mask_and_ack(ioaddr);
3317
e6de30d6 3318 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3319 while (RTL_R8(TxPoll) & NPQ)
3320 udelay(20);
3321
3322 }
3323
1da177e4
LT		 3324 /* Reset the chipset */
3325 RTL_W8(ChipCmd, CmdReset);
3326
3327 /* PCI commit */
3328 RTL_R8(ChipCmd);
3329}
3330
7f796d83 3331static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3332{
3333 void __iomem *ioaddr = tp->mmio_addr;
3334 u32 cfg = rtl8169_rx_config;
3335
3336 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3337 RTL_W32(RxConfig, cfg);
3338
3339 /* Set DMA burst size and Interframe Gap Time */
3340 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3341 (InterFrameGap << TxInterFrameGapShift));
3342}
3343
07ce4064 3344static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3345{
3346 struct rtl8169_private *tp = netdev_priv(dev);
3347 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3348 unsigned int i;
1da177e4
LT		 3349
3350 /* Soft reset the chip. */
3351 RTL_W8(ChipCmd, CmdReset);
3352
3353 /* Check that the chip has finished the reset. */
07d3f51f 3354 for (i = 0; i < 100; i++) {
1da177e4
LT		 3355 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3356 break;
b518fa8e 3357 msleep_interruptible(1);
1da177e4
LT		 3358 }
3359
07ce4064
FR		 3360 tp->hw_start(dev);
3361
07ce4064
FR		 3362 netif_start_queue(dev);
3363}
3364
3365
7f796d83
FR		 3366static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3367 void __iomem *ioaddr)
3368{
3369 /*
3370 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3371 * register to be written before TxDescAddrLow to work.
3372 * Switching from MMIO to I/O access fixes the issue as well.
3373 */
3374 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3375 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3376 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3377 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3378}
3379
3380static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3381{
3382 u16 cmd;
3383
3384 cmd = RTL_R16(CPlusCmd);
3385 RTL_W16(CPlusCmd, cmd);
3386 return cmd;
3387}
3388
fdd7b4c3 3389static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3390{
3391 /* Low hurts. Let's disable the filtering. */
207d6e87 3392 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3393}
3394
6dccd16b
FR		 3395static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3396{
350f7596 3397 static const struct {
6dccd16b
FR		 3398 u32 mac_version;
3399 u32 clk;
3400 u32 val;
3401 } cfg2_info [] = {
3402 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3403 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3404 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3405 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3406 }, *p = cfg2_info;
3407 unsigned int i;
3408 u32 clk;
3409
3410 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3411 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3412 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3413 RTL_W32(0x7c, p->val);
3414 break;
3415 }
3416 }
3417}
3418
07ce4064
FR		 3419static void rtl_hw_start_8169(struct net_device *dev)
3420{
3421 struct rtl8169_private *tp = netdev_priv(dev);
3422 void __iomem *ioaddr = tp->mmio_addr;
3423 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3424
9cb427b6
FR		 3425 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3426 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3427 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3428 }
3429
1da177e4 3430 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3431 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3432 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3433 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3434 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3435 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3436
f0298f81 3437 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3438
6f0333b8 3439 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3440
c946b304
FR		 3441 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3442 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3443 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3444 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3445 rtl_set_rx_tx_config_registers(tp);
1da177e4 3446
7f796d83 3447 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3448
bcf0bf90
FR		 3449 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3450 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3451 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3452 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3453 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3454 }
3455
bcf0bf90
FR		 3456 RTL_W16(CPlusCmd, tp->cp_cmd);
3457
6dccd16b
FR		 3458 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3459
1da177e4
LT		 3460 /*
3461 * Undocumented corner. Supposedly:
3462 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3463 */
3464 RTL_W16(IntrMitigate, 0x0000);
3465
7f796d83 3466 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3467
c946b304
FR		 3468 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3469 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3470 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3471 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3472 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3473 rtl_set_rx_tx_config_registers(tp);
3474 }
3475
1da177e4 3476 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3477
3478 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3479 RTL_R8(IntrMask);
1da177e4
LT		 3480
3481 RTL_W32(RxMissed, 0);
3482
07ce4064 3483 rtl_set_rx_mode(dev);
1da177e4
LT		 3484
3485 /* no early-rx interrupts */
3486 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3487
3488 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3489 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3490}
1da177e4 3491
9c14ceaf 3492static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3493{
9c14ceaf
FR		 3494 struct net_device *dev = pci_get_drvdata(pdev);
3495 struct rtl8169_private *tp = netdev_priv(dev);
3496 int cap = tp->pcie_cap;
3497
3498 if (cap) {
3499 u16 ctl;
458a9f61 3500
9c14ceaf
FR		 3501 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3502 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3503 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3504 }
458a9f61
FR		 3505}
3506
650e8d5d 3507static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3508{
3509 u32 csi;
3510
3511 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3512 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3513}
3514
e6de30d6 3515static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3516{
3517 rtl_csi_access_enable(ioaddr, 0x17000000);
3518}
3519
650e8d5d 3520static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3521{
3522 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3523}
3524
3525struct ephy_info {
3526 unsigned int offset;
3527 u16 mask;
3528 u16 bits;
3529};
3530
350f7596 3531static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3532{
3533 u16 w;
3534
3535 while (len-- > 0) {
3536 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3537 rtl_ephy_write(ioaddr, e->offset, w);
3538 e++;
3539 }
3540}
3541
b726e493
FR		 3542static void rtl_disable_clock_request(struct pci_dev *pdev)
3543{
3544 struct net_device *dev = pci_get_drvdata(pdev);
3545 struct rtl8169_private *tp = netdev_priv(dev);
3546 int cap = tp->pcie_cap;
3547
3548 if (cap) {
3549 u16 ctl;
3550
3551 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3552 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3553 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3554 }
3555}
3556
e6de30d6 3557static void rtl_enable_clock_request(struct pci_dev *pdev)
3558{
3559 struct net_device *dev = pci_get_drvdata(pdev);
3560 struct rtl8169_private *tp = netdev_priv(dev);
3561 int cap = tp->pcie_cap;
3562
3563 if (cap) {
3564 u16 ctl;
3565
3566 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3567 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3568 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3569 }
3570}
3571
b726e493
FR		 3572#define R8168_CPCMD_QUIRK_MASK (\
3573 EnableBist | \
3574 Mac_dbgo_oe | \
3575 Force_half_dup | \
3576 Force_rxflow_en | \
3577 Force_txflow_en | \
3578 Cxpl_dbg_sel | \
3579 ASF | \
3580 PktCntrDisable | \
3581 Mac_dbgo_sel)
3582
219a1e9d
FR		 3583static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3584{
b726e493
FR		 3585 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3586
3587 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3588
2e68ae44
FR		 3589 rtl_tx_performance_tweak(pdev,
3590 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3591}
3592
3593static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3594{
3595 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3596
f0298f81 3597 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3598
3599 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3600}
3601
3602static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3603{
b726e493
FR		 3604 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3605
3606 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3607
219a1e9d 3608 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3609
3610 rtl_disable_clock_request(pdev);
3611
3612 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3613}
3614
ef3386f0 3615static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3616{
350f7596 3617 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3618 { 0x01, 0, 0x0001 },
3619 { 0x02, 0x0800, 0x1000 },
3620 { 0x03, 0, 0x0042 },
3621 { 0x06, 0x0080, 0x0000 },
3622 { 0x07, 0, 0x2000 }
3623 };
3624
650e8d5d 3625 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3626
3627 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3628
219a1e9d
FR		 3629 __rtl_hw_start_8168cp(ioaddr, pdev);
3630}
3631
ef3386f0
FR		 3632static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3633{
650e8d5d 3634 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3635
3636 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3637
3638 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3639
3640 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3641}
3642
7f3e3d3a
FR		 3643static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3644{
650e8d5d 3645 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3646
3647 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3648
3649 /* Magic. */
3650 RTL_W8(DBG_REG, 0x20);
3651
f0298f81 3652 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3653
3654 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3655
3656 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3657}
3658
219a1e9d
FR		 3659static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3660{
350f7596 3661 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3662 { 0x02, 0x0800, 0x1000 },
3663 { 0x03, 0, 0x0002 },
3664 { 0x06, 0x0080, 0x0000 }
3665 };
3666
650e8d5d 3667 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3668
3669 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3670
3671 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3672
219a1e9d
FR		 3673 __rtl_hw_start_8168cp(ioaddr, pdev);
3674}
3675
3676static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3677{
350f7596 3678 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3679 { 0x01, 0, 0x0001 },
3680 { 0x03, 0x0400, 0x0220 }
3681 };
3682
650e8d5d 3683 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3684
3685 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3686
219a1e9d
FR		 3687 __rtl_hw_start_8168cp(ioaddr, pdev);
3688}
3689
197ff761
FR		 3690static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3691{
3692 rtl_hw_start_8168c_2(ioaddr, pdev);
3693}
3694
6fb07058
FR		 3695static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3696{
650e8d5d 3697 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3698
3699 __rtl_hw_start_8168cp(ioaddr, pdev);
3700}
3701
5b538df9
FR		 3702static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3703{
650e8d5d 3704 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3705
3706 rtl_disable_clock_request(pdev);
3707
f0298f81 3708 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3709
3710 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3711
3712 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3713}
3714
e6de30d6 3715static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3716{
3717 static const struct ephy_info e_info_8168d_4[] = {
3718 { 0x0b, ~0, 0x48 },
3719 { 0x19, 0x20, 0x50 },
3720 { 0x0c, ~0, 0x20 }
3721 };
3722 int i;
3723
3724 rtl_csi_access_enable_1(ioaddr);
3725
3726 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3727
3728 RTL_W8(MaxTxPacketSize, TxPacketMax);
3729
3730 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3731 const struct ephy_info *e = e_info_8168d_4 + i;
3732 u16 w;
3733
3734 w = rtl_ephy_read(ioaddr, e->offset);
3735 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3736 }
3737
3738 rtl_enable_clock_request(pdev);
3739}
3740
07ce4064
FR		 3741static void rtl_hw_start_8168(struct net_device *dev)
3742{
2dd99530
FR		 3743 struct rtl8169_private *tp = netdev_priv(dev);
3744 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3745 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3746
3747 RTL_W8(Cfg9346, Cfg9346_Unlock);
3748
f0298f81 3749 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3750
6f0333b8 3751 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3752
0e485150 3753 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3754
3755 RTL_W16(CPlusCmd, tp->cp_cmd);
3756
0e485150 3757 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3758
0e485150
FR		 3759 /* Work around for RxFIFO overflow. */
3760 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3761 tp->intr_event |= RxFIFOOver | PCSTimeout;
3762 tp->intr_event &= ~RxOverflow;
3763 }
3764
3765 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3766
b8363901
FR		 3767 rtl_set_rx_mode(dev);
3768
3769 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3770 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3771
3772 RTL_R8(IntrMask);
3773
219a1e9d
FR		 3774 switch (tp->mac_version) {
3775 case RTL_GIGA_MAC_VER_11:
3776 rtl_hw_start_8168bb(ioaddr, pdev);
3777 break;
3778
3779 case RTL_GIGA_MAC_VER_12:
3780 case RTL_GIGA_MAC_VER_17:
3781 rtl_hw_start_8168bef(ioaddr, pdev);
3782 break;
3783
3784 case RTL_GIGA_MAC_VER_18:
ef3386f0 3785 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3786 break;
3787
3788 case RTL_GIGA_MAC_VER_19:
3789 rtl_hw_start_8168c_1(ioaddr, pdev);
3790 break;
3791
3792 case RTL_GIGA_MAC_VER_20:
3793 rtl_hw_start_8168c_2(ioaddr, pdev);
3794 break;
3795
197ff761
FR		 3796 case RTL_GIGA_MAC_VER_21:
3797 rtl_hw_start_8168c_3(ioaddr, pdev);
3798 break;
3799
6fb07058
FR		 3800 case RTL_GIGA_MAC_VER_22:
3801 rtl_hw_start_8168c_4(ioaddr, pdev);
3802 break;
3803
ef3386f0
FR		 3804 case RTL_GIGA_MAC_VER_23:
3805 rtl_hw_start_8168cp_2(ioaddr, pdev);
3806 break;
3807
7f3e3d3a
FR		 3808 case RTL_GIGA_MAC_VER_24:
3809 rtl_hw_start_8168cp_3(ioaddr, pdev);
3810 break;
3811
5b538df9 3812 case RTL_GIGA_MAC_VER_25:
daf9df6d 3813 case RTL_GIGA_MAC_VER_26:
3814 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3815 rtl_hw_start_8168d(ioaddr, pdev);
3816 break;
3817
e6de30d6 3818 case RTL_GIGA_MAC_VER_28:
3819 rtl_hw_start_8168d_4(ioaddr, pdev);
3820 break;
3821
219a1e9d
FR		 3822 default:
3823 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3824 dev->name, tp->mac_version);
3825 break;
3826 }
2dd99530 3827
0e485150
FR		 3828 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3829
b8363901
FR		 3830 RTL_W8(Cfg9346, Cfg9346_Lock);
3831
2dd99530 3832 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3833
0e485150 3834 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3835}
1da177e4 3836
2857ffb7
FR		 3837#define R810X_CPCMD_QUIRK_MASK (\
3838 EnableBist | \
3839 Mac_dbgo_oe | \
3840 Force_half_dup | \
5edcc537 3841 Force_rxflow_en | \
2857ffb7
FR		 3842 Force_txflow_en | \
3843 Cxpl_dbg_sel | \
3844 ASF | \
3845 PktCntrDisable | \
3846 PCIDAC | \
3847 PCIMulRW)
3848
3849static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3850{
350f7596 3851 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3852 { 0x01, 0, 0x6e65 },
3853 { 0x02, 0, 0x091f },
3854 { 0x03, 0, 0xc2f9 },
3855 { 0x06, 0, 0xafb5 },
3856 { 0x07, 0, 0x0e00 },
3857 { 0x19, 0, 0xec80 },
3858 { 0x01, 0, 0x2e65 },
3859 { 0x01, 0, 0x6e65 }
3860 };
3861 u8 cfg1;
3862
650e8d5d 3863 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3864
3865 RTL_W8(DBG_REG, FIX_NAK_1);
3866
3867 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3868
3869 RTL_W8(Config1,
3870 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3871 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3872
3873 cfg1 = RTL_R8(Config1);
3874 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3875 RTL_W8(Config1, cfg1 & ~LEDS0);
3876
3877 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3878
3879 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3880}
3881
3882static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3883{
650e8d5d 3884 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3885
3886 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3887
3888 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3889 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3890
3891 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3892}
3893
3894static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3895{
3896 rtl_hw_start_8102e_2(ioaddr, pdev);
3897
3898 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3899}
3900
07ce4064
FR		 3901static void rtl_hw_start_8101(struct net_device *dev)
3902{
cdf1a608
FR		 3903 struct rtl8169_private *tp = netdev_priv(dev);
3904 void __iomem *ioaddr = tp->mmio_addr;
3905 struct pci_dev *pdev = tp->pci_dev;
3906
e3cf0cc0
FR		 3907 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3908 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3909 int cap = tp->pcie_cap;
3910
3911 if (cap) {
3912 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3913 PCI_EXP_DEVCTL_NOSNOOP_EN);
3914 }
cdf1a608
FR		 3915 }
3916
2857ffb7
FR		 3917 switch (tp->mac_version) {
3918 case RTL_GIGA_MAC_VER_07:
3919 rtl_hw_start_8102e_1(ioaddr, pdev);
3920 break;
3921
3922 case RTL_GIGA_MAC_VER_08:
3923 rtl_hw_start_8102e_3(ioaddr, pdev);
3924 break;
3925
3926 case RTL_GIGA_MAC_VER_09:
3927 rtl_hw_start_8102e_2(ioaddr, pdev);
3928 break;
cdf1a608
FR		 3929 }
3930
3931 RTL_W8(Cfg9346, Cfg9346_Unlock);
3932
f0298f81 3933 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 3934
6f0333b8 3935 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3936
3937 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3938
3939 RTL_W16(CPlusCmd, tp->cp_cmd);
3940
3941 RTL_W16(IntrMitigate, 0x0000);
3942
3943 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3944
3945 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3946 rtl_set_rx_tx_config_registers(tp);
3947
3948 RTL_W8(Cfg9346, Cfg9346_Lock);
3949
3950 RTL_R8(IntrMask);
3951
cdf1a608
FR		 3952 rtl_set_rx_mode(dev);
3953
0e485150
FR		 3954 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3955
cdf1a608 3956 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3957
0e485150 3958 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3959}
3960
3961static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3962{
1da177e4
LT		 3963 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3964 return -EINVAL;
3965
3966 dev->mtu = new_mtu;
323bb685 3967 return 0;
1da177e4
LT		 3968}
3969
3970static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3971{
95e0918d 3972 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3973 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3974}
3975
6f0333b8
ED		 3976static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3977 void **data_buff, struct RxDesc *desc)
1da177e4 3978{
48addcc9 3979 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3980 DMA_FROM_DEVICE);
48addcc9 3981
6f0333b8
ED		 3982 kfree(*data_buff);
3983 *data_buff = NULL;
1da177e4
LT		 3984 rtl8169_make_unusable_by_asic(desc);
3985}
3986
3987static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3988{
3989 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3990
3991 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3992}
3993
3994static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3995 u32 rx_buf_sz)
3996{
3997 desc->addr = cpu_to_le64(mapping);
3998 wmb();
3999 rtl8169_mark_to_asic(desc, rx_buf_sz);
4000}
4001
6f0333b8
ED		 4002static inline void *rtl8169_align(void *data)
4003{
4004 return (void *)ALIGN((long)data, 16);
4005}
4006
0ecbe1ca
SG		 4007static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4008 struct RxDesc *desc)
1da177e4 4009{
6f0333b8 4010 void *data;
1da177e4 4011 dma_addr_t mapping;
48addcc9 4012 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4013 struct net_device *dev = tp->dev;
6f0333b8 4014 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4015
6f0333b8
ED		 4016 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4017 if (!data)
4018 return NULL;
e9f63f30 4019
6f0333b8
ED		 4020 if (rtl8169_align(data) != data) {
4021 kfree(data);
4022 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4023 if (!data)
4024 return NULL;
4025 }
3eafe507 4026
48addcc9 4027 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4028 DMA_FROM_DEVICE);
d827d86b
SG		 4029 if (unlikely(dma_mapping_error(d, mapping))) {
4030 if (net_ratelimit())
4031 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4032 goto err_out;
d827d86b 4033 }
1da177e4
LT		 4034
4035 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4036 return data;
3eafe507
SG		 4037
4038err_out:
4039 kfree(data);
4040 return NULL;
1da177e4
LT		 4041}
4042
4043static void rtl8169_rx_clear(struct rtl8169_private *tp)
4044{
07d3f51f 4045 unsigned int i;
1da177e4
LT		 4046
4047 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4048 if (tp->Rx_databuff[i]) {
4049 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4050 tp->RxDescArray + i);
4051 }
4052 }
4053}
4054
0ecbe1ca 4055static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4056{
0ecbe1ca
SG		 4057 desc->opts1 |= cpu_to_le32(RingEnd);
4058}
5b0384f4 4059
0ecbe1ca
SG		 4060static int rtl8169_rx_fill(struct rtl8169_private *tp)
4061{
4062 unsigned int i;
1da177e4 4063
0ecbe1ca
SG		 4064 for (i = 0; i < NUM_RX_DESC; i++) {
4065 void *data;
4ae47c2d 4066
6f0333b8 4067 if (tp->Rx_databuff[i])
1da177e4 4068 continue;
bcf0bf90 4069
0ecbe1ca 4070 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4071 if (!data) {
4072 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4073 goto err_out;
6f0333b8
ED		 4074 }
4075 tp->Rx_databuff[i] = data;
1da177e4 4076 }
1da177e4 4077
0ecbe1ca
SG		 4078 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4079 return 0;
4080
4081err_out:
4082 rtl8169_rx_clear(tp);
4083 return -ENOMEM;
1da177e4
LT		 4084}
4085
4086static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4087{
4088 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4089}
4090
4091static int rtl8169_init_ring(struct net_device *dev)
4092{
4093 struct rtl8169_private *tp = netdev_priv(dev);
4094
4095 rtl8169_init_ring_indexes(tp);
4096
4097 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4098 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4099
0ecbe1ca 4100 return rtl8169_rx_fill(tp);
1da177e4
LT		 4101}
4102
48addcc9 4103static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4104 struct TxDesc *desc)
4105{
4106 unsigned int len = tx_skb->len;
4107
48addcc9
SG		 4108 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4109
1da177e4
LT		 4110 desc->opts1 = 0x00;
4111 desc->opts2 = 0x00;
4112 desc->addr = 0x00;
4113 tx_skb->len = 0;
4114}
4115
3eafe507
SG		 4116static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4117 unsigned int n)
1da177e4
LT		 4118{
4119 unsigned int i;
4120
3eafe507
SG		 4121 for (i = 0; i < n; i++) {
4122 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4123 struct ring_info *tx_skb = tp->tx_skb + entry;
4124 unsigned int len = tx_skb->len;
4125
4126 if (len) {
4127 struct sk_buff *skb = tx_skb->skb;
4128
48addcc9 4129 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4130 tp->TxDescArray + entry);
4131 if (skb) {
cac4b22f 4132 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4133 dev_kfree_skb(skb);
4134 tx_skb->skb = NULL;
4135 }
1da177e4
LT		 4136 }
4137 }
3eafe507
SG		 4138}
4139
4140static void rtl8169_tx_clear(struct rtl8169_private *tp)
4141{
4142 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4143 tp->cur_tx = tp->dirty_tx = 0;
4144}
4145
c4028958 4146static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4147{
4148 struct rtl8169_private *tp = netdev_priv(dev);
4149
c4028958 4150 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4151 schedule_delayed_work(&tp->task, 4);
4152}
4153
4154static void rtl8169_wait_for_quiescence(struct net_device *dev)
4155{
4156 struct rtl8169_private *tp = netdev_priv(dev);
4157 void __iomem *ioaddr = tp->mmio_addr;
4158
4159 synchronize_irq(dev->irq);
4160
4161 /* Wait for any pending NAPI task to complete */
bea3348e 4162 napi_disable(&tp->napi);
1da177e4
LT		 4163
4164 rtl8169_irq_mask_and_ack(ioaddr);
4165
d1d08d12
DM		 4166 tp->intr_mask = 0xffff;
4167 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4168 napi_enable(&tp->napi);
1da177e4
LT		 4169}
4170
c4028958 4171static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4172{
c4028958
DH		 4173 struct rtl8169_private *tp =
4174 container_of(work, struct rtl8169_private, task.work);
4175 struct net_device *dev = tp->dev;
1da177e4
LT		 4176 int ret;
4177
eb2a021c
FR		 4178 rtnl_lock();
4179
4180 if (!netif_running(dev))
4181 goto out_unlock;
4182
4183 rtl8169_wait_for_quiescence(dev);
4184 rtl8169_close(dev);
1da177e4
LT		 4185
4186 ret = rtl8169_open(dev);
4187 if (unlikely(ret < 0)) {
bf82c189
JP		 4188 if (net_ratelimit())
4189 netif_err(tp, drv, dev,
4190 "reinit failure (status = %d). Rescheduling\n",
4191 ret);
1da177e4
LT		 4192 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4193 }
eb2a021c
FR		 4194
4195out_unlock:
4196 rtnl_unlock();
1da177e4
LT		 4197}
4198
c4028958 4199static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4200{
c4028958
DH		 4201 struct rtl8169_private *tp =
4202 container_of(work, struct rtl8169_private, task.work);
4203 struct net_device *dev = tp->dev;
1da177e4 4204
eb2a021c
FR		 4205 rtnl_lock();
4206
1da177e4 4207 if (!netif_running(dev))
eb2a021c 4208 goto out_unlock;
1da177e4
LT		 4209
4210 rtl8169_wait_for_quiescence(dev);
4211
bea3348e 4212 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4213 rtl8169_tx_clear(tp);
4214
4215 if (tp->dirty_rx == tp->cur_rx) {
4216 rtl8169_init_ring_indexes(tp);
07ce4064 4217 rtl_hw_start(dev);
1da177e4 4218 netif_wake_queue(dev);
cebf8cc7 4219 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4220 } else {
bf82c189
JP		 4221 if (net_ratelimit())
4222 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4223 rtl8169_schedule_work(dev, rtl8169_reset_task);
4224 }
eb2a021c
FR		 4225
4226out_unlock:
4227 rtnl_unlock();
1da177e4
LT		 4228}
4229
4230static void rtl8169_tx_timeout(struct net_device *dev)
4231{
4232 struct rtl8169_private *tp = netdev_priv(dev);
4233
e6de30d6 4234 rtl8169_hw_reset(tp);
1da177e4
LT		 4235
4236 /* Let's wait a bit while any (async) irq lands on */
4237 rtl8169_schedule_work(dev, rtl8169_reset_task);
4238}
4239
4240static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4241 u32 opts1)
4242{
4243 struct skb_shared_info *info = skb_shinfo(skb);
4244 unsigned int cur_frag, entry;
a6343afb 4245 struct TxDesc * uninitialized_var(txd);
48addcc9 4246 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4247
4248 entry = tp->cur_tx;
4249 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4250 skb_frag_t *frag = info->frags + cur_frag;
4251 dma_addr_t mapping;
4252 u32 status, len;
4253 void *addr;
4254
4255 entry = (entry + 1) % NUM_TX_DESC;
4256
4257 txd = tp->TxDescArray + entry;
4258 len = frag->size;
4259 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4260 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4261 if (unlikely(dma_mapping_error(d, mapping))) {
4262 if (net_ratelimit())
4263 netif_err(tp, drv, tp->dev,
4264 "Failed to map TX fragments DMA!\n");
3eafe507 4265 goto err_out;
d827d86b 4266 }
1da177e4
LT		 4267
4268 /* anti gcc 2.95.3 bugware (sic) */
4269 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4270
4271 txd->opts1 = cpu_to_le32(status);
4272 txd->addr = cpu_to_le64(mapping);
4273
4274 tp->tx_skb[entry].len = len;
4275 }
4276
4277 if (cur_frag) {
4278 tp->tx_skb[entry].skb = skb;
4279 txd->opts1 |= cpu_to_le32(LastFrag);
4280 }
4281
4282 return cur_frag;
3eafe507
SG		 4283
4284err_out:
4285 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4286 return -EIO;
1da177e4
LT		 4287}
4288
4289static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4290{
4291 if (dev->features & NETIF_F_TSO) {
7967168c 4292 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4293
4294 if (mss)
4295 return LargeSend | ((mss & MSSMask) << MSSShift);
4296 }
84fa7933 4297 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4298 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4299
4300 if (ip->protocol == IPPROTO_TCP)
4301 return IPCS | TCPCS;
4302 else if (ip->protocol == IPPROTO_UDP)
4303 return IPCS | UDPCS;
4304 WARN_ON(1); /* we need a WARN() */
4305 }
4306 return 0;
4307}
4308
61357325
SH		 4309static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4310 struct net_device *dev)
1da177e4
LT		 4311{
4312 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4313 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4314 struct TxDesc *txd = tp->TxDescArray + entry;
4315 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4316 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4317 dma_addr_t mapping;
4318 u32 status, len;
4319 u32 opts1;
3eafe507 4320 int frags;
5b0384f4 4321
1da177e4 4322 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4323 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4324 goto err_stop_0;
1da177e4
LT		 4325 }
4326
4327 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4328 goto err_stop_0;
4329
4330 len = skb_headlen(skb);
48addcc9 4331 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4332 if (unlikely(dma_mapping_error(d, mapping))) {
4333 if (net_ratelimit())
4334 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4335 goto err_dma_0;
d827d86b 4336 }
3eafe507
SG		 4337
4338 tp->tx_skb[entry].len = len;
4339 txd->addr = cpu_to_le64(mapping);
4340 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4341
4342 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4343
4344 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4345 if (frags < 0)
4346 goto err_dma_1;
4347 else if (frags)
1da177e4 4348 opts1 |= FirstFrag;
3eafe507 4349 else {
1da177e4
LT		 4350 opts1 |= FirstFrag | LastFrag;
4351 tp->tx_skb[entry].skb = skb;
4352 }
4353
1da177e4
LT		 4354 wmb();
4355
4356 /* anti gcc 2.95.3 bugware (sic) */
4357 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4358 txd->opts1 = cpu_to_le32(status);
4359
1da177e4
LT		 4360 tp->cur_tx += frags + 1;
4361
4c020a96 4362 wmb();
1da177e4 4363
275391a4 4364 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4365
4366 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4367 netif_stop_queue(dev);
4368 smp_rmb();
4369 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4370 netif_wake_queue(dev);
4371 }
4372
61357325 4373 return NETDEV_TX_OK;
1da177e4 4374
3eafe507 4375err_dma_1:
48addcc9 4376 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4377err_dma_0:
4378 dev_kfree_skb(skb);
4379 dev->stats.tx_dropped++;
4380 return NETDEV_TX_OK;
4381
4382err_stop_0:
1da177e4 4383 netif_stop_queue(dev);
cebf8cc7 4384 dev->stats.tx_dropped++;
61357325 4385 return NETDEV_TX_BUSY;
1da177e4
LT		 4386}
4387
4388static void rtl8169_pcierr_interrupt(struct net_device *dev)
4389{
4390 struct rtl8169_private *tp = netdev_priv(dev);
4391 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4392 u16 pci_status, pci_cmd;
4393
4394 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4395 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4396
bf82c189
JP		 4397 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4398 pci_cmd, pci_status);
1da177e4
LT		 4399
4400 /*
4401 * The recovery sequence below admits a very elaborated explanation:
4402 * - it seems to work;
d03902b8
FR		 4403 * - I did not see what else could be done;
4404 * - it makes iop3xx happy.
1da177e4
LT		 4405 *
4406 * Feel free to adjust to your needs.
4407 */
a27993f3 4408 if (pdev->broken_parity_status)
d03902b8
FR		 4409 pci_cmd &= ~PCI_COMMAND_PARITY;
4410 else
4411 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4412
4413 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4414
4415 pci_write_config_word(pdev, PCI_STATUS,
4416 pci_status & (PCI_STATUS_DETECTED_PARITY |
4417 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4418 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4419
4420 /* The infamous DAC f*ckup only happens at boot time */
4421 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4422 void __iomem *ioaddr = tp->mmio_addr;
4423
bf82c189 4424 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4425 tp->cp_cmd &= ~PCIDAC;
4426 RTL_W16(CPlusCmd, tp->cp_cmd);
4427 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4428 }
4429
e6de30d6 4430 rtl8169_hw_reset(tp);
d03902b8
FR		 4431
4432 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4433}
4434
07d3f51f
FR		 4435static void rtl8169_tx_interrupt(struct net_device *dev,
4436 struct rtl8169_private *tp,
4437 void __iomem *ioaddr)
1da177e4
LT		 4438{
4439 unsigned int dirty_tx, tx_left;
4440
1da177e4
LT		 4441 dirty_tx = tp->dirty_tx;
4442 smp_rmb();
4443 tx_left = tp->cur_tx - dirty_tx;
4444
4445 while (tx_left > 0) {
4446 unsigned int entry = dirty_tx % NUM_TX_DESC;
4447 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4448 u32 status;
4449
4450 rmb();
4451 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4452 if (status & DescOwn)
4453 break;
4454
48addcc9
SG		 4455 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4456 tp->TxDescArray + entry);
1da177e4 4457 if (status & LastFrag) {
cac4b22f
SG		 4458 dev->stats.tx_packets++;
4459 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4460 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4461 tx_skb->skb = NULL;
4462 }
4463 dirty_tx++;
4464 tx_left--;
4465 }
4466
4467 if (tp->dirty_tx != dirty_tx) {
4468 tp->dirty_tx = dirty_tx;
4469 smp_wmb();
4470 if (netif_queue_stopped(dev) &&
4471 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4472 netif_wake_queue(dev);
4473 }
d78ae2dc
FR		 4474 /*
4475 * 8168 hack: TxPoll requests are lost when the Tx packets are
4476 * too close. Let's kick an extra TxPoll request when a burst
4477 * of start_xmit activity is detected (if it is not detected,
4478 * it is slow enough). -- FR
4479 */
4480 smp_rmb();
4481 if (tp->cur_tx != dirty_tx)
4482 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4483 }
4484}
4485
126fa4b9
FR		 4486static inline int rtl8169_fragmented_frame(u32 status)
4487{
4488 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4489}
4490
adea1ac7 4491static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4492{
1da177e4
LT		 4493 u32 status = opts1 & RxProtoMask;
4494
4495 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4496 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4497 skb->ip_summed = CHECKSUM_UNNECESSARY;
4498 else
bc8acf2c 4499 skb_checksum_none_assert(skb);
1da177e4
LT		 4500}
4501
6f0333b8
ED		 4502static struct sk_buff *rtl8169_try_rx_copy(void *data,
4503 struct rtl8169_private *tp,
4504 int pkt_size,
4505 dma_addr_t addr)
1da177e4 4506{
b449655f 4507 struct sk_buff *skb;
48addcc9 4508 struct device *d = &tp->pci_dev->dev;
b449655f 4509
6f0333b8 4510 data = rtl8169_align(data);
48addcc9 4511 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4512 prefetch(data);
4513 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4514 if (skb)
4515 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4516 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4517
6f0333b8 4518 return skb;
1da177e4
LT		 4519}
4520
630b943c
ED		 4521/*
4522 * Warning : rtl8169_rx_interrupt() might be called :
4523 * 1) from NAPI (softirq) context
4524 * (polling = 1 : we should call netif_receive_skb())
4525 * 2) from process context (rtl8169_reset_task())
4526 * (polling = 0 : we must call netif_rx() instead)
4527 */
07d3f51f
FR		 4528static int rtl8169_rx_interrupt(struct net_device *dev,
4529 struct rtl8169_private *tp,
bea3348e 4530 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4531{
4532 unsigned int cur_rx, rx_left;
6f0333b8 4533 unsigned int count;
630b943c 4534 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4535
1da177e4
LT		 4536 cur_rx = tp->cur_rx;
4537 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4538 rx_left = min(rx_left, budget);
1da177e4 4539
4dcb7d33 4540 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4541 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4542 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4543 u32 status;
4544
4545 rmb();
126fa4b9 4546 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4547
4548 if (status & DescOwn)
4549 break;
4dcb7d33 4550 if (unlikely(status & RxRES)) {
bf82c189
JP		 4551 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4552 status);
cebf8cc7 4553 dev->stats.rx_errors++;
1da177e4 4554 if (status & (RxRWT | RxRUNT))
cebf8cc7 4555 dev->stats.rx_length_errors++;
1da177e4 4556 if (status & RxCRC)
cebf8cc7 4557 dev->stats.rx_crc_errors++;
9dccf611
FR		 4558 if (status & RxFOVF) {
4559 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4560 dev->stats.rx_fifo_errors++;
9dccf611 4561 }
6f0333b8 4562 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4563 } else {
6f0333b8 4564 struct sk_buff *skb;
b449655f 4565 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4566 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4567
126fa4b9
FR		 4568 /*
4569 * The driver does not support incoming fragmented
4570 * frames. They are seen as a symptom of over-mtu
4571 * sized frames.
4572 */
4573 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4574 dev->stats.rx_dropped++;
4575 dev->stats.rx_length_errors++;
6f0333b8 4576 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4577 continue;
126fa4b9
FR		 4578 }
4579
6f0333b8
ED		 4580 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4581 tp, pkt_size, addr);
4582 rtl8169_mark_to_asic(desc, rx_buf_sz);
4583 if (!skb) {
4584 dev->stats.rx_dropped++;
4585 continue;
1da177e4
LT		 4586 }
4587
adea1ac7 4588 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4589 skb_put(skb, pkt_size);
4590 skb->protocol = eth_type_trans(skb, dev);
4591
630b943c
ED		 4592 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4593 if (likely(polling))
2edae08e 4594 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4595 else
4596 netif_rx(skb);
4597 }
1da177e4 4598
cebf8cc7
FR		 4599 dev->stats.rx_bytes += pkt_size;
4600 dev->stats.rx_packets++;
1da177e4 4601 }
6dccd16b
FR		 4602
4603 /* Work around for AMD plateform. */
95e0918d 4604 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4605 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4606 desc->opts2 = 0;
4607 cur_rx++;
4608 }
1da177e4
LT		 4609 }
4610
4611 count = cur_rx - tp->cur_rx;
4612 tp->cur_rx = cur_rx;
4613
6f0333b8 4614 tp->dirty_rx += count;
1da177e4
LT		 4615
4616 return count;
4617}
4618
07d3f51f 4619static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4620{
07d3f51f 4621 struct net_device *dev = dev_instance;
1da177e4 4622 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4623 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4624 int handled = 0;
865c652d 4625 int status;
1da177e4 4626
f11a377b
DD		 4627 /* loop handling interrupts until we have no new ones or
4628 * we hit a invalid/hotplug case.
4629 */
865c652d 4630 status = RTL_R16(IntrStatus);
f11a377b
DD		 4631 while (status && status != 0xffff) {
4632 handled = 1;
1da177e4 4633
f11a377b
DD		 4634 /* Handle all of the error cases first. These will reset
4635 * the chip, so just exit the loop.
4636 */
4637 if (unlikely(!netif_running(dev))) {
4638 rtl8169_asic_down(ioaddr);
4639 break;
4640 }
1da177e4 4641
f11a377b 4642 /* Work around for rx fifo overflow */
53f57357 4643 if (unlikely(status & RxFIFOOver) &&
4644 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
f11a377b
DD		 4645 netif_stop_queue(dev);
4646 rtl8169_tx_timeout(dev);
4647 break;
4648 }
1da177e4 4649
f11a377b
DD		 4650 if (unlikely(status & SYSErr)) {
4651 rtl8169_pcierr_interrupt(dev);
4652 break;
4653 }
1da177e4 4654
f11a377b 4655 if (status & LinkChg)
e4fbce74 4656 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4657
f11a377b
DD		 4658 /* We need to see the lastest version of tp->intr_mask to
4659 * avoid ignoring an MSI interrupt and having to wait for
4660 * another event which may never come.
4661 */
4662 smp_rmb();
4663 if (status & tp->intr_mask & tp->napi_event) {
4664 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4665 tp->intr_mask = ~tp->napi_event;
4666
4667 if (likely(napi_schedule_prep(&tp->napi)))
4668 __napi_schedule(&tp->napi);
bf82c189
JP		 4669 else
4670 netif_info(tp, intr, dev,
4671 "interrupt %04x in poll\n", status);
f11a377b 4672 }
1da177e4 4673
f11a377b
DD		 4674 /* We only get a new MSI interrupt when all active irq
4675 * sources on the chip have been acknowledged. So, ack
4676 * everything we've seen and check if new sources have become
4677 * active to avoid blocking all interrupts from the chip.
4678 */
4679 RTL_W16(IntrStatus,
4680 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4681 status = RTL_R16(IntrStatus);
865c652d 4682 }
1da177e4 4683
1da177e4
LT		 4684 return IRQ_RETVAL(handled);
4685}
4686
bea3348e 4687static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4688{
bea3348e
SH		 4689 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4690 struct net_device *dev = tp->dev;
1da177e4 4691 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4692 int work_done;
1da177e4 4693
bea3348e 4694 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4695 rtl8169_tx_interrupt(dev, tp, ioaddr);
4696
bea3348e 4697 if (work_done < budget) {
288379f0 4698 napi_complete(napi);
f11a377b
DD		 4699
4700 /* We need for force the visibility of tp->intr_mask
4701 * for other CPUs, as we can loose an MSI interrupt
4702 * and potentially wait for a retransmit timeout if we don't.
4703 * The posted write to IntrMask is safe, as it will
4704 * eventually make it to the chip and we won't loose anything
4705 * until it does.
1da177e4 4706 */
f11a377b 4707 tp->intr_mask = 0xffff;
4c020a96 4708 wmb();
0e485150 4709 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4710 }
4711
bea3348e 4712 return work_done;
1da177e4 4713}
1da177e4 4714
523a6094
FR		 4715static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4716{
4717 struct rtl8169_private *tp = netdev_priv(dev);
4718
4719 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4720 return;
4721
4722 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4723 RTL_W32(RxMissed, 0);
4724}
4725
1da177e4
LT		 4726static void rtl8169_down(struct net_device *dev)
4727{
4728 struct rtl8169_private *tp = netdev_priv(dev);
4729 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4730
4731 rtl8169_delete_timer(dev);
4732
4733 netif_stop_queue(dev);
4734
93dd79e8 4735 napi_disable(&tp->napi);
93dd79e8 4736
1da177e4
LT		 4737 spin_lock_irq(&tp->lock);
4738
4739 rtl8169_asic_down(ioaddr);
323bb685
SG		 4740 /*
4741 * At this point device interrupts can not be enabled in any function,
4742 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4743 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4744 */
523a6094 4745 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4746
4747 spin_unlock_irq(&tp->lock);
4748
4749 synchronize_irq(dev->irq);
4750
1da177e4 4751 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4752 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4753
1da177e4
LT		 4754 rtl8169_tx_clear(tp);
4755
4756 rtl8169_rx_clear(tp);
065c27c1 4757
4758 rtl_pll_power_down(tp);
1da177e4
LT		 4759}
4760
4761static int rtl8169_close(struct net_device *dev)
4762{
4763 struct rtl8169_private *tp = netdev_priv(dev);
4764 struct pci_dev *pdev = tp->pci_dev;
4765
e1759441
RW		 4766 pm_runtime_get_sync(&pdev->dev);
4767
355423d0
IV		 4768 /* update counters before going down */
4769 rtl8169_update_counters(dev);
4770
1da177e4
LT		 4771 rtl8169_down(dev);
4772
4773 free_irq(dev->irq, dev);
4774
82553bb6
SG		 4775 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4776 tp->RxPhyAddr);
4777 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4778 tp->TxPhyAddr);
1da177e4
LT		 4779 tp->TxDescArray = NULL;
4780 tp->RxDescArray = NULL;
4781
e1759441
RW		 4782 pm_runtime_put_sync(&pdev->dev);
4783
1da177e4
LT		 4784 return 0;
4785}
4786
07ce4064 4787static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4788{
4789 struct rtl8169_private *tp = netdev_priv(dev);
4790 void __iomem *ioaddr = tp->mmio_addr;
4791 unsigned long flags;
4792 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4793 int rx_mode;
1da177e4
LT		 4794 u32 tmp = 0;
4795
4796 if (dev->flags & IFF_PROMISC) {
4797 /* Unconditionally log net taps. */
bf82c189 4798 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4799 rx_mode =
4800 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4801 AcceptAllPhys;
4802 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4803 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4804 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4805 /* Too many to filter perfectly -- accept all multicasts. */
4806 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4807 mc_filter[1] = mc_filter[0] = 0xffffffff;
4808 } else {
22bedad3 4809 struct netdev_hw_addr *ha;
07d3f51f 4810
1da177e4
LT		 4811 rx_mode = AcceptBroadcast | AcceptMyPhys;
4812 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4813 netdev_for_each_mc_addr(ha, dev) {
4814 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4815 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4816 rx_mode |= AcceptMulticast;
4817 }
4818 }
4819
4820 spin_lock_irqsave(&tp->lock, flags);
4821
4822 tmp = rtl8169_rx_config | rx_mode |
4823 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4824
f887cce8 4825 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4826 u32 data = mc_filter[0];
4827
4828 mc_filter[0] = swab32(mc_filter[1]);
4829 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4830 }
4831
1da177e4 4832 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4833 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4834
57a9f236
FR		 4835 RTL_W32(RxConfig, tmp);
4836
1da177e4
LT		 4837 spin_unlock_irqrestore(&tp->lock, flags);
4838}
4839
4840/**
4841 * rtl8169_get_stats - Get rtl8169 read/write statistics
4842 * @dev: The Ethernet Device to get statistics for
4843 *
4844 * Get TX/RX statistics for rtl8169
4845 */
4846static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4847{
4848 struct rtl8169_private *tp = netdev_priv(dev);
4849 void __iomem *ioaddr = tp->mmio_addr;
4850 unsigned long flags;
4851
4852 if (netif_running(dev)) {
4853 spin_lock_irqsave(&tp->lock, flags);
523a6094 4854 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4855 spin_unlock_irqrestore(&tp->lock, flags);
4856 }
5b0384f4 4857
cebf8cc7 4858 return &dev->stats;
1da177e4
LT		 4859}
4860
861ab440 4861static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4862{
065c27c1 4863 struct rtl8169_private *tp = netdev_priv(dev);
4864
5d06a99f 4865 if (!netif_running(dev))
861ab440 4866 return;
5d06a99f 4867
065c27c1 4868 rtl_pll_power_down(tp);
4869
5d06a99f
FR		 4870 netif_device_detach(dev);
4871 netif_stop_queue(dev);
861ab440
RW		 4872}
4873
4874#ifdef CONFIG_PM
4875
4876static int rtl8169_suspend(struct device *device)
4877{
4878 struct pci_dev *pdev = to_pci_dev(device);
4879 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4880
861ab440 4881 rtl8169_net_suspend(dev);
1371fa6d 4882
5d06a99f
FR		 4883 return 0;
4884}
4885
e1759441
RW		 4886static void __rtl8169_resume(struct net_device *dev)
4887{
065c27c1 4888 struct rtl8169_private *tp = netdev_priv(dev);
4889
e1759441 4890 netif_device_attach(dev);
065c27c1 4891
4892 rtl_pll_power_up(tp);
4893
e1759441
RW		 4894 rtl8169_schedule_work(dev, rtl8169_reset_task);
4895}
4896
861ab440 4897static int rtl8169_resume(struct device *device)
5d06a99f 4898{
861ab440 4899 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4900 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4901 struct rtl8169_private *tp = netdev_priv(dev);
4902
4903 rtl8169_init_phy(dev, tp);
5d06a99f 4904
e1759441
RW		 4905 if (netif_running(dev))
4906 __rtl8169_resume(dev);
5d06a99f 4907
e1759441
RW		 4908 return 0;
4909}
4910
4911static int rtl8169_runtime_suspend(struct device *device)
4912{
4913 struct pci_dev *pdev = to_pci_dev(device);
4914 struct net_device *dev = pci_get_drvdata(pdev);
4915 struct rtl8169_private *tp = netdev_priv(dev);
4916
4917 if (!tp->TxDescArray)
4918 return 0;
4919
4920 spin_lock_irq(&tp->lock);
4921 tp->saved_wolopts = __rtl8169_get_wol(tp);
4922 __rtl8169_set_wol(tp, WAKE_ANY);
4923 spin_unlock_irq(&tp->lock);
4924
4925 rtl8169_net_suspend(dev);
4926
4927 return 0;
4928}
4929
4930static int rtl8169_runtime_resume(struct device *device)
4931{
4932 struct pci_dev *pdev = to_pci_dev(device);
4933 struct net_device *dev = pci_get_drvdata(pdev);
4934 struct rtl8169_private *tp = netdev_priv(dev);
4935
4936 if (!tp->TxDescArray)
4937 return 0;
4938
4939 spin_lock_irq(&tp->lock);
4940 __rtl8169_set_wol(tp, tp->saved_wolopts);
4941 tp->saved_wolopts = 0;
4942 spin_unlock_irq(&tp->lock);
4943
fccec10b
SG		 4944 rtl8169_init_phy(dev, tp);
4945
e1759441 4946 __rtl8169_resume(dev);
5d06a99f 4947
5d06a99f
FR		 4948 return 0;
4949}
4950
e1759441
RW		 4951static int rtl8169_runtime_idle(struct device *device)
4952{
4953 struct pci_dev *pdev = to_pci_dev(device);
4954 struct net_device *dev = pci_get_drvdata(pdev);
4955 struct rtl8169_private *tp = netdev_priv(dev);
4956
e4fbce74 4957 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4958}
4959
47145210 4960static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4961 .suspend = rtl8169_suspend,
4962 .resume = rtl8169_resume,
4963 .freeze = rtl8169_suspend,
4964 .thaw = rtl8169_resume,
4965 .poweroff = rtl8169_suspend,
4966 .restore = rtl8169_resume,
e1759441
RW		 4967 .runtime_suspend = rtl8169_runtime_suspend,
4968 .runtime_resume = rtl8169_runtime_resume,
4969 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4970};
4971
4972#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4973
4974#else /* !CONFIG_PM */
4975
4976#define RTL8169_PM_OPS NULL
4977
4978#endif /* !CONFIG_PM */
4979
1765f95d
FR		 4980static void rtl_shutdown(struct pci_dev *pdev)
4981{
861ab440 4982 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4983 struct rtl8169_private *tp = netdev_priv(dev);
4984 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4985
4986 rtl8169_net_suspend(dev);
1765f95d 4987
cc098dc7
IV		 4988 /* restore original MAC address */
4989 rtl_rar_set(tp, dev->perm_addr);
4990
4bb3f522 4991 spin_lock_irq(&tp->lock);
4992
4993 rtl8169_asic_down(ioaddr);
4994
4995 spin_unlock_irq(&tp->lock);
4996
861ab440 4997 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4998 /* WoL fails with some 8168 when the receiver is disabled. */
4999 if (tp->features & RTL_FEATURE_WOL) {
5000 pci_clear_master(pdev);
5001
5002 RTL_W8(ChipCmd, CmdRxEnb);
5003 /* PCI commit */
5004 RTL_R8(ChipCmd);
5005 }
5006
861ab440
RW		 5007 pci_wake_from_d3(pdev, true);
5008 pci_set_power_state(pdev, PCI_D3hot);
5009 }
5010}
5d06a99f 5011
1da177e4
LT		 5012static struct pci_driver rtl8169_pci_driver = {
5013 .name = MODULENAME,
5014 .id_table = rtl8169_pci_tbl,
5015 .probe = rtl8169_init_one,
5016 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5017 .shutdown = rtl_shutdown,
861ab440 5018 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5019};
5020
07d3f51f 5021static int __init rtl8169_init_module(void)
1da177e4 5022{
29917620 5023 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5024}
5025
07d3f51f 5026static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5027{
5028 pci_unregister_driver(&rtl8169_pci_driver);
5029}
5030
5031module_init(rtl8169_init_module);
5032module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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