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r8169: adjust some registers.
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 44#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 45
1da177e4
LT		 46#ifdef RTL8169_DEBUG
47#define assert(expr) \
5b0384f4
FR		 48 if (!(expr)) { \
49 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 50 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 51 }
06fa7358
JP		 52#define dprintk(fmt, args...) \
53 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 54#else
55#define assert(expr) do {} while (0)
56#define dprintk(fmt, args...) do {} while (0)
57#endif /* RTL8169_DEBUG */
58
b57b7e5a 59#define R8169_MSG_DEFAULT \
f0e837d9 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 61
1da177e4
LT		 62#define TX_BUFFS_AVAIL(tp) \
63 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
64
1da177e4
LT		 65/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 67static const int multicast_filter_limit = 32;
1da177e4
LT		 68
69/* MAC address length */
70#define MAC_ADDR_LEN 6
71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4 73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
85bffe6c
FR		 101 RTL_GIGA_MAC_VER_01 = 0,
102 RTL_GIGA_MAC_VER_02,
103 RTL_GIGA_MAC_VER_03,
104 RTL_GIGA_MAC_VER_04,
105 RTL_GIGA_MAC_VER_05,
106 RTL_GIGA_MAC_VER_06,
107 RTL_GIGA_MAC_VER_07,
108 RTL_GIGA_MAC_VER_08,
109 RTL_GIGA_MAC_VER_09,
110 RTL_GIGA_MAC_VER_10,
111 RTL_GIGA_MAC_VER_11,
112 RTL_GIGA_MAC_VER_12,
113 RTL_GIGA_MAC_VER_13,
114 RTL_GIGA_MAC_VER_14,
115 RTL_GIGA_MAC_VER_15,
116 RTL_GIGA_MAC_VER_16,
117 RTL_GIGA_MAC_VER_17,
118 RTL_GIGA_MAC_VER_18,
119 RTL_GIGA_MAC_VER_19,
120 RTL_GIGA_MAC_VER_20,
121 RTL_GIGA_MAC_VER_21,
122 RTL_GIGA_MAC_VER_22,
123 RTL_GIGA_MAC_VER_23,
124 RTL_GIGA_MAC_VER_24,
125 RTL_GIGA_MAC_VER_25,
126 RTL_GIGA_MAC_VER_26,
127 RTL_GIGA_MAC_VER_27,
128 RTL_GIGA_MAC_VER_28,
129 RTL_GIGA_MAC_VER_29,
130 RTL_GIGA_MAC_VER_30,
131 RTL_GIGA_MAC_VER_31,
132 RTL_GIGA_MAC_VER_32,
133 RTL_GIGA_MAC_VER_33,
134 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 135};
136
2b7b4318
FR		 137enum rtl_tx_desc_version {
138 RTL_TD_0 = 0,
139 RTL_TD_1 = 1,
140};
141
85bffe6c
FR		 142#define _R(NAME,TD,FW) \
143 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 144
3c6bee1d 145static const struct {
1da177e4 146 const char *name;
2b7b4318 147 enum rtl_tx_desc_version txd_version;
953a12cc 148 const char *fw_name;
85bffe6c
FR		 149} rtl_chip_infos[] = {
150 /* PCI devices. */
151 [RTL_GIGA_MAC_VER_01] =
152 _R("RTL8169", RTL_TD_0, NULL),
153 [RTL_GIGA_MAC_VER_02] =
154 _R("RTL8169s", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_03] =
156 _R("RTL8110s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_04] =
158 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_05] =
160 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_06] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 /* PCI-E devices. */
164 [RTL_GIGA_MAC_VER_07] =
165 _R("RTL8102e", RTL_TD_1, NULL),
166 [RTL_GIGA_MAC_VER_08] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_09] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_10] =
171 _R("RTL8101e", RTL_TD_0, NULL),
172 [RTL_GIGA_MAC_VER_11] =
173 _R("RTL8168b/8111b", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_12] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_13] =
177 _R("RTL8101e", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_14] =
179 _R("RTL8100e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_15] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_16] =
183 _R("RTL8101e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_17] =
185 _R("RTL8168b/8111b", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_18] =
187 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
188 [RTL_GIGA_MAC_VER_19] =
189 _R("RTL8168c/8111c", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_20] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_21] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_22] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_23] =
197 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_24] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_25] =
201 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
202 [RTL_GIGA_MAC_VER_26] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
204 [RTL_GIGA_MAC_VER_27] =
205 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
206 [RTL_GIGA_MAC_VER_28] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_29] =
209 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
210 [RTL_GIGA_MAC_VER_30] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_31] =
213 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
214 [RTL_GIGA_MAC_VER_32] =
215 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
216 [RTL_GIGA_MAC_VER_33] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
953a12cc 218};
85bffe6c 219#undef _R
953a12cc 220
bcf0bf90
FR		 221enum cfg_version {
222 RTL_CFG_0 = 0x00,
223 RTL_CFG_1,
224 RTL_CFG_2
225};
226
07ce4064
FR		 227static void rtl_hw_start_8169(struct net_device *);
228static void rtl_hw_start_8168(struct net_device *);
229static void rtl_hw_start_8101(struct net_device *);
230
a3aa1884 231static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 232 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 233 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
237 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 238 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 239 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
240 { PCI_VENDOR_ID_LINKSYS, 0x1032,
241 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 242 { 0x0001, 0x8168,
243 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 244 {0,},
245};
246
247MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
248
6f0333b8 249static int rx_buf_sz = 16383;
4300e8c7 250static int use_dac;
b57b7e5a
SH		 251static struct {
252 u32 msg_enable;
253} debug = { -1 };
1da177e4 254
07d3f51f
FR		 255enum rtl_registers {
256 MAC0 = 0, /* Ethernet hardware address. */
773d2021 257 MAC4 = 4,
07d3f51f
FR		 258 MAR0 = 8, /* Multicast filter. */
259 CounterAddrLow = 0x10,
260 CounterAddrHigh = 0x14,
261 TxDescStartAddrLow = 0x20,
262 TxDescStartAddrHigh = 0x24,
263 TxHDescStartAddrLow = 0x28,
264 TxHDescStartAddrHigh = 0x2c,
265 FLASH = 0x30,
266 ERSR = 0x36,
267 ChipCmd = 0x37,
268 TxPoll = 0x38,
269 IntrMask = 0x3c,
270 IntrStatus = 0x3e,
4f6b00e5 271
07d3f51f 272 TxConfig = 0x40,
4f6b00e5
HW		 273#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
274#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 275
4f6b00e5
HW		 276 RxConfig = 0x44,
277#define RX128_INT_EN (1 << 15) /* 8111c and later */
278#define RX_MULTI_EN (1 << 14) /* 8111c only */
279#define RXCFG_FIFO_SHIFT 13
280 /* No threshold before first PCI xfer */
281#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
282#define RXCFG_DMA_SHIFT 8
283 /* Unlimited maximum PCI burst. */
284#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318
FR		 285#define RTL_RX_CONFIG_MASK 0xff7e1880u
286
07d3f51f
FR		 287 RxMissed = 0x4c,
288 Cfg9346 = 0x50,
289 Config0 = 0x51,
290 Config1 = 0x52,
291 Config2 = 0x53,
292 Config3 = 0x54,
293 Config4 = 0x55,
294 Config5 = 0x56,
295 MultiIntr = 0x5c,
296 PHYAR = 0x60,
07d3f51f
FR		 297 PHYstatus = 0x6c,
298 RxMaxSize = 0xda,
299 CPlusCmd = 0xe0,
300 IntrMitigate = 0xe2,
301 RxDescAddrLow = 0xe4,
302 RxDescAddrHigh = 0xe8,
f0298f81 303 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
304
305#define NoEarlyTx 0x3f /* Max value : no early transmit. */
306
307 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
308
309#define TxPacketMax (8064 >> 7)
310
07d3f51f
FR		 311 FuncEvent = 0xf0,
312 FuncEventMask = 0xf4,
313 FuncPresetState = 0xf8,
314 FuncForceEvent = 0xfc,
1da177e4
LT		 315};
316
f162a5d1
FR		 317enum rtl8110_registers {
318 TBICSR = 0x64,
319 TBI_ANAR = 0x68,
320 TBI_LPAR = 0x6a,
321};
322
323enum rtl8168_8101_registers {
324 CSIDR = 0x64,
325 CSIAR = 0x68,
326#define CSIAR_FLAG 0x80000000
327#define CSIAR_WRITE_CMD 0x80000000
328#define CSIAR_BYTE_ENABLE 0x0f
329#define CSIAR_BYTE_ENABLE_SHIFT 12
330#define CSIAR_ADDR_MASK 0x0fff
065c27c1 331 PMCH = 0x6f,
f162a5d1
FR		 332 EPHYAR = 0x80,
333#define EPHYAR_FLAG 0x80000000
334#define EPHYAR_WRITE_CMD 0x80000000
335#define EPHYAR_REG_MASK 0x1f
336#define EPHYAR_REG_SHIFT 16
337#define EPHYAR_DATA_MASK 0xffff
5a5e4443 338 DLLPR = 0xd0,
4f6b00e5 339#define PFM_EN (1 << 6)
f162a5d1
FR		 340 DBG_REG = 0xd1,
341#define FIX_NAK_1 (1 << 4)
342#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 343 TWSI = 0xd2,
344 MCU = 0xd3,
4f6b00e5 345#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 346#define EN_NDP (1 << 3)
347#define EN_OOB_RESET (1 << 2)
daf9df6d 348 EFUSEAR = 0xdc,
349#define EFUSEAR_FLAG 0x80000000
350#define EFUSEAR_WRITE_CMD 0x80000000
351#define EFUSEAR_READ_CMD 0x00000000
352#define EFUSEAR_REG_MASK 0x03ff
353#define EFUSEAR_REG_SHIFT 8
354#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 355};
356
c0e45c1c 357enum rtl8168_registers {
4f6b00e5
HW		 358 LED_FREQ = 0x1a,
359 EEE_LED = 0x1b,
b646d900 360 ERIDR = 0x70,
361 ERIAR = 0x74,
362#define ERIAR_FLAG 0x80000000
363#define ERIAR_WRITE_CMD 0x80000000
364#define ERIAR_READ_CMD 0x00000000
365#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 366#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 367#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
368#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
369#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
370#define ERIAR_MASK_SHIFT 12
371#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
372#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
373#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 374 EPHY_RXER_NUM = 0x7c,
375 OCPDR = 0xb0, /* OCP GPHY access */
376#define OCPDR_WRITE_CMD 0x80000000
377#define OCPDR_READ_CMD 0x00000000
378#define OCPDR_REG_MASK 0x7f
379#define OCPDR_GPHY_REG_SHIFT 16
380#define OCPDR_DATA_MASK 0xffff
381 OCPAR = 0xb4,
382#define OCPAR_FLAG 0x80000000
383#define OCPAR_GPHY_WRITE_CMD 0x8000f060
384#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 385 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
386 MISC = 0xf0, /* 8168e only. */
cecb5fd7 387#define TXPLA_RST (1 << 29)
4f6b00e5 388#define PWM_EN (1 << 22)
c0e45c1c 389};
390
07d3f51f 391enum rtl_register_content {
1da177e4 392 /* InterruptStatusBits */
07d3f51f
FR		 393 SYSErr = 0x8000,
394 PCSTimeout = 0x4000,
395 SWInt = 0x0100,
396 TxDescUnavail = 0x0080,
397 RxFIFOOver = 0x0040,
398 LinkChg = 0x0020,
399 RxOverflow = 0x0010,
400 TxErr = 0x0008,
401 TxOK = 0x0004,
402 RxErr = 0x0002,
403 RxOK = 0x0001,
1da177e4
LT		 404
405 /* RxStatusDesc */
9dccf611
FR		 406 RxFOVF = (1 << 23),
407 RxRWT = (1 << 22),
408 RxRES = (1 << 21),
409 RxRUNT = (1 << 20),
410 RxCRC = (1 << 19),
1da177e4
LT		 411
412 /* ChipCmdBits */
4f6b00e5 413 StopReq = 0x80,
07d3f51f
FR		 414 CmdReset = 0x10,
415 CmdRxEnb = 0x08,
416 CmdTxEnb = 0x04,
417 RxBufEmpty = 0x01,
1da177e4 418
275391a4
FR		 419 /* TXPoll register p.5 */
420 HPQ = 0x80, /* Poll cmd on the high prio queue */
421 NPQ = 0x40, /* Poll cmd on the low prio queue */
422 FSWInt = 0x01, /* Forced software interrupt */
423
1da177e4 424 /* Cfg9346Bits */
07d3f51f
FR		 425 Cfg9346_Lock = 0x00,
426 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 427
428 /* rx_mode_bits */
07d3f51f
FR		 429 AcceptErr = 0x20,
430 AcceptRunt = 0x10,
431 AcceptBroadcast = 0x08,
432 AcceptMulticast = 0x04,
433 AcceptMyPhys = 0x02,
434 AcceptAllPhys = 0x01,
1da177e4 435
1da177e4
LT		 436 /* TxConfigBits */
437 TxInterFrameGapShift = 24,
438 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
439
5d06a99f 440 /* Config1 register p.24 */
f162a5d1
FR		 441 LEDS1 = (1 << 7),
442 LEDS0 = (1 << 6),
fbac58fc 443 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 444 Speed_down = (1 << 4),
445 MEMMAP = (1 << 3),
446 IOMAP = (1 << 2),
447 VPD = (1 << 1),
5d06a99f
FR		 448 PMEnable = (1 << 0), /* Power Management Enable */
449
6dccd16b
FR		 450 /* Config2 register p. 25 */
451 PCI_Clock_66MHz = 0x01,
452 PCI_Clock_33MHz = 0x00,
453
61a4dcc2
FR		 454 /* Config3 register p.25 */
455 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
456 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 457 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 458
5d06a99f 459 /* Config5 register p.27 */
61a4dcc2
FR		 460 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
461 MWF = (1 << 5), /* Accept Multicast wakeup frame */
462 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 463 Spi_en = (1 << 3),
61a4dcc2 464 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 465 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
466
1da177e4
LT		 467 /* TBICSR p.28 */
468 TBIReset = 0x80000000,
469 TBILoopback = 0x40000000,
470 TBINwEnable = 0x20000000,
471 TBINwRestart = 0x10000000,
472 TBILinkOk = 0x02000000,
473 TBINwComplete = 0x01000000,
474
475 /* CPlusCmd p.31 */
f162a5d1
FR		 476 EnableBist = (1 << 15), // 8168 8101
477 Mac_dbgo_oe = (1 << 14), // 8168 8101
478 Normal_mode = (1 << 13), // unused
479 Force_half_dup = (1 << 12), // 8168 8101
480 Force_rxflow_en = (1 << 11), // 8168 8101
481 Force_txflow_en = (1 << 10), // 8168 8101
482 Cxpl_dbg_sel = (1 << 9), // 8168 8101
483 ASF = (1 << 8), // 8168 8101
484 PktCntrDisable = (1 << 7), // 8168 8101
485 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 486 RxVlan = (1 << 6),
487 RxChkSum = (1 << 5),
488 PCIDAC = (1 << 4),
489 PCIMulRW = (1 << 3),
0e485150
FR		 490 INTT_0 = 0x0000, // 8168
491 INTT_1 = 0x0001, // 8168
492 INTT_2 = 0x0002, // 8168
493 INTT_3 = 0x0003, // 8168
1da177e4
LT		 494
495 /* rtl8169_PHYstatus */
07d3f51f
FR		 496 TBI_Enable = 0x80,
497 TxFlowCtrl = 0x40,
498 RxFlowCtrl = 0x20,
499 _1000bpsF = 0x10,
500 _100bps = 0x08,
501 _10bps = 0x04,
502 LinkStatus = 0x02,
503 FullDup = 0x01,
1da177e4 504
1da177e4 505 /* _TBICSRBit */
07d3f51f 506 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 507
508 /* DumpCounterCommand */
07d3f51f 509 CounterDump = 0x8,
1da177e4
LT		 510};
511
2b7b4318
FR		 512enum rtl_desc_bit {
513 /* First doubleword. */
1da177e4
LT		 514 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
515 RingEnd = (1 << 30), /* End of descriptor ring */
516 FirstFrag = (1 << 29), /* First segment of a packet */
517 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 518};
519
520/* Generic case. */
521enum rtl_tx_desc_bit {
522 /* First doubleword. */
523 TD_LSO = (1 << 27), /* Large Send Offload */
524#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 525
2b7b4318
FR		 526 /* Second doubleword. */
527 TxVlanTag = (1 << 17), /* Add VLAN tag */
528};
529
530/* 8169, 8168b and 810x except 8102e. */
531enum rtl_tx_desc_bit_0 {
532 /* First doubleword. */
533#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
534 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
535 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
536 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
537};
538
539/* 8102e, 8168c and beyond. */
540enum rtl_tx_desc_bit_1 {
541 /* Second doubleword. */
542#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
543 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
544 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
545 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
546};
1da177e4 547
2b7b4318
FR		 548static const struct rtl_tx_desc_info {
549 struct {
550 u32 udp;
551 u32 tcp;
552 } checksum;
553 u16 mss_shift;
554 u16 opts_offset;
555} tx_desc_info [] = {
556 [RTL_TD_0] = {
557 .checksum = {
558 .udp = TD0_IP_CS | TD0_UDP_CS,
559 .tcp = TD0_IP_CS | TD0_TCP_CS
560 },
561 .mss_shift = TD0_MSS_SHIFT,
562 .opts_offset = 0
563 },
564 [RTL_TD_1] = {
565 .checksum = {
566 .udp = TD1_IP_CS | TD1_UDP_CS,
567 .tcp = TD1_IP_CS | TD1_TCP_CS
568 },
569 .mss_shift = TD1_MSS_SHIFT,
570 .opts_offset = 1
571 }
572};
573
574enum rtl_rx_desc_bit {
1da177e4
LT		 575 /* Rx private */
576 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
577 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
578
579#define RxProtoUDP (PID1)
580#define RxProtoTCP (PID0)
581#define RxProtoIP (PID1 | PID0)
582#define RxProtoMask RxProtoIP
583
584 IPFail = (1 << 16), /* IP checksum failed */
585 UDPFail = (1 << 15), /* UDP/IP checksum failed */
586 TCPFail = (1 << 14), /* TCP/IP checksum failed */
587 RxVlanTag = (1 << 16), /* VLAN tag available */
588};
589
590#define RsvdMask 0x3fffc000
591
592struct TxDesc {
6cccd6e7
REB		 593 __le32 opts1;
594 __le32 opts2;
595 __le64 addr;
1da177e4
LT		 596};
597
598struct RxDesc {
6cccd6e7
REB		 599 __le32 opts1;
600 __le32 opts2;
601 __le64 addr;
1da177e4
LT		 602};
603
604struct ring_info {
605 struct sk_buff *skb;
606 u32 len;
607 u8 __pad[sizeof(void *) - sizeof(u32)];
608};
609
f23e7fda 610enum features {
ccdffb9a
FR		 611 RTL_FEATURE_WOL = (1 << 0),
612 RTL_FEATURE_MSI = (1 << 1),
613 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 614};
615
355423d0
IV		 616struct rtl8169_counters {
617 __le64 tx_packets;
618 __le64 rx_packets;
619 __le64 tx_errors;
620 __le32 rx_errors;
621 __le16 rx_missed;
622 __le16 align_errors;
623 __le32 tx_one_collision;
624 __le32 tx_multi_collision;
625 __le64 rx_unicast;
626 __le64 rx_broadcast;
627 __le32 rx_multicast;
628 __le16 tx_aborted;
629 __le16 tx_underun;
630};
631
1da177e4
LT		 632struct rtl8169_private {
633 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 634 struct pci_dev *pci_dev;
c4028958 635 struct net_device *dev;
bea3348e 636 struct napi_struct napi;
cecb5fd7 637 spinlock_t lock;
b57b7e5a 638 u32 msg_enable;
2b7b4318
FR		 639 u16 txd_version;
640 u16 mac_version;
1da177e4
LT		 641 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
642 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
643 u32 dirty_rx;
644 u32 dirty_tx;
645 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
646 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
647 dma_addr_t TxPhyAddr;
648 dma_addr_t RxPhyAddr;
6f0333b8 649 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 650 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 651 struct timer_list timer;
652 u16 cp_cmd;
0e485150
FR		 653 u16 intr_event;
654 u16 napi_event;
1da177e4 655 u16 intr_mask;
c0e45c1c 656
657 struct mdio_ops {
658 void (*write)(void __iomem *, int, int);
659 int (*read)(void __iomem *, int);
660 } mdio_ops;
661
065c27c1 662 struct pll_power_ops {
663 void (*down)(struct rtl8169_private *);
664 void (*up)(struct rtl8169_private *);
665 } pll_power_ops;
666
54405cde 667 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 668 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 669 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 670 void (*hw_start)(struct net_device *);
4da19633 671 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 672 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 673 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 674 struct delayed_work task;
f23e7fda 675 unsigned features;
ccdffb9a
FR		 676
677 struct mii_if_info mii;
355423d0 678 struct rtl8169_counters counters;
e1759441 679 u32 saved_wolopts;
f1e02ed1 680
b6ffd97f
FR		 681 struct rtl_fw {
682 const struct firmware *fw;
1c361efb
FR		 683
684#define RTL_VER_SIZE 32
685
686 char version[RTL_VER_SIZE];
687
688 struct rtl_fw_phy_action {
689 __le32 *code;
690 size_t size;
691 } phy_action;
b6ffd97f 692 } *rtl_fw;
953a12cc 693#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 694};
695
979b6c13 696MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 697MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 698module_param(use_dac, int, 0);
4300e8c7 699MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 700module_param_named(debug, debug.msg_enable, int, 0);
701MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 702MODULE_LICENSE("GPL");
703MODULE_VERSION(RTL8169_VERSION);
bca03d5f 704MODULE_FIRMWARE(FIRMWARE_8168D_1);
705MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 706MODULE_FIRMWARE(FIRMWARE_8168E_1);
707MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 708MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 709
710static int rtl8169_open(struct net_device *dev);
61357325
SH		 711static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
712 struct net_device *dev);
7d12e780 713static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 714static int rtl8169_init_ring(struct net_device *dev);
07ce4064 715static void rtl_hw_start(struct net_device *dev);
1da177e4 716static int rtl8169_close(struct net_device *dev);
07ce4064 717static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 718static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 719static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 720static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 721 void __iomem *, u32 budget);
4dcb7d33 722static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 723static void rtl8169_down(struct net_device *dev);
99f252b0 724static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 725static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 726
4f6b00e5 727static const unsigned int rtl8169_rx_config = RX_FIFO_THRESH | RX_DMA_BURST;
1da177e4 728
b646d900 729static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
730{
731 void __iomem *ioaddr = tp->mmio_addr;
732 int i;
733
734 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
735 for (i = 0; i < 20; i++) {
736 udelay(100);
737 if (RTL_R32(OCPAR) & OCPAR_FLAG)
738 break;
739 }
740 return RTL_R32(OCPDR);
741}
742
743static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
744{
745 void __iomem *ioaddr = tp->mmio_addr;
746 int i;
747
748 RTL_W32(OCPDR, data);
749 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
750 for (i = 0; i < 20; i++) {
751 udelay(100);
752 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
753 break;
754 }
755}
756
fac5b3ca 757static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 758{
fac5b3ca 759 void __iomem *ioaddr = tp->mmio_addr;
b646d900 760 int i;
761
762 RTL_W8(ERIDR, cmd);
763 RTL_W32(ERIAR, 0x800010e8);
764 msleep(2);
765 for (i = 0; i < 5; i++) {
766 udelay(100);
1e4e82ba 767 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 768 break;
769 }
770
fac5b3ca 771 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 772}
773
774#define OOB_CMD_RESET 0x00
775#define OOB_CMD_DRIVER_START 0x05
776#define OOB_CMD_DRIVER_STOP 0x06
777
cecb5fd7
FR		 778static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
779{
780 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
781}
782
b646d900 783static void rtl8168_driver_start(struct rtl8169_private *tp)
784{
cecb5fd7 785 u16 reg;
b646d900 786 int i;
787
788 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
789
cecb5fd7 790 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 791
b646d900 792 for (i = 0; i < 10; i++) {
793 msleep(10);
4804b3b3 794 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 795 break;
796 }
797}
798
799static void rtl8168_driver_stop(struct rtl8169_private *tp)
800{
cecb5fd7 801 u16 reg;
b646d900 802 int i;
803
804 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
805
cecb5fd7 806 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 807
b646d900 808 for (i = 0; i < 10; i++) {
809 msleep(10);
4804b3b3 810 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 811 break;
812 }
813}
814
4804b3b3 815static int r8168dp_check_dash(struct rtl8169_private *tp)
816{
cecb5fd7 817 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 818
cecb5fd7 819 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 820}
b646d900 821
4da19633 822static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 823{
824 int i;
825
a6baf3af 826 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 827
2371408c 828 for (i = 20; i > 0; i--) {
07d3f51f
FR		 829 /*
830 * Check if the RTL8169 has completed writing to the specified
831 * MII register.
832 */
5b0384f4 833 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 834 break;
2371408c 835 udelay(25);
1da177e4 836 }
024a07ba 837 /*
81a95f04
TT		 838 * According to hardware specs a 20us delay is required after write
839 * complete indication, but before sending next command.
024a07ba 840 */
81a95f04 841 udelay(20);
1da177e4
LT		 842}
843
4da19633 844static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 845{
846 int i, value = -1;
847
a6baf3af 848 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 849
2371408c 850 for (i = 20; i > 0; i--) {
07d3f51f
FR		 851 /*
852 * Check if the RTL8169 has completed retrieving data from
853 * the specified MII register.
854 */
1da177e4 855 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 856 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 857 break;
858 }
2371408c 859 udelay(25);
1da177e4 860 }
81a95f04
TT		 861 /*
862 * According to hardware specs a 20us delay is required after read
863 * complete indication, but before sending next command.
864 */
865 udelay(20);
866
1da177e4
LT		 867 return value;
868}
869
c0e45c1c 870static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
871{
872 int i;
873
874 RTL_W32(OCPDR, data |
875 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
876 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
877 RTL_W32(EPHY_RXER_NUM, 0);
878
879 for (i = 0; i < 100; i++) {
880 mdelay(1);
881 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
882 break;
883 }
884}
885
886static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
887{
888 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
889 (value & OCPDR_DATA_MASK));
890}
891
892static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
893{
894 int i;
895
896 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
897
898 mdelay(1);
899 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
900 RTL_W32(EPHY_RXER_NUM, 0);
901
902 for (i = 0; i < 100; i++) {
903 mdelay(1);
904 if (RTL_R32(OCPAR) & OCPAR_FLAG)
905 break;
906 }
907
908 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
909}
910
e6de30d6 911#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
912
913static void r8168dp_2_mdio_start(void __iomem *ioaddr)
914{
915 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
916}
917
918static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
919{
920 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
921}
922
923static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
924{
925 r8168dp_2_mdio_start(ioaddr);
926
927 r8169_mdio_write(ioaddr, reg_addr, value);
928
929 r8168dp_2_mdio_stop(ioaddr);
930}
931
932static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
933{
934 int value;
935
936 r8168dp_2_mdio_start(ioaddr);
937
938 value = r8169_mdio_read(ioaddr, reg_addr);
939
940 r8168dp_2_mdio_stop(ioaddr);
941
942 return value;
943}
944
4da19633 945static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 946{
c0e45c1c 947 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 948}
949
4da19633 950static int rtl_readphy(struct rtl8169_private *tp, int location)
951{
c0e45c1c 952 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 953}
954
955static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
956{
957 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
958}
959
960static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 961{
962 int val;
963
4da19633 964 val = rtl_readphy(tp, reg_addr);
965 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 966}
967
ccdffb9a
FR		 968static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
969 int val)
970{
971 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 972
4da19633 973 rtl_writephy(tp, location, val);
ccdffb9a
FR		 974}
975
976static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
977{
978 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 979
4da19633 980 return rtl_readphy(tp, location);
ccdffb9a
FR		 981}
982
dacf8154
FR		 983static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
984{
985 unsigned int i;
986
987 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
988 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
989
990 for (i = 0; i < 100; i++) {
991 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
992 break;
993 udelay(10);
994 }
995}
996
997static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
998{
999 u16 value = 0xffff;
1000 unsigned int i;
1001
1002 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1003
1004 for (i = 0; i < 100; i++) {
1005 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1006 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1007 break;
1008 }
1009 udelay(10);
1010 }
1011
1012 return value;
1013}
1014
1015static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1016{
1017 unsigned int i;
1018
1019 RTL_W32(CSIDR, value);
1020 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1021 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1022
1023 for (i = 0; i < 100; i++) {
1024 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1025 break;
1026 udelay(10);
1027 }
1028}
1029
1030static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1031{
1032 u32 value = ~0x00;
1033 unsigned int i;
1034
1035 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1036 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1037
1038 for (i = 0; i < 100; i++) {
1039 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1040 value = RTL_R32(CSIDR);
1041 break;
1042 }
1043 udelay(10);
1044 }
1045
1046 return value;
1047}
1048
daf9df6d 1049static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1050{
1051 u8 value = 0xff;
1052 unsigned int i;
1053
1054 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1055
1056 for (i = 0; i < 300; i++) {
1057 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1058 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1059 break;
1060 }
1061 udelay(100);
1062 }
1063
1064 return value;
1065}
1066
1da177e4
LT		 1067static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1068{
1069 RTL_W16(IntrMask, 0x0000);
1070
1071 RTL_W16(IntrStatus, 0xffff);
1072}
1073
1074static void rtl8169_asic_down(void __iomem *ioaddr)
1075{
1076 RTL_W8(ChipCmd, 0x00);
1077 rtl8169_irq_mask_and_ack(ioaddr);
1078 RTL_R16(CPlusCmd);
1079}
1080
4da19633 1081static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1082{
4da19633 1083 void __iomem *ioaddr = tp->mmio_addr;
1084
1da177e4
LT		 1085 return RTL_R32(TBICSR) & TBIReset;
1086}
1087
4da19633 1088static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1089{
4da19633 1090 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1091}
1092
1093static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1094{
1095 return RTL_R32(TBICSR) & TBILinkOk;
1096}
1097
1098static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1099{
1100 return RTL_R8(PHYstatus) & LinkStatus;
1101}
1102
4da19633 1103static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1104{
4da19633 1105 void __iomem *ioaddr = tp->mmio_addr;
1106
1da177e4
LT		 1107 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1108}
1109
4da19633 1110static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1111{
1112 unsigned int val;
1113
4da19633 1114 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1115 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1116}
1117
e4fbce74 1118static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1119 struct rtl8169_private *tp,
1120 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1121{
1122 unsigned long flags;
1123
1124 spin_lock_irqsave(&tp->lock, flags);
1125 if (tp->link_ok(ioaddr)) {
e1759441 1126 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1127 if (pm)
1128 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1129 netif_carrier_on(dev);
1519e57f
FR		 1130 if (net_ratelimit())
1131 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1132 } else {
1da177e4 1133 netif_carrier_off(dev);
bf82c189 1134 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1135 if (pm)
1136 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1137 }
1da177e4
LT		 1138 spin_unlock_irqrestore(&tp->lock, flags);
1139}
1140
e4fbce74
RW		 1141static void rtl8169_check_link_status(struct net_device *dev,
1142 struct rtl8169_private *tp,
1143 void __iomem *ioaddr)
1144{
1145 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1146}
1147
e1759441
RW		 1148#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1149
1150static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1151{
61a4dcc2
FR		 1152 void __iomem *ioaddr = tp->mmio_addr;
1153 u8 options;
e1759441 1154 u32 wolopts = 0;
61a4dcc2
FR		 1155
1156 options = RTL_R8(Config1);
1157 if (!(options & PMEnable))
e1759441 1158 return 0;
61a4dcc2
FR		 1159
1160 options = RTL_R8(Config3);
1161 if (options & LinkUp)
e1759441 1162 wolopts |= WAKE_PHY;
61a4dcc2 1163 if (options & MagicPacket)
e1759441 1164 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1165
1166 options = RTL_R8(Config5);
1167 if (options & UWF)
e1759441 1168 wolopts |= WAKE_UCAST;
61a4dcc2 1169 if (options & BWF)
e1759441 1170 wolopts |= WAKE_BCAST;
61a4dcc2 1171 if (options & MWF)
e1759441 1172 wolopts |= WAKE_MCAST;
61a4dcc2 1173
e1759441 1174 return wolopts;
61a4dcc2
FR		 1175}
1176
e1759441 1177static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1178{
1179 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1180
1181 spin_lock_irq(&tp->lock);
1182
1183 wol->supported = WAKE_ANY;
1184 wol->wolopts = __rtl8169_get_wol(tp);
1185
1186 spin_unlock_irq(&tp->lock);
1187}
1188
1189static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1190{
61a4dcc2 1191 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1192 unsigned int i;
350f7596 1193 static const struct {
61a4dcc2
FR		 1194 u32 opt;
1195 u16 reg;
1196 u8 mask;
1197 } cfg[] = {
1198 { WAKE_ANY, Config1, PMEnable },
1199 { WAKE_PHY, Config3, LinkUp },
1200 { WAKE_MAGIC, Config3, MagicPacket },
1201 { WAKE_UCAST, Config5, UWF },
1202 { WAKE_BCAST, Config5, BWF },
1203 { WAKE_MCAST, Config5, MWF },
1204 { WAKE_ANY, Config5, LanWake }
1205 };
1206
61a4dcc2
FR		 1207 RTL_W8(Cfg9346, Cfg9346_Unlock);
1208
1209 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1210 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1211 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1212 options |= cfg[i].mask;
1213 RTL_W8(cfg[i].reg, options);
1214 }
1215
1216 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1217}
1218
1219static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1220{
1221 struct rtl8169_private *tp = netdev_priv(dev);
1222
1223 spin_lock_irq(&tp->lock);
61a4dcc2 1224
f23e7fda
FR		 1225 if (wol->wolopts)
1226 tp->features |= RTL_FEATURE_WOL;
1227 else
1228 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1229 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1230 spin_unlock_irq(&tp->lock);
1231
ea80907f 1232 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1233
61a4dcc2
FR		 1234 return 0;
1235}
1236
31bd204f
FR		 1237static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1238{
85bffe6c 1239 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1240}
1241
1da177e4
LT		 1242static void rtl8169_get_drvinfo(struct net_device *dev,
1243 struct ethtool_drvinfo *info)
1244{
1245 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1246 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1247
1248 strcpy(info->driver, MODULENAME);
1249 strcpy(info->version, RTL8169_VERSION);
1250 strcpy(info->bus_info, pci_name(tp->pci_dev));
1c361efb
FR		 1251 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1252 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1253 rtl_fw->version);
1da177e4
LT		 1254}
1255
1256static int rtl8169_get_regs_len(struct net_device *dev)
1257{
1258 return R8169_REGS_SIZE;
1259}
1260
1261static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1262 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1263{
1264 struct rtl8169_private *tp = netdev_priv(dev);
1265 void __iomem *ioaddr = tp->mmio_addr;
1266 int ret = 0;
1267 u32 reg;
1268
1269 reg = RTL_R32(TBICSR);
1270 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1271 (duplex == DUPLEX_FULL)) {
1272 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1273 } else if (autoneg == AUTONEG_ENABLE)
1274 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1275 else {
bf82c189
JP		 1276 netif_warn(tp, link, dev,
1277 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1278 ret = -EOPNOTSUPP;
1279 }
1280
1281 return ret;
1282}
1283
1284static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1285 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1286{
1287 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1288 int giga_ctrl, bmcr;
54405cde 1289 int rc = -EINVAL;
1da177e4 1290
716b50a3 1291 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1292
1293 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1294 int auto_nego;
1295
4da19633 1296 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1297 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1298 ADVERTISE_100HALF | ADVERTISE_100FULL);
1299
1300 if (adv & ADVERTISED_10baseT_Half)
1301 auto_nego |= ADVERTISE_10HALF;
1302 if (adv & ADVERTISED_10baseT_Full)
1303 auto_nego |= ADVERTISE_10FULL;
1304 if (adv & ADVERTISED_100baseT_Half)
1305 auto_nego |= ADVERTISE_100HALF;
1306 if (adv & ADVERTISED_100baseT_Full)
1307 auto_nego |= ADVERTISE_100FULL;
1308
3577aa1b 1309 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1310
4da19633 1311 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1312 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1313
3577aa1b 1314 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1315 if (tp->mii.supports_gmii) {
54405cde
ON		 1316 if (adv & ADVERTISED_1000baseT_Half)
1317 giga_ctrl |= ADVERTISE_1000HALF;
1318 if (adv & ADVERTISED_1000baseT_Full)
1319 giga_ctrl |= ADVERTISE_1000FULL;
1320 } else if (adv & (ADVERTISED_1000baseT_Half |
1321 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1322 netif_info(tp, link, dev,
1323 "PHY does not support 1000Mbps\n");
54405cde 1324 goto out;
bcf0bf90 1325 }
1da177e4 1326
3577aa1b 1327 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1328
4da19633 1329 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1330 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1331 } else {
1332 giga_ctrl = 0;
1333
1334 if (speed == SPEED_10)
1335 bmcr = 0;
1336 else if (speed == SPEED_100)
1337 bmcr = BMCR_SPEED100;
1338 else
54405cde 1339 goto out;
3577aa1b 1340
1341 if (duplex == DUPLEX_FULL)
1342 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1343 }
1344
4da19633 1345 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1346
cecb5fd7
FR		 1347 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1348 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1349 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1350 rtl_writephy(tp, 0x17, 0x2138);
1351 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1352 } else {
4da19633 1353 rtl_writephy(tp, 0x17, 0x2108);
1354 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1355 }
1356 }
1357
54405cde
ON		 1358 rc = 0;
1359out:
1360 return rc;
1da177e4
LT		 1361}
1362
1363static int rtl8169_set_speed(struct net_device *dev,
54405cde 1364 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1365{
1366 struct rtl8169_private *tp = netdev_priv(dev);
1367 int ret;
1368
54405cde 1369 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1370 if (ret < 0)
1371 goto out;
1da177e4 1372
4876cc1e
FR		 1373 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1374 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1375 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1376 }
1377out:
1da177e4
LT		 1378 return ret;
1379}
1380
1381static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1382{
1383 struct rtl8169_private *tp = netdev_priv(dev);
1384 unsigned long flags;
1385 int ret;
1386
4876cc1e
FR		 1387 del_timer_sync(&tp->timer);
1388
1da177e4 1389 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1390 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1391 cmd->duplex, cmd->advertising);
1da177e4 1392 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1393
1da177e4
LT		 1394 return ret;
1395}
1396
350fb32a 1397static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1398{
2b7b4318 1399 if (dev->mtu > TD_MSS_MAX)
350fb32a 1400 features &= ~NETIF_F_ALL_TSO;
1da177e4 1401
350fb32a 1402 return features;
1da177e4
LT		 1403}
1404
350fb32a 1405static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1406{
1407 struct rtl8169_private *tp = netdev_priv(dev);
1408 void __iomem *ioaddr = tp->mmio_addr;
1409 unsigned long flags;
1410
1411 spin_lock_irqsave(&tp->lock, flags);
1412
350fb32a 1413 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1414 tp->cp_cmd |= RxChkSum;
1415 else
1416 tp->cp_cmd &= ~RxChkSum;
1417
350fb32a
MM		 1418 if (dev->features & NETIF_F_HW_VLAN_RX)
1419 tp->cp_cmd |= RxVlan;
1420 else
1421 tp->cp_cmd &= ~RxVlan;
1422
1da177e4
LT		 1423 RTL_W16(CPlusCmd, tp->cp_cmd);
1424 RTL_R16(CPlusCmd);
1425
1426 spin_unlock_irqrestore(&tp->lock, flags);
1427
1428 return 0;
1429}
1430
1da177e4
LT		 1431static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1432 struct sk_buff *skb)
1433{
eab6d18d 1434 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1435 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1436}
1437
7a8fc77b 1438static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1439{
1440 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1441
7a8fc77b
FR		 1442 if (opts2 & RxVlanTag)
1443 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1444
1da177e4 1445 desc->opts2 = 0;
1da177e4
LT		 1446}
1447
ccdffb9a 1448static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1449{
1450 struct rtl8169_private *tp = netdev_priv(dev);
1451 void __iomem *ioaddr = tp->mmio_addr;
1452 u32 status;
1453
1454 cmd->supported =
1455 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1456 cmd->port = PORT_FIBRE;
1457 cmd->transceiver = XCVR_INTERNAL;
1458
1459 status = RTL_R32(TBICSR);
1460 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1461 cmd->autoneg = !!(status & TBINwEnable);
1462
70739497 1463 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1464 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1465
1466 return 0;
1da177e4
LT		 1467}
1468
ccdffb9a 1469static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1470{
1471 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1472
1473 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1474}
1475
1476static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1477{
1478 struct rtl8169_private *tp = netdev_priv(dev);
1479 unsigned long flags;
ccdffb9a 1480 int rc;
1da177e4
LT		 1481
1482 spin_lock_irqsave(&tp->lock, flags);
1483
ccdffb9a 1484 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1485
1486 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1487 return rc;
1da177e4
LT		 1488}
1489
1490static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1491 void *p)
1492{
5b0384f4
FR		 1493 struct rtl8169_private *tp = netdev_priv(dev);
1494 unsigned long flags;
1da177e4 1495
5b0384f4
FR		 1496 if (regs->len > R8169_REGS_SIZE)
1497 regs->len = R8169_REGS_SIZE;
1da177e4 1498
5b0384f4
FR		 1499 spin_lock_irqsave(&tp->lock, flags);
1500 memcpy_fromio(p, tp->mmio_addr, regs->len);
1501 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1502}
1503
b57b7e5a
SH		 1504static u32 rtl8169_get_msglevel(struct net_device *dev)
1505{
1506 struct rtl8169_private *tp = netdev_priv(dev);
1507
1508 return tp->msg_enable;
1509}
1510
1511static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1512{
1513 struct rtl8169_private *tp = netdev_priv(dev);
1514
1515 tp->msg_enable = value;
1516}
1517
d4a3a0fc
SH		 1518static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1519 "tx_packets",
1520 "rx_packets",
1521 "tx_errors",
1522 "rx_errors",
1523 "rx_missed",
1524 "align_errors",
1525 "tx_single_collisions",
1526 "tx_multi_collisions",
1527 "unicast",
1528 "broadcast",
1529 "multicast",
1530 "tx_aborted",
1531 "tx_underrun",
1532};
1533
b9f2c044 1534static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1535{
b9f2c044
JG		 1536 switch (sset) {
1537 case ETH_SS_STATS:
1538 return ARRAY_SIZE(rtl8169_gstrings);
1539 default:
1540 return -EOPNOTSUPP;
1541 }
d4a3a0fc
SH		 1542}
1543
355423d0 1544static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1545{
1546 struct rtl8169_private *tp = netdev_priv(dev);
1547 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1548 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1549 struct rtl8169_counters *counters;
1550 dma_addr_t paddr;
1551 u32 cmd;
355423d0 1552 int wait = 1000;
d4a3a0fc 1553
355423d0
IV		 1554 /*
1555 * Some chips are unable to dump tally counters when the receiver
1556 * is disabled.
1557 */
1558 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1559 return;
d4a3a0fc 1560
48addcc9 1561 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1562 if (!counters)
1563 return;
1564
1565 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1566 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1567 RTL_W32(CounterAddrLow, cmd);
1568 RTL_W32(CounterAddrLow, cmd | CounterDump);
1569
355423d0
IV		 1570 while (wait--) {
1571 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1572 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1573 break;
355423d0
IV		 1574 }
1575 udelay(10);
d4a3a0fc
SH		 1576 }
1577
1578 RTL_W32(CounterAddrLow, 0);
1579 RTL_W32(CounterAddrHigh, 0);
1580
48addcc9 1581 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1582}
1583
355423d0
IV		 1584static void rtl8169_get_ethtool_stats(struct net_device *dev,
1585 struct ethtool_stats *stats, u64 *data)
1586{
1587 struct rtl8169_private *tp = netdev_priv(dev);
1588
1589 ASSERT_RTNL();
1590
1591 rtl8169_update_counters(dev);
1592
1593 data[0] = le64_to_cpu(tp->counters.tx_packets);
1594 data[1] = le64_to_cpu(tp->counters.rx_packets);
1595 data[2] = le64_to_cpu(tp->counters.tx_errors);
1596 data[3] = le32_to_cpu(tp->counters.rx_errors);
1597 data[4] = le16_to_cpu(tp->counters.rx_missed);
1598 data[5] = le16_to_cpu(tp->counters.align_errors);
1599 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1600 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1601 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1602 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1603 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1604 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1605 data[12] = le16_to_cpu(tp->counters.tx_underun);
1606}
1607
d4a3a0fc
SH		 1608static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1609{
1610 switch(stringset) {
1611 case ETH_SS_STATS:
1612 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1613 break;
1614 }
1615}
1616
7282d491 1617static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1618 .get_drvinfo = rtl8169_get_drvinfo,
1619 .get_regs_len = rtl8169_get_regs_len,
1620 .get_link = ethtool_op_get_link,
1621 .get_settings = rtl8169_get_settings,
1622 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1623 .get_msglevel = rtl8169_get_msglevel,
1624 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1625 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1626 .get_wol = rtl8169_get_wol,
1627 .set_wol = rtl8169_set_wol,
d4a3a0fc 1628 .get_strings = rtl8169_get_strings,
b9f2c044 1629 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1630 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1631};
1632
07d3f51f 1633static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1634 struct net_device *dev, u8 default_version)
1da177e4 1635{
5d320a20 1636 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1637 /*
1638 * The driver currently handles the 8168Bf and the 8168Be identically
1639 * but they can be identified more specifically through the test below
1640 * if needed:
1641 *
1642 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1643 *
1644 * Same thing for the 8101Eb and the 8101Ec:
1645 *
1646 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1647 */
3744100e 1648 static const struct rtl_mac_info {
1da177e4 1649 u32 mask;
e3cf0cc0 1650 u32 val;
1da177e4
LT		 1651 int mac_version;
1652 } mac_info[] = {
01dc7fec 1653 /* 8168E family. */
1654 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1655 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1656 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1657
5b538df9 1658 /* 8168D family. */
daf9df6d 1659 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1660 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1661 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1662
e6de30d6 1663 /* 8168DP family. */
1664 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1665 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1666 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1667
ef808d50 1668 /* 8168C family. */
17c99297 1669 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1670 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1671 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1672 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1673 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1674 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1675 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1676 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1677 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1678
1679 /* 8168B family. */
1680 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1681 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1682 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1683 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1684
1685 /* 8101 family. */
36a0e6c2 1686 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1687 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1688 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1689 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1690 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1691 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1692 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1693 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1694 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1695 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1696 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1697 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1698 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1699 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1700 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1701 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1702 /* FIXME: where did these entries come from ? -- FR */
1703 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1704 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1705
1706 /* 8110 family. */
1707 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1708 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1709 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1710 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1711 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1712 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1713
f21b75e9
JD		 1714 /* Catch-all */
1715 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1716 };
1717 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1718 u32 reg;
1719
e3cf0cc0
FR		 1720 reg = RTL_R32(TxConfig);
1721 while ((reg & p->mask) != p->val)
1da177e4
LT		 1722 p++;
1723 tp->mac_version = p->mac_version;
5d320a20
FR		 1724
1725 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1726 netif_notice(tp, probe, dev,
1727 "unknown MAC, using family default\n");
1728 tp->mac_version = default_version;
1729 }
1da177e4
LT		 1730}
1731
1732static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1733{
bcf0bf90 1734 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1735}
1736
867763c1
FR		 1737struct phy_reg {
1738 u16 reg;
1739 u16 val;
1740};
1741
4da19633 1742static void rtl_writephy_batch(struct rtl8169_private *tp,
1743 const struct phy_reg *regs, int len)
867763c1
FR		 1744{
1745 while (len-- > 0) {
4da19633 1746 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1747 regs++;
1748 }
1749}
1750
bca03d5f 1751#define PHY_READ 0x00000000
1752#define PHY_DATA_OR 0x10000000
1753#define PHY_DATA_AND 0x20000000
1754#define PHY_BJMPN 0x30000000
1755#define PHY_READ_EFUSE 0x40000000
1756#define PHY_READ_MAC_BYTE 0x50000000
1757#define PHY_WRITE_MAC_BYTE 0x60000000
1758#define PHY_CLEAR_READCOUNT 0x70000000
1759#define PHY_WRITE 0x80000000
1760#define PHY_READCOUNT_EQ_SKIP 0x90000000
1761#define PHY_COMP_EQ_SKIPN 0xa0000000
1762#define PHY_COMP_NEQ_SKIPN 0xb0000000
1763#define PHY_WRITE_PREVIOUS 0xc0000000
1764#define PHY_SKIPN 0xd0000000
1765#define PHY_DELAY_MS 0xe0000000
1766#define PHY_WRITE_ERI_WORD 0xf0000000
1767
960aee6c
HW		 1768struct fw_info {
1769 u32 magic;
1770 char version[RTL_VER_SIZE];
1771 __le32 fw_start;
1772 __le32 fw_len;
1773 u8 chksum;
1774} __packed;
1775
1c361efb
FR		 1776#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1777
1778static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1779{
b6ffd97f 1780 const struct firmware *fw = rtl_fw->fw;
960aee6c 1781 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1782 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1783 char *version = rtl_fw->version;
1784 bool rc = false;
1785
1786 if (fw->size < FW_OPCODE_SIZE)
1787 goto out;
960aee6c
HW		 1788
1789 if (!fw_info->magic) {
1790 size_t i, size, start;
1791 u8 checksum = 0;
1792
1793 if (fw->size < sizeof(*fw_info))
1794 goto out;
1795
1796 for (i = 0; i < fw->size; i++)
1797 checksum += fw->data[i];
1798 if (checksum != 0)
1799 goto out;
1800
1801 start = le32_to_cpu(fw_info->fw_start);
1802 if (start > fw->size)
1803 goto out;
1804
1805 size = le32_to_cpu(fw_info->fw_len);
1806 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1807 goto out;
1808
1809 memcpy(version, fw_info->version, RTL_VER_SIZE);
1810
1811 pa->code = (__le32 *)(fw->data + start);
1812 pa->size = size;
1813 } else {
1c361efb
FR		 1814 if (fw->size % FW_OPCODE_SIZE)
1815 goto out;
1816
1817 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1818
1819 pa->code = (__le32 *)fw->data;
1820 pa->size = fw->size / FW_OPCODE_SIZE;
1821 }
1822 version[RTL_VER_SIZE - 1] = 0;
1823
1824 rc = true;
1825out:
1826 return rc;
1827}
1828
fd112f2e
FR		 1829static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1830 struct rtl_fw_phy_action *pa)
1c361efb 1831{
fd112f2e 1832 bool rc = false;
1c361efb 1833 size_t index;
bca03d5f 1834
1c361efb
FR		 1835 for (index = 0; index < pa->size; index++) {
1836 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 1837 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1838
42b82dc1 1839 switch(action & 0xf0000000) {
1840 case PHY_READ:
1841 case PHY_DATA_OR:
1842 case PHY_DATA_AND:
1843 case PHY_READ_EFUSE:
1844 case PHY_CLEAR_READCOUNT:
1845 case PHY_WRITE:
1846 case PHY_WRITE_PREVIOUS:
1847 case PHY_DELAY_MS:
1848 break;
1849
1850 case PHY_BJMPN:
1851 if (regno > index) {
fd112f2e 1852 netif_err(tp, ifup, tp->dev,
cecb5fd7 1853 "Out of range of firmware\n");
fd112f2e 1854 goto out;
42b82dc1 1855 }
1856 break;
1857 case PHY_READCOUNT_EQ_SKIP:
1c361efb 1858 if (index + 2 >= pa->size) {
fd112f2e 1859 netif_err(tp, ifup, tp->dev,
cecb5fd7 1860 "Out of range of firmware\n");
fd112f2e 1861 goto out;
42b82dc1 1862 }
1863 break;
1864 case PHY_COMP_EQ_SKIPN:
1865 case PHY_COMP_NEQ_SKIPN:
1866 case PHY_SKIPN:
1c361efb 1867 if (index + 1 + regno >= pa->size) {
fd112f2e 1868 netif_err(tp, ifup, tp->dev,
cecb5fd7 1869 "Out of range of firmware\n");
fd112f2e 1870 goto out;
42b82dc1 1871 }
bca03d5f 1872 break;
1873
42b82dc1 1874 case PHY_READ_MAC_BYTE:
1875 case PHY_WRITE_MAC_BYTE:
1876 case PHY_WRITE_ERI_WORD:
1877 default:
fd112f2e 1878 netif_err(tp, ifup, tp->dev,
42b82dc1 1879 "Invalid action 0x%08x\n", action);
fd112f2e 1880 goto out;
bca03d5f 1881 }
1882 }
fd112f2e
FR		 1883 rc = true;
1884out:
1885 return rc;
1886}
bca03d5f 1887
fd112f2e
FR		 1888static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1889{
1890 struct net_device *dev = tp->dev;
1891 int rc = -EINVAL;
1892
1893 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1894 netif_err(tp, ifup, dev, "invalid firwmare\n");
1895 goto out;
1896 }
1897
1898 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1899 rc = 0;
1900out:
1901 return rc;
1902}
1903
1904static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1905{
1906 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1907 u32 predata, count;
1908 size_t index;
1909
1910 predata = count = 0;
42b82dc1 1911
1c361efb
FR		 1912 for (index = 0; index < pa->size; ) {
1913 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 1914 u32 data = action & 0x0000ffff;
42b82dc1 1915 u32 regno = (action & 0x0fff0000) >> 16;
1916
1917 if (!action)
1918 break;
bca03d5f 1919
1920 switch(action & 0xf0000000) {
42b82dc1 1921 case PHY_READ:
1922 predata = rtl_readphy(tp, regno);
1923 count++;
1924 index++;
1925 break;
1926 case PHY_DATA_OR:
1927 predata |= data;
1928 index++;
1929 break;
1930 case PHY_DATA_AND:
1931 predata &= data;
1932 index++;
1933 break;
1934 case PHY_BJMPN:
1935 index -= regno;
1936 break;
1937 case PHY_READ_EFUSE:
1938 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1939 index++;
1940 break;
1941 case PHY_CLEAR_READCOUNT:
1942 count = 0;
1943 index++;
1944 break;
bca03d5f 1945 case PHY_WRITE:
42b82dc1 1946 rtl_writephy(tp, regno, data);
1947 index++;
1948 break;
1949 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 1950 index += (count == data) ? 2 : 1;
bca03d5f 1951 break;
42b82dc1 1952 case PHY_COMP_EQ_SKIPN:
1953 if (predata == data)
1954 index += regno;
1955 index++;
1956 break;
1957 case PHY_COMP_NEQ_SKIPN:
1958 if (predata != data)
1959 index += regno;
1960 index++;
1961 break;
1962 case PHY_WRITE_PREVIOUS:
1963 rtl_writephy(tp, regno, predata);
1964 index++;
1965 break;
1966 case PHY_SKIPN:
1967 index += regno + 1;
1968 break;
1969 case PHY_DELAY_MS:
1970 mdelay(data);
1971 index++;
1972 break;
1973
1974 case PHY_READ_MAC_BYTE:
1975 case PHY_WRITE_MAC_BYTE:
1976 case PHY_WRITE_ERI_WORD:
bca03d5f 1977 default:
1978 BUG();
1979 }
1980 }
1981}
1982
f1e02ed1 1983static void rtl_release_firmware(struct rtl8169_private *tp)
1984{
b6ffd97f
FR		 1985 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1986 release_firmware(tp->rtl_fw->fw);
1987 kfree(tp->rtl_fw);
1988 }
1989 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1990}
1991
953a12cc 1992static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1993{
b6ffd97f 1994 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 1995
1996 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 1997 if (!IS_ERR_OR_NULL(rtl_fw))
1998 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 1999}
2000
2001static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2002{
2003 if (rtl_readphy(tp, reg) != val)
2004 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2005 else
2006 rtl_apply_firmware(tp);
f1e02ed1 2007}
2008
4da19633 2009static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2010{
350f7596 2011 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2012 { 0x1f, 0x0001 },
2013 { 0x06, 0x006e },
2014 { 0x08, 0x0708 },
2015 { 0x15, 0x4000 },
2016 { 0x18, 0x65c7 },
1da177e4 2017
0b9b571d 2018 { 0x1f, 0x0001 },
2019 { 0x03, 0x00a1 },
2020 { 0x02, 0x0008 },
2021 { 0x01, 0x0120 },
2022 { 0x00, 0x1000 },
2023 { 0x04, 0x0800 },
2024 { 0x04, 0x0000 },
1da177e4 2025
0b9b571d 2026 { 0x03, 0xff41 },
2027 { 0x02, 0xdf60 },
2028 { 0x01, 0x0140 },
2029 { 0x00, 0x0077 },
2030 { 0x04, 0x7800 },
2031 { 0x04, 0x7000 },
2032
2033 { 0x03, 0x802f },
2034 { 0x02, 0x4f02 },
2035 { 0x01, 0x0409 },
2036 { 0x00, 0xf0f9 },
2037 { 0x04, 0x9800 },
2038 { 0x04, 0x9000 },
2039
2040 { 0x03, 0xdf01 },
2041 { 0x02, 0xdf20 },
2042 { 0x01, 0xff95 },
2043 { 0x00, 0xba00 },
2044 { 0x04, 0xa800 },
2045 { 0x04, 0xa000 },
2046
2047 { 0x03, 0xff41 },
2048 { 0x02, 0xdf20 },
2049 { 0x01, 0x0140 },
2050 { 0x00, 0x00bb },
2051 { 0x04, 0xb800 },
2052 { 0x04, 0xb000 },
2053
2054 { 0x03, 0xdf41 },
2055 { 0x02, 0xdc60 },
2056 { 0x01, 0x6340 },
2057 { 0x00, 0x007d },
2058 { 0x04, 0xd800 },
2059 { 0x04, 0xd000 },
2060
2061 { 0x03, 0xdf01 },
2062 { 0x02, 0xdf20 },
2063 { 0x01, 0x100a },
2064 { 0x00, 0xa0ff },
2065 { 0x04, 0xf800 },
2066 { 0x04, 0xf000 },
2067
2068 { 0x1f, 0x0000 },
2069 { 0x0b, 0x0000 },
2070 { 0x00, 0x9200 }
2071 };
1da177e4 2072
4da19633 2073 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2074}
2075
4da19633 2076static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2077{
350f7596 2078 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2079 { 0x1f, 0x0002 },
2080 { 0x01, 0x90d0 },
2081 { 0x1f, 0x0000 }
2082 };
2083
4da19633 2084 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2085}
2086
4da19633 2087static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2088{
2089 struct pci_dev *pdev = tp->pci_dev;
2090 u16 vendor_id, device_id;
2091
2092 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2093 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2094
2095 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2096 return;
2097
4da19633 2098 rtl_writephy(tp, 0x1f, 0x0001);
2099 rtl_writephy(tp, 0x10, 0xf01b);
2100 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2101}
2102
4da19633 2103static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2104{
350f7596 2105 static const struct phy_reg phy_reg_init[] = {
2e955856 2106 { 0x1f, 0x0001 },
2107 { 0x04, 0x0000 },
2108 { 0x03, 0x00a1 },
2109 { 0x02, 0x0008 },
2110 { 0x01, 0x0120 },
2111 { 0x00, 0x1000 },
2112 { 0x04, 0x0800 },
2113 { 0x04, 0x9000 },
2114 { 0x03, 0x802f },
2115 { 0x02, 0x4f02 },
2116 { 0x01, 0x0409 },
2117 { 0x00, 0xf099 },
2118 { 0x04, 0x9800 },
2119 { 0x04, 0xa000 },
2120 { 0x03, 0xdf01 },
2121 { 0x02, 0xdf20 },
2122 { 0x01, 0xff95 },
2123 { 0x00, 0xba00 },
2124 { 0x04, 0xa800 },
2125 { 0x04, 0xf000 },
2126 { 0x03, 0xdf01 },
2127 { 0x02, 0xdf20 },
2128 { 0x01, 0x101a },
2129 { 0x00, 0xa0ff },
2130 { 0x04, 0xf800 },
2131 { 0x04, 0x0000 },
2132 { 0x1f, 0x0000 },
2133
2134 { 0x1f, 0x0001 },
2135 { 0x10, 0xf41b },
2136 { 0x14, 0xfb54 },
2137 { 0x18, 0xf5c7 },
2138 { 0x1f, 0x0000 },
2139
2140 { 0x1f, 0x0001 },
2141 { 0x17, 0x0cc0 },
2142 { 0x1f, 0x0000 }
2143 };
2144
4da19633 2145 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2146
4da19633 2147 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2148}
2149
4da19633 2150static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2151{
350f7596 2152 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2153 { 0x1f, 0x0001 },
2154 { 0x04, 0x0000 },
2155 { 0x03, 0x00a1 },
2156 { 0x02, 0x0008 },
2157 { 0x01, 0x0120 },
2158 { 0x00, 0x1000 },
2159 { 0x04, 0x0800 },
2160 { 0x04, 0x9000 },
2161 { 0x03, 0x802f },
2162 { 0x02, 0x4f02 },
2163 { 0x01, 0x0409 },
2164 { 0x00, 0xf099 },
2165 { 0x04, 0x9800 },
2166 { 0x04, 0xa000 },
2167 { 0x03, 0xdf01 },
2168 { 0x02, 0xdf20 },
2169 { 0x01, 0xff95 },
2170 { 0x00, 0xba00 },
2171 { 0x04, 0xa800 },
2172 { 0x04, 0xf000 },
2173 { 0x03, 0xdf01 },
2174 { 0x02, 0xdf20 },
2175 { 0x01, 0x101a },
2176 { 0x00, 0xa0ff },
2177 { 0x04, 0xf800 },
2178 { 0x04, 0x0000 },
2179 { 0x1f, 0x0000 },
2180
2181 { 0x1f, 0x0001 },
2182 { 0x0b, 0x8480 },
2183 { 0x1f, 0x0000 },
2184
2185 { 0x1f, 0x0001 },
2186 { 0x18, 0x67c7 },
2187 { 0x04, 0x2000 },
2188 { 0x03, 0x002f },
2189 { 0x02, 0x4360 },
2190 { 0x01, 0x0109 },
2191 { 0x00, 0x3022 },
2192 { 0x04, 0x2800 },
2193 { 0x1f, 0x0000 },
2194
2195 { 0x1f, 0x0001 },
2196 { 0x17, 0x0cc0 },
2197 { 0x1f, 0x0000 }
2198 };
2199
4da19633 2200 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2201}
2202
4da19633 2203static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2204{
350f7596 2205 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2206 { 0x10, 0xf41b },
2207 { 0x1f, 0x0000 }
2208 };
2209
4da19633 2210 rtl_writephy(tp, 0x1f, 0x0001);
2211 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2212
4da19633 2213 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2214}
2215
4da19633 2216static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2217{
350f7596 2218 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2219 { 0x1f, 0x0001 },
2220 { 0x10, 0xf41b },
2221 { 0x1f, 0x0000 }
2222 };
2223
4da19633 2224 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2225}
2226
4da19633 2227static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2228{
350f7596 2229 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2230 { 0x1f, 0x0000 },
2231 { 0x1d, 0x0f00 },
2232 { 0x1f, 0x0002 },
2233 { 0x0c, 0x1ec8 },
2234 { 0x1f, 0x0000 }
2235 };
2236
4da19633 2237 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2238}
2239
4da19633 2240static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2241{
350f7596 2242 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2243 { 0x1f, 0x0001 },
2244 { 0x1d, 0x3d98 },
2245 { 0x1f, 0x0000 }
2246 };
2247
4da19633 2248 rtl_writephy(tp, 0x1f, 0x0000);
2249 rtl_patchphy(tp, 0x14, 1 << 5);
2250 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2251
4da19633 2252 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2253}
2254
4da19633 2255static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2256{
350f7596 2257 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2258 { 0x1f, 0x0001 },
2259 { 0x12, 0x2300 },
867763c1
FR		 2260 { 0x1f, 0x0002 },
2261 { 0x00, 0x88d4 },
2262 { 0x01, 0x82b1 },
2263 { 0x03, 0x7002 },
2264 { 0x08, 0x9e30 },
2265 { 0x09, 0x01f0 },
2266 { 0x0a, 0x5500 },
2267 { 0x0c, 0x00c8 },
2268 { 0x1f, 0x0003 },
2269 { 0x12, 0xc096 },
2270 { 0x16, 0x000a },
f50d4275
FR		 2271 { 0x1f, 0x0000 },
2272 { 0x1f, 0x0000 },
2273 { 0x09, 0x2000 },
2274 { 0x09, 0x0000 }
867763c1
FR		 2275 };
2276
4da19633 2277 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2278
4da19633 2279 rtl_patchphy(tp, 0x14, 1 << 5);
2280 rtl_patchphy(tp, 0x0d, 1 << 5);
2281 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2282}
2283
4da19633 2284static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2285{
350f7596 2286 static const struct phy_reg phy_reg_init[] = {
f50d4275 2287 { 0x1f, 0x0001 },
7da97ec9 2288 { 0x12, 0x2300 },
f50d4275
FR		 2289 { 0x03, 0x802f },
2290 { 0x02, 0x4f02 },
2291 { 0x01, 0x0409 },
2292 { 0x00, 0xf099 },
2293 { 0x04, 0x9800 },
2294 { 0x04, 0x9000 },
2295 { 0x1d, 0x3d98 },
7da97ec9
FR		 2296 { 0x1f, 0x0002 },
2297 { 0x0c, 0x7eb8 },
f50d4275
FR		 2298 { 0x06, 0x0761 },
2299 { 0x1f, 0x0003 },
2300 { 0x16, 0x0f0a },
7da97ec9
FR		 2301 { 0x1f, 0x0000 }
2302 };
2303
4da19633 2304 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2305
4da19633 2306 rtl_patchphy(tp, 0x16, 1 << 0);
2307 rtl_patchphy(tp, 0x14, 1 << 5);
2308 rtl_patchphy(tp, 0x0d, 1 << 5);
2309 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2310}
2311
4da19633 2312static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2313{
350f7596 2314 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2315 { 0x1f, 0x0001 },
2316 { 0x12, 0x2300 },
2317 { 0x1d, 0x3d98 },
2318 { 0x1f, 0x0002 },
2319 { 0x0c, 0x7eb8 },
2320 { 0x06, 0x5461 },
2321 { 0x1f, 0x0003 },
2322 { 0x16, 0x0f0a },
2323 { 0x1f, 0x0000 }
2324 };
2325
4da19633 2326 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2327
4da19633 2328 rtl_patchphy(tp, 0x16, 1 << 0);
2329 rtl_patchphy(tp, 0x14, 1 << 5);
2330 rtl_patchphy(tp, 0x0d, 1 << 5);
2331 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2332}
2333
4da19633 2334static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2335{
4da19633 2336 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2337}
2338
bca03d5f 2339static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2340{
350f7596 2341 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2342 /* Channel Estimation */
5b538df9 2343 { 0x1f, 0x0001 },
daf9df6d 2344 { 0x06, 0x4064 },
2345 { 0x07, 0x2863 },
2346 { 0x08, 0x059c },
2347 { 0x09, 0x26b4 },
2348 { 0x0a, 0x6a19 },
2349 { 0x0b, 0xdcc8 },
2350 { 0x10, 0xf06d },
2351 { 0x14, 0x7f68 },
2352 { 0x18, 0x7fd9 },
2353 { 0x1c, 0xf0ff },
2354 { 0x1d, 0x3d9c },
5b538df9 2355 { 0x1f, 0x0003 },
daf9df6d 2356 { 0x12, 0xf49f },
2357 { 0x13, 0x070b },
2358 { 0x1a, 0x05ad },
bca03d5f 2359 { 0x14, 0x94c0 },
2360
2361 /*
2362 * Tx Error Issue
cecb5fd7 2363 * Enhance line driver power
bca03d5f 2364 */
5b538df9 2365 { 0x1f, 0x0002 },
daf9df6d 2366 { 0x06, 0x5561 },
2367 { 0x1f, 0x0005 },
2368 { 0x05, 0x8332 },
bca03d5f 2369 { 0x06, 0x5561 },
2370
2371 /*
2372 * Can not link to 1Gbps with bad cable
2373 * Decrease SNR threshold form 21.07dB to 19.04dB
2374 */
2375 { 0x1f, 0x0001 },
2376 { 0x17, 0x0cc0 },
daf9df6d 2377
5b538df9 2378 { 0x1f, 0x0000 },
bca03d5f 2379 { 0x0d, 0xf880 }
daf9df6d 2380 };
bca03d5f 2381 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2382
4da19633 2383 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2384
bca03d5f 2385 /*
2386 * Rx Error Issue
2387 * Fine Tune Switching regulator parameter
2388 */
4da19633 2389 rtl_writephy(tp, 0x1f, 0x0002);
2390 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2391 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2392
daf9df6d 2393 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2394 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2395 { 0x1f, 0x0002 },
2396 { 0x05, 0x669a },
2397 { 0x1f, 0x0005 },
2398 { 0x05, 0x8330 },
2399 { 0x06, 0x669a },
2400 { 0x1f, 0x0002 }
2401 };
2402 int val;
2403
4da19633 2404 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2405
4da19633 2406 val = rtl_readphy(tp, 0x0d);
daf9df6d 2407
2408 if ((val & 0x00ff) != 0x006c) {
350f7596 2409 static const u32 set[] = {
daf9df6d 2410 0x0065, 0x0066, 0x0067, 0x0068,
2411 0x0069, 0x006a, 0x006b, 0x006c
2412 };
2413 int i;
2414
4da19633 2415 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2416
2417 val &= 0xff00;
2418 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2419 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2420 }
2421 } else {
350f7596 2422 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2423 { 0x1f, 0x0002 },
2424 { 0x05, 0x6662 },
2425 { 0x1f, 0x0005 },
2426 { 0x05, 0x8330 },
2427 { 0x06, 0x6662 }
2428 };
2429
4da19633 2430 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2431 }
2432
bca03d5f 2433 /* RSET couple improve */
4da19633 2434 rtl_writephy(tp, 0x1f, 0x0002);
2435 rtl_patchphy(tp, 0x0d, 0x0300);
2436 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2437
bca03d5f 2438 /* Fine tune PLL performance */
4da19633 2439 rtl_writephy(tp, 0x1f, 0x0002);
2440 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2441 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2442
4da19633 2443 rtl_writephy(tp, 0x1f, 0x0005);
2444 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2445
2446 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2447
4da19633 2448 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2449}
2450
bca03d5f 2451static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2452{
350f7596 2453 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2454 /* Channel Estimation */
daf9df6d 2455 { 0x1f, 0x0001 },
2456 { 0x06, 0x4064 },
2457 { 0x07, 0x2863 },
2458 { 0x08, 0x059c },
2459 { 0x09, 0x26b4 },
2460 { 0x0a, 0x6a19 },
2461 { 0x0b, 0xdcc8 },
2462 { 0x10, 0xf06d },
2463 { 0x14, 0x7f68 },
2464 { 0x18, 0x7fd9 },
2465 { 0x1c, 0xf0ff },
2466 { 0x1d, 0x3d9c },
2467 { 0x1f, 0x0003 },
2468 { 0x12, 0xf49f },
2469 { 0x13, 0x070b },
2470 { 0x1a, 0x05ad },
2471 { 0x14, 0x94c0 },
2472
bca03d5f 2473 /*
2474 * Tx Error Issue
cecb5fd7 2475 * Enhance line driver power
bca03d5f 2476 */
daf9df6d 2477 { 0x1f, 0x0002 },
2478 { 0x06, 0x5561 },
2479 { 0x1f, 0x0005 },
2480 { 0x05, 0x8332 },
bca03d5f 2481 { 0x06, 0x5561 },
2482
2483 /*
2484 * Can not link to 1Gbps with bad cable
2485 * Decrease SNR threshold form 21.07dB to 19.04dB
2486 */
2487 { 0x1f, 0x0001 },
2488 { 0x17, 0x0cc0 },
daf9df6d 2489
2490 { 0x1f, 0x0000 },
bca03d5f 2491 { 0x0d, 0xf880 }
5b538df9 2492 };
bca03d5f 2493 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2494
4da19633 2495 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2496
daf9df6d 2497 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2498 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2499 { 0x1f, 0x0002 },
2500 { 0x05, 0x669a },
5b538df9 2501 { 0x1f, 0x0005 },
daf9df6d 2502 { 0x05, 0x8330 },
2503 { 0x06, 0x669a },
2504
2505 { 0x1f, 0x0002 }
2506 };
2507 int val;
2508
4da19633 2509 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2510
4da19633 2511 val = rtl_readphy(tp, 0x0d);
daf9df6d 2512 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2513 static const u32 set[] = {
daf9df6d 2514 0x0065, 0x0066, 0x0067, 0x0068,
2515 0x0069, 0x006a, 0x006b, 0x006c
2516 };
2517 int i;
2518
4da19633 2519 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2520
2521 val &= 0xff00;
2522 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2523 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2524 }
2525 } else {
350f7596 2526 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2527 { 0x1f, 0x0002 },
2528 { 0x05, 0x2642 },
5b538df9 2529 { 0x1f, 0x0005 },
daf9df6d 2530 { 0x05, 0x8330 },
2531 { 0x06, 0x2642 }
5b538df9
FR		 2532 };
2533
4da19633 2534 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2535 }
2536
bca03d5f 2537 /* Fine tune PLL performance */
4da19633 2538 rtl_writephy(tp, 0x1f, 0x0002);
2539 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2540 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2541
bca03d5f 2542 /* Switching regulator Slew rate */
4da19633 2543 rtl_writephy(tp, 0x1f, 0x0002);
2544 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2545
4da19633 2546 rtl_writephy(tp, 0x1f, 0x0005);
2547 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2548
2549 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2550
4da19633 2551 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2552}
2553
4da19633 2554static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2555{
350f7596 2556 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2557 { 0x1f, 0x0002 },
2558 { 0x10, 0x0008 },
2559 { 0x0d, 0x006c },
2560
2561 { 0x1f, 0x0000 },
2562 { 0x0d, 0xf880 },
2563
2564 { 0x1f, 0x0001 },
2565 { 0x17, 0x0cc0 },
2566
2567 { 0x1f, 0x0001 },
2568 { 0x0b, 0xa4d8 },
2569 { 0x09, 0x281c },
2570 { 0x07, 0x2883 },
2571 { 0x0a, 0x6b35 },
2572 { 0x1d, 0x3da4 },
2573 { 0x1c, 0xeffd },
2574 { 0x14, 0x7f52 },
2575 { 0x18, 0x7fc6 },
2576 { 0x08, 0x0601 },
2577 { 0x06, 0x4063 },
2578 { 0x10, 0xf074 },
2579 { 0x1f, 0x0003 },
2580 { 0x13, 0x0789 },
2581 { 0x12, 0xf4bd },
2582 { 0x1a, 0x04fd },
2583 { 0x14, 0x84b0 },
2584 { 0x1f, 0x0000 },
2585 { 0x00, 0x9200 },
2586
2587 { 0x1f, 0x0005 },
2588 { 0x01, 0x0340 },
2589 { 0x1f, 0x0001 },
2590 { 0x04, 0x4000 },
2591 { 0x03, 0x1d21 },
2592 { 0x02, 0x0c32 },
2593 { 0x01, 0x0200 },
2594 { 0x00, 0x5554 },
2595 { 0x04, 0x4800 },
2596 { 0x04, 0x4000 },
2597 { 0x04, 0xf000 },
2598 { 0x03, 0xdf01 },
2599 { 0x02, 0xdf20 },
2600 { 0x01, 0x101a },
2601 { 0x00, 0xa0ff },
2602 { 0x04, 0xf800 },
2603 { 0x04, 0xf000 },
2604 { 0x1f, 0x0000 },
2605
2606 { 0x1f, 0x0007 },
2607 { 0x1e, 0x0023 },
2608 { 0x16, 0x0000 },
2609 { 0x1f, 0x0000 }
2610 };
2611
4da19633 2612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2613}
2614
e6de30d6 2615static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2616{
2617 static const struct phy_reg phy_reg_init[] = {
2618 { 0x1f, 0x0001 },
2619 { 0x17, 0x0cc0 },
2620
2621 { 0x1f, 0x0007 },
2622 { 0x1e, 0x002d },
2623 { 0x18, 0x0040 },
2624 { 0x1f, 0x0000 }
2625 };
2626
2627 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2628 rtl_patchphy(tp, 0x0d, 1 << 5);
2629}
2630
01dc7fec 2631static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2632{
2633 static const struct phy_reg phy_reg_init[] = {
2634 /* Enable Delay cap */
2635 { 0x1f, 0x0005 },
2636 { 0x05, 0x8b80 },
2637 { 0x06, 0xc896 },
2638 { 0x1f, 0x0000 },
2639
2640 /* Channel estimation fine tune */
2641 { 0x1f, 0x0001 },
2642 { 0x0b, 0x6c20 },
2643 { 0x07, 0x2872 },
2644 { 0x1c, 0xefff },
2645 { 0x1f, 0x0003 },
2646 { 0x14, 0x6420 },
2647 { 0x1f, 0x0000 },
2648
2649 /* Update PFM & 10M TX idle timer */
2650 { 0x1f, 0x0007 },
2651 { 0x1e, 0x002f },
2652 { 0x15, 0x1919 },
2653 { 0x1f, 0x0000 },
2654
2655 { 0x1f, 0x0007 },
2656 { 0x1e, 0x00ac },
2657 { 0x18, 0x0006 },
2658 { 0x1f, 0x0000 }
2659 };
2660
15ecd039
FR		 2661 rtl_apply_firmware(tp);
2662
01dc7fec 2663 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2664
2665 /* DCO enable for 10M IDLE Power */
2666 rtl_writephy(tp, 0x1f, 0x0007);
2667 rtl_writephy(tp, 0x1e, 0x0023);
2668 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2669 rtl_writephy(tp, 0x1f, 0x0000);
2670
2671 /* For impedance matching */
2672 rtl_writephy(tp, 0x1f, 0x0002);
2673 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2674 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2675
2676 /* PHY auto speed down */
2677 rtl_writephy(tp, 0x1f, 0x0007);
2678 rtl_writephy(tp, 0x1e, 0x002d);
2679 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2680 rtl_writephy(tp, 0x1f, 0x0000);
2681 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2682
2683 rtl_writephy(tp, 0x1f, 0x0005);
2684 rtl_writephy(tp, 0x05, 0x8b86);
2685 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2686 rtl_writephy(tp, 0x1f, 0x0000);
2687
2688 rtl_writephy(tp, 0x1f, 0x0005);
2689 rtl_writephy(tp, 0x05, 0x8b85);
2690 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2691 rtl_writephy(tp, 0x1f, 0x0007);
2692 rtl_writephy(tp, 0x1e, 0x0020);
2693 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2694 rtl_writephy(tp, 0x1f, 0x0006);
2695 rtl_writephy(tp, 0x00, 0x5a00);
2696 rtl_writephy(tp, 0x1f, 0x0000);
2697 rtl_writephy(tp, 0x0d, 0x0007);
2698 rtl_writephy(tp, 0x0e, 0x003c);
2699 rtl_writephy(tp, 0x0d, 0x4007);
2700 rtl_writephy(tp, 0x0e, 0x0000);
2701 rtl_writephy(tp, 0x0d, 0x0000);
2702}
2703
4da19633 2704static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2705{
350f7596 2706 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2707 { 0x1f, 0x0003 },
2708 { 0x08, 0x441d },
2709 { 0x01, 0x9100 },
2710 { 0x1f, 0x0000 }
2711 };
2712
4da19633 2713 rtl_writephy(tp, 0x1f, 0x0000);
2714 rtl_patchphy(tp, 0x11, 1 << 12);
2715 rtl_patchphy(tp, 0x19, 1 << 13);
2716 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2717
4da19633 2718 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2719}
2720
5a5e4443
HW		 2721static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2722{
2723 static const struct phy_reg phy_reg_init[] = {
2724 { 0x1f, 0x0005 },
2725 { 0x1a, 0x0000 },
2726 { 0x1f, 0x0000 },
2727
2728 { 0x1f, 0x0004 },
2729 { 0x1c, 0x0000 },
2730 { 0x1f, 0x0000 },
2731
2732 { 0x1f, 0x0001 },
2733 { 0x15, 0x7701 },
2734 { 0x1f, 0x0000 }
2735 };
2736
2737 /* Disable ALDPS before ram code */
2738 rtl_writephy(tp, 0x1f, 0x0000);
2739 rtl_writephy(tp, 0x18, 0x0310);
2740 msleep(100);
2741
953a12cc 2742 rtl_apply_firmware(tp);
5a5e4443
HW		 2743
2744 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2745}
2746
5615d9f1
FR		 2747static void rtl_hw_phy_config(struct net_device *dev)
2748{
2749 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2750
2751 rtl8169_print_mac_version(tp);
2752
2753 switch (tp->mac_version) {
2754 case RTL_GIGA_MAC_VER_01:
2755 break;
2756 case RTL_GIGA_MAC_VER_02:
2757 case RTL_GIGA_MAC_VER_03:
4da19633 2758 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2759 break;
2760 case RTL_GIGA_MAC_VER_04:
4da19633 2761 rtl8169sb_hw_phy_config(tp);
5615d9f1 2762 break;
2e955856 2763 case RTL_GIGA_MAC_VER_05:
4da19633 2764 rtl8169scd_hw_phy_config(tp);
2e955856 2765 break;
8c7006aa 2766 case RTL_GIGA_MAC_VER_06:
4da19633 2767 rtl8169sce_hw_phy_config(tp);
8c7006aa 2768 break;
2857ffb7
FR		 2769 case RTL_GIGA_MAC_VER_07:
2770 case RTL_GIGA_MAC_VER_08:
2771 case RTL_GIGA_MAC_VER_09:
4da19633 2772 rtl8102e_hw_phy_config(tp);
2857ffb7 2773 break;
236b8082 2774 case RTL_GIGA_MAC_VER_11:
4da19633 2775 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2776 break;
2777 case RTL_GIGA_MAC_VER_12:
4da19633 2778 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2779 break;
2780 case RTL_GIGA_MAC_VER_17:
4da19633 2781 rtl8168bef_hw_phy_config(tp);
236b8082 2782 break;
867763c1 2783 case RTL_GIGA_MAC_VER_18:
4da19633 2784 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2785 break;
2786 case RTL_GIGA_MAC_VER_19:
4da19633 2787 rtl8168c_1_hw_phy_config(tp);
867763c1 2788 break;
7da97ec9 2789 case RTL_GIGA_MAC_VER_20:
4da19633 2790 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2791 break;
197ff761 2792 case RTL_GIGA_MAC_VER_21:
4da19633 2793 rtl8168c_3_hw_phy_config(tp);
197ff761 2794 break;
6fb07058 2795 case RTL_GIGA_MAC_VER_22:
4da19633 2796 rtl8168c_4_hw_phy_config(tp);
6fb07058 2797 break;
ef3386f0 2798 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2799 case RTL_GIGA_MAC_VER_24:
4da19633 2800 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2801 break;
5b538df9 2802 case RTL_GIGA_MAC_VER_25:
bca03d5f 2803 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2804 break;
2805 case RTL_GIGA_MAC_VER_26:
bca03d5f 2806 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2807 break;
2808 case RTL_GIGA_MAC_VER_27:
4da19633 2809 rtl8168d_3_hw_phy_config(tp);
5b538df9 2810 break;
e6de30d6 2811 case RTL_GIGA_MAC_VER_28:
2812 rtl8168d_4_hw_phy_config(tp);
2813 break;
5a5e4443
HW		 2814 case RTL_GIGA_MAC_VER_29:
2815 case RTL_GIGA_MAC_VER_30:
2816 rtl8105e_hw_phy_config(tp);
2817 break;
cecb5fd7
FR		 2818 case RTL_GIGA_MAC_VER_31:
2819 /* None. */
2820 break;
01dc7fec 2821 case RTL_GIGA_MAC_VER_32:
01dc7fec 2822 case RTL_GIGA_MAC_VER_33:
15ecd039 2823 rtl8168e_hw_phy_config(tp);
01dc7fec 2824 break;
ef3386f0 2825
5615d9f1
FR		 2826 default:
2827 break;
2828 }
2829}
2830
1da177e4
LT		 2831static void rtl8169_phy_timer(unsigned long __opaque)
2832{
2833 struct net_device *dev = (struct net_device *)__opaque;
2834 struct rtl8169_private *tp = netdev_priv(dev);
2835 struct timer_list *timer = &tp->timer;
2836 void __iomem *ioaddr = tp->mmio_addr;
2837 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2838
bcf0bf90 2839 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2840
1da177e4
LT		 2841 spin_lock_irq(&tp->lock);
2842
4da19633 2843 if (tp->phy_reset_pending(tp)) {
5b0384f4 2844 /*
1da177e4
LT		 2845 * A busy loop could burn quite a few cycles on nowadays CPU.
2846 * Let's delay the execution of the timer for a few ticks.
2847 */
2848 timeout = HZ/10;
2849 goto out_mod_timer;
2850 }
2851
2852 if (tp->link_ok(ioaddr))
2853 goto out_unlock;
2854
bf82c189 2855 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2856
4da19633 2857 tp->phy_reset_enable(tp);
1da177e4
LT		 2858
2859out_mod_timer:
2860 mod_timer(timer, jiffies + timeout);
2861out_unlock:
2862 spin_unlock_irq(&tp->lock);
2863}
2864
1da177e4
LT		 2865#ifdef CONFIG_NET_POLL_CONTROLLER
2866/*
2867 * Polling 'interrupt' - used by things like netconsole to send skbs
2868 * without having to re-enable interrupts. It's not called while
2869 * the interrupt routine is executing.
2870 */
2871static void rtl8169_netpoll(struct net_device *dev)
2872{
2873 struct rtl8169_private *tp = netdev_priv(dev);
2874 struct pci_dev *pdev = tp->pci_dev;
2875
2876 disable_irq(pdev->irq);
7d12e780 2877 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2878 enable_irq(pdev->irq);
2879}
2880#endif
2881
2882static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2883 void __iomem *ioaddr)
2884{
2885 iounmap(ioaddr);
2886 pci_release_regions(pdev);
87aeec76 2887 pci_clear_mwi(pdev);
1da177e4
LT		 2888 pci_disable_device(pdev);
2889 free_netdev(dev);
2890}
2891
bf793295
FR		 2892static void rtl8169_phy_reset(struct net_device *dev,
2893 struct rtl8169_private *tp)
2894{
07d3f51f 2895 unsigned int i;
bf793295 2896
4da19633 2897 tp->phy_reset_enable(tp);
bf793295 2898 for (i = 0; i < 100; i++) {
4da19633 2899 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2900 return;
2901 msleep(1);
2902 }
bf82c189 2903 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2904}
2905
4ff96fa6
FR		 2906static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2907{
2908 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2909
5615d9f1 2910 rtl_hw_phy_config(dev);
4ff96fa6 2911
77332894
MS		 2912 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2913 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2914 RTL_W8(0x82, 0x01);
2915 }
4ff96fa6 2916
6dccd16b
FR		 2917 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2918
2919 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2920 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2921
bcf0bf90 2922 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2923 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2924 RTL_W8(0x82, 0x01);
2925 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2926 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2927 }
2928
bf793295
FR		 2929 rtl8169_phy_reset(dev, tp);
2930
54405cde 2931 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 2932 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2933 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2934 (tp->mii.supports_gmii ?
2935 ADVERTISED_1000baseT_Half |
2936 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2937
bf82c189
JP		 2938 if (RTL_R8(PHYstatus) & TBI_Enable)
2939 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2940}
2941
773d2021
FR		 2942static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2943{
2944 void __iomem *ioaddr = tp->mmio_addr;
2945 u32 high;
2946 u32 low;
2947
2948 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2949 high = addr[4] | (addr[5] << 8);
2950
2951 spin_lock_irq(&tp->lock);
2952
2953 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2954
773d2021 2955 RTL_W32(MAC4, high);
908ba2bf 2956 RTL_R32(MAC4);
2957
78f1cd02 2958 RTL_W32(MAC0, low);
908ba2bf 2959 RTL_R32(MAC0);
2960
773d2021
FR		 2961 RTL_W8(Cfg9346, Cfg9346_Lock);
2962
2963 spin_unlock_irq(&tp->lock);
2964}
2965
2966static int rtl_set_mac_address(struct net_device *dev, void *p)
2967{
2968 struct rtl8169_private *tp = netdev_priv(dev);
2969 struct sockaddr *addr = p;
2970
2971 if (!is_valid_ether_addr(addr->sa_data))
2972 return -EADDRNOTAVAIL;
2973
2974 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2975
2976 rtl_rar_set(tp, dev->dev_addr);
2977
2978 return 0;
2979}
2980
5f787a1a
FR		 2981static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2982{
2983 struct rtl8169_private *tp = netdev_priv(dev);
2984 struct mii_ioctl_data *data = if_mii(ifr);
2985
8b4ab28d
FR		 2986 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2987}
5f787a1a 2988
cecb5fd7
FR		 2989static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2990 struct mii_ioctl_data *data, int cmd)
8b4ab28d 2991{
5f787a1a
FR		 2992 switch (cmd) {
2993 case SIOCGMIIPHY:
2994 data->phy_id = 32; /* Internal PHY */
2995 return 0;
2996
2997 case SIOCGMIIREG:
4da19633 2998 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2999 return 0;
3000
3001 case SIOCSMIIREG:
4da19633 3002 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3003 return 0;
3004 }
3005 return -EOPNOTSUPP;
3006}
3007
8b4ab28d
FR		 3008static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3009{
3010 return -EOPNOTSUPP;
3011}
3012
0e485150
FR		 3013static const struct rtl_cfg_info {
3014 void (*hw_start)(struct net_device *);
3015 unsigned int region;
3016 unsigned int align;
3017 u16 intr_event;
3018 u16 napi_event;
ccdffb9a 3019 unsigned features;
f21b75e9 3020 u8 default_ver;
0e485150
FR		 3021} rtl_cfg_infos [] = {
3022 [RTL_CFG_0] = {
3023 .hw_start = rtl_hw_start_8169,
3024 .region = 1,
e9f63f30 3025 .align = 0,
0e485150
FR		 3026 .intr_event = SYSErr | LinkChg | RxOverflow |
3027 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3028 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3029 .features = RTL_FEATURE_GMII,
3030 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3031 },
3032 [RTL_CFG_1] = {
3033 .hw_start = rtl_hw_start_8168,
3034 .region = 2,
3035 .align = 8,
53f57357 3036 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3037 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3038 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3039 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3040 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3041 },
3042 [RTL_CFG_2] = {
3043 .hw_start = rtl_hw_start_8101,
3044 .region = 2,
3045 .align = 8,
3046 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3047 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3048 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3049 .features = RTL_FEATURE_MSI,
3050 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3051 }
3052};
3053
fbac58fc
FR		 3054/* Cfg9346_Unlock assumed. */
3055static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3056 const struct rtl_cfg_info *cfg)
3057{
3058 unsigned msi = 0;
3059 u8 cfg2;
3060
3061 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3062 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 3063 if (pci_enable_msi(pdev)) {
3064 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3065 } else {
3066 cfg2 |= MSIEnable;
3067 msi = RTL_FEATURE_MSI;
3068 }
3069 }
3070 RTL_W8(Config2, cfg2);
3071 return msi;
3072}
3073
3074static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3075{
3076 if (tp->features & RTL_FEATURE_MSI) {
3077 pci_disable_msi(pdev);
3078 tp->features &= ~RTL_FEATURE_MSI;
3079 }
3080}
3081
8b4ab28d
FR		 3082static const struct net_device_ops rtl8169_netdev_ops = {
3083 .ndo_open = rtl8169_open,
3084 .ndo_stop = rtl8169_close,
3085 .ndo_get_stats = rtl8169_get_stats,
00829823 3086 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3087 .ndo_tx_timeout = rtl8169_tx_timeout,
3088 .ndo_validate_addr = eth_validate_addr,
3089 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3090 .ndo_fix_features = rtl8169_fix_features,
3091 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3092 .ndo_set_mac_address = rtl_set_mac_address,
3093 .ndo_do_ioctl = rtl8169_ioctl,
3094 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 3095#ifdef CONFIG_NET_POLL_CONTROLLER
3096 .ndo_poll_controller = rtl8169_netpoll,
3097#endif
3098
3099};
3100
c0e45c1c 3101static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3102{
3103 struct mdio_ops *ops = &tp->mdio_ops;
3104
3105 switch (tp->mac_version) {
3106 case RTL_GIGA_MAC_VER_27:
3107 ops->write = r8168dp_1_mdio_write;
3108 ops->read = r8168dp_1_mdio_read;
3109 break;
e6de30d6 3110 case RTL_GIGA_MAC_VER_28:
4804b3b3 3111 case RTL_GIGA_MAC_VER_31:
e6de30d6 3112 ops->write = r8168dp_2_mdio_write;
3113 ops->read = r8168dp_2_mdio_read;
3114 break;
c0e45c1c 3115 default:
3116 ops->write = r8169_mdio_write;
3117 ops->read = r8169_mdio_read;
3118 break;
3119 }
3120}
3121
065c27c1 3122static void r810x_phy_power_down(struct rtl8169_private *tp)
3123{
3124 rtl_writephy(tp, 0x1f, 0x0000);
3125 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3126}
3127
3128static void r810x_phy_power_up(struct rtl8169_private *tp)
3129{
3130 rtl_writephy(tp, 0x1f, 0x0000);
3131 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3132}
3133
3134static void r810x_pll_power_down(struct rtl8169_private *tp)
3135{
3136 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3137 rtl_writephy(tp, 0x1f, 0x0000);
3138 rtl_writephy(tp, MII_BMCR, 0x0000);
3139 return;
3140 }
3141
3142 r810x_phy_power_down(tp);
3143}
3144
3145static void r810x_pll_power_up(struct rtl8169_private *tp)
3146{
3147 r810x_phy_power_up(tp);
3148}
3149
3150static void r8168_phy_power_up(struct rtl8169_private *tp)
3151{
3152 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3153 switch (tp->mac_version) {
3154 case RTL_GIGA_MAC_VER_11:
3155 case RTL_GIGA_MAC_VER_12:
3156 case RTL_GIGA_MAC_VER_17:
3157 case RTL_GIGA_MAC_VER_18:
3158 case RTL_GIGA_MAC_VER_19:
3159 case RTL_GIGA_MAC_VER_20:
3160 case RTL_GIGA_MAC_VER_21:
3161 case RTL_GIGA_MAC_VER_22:
3162 case RTL_GIGA_MAC_VER_23:
3163 case RTL_GIGA_MAC_VER_24:
3164 case RTL_GIGA_MAC_VER_25:
3165 case RTL_GIGA_MAC_VER_26:
3166 case RTL_GIGA_MAC_VER_27:
3167 case RTL_GIGA_MAC_VER_28:
3168 case RTL_GIGA_MAC_VER_31:
3169 rtl_writephy(tp, 0x0e, 0x0000);
3170 break;
3171 default:
3172 break;
3173 }
065c27c1 3174 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3175}
3176
3177static void r8168_phy_power_down(struct rtl8169_private *tp)
3178{
3179 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3180 switch (tp->mac_version) {
3181 case RTL_GIGA_MAC_VER_32:
3182 case RTL_GIGA_MAC_VER_33:
3183 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3184 break;
3185
3186 case RTL_GIGA_MAC_VER_11:
3187 case RTL_GIGA_MAC_VER_12:
3188 case RTL_GIGA_MAC_VER_17:
3189 case RTL_GIGA_MAC_VER_18:
3190 case RTL_GIGA_MAC_VER_19:
3191 case RTL_GIGA_MAC_VER_20:
3192 case RTL_GIGA_MAC_VER_21:
3193 case RTL_GIGA_MAC_VER_22:
3194 case RTL_GIGA_MAC_VER_23:
3195 case RTL_GIGA_MAC_VER_24:
3196 case RTL_GIGA_MAC_VER_25:
3197 case RTL_GIGA_MAC_VER_26:
3198 case RTL_GIGA_MAC_VER_27:
3199 case RTL_GIGA_MAC_VER_28:
3200 case RTL_GIGA_MAC_VER_31:
3201 rtl_writephy(tp, 0x0e, 0x0200);
3202 default:
3203 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3204 break;
3205 }
065c27c1 3206}
3207
3208static void r8168_pll_power_down(struct rtl8169_private *tp)
3209{
3210 void __iomem *ioaddr = tp->mmio_addr;
3211
cecb5fd7
FR		 3212 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3213 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3214 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3215 r8168dp_check_dash(tp)) {
065c27c1 3216 return;
5d2e1957 3217 }
065c27c1 3218
cecb5fd7
FR		 3219 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3220 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3221 (RTL_R16(CPlusCmd) & ASF)) {
3222 return;
3223 }
3224
01dc7fec 3225 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3226 tp->mac_version == RTL_GIGA_MAC_VER_33)
3227 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3228
065c27c1 3229 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3230 rtl_writephy(tp, 0x1f, 0x0000);
3231 rtl_writephy(tp, MII_BMCR, 0x0000);
3232
3233 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3234 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3235 return;
3236 }
3237
3238 r8168_phy_power_down(tp);
3239
3240 switch (tp->mac_version) {
3241 case RTL_GIGA_MAC_VER_25:
3242 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3243 case RTL_GIGA_MAC_VER_27:
3244 case RTL_GIGA_MAC_VER_28:
4804b3b3 3245 case RTL_GIGA_MAC_VER_31:
01dc7fec 3246 case RTL_GIGA_MAC_VER_32:
3247 case RTL_GIGA_MAC_VER_33:
065c27c1 3248 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3249 break;
3250 }
3251}
3252
3253static void r8168_pll_power_up(struct rtl8169_private *tp)
3254{
3255 void __iomem *ioaddr = tp->mmio_addr;
3256
cecb5fd7
FR		 3257 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3258 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3259 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3260 r8168dp_check_dash(tp)) {
065c27c1 3261 return;
5d2e1957 3262 }
065c27c1 3263
3264 switch (tp->mac_version) {
3265 case RTL_GIGA_MAC_VER_25:
3266 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3267 case RTL_GIGA_MAC_VER_27:
3268 case RTL_GIGA_MAC_VER_28:
4804b3b3 3269 case RTL_GIGA_MAC_VER_31:
01dc7fec 3270 case RTL_GIGA_MAC_VER_32:
3271 case RTL_GIGA_MAC_VER_33:
065c27c1 3272 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3273 break;
3274 }
3275
3276 r8168_phy_power_up(tp);
3277}
3278
3279static void rtl_pll_power_op(struct rtl8169_private *tp,
3280 void (*op)(struct rtl8169_private *))
3281{
3282 if (op)
3283 op(tp);
3284}
3285
3286static void rtl_pll_power_down(struct rtl8169_private *tp)
3287{
3288 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3289}
3290
3291static void rtl_pll_power_up(struct rtl8169_private *tp)
3292{
3293 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3294}
3295
3296static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3297{
3298 struct pll_power_ops *ops = &tp->pll_power_ops;
3299
3300 switch (tp->mac_version) {
3301 case RTL_GIGA_MAC_VER_07:
3302 case RTL_GIGA_MAC_VER_08:
3303 case RTL_GIGA_MAC_VER_09:
3304 case RTL_GIGA_MAC_VER_10:
3305 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3306 case RTL_GIGA_MAC_VER_29:
3307 case RTL_GIGA_MAC_VER_30:
065c27c1 3308 ops->down = r810x_pll_power_down;
3309 ops->up = r810x_pll_power_up;
3310 break;
3311
3312 case RTL_GIGA_MAC_VER_11:
3313 case RTL_GIGA_MAC_VER_12:
3314 case RTL_GIGA_MAC_VER_17:
3315 case RTL_GIGA_MAC_VER_18:
3316 case RTL_GIGA_MAC_VER_19:
3317 case RTL_GIGA_MAC_VER_20:
3318 case RTL_GIGA_MAC_VER_21:
3319 case RTL_GIGA_MAC_VER_22:
3320 case RTL_GIGA_MAC_VER_23:
3321 case RTL_GIGA_MAC_VER_24:
3322 case RTL_GIGA_MAC_VER_25:
3323 case RTL_GIGA_MAC_VER_26:
3324 case RTL_GIGA_MAC_VER_27:
e6de30d6 3325 case RTL_GIGA_MAC_VER_28:
4804b3b3 3326 case RTL_GIGA_MAC_VER_31:
01dc7fec 3327 case RTL_GIGA_MAC_VER_32:
3328 case RTL_GIGA_MAC_VER_33:
065c27c1 3329 ops->down = r8168_pll_power_down;
3330 ops->up = r8168_pll_power_up;
3331 break;
3332
3333 default:
3334 ops->down = NULL;
3335 ops->up = NULL;
3336 break;
3337 }
3338}
3339
6f43adc8
FR		 3340static void rtl_hw_reset(struct rtl8169_private *tp)
3341{
3342 void __iomem *ioaddr = tp->mmio_addr;
3343 int i;
3344
3345 /* Soft reset the chip. */
3346 RTL_W8(ChipCmd, CmdReset);
3347
3348 /* Check that the chip has finished the reset. */
3349 for (i = 0; i < 100; i++) {
3350 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3351 break;
3352 msleep_interruptible(1);
3353 }
3354}
3355
1da177e4 3356static int __devinit
4ff96fa6 3357rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3358{
0e485150
FR		 3359 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3360 const unsigned int region = cfg->region;
1da177e4 3361 struct rtl8169_private *tp;
ccdffb9a 3362 struct mii_if_info *mii;
4ff96fa6
FR		 3363 struct net_device *dev;
3364 void __iomem *ioaddr;
2b7b4318 3365 int chipset, i;
07d3f51f 3366 int rc;
1da177e4 3367
4ff96fa6
FR		 3368 if (netif_msg_drv(&debug)) {
3369 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3370 MODULENAME, RTL8169_VERSION);
3371 }
1da177e4 3372
1da177e4 3373 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3374 if (!dev) {
b57b7e5a 3375 if (netif_msg_drv(&debug))
9b91cf9d 3376 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3377 rc = -ENOMEM;
3378 goto out;
1da177e4
LT		 3379 }
3380
1da177e4 3381 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3382 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3383 tp = netdev_priv(dev);
c4028958 3384 tp->dev = dev;
21e197f2 3385 tp->pci_dev = pdev;
b57b7e5a 3386 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3387
ccdffb9a
FR		 3388 mii = &tp->mii;
3389 mii->dev = dev;
3390 mii->mdio_read = rtl_mdio_read;
3391 mii->mdio_write = rtl_mdio_write;
3392 mii->phy_id_mask = 0x1f;
3393 mii->reg_num_mask = 0x1f;
3394 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3395
ba04c7c9
SG		 3396 /* disable ASPM completely as that cause random device stop working
3397 * problems as well as full system hangs for some PCIe devices users */
3398 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3399 PCIE_LINK_STATE_CLKPM);
3400
1da177e4
LT		 3401 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3402 rc = pci_enable_device(pdev);
b57b7e5a 3403 if (rc < 0) {
bf82c189 3404 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3405 goto err_out_free_dev_1;
1da177e4
LT		 3406 }
3407
87aeec76 3408 if (pci_set_mwi(pdev) < 0)
3409 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3410
1da177e4 3411 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3412 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3413 netif_err(tp, probe, dev,
3414 "region #%d not an MMIO resource, aborting\n",
3415 region);
1da177e4 3416 rc = -ENODEV;
87aeec76 3417 goto err_out_mwi_2;
1da177e4 3418 }
4ff96fa6 3419
1da177e4 3420 /* check for weird/broken PCI region reporting */
bcf0bf90 3421 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3422 netif_err(tp, probe, dev,
3423 "Invalid PCI region size(s), aborting\n");
1da177e4 3424 rc = -ENODEV;
87aeec76 3425 goto err_out_mwi_2;
1da177e4
LT		 3426 }
3427
3428 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3429 if (rc < 0) {
bf82c189 3430 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3431 goto err_out_mwi_2;
1da177e4
LT		 3432 }
3433
d24e9aaf 3434 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3435
3436 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3437 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3438 tp->cp_cmd |= PCIDAC;
3439 dev->features |= NETIF_F_HIGHDMA;
3440 } else {
284901a9 3441 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3442 if (rc < 0) {
bf82c189 3443 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3444 goto err_out_free_res_3;
1da177e4
LT		 3445 }
3446 }
3447
1da177e4 3448 /* ioremap MMIO region */
bcf0bf90 3449 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3450 if (!ioaddr) {
bf82c189 3451 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3452 rc = -EIO;
87aeec76 3453 goto err_out_free_res_3;
1da177e4 3454 }
6f43adc8 3455 tp->mmio_addr = ioaddr;
1da177e4 3456
e44daade
JM		 3457 if (!pci_is_pcie(pdev))
3458 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 3459
d78ad8cb 3460 RTL_W16(IntrMask, 0x0000);
1da177e4 3461
6f43adc8 3462 rtl_hw_reset(tp);
1da177e4 3463
d78ad8cb
KW		 3464 RTL_W16(IntrStatus, 0xffff);
3465
ca52efd5 3466 pci_set_master(pdev);
3467
1da177e4 3468 /* Identify chip attached to board */
5d320a20 3469 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
1da177e4 3470
7a8fc77b
FR		 3471 /*
3472 * Pretend we are using VLANs; This bypasses a nasty bug where
3473 * Interrupts stop flowing on high load on 8110SCd controllers.
3474 */
3475 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3476 tp->cp_cmd |= RxVlan;
3477
c0e45c1c 3478 rtl_init_mdio_ops(tp);
065c27c1 3479 rtl_init_pll_power_ops(tp);
c0e45c1c 3480
1da177e4 3481 rtl8169_print_mac_version(tp);
1da177e4 3482
85bffe6c
FR		 3483 chipset = tp->mac_version;
3484 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3485
5d06a99f
FR		 3486 RTL_W8(Cfg9346, Cfg9346_Unlock);
3487 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3488 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3489 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3490 tp->features |= RTL_FEATURE_WOL;
3491 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3492 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3493 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3494 RTL_W8(Cfg9346, Cfg9346_Lock);
3495
66ec5d4f
FR		 3496 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3497 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3498 tp->set_speed = rtl8169_set_speed_tbi;
3499 tp->get_settings = rtl8169_gset_tbi;
3500 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3501 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3502 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3503 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3504 } else {
3505 tp->set_speed = rtl8169_set_speed_xmii;
3506 tp->get_settings = rtl8169_gset_xmii;
3507 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3508 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3509 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3510 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3511 }
3512
df58ef51
FR		 3513 spin_lock_init(&tp->lock);
3514
7bf6bf48 3515 /* Get MAC address */
1da177e4
LT		 3516 for (i = 0; i < MAC_ADDR_LEN; i++)
3517 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3518 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3519
1da177e4 3520 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3521 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3522 dev->irq = pdev->irq;
3523 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3524
bea3348e 3525 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3526
350fb32a
MM		 3527 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3528 * properly for all devices */
3529 dev->features |= NETIF_F_RXCSUM |
3530 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3531
3532 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3533 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3534 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3535 NETIF_F_HIGHDMA;
3536
3537 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3538 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3539 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3540
3541 tp->intr_mask = 0xffff;
0e485150
FR		 3542 tp->hw_start = cfg->hw_start;
3543 tp->intr_event = cfg->intr_event;
3544 tp->napi_event = cfg->napi_event;
1da177e4 3545
2efa53f3
FR		 3546 init_timer(&tp->timer);
3547 tp->timer.data = (unsigned long) dev;
3548 tp->timer.function = rtl8169_phy_timer;
3549
b6ffd97f 3550 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3551
1da177e4 3552 rc = register_netdev(dev);
4ff96fa6 3553 if (rc < 0)
87aeec76 3554 goto err_out_msi_4;
1da177e4
LT		 3555
3556 pci_set_drvdata(pdev, dev);
3557
bf82c189 3558 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3559 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3560 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3561
cecb5fd7
FR		 3562 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3563 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3564 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3565 rtl8168_driver_start(tp);
e6de30d6 3566 }
b646d900 3567
8b76ab39 3568 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3569
f3ec4f87
AS		 3570 if (pci_dev_run_wake(pdev))
3571 pm_runtime_put_noidle(&pdev->dev);
e1759441 3572
0d672e9f
IV		 3573 netif_carrier_off(dev);
3574
4ff96fa6
FR		 3575out:
3576 return rc;
1da177e4 3577
87aeec76 3578err_out_msi_4:
fbac58fc 3579 rtl_disable_msi(pdev, tp);
4ff96fa6 3580 iounmap(ioaddr);
87aeec76 3581err_out_free_res_3:
4ff96fa6 3582 pci_release_regions(pdev);
87aeec76 3583err_out_mwi_2:
4ff96fa6 3584 pci_clear_mwi(pdev);
4ff96fa6
FR		 3585 pci_disable_device(pdev);
3586err_out_free_dev_1:
3587 free_netdev(dev);
3588 goto out;
1da177e4
LT		 3589}
3590
07d3f51f 3591static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3592{
3593 struct net_device *dev = pci_get_drvdata(pdev);
3594 struct rtl8169_private *tp = netdev_priv(dev);
3595
cecb5fd7
FR		 3596 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3597 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3598 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3599 rtl8168_driver_stop(tp);
e6de30d6 3600 }
b646d900 3601
23f333a2 3602 cancel_delayed_work_sync(&tp->task);
eb2a021c 3603
1da177e4 3604 unregister_netdev(dev);
cc098dc7 3605
953a12cc
FR		 3606 rtl_release_firmware(tp);
3607
f3ec4f87
AS		 3608 if (pci_dev_run_wake(pdev))
3609 pm_runtime_get_noresume(&pdev->dev);
e1759441 3610
cc098dc7
IV		 3611 /* restore original MAC address */
3612 rtl_rar_set(tp, dev->perm_addr);
3613
fbac58fc 3614 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3615 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3616 pci_set_drvdata(pdev, NULL);
3617}
3618
b6ffd97f 3619static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3620{
b6ffd97f
FR		 3621 struct rtl_fw *rtl_fw;
3622 const char *name;
3623 int rc = -ENOMEM;
953a12cc 3624
b6ffd97f
FR		 3625 name = rtl_lookup_firmware_name(tp);
3626 if (!name)
3627 goto out_no_firmware;
953a12cc 3628
b6ffd97f
FR		 3629 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3630 if (!rtl_fw)
3631 goto err_warn;
31bd204f 3632
b6ffd97f
FR		 3633 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3634 if (rc < 0)
3635 goto err_free;
3636
fd112f2e
FR		 3637 rc = rtl_check_firmware(tp, rtl_fw);
3638 if (rc < 0)
3639 goto err_release_firmware;
3640
b6ffd97f
FR		 3641 tp->rtl_fw = rtl_fw;
3642out:
3643 return;
3644
fd112f2e
FR		 3645err_release_firmware:
3646 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3647err_free:
3648 kfree(rtl_fw);
3649err_warn:
3650 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3651 name, rc);
3652out_no_firmware:
3653 tp->rtl_fw = NULL;
3654 goto out;
3655}
3656
3657static void rtl_request_firmware(struct rtl8169_private *tp)
3658{
3659 if (IS_ERR(tp->rtl_fw))
3660 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3661}
3662
1da177e4
LT		 3663static int rtl8169_open(struct net_device *dev)
3664{
3665 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3666 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3667 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3668 int retval = -ENOMEM;
1da177e4 3669
e1759441 3670 pm_runtime_get_sync(&pdev->dev);
1da177e4 3671
1da177e4
LT		 3672 /*
3673 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3674 * dma_alloc_coherent provides more.
1da177e4 3675 */
82553bb6
SG		 3676 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3677 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3678 if (!tp->TxDescArray)
e1759441 3679 goto err_pm_runtime_put;
1da177e4 3680
82553bb6
SG		 3681 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3682 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3683 if (!tp->RxDescArray)
99f252b0 3684 goto err_free_tx_0;
1da177e4
LT		 3685
3686 retval = rtl8169_init_ring(dev);
3687 if (retval < 0)
99f252b0 3688 goto err_free_rx_1;
1da177e4 3689
c4028958 3690 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3691
99f252b0
FR		 3692 smp_mb();
3693
953a12cc
FR		 3694 rtl_request_firmware(tp);
3695
fbac58fc
FR		 3696 retval = request_irq(dev->irq, rtl8169_interrupt,
3697 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3698 dev->name, dev);
3699 if (retval < 0)
953a12cc 3700 goto err_release_fw_2;
99f252b0 3701
bea3348e 3702 napi_enable(&tp->napi);
bea3348e 3703
eee3a96c 3704 rtl8169_init_phy(dev, tp);
3705
350fb32a 3706 rtl8169_set_features(dev, dev->features);
eee3a96c 3707
065c27c1 3708 rtl_pll_power_up(tp);
3709
07ce4064 3710 rtl_hw_start(dev);
1da177e4 3711
e1759441
RW		 3712 tp->saved_wolopts = 0;
3713 pm_runtime_put_noidle(&pdev->dev);
3714
eee3a96c 3715 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3716out:
3717 return retval;
3718
953a12cc
FR		 3719err_release_fw_2:
3720 rtl_release_firmware(tp);
99f252b0
FR		 3721 rtl8169_rx_clear(tp);
3722err_free_rx_1:
82553bb6
SG		 3723 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3724 tp->RxPhyAddr);
e1759441 3725 tp->RxDescArray = NULL;
99f252b0 3726err_free_tx_0:
82553bb6
SG		 3727 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3728 tp->TxPhyAddr);
e1759441
RW		 3729 tp->TxDescArray = NULL;
3730err_pm_runtime_put:
3731 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3732 goto out;
3733}
3734
e6de30d6 3735static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3736{
e6de30d6 3737 void __iomem *ioaddr = tp->mmio_addr;
3738
1da177e4
LT		 3739 /* Disable interrupts */
3740 rtl8169_irq_mask_and_ack(ioaddr);
3741
5d2e1957 3742 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3743 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3744 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3745 while (RTL_R8(TxPoll) & NPQ)
3746 udelay(20);
3747
3748 }
3749
1da177e4
LT		 3750 /* Reset the chipset */
3751 RTL_W8(ChipCmd, CmdReset);
3752
3753 /* PCI commit */
3754 RTL_R8(ChipCmd);
3755}
3756
7f796d83 3757static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3758{
3759 void __iomem *ioaddr = tp->mmio_addr;
3760 u32 cfg = rtl8169_rx_config;
3761
2b7b4318 3762 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3763 RTL_W32(RxConfig, cfg);
3764
3765 /* Set DMA burst size and Interframe Gap Time */
3766 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3767 (InterFrameGap << TxInterFrameGapShift));
3768}
3769
07ce4064 3770static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3771{
3772 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3773
6f43adc8 3774 rtl_hw_reset(tp);
1da177e4 3775
07ce4064
FR		 3776 tp->hw_start(dev);
3777
07ce4064
FR		 3778 netif_start_queue(dev);
3779}
3780
7f796d83
FR		 3781static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3782 void __iomem *ioaddr)
3783{
3784 /*
3785 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3786 * register to be written before TxDescAddrLow to work.
3787 * Switching from MMIO to I/O access fixes the issue as well.
3788 */
3789 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3790 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3791 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3792 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3793}
3794
3795static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3796{
3797 u16 cmd;
3798
3799 cmd = RTL_R16(CPlusCmd);
3800 RTL_W16(CPlusCmd, cmd);
3801 return cmd;
3802}
3803
fdd7b4c3 3804static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3805{
3806 /* Low hurts. Let's disable the filtering. */
207d6e87 3807 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3808}
3809
6dccd16b
FR		 3810static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3811{
3744100e 3812 static const struct rtl_cfg2_info {
6dccd16b
FR		 3813 u32 mac_version;
3814 u32 clk;
3815 u32 val;
3816 } cfg2_info [] = {
3817 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3818 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3819 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3820 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 3821 };
3822 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 3823 unsigned int i;
3824 u32 clk;
3825
3826 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3827 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3828 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3829 RTL_W32(0x7c, p->val);
3830 break;
3831 }
3832 }
3833}
3834
07ce4064
FR		 3835static void rtl_hw_start_8169(struct net_device *dev)
3836{
3837 struct rtl8169_private *tp = netdev_priv(dev);
3838 void __iomem *ioaddr = tp->mmio_addr;
3839 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3840
9cb427b6
FR		 3841 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3842 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3843 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3844 }
3845
1da177e4 3846 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 3847 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3848 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3849 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3850 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 3851 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3852
f0298f81 3853 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3854
6f0333b8 3855 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3856
cecb5fd7
FR		 3857 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3858 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3859 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3860 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 3861 rtl_set_rx_tx_config_registers(tp);
1da177e4 3862
7f796d83 3863 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3864
cecb5fd7
FR		 3865 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3866 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 3867 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3868 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3869 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3870 }
3871
bcf0bf90
FR		 3872 RTL_W16(CPlusCmd, tp->cp_cmd);
3873
6dccd16b
FR		 3874 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3875
1da177e4
LT		 3876 /*
3877 * Undocumented corner. Supposedly:
3878 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3879 */
3880 RTL_W16(IntrMitigate, 0x0000);
3881
7f796d83 3882 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3883
cecb5fd7
FR		 3884 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3885 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3886 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3887 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 3888 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3889 rtl_set_rx_tx_config_registers(tp);
3890 }
3891
1da177e4 3892 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3893
3894 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3895 RTL_R8(IntrMask);
1da177e4
LT		 3896
3897 RTL_W32(RxMissed, 0);
3898
07ce4064 3899 rtl_set_rx_mode(dev);
1da177e4
LT		 3900
3901 /* no early-rx interrupts */
3902 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3903
3904 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3905 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3906}
1da177e4 3907
9c14ceaf 3908static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3909{
e44daade 3910 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 3911
3912 if (cap) {
3913 u16 ctl;
458a9f61 3914
9c14ceaf
FR		 3915 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3916 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3917 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3918 }
458a9f61
FR		 3919}
3920
650e8d5d 3921static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3922{
3923 u32 csi;
3924
3925 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3926 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3927}
3928
e6de30d6 3929static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3930{
3931 rtl_csi_access_enable(ioaddr, 0x17000000);
3932}
3933
650e8d5d 3934static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3935{
3936 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3937}
3938
3939struct ephy_info {
3940 unsigned int offset;
3941 u16 mask;
3942 u16 bits;
3943};
3944
350f7596 3945static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3946{
3947 u16 w;
3948
3949 while (len-- > 0) {
3950 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3951 rtl_ephy_write(ioaddr, e->offset, w);
3952 e++;
3953 }
3954}
3955
b726e493
FR		 3956static void rtl_disable_clock_request(struct pci_dev *pdev)
3957{
e44daade 3958 int cap = pci_pcie_cap(pdev);
b726e493
FR		 3959
3960 if (cap) {
3961 u16 ctl;
3962
3963 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3964 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3965 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3966 }
3967}
3968
e6de30d6 3969static void rtl_enable_clock_request(struct pci_dev *pdev)
3970{
e44daade 3971 int cap = pci_pcie_cap(pdev);
e6de30d6 3972
3973 if (cap) {
3974 u16 ctl;
3975
3976 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3977 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3978 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3979 }
3980}
3981
b726e493
FR		 3982#define R8168_CPCMD_QUIRK_MASK (\
3983 EnableBist | \
3984 Mac_dbgo_oe | \
3985 Force_half_dup | \
3986 Force_rxflow_en | \
3987 Force_txflow_en | \
3988 Cxpl_dbg_sel | \
3989 ASF | \
3990 PktCntrDisable | \
3991 Mac_dbgo_sel)
3992
219a1e9d
FR		 3993static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3994{
b726e493
FR		 3995 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3996
3997 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3998
2e68ae44
FR		 3999 rtl_tx_performance_tweak(pdev,
4000 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4001}
4002
4003static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4004{
4005 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4006
f0298f81 4007 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4008
4009 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4010}
4011
4012static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4013{
b726e493
FR		 4014 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4015
4016 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4017
219a1e9d 4018 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4019
4020 rtl_disable_clock_request(pdev);
4021
4022 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4023}
4024
ef3386f0 4025static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4026{
350f7596 4027 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4028 { 0x01, 0, 0x0001 },
4029 { 0x02, 0x0800, 0x1000 },
4030 { 0x03, 0, 0x0042 },
4031 { 0x06, 0x0080, 0x0000 },
4032 { 0x07, 0, 0x2000 }
4033 };
4034
650e8d5d 4035 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4036
4037 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4038
219a1e9d
FR		 4039 __rtl_hw_start_8168cp(ioaddr, pdev);
4040}
4041
ef3386f0
FR		 4042static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4043{
650e8d5d 4044 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4045
4046 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4047
4048 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4049
4050 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4051}
4052
7f3e3d3a
FR		 4053static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4054{
650e8d5d 4055 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4056
4057 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4058
4059 /* Magic. */
4060 RTL_W8(DBG_REG, 0x20);
4061
f0298f81 4062 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4063
4064 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4065
4066 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4067}
4068
219a1e9d
FR		 4069static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4070{
350f7596 4071 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4072 { 0x02, 0x0800, 0x1000 },
4073 { 0x03, 0, 0x0002 },
4074 { 0x06, 0x0080, 0x0000 }
4075 };
4076
650e8d5d 4077 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4078
4079 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4080
4081 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4082
219a1e9d
FR		 4083 __rtl_hw_start_8168cp(ioaddr, pdev);
4084}
4085
4086static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4087{
350f7596 4088 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4089 { 0x01, 0, 0x0001 },
4090 { 0x03, 0x0400, 0x0220 }
4091 };
4092
650e8d5d 4093 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4094
4095 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4096
219a1e9d
FR		 4097 __rtl_hw_start_8168cp(ioaddr, pdev);
4098}
4099
197ff761
FR		 4100static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4101{
4102 rtl_hw_start_8168c_2(ioaddr, pdev);
4103}
4104
6fb07058
FR		 4105static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4106{
650e8d5d 4107 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4108
4109 __rtl_hw_start_8168cp(ioaddr, pdev);
4110}
4111
5b538df9
FR		 4112static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4113{
650e8d5d 4114 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4115
4116 rtl_disable_clock_request(pdev);
4117
f0298f81 4118 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4119
4120 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4121
4122 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4123}
4124
4804b3b3 4125static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4126{
4127 rtl_csi_access_enable_1(ioaddr);
4128
4129 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4130
4131 RTL_W8(MaxTxPacketSize, TxPacketMax);
4132
4133 rtl_disable_clock_request(pdev);
4134}
4135
e6de30d6 4136static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4137{
4138 static const struct ephy_info e_info_8168d_4[] = {
4139 { 0x0b, ~0, 0x48 },
4140 { 0x19, 0x20, 0x50 },
4141 { 0x0c, ~0, 0x20 }
4142 };
4143 int i;
4144
4145 rtl_csi_access_enable_1(ioaddr);
4146
4147 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4148
4149 RTL_W8(MaxTxPacketSize, TxPacketMax);
4150
4151 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4152 const struct ephy_info *e = e_info_8168d_4 + i;
4153 u16 w;
4154
4155 w = rtl_ephy_read(ioaddr, e->offset);
4156 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4157 }
4158
4159 rtl_enable_clock_request(pdev);
4160}
4161
01dc7fec 4162static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4163{
4164 static const struct ephy_info e_info_8168e[] = {
4165 { 0x00, 0x0200, 0x0100 },
4166 { 0x00, 0x0000, 0x0004 },
4167 { 0x06, 0x0002, 0x0001 },
4168 { 0x06, 0x0000, 0x0030 },
4169 { 0x07, 0x0000, 0x2000 },
4170 { 0x00, 0x0000, 0x0020 },
4171 { 0x03, 0x5800, 0x2000 },
4172 { 0x03, 0x0000, 0x0001 },
4173 { 0x01, 0x0800, 0x1000 },
4174 { 0x07, 0x0000, 0x4000 },
4175 { 0x1e, 0x0000, 0x2000 },
4176 { 0x19, 0xffff, 0xfe6c },
4177 { 0x0a, 0x0000, 0x0040 }
4178 };
4179
4180 rtl_csi_access_enable_2(ioaddr);
4181
4182 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4183
4184 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4185
4186 RTL_W8(MaxTxPacketSize, TxPacketMax);
4187
4188 rtl_disable_clock_request(pdev);
4189
4190 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4191 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4192 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4193
cecb5fd7 4194 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4195}
4196
07ce4064
FR		 4197static void rtl_hw_start_8168(struct net_device *dev)
4198{
2dd99530
FR		 4199 struct rtl8169_private *tp = netdev_priv(dev);
4200 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4201 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4202
4203 RTL_W8(Cfg9346, Cfg9346_Unlock);
4204
f0298f81 4205 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4206
6f0333b8 4207 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4208
0e485150 4209 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4210
4211 RTL_W16(CPlusCmd, tp->cp_cmd);
4212
0e485150 4213 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4214
0e485150 4215 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4216 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4217 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4218 tp->intr_event |= RxFIFOOver | PCSTimeout;
4219 tp->intr_event &= ~RxOverflow;
4220 }
4221
4222 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4223
b8363901
FR		 4224 rtl_set_rx_mode(dev);
4225
4226 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4227 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4228
4229 RTL_R8(IntrMask);
4230
219a1e9d
FR		 4231 switch (tp->mac_version) {
4232 case RTL_GIGA_MAC_VER_11:
4233 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4234 break;
219a1e9d
FR		 4235
4236 case RTL_GIGA_MAC_VER_12:
4237 case RTL_GIGA_MAC_VER_17:
4238 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4239 break;
219a1e9d
FR		 4240
4241 case RTL_GIGA_MAC_VER_18:
ef3386f0 4242 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4243 break;
219a1e9d
FR		 4244
4245 case RTL_GIGA_MAC_VER_19:
4246 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4247 break;
219a1e9d
FR		 4248
4249 case RTL_GIGA_MAC_VER_20:
4250 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4251 break;
219a1e9d 4252
197ff761
FR		 4253 case RTL_GIGA_MAC_VER_21:
4254 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4255 break;
197ff761 4256
6fb07058
FR		 4257 case RTL_GIGA_MAC_VER_22:
4258 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4259 break;
6fb07058 4260
ef3386f0
FR		 4261 case RTL_GIGA_MAC_VER_23:
4262 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4263 break;
ef3386f0 4264
7f3e3d3a
FR		 4265 case RTL_GIGA_MAC_VER_24:
4266 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4267 break;
7f3e3d3a 4268
5b538df9 4269 case RTL_GIGA_MAC_VER_25:
daf9df6d 4270 case RTL_GIGA_MAC_VER_26:
4271 case RTL_GIGA_MAC_VER_27:
5b538df9 4272 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4273 break;
5b538df9 4274
e6de30d6 4275 case RTL_GIGA_MAC_VER_28:
4276 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4277 break;
cecb5fd7 4278
4804b3b3 4279 case RTL_GIGA_MAC_VER_31:
4280 rtl_hw_start_8168dp(ioaddr, pdev);
4281 break;
4282
01dc7fec 4283 case RTL_GIGA_MAC_VER_32:
4284 case RTL_GIGA_MAC_VER_33:
4285 rtl_hw_start_8168e(ioaddr, pdev);
4286 break;
e6de30d6 4287
219a1e9d
FR		 4288 default:
4289 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4290 dev->name, tp->mac_version);
4804b3b3 4291 break;
219a1e9d 4292 }
2dd99530 4293
0e485150
FR		 4294 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4295
b8363901
FR		 4296 RTL_W8(Cfg9346, Cfg9346_Lock);
4297
2dd99530 4298 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4299
0e485150 4300 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4301}
1da177e4 4302
2857ffb7
FR		 4303#define R810X_CPCMD_QUIRK_MASK (\
4304 EnableBist | \
4305 Mac_dbgo_oe | \
4306 Force_half_dup | \
5edcc537 4307 Force_rxflow_en | \
2857ffb7
FR		 4308 Force_txflow_en | \
4309 Cxpl_dbg_sel | \
4310 ASF | \
4311 PktCntrDisable | \
d24e9aaf 4312 Mac_dbgo_sel)
2857ffb7
FR		 4313
4314static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4315{
350f7596 4316 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4317 { 0x01, 0, 0x6e65 },
4318 { 0x02, 0, 0x091f },
4319 { 0x03, 0, 0xc2f9 },
4320 { 0x06, 0, 0xafb5 },
4321 { 0x07, 0, 0x0e00 },
4322 { 0x19, 0, 0xec80 },
4323 { 0x01, 0, 0x2e65 },
4324 { 0x01, 0, 0x6e65 }
4325 };
4326 u8 cfg1;
4327
650e8d5d 4328 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4329
4330 RTL_W8(DBG_REG, FIX_NAK_1);
4331
4332 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4333
4334 RTL_W8(Config1,
4335 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4336 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4337
4338 cfg1 = RTL_R8(Config1);
4339 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4340 RTL_W8(Config1, cfg1 & ~LEDS0);
4341
2857ffb7
FR		 4342 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4343}
4344
4345static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4346{
650e8d5d 4347 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4348
4349 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4350
4351 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4352 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4353}
4354
4355static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4356{
4357 rtl_hw_start_8102e_2(ioaddr, pdev);
4358
4359 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4360}
4361
5a5e4443
HW		 4362static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4363{
4364 static const struct ephy_info e_info_8105e_1[] = {
4365 { 0x07, 0, 0x4000 },
4366 { 0x19, 0, 0x0200 },
4367 { 0x19, 0, 0x0020 },
4368 { 0x1e, 0, 0x2000 },
4369 { 0x03, 0, 0x0001 },
4370 { 0x19, 0, 0x0100 },
4371 { 0x19, 0, 0x0004 },
4372 { 0x0a, 0, 0x0020 }
4373 };
4374
cecb5fd7 4375 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4376 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4377
cecb5fd7 4378 /* Disable Early Tally Counter */
5a5e4443
HW		 4379 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4380
4381 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4382 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4383
4384 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4385}
4386
4387static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4388{
4389 rtl_hw_start_8105e_1(ioaddr, pdev);
4390 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4391}
4392
07ce4064
FR		 4393static void rtl_hw_start_8101(struct net_device *dev)
4394{
cdf1a608
FR		 4395 struct rtl8169_private *tp = netdev_priv(dev);
4396 void __iomem *ioaddr = tp->mmio_addr;
4397 struct pci_dev *pdev = tp->pci_dev;
4398
cecb5fd7
FR		 4399 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4400 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4401 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4402
4403 if (cap) {
4404 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4405 PCI_EXP_DEVCTL_NOSNOOP_EN);
4406 }
cdf1a608
FR		 4407 }
4408
d24e9aaf
HW		 4409 RTL_W8(Cfg9346, Cfg9346_Unlock);
4410
2857ffb7
FR		 4411 switch (tp->mac_version) {
4412 case RTL_GIGA_MAC_VER_07:
4413 rtl_hw_start_8102e_1(ioaddr, pdev);
4414 break;
4415
4416 case RTL_GIGA_MAC_VER_08:
4417 rtl_hw_start_8102e_3(ioaddr, pdev);
4418 break;
4419
4420 case RTL_GIGA_MAC_VER_09:
4421 rtl_hw_start_8102e_2(ioaddr, pdev);
4422 break;
5a5e4443
HW		 4423
4424 case RTL_GIGA_MAC_VER_29:
4425 rtl_hw_start_8105e_1(ioaddr, pdev);
4426 break;
4427 case RTL_GIGA_MAC_VER_30:
4428 rtl_hw_start_8105e_2(ioaddr, pdev);
4429 break;
cdf1a608
FR		 4430 }
4431
d24e9aaf 4432 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4433
f0298f81 4434 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4435
6f0333b8 4436 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4437
d24e9aaf 4438 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4439 RTL_W16(CPlusCmd, tp->cp_cmd);
4440
4441 RTL_W16(IntrMitigate, 0x0000);
4442
4443 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4444
4445 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4446 rtl_set_rx_tx_config_registers(tp);
4447
cdf1a608
FR		 4448 RTL_R8(IntrMask);
4449
cdf1a608
FR		 4450 rtl_set_rx_mode(dev);
4451
4452 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4453
0e485150 4454 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4455}
4456
4457static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4458{
1da177e4
LT		 4459 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4460 return -EINVAL;
4461
4462 dev->mtu = new_mtu;
350fb32a
MM		 4463 netdev_update_features(dev);
4464
323bb685 4465 return 0;
1da177e4
LT		 4466}
4467
4468static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4469{
95e0918d 4470 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4471 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4472}
4473
6f0333b8
ED		 4474static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4475 void **data_buff, struct RxDesc *desc)
1da177e4 4476{
48addcc9 4477 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4478 DMA_FROM_DEVICE);
48addcc9 4479
6f0333b8
ED		 4480 kfree(*data_buff);
4481 *data_buff = NULL;
1da177e4
LT		 4482 rtl8169_make_unusable_by_asic(desc);
4483}
4484
4485static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4486{
4487 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4488
4489 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4490}
4491
4492static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4493 u32 rx_buf_sz)
4494{
4495 desc->addr = cpu_to_le64(mapping);
4496 wmb();
4497 rtl8169_mark_to_asic(desc, rx_buf_sz);
4498}
4499
6f0333b8
ED		 4500static inline void *rtl8169_align(void *data)
4501{
4502 return (void *)ALIGN((long)data, 16);
4503}
4504
0ecbe1ca
SG		 4505static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4506 struct RxDesc *desc)
1da177e4 4507{
6f0333b8 4508 void *data;
1da177e4 4509 dma_addr_t mapping;
48addcc9 4510 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4511 struct net_device *dev = tp->dev;
6f0333b8 4512 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4513
6f0333b8
ED		 4514 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4515 if (!data)
4516 return NULL;
e9f63f30 4517
6f0333b8
ED		 4518 if (rtl8169_align(data) != data) {
4519 kfree(data);
4520 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4521 if (!data)
4522 return NULL;
4523 }
3eafe507 4524
48addcc9 4525 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4526 DMA_FROM_DEVICE);
d827d86b
SG		 4527 if (unlikely(dma_mapping_error(d, mapping))) {
4528 if (net_ratelimit())
4529 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4530 goto err_out;
d827d86b 4531 }
1da177e4
LT		 4532
4533 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4534 return data;
3eafe507
SG		 4535
4536err_out:
4537 kfree(data);
4538 return NULL;
1da177e4
LT		 4539}
4540
4541static void rtl8169_rx_clear(struct rtl8169_private *tp)
4542{
07d3f51f 4543 unsigned int i;
1da177e4
LT		 4544
4545 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4546 if (tp->Rx_databuff[i]) {
4547 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4548 tp->RxDescArray + i);
4549 }
4550 }
4551}
4552
0ecbe1ca 4553static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4554{
0ecbe1ca
SG		 4555 desc->opts1 |= cpu_to_le32(RingEnd);
4556}
5b0384f4 4557
0ecbe1ca
SG		 4558static int rtl8169_rx_fill(struct rtl8169_private *tp)
4559{
4560 unsigned int i;
1da177e4 4561
0ecbe1ca
SG		 4562 for (i = 0; i < NUM_RX_DESC; i++) {
4563 void *data;
4ae47c2d 4564
6f0333b8 4565 if (tp->Rx_databuff[i])
1da177e4 4566 continue;
bcf0bf90 4567
0ecbe1ca 4568 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4569 if (!data) {
4570 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4571 goto err_out;
6f0333b8
ED		 4572 }
4573 tp->Rx_databuff[i] = data;
1da177e4 4574 }
1da177e4 4575
0ecbe1ca
SG		 4576 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4577 return 0;
4578
4579err_out:
4580 rtl8169_rx_clear(tp);
4581 return -ENOMEM;
1da177e4
LT		 4582}
4583
4584static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4585{
4586 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4587}
4588
4589static int rtl8169_init_ring(struct net_device *dev)
4590{
4591 struct rtl8169_private *tp = netdev_priv(dev);
4592
4593 rtl8169_init_ring_indexes(tp);
4594
4595 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4596 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4597
0ecbe1ca 4598 return rtl8169_rx_fill(tp);
1da177e4
LT		 4599}
4600
48addcc9 4601static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4602 struct TxDesc *desc)
4603{
4604 unsigned int len = tx_skb->len;
4605
48addcc9
SG		 4606 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4607
1da177e4
LT		 4608 desc->opts1 = 0x00;
4609 desc->opts2 = 0x00;
4610 desc->addr = 0x00;
4611 tx_skb->len = 0;
4612}
4613
3eafe507
SG		 4614static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4615 unsigned int n)
1da177e4
LT		 4616{
4617 unsigned int i;
4618
3eafe507
SG		 4619 for (i = 0; i < n; i++) {
4620 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4621 struct ring_info *tx_skb = tp->tx_skb + entry;
4622 unsigned int len = tx_skb->len;
4623
4624 if (len) {
4625 struct sk_buff *skb = tx_skb->skb;
4626
48addcc9 4627 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4628 tp->TxDescArray + entry);
4629 if (skb) {
cac4b22f 4630 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4631 dev_kfree_skb(skb);
4632 tx_skb->skb = NULL;
4633 }
1da177e4
LT		 4634 }
4635 }
3eafe507
SG		 4636}
4637
4638static void rtl8169_tx_clear(struct rtl8169_private *tp)
4639{
4640 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4641 tp->cur_tx = tp->dirty_tx = 0;
4642}
4643
c4028958 4644static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4645{
4646 struct rtl8169_private *tp = netdev_priv(dev);
4647
c4028958 4648 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4649 schedule_delayed_work(&tp->task, 4);
4650}
4651
4652static void rtl8169_wait_for_quiescence(struct net_device *dev)
4653{
4654 struct rtl8169_private *tp = netdev_priv(dev);
4655 void __iomem *ioaddr = tp->mmio_addr;
4656
4657 synchronize_irq(dev->irq);
4658
4659 /* Wait for any pending NAPI task to complete */
bea3348e 4660 napi_disable(&tp->napi);
1da177e4
LT		 4661
4662 rtl8169_irq_mask_and_ack(ioaddr);
4663
d1d08d12
DM		 4664 tp->intr_mask = 0xffff;
4665 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4666 napi_enable(&tp->napi);
1da177e4
LT		 4667}
4668
c4028958 4669static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4670{
c4028958
DH		 4671 struct rtl8169_private *tp =
4672 container_of(work, struct rtl8169_private, task.work);
4673 struct net_device *dev = tp->dev;
1da177e4
LT		 4674 int ret;
4675
eb2a021c
FR		 4676 rtnl_lock();
4677
4678 if (!netif_running(dev))
4679 goto out_unlock;
4680
4681 rtl8169_wait_for_quiescence(dev);
4682 rtl8169_close(dev);
1da177e4
LT		 4683
4684 ret = rtl8169_open(dev);
4685 if (unlikely(ret < 0)) {
bf82c189
JP		 4686 if (net_ratelimit())
4687 netif_err(tp, drv, dev,
4688 "reinit failure (status = %d). Rescheduling\n",
4689 ret);
1da177e4
LT		 4690 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4691 }
eb2a021c
FR		 4692
4693out_unlock:
4694 rtnl_unlock();
1da177e4
LT		 4695}
4696
c4028958 4697static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4698{
c4028958
DH		 4699 struct rtl8169_private *tp =
4700 container_of(work, struct rtl8169_private, task.work);
4701 struct net_device *dev = tp->dev;
56de414c 4702 int i;
1da177e4 4703
eb2a021c
FR		 4704 rtnl_lock();
4705
1da177e4 4706 if (!netif_running(dev))
eb2a021c 4707 goto out_unlock;
1da177e4
LT		 4708
4709 rtl8169_wait_for_quiescence(dev);
4710
56de414c
FR		 4711 for (i = 0; i < NUM_RX_DESC; i++)
4712 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4713
1da177e4
LT		 4714 rtl8169_tx_clear(tp);
4715
56de414c
FR		 4716 rtl8169_init_ring_indexes(tp);
4717 rtl_hw_start(dev);
4718 netif_wake_queue(dev);
4719 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4720
4721out_unlock:
4722 rtnl_unlock();
1da177e4
LT		 4723}
4724
4725static void rtl8169_tx_timeout(struct net_device *dev)
4726{
4727 struct rtl8169_private *tp = netdev_priv(dev);
4728
e6de30d6 4729 rtl8169_hw_reset(tp);
1da177e4
LT		 4730
4731 /* Let's wait a bit while any (async) irq lands on */
4732 rtl8169_schedule_work(dev, rtl8169_reset_task);
4733}
4734
4735static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4736 u32 *opts)
1da177e4
LT		 4737{
4738 struct skb_shared_info *info = skb_shinfo(skb);
4739 unsigned int cur_frag, entry;
a6343afb 4740 struct TxDesc * uninitialized_var(txd);
48addcc9 4741 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4742
4743 entry = tp->cur_tx;
4744 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4745 skb_frag_t *frag = info->frags + cur_frag;
4746 dma_addr_t mapping;
4747 u32 status, len;
4748 void *addr;
4749
4750 entry = (entry + 1) % NUM_TX_DESC;
4751
4752 txd = tp->TxDescArray + entry;
4753 len = frag->size;
4754 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4755 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4756 if (unlikely(dma_mapping_error(d, mapping))) {
4757 if (net_ratelimit())
4758 netif_err(tp, drv, tp->dev,
4759 "Failed to map TX fragments DMA!\n");
3eafe507 4760 goto err_out;
d827d86b 4761 }
1da177e4 4762
cecb5fd7 4763 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4764 status = opts[0] | len |
4765 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4766
4767 txd->opts1 = cpu_to_le32(status);
2b7b4318 4768 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4769 txd->addr = cpu_to_le64(mapping);
4770
4771 tp->tx_skb[entry].len = len;
4772 }
4773
4774 if (cur_frag) {
4775 tp->tx_skb[entry].skb = skb;
4776 txd->opts1 |= cpu_to_le32(LastFrag);
4777 }
4778
4779 return cur_frag;
3eafe507
SG		 4780
4781err_out:
4782 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4783 return -EIO;
1da177e4
LT		 4784}
4785
2b7b4318
FR		 4786static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4787 struct sk_buff *skb, u32 *opts)
1da177e4 4788{
2b7b4318 4789 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4790 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4791 int offset = info->opts_offset;
350fb32a 4792
2b7b4318
FR		 4793 if (mss) {
4794 opts[0] |= TD_LSO;
4795 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4796 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4797 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4798
4799 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4800 opts[offset] |= info->checksum.tcp;
1da177e4 4801 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4802 opts[offset] |= info->checksum.udp;
4803 else
4804 WARN_ON_ONCE(1);
1da177e4 4805 }
1da177e4
LT		 4806}
4807
61357325
SH		 4808static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4809 struct net_device *dev)
1da177e4
LT		 4810{
4811 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4812 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4813 struct TxDesc *txd = tp->TxDescArray + entry;
4814 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4815 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4816 dma_addr_t mapping;
4817 u32 status, len;
2b7b4318 4818 u32 opts[2];
3eafe507 4819 int frags;
5b0384f4 4820
1da177e4 4821 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4822 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4823 goto err_stop_0;
1da177e4
LT		 4824 }
4825
4826 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4827 goto err_stop_0;
4828
4829 len = skb_headlen(skb);
48addcc9 4830 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4831 if (unlikely(dma_mapping_error(d, mapping))) {
4832 if (net_ratelimit())
4833 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4834 goto err_dma_0;
d827d86b 4835 }
3eafe507
SG		 4836
4837 tp->tx_skb[entry].len = len;
4838 txd->addr = cpu_to_le64(mapping);
1da177e4 4839
2b7b4318
FR		 4840 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4841 opts[0] = DescOwn;
1da177e4 4842
2b7b4318
FR		 4843 rtl8169_tso_csum(tp, skb, opts);
4844
4845 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4846 if (frags < 0)
4847 goto err_dma_1;
4848 else if (frags)
2b7b4318 4849 opts[0] |= FirstFrag;
3eafe507 4850 else {
2b7b4318 4851 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4852 tp->tx_skb[entry].skb = skb;
4853 }
4854
2b7b4318
FR		 4855 txd->opts2 = cpu_to_le32(opts[1]);
4856
1da177e4
LT		 4857 wmb();
4858
cecb5fd7 4859 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 4860 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4861 txd->opts1 = cpu_to_le32(status);
4862
1da177e4
LT		 4863 tp->cur_tx += frags + 1;
4864
4c020a96 4865 wmb();
1da177e4 4866
cecb5fd7 4867 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4868
4869 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4870 netif_stop_queue(dev);
4871 smp_rmb();
4872 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4873 netif_wake_queue(dev);
4874 }
4875
61357325 4876 return NETDEV_TX_OK;
1da177e4 4877
3eafe507 4878err_dma_1:
48addcc9 4879 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4880err_dma_0:
4881 dev_kfree_skb(skb);
4882 dev->stats.tx_dropped++;
4883 return NETDEV_TX_OK;
4884
4885err_stop_0:
1da177e4 4886 netif_stop_queue(dev);
cebf8cc7 4887 dev->stats.tx_dropped++;
61357325 4888 return NETDEV_TX_BUSY;
1da177e4
LT		 4889}
4890
4891static void rtl8169_pcierr_interrupt(struct net_device *dev)
4892{
4893 struct rtl8169_private *tp = netdev_priv(dev);
4894 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4895 u16 pci_status, pci_cmd;
4896
4897 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4898 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4899
bf82c189
JP		 4900 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4901 pci_cmd, pci_status);
1da177e4
LT		 4902
4903 /*
4904 * The recovery sequence below admits a very elaborated explanation:
4905 * - it seems to work;
d03902b8
FR		 4906 * - I did not see what else could be done;
4907 * - it makes iop3xx happy.
1da177e4
LT		 4908 *
4909 * Feel free to adjust to your needs.
4910 */
a27993f3 4911 if (pdev->broken_parity_status)
d03902b8
FR		 4912 pci_cmd &= ~PCI_COMMAND_PARITY;
4913 else
4914 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4915
4916 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4917
4918 pci_write_config_word(pdev, PCI_STATUS,
4919 pci_status & (PCI_STATUS_DETECTED_PARITY |
4920 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4921 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4922
4923 /* The infamous DAC f*ckup only happens at boot time */
4924 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4925 void __iomem *ioaddr = tp->mmio_addr;
4926
bf82c189 4927 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4928 tp->cp_cmd &= ~PCIDAC;
4929 RTL_W16(CPlusCmd, tp->cp_cmd);
4930 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4931 }
4932
e6de30d6 4933 rtl8169_hw_reset(tp);
d03902b8
FR		 4934
4935 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4936}
4937
07d3f51f
FR		 4938static void rtl8169_tx_interrupt(struct net_device *dev,
4939 struct rtl8169_private *tp,
4940 void __iomem *ioaddr)
1da177e4
LT		 4941{
4942 unsigned int dirty_tx, tx_left;
4943
1da177e4
LT		 4944 dirty_tx = tp->dirty_tx;
4945 smp_rmb();
4946 tx_left = tp->cur_tx - dirty_tx;
4947
4948 while (tx_left > 0) {
4949 unsigned int entry = dirty_tx % NUM_TX_DESC;
4950 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4951 u32 status;
4952
4953 rmb();
4954 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4955 if (status & DescOwn)
4956 break;
4957
48addcc9
SG		 4958 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4959 tp->TxDescArray + entry);
1da177e4 4960 if (status & LastFrag) {
cac4b22f
SG		 4961 dev->stats.tx_packets++;
4962 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4963 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4964 tx_skb->skb = NULL;
4965 }
4966 dirty_tx++;
4967 tx_left--;
4968 }
4969
4970 if (tp->dirty_tx != dirty_tx) {
4971 tp->dirty_tx = dirty_tx;
4972 smp_wmb();
4973 if (netif_queue_stopped(dev) &&
4974 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4975 netif_wake_queue(dev);
4976 }
d78ae2dc
FR		 4977 /*
4978 * 8168 hack: TxPoll requests are lost when the Tx packets are
4979 * too close. Let's kick an extra TxPoll request when a burst
4980 * of start_xmit activity is detected (if it is not detected,
4981 * it is slow enough). -- FR
4982 */
4983 smp_rmb();
4984 if (tp->cur_tx != dirty_tx)
4985 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4986 }
4987}
4988
126fa4b9
FR		 4989static inline int rtl8169_fragmented_frame(u32 status)
4990{
4991 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4992}
4993
adea1ac7 4994static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4995{
1da177e4
LT		 4996 u32 status = opts1 & RxProtoMask;
4997
4998 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4999 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5000 skb->ip_summed = CHECKSUM_UNNECESSARY;
5001 else
bc8acf2c 5002 skb_checksum_none_assert(skb);
1da177e4
LT		 5003}
5004
6f0333b8
ED		 5005static struct sk_buff *rtl8169_try_rx_copy(void *data,
5006 struct rtl8169_private *tp,
5007 int pkt_size,
5008 dma_addr_t addr)
1da177e4 5009{
b449655f 5010 struct sk_buff *skb;
48addcc9 5011 struct device *d = &tp->pci_dev->dev;
b449655f 5012
6f0333b8 5013 data = rtl8169_align(data);
48addcc9 5014 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5015 prefetch(data);
5016 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5017 if (skb)
5018 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5019 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5020
6f0333b8 5021 return skb;
1da177e4
LT		 5022}
5023
07d3f51f
FR		 5024static int rtl8169_rx_interrupt(struct net_device *dev,
5025 struct rtl8169_private *tp,
bea3348e 5026 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5027{
5028 unsigned int cur_rx, rx_left;
6f0333b8 5029 unsigned int count;
1da177e4 5030
1da177e4
LT		 5031 cur_rx = tp->cur_rx;
5032 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5033 rx_left = min(rx_left, budget);
1da177e4 5034
4dcb7d33 5035 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5036 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5037 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5038 u32 status;
5039
5040 rmb();
126fa4b9 5041 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 5042
5043 if (status & DescOwn)
5044 break;
4dcb7d33 5045 if (unlikely(status & RxRES)) {
bf82c189
JP		 5046 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5047 status);
cebf8cc7 5048 dev->stats.rx_errors++;
1da177e4 5049 if (status & (RxRWT | RxRUNT))
cebf8cc7 5050 dev->stats.rx_length_errors++;
1da177e4 5051 if (status & RxCRC)
cebf8cc7 5052 dev->stats.rx_crc_errors++;
9dccf611
FR		 5053 if (status & RxFOVF) {
5054 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5055 dev->stats.rx_fifo_errors++;
9dccf611 5056 }
6f0333b8 5057 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5058 } else {
6f0333b8 5059 struct sk_buff *skb;
b449655f 5060 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 5061 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 5062
126fa4b9
FR		 5063 /*
5064 * The driver does not support incoming fragmented
5065 * frames. They are seen as a symptom of over-mtu
5066 * sized frames.
5067 */
5068 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5069 dev->stats.rx_dropped++;
5070 dev->stats.rx_length_errors++;
6f0333b8 5071 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5072 continue;
126fa4b9
FR		 5073 }
5074
6f0333b8
ED		 5075 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5076 tp, pkt_size, addr);
5077 rtl8169_mark_to_asic(desc, rx_buf_sz);
5078 if (!skb) {
5079 dev->stats.rx_dropped++;
5080 continue;
1da177e4
LT		 5081 }
5082
adea1ac7 5083 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5084 skb_put(skb, pkt_size);
5085 skb->protocol = eth_type_trans(skb, dev);
5086
7a8fc77b
FR		 5087 rtl8169_rx_vlan_tag(desc, skb);
5088
56de414c 5089 napi_gro_receive(&tp->napi, skb);
1da177e4 5090
cebf8cc7
FR		 5091 dev->stats.rx_bytes += pkt_size;
5092 dev->stats.rx_packets++;
1da177e4 5093 }
6dccd16b
FR		 5094
5095 /* Work around for AMD plateform. */
95e0918d 5096 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5097 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5098 desc->opts2 = 0;
5099 cur_rx++;
5100 }
1da177e4
LT		 5101 }
5102
5103 count = cur_rx - tp->cur_rx;
5104 tp->cur_rx = cur_rx;
5105
6f0333b8 5106 tp->dirty_rx += count;
1da177e4
LT		 5107
5108 return count;
5109}
5110
07d3f51f 5111static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5112{
07d3f51f 5113 struct net_device *dev = dev_instance;
1da177e4 5114 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5115 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5116 int handled = 0;
865c652d 5117 int status;
1da177e4 5118
f11a377b
DD		 5119 /* loop handling interrupts until we have no new ones or
5120 * we hit a invalid/hotplug case.
5121 */
865c652d 5122 status = RTL_R16(IntrStatus);
f11a377b
DD		 5123 while (status && status != 0xffff) {
5124 handled = 1;
1da177e4 5125
f11a377b
DD		 5126 /* Handle all of the error cases first. These will reset
5127 * the chip, so just exit the loop.
5128 */
5129 if (unlikely(!netif_running(dev))) {
5130 rtl8169_asic_down(ioaddr);
5131 break;
5132 }
1da177e4 5133
1519e57f
FR		 5134 if (unlikely(status & RxFIFOOver)) {
5135 switch (tp->mac_version) {
5136 /* Work around for rx fifo overflow */
5137 case RTL_GIGA_MAC_VER_11:
5138 case RTL_GIGA_MAC_VER_22:
5139 case RTL_GIGA_MAC_VER_26:
5140 netif_stop_queue(dev);
5141 rtl8169_tx_timeout(dev);
5142 goto done;
f60ac8e7
FR		 5143 /* Testers needed. */
5144 case RTL_GIGA_MAC_VER_17:
5145 case RTL_GIGA_MAC_VER_19:
5146 case RTL_GIGA_MAC_VER_20:
5147 case RTL_GIGA_MAC_VER_21:
5148 case RTL_GIGA_MAC_VER_23:
5149 case RTL_GIGA_MAC_VER_24:
5150 case RTL_GIGA_MAC_VER_27:
5151 case RTL_GIGA_MAC_VER_28:
4804b3b3 5152 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5153 /* Experimental science. Pktgen proof. */
5154 case RTL_GIGA_MAC_VER_12:
5155 case RTL_GIGA_MAC_VER_25:
5156 if (status == RxFIFOOver)
5157 goto done;
5158 break;
5159 default:
5160 break;
5161 }
f11a377b 5162 }
1da177e4 5163
f11a377b
DD		 5164 if (unlikely(status & SYSErr)) {
5165 rtl8169_pcierr_interrupt(dev);
5166 break;
5167 }
1da177e4 5168
f11a377b 5169 if (status & LinkChg)
e4fbce74 5170 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5171
f11a377b
DD		 5172 /* We need to see the lastest version of tp->intr_mask to
5173 * avoid ignoring an MSI interrupt and having to wait for
5174 * another event which may never come.
5175 */
5176 smp_rmb();
5177 if (status & tp->intr_mask & tp->napi_event) {
5178 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5179 tp->intr_mask = ~tp->napi_event;
5180
5181 if (likely(napi_schedule_prep(&tp->napi)))
5182 __napi_schedule(&tp->napi);
bf82c189
JP		 5183 else
5184 netif_info(tp, intr, dev,
5185 "interrupt %04x in poll\n", status);
f11a377b 5186 }
1da177e4 5187
f11a377b
DD		 5188 /* We only get a new MSI interrupt when all active irq
5189 * sources on the chip have been acknowledged. So, ack
5190 * everything we've seen and check if new sources have become
5191 * active to avoid blocking all interrupts from the chip.
5192 */
5193 RTL_W16(IntrStatus,
5194 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5195 status = RTL_R16(IntrStatus);
865c652d 5196 }
1519e57f 5197done:
1da177e4
LT		 5198 return IRQ_RETVAL(handled);
5199}
5200
bea3348e 5201static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5202{
bea3348e
SH		 5203 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5204 struct net_device *dev = tp->dev;
1da177e4 5205 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5206 int work_done;
1da177e4 5207
bea3348e 5208 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5209 rtl8169_tx_interrupt(dev, tp, ioaddr);
5210
bea3348e 5211 if (work_done < budget) {
288379f0 5212 napi_complete(napi);
f11a377b
DD		 5213
5214 /* We need for force the visibility of tp->intr_mask
5215 * for other CPUs, as we can loose an MSI interrupt
5216 * and potentially wait for a retransmit timeout if we don't.
5217 * The posted write to IntrMask is safe, as it will
5218 * eventually make it to the chip and we won't loose anything
5219 * until it does.
1da177e4 5220 */
f11a377b 5221 tp->intr_mask = 0xffff;
4c020a96 5222 wmb();
0e485150 5223 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5224 }
5225
bea3348e 5226 return work_done;
1da177e4 5227}
1da177e4 5228
523a6094
FR		 5229static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5230{
5231 struct rtl8169_private *tp = netdev_priv(dev);
5232
5233 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5234 return;
5235
5236 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5237 RTL_W32(RxMissed, 0);
5238}
5239
1da177e4
LT		 5240static void rtl8169_down(struct net_device *dev)
5241{
5242 struct rtl8169_private *tp = netdev_priv(dev);
5243 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5244
4876cc1e 5245 del_timer_sync(&tp->timer);
1da177e4
LT		 5246
5247 netif_stop_queue(dev);
5248
93dd79e8 5249 napi_disable(&tp->napi);
93dd79e8 5250
1da177e4
LT		 5251 spin_lock_irq(&tp->lock);
5252
5253 rtl8169_asic_down(ioaddr);
323bb685
SG		 5254 /*
5255 * At this point device interrupts can not be enabled in any function,
5256 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5257 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5258 */
523a6094 5259 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5260
5261 spin_unlock_irq(&tp->lock);
5262
5263 synchronize_irq(dev->irq);
5264
1da177e4 5265 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5266 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5267
1da177e4
LT		 5268 rtl8169_tx_clear(tp);
5269
5270 rtl8169_rx_clear(tp);
065c27c1 5271
5272 rtl_pll_power_down(tp);
1da177e4
LT		 5273}
5274
5275static int rtl8169_close(struct net_device *dev)
5276{
5277 struct rtl8169_private *tp = netdev_priv(dev);
5278 struct pci_dev *pdev = tp->pci_dev;
5279
e1759441
RW		 5280 pm_runtime_get_sync(&pdev->dev);
5281
cecb5fd7 5282 /* Update counters before going down */
355423d0
IV		 5283 rtl8169_update_counters(dev);
5284
1da177e4
LT		 5285 rtl8169_down(dev);
5286
5287 free_irq(dev->irq, dev);
5288
82553bb6
SG		 5289 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5290 tp->RxPhyAddr);
5291 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5292 tp->TxPhyAddr);
1da177e4
LT		 5293 tp->TxDescArray = NULL;
5294 tp->RxDescArray = NULL;
5295
e1759441
RW		 5296 pm_runtime_put_sync(&pdev->dev);
5297
1da177e4
LT		 5298 return 0;
5299}
5300
07ce4064 5301static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5302{
5303 struct rtl8169_private *tp = netdev_priv(dev);
5304 void __iomem *ioaddr = tp->mmio_addr;
5305 unsigned long flags;
5306 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5307 int rx_mode;
1da177e4
LT		 5308 u32 tmp = 0;
5309
5310 if (dev->flags & IFF_PROMISC) {
5311 /* Unconditionally log net taps. */
bf82c189 5312 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5313 rx_mode =
5314 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5315 AcceptAllPhys;
5316 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5317 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5318 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5319 /* Too many to filter perfectly -- accept all multicasts. */
5320 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5321 mc_filter[1] = mc_filter[0] = 0xffffffff;
5322 } else {
22bedad3 5323 struct netdev_hw_addr *ha;
07d3f51f 5324
1da177e4
LT		 5325 rx_mode = AcceptBroadcast | AcceptMyPhys;
5326 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5327 netdev_for_each_mc_addr(ha, dev) {
5328 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5329 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5330 rx_mode |= AcceptMulticast;
5331 }
5332 }
5333
5334 spin_lock_irqsave(&tp->lock, flags);
5335
5336 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5337 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5338
f887cce8 5339 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5340 u32 data = mc_filter[0];
5341
5342 mc_filter[0] = swab32(mc_filter[1]);
5343 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5344 }
5345
1da177e4 5346 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5347 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5348
57a9f236
FR		 5349 RTL_W32(RxConfig, tmp);
5350
1da177e4
LT		 5351 spin_unlock_irqrestore(&tp->lock, flags);
5352}
5353
5354/**
5355 * rtl8169_get_stats - Get rtl8169 read/write statistics
5356 * @dev: The Ethernet Device to get statistics for
5357 *
5358 * Get TX/RX statistics for rtl8169
5359 */
5360static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5361{
5362 struct rtl8169_private *tp = netdev_priv(dev);
5363 void __iomem *ioaddr = tp->mmio_addr;
5364 unsigned long flags;
5365
5366 if (netif_running(dev)) {
5367 spin_lock_irqsave(&tp->lock, flags);
523a6094 5368 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5369 spin_unlock_irqrestore(&tp->lock, flags);
5370 }
5b0384f4 5371
cebf8cc7 5372 return &dev->stats;
1da177e4
LT		 5373}
5374
861ab440 5375static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5376{
065c27c1 5377 struct rtl8169_private *tp = netdev_priv(dev);
5378
5d06a99f 5379 if (!netif_running(dev))
861ab440 5380 return;
5d06a99f 5381
065c27c1 5382 rtl_pll_power_down(tp);
5383
5d06a99f
FR		 5384 netif_device_detach(dev);
5385 netif_stop_queue(dev);
861ab440
RW		 5386}
5387
5388#ifdef CONFIG_PM
5389
5390static int rtl8169_suspend(struct device *device)
5391{
5392 struct pci_dev *pdev = to_pci_dev(device);
5393 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5394
861ab440 5395 rtl8169_net_suspend(dev);
1371fa6d 5396
5d06a99f
FR		 5397 return 0;
5398}
5399
e1759441
RW		 5400static void __rtl8169_resume(struct net_device *dev)
5401{
065c27c1 5402 struct rtl8169_private *tp = netdev_priv(dev);
5403
e1759441 5404 netif_device_attach(dev);
065c27c1 5405
5406 rtl_pll_power_up(tp);
5407
e1759441
RW		 5408 rtl8169_schedule_work(dev, rtl8169_reset_task);
5409}
5410
861ab440 5411static int rtl8169_resume(struct device *device)
5d06a99f 5412{
861ab440 5413 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5414 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5415 struct rtl8169_private *tp = netdev_priv(dev);
5416
5417 rtl8169_init_phy(dev, tp);
5d06a99f 5418
e1759441
RW		 5419 if (netif_running(dev))
5420 __rtl8169_resume(dev);
5d06a99f 5421
e1759441
RW		 5422 return 0;
5423}
5424
5425static int rtl8169_runtime_suspend(struct device *device)
5426{
5427 struct pci_dev *pdev = to_pci_dev(device);
5428 struct net_device *dev = pci_get_drvdata(pdev);
5429 struct rtl8169_private *tp = netdev_priv(dev);
5430
5431 if (!tp->TxDescArray)
5432 return 0;
5433
5434 spin_lock_irq(&tp->lock);
5435 tp->saved_wolopts = __rtl8169_get_wol(tp);
5436 __rtl8169_set_wol(tp, WAKE_ANY);
5437 spin_unlock_irq(&tp->lock);
5438
5439 rtl8169_net_suspend(dev);
5440
5441 return 0;
5442}
5443
5444static int rtl8169_runtime_resume(struct device *device)
5445{
5446 struct pci_dev *pdev = to_pci_dev(device);
5447 struct net_device *dev = pci_get_drvdata(pdev);
5448 struct rtl8169_private *tp = netdev_priv(dev);
5449
5450 if (!tp->TxDescArray)
5451 return 0;
5452
5453 spin_lock_irq(&tp->lock);
5454 __rtl8169_set_wol(tp, tp->saved_wolopts);
5455 tp->saved_wolopts = 0;
5456 spin_unlock_irq(&tp->lock);
5457
fccec10b
SG		 5458 rtl8169_init_phy(dev, tp);
5459
e1759441 5460 __rtl8169_resume(dev);
5d06a99f 5461
5d06a99f
FR		 5462 return 0;
5463}
5464
e1759441
RW		 5465static int rtl8169_runtime_idle(struct device *device)
5466{
5467 struct pci_dev *pdev = to_pci_dev(device);
5468 struct net_device *dev = pci_get_drvdata(pdev);
5469 struct rtl8169_private *tp = netdev_priv(dev);
5470
e4fbce74 5471 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5472}
5473
47145210 5474static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5475 .suspend = rtl8169_suspend,
5476 .resume = rtl8169_resume,
5477 .freeze = rtl8169_suspend,
5478 .thaw = rtl8169_resume,
5479 .poweroff = rtl8169_suspend,
5480 .restore = rtl8169_resume,
5481 .runtime_suspend = rtl8169_runtime_suspend,
5482 .runtime_resume = rtl8169_runtime_resume,
5483 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5484};
5485
5486#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5487
5488#else /* !CONFIG_PM */
5489
5490#define RTL8169_PM_OPS NULL
5491
5492#endif /* !CONFIG_PM */
5493
1765f95d
FR		 5494static void rtl_shutdown(struct pci_dev *pdev)
5495{
861ab440 5496 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5497 struct rtl8169_private *tp = netdev_priv(dev);
5498 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5499
5500 rtl8169_net_suspend(dev);
1765f95d 5501
cecb5fd7 5502 /* Restore original MAC address */
cc098dc7
IV		 5503 rtl_rar_set(tp, dev->perm_addr);
5504
4bb3f522 5505 spin_lock_irq(&tp->lock);
5506
5507 rtl8169_asic_down(ioaddr);
5508
5509 spin_unlock_irq(&tp->lock);
5510
861ab440 5511 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5512 /* WoL fails with some 8168 when the receiver is disabled. */
5513 if (tp->features & RTL_FEATURE_WOL) {
5514 pci_clear_master(pdev);
5515
5516 RTL_W8(ChipCmd, CmdRxEnb);
5517 /* PCI commit */
5518 RTL_R8(ChipCmd);
5519 }
5520
861ab440
RW		 5521 pci_wake_from_d3(pdev, true);
5522 pci_set_power_state(pdev, PCI_D3hot);
5523 }
5524}
5d06a99f 5525
1da177e4
LT		 5526static struct pci_driver rtl8169_pci_driver = {
5527 .name = MODULENAME,
5528 .id_table = rtl8169_pci_tbl,
5529 .probe = rtl8169_init_one,
5530 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5531 .shutdown = rtl_shutdown,
861ab440 5532 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5533};
5534
07d3f51f 5535static int __init rtl8169_init_module(void)
1da177e4 5536{
29917620 5537 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5538}
5539
07d3f51f 5540static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5541{
5542 pci_unregister_driver(&rtl8169_pci_driver);
5543}
5544
5545module_init(rtl8169_init_module);
5546module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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