Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | ||
99f252b0 | 27 | #include <asm/system.h> |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/irq.h> | |
30 | ||
865c652d | 31 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
32 | #define MODULENAME "r8169" |
33 | #define PFX MODULENAME ": " | |
34 | ||
35 | #ifdef RTL8169_DEBUG | |
36 | #define assert(expr) \ | |
5b0384f4 FR |
37 | if (!(expr)) { \ |
38 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 39 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 40 | } |
06fa7358 JP |
41 | #define dprintk(fmt, args...) \ |
42 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
43 | #else |
44 | #define assert(expr) do {} while (0) | |
45 | #define dprintk(fmt, args...) do {} while (0) | |
46 | #endif /* RTL8169_DEBUG */ | |
47 | ||
b57b7e5a | 48 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 49 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 50 | |
1da177e4 LT |
51 | #define TX_BUFFS_AVAIL(tp) \ |
52 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
53 | ||
1da177e4 | 54 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
f71e1309 | 55 | static const int max_interrupt_work = 20; |
1da177e4 LT |
56 | |
57 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
58 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 59 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
60 | |
61 | /* MAC address length */ | |
62 | #define MAC_ADDR_LEN 6 | |
63 | ||
9c14ceaf | 64 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 LT |
65 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
66 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
67 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
07d3f51f | 68 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
1da177e4 LT |
69 | #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
70 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ | |
71 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
72 | ||
73 | #define R8169_REGS_SIZE 256 | |
74 | #define R8169_NAPI_WEIGHT 64 | |
75 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
76 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
77 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
78 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
79 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
80 | ||
81 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
82 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
83 | ||
84 | /* write/read MMIO register */ | |
85 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
86 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
87 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
88 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
89 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
90 | #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) | |
91 | ||
92 | enum mac_version { | |
ba6eb6ee FR |
93 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
94 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
95 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
96 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
97 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 98 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2857ffb7 FR |
99 | RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
100 | RTL_GIGA_MAC_VER_08 = 0x08, // 8102e | |
101 | RTL_GIGA_MAC_VER_09 = 0x09, // 8102e | |
102 | RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e | |
2dd99530 | 103 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
e3cf0cc0 FR |
104 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
105 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb | |
106 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? | |
107 | RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? | |
108 | RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec | |
109 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | |
110 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | |
111 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | |
197ff761 | 112 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
6fb07058 | 113 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
ef3386f0 | 114 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
7f3e3d3a | 115 | RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
5b538df9 FR |
116 | RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
117 | RTL_GIGA_MAC_VER_25 = 0x19 // 8168D | |
1da177e4 LT |
118 | }; |
119 | ||
1da177e4 LT |
120 | #define _R(NAME,MAC,MASK) \ |
121 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
122 | ||
3c6bee1d | 123 | static const struct { |
1da177e4 LT |
124 | const char *name; |
125 | u8 mac_version; | |
126 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
127 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
128 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
129 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
130 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
131 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
132 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 133 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
2857ffb7 FR |
134 | _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
135 | _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E | |
136 | _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E | |
137 | _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E | |
bcf0bf90 FR |
138 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
139 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
140 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
141 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
e3cf0cc0 FR |
142 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
143 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E | |
144 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | |
145 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | |
146 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | |
197ff761 | 147 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
6fb07058 | 148 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
ef3386f0 | 149 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
7f3e3d3a | 150 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
5b538df9 FR |
151 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
152 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E | |
1da177e4 LT |
153 | }; |
154 | #undef _R | |
155 | ||
bcf0bf90 FR |
156 | enum cfg_version { |
157 | RTL_CFG_0 = 0x00, | |
158 | RTL_CFG_1, | |
159 | RTL_CFG_2 | |
160 | }; | |
161 | ||
07ce4064 FR |
162 | static void rtl_hw_start_8169(struct net_device *); |
163 | static void rtl_hw_start_8168(struct net_device *); | |
164 | static void rtl_hw_start_8101(struct net_device *); | |
165 | ||
1da177e4 | 166 | static struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 167 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 168 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 169 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 170 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
171 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
172 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
bc1660b5 | 173 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
174 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
175 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
176 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
177 | { 0x0001, 0x8168, |
178 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
179 | {0,}, |
180 | }; | |
181 | ||
182 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
183 | ||
184 | static int rx_copybreak = 200; | |
185 | static int use_dac; | |
b57b7e5a SH |
186 | static struct { |
187 | u32 msg_enable; | |
188 | } debug = { -1 }; | |
1da177e4 | 189 | |
07d3f51f FR |
190 | enum rtl_registers { |
191 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 192 | MAC4 = 4, |
07d3f51f FR |
193 | MAR0 = 8, /* Multicast filter. */ |
194 | CounterAddrLow = 0x10, | |
195 | CounterAddrHigh = 0x14, | |
196 | TxDescStartAddrLow = 0x20, | |
197 | TxDescStartAddrHigh = 0x24, | |
198 | TxHDescStartAddrLow = 0x28, | |
199 | TxHDescStartAddrHigh = 0x2c, | |
200 | FLASH = 0x30, | |
201 | ERSR = 0x36, | |
202 | ChipCmd = 0x37, | |
203 | TxPoll = 0x38, | |
204 | IntrMask = 0x3c, | |
205 | IntrStatus = 0x3e, | |
206 | TxConfig = 0x40, | |
207 | RxConfig = 0x44, | |
208 | RxMissed = 0x4c, | |
209 | Cfg9346 = 0x50, | |
210 | Config0 = 0x51, | |
211 | Config1 = 0x52, | |
212 | Config2 = 0x53, | |
213 | Config3 = 0x54, | |
214 | Config4 = 0x55, | |
215 | Config5 = 0x56, | |
216 | MultiIntr = 0x5c, | |
217 | PHYAR = 0x60, | |
07d3f51f FR |
218 | PHYstatus = 0x6c, |
219 | RxMaxSize = 0xda, | |
220 | CPlusCmd = 0xe0, | |
221 | IntrMitigate = 0xe2, | |
222 | RxDescAddrLow = 0xe4, | |
223 | RxDescAddrHigh = 0xe8, | |
224 | EarlyTxThres = 0xec, | |
225 | FuncEvent = 0xf0, | |
226 | FuncEventMask = 0xf4, | |
227 | FuncPresetState = 0xf8, | |
228 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
229 | }; |
230 | ||
f162a5d1 FR |
231 | enum rtl8110_registers { |
232 | TBICSR = 0x64, | |
233 | TBI_ANAR = 0x68, | |
234 | TBI_LPAR = 0x6a, | |
235 | }; | |
236 | ||
237 | enum rtl8168_8101_registers { | |
238 | CSIDR = 0x64, | |
239 | CSIAR = 0x68, | |
240 | #define CSIAR_FLAG 0x80000000 | |
241 | #define CSIAR_WRITE_CMD 0x80000000 | |
242 | #define CSIAR_BYTE_ENABLE 0x0f | |
243 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
244 | #define CSIAR_ADDR_MASK 0x0fff | |
245 | ||
246 | EPHYAR = 0x80, | |
247 | #define EPHYAR_FLAG 0x80000000 | |
248 | #define EPHYAR_WRITE_CMD 0x80000000 | |
249 | #define EPHYAR_REG_MASK 0x1f | |
250 | #define EPHYAR_REG_SHIFT 16 | |
251 | #define EPHYAR_DATA_MASK 0xffff | |
252 | DBG_REG = 0xd1, | |
253 | #define FIX_NAK_1 (1 << 4) | |
254 | #define FIX_NAK_2 (1 << 3) | |
255 | }; | |
256 | ||
07d3f51f | 257 | enum rtl_register_content { |
1da177e4 | 258 | /* InterruptStatusBits */ |
07d3f51f FR |
259 | SYSErr = 0x8000, |
260 | PCSTimeout = 0x4000, | |
261 | SWInt = 0x0100, | |
262 | TxDescUnavail = 0x0080, | |
263 | RxFIFOOver = 0x0040, | |
264 | LinkChg = 0x0020, | |
265 | RxOverflow = 0x0010, | |
266 | TxErr = 0x0008, | |
267 | TxOK = 0x0004, | |
268 | RxErr = 0x0002, | |
269 | RxOK = 0x0001, | |
1da177e4 LT |
270 | |
271 | /* RxStatusDesc */ | |
9dccf611 FR |
272 | RxFOVF = (1 << 23), |
273 | RxRWT = (1 << 22), | |
274 | RxRES = (1 << 21), | |
275 | RxRUNT = (1 << 20), | |
276 | RxCRC = (1 << 19), | |
1da177e4 LT |
277 | |
278 | /* ChipCmdBits */ | |
07d3f51f FR |
279 | CmdReset = 0x10, |
280 | CmdRxEnb = 0x08, | |
281 | CmdTxEnb = 0x04, | |
282 | RxBufEmpty = 0x01, | |
1da177e4 | 283 | |
275391a4 FR |
284 | /* TXPoll register p.5 */ |
285 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
286 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
287 | FSWInt = 0x01, /* Forced software interrupt */ | |
288 | ||
1da177e4 | 289 | /* Cfg9346Bits */ |
07d3f51f FR |
290 | Cfg9346_Lock = 0x00, |
291 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
292 | |
293 | /* rx_mode_bits */ | |
07d3f51f FR |
294 | AcceptErr = 0x20, |
295 | AcceptRunt = 0x10, | |
296 | AcceptBroadcast = 0x08, | |
297 | AcceptMulticast = 0x04, | |
298 | AcceptMyPhys = 0x02, | |
299 | AcceptAllPhys = 0x01, | |
1da177e4 LT |
300 | |
301 | /* RxConfigBits */ | |
07d3f51f FR |
302 | RxCfgFIFOShift = 13, |
303 | RxCfgDMAShift = 8, | |
1da177e4 LT |
304 | |
305 | /* TxConfigBits */ | |
306 | TxInterFrameGapShift = 24, | |
307 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
308 | ||
5d06a99f | 309 | /* Config1 register p.24 */ |
f162a5d1 FR |
310 | LEDS1 = (1 << 7), |
311 | LEDS0 = (1 << 6), | |
fbac58fc | 312 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
313 | Speed_down = (1 << 4), |
314 | MEMMAP = (1 << 3), | |
315 | IOMAP = (1 << 2), | |
316 | VPD = (1 << 1), | |
5d06a99f FR |
317 | PMEnable = (1 << 0), /* Power Management Enable */ |
318 | ||
6dccd16b FR |
319 | /* Config2 register p. 25 */ |
320 | PCI_Clock_66MHz = 0x01, | |
321 | PCI_Clock_33MHz = 0x00, | |
322 | ||
61a4dcc2 FR |
323 | /* Config3 register p.25 */ |
324 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
325 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
f162a5d1 | 326 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 327 | |
5d06a99f | 328 | /* Config5 register p.27 */ |
61a4dcc2 FR |
329 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
330 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
331 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
332 | LanWake = (1 << 1), /* LanWake enable/disable */ | |
5d06a99f FR |
333 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
334 | ||
1da177e4 LT |
335 | /* TBICSR p.28 */ |
336 | TBIReset = 0x80000000, | |
337 | TBILoopback = 0x40000000, | |
338 | TBINwEnable = 0x20000000, | |
339 | TBINwRestart = 0x10000000, | |
340 | TBILinkOk = 0x02000000, | |
341 | TBINwComplete = 0x01000000, | |
342 | ||
343 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
344 | EnableBist = (1 << 15), // 8168 8101 |
345 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
346 | Normal_mode = (1 << 13), // unused | |
347 | Force_half_dup = (1 << 12), // 8168 8101 | |
348 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
349 | Force_txflow_en = (1 << 10), // 8168 8101 | |
350 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
351 | ASF = (1 << 8), // 8168 8101 | |
352 | PktCntrDisable = (1 << 7), // 8168 8101 | |
353 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
354 | RxVlan = (1 << 6), |
355 | RxChkSum = (1 << 5), | |
356 | PCIDAC = (1 << 4), | |
357 | PCIMulRW = (1 << 3), | |
0e485150 FR |
358 | INTT_0 = 0x0000, // 8168 |
359 | INTT_1 = 0x0001, // 8168 | |
360 | INTT_2 = 0x0002, // 8168 | |
361 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
362 | |
363 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
364 | TBI_Enable = 0x80, |
365 | TxFlowCtrl = 0x40, | |
366 | RxFlowCtrl = 0x20, | |
367 | _1000bpsF = 0x10, | |
368 | _100bps = 0x08, | |
369 | _10bps = 0x04, | |
370 | LinkStatus = 0x02, | |
371 | FullDup = 0x01, | |
1da177e4 | 372 | |
1da177e4 | 373 | /* _TBICSRBit */ |
07d3f51f | 374 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
375 | |
376 | /* DumpCounterCommand */ | |
07d3f51f | 377 | CounterDump = 0x8, |
1da177e4 LT |
378 | }; |
379 | ||
07d3f51f | 380 | enum desc_status_bit { |
1da177e4 LT |
381 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
382 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
383 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
384 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
385 | ||
386 | /* Tx private */ | |
387 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ | |
388 | MSSShift = 16, /* MSS value position */ | |
389 | MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ | |
390 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
391 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
392 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
393 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
394 | ||
395 | /* Rx private */ | |
396 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
397 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
398 | ||
399 | #define RxProtoUDP (PID1) | |
400 | #define RxProtoTCP (PID0) | |
401 | #define RxProtoIP (PID1 | PID0) | |
402 | #define RxProtoMask RxProtoIP | |
403 | ||
404 | IPFail = (1 << 16), /* IP checksum failed */ | |
405 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
406 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
407 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
408 | }; | |
409 | ||
410 | #define RsvdMask 0x3fffc000 | |
411 | ||
412 | struct TxDesc { | |
6cccd6e7 REB |
413 | __le32 opts1; |
414 | __le32 opts2; | |
415 | __le64 addr; | |
1da177e4 LT |
416 | }; |
417 | ||
418 | struct RxDesc { | |
6cccd6e7 REB |
419 | __le32 opts1; |
420 | __le32 opts2; | |
421 | __le64 addr; | |
1da177e4 LT |
422 | }; |
423 | ||
424 | struct ring_info { | |
425 | struct sk_buff *skb; | |
426 | u32 len; | |
427 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
428 | }; | |
429 | ||
f23e7fda | 430 | enum features { |
ccdffb9a FR |
431 | RTL_FEATURE_WOL = (1 << 0), |
432 | RTL_FEATURE_MSI = (1 << 1), | |
433 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
434 | }; |
435 | ||
1da177e4 LT |
436 | struct rtl8169_private { |
437 | void __iomem *mmio_addr; /* memory map physical address */ | |
438 | struct pci_dev *pci_dev; /* Index of PCI device */ | |
c4028958 | 439 | struct net_device *dev; |
bea3348e | 440 | struct napi_struct napi; |
1da177e4 | 441 | spinlock_t lock; /* spin lock flag */ |
b57b7e5a | 442 | u32 msg_enable; |
1da177e4 LT |
443 | int chipset; |
444 | int mac_version; | |
1da177e4 LT |
445 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
446 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
447 | u32 dirty_rx; | |
448 | u32 dirty_tx; | |
449 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
450 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
451 | dma_addr_t TxPhyAddr; | |
452 | dma_addr_t RxPhyAddr; | |
453 | struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ | |
454 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ | |
bcf0bf90 | 455 | unsigned align; |
1da177e4 LT |
456 | unsigned rx_buf_sz; |
457 | struct timer_list timer; | |
458 | u16 cp_cmd; | |
0e485150 FR |
459 | u16 intr_event; |
460 | u16 napi_event; | |
1da177e4 LT |
461 | u16 intr_mask; |
462 | int phy_auto_nego_reg; | |
463 | int phy_1000_ctrl_reg; | |
464 | #ifdef CONFIG_R8169_VLAN | |
465 | struct vlan_group *vlgrp; | |
466 | #endif | |
467 | int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); | |
ccdffb9a | 468 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
1da177e4 | 469 | void (*phy_reset_enable)(void __iomem *); |
07ce4064 | 470 | void (*hw_start)(struct net_device *); |
1da177e4 LT |
471 | unsigned int (*phy_reset_pending)(void __iomem *); |
472 | unsigned int (*link_ok)(void __iomem *); | |
9c14ceaf | 473 | int pcie_cap; |
c4028958 | 474 | struct delayed_work task; |
f23e7fda | 475 | unsigned features; |
ccdffb9a FR |
476 | |
477 | struct mii_if_info mii; | |
1da177e4 LT |
478 | }; |
479 | ||
979b6c13 | 480 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 481 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 482 | module_param(rx_copybreak, int, 0); |
1b7efd58 | 483 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
1da177e4 LT |
484 | module_param(use_dac, int, 0); |
485 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); | |
b57b7e5a SH |
486 | module_param_named(debug, debug.msg_enable, int, 0); |
487 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
488 | MODULE_LICENSE("GPL"); |
489 | MODULE_VERSION(RTL8169_VERSION); | |
490 | ||
491 | static int rtl8169_open(struct net_device *dev); | |
492 | static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 493 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 494 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 495 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 496 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 497 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 498 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 499 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 500 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 501 | void __iomem *, u32 budget); |
4dcb7d33 | 502 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 503 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 504 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 505 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 506 | |
1da177e4 | 507 | static const unsigned int rtl8169_rx_config = |
5b0384f4 | 508 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
1da177e4 | 509 | |
07d3f51f | 510 | static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
511 | { |
512 | int i; | |
513 | ||
a6baf3af | 514 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 515 | |
2371408c | 516 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
517 | /* |
518 | * Check if the RTL8169 has completed writing to the specified | |
519 | * MII register. | |
520 | */ | |
5b0384f4 | 521 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 522 | break; |
2371408c | 523 | udelay(25); |
1da177e4 LT |
524 | } |
525 | } | |
526 | ||
07d3f51f | 527 | static int mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
528 | { |
529 | int i, value = -1; | |
530 | ||
a6baf3af | 531 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 532 | |
2371408c | 533 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
534 | /* |
535 | * Check if the RTL8169 has completed retrieving data from | |
536 | * the specified MII register. | |
537 | */ | |
1da177e4 | 538 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 539 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
540 | break; |
541 | } | |
2371408c | 542 | udelay(25); |
1da177e4 LT |
543 | } |
544 | return value; | |
545 | } | |
546 | ||
dacf8154 FR |
547 | static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
548 | { | |
549 | mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); | |
550 | } | |
551 | ||
ccdffb9a FR |
552 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
553 | int val) | |
554 | { | |
555 | struct rtl8169_private *tp = netdev_priv(dev); | |
556 | void __iomem *ioaddr = tp->mmio_addr; | |
557 | ||
558 | mdio_write(ioaddr, location, val); | |
559 | } | |
560 | ||
561 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
562 | { | |
563 | struct rtl8169_private *tp = netdev_priv(dev); | |
564 | void __iomem *ioaddr = tp->mmio_addr; | |
565 | ||
566 | return mdio_read(ioaddr, location); | |
567 | } | |
568 | ||
dacf8154 FR |
569 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
570 | { | |
571 | unsigned int i; | |
572 | ||
573 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
574 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
575 | ||
576 | for (i = 0; i < 100; i++) { | |
577 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
578 | break; | |
579 | udelay(10); | |
580 | } | |
581 | } | |
582 | ||
583 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
584 | { | |
585 | u16 value = 0xffff; | |
586 | unsigned int i; | |
587 | ||
588 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
589 | ||
590 | for (i = 0; i < 100; i++) { | |
591 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
592 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
593 | break; | |
594 | } | |
595 | udelay(10); | |
596 | } | |
597 | ||
598 | return value; | |
599 | } | |
600 | ||
601 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
602 | { | |
603 | unsigned int i; | |
604 | ||
605 | RTL_W32(CSIDR, value); | |
606 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
607 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
608 | ||
609 | for (i = 0; i < 100; i++) { | |
610 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
611 | break; | |
612 | udelay(10); | |
613 | } | |
614 | } | |
615 | ||
616 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
617 | { | |
618 | u32 value = ~0x00; | |
619 | unsigned int i; | |
620 | ||
621 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
622 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
623 | ||
624 | for (i = 0; i < 100; i++) { | |
625 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
626 | value = RTL_R32(CSIDR); | |
627 | break; | |
628 | } | |
629 | udelay(10); | |
630 | } | |
631 | ||
632 | return value; | |
633 | } | |
634 | ||
1da177e4 LT |
635 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
636 | { | |
637 | RTL_W16(IntrMask, 0x0000); | |
638 | ||
639 | RTL_W16(IntrStatus, 0xffff); | |
640 | } | |
641 | ||
642 | static void rtl8169_asic_down(void __iomem *ioaddr) | |
643 | { | |
644 | RTL_W8(ChipCmd, 0x00); | |
645 | rtl8169_irq_mask_and_ack(ioaddr); | |
646 | RTL_R16(CPlusCmd); | |
647 | } | |
648 | ||
649 | static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) | |
650 | { | |
651 | return RTL_R32(TBICSR) & TBIReset; | |
652 | } | |
653 | ||
654 | static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) | |
655 | { | |
64e4bfb4 | 656 | return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
657 | } |
658 | ||
659 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
660 | { | |
661 | return RTL_R32(TBICSR) & TBILinkOk; | |
662 | } | |
663 | ||
664 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
665 | { | |
666 | return RTL_R8(PHYstatus) & LinkStatus; | |
667 | } | |
668 | ||
669 | static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) | |
670 | { | |
671 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); | |
672 | } | |
673 | ||
674 | static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) | |
675 | { | |
676 | unsigned int val; | |
677 | ||
9e0db8ef FR |
678 | val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
679 | mdio_write(ioaddr, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
680 | } |
681 | ||
682 | static void rtl8169_check_link_status(struct net_device *dev, | |
07d3f51f FR |
683 | struct rtl8169_private *tp, |
684 | void __iomem *ioaddr) | |
1da177e4 LT |
685 | { |
686 | unsigned long flags; | |
687 | ||
688 | spin_lock_irqsave(&tp->lock, flags); | |
689 | if (tp->link_ok(ioaddr)) { | |
690 | netif_carrier_on(dev); | |
b57b7e5a SH |
691 | if (netif_msg_ifup(tp)) |
692 | printk(KERN_INFO PFX "%s: link up\n", dev->name); | |
693 | } else { | |
694 | if (netif_msg_ifdown(tp)) | |
695 | printk(KERN_INFO PFX "%s: link down\n", dev->name); | |
1da177e4 | 696 | netif_carrier_off(dev); |
b57b7e5a | 697 | } |
1da177e4 LT |
698 | spin_unlock_irqrestore(&tp->lock, flags); |
699 | } | |
700 | ||
61a4dcc2 FR |
701 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
702 | { | |
703 | struct rtl8169_private *tp = netdev_priv(dev); | |
704 | void __iomem *ioaddr = tp->mmio_addr; | |
705 | u8 options; | |
706 | ||
707 | wol->wolopts = 0; | |
708 | ||
709 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) | |
710 | wol->supported = WAKE_ANY; | |
711 | ||
712 | spin_lock_irq(&tp->lock); | |
713 | ||
714 | options = RTL_R8(Config1); | |
715 | if (!(options & PMEnable)) | |
716 | goto out_unlock; | |
717 | ||
718 | options = RTL_R8(Config3); | |
719 | if (options & LinkUp) | |
720 | wol->wolopts |= WAKE_PHY; | |
721 | if (options & MagicPacket) | |
722 | wol->wolopts |= WAKE_MAGIC; | |
723 | ||
724 | options = RTL_R8(Config5); | |
725 | if (options & UWF) | |
726 | wol->wolopts |= WAKE_UCAST; | |
727 | if (options & BWF) | |
5b0384f4 | 728 | wol->wolopts |= WAKE_BCAST; |
61a4dcc2 | 729 | if (options & MWF) |
5b0384f4 | 730 | wol->wolopts |= WAKE_MCAST; |
61a4dcc2 FR |
731 | |
732 | out_unlock: | |
733 | spin_unlock_irq(&tp->lock); | |
734 | } | |
735 | ||
736 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
737 | { | |
738 | struct rtl8169_private *tp = netdev_priv(dev); | |
739 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 740 | unsigned int i; |
61a4dcc2 FR |
741 | static struct { |
742 | u32 opt; | |
743 | u16 reg; | |
744 | u8 mask; | |
745 | } cfg[] = { | |
746 | { WAKE_ANY, Config1, PMEnable }, | |
747 | { WAKE_PHY, Config3, LinkUp }, | |
748 | { WAKE_MAGIC, Config3, MagicPacket }, | |
749 | { WAKE_UCAST, Config5, UWF }, | |
750 | { WAKE_BCAST, Config5, BWF }, | |
751 | { WAKE_MCAST, Config5, MWF }, | |
752 | { WAKE_ANY, Config5, LanWake } | |
753 | }; | |
754 | ||
755 | spin_lock_irq(&tp->lock); | |
756 | ||
757 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
758 | ||
759 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
760 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
761 | if (wol->wolopts & cfg[i].opt) | |
762 | options |= cfg[i].mask; | |
763 | RTL_W8(cfg[i].reg, options); | |
764 | } | |
765 | ||
766 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
767 | ||
f23e7fda FR |
768 | if (wol->wolopts) |
769 | tp->features |= RTL_FEATURE_WOL; | |
770 | else | |
771 | tp->features &= ~RTL_FEATURE_WOL; | |
8b76ab39 | 772 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
61a4dcc2 FR |
773 | |
774 | spin_unlock_irq(&tp->lock); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
1da177e4 LT |
779 | static void rtl8169_get_drvinfo(struct net_device *dev, |
780 | struct ethtool_drvinfo *info) | |
781 | { | |
782 | struct rtl8169_private *tp = netdev_priv(dev); | |
783 | ||
784 | strcpy(info->driver, MODULENAME); | |
785 | strcpy(info->version, RTL8169_VERSION); | |
786 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
787 | } | |
788 | ||
789 | static int rtl8169_get_regs_len(struct net_device *dev) | |
790 | { | |
791 | return R8169_REGS_SIZE; | |
792 | } | |
793 | ||
794 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
795 | u8 autoneg, u16 speed, u8 duplex) | |
796 | { | |
797 | struct rtl8169_private *tp = netdev_priv(dev); | |
798 | void __iomem *ioaddr = tp->mmio_addr; | |
799 | int ret = 0; | |
800 | u32 reg; | |
801 | ||
802 | reg = RTL_R32(TBICSR); | |
803 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
804 | (duplex == DUPLEX_FULL)) { | |
805 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
806 | } else if (autoneg == AUTONEG_ENABLE) | |
807 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
808 | else { | |
b57b7e5a SH |
809 | if (netif_msg_link(tp)) { |
810 | printk(KERN_WARNING "%s: " | |
811 | "incorrect speed setting refused in TBI mode\n", | |
812 | dev->name); | |
813 | } | |
1da177e4 LT |
814 | ret = -EOPNOTSUPP; |
815 | } | |
816 | ||
817 | return ret; | |
818 | } | |
819 | ||
820 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
821 | u8 autoneg, u16 speed, u8 duplex) | |
822 | { | |
823 | struct rtl8169_private *tp = netdev_priv(dev); | |
824 | void __iomem *ioaddr = tp->mmio_addr; | |
825 | int auto_nego, giga_ctrl; | |
826 | ||
64e4bfb4 FR |
827 | auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
828 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
829 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
830 | giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); | |
831 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
1da177e4 LT |
832 | |
833 | if (autoneg == AUTONEG_ENABLE) { | |
64e4bfb4 FR |
834 | auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
835 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
836 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
1da177e4 LT |
837 | } else { |
838 | if (speed == SPEED_10) | |
64e4bfb4 | 839 | auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
1da177e4 | 840 | else if (speed == SPEED_100) |
64e4bfb4 | 841 | auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
1da177e4 | 842 | else if (speed == SPEED_1000) |
64e4bfb4 | 843 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
1da177e4 LT |
844 | |
845 | if (duplex == DUPLEX_HALF) | |
64e4bfb4 | 846 | auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); |
726ecdcf AG |
847 | |
848 | if (duplex == DUPLEX_FULL) | |
64e4bfb4 | 849 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); |
bcf0bf90 FR |
850 | |
851 | /* This tweak comes straight from Realtek's driver. */ | |
852 | if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && | |
e3cf0cc0 FR |
853 | ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
854 | (tp->mac_version == RTL_GIGA_MAC_VER_16))) { | |
64e4bfb4 | 855 | auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; |
bcf0bf90 FR |
856 | } |
857 | } | |
858 | ||
2857ffb7 FR |
859 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
860 | if ((tp->mac_version == RTL_GIGA_MAC_VER_07) || | |
861 | (tp->mac_version == RTL_GIGA_MAC_VER_08) || | |
862 | (tp->mac_version == RTL_GIGA_MAC_VER_09) || | |
863 | (tp->mac_version == RTL_GIGA_MAC_VER_10) || | |
864 | (tp->mac_version == RTL_GIGA_MAC_VER_13) || | |
bcf0bf90 | 865 | (tp->mac_version == RTL_GIGA_MAC_VER_14) || |
e3cf0cc0 FR |
866 | (tp->mac_version == RTL_GIGA_MAC_VER_15) || |
867 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
64e4bfb4 | 868 | if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && |
bcf0bf90 FR |
869 | netif_msg_link(tp)) { |
870 | printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", | |
871 | dev->name); | |
872 | } | |
64e4bfb4 | 873 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
1da177e4 LT |
874 | } |
875 | ||
623a1593 FR |
876 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
877 | ||
a2de6b89 FR |
878 | if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
879 | (tp->mac_version == RTL_GIGA_MAC_VER_12) || | |
880 | (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { | |
881 | /* | |
882 | * Wake up the PHY. | |
883 | * Vendor specific (0x1f) and reserved (0x0e) MII registers. | |
884 | */ | |
2584fbc3 RS |
885 | mdio_write(ioaddr, 0x1f, 0x0000); |
886 | mdio_write(ioaddr, 0x0e, 0x0000); | |
887 | } | |
888 | ||
1da177e4 LT |
889 | tp->phy_auto_nego_reg = auto_nego; |
890 | tp->phy_1000_ctrl_reg = giga_ctrl; | |
891 | ||
64e4bfb4 FR |
892 | mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
893 | mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); | |
894 | mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); | |
1da177e4 LT |
895 | return 0; |
896 | } | |
897 | ||
898 | static int rtl8169_set_speed(struct net_device *dev, | |
899 | u8 autoneg, u16 speed, u8 duplex) | |
900 | { | |
901 | struct rtl8169_private *tp = netdev_priv(dev); | |
902 | int ret; | |
903 | ||
904 | ret = tp->set_speed(dev, autoneg, speed, duplex); | |
905 | ||
64e4bfb4 | 906 | if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
907 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
908 | ||
909 | return ret; | |
910 | } | |
911 | ||
912 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
913 | { | |
914 | struct rtl8169_private *tp = netdev_priv(dev); | |
915 | unsigned long flags; | |
916 | int ret; | |
917 | ||
918 | spin_lock_irqsave(&tp->lock, flags); | |
919 | ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); | |
920 | spin_unlock_irqrestore(&tp->lock, flags); | |
5b0384f4 | 921 | |
1da177e4 LT |
922 | return ret; |
923 | } | |
924 | ||
925 | static u32 rtl8169_get_rx_csum(struct net_device *dev) | |
926 | { | |
927 | struct rtl8169_private *tp = netdev_priv(dev); | |
928 | ||
929 | return tp->cp_cmd & RxChkSum; | |
930 | } | |
931 | ||
932 | static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) | |
933 | { | |
934 | struct rtl8169_private *tp = netdev_priv(dev); | |
935 | void __iomem *ioaddr = tp->mmio_addr; | |
936 | unsigned long flags; | |
937 | ||
938 | spin_lock_irqsave(&tp->lock, flags); | |
939 | ||
940 | if (data) | |
941 | tp->cp_cmd |= RxChkSum; | |
942 | else | |
943 | tp->cp_cmd &= ~RxChkSum; | |
944 | ||
945 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
946 | RTL_R16(CPlusCmd); | |
947 | ||
948 | spin_unlock_irqrestore(&tp->lock, flags); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
953 | #ifdef CONFIG_R8169_VLAN | |
954 | ||
955 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
956 | struct sk_buff *skb) | |
957 | { | |
958 | return (tp->vlgrp && vlan_tx_tag_present(skb)) ? | |
959 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; | |
960 | } | |
961 | ||
962 | static void rtl8169_vlan_rx_register(struct net_device *dev, | |
963 | struct vlan_group *grp) | |
964 | { | |
965 | struct rtl8169_private *tp = netdev_priv(dev); | |
966 | void __iomem *ioaddr = tp->mmio_addr; | |
967 | unsigned long flags; | |
968 | ||
969 | spin_lock_irqsave(&tp->lock, flags); | |
970 | tp->vlgrp = grp; | |
971 | if (tp->vlgrp) | |
972 | tp->cp_cmd |= RxVlan; | |
973 | else | |
974 | tp->cp_cmd &= ~RxVlan; | |
975 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
976 | RTL_R16(CPlusCmd); | |
977 | spin_unlock_irqrestore(&tp->lock, flags); | |
978 | } | |
979 | ||
1da177e4 LT |
980 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
981 | struct sk_buff *skb) | |
982 | { | |
983 | u32 opts2 = le32_to_cpu(desc->opts2); | |
865c652d | 984 | struct vlan_group *vlgrp = tp->vlgrp; |
1da177e4 LT |
985 | int ret; |
986 | ||
865c652d FR |
987 | if (vlgrp && (opts2 & RxVlanTag)) { |
988 | vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); | |
1da177e4 LT |
989 | ret = 0; |
990 | } else | |
991 | ret = -1; | |
992 | desc->opts2 = 0; | |
993 | return ret; | |
994 | } | |
995 | ||
996 | #else /* !CONFIG_R8169_VLAN */ | |
997 | ||
998 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
999 | struct sk_buff *skb) | |
1000 | { | |
1001 | return 0; | |
1002 | } | |
1003 | ||
1004 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, | |
1005 | struct sk_buff *skb) | |
1006 | { | |
1007 | return -1; | |
1008 | } | |
1009 | ||
1010 | #endif | |
1011 | ||
ccdffb9a | 1012 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1013 | { |
1014 | struct rtl8169_private *tp = netdev_priv(dev); | |
1015 | void __iomem *ioaddr = tp->mmio_addr; | |
1016 | u32 status; | |
1017 | ||
1018 | cmd->supported = | |
1019 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1020 | cmd->port = PORT_FIBRE; | |
1021 | cmd->transceiver = XCVR_INTERNAL; | |
1022 | ||
1023 | status = RTL_R32(TBICSR); | |
1024 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1025 | cmd->autoneg = !!(status & TBINwEnable); | |
1026 | ||
1027 | cmd->speed = SPEED_1000; | |
1028 | cmd->duplex = DUPLEX_FULL; /* Always set */ | |
ccdffb9a FR |
1029 | |
1030 | return 0; | |
1da177e4 LT |
1031 | } |
1032 | ||
ccdffb9a | 1033 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1034 | { |
1035 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1036 | |
1037 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1038 | } |
1039 | ||
1040 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1041 | { | |
1042 | struct rtl8169_private *tp = netdev_priv(dev); | |
1043 | unsigned long flags; | |
ccdffb9a | 1044 | int rc; |
1da177e4 LT |
1045 | |
1046 | spin_lock_irqsave(&tp->lock, flags); | |
1047 | ||
ccdffb9a | 1048 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1049 | |
1050 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1051 | return rc; |
1da177e4 LT |
1052 | } |
1053 | ||
1054 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1055 | void *p) | |
1056 | { | |
5b0384f4 FR |
1057 | struct rtl8169_private *tp = netdev_priv(dev); |
1058 | unsigned long flags; | |
1da177e4 | 1059 | |
5b0384f4 FR |
1060 | if (regs->len > R8169_REGS_SIZE) |
1061 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1062 | |
5b0384f4 FR |
1063 | spin_lock_irqsave(&tp->lock, flags); |
1064 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1065 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1066 | } |
1067 | ||
b57b7e5a SH |
1068 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1069 | { | |
1070 | struct rtl8169_private *tp = netdev_priv(dev); | |
1071 | ||
1072 | return tp->msg_enable; | |
1073 | } | |
1074 | ||
1075 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1076 | { | |
1077 | struct rtl8169_private *tp = netdev_priv(dev); | |
1078 | ||
1079 | tp->msg_enable = value; | |
1080 | } | |
1081 | ||
d4a3a0fc SH |
1082 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1083 | "tx_packets", | |
1084 | "rx_packets", | |
1085 | "tx_errors", | |
1086 | "rx_errors", | |
1087 | "rx_missed", | |
1088 | "align_errors", | |
1089 | "tx_single_collisions", | |
1090 | "tx_multi_collisions", | |
1091 | "unicast", | |
1092 | "broadcast", | |
1093 | "multicast", | |
1094 | "tx_aborted", | |
1095 | "tx_underrun", | |
1096 | }; | |
1097 | ||
1098 | struct rtl8169_counters { | |
b1eab701 AV |
1099 | __le64 tx_packets; |
1100 | __le64 rx_packets; | |
1101 | __le64 tx_errors; | |
1102 | __le32 rx_errors; | |
1103 | __le16 rx_missed; | |
1104 | __le16 align_errors; | |
1105 | __le32 tx_one_collision; | |
1106 | __le32 tx_multi_collision; | |
1107 | __le64 rx_unicast; | |
1108 | __le64 rx_broadcast; | |
1109 | __le32 rx_multicast; | |
1110 | __le16 tx_aborted; | |
1111 | __le16 tx_underun; | |
d4a3a0fc SH |
1112 | }; |
1113 | ||
b9f2c044 | 1114 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1115 | { |
b9f2c044 JG |
1116 | switch (sset) { |
1117 | case ETH_SS_STATS: | |
1118 | return ARRAY_SIZE(rtl8169_gstrings); | |
1119 | default: | |
1120 | return -EOPNOTSUPP; | |
1121 | } | |
d4a3a0fc SH |
1122 | } |
1123 | ||
1124 | static void rtl8169_get_ethtool_stats(struct net_device *dev, | |
1125 | struct ethtool_stats *stats, u64 *data) | |
1126 | { | |
1127 | struct rtl8169_private *tp = netdev_priv(dev); | |
1128 | void __iomem *ioaddr = tp->mmio_addr; | |
1129 | struct rtl8169_counters *counters; | |
1130 | dma_addr_t paddr; | |
1131 | u32 cmd; | |
1132 | ||
1133 | ASSERT_RTNL(); | |
1134 | ||
1135 | counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); | |
1136 | if (!counters) | |
1137 | return; | |
1138 | ||
1139 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
1140 | cmd = (u64)paddr & DMA_32BIT_MASK; | |
1141 | RTL_W32(CounterAddrLow, cmd); | |
1142 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1143 | ||
1144 | while (RTL_R32(CounterAddrLow) & CounterDump) { | |
1145 | if (msleep_interruptible(1)) | |
1146 | break; | |
1147 | } | |
1148 | ||
1149 | RTL_W32(CounterAddrLow, 0); | |
1150 | RTL_W32(CounterAddrHigh, 0); | |
1151 | ||
5b0384f4 | 1152 | data[0] = le64_to_cpu(counters->tx_packets); |
d4a3a0fc SH |
1153 | data[1] = le64_to_cpu(counters->rx_packets); |
1154 | data[2] = le64_to_cpu(counters->tx_errors); | |
1155 | data[3] = le32_to_cpu(counters->rx_errors); | |
1156 | data[4] = le16_to_cpu(counters->rx_missed); | |
1157 | data[5] = le16_to_cpu(counters->align_errors); | |
1158 | data[6] = le32_to_cpu(counters->tx_one_collision); | |
1159 | data[7] = le32_to_cpu(counters->tx_multi_collision); | |
1160 | data[8] = le64_to_cpu(counters->rx_unicast); | |
1161 | data[9] = le64_to_cpu(counters->rx_broadcast); | |
1162 | data[10] = le32_to_cpu(counters->rx_multicast); | |
1163 | data[11] = le16_to_cpu(counters->tx_aborted); | |
1164 | data[12] = le16_to_cpu(counters->tx_underun); | |
1165 | ||
1166 | pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); | |
1167 | } | |
1168 | ||
1169 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
1170 | { | |
1171 | switch(stringset) { | |
1172 | case ETH_SS_STATS: | |
1173 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1174 | break; | |
1175 | } | |
1176 | } | |
1177 | ||
7282d491 | 1178 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1179 | .get_drvinfo = rtl8169_get_drvinfo, |
1180 | .get_regs_len = rtl8169_get_regs_len, | |
1181 | .get_link = ethtool_op_get_link, | |
1182 | .get_settings = rtl8169_get_settings, | |
1183 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1184 | .get_msglevel = rtl8169_get_msglevel, |
1185 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 LT |
1186 | .get_rx_csum = rtl8169_get_rx_csum, |
1187 | .set_rx_csum = rtl8169_set_rx_csum, | |
1da177e4 | 1188 | .set_tx_csum = ethtool_op_set_tx_csum, |
1da177e4 | 1189 | .set_sg = ethtool_op_set_sg, |
1da177e4 LT |
1190 | .set_tso = ethtool_op_set_tso, |
1191 | .get_regs = rtl8169_get_regs, | |
61a4dcc2 FR |
1192 | .get_wol = rtl8169_get_wol, |
1193 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1194 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1195 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1196 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
1da177e4 LT |
1197 | }; |
1198 | ||
07d3f51f FR |
1199 | static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
1200 | int bitnum, int bitval) | |
1da177e4 LT |
1201 | { |
1202 | int val; | |
1203 | ||
1204 | val = mdio_read(ioaddr, reg); | |
1205 | val = (bitval == 1) ? | |
1206 | val | (bitval << bitnum) : val & ~(0x0001 << bitnum); | |
5b0384f4 | 1207 | mdio_write(ioaddr, reg, val & 0xffff); |
1da177e4 LT |
1208 | } |
1209 | ||
07d3f51f FR |
1210 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
1211 | void __iomem *ioaddr) | |
1da177e4 | 1212 | { |
0e485150 FR |
1213 | /* |
1214 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1215 | * but they can be identified more specifically through the test below | |
1216 | * if needed: | |
1217 | * | |
1218 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1219 | * |
1220 | * Same thing for the 8101Eb and the 8101Ec: | |
1221 | * | |
1222 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1223 | */ |
1da177e4 LT |
1224 | const struct { |
1225 | u32 mask; | |
e3cf0cc0 | 1226 | u32 val; |
1da177e4 LT |
1227 | int mac_version; |
1228 | } mac_info[] = { | |
5b538df9 FR |
1229 | /* 8168D family. */ |
1230 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, | |
1231 | ||
ef808d50 | 1232 | /* 8168C family. */ |
7f3e3d3a | 1233 | { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1234 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1235 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1236 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1237 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1238 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1239 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1240 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1241 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1242 | |
1243 | /* 8168B family. */ | |
1244 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1245 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1246 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1247 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1248 | ||
1249 | /* 8101 family. */ | |
2857ffb7 FR |
1250 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1251 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1252 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1253 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1254 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1255 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1256 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1257 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1258 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1259 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1260 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1261 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1262 | /* FIXME: where did these entries come from ? -- FR */ | |
1263 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1264 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1265 | ||
1266 | /* 8110 family. */ | |
1267 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1268 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1269 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1270 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1271 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1272 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1273 | ||
1274 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ | |
1da177e4 LT |
1275 | }, *p = mac_info; |
1276 | u32 reg; | |
1277 | ||
e3cf0cc0 FR |
1278 | reg = RTL_R32(TxConfig); |
1279 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1280 | p++; |
1281 | tp->mac_version = p->mac_version; | |
e3cf0cc0 FR |
1282 | |
1283 | if (p->mask == 0x00000000) { | |
1284 | struct pci_dev *pdev = tp->pci_dev; | |
1285 | ||
1286 | dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg); | |
1287 | } | |
1da177e4 LT |
1288 | } |
1289 | ||
1290 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1291 | { | |
bcf0bf90 | 1292 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1293 | } |
1294 | ||
867763c1 FR |
1295 | struct phy_reg { |
1296 | u16 reg; | |
1297 | u16 val; | |
1298 | }; | |
1299 | ||
1300 | static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) | |
1301 | { | |
1302 | while (len-- > 0) { | |
1303 | mdio_write(ioaddr, regs->reg, regs->val); | |
1304 | regs++; | |
1305 | } | |
1306 | } | |
1307 | ||
5615d9f1 | 1308 | static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
1da177e4 | 1309 | { |
1da177e4 LT |
1310 | struct { |
1311 | u16 regs[5]; /* Beware of bit-sign propagation */ | |
1312 | } phy_magic[5] = { { | |
1313 | { 0x0000, //w 4 15 12 0 | |
1314 | 0x00a1, //w 3 15 0 00a1 | |
1315 | 0x0008, //w 2 15 0 0008 | |
1316 | 0x1020, //w 1 15 0 1020 | |
1317 | 0x1000 } },{ //w 0 15 0 1000 | |
1318 | { 0x7000, //w 4 15 12 7 | |
1319 | 0xff41, //w 3 15 0 ff41 | |
1320 | 0xde60, //w 2 15 0 de60 | |
1321 | 0x0140, //w 1 15 0 0140 | |
1322 | 0x0077 } },{ //w 0 15 0 0077 | |
1323 | { 0xa000, //w 4 15 12 a | |
1324 | 0xdf01, //w 3 15 0 df01 | |
1325 | 0xdf20, //w 2 15 0 df20 | |
1326 | 0xff95, //w 1 15 0 ff95 | |
1327 | 0xfa00 } },{ //w 0 15 0 fa00 | |
1328 | { 0xb000, //w 4 15 12 b | |
1329 | 0xff41, //w 3 15 0 ff41 | |
1330 | 0xde20, //w 2 15 0 de20 | |
1331 | 0x0140, //w 1 15 0 0140 | |
1332 | 0x00bb } },{ //w 0 15 0 00bb | |
1333 | { 0xf000, //w 4 15 12 f | |
1334 | 0xdf01, //w 3 15 0 df01 | |
1335 | 0xdf20, //w 2 15 0 df20 | |
1336 | 0xff95, //w 1 15 0 ff95 | |
1337 | 0xbf00 } //w 0 15 0 bf00 | |
1338 | } | |
1339 | }, *p = phy_magic; | |
07d3f51f | 1340 | unsigned int i; |
1da177e4 | 1341 | |
a441d7b6 FR |
1342 | mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 |
1343 | mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 | |
1344 | mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 | |
1da177e4 LT |
1345 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
1346 | ||
1347 | for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { | |
1348 | int val, pos = 4; | |
1349 | ||
1350 | val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); | |
1351 | mdio_write(ioaddr, pos, val); | |
1352 | while (--pos >= 0) | |
1353 | mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); | |
1354 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 | |
1355 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 | |
1356 | } | |
a441d7b6 | 1357 | mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 |
1da177e4 LT |
1358 | } |
1359 | ||
5615d9f1 FR |
1360 | static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
1361 | { | |
a441d7b6 FR |
1362 | struct phy_reg phy_reg_init[] = { |
1363 | { 0x1f, 0x0002 }, | |
1364 | { 0x01, 0x90d0 }, | |
1365 | { 0x1f, 0x0000 } | |
1366 | }; | |
1367 | ||
1368 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
5615d9f1 FR |
1369 | } |
1370 | ||
236b8082 FR |
1371 | static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
1372 | { | |
1373 | struct phy_reg phy_reg_init[] = { | |
1374 | { 0x10, 0xf41b }, | |
1375 | { 0x1f, 0x0000 } | |
1376 | }; | |
1377 | ||
1378 | mdio_write(ioaddr, 0x1f, 0x0001); | |
1379 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1380 | ||
1381 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1382 | } | |
1383 | ||
1384 | static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) | |
1385 | { | |
1386 | struct phy_reg phy_reg_init[] = { | |
1387 | { 0x1f, 0x0001 }, | |
1388 | { 0x10, 0xf41b }, | |
1389 | { 0x1f, 0x0000 } | |
1390 | }; | |
1391 | ||
1392 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1393 | } | |
1394 | ||
ef3386f0 | 1395 | static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
867763c1 FR |
1396 | { |
1397 | struct phy_reg phy_reg_init[] = { | |
1398 | { 0x1f, 0x0000 }, | |
1399 | { 0x1d, 0x0f00 }, | |
1400 | { 0x1f, 0x0002 }, | |
1401 | { 0x0c, 0x1ec8 }, | |
1402 | { 0x1f, 0x0000 } | |
1403 | }; | |
1404 | ||
1405 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1406 | } | |
1407 | ||
ef3386f0 FR |
1408 | static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
1409 | { | |
1410 | struct phy_reg phy_reg_init[] = { | |
1411 | { 0x1f, 0x0001 }, | |
1412 | { 0x1d, 0x3d98 }, | |
1413 | { 0x1f, 0x0000 } | |
1414 | }; | |
1415 | ||
1416 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1417 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1418 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1419 | ||
1420 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1421 | } | |
1422 | ||
219a1e9d | 1423 | static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
867763c1 FR |
1424 | { |
1425 | struct phy_reg phy_reg_init[] = { | |
a3f80671 FR |
1426 | { 0x1f, 0x0001 }, |
1427 | { 0x12, 0x2300 }, | |
867763c1 FR |
1428 | { 0x1f, 0x0002 }, |
1429 | { 0x00, 0x88d4 }, | |
1430 | { 0x01, 0x82b1 }, | |
1431 | { 0x03, 0x7002 }, | |
1432 | { 0x08, 0x9e30 }, | |
1433 | { 0x09, 0x01f0 }, | |
1434 | { 0x0a, 0x5500 }, | |
1435 | { 0x0c, 0x00c8 }, | |
1436 | { 0x1f, 0x0003 }, | |
1437 | { 0x12, 0xc096 }, | |
1438 | { 0x16, 0x000a }, | |
f50d4275 FR |
1439 | { 0x1f, 0x0000 }, |
1440 | { 0x1f, 0x0000 }, | |
1441 | { 0x09, 0x2000 }, | |
1442 | { 0x09, 0x0000 } | |
867763c1 FR |
1443 | }; |
1444 | ||
1445 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
f50d4275 FR |
1446 | |
1447 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1448 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1449 | mdio_write(ioaddr, 0x1f, 0x0000); | |
867763c1 FR |
1450 | } |
1451 | ||
219a1e9d | 1452 | static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
7da97ec9 FR |
1453 | { |
1454 | struct phy_reg phy_reg_init[] = { | |
f50d4275 | 1455 | { 0x1f, 0x0001 }, |
7da97ec9 | 1456 | { 0x12, 0x2300 }, |
f50d4275 FR |
1457 | { 0x03, 0x802f }, |
1458 | { 0x02, 0x4f02 }, | |
1459 | { 0x01, 0x0409 }, | |
1460 | { 0x00, 0xf099 }, | |
1461 | { 0x04, 0x9800 }, | |
1462 | { 0x04, 0x9000 }, | |
1463 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
1464 | { 0x1f, 0x0002 }, |
1465 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
1466 | { 0x06, 0x0761 }, |
1467 | { 0x1f, 0x0003 }, | |
1468 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
1469 | { 0x1f, 0x0000 } |
1470 | }; | |
1471 | ||
1472 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
f50d4275 FR |
1473 | |
1474 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1475 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1476 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1477 | mdio_write(ioaddr, 0x1f, 0x0000); | |
7da97ec9 FR |
1478 | } |
1479 | ||
197ff761 FR |
1480 | static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) |
1481 | { | |
1482 | struct phy_reg phy_reg_init[] = { | |
1483 | { 0x1f, 0x0001 }, | |
1484 | { 0x12, 0x2300 }, | |
1485 | { 0x1d, 0x3d98 }, | |
1486 | { 0x1f, 0x0002 }, | |
1487 | { 0x0c, 0x7eb8 }, | |
1488 | { 0x06, 0x5461 }, | |
1489 | { 0x1f, 0x0003 }, | |
1490 | { 0x16, 0x0f0a }, | |
1491 | { 0x1f, 0x0000 } | |
1492 | }; | |
1493 | ||
1494 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1495 | ||
1496 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1497 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1498 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1499 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1500 | } | |
1501 | ||
6fb07058 FR |
1502 | static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) |
1503 | { | |
1504 | rtl8168c_3_hw_phy_config(ioaddr); | |
1505 | } | |
1506 | ||
5b538df9 FR |
1507 | static void rtl8168d_hw_phy_config(void __iomem *ioaddr) |
1508 | { | |
1509 | struct phy_reg phy_reg_init_0[] = { | |
1510 | { 0x1f, 0x0001 }, | |
1511 | { 0x09, 0x2770 }, | |
1512 | { 0x08, 0x04d0 }, | |
1513 | { 0x0b, 0xad15 }, | |
1514 | { 0x0c, 0x5bf0 }, | |
1515 | { 0x1c, 0xf101 }, | |
1516 | { 0x1f, 0x0003 }, | |
1517 | { 0x14, 0x94d7 }, | |
1518 | { 0x12, 0xf4d6 }, | |
1519 | { 0x09, 0xca0f }, | |
1520 | { 0x1f, 0x0002 }, | |
1521 | { 0x0b, 0x0b10 }, | |
1522 | { 0x0c, 0xd1f7 }, | |
1523 | { 0x1f, 0x0002 }, | |
1524 | { 0x06, 0x5461 }, | |
1525 | { 0x1f, 0x0002 }, | |
1526 | { 0x05, 0x6662 }, | |
1527 | { 0x1f, 0x0000 }, | |
1528 | { 0x14, 0x0060 }, | |
1529 | { 0x1f, 0x0000 }, | |
1530 | { 0x0d, 0xf8a0 }, | |
1531 | { 0x1f, 0x0005 }, | |
1532 | { 0x05, 0xffc2 } | |
1533 | }; | |
1534 | ||
1535 | rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); | |
1536 | ||
1537 | if (mdio_read(ioaddr, 0x06) == 0xc400) { | |
1538 | struct phy_reg phy_reg_init_1[] = { | |
1539 | { 0x1f, 0x0005 }, | |
1540 | { 0x01, 0x0300 }, | |
1541 | { 0x1f, 0x0000 }, | |
1542 | { 0x11, 0x401c }, | |
1543 | { 0x16, 0x4100 }, | |
1544 | { 0x1f, 0x0005 }, | |
1545 | { 0x07, 0x0010 }, | |
1546 | { 0x05, 0x83dc }, | |
1547 | { 0x06, 0x087d }, | |
1548 | { 0x05, 0x8300 }, | |
1549 | { 0x06, 0x0101 }, | |
1550 | { 0x06, 0x05f8 }, | |
1551 | { 0x06, 0xf9fa }, | |
1552 | { 0x06, 0xfbef }, | |
1553 | { 0x06, 0x79e2 }, | |
1554 | { 0x06, 0x835f }, | |
1555 | { 0x06, 0xe0f8 }, | |
1556 | { 0x06, 0x9ae1 }, | |
1557 | { 0x06, 0xf89b }, | |
1558 | { 0x06, 0xef31 }, | |
1559 | { 0x06, 0x3b65 }, | |
1560 | { 0x06, 0xaa07 }, | |
1561 | { 0x06, 0x81e4 }, | |
1562 | { 0x06, 0xf89a }, | |
1563 | { 0x06, 0xe5f8 }, | |
1564 | { 0x06, 0x9baf }, | |
1565 | { 0x06, 0x06ae }, | |
1566 | { 0x05, 0x83dc }, | |
1567 | { 0x06, 0x8300 }, | |
1568 | }; | |
1569 | ||
1570 | rtl_phy_write(ioaddr, phy_reg_init_1, | |
1571 | ARRAY_SIZE(phy_reg_init_1)); | |
1572 | } | |
1573 | ||
1574 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1575 | } | |
1576 | ||
2857ffb7 FR |
1577 | static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
1578 | { | |
1579 | struct phy_reg phy_reg_init[] = { | |
1580 | { 0x1f, 0x0003 }, | |
1581 | { 0x08, 0x441d }, | |
1582 | { 0x01, 0x9100 }, | |
1583 | { 0x1f, 0x0000 } | |
1584 | }; | |
1585 | ||
1586 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1587 | mdio_patch(ioaddr, 0x11, 1 << 12); | |
1588 | mdio_patch(ioaddr, 0x19, 1 << 13); | |
1589 | ||
1590 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1591 | } | |
1592 | ||
5615d9f1 FR |
1593 | static void rtl_hw_phy_config(struct net_device *dev) |
1594 | { | |
1595 | struct rtl8169_private *tp = netdev_priv(dev); | |
1596 | void __iomem *ioaddr = tp->mmio_addr; | |
1597 | ||
1598 | rtl8169_print_mac_version(tp); | |
1599 | ||
1600 | switch (tp->mac_version) { | |
1601 | case RTL_GIGA_MAC_VER_01: | |
1602 | break; | |
1603 | case RTL_GIGA_MAC_VER_02: | |
1604 | case RTL_GIGA_MAC_VER_03: | |
1605 | rtl8169s_hw_phy_config(ioaddr); | |
1606 | break; | |
1607 | case RTL_GIGA_MAC_VER_04: | |
1608 | rtl8169sb_hw_phy_config(ioaddr); | |
1609 | break; | |
2857ffb7 FR |
1610 | case RTL_GIGA_MAC_VER_07: |
1611 | case RTL_GIGA_MAC_VER_08: | |
1612 | case RTL_GIGA_MAC_VER_09: | |
1613 | rtl8102e_hw_phy_config(ioaddr); | |
1614 | break; | |
236b8082 FR |
1615 | case RTL_GIGA_MAC_VER_11: |
1616 | rtl8168bb_hw_phy_config(ioaddr); | |
1617 | break; | |
1618 | case RTL_GIGA_MAC_VER_12: | |
1619 | rtl8168bef_hw_phy_config(ioaddr); | |
1620 | break; | |
1621 | case RTL_GIGA_MAC_VER_17: | |
1622 | rtl8168bef_hw_phy_config(ioaddr); | |
1623 | break; | |
867763c1 | 1624 | case RTL_GIGA_MAC_VER_18: |
ef3386f0 | 1625 | rtl8168cp_1_hw_phy_config(ioaddr); |
867763c1 FR |
1626 | break; |
1627 | case RTL_GIGA_MAC_VER_19: | |
219a1e9d | 1628 | rtl8168c_1_hw_phy_config(ioaddr); |
867763c1 | 1629 | break; |
7da97ec9 | 1630 | case RTL_GIGA_MAC_VER_20: |
219a1e9d | 1631 | rtl8168c_2_hw_phy_config(ioaddr); |
7da97ec9 | 1632 | break; |
197ff761 FR |
1633 | case RTL_GIGA_MAC_VER_21: |
1634 | rtl8168c_3_hw_phy_config(ioaddr); | |
1635 | break; | |
6fb07058 FR |
1636 | case RTL_GIGA_MAC_VER_22: |
1637 | rtl8168c_4_hw_phy_config(ioaddr); | |
1638 | break; | |
ef3386f0 | 1639 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 1640 | case RTL_GIGA_MAC_VER_24: |
ef3386f0 FR |
1641 | rtl8168cp_2_hw_phy_config(ioaddr); |
1642 | break; | |
5b538df9 FR |
1643 | case RTL_GIGA_MAC_VER_25: |
1644 | rtl8168d_hw_phy_config(ioaddr); | |
1645 | break; | |
ef3386f0 | 1646 | |
5615d9f1 FR |
1647 | default: |
1648 | break; | |
1649 | } | |
1650 | } | |
1651 | ||
1da177e4 LT |
1652 | static void rtl8169_phy_timer(unsigned long __opaque) |
1653 | { | |
1654 | struct net_device *dev = (struct net_device *)__opaque; | |
1655 | struct rtl8169_private *tp = netdev_priv(dev); | |
1656 | struct timer_list *timer = &tp->timer; | |
1657 | void __iomem *ioaddr = tp->mmio_addr; | |
1658 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
1659 | ||
bcf0bf90 | 1660 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 1661 | |
64e4bfb4 | 1662 | if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
1663 | return; |
1664 | ||
1665 | spin_lock_irq(&tp->lock); | |
1666 | ||
1667 | if (tp->phy_reset_pending(ioaddr)) { | |
5b0384f4 | 1668 | /* |
1da177e4 LT |
1669 | * A busy loop could burn quite a few cycles on nowadays CPU. |
1670 | * Let's delay the execution of the timer for a few ticks. | |
1671 | */ | |
1672 | timeout = HZ/10; | |
1673 | goto out_mod_timer; | |
1674 | } | |
1675 | ||
1676 | if (tp->link_ok(ioaddr)) | |
1677 | goto out_unlock; | |
1678 | ||
b57b7e5a SH |
1679 | if (netif_msg_link(tp)) |
1680 | printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); | |
1da177e4 LT |
1681 | |
1682 | tp->phy_reset_enable(ioaddr); | |
1683 | ||
1684 | out_mod_timer: | |
1685 | mod_timer(timer, jiffies + timeout); | |
1686 | out_unlock: | |
1687 | spin_unlock_irq(&tp->lock); | |
1688 | } | |
1689 | ||
1690 | static inline void rtl8169_delete_timer(struct net_device *dev) | |
1691 | { | |
1692 | struct rtl8169_private *tp = netdev_priv(dev); | |
1693 | struct timer_list *timer = &tp->timer; | |
1694 | ||
e179bb7b | 1695 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1696 | return; |
1697 | ||
1698 | del_timer_sync(timer); | |
1699 | } | |
1700 | ||
1701 | static inline void rtl8169_request_timer(struct net_device *dev) | |
1702 | { | |
1703 | struct rtl8169_private *tp = netdev_priv(dev); | |
1704 | struct timer_list *timer = &tp->timer; | |
1705 | ||
e179bb7b | 1706 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1707 | return; |
1708 | ||
2efa53f3 | 1709 | mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
1da177e4 LT |
1710 | } |
1711 | ||
1712 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1713 | /* | |
1714 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1715 | * without having to re-enable interrupts. It's not called while | |
1716 | * the interrupt routine is executing. | |
1717 | */ | |
1718 | static void rtl8169_netpoll(struct net_device *dev) | |
1719 | { | |
1720 | struct rtl8169_private *tp = netdev_priv(dev); | |
1721 | struct pci_dev *pdev = tp->pci_dev; | |
1722 | ||
1723 | disable_irq(pdev->irq); | |
7d12e780 | 1724 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
1725 | enable_irq(pdev->irq); |
1726 | } | |
1727 | #endif | |
1728 | ||
1729 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
1730 | void __iomem *ioaddr) | |
1731 | { | |
1732 | iounmap(ioaddr); | |
1733 | pci_release_regions(pdev); | |
1734 | pci_disable_device(pdev); | |
1735 | free_netdev(dev); | |
1736 | } | |
1737 | ||
bf793295 FR |
1738 | static void rtl8169_phy_reset(struct net_device *dev, |
1739 | struct rtl8169_private *tp) | |
1740 | { | |
1741 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 1742 | unsigned int i; |
bf793295 FR |
1743 | |
1744 | tp->phy_reset_enable(ioaddr); | |
1745 | for (i = 0; i < 100; i++) { | |
1746 | if (!tp->phy_reset_pending(ioaddr)) | |
1747 | return; | |
1748 | msleep(1); | |
1749 | } | |
1750 | if (netif_msg_link(tp)) | |
1751 | printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); | |
1752 | } | |
1753 | ||
4ff96fa6 FR |
1754 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
1755 | { | |
1756 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 1757 | |
5615d9f1 | 1758 | rtl_hw_phy_config(dev); |
4ff96fa6 | 1759 | |
77332894 MS |
1760 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
1761 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
1762 | RTL_W8(0x82, 0x01); | |
1763 | } | |
4ff96fa6 | 1764 | |
6dccd16b FR |
1765 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
1766 | ||
1767 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
1768 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 1769 | |
bcf0bf90 | 1770 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
1771 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1772 | RTL_W8(0x82, 0x01); | |
1773 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
1774 | mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 | |
1775 | } | |
1776 | ||
bf793295 FR |
1777 | rtl8169_phy_reset(dev, tp); |
1778 | ||
901dda2b FR |
1779 | /* |
1780 | * rtl8169_set_speed_xmii takes good care of the Fast Ethernet | |
1781 | * only 8101. Don't panic. | |
1782 | */ | |
1783 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); | |
4ff96fa6 FR |
1784 | |
1785 | if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) | |
1786 | printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); | |
1787 | } | |
1788 | ||
773d2021 FR |
1789 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
1790 | { | |
1791 | void __iomem *ioaddr = tp->mmio_addr; | |
1792 | u32 high; | |
1793 | u32 low; | |
1794 | ||
1795 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
1796 | high = addr[4] | (addr[5] << 8); | |
1797 | ||
1798 | spin_lock_irq(&tp->lock); | |
1799 | ||
1800 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
1801 | RTL_W32(MAC0, low); | |
1802 | RTL_W32(MAC4, high); | |
1803 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
1804 | ||
1805 | spin_unlock_irq(&tp->lock); | |
1806 | } | |
1807 | ||
1808 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
1809 | { | |
1810 | struct rtl8169_private *tp = netdev_priv(dev); | |
1811 | struct sockaddr *addr = p; | |
1812 | ||
1813 | if (!is_valid_ether_addr(addr->sa_data)) | |
1814 | return -EADDRNOTAVAIL; | |
1815 | ||
1816 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1817 | ||
1818 | rtl_rar_set(tp, dev->dev_addr); | |
1819 | ||
1820 | return 0; | |
1821 | } | |
1822 | ||
5f787a1a FR |
1823 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1824 | { | |
1825 | struct rtl8169_private *tp = netdev_priv(dev); | |
1826 | struct mii_ioctl_data *data = if_mii(ifr); | |
1827 | ||
1828 | if (!netif_running(dev)) | |
1829 | return -ENODEV; | |
1830 | ||
1831 | switch (cmd) { | |
1832 | case SIOCGMIIPHY: | |
1833 | data->phy_id = 32; /* Internal PHY */ | |
1834 | return 0; | |
1835 | ||
1836 | case SIOCGMIIREG: | |
1837 | data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); | |
1838 | return 0; | |
1839 | ||
1840 | case SIOCSMIIREG: | |
1841 | if (!capable(CAP_NET_ADMIN)) | |
1842 | return -EPERM; | |
1843 | mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); | |
1844 | return 0; | |
1845 | } | |
1846 | return -EOPNOTSUPP; | |
1847 | } | |
1848 | ||
0e485150 FR |
1849 | static const struct rtl_cfg_info { |
1850 | void (*hw_start)(struct net_device *); | |
1851 | unsigned int region; | |
1852 | unsigned int align; | |
1853 | u16 intr_event; | |
1854 | u16 napi_event; | |
ccdffb9a | 1855 | unsigned features; |
0e485150 FR |
1856 | } rtl_cfg_infos [] = { |
1857 | [RTL_CFG_0] = { | |
1858 | .hw_start = rtl_hw_start_8169, | |
1859 | .region = 1, | |
e9f63f30 | 1860 | .align = 0, |
0e485150 FR |
1861 | .intr_event = SYSErr | LinkChg | RxOverflow | |
1862 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 1863 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
ccdffb9a | 1864 | .features = RTL_FEATURE_GMII |
0e485150 FR |
1865 | }, |
1866 | [RTL_CFG_1] = { | |
1867 | .hw_start = rtl_hw_start_8168, | |
1868 | .region = 2, | |
1869 | .align = 8, | |
1870 | .intr_event = SYSErr | LinkChg | RxOverflow | | |
1871 | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 1872 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
ccdffb9a | 1873 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI |
0e485150 FR |
1874 | }, |
1875 | [RTL_CFG_2] = { | |
1876 | .hw_start = rtl_hw_start_8101, | |
1877 | .region = 2, | |
1878 | .align = 8, | |
1879 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
1880 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 1881 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
ccdffb9a | 1882 | .features = RTL_FEATURE_MSI |
0e485150 FR |
1883 | } |
1884 | }; | |
1885 | ||
fbac58fc FR |
1886 | /* Cfg9346_Unlock assumed. */ |
1887 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
1888 | const struct rtl_cfg_info *cfg) | |
1889 | { | |
1890 | unsigned msi = 0; | |
1891 | u8 cfg2; | |
1892 | ||
1893 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 1894 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
1895 | if (pci_enable_msi(pdev)) { |
1896 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
1897 | } else { | |
1898 | cfg2 |= MSIEnable; | |
1899 | msi = RTL_FEATURE_MSI; | |
1900 | } | |
1901 | } | |
1902 | RTL_W8(Config2, cfg2); | |
1903 | return msi; | |
1904 | } | |
1905 | ||
1906 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
1907 | { | |
1908 | if (tp->features & RTL_FEATURE_MSI) { | |
1909 | pci_disable_msi(pdev); | |
1910 | tp->features &= ~RTL_FEATURE_MSI; | |
1911 | } | |
1912 | } | |
1913 | ||
7bf6bf48 IV |
1914 | static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val) |
1915 | { | |
1916 | int ret, count = 100; | |
1917 | u16 status = 0; | |
1918 | u32 value; | |
1919 | ||
1920 | ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr); | |
1921 | if (ret < 0) | |
1922 | return ret; | |
1923 | ||
1924 | do { | |
1925 | udelay(10); | |
1926 | ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status); | |
1927 | if (ret < 0) | |
1928 | return ret; | |
1929 | } while (!(status & PCI_VPD_ADDR_F) && --count); | |
1930 | ||
1931 | if (!(status & PCI_VPD_ADDR_F)) | |
1932 | return -ETIMEDOUT; | |
1933 | ||
1934 | ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value); | |
1935 | if (ret < 0) | |
1936 | return ret; | |
1937 | ||
1938 | *val = cpu_to_le32(value); | |
1939 | ||
1940 | return 0; | |
1941 | } | |
1942 | ||
1943 | static void rtl_init_mac_address(struct rtl8169_private *tp, | |
1944 | void __iomem *ioaddr) | |
1945 | { | |
1946 | struct pci_dev *pdev = tp->pci_dev; | |
1947 | u8 cfg1; | |
1948 | int vpd_cap; | |
1949 | u8 mac[8]; | |
1950 | DECLARE_MAC_BUF(buf); | |
1951 | ||
1952 | cfg1 = RTL_R8(Config1); | |
1953 | if (!(cfg1 & VPD)) { | |
1954 | dprintk("VPD access not enabled, enabling\n"); | |
1955 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
1956 | RTL_W8(Config1, cfg1 | VPD); | |
1957 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
1958 | } | |
1959 | ||
1960 | vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD); | |
1961 | if (!vpd_cap) | |
1962 | return; | |
1963 | ||
1964 | /* MAC address is stored in EEPROM at offset 0x0e | |
1965 | * Realtek says: "The VPD address does not have to be a DWORD-aligned | |
1966 | * address as defined in the PCI 2.2 Specifications, but the VPD data | |
1967 | * is always consecutive 4-byte data starting from the VPD address | |
1968 | * specified." | |
1969 | */ | |
1970 | if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 || | |
1971 | rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) { | |
1972 | dprintk("Reading MAC address from EEPROM failed\n"); | |
1973 | return; | |
1974 | } | |
1975 | ||
1976 | dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac)); | |
1977 | ||
1978 | /* Write MAC address */ | |
1979 | rtl_rar_set(tp, mac); | |
1980 | } | |
1981 | ||
1da177e4 | 1982 | static int __devinit |
4ff96fa6 | 1983 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1984 | { |
0e485150 FR |
1985 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
1986 | const unsigned int region = cfg->region; | |
1da177e4 | 1987 | struct rtl8169_private *tp; |
ccdffb9a | 1988 | struct mii_if_info *mii; |
4ff96fa6 FR |
1989 | struct net_device *dev; |
1990 | void __iomem *ioaddr; | |
07d3f51f FR |
1991 | unsigned int i; |
1992 | int rc; | |
1da177e4 | 1993 | |
4ff96fa6 FR |
1994 | if (netif_msg_drv(&debug)) { |
1995 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
1996 | MODULENAME, RTL8169_VERSION); | |
1997 | } | |
1da177e4 | 1998 | |
1da177e4 | 1999 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 2000 | if (!dev) { |
b57b7e5a | 2001 | if (netif_msg_drv(&debug)) |
9b91cf9d | 2002 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
2003 | rc = -ENOMEM; |
2004 | goto out; | |
1da177e4 LT |
2005 | } |
2006 | ||
1da177e4 LT |
2007 | SET_NETDEV_DEV(dev, &pdev->dev); |
2008 | tp = netdev_priv(dev); | |
c4028958 | 2009 | tp->dev = dev; |
21e197f2 | 2010 | tp->pci_dev = pdev; |
b57b7e5a | 2011 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 2012 | |
ccdffb9a FR |
2013 | mii = &tp->mii; |
2014 | mii->dev = dev; | |
2015 | mii->mdio_read = rtl_mdio_read; | |
2016 | mii->mdio_write = rtl_mdio_write; | |
2017 | mii->phy_id_mask = 0x1f; | |
2018 | mii->reg_num_mask = 0x1f; | |
2019 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
2020 | ||
1da177e4 LT |
2021 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
2022 | rc = pci_enable_device(pdev); | |
b57b7e5a | 2023 | if (rc < 0) { |
2e8a538d | 2024 | if (netif_msg_probe(tp)) |
9b91cf9d | 2025 | dev_err(&pdev->dev, "enable failure\n"); |
4ff96fa6 | 2026 | goto err_out_free_dev_1; |
1da177e4 LT |
2027 | } |
2028 | ||
2029 | rc = pci_set_mwi(pdev); | |
2030 | if (rc < 0) | |
4ff96fa6 | 2031 | goto err_out_disable_2; |
1da177e4 | 2032 | |
1da177e4 | 2033 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 2034 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
4ff96fa6 | 2035 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2036 | dev_err(&pdev->dev, |
bcf0bf90 FR |
2037 | "region #%d not an MMIO resource, aborting\n", |
2038 | region); | |
4ff96fa6 | 2039 | } |
1da177e4 | 2040 | rc = -ENODEV; |
4ff96fa6 | 2041 | goto err_out_mwi_3; |
1da177e4 | 2042 | } |
4ff96fa6 | 2043 | |
1da177e4 | 2044 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 2045 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
4ff96fa6 | 2046 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2047 | dev_err(&pdev->dev, |
4ff96fa6 FR |
2048 | "Invalid PCI region size(s), aborting\n"); |
2049 | } | |
1da177e4 | 2050 | rc = -ENODEV; |
4ff96fa6 | 2051 | goto err_out_mwi_3; |
1da177e4 LT |
2052 | } |
2053 | ||
2054 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 2055 | if (rc < 0) { |
2e8a538d | 2056 | if (netif_msg_probe(tp)) |
9b91cf9d | 2057 | dev_err(&pdev->dev, "could not request regions.\n"); |
4ff96fa6 | 2058 | goto err_out_mwi_3; |
1da177e4 LT |
2059 | } |
2060 | ||
2061 | tp->cp_cmd = PCIMulRW | RxChkSum; | |
2062 | ||
2063 | if ((sizeof(dma_addr_t) > 4) && | |
2064 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { | |
2065 | tp->cp_cmd |= PCIDAC; | |
2066 | dev->features |= NETIF_F_HIGHDMA; | |
2067 | } else { | |
2068 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2069 | if (rc < 0) { | |
4ff96fa6 | 2070 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2071 | dev_err(&pdev->dev, |
4ff96fa6 FR |
2072 | "DMA configuration failed.\n"); |
2073 | } | |
2074 | goto err_out_free_res_4; | |
1da177e4 LT |
2075 | } |
2076 | } | |
2077 | ||
2078 | pci_set_master(pdev); | |
2079 | ||
2080 | /* ioremap MMIO region */ | |
bcf0bf90 | 2081 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 2082 | if (!ioaddr) { |
b57b7e5a | 2083 | if (netif_msg_probe(tp)) |
9b91cf9d | 2084 | dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 2085 | rc = -EIO; |
4ff96fa6 | 2086 | goto err_out_free_res_4; |
1da177e4 LT |
2087 | } |
2088 | ||
9c14ceaf FR |
2089 | tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
2090 | if (!tp->pcie_cap && netif_msg_probe(tp)) | |
2091 | dev_info(&pdev->dev, "no PCI Express capability\n"); | |
2092 | ||
1da177e4 LT |
2093 | /* Unneeded ? Don't mess with Mrs. Murphy. */ |
2094 | rtl8169_irq_mask_and_ack(ioaddr); | |
2095 | ||
2096 | /* Soft reset the chip. */ | |
2097 | RTL_W8(ChipCmd, CmdReset); | |
2098 | ||
2099 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 2100 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
2101 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
2102 | break; | |
b518fa8e | 2103 | msleep_interruptible(1); |
1da177e4 LT |
2104 | } |
2105 | ||
2106 | /* Identify chip attached to board */ | |
2107 | rtl8169_get_mac_version(tp, ioaddr); | |
1da177e4 LT |
2108 | |
2109 | rtl8169_print_mac_version(tp); | |
1da177e4 | 2110 | |
cee60c37 | 2111 | for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
1da177e4 LT |
2112 | if (tp->mac_version == rtl_chip_info[i].mac_version) |
2113 | break; | |
2114 | } | |
cee60c37 | 2115 | if (i == ARRAY_SIZE(rtl_chip_info)) { |
1da177e4 | 2116 | /* Unknown chip: assume array element #0, original RTL-8169 */ |
b57b7e5a | 2117 | if (netif_msg_probe(tp)) { |
2e8a538d | 2118 | dev_printk(KERN_DEBUG, &pdev->dev, |
4ff96fa6 FR |
2119 | "unknown chip version, assuming %s\n", |
2120 | rtl_chip_info[0].name); | |
b57b7e5a | 2121 | } |
cee60c37 | 2122 | i = 0; |
1da177e4 LT |
2123 | } |
2124 | tp->chipset = i; | |
2125 | ||
5d06a99f FR |
2126 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
2127 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
2128 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
2129 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
2130 | tp->features |= RTL_FEATURE_WOL; | |
2131 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
2132 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 2133 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
2134 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2135 | ||
66ec5d4f FR |
2136 | if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
2137 | (RTL_R8(PHYstatus) & TBI_Enable)) { | |
1da177e4 LT |
2138 | tp->set_speed = rtl8169_set_speed_tbi; |
2139 | tp->get_settings = rtl8169_gset_tbi; | |
2140 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
2141 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
2142 | tp->link_ok = rtl8169_tbi_link_ok; | |
2143 | ||
64e4bfb4 | 2144 | tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
1da177e4 LT |
2145 | } else { |
2146 | tp->set_speed = rtl8169_set_speed_xmii; | |
2147 | tp->get_settings = rtl8169_gset_xmii; | |
2148 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
2149 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
2150 | tp->link_ok = rtl8169_xmii_link_ok; | |
5f787a1a FR |
2151 | |
2152 | dev->do_ioctl = rtl8169_ioctl; | |
1da177e4 LT |
2153 | } |
2154 | ||
df58ef51 FR |
2155 | spin_lock_init(&tp->lock); |
2156 | ||
7bf6bf48 IV |
2157 | rtl_init_mac_address(tp, ioaddr); |
2158 | ||
2159 | /* Get MAC address */ | |
1da177e4 LT |
2160 | for (i = 0; i < MAC_ADDR_LEN; i++) |
2161 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 2162 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
2163 | |
2164 | dev->open = rtl8169_open; | |
2165 | dev->hard_start_xmit = rtl8169_start_xmit; | |
2166 | dev->get_stats = rtl8169_get_stats; | |
2167 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); | |
2168 | dev->stop = rtl8169_close; | |
2169 | dev->tx_timeout = rtl8169_tx_timeout; | |
07ce4064 | 2170 | dev->set_multicast_list = rtl_set_rx_mode; |
1da177e4 LT |
2171 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
2172 | dev->irq = pdev->irq; | |
2173 | dev->base_addr = (unsigned long) ioaddr; | |
2174 | dev->change_mtu = rtl8169_change_mtu; | |
773d2021 | 2175 | dev->set_mac_address = rtl_set_mac_address; |
1da177e4 | 2176 | |
bea3348e | 2177 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 LT |
2178 | |
2179 | #ifdef CONFIG_R8169_VLAN | |
2180 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
2181 | dev->vlan_rx_register = rtl8169_vlan_rx_register; | |
1da177e4 LT |
2182 | #endif |
2183 | ||
2184 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2185 | dev->poll_controller = rtl8169_netpoll; | |
2186 | #endif | |
2187 | ||
2188 | tp->intr_mask = 0xffff; | |
1da177e4 | 2189 | tp->mmio_addr = ioaddr; |
0e485150 FR |
2190 | tp->align = cfg->align; |
2191 | tp->hw_start = cfg->hw_start; | |
2192 | tp->intr_event = cfg->intr_event; | |
2193 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 2194 | |
2efa53f3 FR |
2195 | init_timer(&tp->timer); |
2196 | tp->timer.data = (unsigned long) dev; | |
2197 | tp->timer.function = rtl8169_phy_timer; | |
2198 | ||
1da177e4 | 2199 | rc = register_netdev(dev); |
4ff96fa6 | 2200 | if (rc < 0) |
fbac58fc | 2201 | goto err_out_msi_5; |
1da177e4 LT |
2202 | |
2203 | pci_set_drvdata(pdev, dev); | |
2204 | ||
b57b7e5a | 2205 | if (netif_msg_probe(tp)) { |
96b9709c FR |
2206 | u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
2207 | ||
b57b7e5a SH |
2208 | printk(KERN_INFO "%s: %s at 0x%lx, " |
2209 | "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " | |
96b9709c | 2210 | "XID %08x IRQ %d\n", |
b57b7e5a | 2211 | dev->name, |
bcf0bf90 | 2212 | rtl_chip_info[tp->chipset].name, |
b57b7e5a SH |
2213 | dev->base_addr, |
2214 | dev->dev_addr[0], dev->dev_addr[1], | |
2215 | dev->dev_addr[2], dev->dev_addr[3], | |
96b9709c | 2216 | dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
b57b7e5a | 2217 | } |
1da177e4 | 2218 | |
4ff96fa6 | 2219 | rtl8169_init_phy(dev, tp); |
8b76ab39 | 2220 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 2221 | |
4ff96fa6 FR |
2222 | out: |
2223 | return rc; | |
1da177e4 | 2224 | |
fbac58fc FR |
2225 | err_out_msi_5: |
2226 | rtl_disable_msi(pdev, tp); | |
4ff96fa6 FR |
2227 | iounmap(ioaddr); |
2228 | err_out_free_res_4: | |
2229 | pci_release_regions(pdev); | |
2230 | err_out_mwi_3: | |
2231 | pci_clear_mwi(pdev); | |
2232 | err_out_disable_2: | |
2233 | pci_disable_device(pdev); | |
2234 | err_out_free_dev_1: | |
2235 | free_netdev(dev); | |
2236 | goto out; | |
1da177e4 LT |
2237 | } |
2238 | ||
07d3f51f | 2239 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
2240 | { |
2241 | struct net_device *dev = pci_get_drvdata(pdev); | |
2242 | struct rtl8169_private *tp = netdev_priv(dev); | |
2243 | ||
eb2a021c FR |
2244 | flush_scheduled_work(); |
2245 | ||
1da177e4 | 2246 | unregister_netdev(dev); |
fbac58fc | 2247 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
2248 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
2249 | pci_set_drvdata(pdev, NULL); | |
2250 | } | |
2251 | ||
1da177e4 LT |
2252 | static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
2253 | struct net_device *dev) | |
2254 | { | |
2255 | unsigned int mtu = dev->mtu; | |
2256 | ||
2257 | tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; | |
2258 | } | |
2259 | ||
2260 | static int rtl8169_open(struct net_device *dev) | |
2261 | { | |
2262 | struct rtl8169_private *tp = netdev_priv(dev); | |
2263 | struct pci_dev *pdev = tp->pci_dev; | |
99f252b0 | 2264 | int retval = -ENOMEM; |
1da177e4 | 2265 | |
1da177e4 | 2266 | |
99f252b0 | 2267 | rtl8169_set_rxbufsize(tp, dev); |
1da177e4 LT |
2268 | |
2269 | /* | |
2270 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
2271 | * pci_alloc_consistent provides more. | |
2272 | */ | |
2273 | tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, | |
2274 | &tp->TxPhyAddr); | |
2275 | if (!tp->TxDescArray) | |
99f252b0 | 2276 | goto out; |
1da177e4 LT |
2277 | |
2278 | tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, | |
2279 | &tp->RxPhyAddr); | |
2280 | if (!tp->RxDescArray) | |
99f252b0 | 2281 | goto err_free_tx_0; |
1da177e4 LT |
2282 | |
2283 | retval = rtl8169_init_ring(dev); | |
2284 | if (retval < 0) | |
99f252b0 | 2285 | goto err_free_rx_1; |
1da177e4 | 2286 | |
c4028958 | 2287 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 2288 | |
99f252b0 FR |
2289 | smp_mb(); |
2290 | ||
fbac58fc FR |
2291 | retval = request_irq(dev->irq, rtl8169_interrupt, |
2292 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
2293 | dev->name, dev); |
2294 | if (retval < 0) | |
2295 | goto err_release_ring_2; | |
2296 | ||
bea3348e | 2297 | napi_enable(&tp->napi); |
bea3348e | 2298 | |
07ce4064 | 2299 | rtl_hw_start(dev); |
1da177e4 LT |
2300 | |
2301 | rtl8169_request_timer(dev); | |
2302 | ||
2303 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
2304 | out: | |
2305 | return retval; | |
2306 | ||
99f252b0 FR |
2307 | err_release_ring_2: |
2308 | rtl8169_rx_clear(tp); | |
2309 | err_free_rx_1: | |
1da177e4 LT |
2310 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
2311 | tp->RxPhyAddr); | |
99f252b0 | 2312 | err_free_tx_0: |
1da177e4 LT |
2313 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
2314 | tp->TxPhyAddr); | |
1da177e4 LT |
2315 | goto out; |
2316 | } | |
2317 | ||
2318 | static void rtl8169_hw_reset(void __iomem *ioaddr) | |
2319 | { | |
2320 | /* Disable interrupts */ | |
2321 | rtl8169_irq_mask_and_ack(ioaddr); | |
2322 | ||
2323 | /* Reset the chipset */ | |
2324 | RTL_W8(ChipCmd, CmdReset); | |
2325 | ||
2326 | /* PCI commit */ | |
2327 | RTL_R8(ChipCmd); | |
2328 | } | |
2329 | ||
7f796d83 | 2330 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
2331 | { |
2332 | void __iomem *ioaddr = tp->mmio_addr; | |
2333 | u32 cfg = rtl8169_rx_config; | |
2334 | ||
2335 | cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
2336 | RTL_W32(RxConfig, cfg); | |
2337 | ||
2338 | /* Set DMA burst size and Interframe Gap Time */ | |
2339 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
2340 | (InterFrameGap << TxInterFrameGapShift)); | |
2341 | } | |
2342 | ||
07ce4064 | 2343 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
2344 | { |
2345 | struct rtl8169_private *tp = netdev_priv(dev); | |
2346 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 2347 | unsigned int i; |
1da177e4 LT |
2348 | |
2349 | /* Soft reset the chip. */ | |
2350 | RTL_W8(ChipCmd, CmdReset); | |
2351 | ||
2352 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 2353 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
2354 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
2355 | break; | |
b518fa8e | 2356 | msleep_interruptible(1); |
1da177e4 LT |
2357 | } |
2358 | ||
07ce4064 FR |
2359 | tp->hw_start(dev); |
2360 | ||
07ce4064 FR |
2361 | netif_start_queue(dev); |
2362 | } | |
2363 | ||
2364 | ||
7f796d83 FR |
2365 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
2366 | void __iomem *ioaddr) | |
2367 | { | |
2368 | /* | |
2369 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
2370 | * register to be written before TxDescAddrLow to work. | |
2371 | * Switching from MMIO to I/O access fixes the issue as well. | |
2372 | */ | |
2373 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
2374 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); | |
2375 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); | |
2376 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); | |
2377 | } | |
2378 | ||
2379 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
2380 | { | |
2381 | u16 cmd; | |
2382 | ||
2383 | cmd = RTL_R16(CPlusCmd); | |
2384 | RTL_W16(CPlusCmd, cmd); | |
2385 | return cmd; | |
2386 | } | |
2387 | ||
2388 | static void rtl_set_rx_max_size(void __iomem *ioaddr) | |
2389 | { | |
2390 | /* Low hurts. Let's disable the filtering. */ | |
2391 | RTL_W16(RxMaxSize, 16383); | |
2392 | } | |
2393 | ||
6dccd16b FR |
2394 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
2395 | { | |
2396 | struct { | |
2397 | u32 mac_version; | |
2398 | u32 clk; | |
2399 | u32 val; | |
2400 | } cfg2_info [] = { | |
2401 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
2402 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
2403 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
2404 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
2405 | }, *p = cfg2_info; | |
2406 | unsigned int i; | |
2407 | u32 clk; | |
2408 | ||
2409 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 2410 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
2411 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
2412 | RTL_W32(0x7c, p->val); | |
2413 | break; | |
2414 | } | |
2415 | } | |
2416 | } | |
2417 | ||
07ce4064 FR |
2418 | static void rtl_hw_start_8169(struct net_device *dev) |
2419 | { | |
2420 | struct rtl8169_private *tp = netdev_priv(dev); | |
2421 | void __iomem *ioaddr = tp->mmio_addr; | |
2422 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 2423 | |
9cb427b6 FR |
2424 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
2425 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
2426 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
2427 | } | |
2428 | ||
1da177e4 | 2429 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
9cb427b6 FR |
2430 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2431 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2432 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2433 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2434 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2435 | ||
1da177e4 LT |
2436 | RTL_W8(EarlyTxThres, EarlyTxThld); |
2437 | ||
7f796d83 | 2438 | rtl_set_rx_max_size(ioaddr); |
1da177e4 | 2439 | |
c946b304 FR |
2440 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2441 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2442 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2443 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2444 | rtl_set_rx_tx_config_registers(tp); | |
1da177e4 | 2445 | |
7f796d83 | 2446 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 2447 | |
bcf0bf90 FR |
2448 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
2449 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
06fa7358 | 2450 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 2451 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 2452 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
2453 | } |
2454 | ||
bcf0bf90 FR |
2455 | RTL_W16(CPlusCmd, tp->cp_cmd); |
2456 | ||
6dccd16b FR |
2457 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
2458 | ||
1da177e4 LT |
2459 | /* |
2460 | * Undocumented corner. Supposedly: | |
2461 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
2462 | */ | |
2463 | RTL_W16(IntrMitigate, 0x0000); | |
2464 | ||
7f796d83 | 2465 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 2466 | |
c946b304 FR |
2467 | if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
2468 | (tp->mac_version != RTL_GIGA_MAC_VER_02) && | |
2469 | (tp->mac_version != RTL_GIGA_MAC_VER_03) && | |
2470 | (tp->mac_version != RTL_GIGA_MAC_VER_04)) { | |
2471 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2472 | rtl_set_rx_tx_config_registers(tp); | |
2473 | } | |
2474 | ||
1da177e4 | 2475 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
2476 | |
2477 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
2478 | RTL_R8(IntrMask); | |
1da177e4 LT |
2479 | |
2480 | RTL_W32(RxMissed, 0); | |
2481 | ||
07ce4064 | 2482 | rtl_set_rx_mode(dev); |
1da177e4 LT |
2483 | |
2484 | /* no early-rx interrupts */ | |
2485 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
2486 | |
2487 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 2488 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2489 | } |
1da177e4 | 2490 | |
9c14ceaf | 2491 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
458a9f61 | 2492 | { |
9c14ceaf FR |
2493 | struct net_device *dev = pci_get_drvdata(pdev); |
2494 | struct rtl8169_private *tp = netdev_priv(dev); | |
2495 | int cap = tp->pcie_cap; | |
2496 | ||
2497 | if (cap) { | |
2498 | u16 ctl; | |
458a9f61 | 2499 | |
9c14ceaf FR |
2500 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
2501 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
2502 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
2503 | } | |
458a9f61 FR |
2504 | } |
2505 | ||
dacf8154 FR |
2506 | static void rtl_csi_access_enable(void __iomem *ioaddr) |
2507 | { | |
2508 | u32 csi; | |
2509 | ||
2510 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
2511 | rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); | |
2512 | } | |
2513 | ||
2514 | struct ephy_info { | |
2515 | unsigned int offset; | |
2516 | u16 mask; | |
2517 | u16 bits; | |
2518 | }; | |
2519 | ||
2520 | static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) | |
2521 | { | |
2522 | u16 w; | |
2523 | ||
2524 | while (len-- > 0) { | |
2525 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
2526 | rtl_ephy_write(ioaddr, e->offset, w); | |
2527 | e++; | |
2528 | } | |
2529 | } | |
2530 | ||
b726e493 FR |
2531 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
2532 | { | |
2533 | struct net_device *dev = pci_get_drvdata(pdev); | |
2534 | struct rtl8169_private *tp = netdev_priv(dev); | |
2535 | int cap = tp->pcie_cap; | |
2536 | ||
2537 | if (cap) { | |
2538 | u16 ctl; | |
2539 | ||
2540 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
2541 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
2542 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
2543 | } | |
2544 | } | |
2545 | ||
2546 | #define R8168_CPCMD_QUIRK_MASK (\ | |
2547 | EnableBist | \ | |
2548 | Mac_dbgo_oe | \ | |
2549 | Force_half_dup | \ | |
2550 | Force_rxflow_en | \ | |
2551 | Force_txflow_en | \ | |
2552 | Cxpl_dbg_sel | \ | |
2553 | ASF | \ | |
2554 | PktCntrDisable | \ | |
2555 | Mac_dbgo_sel) | |
2556 | ||
219a1e9d FR |
2557 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
2558 | { | |
b726e493 FR |
2559 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
2560 | ||
2561 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2562 | ||
2e68ae44 FR |
2563 | rtl_tx_performance_tweak(pdev, |
2564 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
2565 | } |
2566 | ||
2567 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
2568 | { | |
2569 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 FR |
2570 | |
2571 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2572 | ||
2573 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
2574 | } |
2575 | ||
2576 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
2577 | { | |
b726e493 FR |
2578 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
2579 | ||
2580 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2581 | ||
219a1e9d | 2582 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
2583 | |
2584 | rtl_disable_clock_request(pdev); | |
2585 | ||
2586 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
2587 | } |
2588 | ||
ef3386f0 | 2589 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 2590 | { |
b726e493 FR |
2591 | static struct ephy_info e_info_8168cp[] = { |
2592 | { 0x01, 0, 0x0001 }, | |
2593 | { 0x02, 0x0800, 0x1000 }, | |
2594 | { 0x03, 0, 0x0042 }, | |
2595 | { 0x06, 0x0080, 0x0000 }, | |
2596 | { 0x07, 0, 0x2000 } | |
2597 | }; | |
2598 | ||
2599 | rtl_csi_access_enable(ioaddr); | |
2600 | ||
2601 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
2602 | ||
219a1e9d FR |
2603 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2604 | } | |
2605 | ||
ef3386f0 FR |
2606 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
2607 | { | |
2608 | rtl_csi_access_enable(ioaddr); | |
2609 | ||
2610 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2611 | ||
2612 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2613 | ||
2614 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2615 | } | |
2616 | ||
7f3e3d3a FR |
2617 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
2618 | { | |
2619 | rtl_csi_access_enable(ioaddr); | |
2620 | ||
2621 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2622 | ||
2623 | /* Magic. */ | |
2624 | RTL_W8(DBG_REG, 0x20); | |
2625 | ||
2626 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2627 | ||
2628 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2629 | ||
2630 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2631 | } | |
2632 | ||
219a1e9d FR |
2633 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
2634 | { | |
b726e493 FR |
2635 | static struct ephy_info e_info_8168c_1[] = { |
2636 | { 0x02, 0x0800, 0x1000 }, | |
2637 | { 0x03, 0, 0x0002 }, | |
2638 | { 0x06, 0x0080, 0x0000 } | |
2639 | }; | |
2640 | ||
2641 | rtl_csi_access_enable(ioaddr); | |
2642 | ||
2643 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
2644 | ||
2645 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
2646 | ||
219a1e9d FR |
2647 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2648 | } | |
2649 | ||
2650 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
2651 | { | |
b726e493 FR |
2652 | static struct ephy_info e_info_8168c_2[] = { |
2653 | { 0x01, 0, 0x0001 }, | |
2654 | { 0x03, 0x0400, 0x0220 } | |
2655 | }; | |
2656 | ||
2657 | rtl_csi_access_enable(ioaddr); | |
2658 | ||
2659 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
2660 | ||
219a1e9d FR |
2661 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2662 | } | |
2663 | ||
197ff761 FR |
2664 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
2665 | { | |
2666 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
2667 | } | |
2668 | ||
6fb07058 FR |
2669 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
2670 | { | |
2671 | rtl_csi_access_enable(ioaddr); | |
2672 | ||
2673 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
2674 | } | |
2675 | ||
5b538df9 FR |
2676 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
2677 | { | |
2678 | rtl_csi_access_enable(ioaddr); | |
2679 | ||
2680 | rtl_disable_clock_request(pdev); | |
2681 | ||
2682 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2683 | ||
2684 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2685 | ||
2686 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2687 | } | |
2688 | ||
07ce4064 FR |
2689 | static void rtl_hw_start_8168(struct net_device *dev) |
2690 | { | |
2dd99530 FR |
2691 | struct rtl8169_private *tp = netdev_priv(dev); |
2692 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 2693 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
2694 | |
2695 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2696 | ||
2697 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2698 | ||
2699 | rtl_set_rx_max_size(ioaddr); | |
2700 | ||
0e485150 | 2701 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
2702 | |
2703 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2704 | ||
0e485150 | 2705 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 2706 | |
0e485150 FR |
2707 | /* Work around for RxFIFO overflow. */ |
2708 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { | |
2709 | tp->intr_event |= RxFIFOOver | PCSTimeout; | |
2710 | tp->intr_event &= ~RxOverflow; | |
2711 | } | |
2712 | ||
2713 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 2714 | |
b8363901 FR |
2715 | rtl_set_rx_mode(dev); |
2716 | ||
2717 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
2718 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
2719 | |
2720 | RTL_R8(IntrMask); | |
2721 | ||
219a1e9d FR |
2722 | switch (tp->mac_version) { |
2723 | case RTL_GIGA_MAC_VER_11: | |
2724 | rtl_hw_start_8168bb(ioaddr, pdev); | |
2725 | break; | |
2726 | ||
2727 | case RTL_GIGA_MAC_VER_12: | |
2728 | case RTL_GIGA_MAC_VER_17: | |
2729 | rtl_hw_start_8168bef(ioaddr, pdev); | |
2730 | break; | |
2731 | ||
2732 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 2733 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
219a1e9d FR |
2734 | break; |
2735 | ||
2736 | case RTL_GIGA_MAC_VER_19: | |
2737 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
2738 | break; | |
2739 | ||
2740 | case RTL_GIGA_MAC_VER_20: | |
2741 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
2742 | break; | |
2743 | ||
197ff761 FR |
2744 | case RTL_GIGA_MAC_VER_21: |
2745 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
2746 | break; | |
2747 | ||
6fb07058 FR |
2748 | case RTL_GIGA_MAC_VER_22: |
2749 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
2750 | break; | |
2751 | ||
ef3386f0 FR |
2752 | case RTL_GIGA_MAC_VER_23: |
2753 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
2754 | break; | |
2755 | ||
7f3e3d3a FR |
2756 | case RTL_GIGA_MAC_VER_24: |
2757 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
2758 | break; | |
2759 | ||
5b538df9 FR |
2760 | case RTL_GIGA_MAC_VER_25: |
2761 | rtl_hw_start_8168d(ioaddr, pdev); | |
2762 | break; | |
2763 | ||
219a1e9d FR |
2764 | default: |
2765 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
2766 | dev->name, tp->mac_version); | |
2767 | break; | |
2768 | } | |
2dd99530 | 2769 | |
0e485150 FR |
2770 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2771 | ||
b8363901 FR |
2772 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2773 | ||
2dd99530 | 2774 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 2775 | |
0e485150 | 2776 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2777 | } |
1da177e4 | 2778 | |
2857ffb7 FR |
2779 | #define R810X_CPCMD_QUIRK_MASK (\ |
2780 | EnableBist | \ | |
2781 | Mac_dbgo_oe | \ | |
2782 | Force_half_dup | \ | |
2783 | Force_half_dup | \ | |
2784 | Force_txflow_en | \ | |
2785 | Cxpl_dbg_sel | \ | |
2786 | ASF | \ | |
2787 | PktCntrDisable | \ | |
2788 | PCIDAC | \ | |
2789 | PCIMulRW) | |
2790 | ||
2791 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
2792 | { | |
2793 | static struct ephy_info e_info_8102e_1[] = { | |
2794 | { 0x01, 0, 0x6e65 }, | |
2795 | { 0x02, 0, 0x091f }, | |
2796 | { 0x03, 0, 0xc2f9 }, | |
2797 | { 0x06, 0, 0xafb5 }, | |
2798 | { 0x07, 0, 0x0e00 }, | |
2799 | { 0x19, 0, 0xec80 }, | |
2800 | { 0x01, 0, 0x2e65 }, | |
2801 | { 0x01, 0, 0x6e65 } | |
2802 | }; | |
2803 | u8 cfg1; | |
2804 | ||
2805 | rtl_csi_access_enable(ioaddr); | |
2806 | ||
2807 | RTL_W8(DBG_REG, FIX_NAK_1); | |
2808 | ||
2809 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2810 | ||
2811 | RTL_W8(Config1, | |
2812 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
2813 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2814 | ||
2815 | cfg1 = RTL_R8(Config1); | |
2816 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
2817 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
2818 | ||
2819 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); | |
2820 | ||
2821 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); | |
2822 | } | |
2823 | ||
2824 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
2825 | { | |
2826 | rtl_csi_access_enable(ioaddr); | |
2827 | ||
2828 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2829 | ||
2830 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
2831 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2832 | ||
2833 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); | |
2834 | } | |
2835 | ||
2836 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
2837 | { | |
2838 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
2839 | ||
2840 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
2841 | } | |
2842 | ||
07ce4064 FR |
2843 | static void rtl_hw_start_8101(struct net_device *dev) |
2844 | { | |
cdf1a608 FR |
2845 | struct rtl8169_private *tp = netdev_priv(dev); |
2846 | void __iomem *ioaddr = tp->mmio_addr; | |
2847 | struct pci_dev *pdev = tp->pci_dev; | |
2848 | ||
e3cf0cc0 FR |
2849 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
2850 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
9c14ceaf FR |
2851 | int cap = tp->pcie_cap; |
2852 | ||
2853 | if (cap) { | |
2854 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
2855 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
2856 | } | |
cdf1a608 FR |
2857 | } |
2858 | ||
2857ffb7 FR |
2859 | switch (tp->mac_version) { |
2860 | case RTL_GIGA_MAC_VER_07: | |
2861 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
2862 | break; | |
2863 | ||
2864 | case RTL_GIGA_MAC_VER_08: | |
2865 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
2866 | break; | |
2867 | ||
2868 | case RTL_GIGA_MAC_VER_09: | |
2869 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
2870 | break; | |
cdf1a608 FR |
2871 | } |
2872 | ||
2873 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2874 | ||
2875 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2876 | ||
2877 | rtl_set_rx_max_size(ioaddr); | |
2878 | ||
2879 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; | |
2880 | ||
2881 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2882 | ||
2883 | RTL_W16(IntrMitigate, 0x0000); | |
2884 | ||
2885 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2886 | ||
2887 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2888 | rtl_set_rx_tx_config_registers(tp); | |
2889 | ||
2890 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
2891 | ||
2892 | RTL_R8(IntrMask); | |
2893 | ||
cdf1a608 FR |
2894 | rtl_set_rx_mode(dev); |
2895 | ||
0e485150 FR |
2896 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2897 | ||
cdf1a608 | 2898 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
6dccd16b | 2899 | |
0e485150 | 2900 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
2901 | } |
2902 | ||
2903 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
2904 | { | |
2905 | struct rtl8169_private *tp = netdev_priv(dev); | |
2906 | int ret = 0; | |
2907 | ||
2908 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) | |
2909 | return -EINVAL; | |
2910 | ||
2911 | dev->mtu = new_mtu; | |
2912 | ||
2913 | if (!netif_running(dev)) | |
2914 | goto out; | |
2915 | ||
2916 | rtl8169_down(dev); | |
2917 | ||
2918 | rtl8169_set_rxbufsize(tp, dev); | |
2919 | ||
2920 | ret = rtl8169_init_ring(dev); | |
2921 | if (ret < 0) | |
2922 | goto out; | |
2923 | ||
bea3348e | 2924 | napi_enable(&tp->napi); |
1da177e4 | 2925 | |
07ce4064 | 2926 | rtl_hw_start(dev); |
1da177e4 LT |
2927 | |
2928 | rtl8169_request_timer(dev); | |
2929 | ||
2930 | out: | |
2931 | return ret; | |
2932 | } | |
2933 | ||
2934 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
2935 | { | |
95e0918d | 2936 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
2937 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
2938 | } | |
2939 | ||
2940 | static void rtl8169_free_rx_skb(struct rtl8169_private *tp, | |
2941 | struct sk_buff **sk_buff, struct RxDesc *desc) | |
2942 | { | |
2943 | struct pci_dev *pdev = tp->pci_dev; | |
2944 | ||
2945 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, | |
2946 | PCI_DMA_FROMDEVICE); | |
2947 | dev_kfree_skb(*sk_buff); | |
2948 | *sk_buff = NULL; | |
2949 | rtl8169_make_unusable_by_asic(desc); | |
2950 | } | |
2951 | ||
2952 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
2953 | { | |
2954 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
2955 | ||
2956 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
2957 | } | |
2958 | ||
2959 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
2960 | u32 rx_buf_sz) | |
2961 | { | |
2962 | desc->addr = cpu_to_le64(mapping); | |
2963 | wmb(); | |
2964 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
2965 | } | |
2966 | ||
15d31758 SH |
2967 | static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
2968 | struct net_device *dev, | |
2969 | struct RxDesc *desc, int rx_buf_sz, | |
2970 | unsigned int align) | |
1da177e4 LT |
2971 | { |
2972 | struct sk_buff *skb; | |
2973 | dma_addr_t mapping; | |
e9f63f30 | 2974 | unsigned int pad; |
1da177e4 | 2975 | |
e9f63f30 FR |
2976 | pad = align ? align : NET_IP_ALIGN; |
2977 | ||
2978 | skb = netdev_alloc_skb(dev, rx_buf_sz + pad); | |
1da177e4 LT |
2979 | if (!skb) |
2980 | goto err_out; | |
2981 | ||
e9f63f30 | 2982 | skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
1da177e4 | 2983 | |
689be439 | 2984 | mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
1da177e4 LT |
2985 | PCI_DMA_FROMDEVICE); |
2986 | ||
2987 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
1da177e4 | 2988 | out: |
15d31758 | 2989 | return skb; |
1da177e4 LT |
2990 | |
2991 | err_out: | |
1da177e4 LT |
2992 | rtl8169_make_unusable_by_asic(desc); |
2993 | goto out; | |
2994 | } | |
2995 | ||
2996 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
2997 | { | |
07d3f51f | 2998 | unsigned int i; |
1da177e4 LT |
2999 | |
3000 | for (i = 0; i < NUM_RX_DESC; i++) { | |
3001 | if (tp->Rx_skbuff[i]) { | |
3002 | rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, | |
3003 | tp->RxDescArray + i); | |
3004 | } | |
3005 | } | |
3006 | } | |
3007 | ||
3008 | static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, | |
3009 | u32 start, u32 end) | |
3010 | { | |
3011 | u32 cur; | |
5b0384f4 | 3012 | |
4ae47c2d | 3013 | for (cur = start; end - cur != 0; cur++) { |
15d31758 SH |
3014 | struct sk_buff *skb; |
3015 | unsigned int i = cur % NUM_RX_DESC; | |
1da177e4 | 3016 | |
4ae47c2d FR |
3017 | WARN_ON((s32)(end - cur) < 0); |
3018 | ||
1da177e4 LT |
3019 | if (tp->Rx_skbuff[i]) |
3020 | continue; | |
bcf0bf90 | 3021 | |
15d31758 SH |
3022 | skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
3023 | tp->RxDescArray + i, | |
3024 | tp->rx_buf_sz, tp->align); | |
3025 | if (!skb) | |
1da177e4 | 3026 | break; |
15d31758 SH |
3027 | |
3028 | tp->Rx_skbuff[i] = skb; | |
1da177e4 LT |
3029 | } |
3030 | return cur - start; | |
3031 | } | |
3032 | ||
3033 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) | |
3034 | { | |
3035 | desc->opts1 |= cpu_to_le32(RingEnd); | |
3036 | } | |
3037 | ||
3038 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) | |
3039 | { | |
3040 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
3041 | } | |
3042 | ||
3043 | static int rtl8169_init_ring(struct net_device *dev) | |
3044 | { | |
3045 | struct rtl8169_private *tp = netdev_priv(dev); | |
3046 | ||
3047 | rtl8169_init_ring_indexes(tp); | |
3048 | ||
3049 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
3050 | memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); | |
3051 | ||
3052 | if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) | |
3053 | goto err_out; | |
3054 | ||
3055 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); | |
3056 | ||
3057 | return 0; | |
3058 | ||
3059 | err_out: | |
3060 | rtl8169_rx_clear(tp); | |
3061 | return -ENOMEM; | |
3062 | } | |
3063 | ||
3064 | static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, | |
3065 | struct TxDesc *desc) | |
3066 | { | |
3067 | unsigned int len = tx_skb->len; | |
3068 | ||
3069 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); | |
3070 | desc->opts1 = 0x00; | |
3071 | desc->opts2 = 0x00; | |
3072 | desc->addr = 0x00; | |
3073 | tx_skb->len = 0; | |
3074 | } | |
3075 | ||
3076 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
3077 | { | |
3078 | unsigned int i; | |
3079 | ||
3080 | for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { | |
3081 | unsigned int entry = i % NUM_TX_DESC; | |
3082 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
3083 | unsigned int len = tx_skb->len; | |
3084 | ||
3085 | if (len) { | |
3086 | struct sk_buff *skb = tx_skb->skb; | |
3087 | ||
3088 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, | |
3089 | tp->TxDescArray + entry); | |
3090 | if (skb) { | |
3091 | dev_kfree_skb(skb); | |
3092 | tx_skb->skb = NULL; | |
3093 | } | |
cebf8cc7 | 3094 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
3095 | } |
3096 | } | |
3097 | tp->cur_tx = tp->dirty_tx = 0; | |
3098 | } | |
3099 | ||
c4028958 | 3100 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
3101 | { |
3102 | struct rtl8169_private *tp = netdev_priv(dev); | |
3103 | ||
c4028958 | 3104 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
3105 | schedule_delayed_work(&tp->task, 4); |
3106 | } | |
3107 | ||
3108 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
3109 | { | |
3110 | struct rtl8169_private *tp = netdev_priv(dev); | |
3111 | void __iomem *ioaddr = tp->mmio_addr; | |
3112 | ||
3113 | synchronize_irq(dev->irq); | |
3114 | ||
3115 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 3116 | napi_disable(&tp->napi); |
1da177e4 LT |
3117 | |
3118 | rtl8169_irq_mask_and_ack(ioaddr); | |
3119 | ||
d1d08d12 DM |
3120 | tp->intr_mask = 0xffff; |
3121 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 3122 | napi_enable(&tp->napi); |
1da177e4 LT |
3123 | } |
3124 | ||
c4028958 | 3125 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 3126 | { |
c4028958 DH |
3127 | struct rtl8169_private *tp = |
3128 | container_of(work, struct rtl8169_private, task.work); | |
3129 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
3130 | int ret; |
3131 | ||
eb2a021c FR |
3132 | rtnl_lock(); |
3133 | ||
3134 | if (!netif_running(dev)) | |
3135 | goto out_unlock; | |
3136 | ||
3137 | rtl8169_wait_for_quiescence(dev); | |
3138 | rtl8169_close(dev); | |
1da177e4 LT |
3139 | |
3140 | ret = rtl8169_open(dev); | |
3141 | if (unlikely(ret < 0)) { | |
07d3f51f | 3142 | if (net_ratelimit() && netif_msg_drv(tp)) { |
53edbecd | 3143 | printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
07d3f51f | 3144 | " Rescheduling.\n", dev->name, ret); |
1da177e4 LT |
3145 | } |
3146 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
3147 | } | |
eb2a021c FR |
3148 | |
3149 | out_unlock: | |
3150 | rtnl_unlock(); | |
1da177e4 LT |
3151 | } |
3152 | ||
c4028958 | 3153 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 3154 | { |
c4028958 DH |
3155 | struct rtl8169_private *tp = |
3156 | container_of(work, struct rtl8169_private, task.work); | |
3157 | struct net_device *dev = tp->dev; | |
1da177e4 | 3158 | |
eb2a021c FR |
3159 | rtnl_lock(); |
3160 | ||
1da177e4 | 3161 | if (!netif_running(dev)) |
eb2a021c | 3162 | goto out_unlock; |
1da177e4 LT |
3163 | |
3164 | rtl8169_wait_for_quiescence(dev); | |
3165 | ||
bea3348e | 3166 | rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
1da177e4 LT |
3167 | rtl8169_tx_clear(tp); |
3168 | ||
3169 | if (tp->dirty_rx == tp->cur_rx) { | |
3170 | rtl8169_init_ring_indexes(tp); | |
07ce4064 | 3171 | rtl_hw_start(dev); |
1da177e4 | 3172 | netif_wake_queue(dev); |
cebf8cc7 | 3173 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
1da177e4 | 3174 | } else { |
07d3f51f | 3175 | if (net_ratelimit() && netif_msg_intr(tp)) { |
53edbecd | 3176 | printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
07d3f51f | 3177 | dev->name); |
1da177e4 LT |
3178 | } |
3179 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
3180 | } | |
eb2a021c FR |
3181 | |
3182 | out_unlock: | |
3183 | rtnl_unlock(); | |
1da177e4 LT |
3184 | } |
3185 | ||
3186 | static void rtl8169_tx_timeout(struct net_device *dev) | |
3187 | { | |
3188 | struct rtl8169_private *tp = netdev_priv(dev); | |
3189 | ||
3190 | rtl8169_hw_reset(tp->mmio_addr); | |
3191 | ||
3192 | /* Let's wait a bit while any (async) irq lands on */ | |
3193 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
3194 | } | |
3195 | ||
3196 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
3197 | u32 opts1) | |
3198 | { | |
3199 | struct skb_shared_info *info = skb_shinfo(skb); | |
3200 | unsigned int cur_frag, entry; | |
a6343afb | 3201 | struct TxDesc * uninitialized_var(txd); |
1da177e4 LT |
3202 | |
3203 | entry = tp->cur_tx; | |
3204 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
3205 | skb_frag_t *frag = info->frags + cur_frag; | |
3206 | dma_addr_t mapping; | |
3207 | u32 status, len; | |
3208 | void *addr; | |
3209 | ||
3210 | entry = (entry + 1) % NUM_TX_DESC; | |
3211 | ||
3212 | txd = tp->TxDescArray + entry; | |
3213 | len = frag->size; | |
3214 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
3215 | mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); | |
3216 | ||
3217 | /* anti gcc 2.95.3 bugware (sic) */ | |
3218 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
3219 | ||
3220 | txd->opts1 = cpu_to_le32(status); | |
3221 | txd->addr = cpu_to_le64(mapping); | |
3222 | ||
3223 | tp->tx_skb[entry].len = len; | |
3224 | } | |
3225 | ||
3226 | if (cur_frag) { | |
3227 | tp->tx_skb[entry].skb = skb; | |
3228 | txd->opts1 |= cpu_to_le32(LastFrag); | |
3229 | } | |
3230 | ||
3231 | return cur_frag; | |
3232 | } | |
3233 | ||
3234 | static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) | |
3235 | { | |
3236 | if (dev->features & NETIF_F_TSO) { | |
7967168c | 3237 | u32 mss = skb_shinfo(skb)->gso_size; |
1da177e4 LT |
3238 | |
3239 | if (mss) | |
3240 | return LargeSend | ((mss & MSSMask) << MSSShift); | |
3241 | } | |
84fa7933 | 3242 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 3243 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
3244 | |
3245 | if (ip->protocol == IPPROTO_TCP) | |
3246 | return IPCS | TCPCS; | |
3247 | else if (ip->protocol == IPPROTO_UDP) | |
3248 | return IPCS | UDPCS; | |
3249 | WARN_ON(1); /* we need a WARN() */ | |
3250 | } | |
3251 | return 0; | |
3252 | } | |
3253 | ||
3254 | static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
3255 | { | |
3256 | struct rtl8169_private *tp = netdev_priv(dev); | |
3257 | unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; | |
3258 | struct TxDesc *txd = tp->TxDescArray + entry; | |
3259 | void __iomem *ioaddr = tp->mmio_addr; | |
3260 | dma_addr_t mapping; | |
3261 | u32 status, len; | |
3262 | u32 opts1; | |
188f4af0 | 3263 | int ret = NETDEV_TX_OK; |
5b0384f4 | 3264 | |
1da177e4 | 3265 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
b57b7e5a SH |
3266 | if (netif_msg_drv(tp)) { |
3267 | printk(KERN_ERR | |
3268 | "%s: BUG! Tx Ring full when queue awake!\n", | |
3269 | dev->name); | |
3270 | } | |
1da177e4 LT |
3271 | goto err_stop; |
3272 | } | |
3273 | ||
3274 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3275 | goto err_stop; | |
3276 | ||
3277 | opts1 = DescOwn | rtl8169_tso_csum(skb, dev); | |
3278 | ||
3279 | frags = rtl8169_xmit_frags(tp, skb, opts1); | |
3280 | if (frags) { | |
3281 | len = skb_headlen(skb); | |
3282 | opts1 |= FirstFrag; | |
3283 | } else { | |
3284 | len = skb->len; | |
3285 | ||
3286 | if (unlikely(len < ETH_ZLEN)) { | |
5b057c6b | 3287 | if (skb_padto(skb, ETH_ZLEN)) |
1da177e4 LT |
3288 | goto err_update_stats; |
3289 | len = ETH_ZLEN; | |
3290 | } | |
3291 | ||
3292 | opts1 |= FirstFrag | LastFrag; | |
3293 | tp->tx_skb[entry].skb = skb; | |
3294 | } | |
3295 | ||
3296 | mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); | |
3297 | ||
3298 | tp->tx_skb[entry].len = len; | |
3299 | txd->addr = cpu_to_le64(mapping); | |
3300 | txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); | |
3301 | ||
3302 | wmb(); | |
3303 | ||
3304 | /* anti gcc 2.95.3 bugware (sic) */ | |
3305 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
3306 | txd->opts1 = cpu_to_le32(status); | |
3307 | ||
3308 | dev->trans_start = jiffies; | |
3309 | ||
3310 | tp->cur_tx += frags + 1; | |
3311 | ||
3312 | smp_wmb(); | |
3313 | ||
275391a4 | 3314 | RTL_W8(TxPoll, NPQ); /* set polling bit */ |
1da177e4 LT |
3315 | |
3316 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
3317 | netif_stop_queue(dev); | |
3318 | smp_rmb(); | |
3319 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
3320 | netif_wake_queue(dev); | |
3321 | } | |
3322 | ||
3323 | out: | |
3324 | return ret; | |
3325 | ||
3326 | err_stop: | |
3327 | netif_stop_queue(dev); | |
188f4af0 | 3328 | ret = NETDEV_TX_BUSY; |
1da177e4 | 3329 | err_update_stats: |
cebf8cc7 | 3330 | dev->stats.tx_dropped++; |
1da177e4 LT |
3331 | goto out; |
3332 | } | |
3333 | ||
3334 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
3335 | { | |
3336 | struct rtl8169_private *tp = netdev_priv(dev); | |
3337 | struct pci_dev *pdev = tp->pci_dev; | |
3338 | void __iomem *ioaddr = tp->mmio_addr; | |
3339 | u16 pci_status, pci_cmd; | |
3340 | ||
3341 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
3342 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
3343 | ||
b57b7e5a SH |
3344 | if (netif_msg_intr(tp)) { |
3345 | printk(KERN_ERR | |
3346 | "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", | |
3347 | dev->name, pci_cmd, pci_status); | |
3348 | } | |
1da177e4 LT |
3349 | |
3350 | /* | |
3351 | * The recovery sequence below admits a very elaborated explanation: | |
3352 | * - it seems to work; | |
d03902b8 FR |
3353 | * - I did not see what else could be done; |
3354 | * - it makes iop3xx happy. | |
1da177e4 LT |
3355 | * |
3356 | * Feel free to adjust to your needs. | |
3357 | */ | |
a27993f3 | 3358 | if (pdev->broken_parity_status) |
d03902b8 FR |
3359 | pci_cmd &= ~PCI_COMMAND_PARITY; |
3360 | else | |
3361 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
3362 | ||
3363 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
3364 | |
3365 | pci_write_config_word(pdev, PCI_STATUS, | |
3366 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
3367 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
3368 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
3369 | ||
3370 | /* The infamous DAC f*ckup only happens at boot time */ | |
3371 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
b57b7e5a SH |
3372 | if (netif_msg_intr(tp)) |
3373 | printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); | |
1da177e4 LT |
3374 | tp->cp_cmd &= ~PCIDAC; |
3375 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
3376 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
3377 | } |
3378 | ||
3379 | rtl8169_hw_reset(ioaddr); | |
d03902b8 FR |
3380 | |
3381 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
3382 | } |
3383 | ||
07d3f51f FR |
3384 | static void rtl8169_tx_interrupt(struct net_device *dev, |
3385 | struct rtl8169_private *tp, | |
3386 | void __iomem *ioaddr) | |
1da177e4 LT |
3387 | { |
3388 | unsigned int dirty_tx, tx_left; | |
3389 | ||
1da177e4 LT |
3390 | dirty_tx = tp->dirty_tx; |
3391 | smp_rmb(); | |
3392 | tx_left = tp->cur_tx - dirty_tx; | |
3393 | ||
3394 | while (tx_left > 0) { | |
3395 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
3396 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
3397 | u32 len = tx_skb->len; | |
3398 | u32 status; | |
3399 | ||
3400 | rmb(); | |
3401 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
3402 | if (status & DescOwn) | |
3403 | break; | |
3404 | ||
cebf8cc7 FR |
3405 | dev->stats.tx_bytes += len; |
3406 | dev->stats.tx_packets++; | |
1da177e4 LT |
3407 | |
3408 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); | |
3409 | ||
3410 | if (status & LastFrag) { | |
3411 | dev_kfree_skb_irq(tx_skb->skb); | |
3412 | tx_skb->skb = NULL; | |
3413 | } | |
3414 | dirty_tx++; | |
3415 | tx_left--; | |
3416 | } | |
3417 | ||
3418 | if (tp->dirty_tx != dirty_tx) { | |
3419 | tp->dirty_tx = dirty_tx; | |
3420 | smp_wmb(); | |
3421 | if (netif_queue_stopped(dev) && | |
3422 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
3423 | netif_wake_queue(dev); | |
3424 | } | |
d78ae2dc FR |
3425 | /* |
3426 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
3427 | * too close. Let's kick an extra TxPoll request when a burst | |
3428 | * of start_xmit activity is detected (if it is not detected, | |
3429 | * it is slow enough). -- FR | |
3430 | */ | |
3431 | smp_rmb(); | |
3432 | if (tp->cur_tx != dirty_tx) | |
3433 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
3434 | } |
3435 | } | |
3436 | ||
126fa4b9 FR |
3437 | static inline int rtl8169_fragmented_frame(u32 status) |
3438 | { | |
3439 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
3440 | } | |
3441 | ||
1da177e4 LT |
3442 | static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
3443 | { | |
3444 | u32 opts1 = le32_to_cpu(desc->opts1); | |
3445 | u32 status = opts1 & RxProtoMask; | |
3446 | ||
3447 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
3448 | ((status == RxProtoUDP) && !(opts1 & UDPFail)) || | |
3449 | ((status == RxProtoIP) && !(opts1 & IPFail))) | |
3450 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3451 | else | |
3452 | skb->ip_summed = CHECKSUM_NONE; | |
3453 | } | |
3454 | ||
07d3f51f FR |
3455 | static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
3456 | struct rtl8169_private *tp, int pkt_size, | |
3457 | dma_addr_t addr) | |
1da177e4 | 3458 | { |
b449655f SH |
3459 | struct sk_buff *skb; |
3460 | bool done = false; | |
1da177e4 | 3461 | |
b449655f SH |
3462 | if (pkt_size >= rx_copybreak) |
3463 | goto out; | |
1da177e4 | 3464 | |
07d3f51f | 3465 | skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
b449655f SH |
3466 | if (!skb) |
3467 | goto out; | |
3468 | ||
07d3f51f FR |
3469 | pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
3470 | PCI_DMA_FROMDEVICE); | |
86402234 | 3471 | skb_reserve(skb, NET_IP_ALIGN); |
b449655f SH |
3472 | skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
3473 | *sk_buff = skb; | |
3474 | done = true; | |
3475 | out: | |
3476 | return done; | |
1da177e4 LT |
3477 | } |
3478 | ||
07d3f51f FR |
3479 | static int rtl8169_rx_interrupt(struct net_device *dev, |
3480 | struct rtl8169_private *tp, | |
bea3348e | 3481 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
3482 | { |
3483 | unsigned int cur_rx, rx_left; | |
3484 | unsigned int delta, count; | |
3485 | ||
1da177e4 LT |
3486 | cur_rx = tp->cur_rx; |
3487 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 3488 | rx_left = min(rx_left, budget); |
1da177e4 | 3489 | |
4dcb7d33 | 3490 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 3491 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 3492 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
3493 | u32 status; |
3494 | ||
3495 | rmb(); | |
126fa4b9 | 3496 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
3497 | |
3498 | if (status & DescOwn) | |
3499 | break; | |
4dcb7d33 | 3500 | if (unlikely(status & RxRES)) { |
b57b7e5a SH |
3501 | if (netif_msg_rx_err(tp)) { |
3502 | printk(KERN_INFO | |
3503 | "%s: Rx ERROR. status = %08x\n", | |
3504 | dev->name, status); | |
3505 | } | |
cebf8cc7 | 3506 | dev->stats.rx_errors++; |
1da177e4 | 3507 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 3508 | dev->stats.rx_length_errors++; |
1da177e4 | 3509 | if (status & RxCRC) |
cebf8cc7 | 3510 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
3511 | if (status & RxFOVF) { |
3512 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 3513 | dev->stats.rx_fifo_errors++; |
9dccf611 | 3514 | } |
126fa4b9 | 3515 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
1da177e4 | 3516 | } else { |
1da177e4 | 3517 | struct sk_buff *skb = tp->Rx_skbuff[entry]; |
b449655f | 3518 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 3519 | int pkt_size = (status & 0x00001FFF) - 4; |
b449655f | 3520 | struct pci_dev *pdev = tp->pci_dev; |
1da177e4 | 3521 | |
126fa4b9 FR |
3522 | /* |
3523 | * The driver does not support incoming fragmented | |
3524 | * frames. They are seen as a symptom of over-mtu | |
3525 | * sized frames. | |
3526 | */ | |
3527 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
3528 | dev->stats.rx_dropped++; |
3529 | dev->stats.rx_length_errors++; | |
126fa4b9 | 3530 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
4dcb7d33 | 3531 | continue; |
126fa4b9 FR |
3532 | } |
3533 | ||
1da177e4 | 3534 | rtl8169_rx_csum(skb, desc); |
bcf0bf90 | 3535 | |
07d3f51f | 3536 | if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
b449655f SH |
3537 | pci_dma_sync_single_for_device(pdev, addr, |
3538 | pkt_size, PCI_DMA_FROMDEVICE); | |
3539 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); | |
3540 | } else { | |
a866bbf6 | 3541 | pci_unmap_single(pdev, addr, tp->rx_buf_sz, |
b449655f | 3542 | PCI_DMA_FROMDEVICE); |
1da177e4 LT |
3543 | tp->Rx_skbuff[entry] = NULL; |
3544 | } | |
3545 | ||
1da177e4 LT |
3546 | skb_put(skb, pkt_size); |
3547 | skb->protocol = eth_type_trans(skb, dev); | |
3548 | ||
3549 | if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) | |
865c652d | 3550 | netif_receive_skb(skb); |
1da177e4 LT |
3551 | |
3552 | dev->last_rx = jiffies; | |
cebf8cc7 FR |
3553 | dev->stats.rx_bytes += pkt_size; |
3554 | dev->stats.rx_packets++; | |
1da177e4 | 3555 | } |
6dccd16b FR |
3556 | |
3557 | /* Work around for AMD plateform. */ | |
95e0918d | 3558 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
3559 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
3560 | desc->opts2 = 0; | |
3561 | cur_rx++; | |
3562 | } | |
1da177e4 LT |
3563 | } |
3564 | ||
3565 | count = cur_rx - tp->cur_rx; | |
3566 | tp->cur_rx = cur_rx; | |
3567 | ||
3568 | delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); | |
b57b7e5a | 3569 | if (!delta && count && netif_msg_intr(tp)) |
1da177e4 LT |
3570 | printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
3571 | tp->dirty_rx += delta; | |
3572 | ||
3573 | /* | |
3574 | * FIXME: until there is periodic timer to try and refill the ring, | |
3575 | * a temporary shortage may definitely kill the Rx process. | |
3576 | * - disable the asic to try and avoid an overflow and kick it again | |
3577 | * after refill ? | |
3578 | * - how do others driver handle this condition (Uh oh...). | |
3579 | */ | |
b57b7e5a | 3580 | if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
1da177e4 LT |
3581 | printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
3582 | ||
3583 | return count; | |
3584 | } | |
3585 | ||
07d3f51f | 3586 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 3587 | { |
07d3f51f | 3588 | struct net_device *dev = dev_instance; |
1da177e4 | 3589 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 3590 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 3591 | int handled = 0; |
865c652d | 3592 | int status; |
1da177e4 | 3593 | |
865c652d | 3594 | status = RTL_R16(IntrStatus); |
1da177e4 | 3595 | |
865c652d FR |
3596 | /* hotplug/major error/no more work/shared irq */ |
3597 | if ((status == 0xffff) || !status) | |
3598 | goto out; | |
1da177e4 | 3599 | |
865c652d | 3600 | handled = 1; |
1da177e4 | 3601 | |
865c652d FR |
3602 | if (unlikely(!netif_running(dev))) { |
3603 | rtl8169_asic_down(ioaddr); | |
3604 | goto out; | |
3605 | } | |
1da177e4 | 3606 | |
865c652d FR |
3607 | status &= tp->intr_mask; |
3608 | RTL_W16(IntrStatus, | |
3609 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
1da177e4 | 3610 | |
865c652d FR |
3611 | if (!(status & tp->intr_event)) |
3612 | goto out; | |
0e485150 | 3613 | |
865c652d FR |
3614 | /* Work around for rx fifo overflow */ |
3615 | if (unlikely(status & RxFIFOOver) && | |
3616 | (tp->mac_version == RTL_GIGA_MAC_VER_11)) { | |
3617 | netif_stop_queue(dev); | |
3618 | rtl8169_tx_timeout(dev); | |
3619 | goto out; | |
3620 | } | |
1da177e4 | 3621 | |
865c652d FR |
3622 | if (unlikely(status & SYSErr)) { |
3623 | rtl8169_pcierr_interrupt(dev); | |
3624 | goto out; | |
3625 | } | |
1da177e4 | 3626 | |
865c652d FR |
3627 | if (status & LinkChg) |
3628 | rtl8169_check_link_status(dev, tp, ioaddr); | |
1da177e4 | 3629 | |
865c652d FR |
3630 | if (status & tp->napi_event) { |
3631 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
3632 | tp->intr_mask = ~tp->napi_event; | |
313b0305 | 3633 | |
bea3348e SH |
3634 | if (likely(netif_rx_schedule_prep(dev, &tp->napi))) |
3635 | __netif_rx_schedule(dev, &tp->napi); | |
865c652d FR |
3636 | else if (netif_msg_intr(tp)) { |
3637 | printk(KERN_INFO "%s: interrupt %04x in poll\n", | |
3638 | dev->name, status); | |
b57b7e5a | 3639 | } |
1da177e4 LT |
3640 | } |
3641 | out: | |
3642 | return IRQ_RETVAL(handled); | |
3643 | } | |
3644 | ||
bea3348e | 3645 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 3646 | { |
bea3348e SH |
3647 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
3648 | struct net_device *dev = tp->dev; | |
1da177e4 | 3649 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 3650 | int work_done; |
1da177e4 | 3651 | |
bea3348e | 3652 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
3653 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
3654 | ||
bea3348e SH |
3655 | if (work_done < budget) { |
3656 | netif_rx_complete(dev, napi); | |
1da177e4 LT |
3657 | tp->intr_mask = 0xffff; |
3658 | /* | |
3659 | * 20040426: the barrier is not strictly required but the | |
3660 | * behavior of the irq handler could be less predictable | |
3661 | * without it. Btw, the lack of flush for the posted pci | |
3662 | * write is safe - FR | |
3663 | */ | |
3664 | smp_wmb(); | |
0e485150 | 3665 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
3666 | } |
3667 | ||
bea3348e | 3668 | return work_done; |
1da177e4 | 3669 | } |
1da177e4 | 3670 | |
523a6094 FR |
3671 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
3672 | { | |
3673 | struct rtl8169_private *tp = netdev_priv(dev); | |
3674 | ||
3675 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
3676 | return; | |
3677 | ||
3678 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
3679 | RTL_W32(RxMissed, 0); | |
3680 | } | |
3681 | ||
1da177e4 LT |
3682 | static void rtl8169_down(struct net_device *dev) |
3683 | { | |
3684 | struct rtl8169_private *tp = netdev_priv(dev); | |
3685 | void __iomem *ioaddr = tp->mmio_addr; | |
733b736c | 3686 | unsigned int intrmask; |
1da177e4 LT |
3687 | |
3688 | rtl8169_delete_timer(dev); | |
3689 | ||
3690 | netif_stop_queue(dev); | |
3691 | ||
93dd79e8 | 3692 | napi_disable(&tp->napi); |
93dd79e8 | 3693 | |
1da177e4 LT |
3694 | core_down: |
3695 | spin_lock_irq(&tp->lock); | |
3696 | ||
3697 | rtl8169_asic_down(ioaddr); | |
3698 | ||
523a6094 | 3699 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
3700 | |
3701 | spin_unlock_irq(&tp->lock); | |
3702 | ||
3703 | synchronize_irq(dev->irq); | |
3704 | ||
1da177e4 | 3705 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 3706 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 LT |
3707 | |
3708 | /* | |
3709 | * And now for the 50k$ question: are IRQ disabled or not ? | |
3710 | * | |
3711 | * Two paths lead here: | |
3712 | * 1) dev->close | |
3713 | * -> netif_running() is available to sync the current code and the | |
3714 | * IRQ handler. See rtl8169_interrupt for details. | |
3715 | * 2) dev->change_mtu | |
3716 | * -> rtl8169_poll can not be issued again and re-enable the | |
3717 | * interruptions. Let's simply issue the IRQ down sequence again. | |
733b736c AP |
3718 | * |
3719 | * No loop if hotpluged or major error (0xffff). | |
1da177e4 | 3720 | */ |
733b736c AP |
3721 | intrmask = RTL_R16(IntrMask); |
3722 | if (intrmask && (intrmask != 0xffff)) | |
1da177e4 LT |
3723 | goto core_down; |
3724 | ||
3725 | rtl8169_tx_clear(tp); | |
3726 | ||
3727 | rtl8169_rx_clear(tp); | |
3728 | } | |
3729 | ||
3730 | static int rtl8169_close(struct net_device *dev) | |
3731 | { | |
3732 | struct rtl8169_private *tp = netdev_priv(dev); | |
3733 | struct pci_dev *pdev = tp->pci_dev; | |
3734 | ||
3735 | rtl8169_down(dev); | |
3736 | ||
3737 | free_irq(dev->irq, dev); | |
3738 | ||
1da177e4 LT |
3739 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3740 | tp->RxPhyAddr); | |
3741 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
3742 | tp->TxPhyAddr); | |
3743 | tp->TxDescArray = NULL; | |
3744 | tp->RxDescArray = NULL; | |
3745 | ||
3746 | return 0; | |
3747 | } | |
3748 | ||
07ce4064 | 3749 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
3750 | { |
3751 | struct rtl8169_private *tp = netdev_priv(dev); | |
3752 | void __iomem *ioaddr = tp->mmio_addr; | |
3753 | unsigned long flags; | |
3754 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 3755 | int rx_mode; |
1da177e4 LT |
3756 | u32 tmp = 0; |
3757 | ||
3758 | if (dev->flags & IFF_PROMISC) { | |
3759 | /* Unconditionally log net taps. */ | |
b57b7e5a SH |
3760 | if (netif_msg_link(tp)) { |
3761 | printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", | |
3762 | dev->name); | |
3763 | } | |
1da177e4 LT |
3764 | rx_mode = |
3765 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
3766 | AcceptAllPhys; | |
3767 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3768 | } else if ((dev->mc_count > multicast_filter_limit) | |
3769 | || (dev->flags & IFF_ALLMULTI)) { | |
3770 | /* Too many to filter perfectly -- accept all multicasts. */ | |
3771 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
3772 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3773 | } else { | |
3774 | struct dev_mc_list *mclist; | |
07d3f51f FR |
3775 | unsigned int i; |
3776 | ||
1da177e4 LT |
3777 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
3778 | mc_filter[1] = mc_filter[0] = 0; | |
3779 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
3780 | i++, mclist = mclist->next) { | |
3781 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
3782 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
3783 | rx_mode |= AcceptMulticast; | |
3784 | } | |
3785 | } | |
3786 | ||
3787 | spin_lock_irqsave(&tp->lock, flags); | |
3788 | ||
3789 | tmp = rtl8169_rx_config | rx_mode | | |
3790 | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
3791 | ||
f887cce8 | 3792 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
3793 | u32 data = mc_filter[0]; |
3794 | ||
3795 | mc_filter[0] = swab32(mc_filter[1]); | |
3796 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
3797 | } |
3798 | ||
1da177e4 LT |
3799 | RTL_W32(MAR0 + 0, mc_filter[0]); |
3800 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
3801 | ||
57a9f236 FR |
3802 | RTL_W32(RxConfig, tmp); |
3803 | ||
1da177e4 LT |
3804 | spin_unlock_irqrestore(&tp->lock, flags); |
3805 | } | |
3806 | ||
3807 | /** | |
3808 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
3809 | * @dev: The Ethernet Device to get statistics for | |
3810 | * | |
3811 | * Get TX/RX statistics for rtl8169 | |
3812 | */ | |
3813 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
3814 | { | |
3815 | struct rtl8169_private *tp = netdev_priv(dev); | |
3816 | void __iomem *ioaddr = tp->mmio_addr; | |
3817 | unsigned long flags; | |
3818 | ||
3819 | if (netif_running(dev)) { | |
3820 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 3821 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
3822 | spin_unlock_irqrestore(&tp->lock, flags); |
3823 | } | |
5b0384f4 | 3824 | |
cebf8cc7 | 3825 | return &dev->stats; |
1da177e4 LT |
3826 | } |
3827 | ||
5d06a99f FR |
3828 | #ifdef CONFIG_PM |
3829 | ||
3830 | static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) | |
3831 | { | |
3832 | struct net_device *dev = pci_get_drvdata(pdev); | |
3833 | struct rtl8169_private *tp = netdev_priv(dev); | |
3834 | void __iomem *ioaddr = tp->mmio_addr; | |
3835 | ||
3836 | if (!netif_running(dev)) | |
1371fa6d | 3837 | goto out_pci_suspend; |
5d06a99f FR |
3838 | |
3839 | netif_device_detach(dev); | |
3840 | netif_stop_queue(dev); | |
3841 | ||
3842 | spin_lock_irq(&tp->lock); | |
3843 | ||
3844 | rtl8169_asic_down(ioaddr); | |
3845 | ||
523a6094 | 3846 | rtl8169_rx_missed(dev, ioaddr); |
5d06a99f FR |
3847 | |
3848 | spin_unlock_irq(&tp->lock); | |
3849 | ||
1371fa6d | 3850 | out_pci_suspend: |
5d06a99f | 3851 | pci_save_state(pdev); |
f23e7fda FR |
3852 | pci_enable_wake(pdev, pci_choose_state(pdev, state), |
3853 | (tp->features & RTL_FEATURE_WOL) ? 1 : 0); | |
5d06a99f | 3854 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
1371fa6d | 3855 | |
5d06a99f FR |
3856 | return 0; |
3857 | } | |
3858 | ||
3859 | static int rtl8169_resume(struct pci_dev *pdev) | |
3860 | { | |
3861 | struct net_device *dev = pci_get_drvdata(pdev); | |
3862 | ||
1371fa6d FR |
3863 | pci_set_power_state(pdev, PCI_D0); |
3864 | pci_restore_state(pdev); | |
3865 | pci_enable_wake(pdev, PCI_D0, 0); | |
3866 | ||
5d06a99f FR |
3867 | if (!netif_running(dev)) |
3868 | goto out; | |
3869 | ||
3870 | netif_device_attach(dev); | |
3871 | ||
5d06a99f FR |
3872 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
3873 | out: | |
3874 | return 0; | |
3875 | } | |
3876 | ||
3877 | #endif /* CONFIG_PM */ | |
3878 | ||
1da177e4 LT |
3879 | static struct pci_driver rtl8169_pci_driver = { |
3880 | .name = MODULENAME, | |
3881 | .id_table = rtl8169_pci_tbl, | |
3882 | .probe = rtl8169_init_one, | |
3883 | .remove = __devexit_p(rtl8169_remove_one), | |
3884 | #ifdef CONFIG_PM | |
3885 | .suspend = rtl8169_suspend, | |
3886 | .resume = rtl8169_resume, | |
3887 | #endif | |
3888 | }; | |
3889 | ||
07d3f51f | 3890 | static int __init rtl8169_init_module(void) |
1da177e4 | 3891 | { |
29917620 | 3892 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
3893 | } |
3894 | ||
07d3f51f | 3895 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
3896 | { |
3897 | pci_unregister_driver(&rtl8169_pci_driver); | |
3898 | } | |
3899 | ||
3900 | module_init(rtl8169_init_module); | |
3901 | module_exit(rtl8169_cleanup_module); |