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net: fix kernel-doc warning in core/filter.c
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
1da177e4
LT		 40#ifdef RTL8169_DEBUG
41#define assert(expr) \
5b0384f4
FR		 42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 44 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 45 }
06fa7358
JP		 46#define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4
LT		 62
63/* MAC address length */
64#define MAC_ADDR_LEN 6
65
9c14ceaf 66#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 67#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 94#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 95
96enum mac_version {
f21b75e9 97 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
1da177e4
LT		 126};
127
1da177e4
LT		 128#define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
3c6bee1d 131static const struct {
1da177e4
LT		 132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135} rtl_chip_info[] = {
ba6eb6ee
FR		 136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
e6de30d6 162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
1da177e4
LT		 164};
165#undef _R
166
bcf0bf90
FR		 167enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171};
172
07ce4064
FR		 173static void rtl_hw_start_8169(struct net_device *);
174static void rtl_hw_start_8168(struct net_device *);
175static void rtl_hw_start_8101(struct net_device *);
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
6f0333b8 195static int rx_buf_sz = 16383;
4300e8c7 196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4 200
07d3f51f
FR		 201enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
773d2021 203 MAC4 = 4,
07d3f51f
FR		 204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
07d3f51f
FR		 229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
f0298f81 235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237#define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241#define TxPacketMax (8064 >> 7)
242
07d3f51f
FR		 243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
1da177e4
LT		 247};
248
f162a5d1
FR		 249enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253};
254
255enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258#define CSIAR_FLAG 0x80000000
259#define CSIAR_WRITE_CMD 0x80000000
260#define CSIAR_BYTE_ENABLE 0x0f
261#define CSIAR_BYTE_ENABLE_SHIFT 12
262#define CSIAR_ADDR_MASK 0x0fff
065c27c1 263 PMCH = 0x6f,
f162a5d1
FR		 264 EPHYAR = 0x80,
265#define EPHYAR_FLAG 0x80000000
266#define EPHYAR_WRITE_CMD 0x80000000
267#define EPHYAR_REG_MASK 0x1f
268#define EPHYAR_REG_SHIFT 16
269#define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271#define FIX_NAK_1 (1 << 4)
272#define FIX_NAK_2 (1 << 3)
daf9df6d 273 EFUSEAR = 0xdc,
274#define EFUSEAR_FLAG 0x80000000
275#define EFUSEAR_WRITE_CMD 0x80000000
276#define EFUSEAR_READ_CMD 0x00000000
277#define EFUSEAR_REG_MASK 0x03ff
278#define EFUSEAR_REG_SHIFT 8
279#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 280};
281
c0e45c1c 282enum rtl8168_registers {
b646d900 283 ERIDR = 0x70,
284 ERIAR = 0x74,
285#define ERIAR_FLAG 0x80000000
286#define ERIAR_WRITE_CMD 0x80000000
287#define ERIAR_READ_CMD 0x00000000
288#define ERIAR_ADDR_BYTE_ALIGN 4
289#define ERIAR_EXGMAC 0
290#define ERIAR_MSIX 1
291#define ERIAR_ASF 2
292#define ERIAR_TYPE_SHIFT 16
293#define ERIAR_BYTEEN 0x0f
294#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297#define OCPDR_WRITE_CMD 0x80000000
298#define OCPDR_READ_CMD 0x00000000
299#define OCPDR_REG_MASK 0x7f
300#define OCPDR_GPHY_REG_SHIFT 16
301#define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303#define OCPAR_FLAG 0x80000000
304#define OCPAR_GPHY_WRITE_CMD 0x8000f060
305#define OCPAR_GPHY_READ_CMD 0x0000f060
e6de30d6 306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
c0e45c1c 307};
308
07d3f51f 309enum rtl_register_content {
1da177e4 310 /* InterruptStatusBits */
07d3f51f
FR		 311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
1da177e4
LT		 322
323 /* RxStatusDesc */
9dccf611
FR		 324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
1da177e4
LT		 329
330 /* ChipCmdBits */
07d3f51f
FR		 331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
1da177e4 335
275391a4
FR		 336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
1da177e4 341 /* Cfg9346Bits */
07d3f51f
FR		 342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 344
345 /* rx_mode_bits */
07d3f51f
FR		 346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
1da177e4
LT		 352
353 /* RxConfigBits */
07d3f51f
FR		 354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
1da177e4
LT		 356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
5d06a99f 361 /* Config1 register p.24 */
f162a5d1
FR		 362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
fbac58fc 364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
5d06a99f
FR		 369 PMEnable = (1 << 0), /* Power Management Enable */
370
6dccd16b
FR		 371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
61a4dcc2
FR		 375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 379
5d06a99f 380 /* Config5 register p.27 */
61a4dcc2
FR		 381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
1da177e4
LT		 387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
f162a5d1
FR		 396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
0e485150
FR		 410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
1da177e4
LT		 414
415 /* rtl8169_PHYstatus */
07d3f51f
FR		 416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
1da177e4 424
1da177e4 425 /* _TBICSRBit */
07d3f51f 426 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 427
428 /* DumpCounterCommand */
07d3f51f 429 CounterDump = 0x8,
1da177e4
LT		 430};
431
07d3f51f 432enum desc_status_bit {
1da177e4
LT		 433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451#define RxProtoUDP (PID1)
452#define RxProtoTCP (PID0)
453#define RxProtoIP (PID1 | PID0)
454#define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460};
461
462#define RsvdMask 0x3fffc000
463
464struct TxDesc {
6cccd6e7
REB		 465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
1da177e4
LT		 468};
469
470struct RxDesc {
6cccd6e7
REB		 471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
1da177e4
LT		 474};
475
476struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480};
481
f23e7fda 482enum features {
ccdffb9a
FR		 483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 486};
487
355423d0
IV		 488struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502};
503
1da177e4
LT		 504struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 507 struct net_device *dev;
bea3348e 508 struct napi_struct napi;
1da177e4 509 spinlock_t lock; /* spin lock flag */
b57b7e5a 510 u32 msg_enable;
1da177e4
LT		 511 int chipset;
512 int mac_version;
1da177e4
LT		 513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
6f0333b8 521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 523 struct timer_list timer;
524 u16 cp_cmd;
0e485150
FR		 525 u16 intr_event;
526 u16 napi_event;
1da177e4 527 u16 intr_mask;
1da177e4
LT		 528 int phy_1000_ctrl_reg;
529#ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531#endif
c0e45c1c 532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
065c27c1 538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
1da177e4 543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 545 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 546 void (*hw_start)(struct net_device *);
4da19633 547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 548 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 550 int pcie_cap;
c4028958 551 struct delayed_work task;
f23e7fda 552 unsigned features;
ccdffb9a
FR		 553
554 struct mii_if_info mii;
355423d0 555 struct rtl8169_counters counters;
e1759441 556 u32 saved_wolopts;
1da177e4
LT		 557};
558
979b6c13 559MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 560MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 561module_param(use_dac, int, 0);
4300e8c7 562MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 563module_param_named(debug, debug.msg_enable, int, 0);
564MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 565MODULE_LICENSE("GPL");
566MODULE_VERSION(RTL8169_VERSION);
bca03d5f 567MODULE_FIRMWARE(FIRMWARE_8168D_1);
568MODULE_FIRMWARE(FIRMWARE_8168D_2);
1da177e4
LT		 569
570static int rtl8169_open(struct net_device *dev);
61357325
SH		 571static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
572 struct net_device *dev);
7d12e780 573static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 574static int rtl8169_init_ring(struct net_device *dev);
07ce4064 575static void rtl_hw_start(struct net_device *dev);
1da177e4 576static int rtl8169_close(struct net_device *dev);
07ce4064 577static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 578static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 579static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 580static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 581 void __iomem *, u32 budget);
4dcb7d33 582static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 583static void rtl8169_down(struct net_device *dev);
99f252b0 584static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 585static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 586
1da177e4 587static const unsigned int rtl8169_rx_config =
5b0384f4 588 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 589
b646d900 590static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
591{
592 void __iomem *ioaddr = tp->mmio_addr;
593 int i;
594
595 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
596 for (i = 0; i < 20; i++) {
597 udelay(100);
598 if (RTL_R32(OCPAR) & OCPAR_FLAG)
599 break;
600 }
601 return RTL_R32(OCPDR);
602}
603
604static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
605{
606 void __iomem *ioaddr = tp->mmio_addr;
607 int i;
608
609 RTL_W32(OCPDR, data);
610 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
611 for (i = 0; i < 20; i++) {
612 udelay(100);
613 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
614 break;
615 }
616}
617
618static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
619{
620 int i;
621
622 RTL_W8(ERIDR, cmd);
623 RTL_W32(ERIAR, 0x800010e8);
624 msleep(2);
625 for (i = 0; i < 5; i++) {
626 udelay(100);
627 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
628 break;
629 }
630
631 ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
632}
633
634#define OOB_CMD_RESET 0x00
635#define OOB_CMD_DRIVER_START 0x05
636#define OOB_CMD_DRIVER_STOP 0x06
637
638static void rtl8168_driver_start(struct rtl8169_private *tp)
639{
640 int i;
641
642 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
643
644 for (i = 0; i < 10; i++) {
645 msleep(10);
646 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
647 break;
648 }
649}
650
651static void rtl8168_driver_stop(struct rtl8169_private *tp)
652{
653 int i;
654
655 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
656
657 for (i = 0; i < 10; i++) {
658 msleep(10);
659 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
660 break;
661 }
662}
663
664
4da19633 665static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 666{
667 int i;
668
a6baf3af 669 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 670
2371408c 671 for (i = 20; i > 0; i--) {
07d3f51f
FR		 672 /*
673 * Check if the RTL8169 has completed writing to the specified
674 * MII register.
675 */
5b0384f4 676 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 677 break;
2371408c 678 udelay(25);
1da177e4 679 }
024a07ba 680 /*
81a95f04
TT		 681 * According to hardware specs a 20us delay is required after write
682 * complete indication, but before sending next command.
024a07ba 683 */
81a95f04 684 udelay(20);
1da177e4
LT		 685}
686
4da19633 687static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 688{
689 int i, value = -1;
690
a6baf3af 691 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 692
2371408c 693 for (i = 20; i > 0; i--) {
07d3f51f
FR		 694 /*
695 * Check if the RTL8169 has completed retrieving data from
696 * the specified MII register.
697 */
1da177e4 698 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 699 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 700 break;
701 }
2371408c 702 udelay(25);
1da177e4 703 }
81a95f04
TT		 704 /*
705 * According to hardware specs a 20us delay is required after read
706 * complete indication, but before sending next command.
707 */
708 udelay(20);
709
1da177e4
LT		 710 return value;
711}
712
c0e45c1c 713static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
714{
715 int i;
716
717 RTL_W32(OCPDR, data |
718 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
719 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
720 RTL_W32(EPHY_RXER_NUM, 0);
721
722 for (i = 0; i < 100; i++) {
723 mdelay(1);
724 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
725 break;
726 }
727}
728
729static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
730{
731 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
732 (value & OCPDR_DATA_MASK));
733}
734
735static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
736{
737 int i;
738
739 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
740
741 mdelay(1);
742 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
743 RTL_W32(EPHY_RXER_NUM, 0);
744
745 for (i = 0; i < 100; i++) {
746 mdelay(1);
747 if (RTL_R32(OCPAR) & OCPAR_FLAG)
748 break;
749 }
750
751 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
752}
753
e6de30d6 754#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
755
756static void r8168dp_2_mdio_start(void __iomem *ioaddr)
757{
758 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
759}
760
761static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
762{
763 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
764}
765
766static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
767{
768 r8168dp_2_mdio_start(ioaddr);
769
770 r8169_mdio_write(ioaddr, reg_addr, value);
771
772 r8168dp_2_mdio_stop(ioaddr);
773}
774
775static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
776{
777 int value;
778
779 r8168dp_2_mdio_start(ioaddr);
780
781 value = r8169_mdio_read(ioaddr, reg_addr);
782
783 r8168dp_2_mdio_stop(ioaddr);
784
785 return value;
786}
787
4da19633 788static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 789{
c0e45c1c 790 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 791}
792
4da19633 793static int rtl_readphy(struct rtl8169_private *tp, int location)
794{
c0e45c1c 795 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 796}
797
798static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
799{
800 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
801}
802
803static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 804{
805 int val;
806
4da19633 807 val = rtl_readphy(tp, reg_addr);
808 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 809}
810
ccdffb9a
FR		 811static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
812 int val)
813{
814 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 815
4da19633 816 rtl_writephy(tp, location, val);
ccdffb9a
FR		 817}
818
819static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
820{
821 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 822
4da19633 823 return rtl_readphy(tp, location);
ccdffb9a
FR		 824}
825
dacf8154
FR		 826static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
827{
828 unsigned int i;
829
830 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
831 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
832
833 for (i = 0; i < 100; i++) {
834 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
835 break;
836 udelay(10);
837 }
838}
839
840static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
841{
842 u16 value = 0xffff;
843 unsigned int i;
844
845 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
846
847 for (i = 0; i < 100; i++) {
848 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
849 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
850 break;
851 }
852 udelay(10);
853 }
854
855 return value;
856}
857
858static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
859{
860 unsigned int i;
861
862 RTL_W32(CSIDR, value);
863 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
864 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
865
866 for (i = 0; i < 100; i++) {
867 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
868 break;
869 udelay(10);
870 }
871}
872
873static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
874{
875 u32 value = ~0x00;
876 unsigned int i;
877
878 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
879 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
880
881 for (i = 0; i < 100; i++) {
882 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
883 value = RTL_R32(CSIDR);
884 break;
885 }
886 udelay(10);
887 }
888
889 return value;
890}
891
daf9df6d 892static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
893{
894 u8 value = 0xff;
895 unsigned int i;
896
897 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
898
899 for (i = 0; i < 300; i++) {
900 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
901 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
902 break;
903 }
904 udelay(100);
905 }
906
907 return value;
908}
909
1da177e4
LT		 910static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
911{
912 RTL_W16(IntrMask, 0x0000);
913
914 RTL_W16(IntrStatus, 0xffff);
915}
916
917static void rtl8169_asic_down(void __iomem *ioaddr)
918{
919 RTL_W8(ChipCmd, 0x00);
920 rtl8169_irq_mask_and_ack(ioaddr);
921 RTL_R16(CPlusCmd);
922}
923
4da19633 924static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 925{
4da19633 926 void __iomem *ioaddr = tp->mmio_addr;
927
1da177e4
LT		 928 return RTL_R32(TBICSR) & TBIReset;
929}
930
4da19633 931static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 932{
4da19633 933 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 934}
935
936static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
937{
938 return RTL_R32(TBICSR) & TBILinkOk;
939}
940
941static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
942{
943 return RTL_R8(PHYstatus) & LinkStatus;
944}
945
4da19633 946static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 947{
4da19633 948 void __iomem *ioaddr = tp->mmio_addr;
949
1da177e4
LT		 950 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
951}
952
4da19633 953static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 954{
955 unsigned int val;
956
4da19633 957 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
958 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 959}
960
e4fbce74 961static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 962 struct rtl8169_private *tp,
e4fbce74
RW		 963 void __iomem *ioaddr,
964 bool pm)
1da177e4
LT		 965{
966 unsigned long flags;
967
968 spin_lock_irqsave(&tp->lock, flags);
969 if (tp->link_ok(ioaddr)) {
e1759441 970 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 971 if (pm)
972 pm_request_resume(&tp->pci_dev->dev);
1da177e4 973 netif_carrier_on(dev);
bf82c189 974 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 975 } else {
1da177e4 976 netif_carrier_off(dev);
bf82c189 977 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 978 if (pm)
979 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 980 }
1da177e4
LT		 981 spin_unlock_irqrestore(&tp->lock, flags);
982}
983
e4fbce74
RW		 984static void rtl8169_check_link_status(struct net_device *dev,
985 struct rtl8169_private *tp,
986 void __iomem *ioaddr)
987{
988 __rtl8169_check_link_status(dev, tp, ioaddr, false);
989}
990
e1759441
RW		 991#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
992
993static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 994{
61a4dcc2
FR		 995 void __iomem *ioaddr = tp->mmio_addr;
996 u8 options;
e1759441 997 u32 wolopts = 0;
61a4dcc2
FR		 998
999 options = RTL_R8(Config1);
1000 if (!(options & PMEnable))
e1759441 1001 return 0;
61a4dcc2
FR		 1002
1003 options = RTL_R8(Config3);
1004 if (options & LinkUp)
e1759441 1005 wolopts |= WAKE_PHY;
61a4dcc2 1006 if (options & MagicPacket)
e1759441 1007 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1008
1009 options = RTL_R8(Config5);
1010 if (options & UWF)
e1759441 1011 wolopts |= WAKE_UCAST;
61a4dcc2 1012 if (options & BWF)
e1759441 1013 wolopts |= WAKE_BCAST;
61a4dcc2 1014 if (options & MWF)
e1759441 1015 wolopts |= WAKE_MCAST;
61a4dcc2 1016
e1759441 1017 return wolopts;
61a4dcc2
FR		 1018}
1019
e1759441 1020static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1021{
1022 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1023
1024 spin_lock_irq(&tp->lock);
1025
1026 wol->supported = WAKE_ANY;
1027 wol->wolopts = __rtl8169_get_wol(tp);
1028
1029 spin_unlock_irq(&tp->lock);
1030}
1031
1032static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1033{
61a4dcc2 1034 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1035 unsigned int i;
350f7596 1036 static const struct {
61a4dcc2
FR		 1037 u32 opt;
1038 u16 reg;
1039 u8 mask;
1040 } cfg[] = {
1041 { WAKE_ANY, Config1, PMEnable },
1042 { WAKE_PHY, Config3, LinkUp },
1043 { WAKE_MAGIC, Config3, MagicPacket },
1044 { WAKE_UCAST, Config5, UWF },
1045 { WAKE_BCAST, Config5, BWF },
1046 { WAKE_MCAST, Config5, MWF },
1047 { WAKE_ANY, Config5, LanWake }
1048 };
1049
61a4dcc2
FR		 1050 RTL_W8(Cfg9346, Cfg9346_Unlock);
1051
1052 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1053 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1054 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1055 options |= cfg[i].mask;
1056 RTL_W8(cfg[i].reg, options);
1057 }
1058
1059 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1060}
1061
1062static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1063{
1064 struct rtl8169_private *tp = netdev_priv(dev);
1065
1066 spin_lock_irq(&tp->lock);
61a4dcc2 1067
f23e7fda
FR		 1068 if (wol->wolopts)
1069 tp->features |= RTL_FEATURE_WOL;
1070 else
1071 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1072 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1073 spin_unlock_irq(&tp->lock);
1074
ea80907f 1075 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1076
61a4dcc2
FR		 1077 return 0;
1078}
1079
1da177e4
LT		 1080static void rtl8169_get_drvinfo(struct net_device *dev,
1081 struct ethtool_drvinfo *info)
1082{
1083 struct rtl8169_private *tp = netdev_priv(dev);
1084
1085 strcpy(info->driver, MODULENAME);
1086 strcpy(info->version, RTL8169_VERSION);
1087 strcpy(info->bus_info, pci_name(tp->pci_dev));
1088}
1089
1090static int rtl8169_get_regs_len(struct net_device *dev)
1091{
1092 return R8169_REGS_SIZE;
1093}
1094
1095static int rtl8169_set_speed_tbi(struct net_device *dev,
1096 u8 autoneg, u16 speed, u8 duplex)
1097{
1098 struct rtl8169_private *tp = netdev_priv(dev);
1099 void __iomem *ioaddr = tp->mmio_addr;
1100 int ret = 0;
1101 u32 reg;
1102
1103 reg = RTL_R32(TBICSR);
1104 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1105 (duplex == DUPLEX_FULL)) {
1106 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1107 } else if (autoneg == AUTONEG_ENABLE)
1108 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1109 else {
bf82c189
JP		 1110 netif_warn(tp, link, dev,
1111 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1112 ret = -EOPNOTSUPP;
1113 }
1114
1115 return ret;
1116}
1117
1118static int rtl8169_set_speed_xmii(struct net_device *dev,
1119 u8 autoneg, u16 speed, u8 duplex)
1120{
1121 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1122 int giga_ctrl, bmcr;
1da177e4
LT		 1123
1124 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1125 int auto_nego;
1126
4da19633 1127 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
64e4bfb4
FR		 1128 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1129 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 1130 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1131
4da19633 1132 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1133 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1134
3577aa1b 1135 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1136 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1137 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1138 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1139 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1140 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1144 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 1145 } else {
1146 netif_info(tp, link, dev,
1147 "PHY does not support 1000Mbps\n");
bcf0bf90 1148 }
1da177e4 1149
3577aa1b 1150 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1151
1152 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1153 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1154 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1155 /*
1156 * Wake up the PHY.
1157 * Vendor specific (0x1f) and reserved (0x0e) MII
1158 * registers.
1159 */
4da19633 1160 rtl_writephy(tp, 0x1f, 0x0000);
1161 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1162 }
1163
4da19633 1164 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1165 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1166 } else {
1167 giga_ctrl = 0;
1168
1169 if (speed == SPEED_10)
1170 bmcr = 0;
1171 else if (speed == SPEED_100)
1172 bmcr = BMCR_SPEED100;
1173 else
1174 return -EINVAL;
1175
1176 if (duplex == DUPLEX_FULL)
1177 bmcr |= BMCR_FULLDPLX;
623a1593 1178
4da19633 1179 rtl_writephy(tp, 0x1f, 0x0000);
2584fbc3
RS		 1180 }
1181
1da177e4
LT		 1182 tp->phy_1000_ctrl_reg = giga_ctrl;
1183
4da19633 1184 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1185
1186 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1187 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1188 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1189 rtl_writephy(tp, 0x17, 0x2138);
1190 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1191 } else {
4da19633 1192 rtl_writephy(tp, 0x17, 0x2108);
1193 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1194 }
1195 }
1196
1da177e4
LT		 1197 return 0;
1198}
1199
1200static int rtl8169_set_speed(struct net_device *dev,
1201 u8 autoneg, u16 speed, u8 duplex)
1202{
1203 struct rtl8169_private *tp = netdev_priv(dev);
1204 int ret;
1205
1206 ret = tp->set_speed(dev, autoneg, speed, duplex);
1207
64e4bfb4 1208 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1209 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1210
1211 return ret;
1212}
1213
1214static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
1217 unsigned long flags;
1218 int ret;
1219
1220 spin_lock_irqsave(&tp->lock, flags);
1221 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1222 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1223
1da177e4
LT		 1224 return ret;
1225}
1226
1227static u32 rtl8169_get_rx_csum(struct net_device *dev)
1228{
1229 struct rtl8169_private *tp = netdev_priv(dev);
1230
1231 return tp->cp_cmd & RxChkSum;
1232}
1233
1234static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1235{
1236 struct rtl8169_private *tp = netdev_priv(dev);
1237 void __iomem *ioaddr = tp->mmio_addr;
1238 unsigned long flags;
1239
1240 spin_lock_irqsave(&tp->lock, flags);
1241
1242 if (data)
1243 tp->cp_cmd |= RxChkSum;
1244 else
1245 tp->cp_cmd &= ~RxChkSum;
1246
1247 RTL_W16(CPlusCmd, tp->cp_cmd);
1248 RTL_R16(CPlusCmd);
1249
1250 spin_unlock_irqrestore(&tp->lock, flags);
1251
1252 return 0;
1253}
1254
1255#ifdef CONFIG_R8169_VLAN
1256
1257static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1258 struct sk_buff *skb)
1259{
eab6d18d 1260 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1261 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1262}
1263
1264static void rtl8169_vlan_rx_register(struct net_device *dev,
1265 struct vlan_group *grp)
1266{
1267 struct rtl8169_private *tp = netdev_priv(dev);
1268 void __iomem *ioaddr = tp->mmio_addr;
1269 unsigned long flags;
1270
1271 spin_lock_irqsave(&tp->lock, flags);
1272 tp->vlgrp = grp;
05af2142
SW		 1273 /*
1274 * Do not disable RxVlan on 8110SCd.
1275 */
1276 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1277 tp->cp_cmd |= RxVlan;
1278 else
1279 tp->cp_cmd &= ~RxVlan;
1280 RTL_W16(CPlusCmd, tp->cp_cmd);
1281 RTL_R16(CPlusCmd);
1282 spin_unlock_irqrestore(&tp->lock, flags);
1283}
1284
1da177e4 1285static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1286 struct sk_buff *skb, int polling)
1da177e4
LT		 1287{
1288 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1289 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1290 int ret;
1291
865c652d 1292 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1293 u16 vtag = swab16(opts2 & 0xffff);
1294
1295 if (likely(polling))
1296 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1297 else
1298 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1299 ret = 0;
1300 } else
1301 ret = -1;
1302 desc->opts2 = 0;
1303 return ret;
1304}
1305
1306#else /* !CONFIG_R8169_VLAN */
1307
1308static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1309 struct sk_buff *skb)
1310{
1311 return 0;
1312}
1313
1314static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1315 struct sk_buff *skb, int polling)
1da177e4
LT		 1316{
1317 return -1;
1318}
1319
1320#endif
1321
ccdffb9a 1322static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1323{
1324 struct rtl8169_private *tp = netdev_priv(dev);
1325 void __iomem *ioaddr = tp->mmio_addr;
1326 u32 status;
1327
1328 cmd->supported =
1329 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1330 cmd->port = PORT_FIBRE;
1331 cmd->transceiver = XCVR_INTERNAL;
1332
1333 status = RTL_R32(TBICSR);
1334 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1335 cmd->autoneg = !!(status & TBINwEnable);
1336
1337 cmd->speed = SPEED_1000;
1338 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1339
1340 return 0;
1da177e4
LT		 1341}
1342
ccdffb9a 1343static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1344{
1345 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1346
1347 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1348}
1349
1350static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1351{
1352 struct rtl8169_private *tp = netdev_priv(dev);
1353 unsigned long flags;
ccdffb9a 1354 int rc;
1da177e4
LT		 1355
1356 spin_lock_irqsave(&tp->lock, flags);
1357
ccdffb9a 1358 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1359
1360 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1361 return rc;
1da177e4
LT		 1362}
1363
1364static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1365 void *p)
1366{
5b0384f4
FR		 1367 struct rtl8169_private *tp = netdev_priv(dev);
1368 unsigned long flags;
1da177e4 1369
5b0384f4
FR		 1370 if (regs->len > R8169_REGS_SIZE)
1371 regs->len = R8169_REGS_SIZE;
1da177e4 1372
5b0384f4
FR		 1373 spin_lock_irqsave(&tp->lock, flags);
1374 memcpy_fromio(p, tp->mmio_addr, regs->len);
1375 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1376}
1377
b57b7e5a
SH		 1378static u32 rtl8169_get_msglevel(struct net_device *dev)
1379{
1380 struct rtl8169_private *tp = netdev_priv(dev);
1381
1382 return tp->msg_enable;
1383}
1384
1385static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1386{
1387 struct rtl8169_private *tp = netdev_priv(dev);
1388
1389 tp->msg_enable = value;
1390}
1391
d4a3a0fc
SH		 1392static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1393 "tx_packets",
1394 "rx_packets",
1395 "tx_errors",
1396 "rx_errors",
1397 "rx_missed",
1398 "align_errors",
1399 "tx_single_collisions",
1400 "tx_multi_collisions",
1401 "unicast",
1402 "broadcast",
1403 "multicast",
1404 "tx_aborted",
1405 "tx_underrun",
1406};
1407
b9f2c044 1408static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1409{
b9f2c044
JG		 1410 switch (sset) {
1411 case ETH_SS_STATS:
1412 return ARRAY_SIZE(rtl8169_gstrings);
1413 default:
1414 return -EOPNOTSUPP;
1415 }
d4a3a0fc
SH		 1416}
1417
355423d0 1418static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1419{
1420 struct rtl8169_private *tp = netdev_priv(dev);
1421 void __iomem *ioaddr = tp->mmio_addr;
1422 struct rtl8169_counters *counters;
1423 dma_addr_t paddr;
1424 u32 cmd;
355423d0 1425 int wait = 1000;
48addcc9 1426 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1427
355423d0
IV		 1428 /*
1429 * Some chips are unable to dump tally counters when the receiver
1430 * is disabled.
1431 */
1432 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1433 return;
d4a3a0fc 1434
48addcc9 1435 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1436 if (!counters)
1437 return;
1438
1439 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1440 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1441 RTL_W32(CounterAddrLow, cmd);
1442 RTL_W32(CounterAddrLow, cmd | CounterDump);
1443
355423d0
IV		 1444 while (wait--) {
1445 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1446 /* copy updated counters */
1447 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1448 break;
355423d0
IV		 1449 }
1450 udelay(10);
d4a3a0fc
SH		 1451 }
1452
1453 RTL_W32(CounterAddrLow, 0);
1454 RTL_W32(CounterAddrHigh, 0);
1455
48addcc9 1456 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1457}
1458
355423d0
IV		 1459static void rtl8169_get_ethtool_stats(struct net_device *dev,
1460 struct ethtool_stats *stats, u64 *data)
1461{
1462 struct rtl8169_private *tp = netdev_priv(dev);
1463
1464 ASSERT_RTNL();
1465
1466 rtl8169_update_counters(dev);
1467
1468 data[0] = le64_to_cpu(tp->counters.tx_packets);
1469 data[1] = le64_to_cpu(tp->counters.rx_packets);
1470 data[2] = le64_to_cpu(tp->counters.tx_errors);
1471 data[3] = le32_to_cpu(tp->counters.rx_errors);
1472 data[4] = le16_to_cpu(tp->counters.rx_missed);
1473 data[5] = le16_to_cpu(tp->counters.align_errors);
1474 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1475 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1476 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1477 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1478 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1479 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1480 data[12] = le16_to_cpu(tp->counters.tx_underun);
1481}
1482
d4a3a0fc
SH		 1483static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1484{
1485 switch(stringset) {
1486 case ETH_SS_STATS:
1487 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1488 break;
1489 }
1490}
1491
7282d491 1492static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1493 .get_drvinfo = rtl8169_get_drvinfo,
1494 .get_regs_len = rtl8169_get_regs_len,
1495 .get_link = ethtool_op_get_link,
1496 .get_settings = rtl8169_get_settings,
1497 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1498 .get_msglevel = rtl8169_get_msglevel,
1499 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1500 .get_rx_csum = rtl8169_get_rx_csum,
1501 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1502 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1503 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1504 .set_tso = ethtool_op_set_tso,
1505 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1506 .get_wol = rtl8169_get_wol,
1507 .set_wol = rtl8169_set_wol,
d4a3a0fc 1508 .get_strings = rtl8169_get_strings,
b9f2c044 1509 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1510 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1511};
1512
07d3f51f
FR		 1513static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1514 void __iomem *ioaddr)
1da177e4 1515{
0e485150
FR		 1516 /*
1517 * The driver currently handles the 8168Bf and the 8168Be identically
1518 * but they can be identified more specifically through the test below
1519 * if needed:
1520 *
1521 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1522 *
1523 * Same thing for the 8101Eb and the 8101Ec:
1524 *
1525 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1526 */
350f7596 1527 static const struct {
1da177e4 1528 u32 mask;
e3cf0cc0 1529 u32 val;
1da177e4
LT		 1530 int mac_version;
1531 } mac_info[] = {
5b538df9 1532 /* 8168D family. */
daf9df6d 1533 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1534 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1535 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1536
e6de30d6 1537 /* 8168DP family. */
1538 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1539 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1540
ef808d50 1541 /* 8168C family. */
17c99297 1542 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1543 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1544 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1545 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1546 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1547 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1548 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1549 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1550 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1551
1552 /* 8168B family. */
1553 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1554 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1555 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1556 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1557
1558 /* 8101 family. */
2857ffb7
FR		 1559 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1560 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1561 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1562 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1563 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1564 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1565 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1566 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1567 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1568 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1569 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1570 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1571 /* FIXME: where did these entries come from ? -- FR */
1572 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1573 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1574
1575 /* 8110 family. */
1576 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1577 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1578 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1579 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1580 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1581 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1582
f21b75e9
JD		 1583 /* Catch-all */
1584 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1585 }, *p = mac_info;
1586 u32 reg;
1587
e3cf0cc0
FR		 1588 reg = RTL_R32(TxConfig);
1589 while ((reg & p->mask) != p->val)
1da177e4
LT		 1590 p++;
1591 tp->mac_version = p->mac_version;
1592}
1593
1594static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1595{
bcf0bf90 1596 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1597}
1598
867763c1
FR		 1599struct phy_reg {
1600 u16 reg;
1601 u16 val;
1602};
1603
4da19633 1604static void rtl_writephy_batch(struct rtl8169_private *tp,
1605 const struct phy_reg *regs, int len)
867763c1
FR		 1606{
1607 while (len-- > 0) {
4da19633 1608 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1609 regs++;
1610 }
1611}
1612
bca03d5f 1613#define PHY_READ 0x00000000
1614#define PHY_DATA_OR 0x10000000
1615#define PHY_DATA_AND 0x20000000
1616#define PHY_BJMPN 0x30000000
1617#define PHY_READ_EFUSE 0x40000000
1618#define PHY_READ_MAC_BYTE 0x50000000
1619#define PHY_WRITE_MAC_BYTE 0x60000000
1620#define PHY_CLEAR_READCOUNT 0x70000000
1621#define PHY_WRITE 0x80000000
1622#define PHY_READCOUNT_EQ_SKIP 0x90000000
1623#define PHY_COMP_EQ_SKIPN 0xa0000000
1624#define PHY_COMP_NEQ_SKIPN 0xb0000000
1625#define PHY_WRITE_PREVIOUS 0xc0000000
1626#define PHY_SKIPN 0xd0000000
1627#define PHY_DELAY_MS 0xe0000000
1628#define PHY_WRITE_ERI_WORD 0xf0000000
1629
1630static void
1631rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1632{
bca03d5f 1633 __le32 *phytable = (__le32 *)fw->data;
1634 struct net_device *dev = tp->dev;
1635 size_t i;
1636
1637 if (fw->size % sizeof(*phytable)) {
1638 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1639 return;
1640 }
1641
1642 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1643 u32 action = le32_to_cpu(phytable[i]);
1644
1645 if (!action)
1646 break;
1647
1648 if ((action & 0xf0000000) != PHY_WRITE) {
1649 netif_err(tp, probe, dev,
1650 "unknown action 0x%08x\n", action);
1651 return;
1652 }
1653 }
1654
1655 while (i-- != 0) {
1656 u32 action = le32_to_cpu(*phytable);
1657 u32 data = action & 0x0000ffff;
1658 u32 reg = (action & 0x0fff0000) >> 16;
1659
1660 switch(action & 0xf0000000) {
1661 case PHY_WRITE:
4da19633 1662 rtl_writephy(tp, reg, data);
bca03d5f 1663 phytable++;
1664 break;
1665 default:
1666 BUG();
1667 }
1668 }
1669}
1670
4da19633 1671static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1672{
350f7596 1673 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1674 { 0x1f, 0x0001 },
1675 { 0x06, 0x006e },
1676 { 0x08, 0x0708 },
1677 { 0x15, 0x4000 },
1678 { 0x18, 0x65c7 },
1da177e4 1679
0b9b571d 1680 { 0x1f, 0x0001 },
1681 { 0x03, 0x00a1 },
1682 { 0x02, 0x0008 },
1683 { 0x01, 0x0120 },
1684 { 0x00, 0x1000 },
1685 { 0x04, 0x0800 },
1686 { 0x04, 0x0000 },
1da177e4 1687
0b9b571d 1688 { 0x03, 0xff41 },
1689 { 0x02, 0xdf60 },
1690 { 0x01, 0x0140 },
1691 { 0x00, 0x0077 },
1692 { 0x04, 0x7800 },
1693 { 0x04, 0x7000 },
1694
1695 { 0x03, 0x802f },
1696 { 0x02, 0x4f02 },
1697 { 0x01, 0x0409 },
1698 { 0x00, 0xf0f9 },
1699 { 0x04, 0x9800 },
1700 { 0x04, 0x9000 },
1701
1702 { 0x03, 0xdf01 },
1703 { 0x02, 0xdf20 },
1704 { 0x01, 0xff95 },
1705 { 0x00, 0xba00 },
1706 { 0x04, 0xa800 },
1707 { 0x04, 0xa000 },
1708
1709 { 0x03, 0xff41 },
1710 { 0x02, 0xdf20 },
1711 { 0x01, 0x0140 },
1712 { 0x00, 0x00bb },
1713 { 0x04, 0xb800 },
1714 { 0x04, 0xb000 },
1715
1716 { 0x03, 0xdf41 },
1717 { 0x02, 0xdc60 },
1718 { 0x01, 0x6340 },
1719 { 0x00, 0x007d },
1720 { 0x04, 0xd800 },
1721 { 0x04, 0xd000 },
1722
1723 { 0x03, 0xdf01 },
1724 { 0x02, 0xdf20 },
1725 { 0x01, 0x100a },
1726 { 0x00, 0xa0ff },
1727 { 0x04, 0xf800 },
1728 { 0x04, 0xf000 },
1729
1730 { 0x1f, 0x0000 },
1731 { 0x0b, 0x0000 },
1732 { 0x00, 0x9200 }
1733 };
1da177e4 1734
4da19633 1735 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1736}
1737
4da19633 1738static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1739{
350f7596 1740 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1741 { 0x1f, 0x0002 },
1742 { 0x01, 0x90d0 },
1743 { 0x1f, 0x0000 }
1744 };
1745
4da19633 1746 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1747}
1748
4da19633 1749static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1750{
1751 struct pci_dev *pdev = tp->pci_dev;
1752 u16 vendor_id, device_id;
1753
1754 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1755 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1756
1757 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1758 return;
1759
4da19633 1760 rtl_writephy(tp, 0x1f, 0x0001);
1761 rtl_writephy(tp, 0x10, 0xf01b);
1762 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1763}
1764
4da19633 1765static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1766{
350f7596 1767 static const struct phy_reg phy_reg_init[] = {
2e955856 1768 { 0x1f, 0x0001 },
1769 { 0x04, 0x0000 },
1770 { 0x03, 0x00a1 },
1771 { 0x02, 0x0008 },
1772 { 0x01, 0x0120 },
1773 { 0x00, 0x1000 },
1774 { 0x04, 0x0800 },
1775 { 0x04, 0x9000 },
1776 { 0x03, 0x802f },
1777 { 0x02, 0x4f02 },
1778 { 0x01, 0x0409 },
1779 { 0x00, 0xf099 },
1780 { 0x04, 0x9800 },
1781 { 0x04, 0xa000 },
1782 { 0x03, 0xdf01 },
1783 { 0x02, 0xdf20 },
1784 { 0x01, 0xff95 },
1785 { 0x00, 0xba00 },
1786 { 0x04, 0xa800 },
1787 { 0x04, 0xf000 },
1788 { 0x03, 0xdf01 },
1789 { 0x02, 0xdf20 },
1790 { 0x01, 0x101a },
1791 { 0x00, 0xa0ff },
1792 { 0x04, 0xf800 },
1793 { 0x04, 0x0000 },
1794 { 0x1f, 0x0000 },
1795
1796 { 0x1f, 0x0001 },
1797 { 0x10, 0xf41b },
1798 { 0x14, 0xfb54 },
1799 { 0x18, 0xf5c7 },
1800 { 0x1f, 0x0000 },
1801
1802 { 0x1f, 0x0001 },
1803 { 0x17, 0x0cc0 },
1804 { 0x1f, 0x0000 }
1805 };
1806
4da19633 1807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1808
4da19633 1809 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1810}
1811
4da19633 1812static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1813{
350f7596 1814 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1815 { 0x1f, 0x0001 },
1816 { 0x04, 0x0000 },
1817 { 0x03, 0x00a1 },
1818 { 0x02, 0x0008 },
1819 { 0x01, 0x0120 },
1820 { 0x00, 0x1000 },
1821 { 0x04, 0x0800 },
1822 { 0x04, 0x9000 },
1823 { 0x03, 0x802f },
1824 { 0x02, 0x4f02 },
1825 { 0x01, 0x0409 },
1826 { 0x00, 0xf099 },
1827 { 0x04, 0x9800 },
1828 { 0x04, 0xa000 },
1829 { 0x03, 0xdf01 },
1830 { 0x02, 0xdf20 },
1831 { 0x01, 0xff95 },
1832 { 0x00, 0xba00 },
1833 { 0x04, 0xa800 },
1834 { 0x04, 0xf000 },
1835 { 0x03, 0xdf01 },
1836 { 0x02, 0xdf20 },
1837 { 0x01, 0x101a },
1838 { 0x00, 0xa0ff },
1839 { 0x04, 0xf800 },
1840 { 0x04, 0x0000 },
1841 { 0x1f, 0x0000 },
1842
1843 { 0x1f, 0x0001 },
1844 { 0x0b, 0x8480 },
1845 { 0x1f, 0x0000 },
1846
1847 { 0x1f, 0x0001 },
1848 { 0x18, 0x67c7 },
1849 { 0x04, 0x2000 },
1850 { 0x03, 0x002f },
1851 { 0x02, 0x4360 },
1852 { 0x01, 0x0109 },
1853 { 0x00, 0x3022 },
1854 { 0x04, 0x2800 },
1855 { 0x1f, 0x0000 },
1856
1857 { 0x1f, 0x0001 },
1858 { 0x17, 0x0cc0 },
1859 { 0x1f, 0x0000 }
1860 };
1861
4da19633 1862 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 1863}
1864
4da19633 1865static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 1866{
350f7596 1867 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1868 { 0x10, 0xf41b },
1869 { 0x1f, 0x0000 }
1870 };
1871
4da19633 1872 rtl_writephy(tp, 0x1f, 0x0001);
1873 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 1874
4da19633 1875 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1876}
1877
4da19633 1878static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 1879{
350f7596 1880 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1881 { 0x1f, 0x0001 },
1882 { 0x10, 0xf41b },
1883 { 0x1f, 0x0000 }
1884 };
1885
4da19633 1886 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1887}
1888
4da19633 1889static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1890{
350f7596 1891 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1892 { 0x1f, 0x0000 },
1893 { 0x1d, 0x0f00 },
1894 { 0x1f, 0x0002 },
1895 { 0x0c, 0x1ec8 },
1896 { 0x1f, 0x0000 }
1897 };
1898
4da19633 1899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 1900}
1901
4da19633 1902static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 1903{
350f7596 1904 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1905 { 0x1f, 0x0001 },
1906 { 0x1d, 0x3d98 },
1907 { 0x1f, 0x0000 }
1908 };
1909
4da19633 1910 rtl_writephy(tp, 0x1f, 0x0000);
1911 rtl_patchphy(tp, 0x14, 1 << 5);
1912 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 1913
4da19633 1914 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 1915}
1916
4da19633 1917static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1918{
350f7596 1919 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1920 { 0x1f, 0x0001 },
1921 { 0x12, 0x2300 },
867763c1
FR		 1922 { 0x1f, 0x0002 },
1923 { 0x00, 0x88d4 },
1924 { 0x01, 0x82b1 },
1925 { 0x03, 0x7002 },
1926 { 0x08, 0x9e30 },
1927 { 0x09, 0x01f0 },
1928 { 0x0a, 0x5500 },
1929 { 0x0c, 0x00c8 },
1930 { 0x1f, 0x0003 },
1931 { 0x12, 0xc096 },
1932 { 0x16, 0x000a },
f50d4275
FR		 1933 { 0x1f, 0x0000 },
1934 { 0x1f, 0x0000 },
1935 { 0x09, 0x2000 },
1936 { 0x09, 0x0000 }
867763c1
FR		 1937 };
1938
4da19633 1939 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 1940
4da19633 1941 rtl_patchphy(tp, 0x14, 1 << 5);
1942 rtl_patchphy(tp, 0x0d, 1 << 5);
1943 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 1944}
1945
4da19633 1946static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 1947{
350f7596 1948 static const struct phy_reg phy_reg_init[] = {
f50d4275 1949 { 0x1f, 0x0001 },
7da97ec9 1950 { 0x12, 0x2300 },
f50d4275
FR		 1951 { 0x03, 0x802f },
1952 { 0x02, 0x4f02 },
1953 { 0x01, 0x0409 },
1954 { 0x00, 0xf099 },
1955 { 0x04, 0x9800 },
1956 { 0x04, 0x9000 },
1957 { 0x1d, 0x3d98 },
7da97ec9
FR		 1958 { 0x1f, 0x0002 },
1959 { 0x0c, 0x7eb8 },
f50d4275
FR		 1960 { 0x06, 0x0761 },
1961 { 0x1f, 0x0003 },
1962 { 0x16, 0x0f0a },
7da97ec9
FR		 1963 { 0x1f, 0x0000 }
1964 };
1965
4da19633 1966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 1967
4da19633 1968 rtl_patchphy(tp, 0x16, 1 << 0);
1969 rtl_patchphy(tp, 0x14, 1 << 5);
1970 rtl_patchphy(tp, 0x0d, 1 << 5);
1971 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 1972}
1973
4da19633 1974static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 1975{
350f7596 1976 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1977 { 0x1f, 0x0001 },
1978 { 0x12, 0x2300 },
1979 { 0x1d, 0x3d98 },
1980 { 0x1f, 0x0002 },
1981 { 0x0c, 0x7eb8 },
1982 { 0x06, 0x5461 },
1983 { 0x1f, 0x0003 },
1984 { 0x16, 0x0f0a },
1985 { 0x1f, 0x0000 }
1986 };
1987
4da19633 1988 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 1989
4da19633 1990 rtl_patchphy(tp, 0x16, 1 << 0);
1991 rtl_patchphy(tp, 0x14, 1 << 5);
1992 rtl_patchphy(tp, 0x0d, 1 << 5);
1993 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 1994}
1995
4da19633 1996static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 1997{
4da19633 1998 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 1999}
2000
bca03d5f 2001static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2002{
350f7596 2003 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2004 /* Channel Estimation */
5b538df9 2005 { 0x1f, 0x0001 },
daf9df6d 2006 { 0x06, 0x4064 },
2007 { 0x07, 0x2863 },
2008 { 0x08, 0x059c },
2009 { 0x09, 0x26b4 },
2010 { 0x0a, 0x6a19 },
2011 { 0x0b, 0xdcc8 },
2012 { 0x10, 0xf06d },
2013 { 0x14, 0x7f68 },
2014 { 0x18, 0x7fd9 },
2015 { 0x1c, 0xf0ff },
2016 { 0x1d, 0x3d9c },
5b538df9 2017 { 0x1f, 0x0003 },
daf9df6d 2018 { 0x12, 0xf49f },
2019 { 0x13, 0x070b },
2020 { 0x1a, 0x05ad },
bca03d5f 2021 { 0x14, 0x94c0 },
2022
2023 /*
2024 * Tx Error Issue
2025 * enhance line driver power
2026 */
5b538df9 2027 { 0x1f, 0x0002 },
daf9df6d 2028 { 0x06, 0x5561 },
2029 { 0x1f, 0x0005 },
2030 { 0x05, 0x8332 },
bca03d5f 2031 { 0x06, 0x5561 },
2032
2033 /*
2034 * Can not link to 1Gbps with bad cable
2035 * Decrease SNR threshold form 21.07dB to 19.04dB
2036 */
2037 { 0x1f, 0x0001 },
2038 { 0x17, 0x0cc0 },
daf9df6d 2039
5b538df9 2040 { 0x1f, 0x0000 },
bca03d5f 2041 { 0x0d, 0xf880 }
daf9df6d 2042 };
bca03d5f 2043 void __iomem *ioaddr = tp->mmio_addr;
2044 const struct firmware *fw;
daf9df6d 2045
4da19633 2046 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2047
bca03d5f 2048 /*
2049 * Rx Error Issue
2050 * Fine Tune Switching regulator parameter
2051 */
4da19633 2052 rtl_writephy(tp, 0x1f, 0x0002);
2053 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2054 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2055
daf9df6d 2056 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2057 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2058 { 0x1f, 0x0002 },
2059 { 0x05, 0x669a },
2060 { 0x1f, 0x0005 },
2061 { 0x05, 0x8330 },
2062 { 0x06, 0x669a },
2063 { 0x1f, 0x0002 }
2064 };
2065 int val;
2066
4da19633 2067 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2068
4da19633 2069 val = rtl_readphy(tp, 0x0d);
daf9df6d 2070
2071 if ((val & 0x00ff) != 0x006c) {
350f7596 2072 static const u32 set[] = {
daf9df6d 2073 0x0065, 0x0066, 0x0067, 0x0068,
2074 0x0069, 0x006a, 0x006b, 0x006c
2075 };
2076 int i;
2077
4da19633 2078 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2079
2080 val &= 0xff00;
2081 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2082 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2083 }
2084 } else {
350f7596 2085 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2086 { 0x1f, 0x0002 },
2087 { 0x05, 0x6662 },
2088 { 0x1f, 0x0005 },
2089 { 0x05, 0x8330 },
2090 { 0x06, 0x6662 }
2091 };
2092
4da19633 2093 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2094 }
2095
bca03d5f 2096 /* RSET couple improve */
4da19633 2097 rtl_writephy(tp, 0x1f, 0x0002);
2098 rtl_patchphy(tp, 0x0d, 0x0300);
2099 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2100
bca03d5f 2101 /* Fine tune PLL performance */
4da19633 2102 rtl_writephy(tp, 0x1f, 0x0002);
2103 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2104 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2105
4da19633 2106 rtl_writephy(tp, 0x1f, 0x0005);
2107 rtl_writephy(tp, 0x05, 0x001b);
2108 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
bca03d5f 2109 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
2110 rtl_phy_write_fw(tp, fw);
2111 release_firmware(fw);
2112 } else {
2113 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2114 }
2115
4da19633 2116 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2117}
2118
bca03d5f 2119static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2120{
350f7596 2121 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2122 /* Channel Estimation */
daf9df6d 2123 { 0x1f, 0x0001 },
2124 { 0x06, 0x4064 },
2125 { 0x07, 0x2863 },
2126 { 0x08, 0x059c },
2127 { 0x09, 0x26b4 },
2128 { 0x0a, 0x6a19 },
2129 { 0x0b, 0xdcc8 },
2130 { 0x10, 0xf06d },
2131 { 0x14, 0x7f68 },
2132 { 0x18, 0x7fd9 },
2133 { 0x1c, 0xf0ff },
2134 { 0x1d, 0x3d9c },
2135 { 0x1f, 0x0003 },
2136 { 0x12, 0xf49f },
2137 { 0x13, 0x070b },
2138 { 0x1a, 0x05ad },
2139 { 0x14, 0x94c0 },
2140
bca03d5f 2141 /*
2142 * Tx Error Issue
2143 * enhance line driver power
2144 */
daf9df6d 2145 { 0x1f, 0x0002 },
2146 { 0x06, 0x5561 },
2147 { 0x1f, 0x0005 },
2148 { 0x05, 0x8332 },
bca03d5f 2149 { 0x06, 0x5561 },
2150
2151 /*
2152 * Can not link to 1Gbps with bad cable
2153 * Decrease SNR threshold form 21.07dB to 19.04dB
2154 */
2155 { 0x1f, 0x0001 },
2156 { 0x17, 0x0cc0 },
daf9df6d 2157
2158 { 0x1f, 0x0000 },
bca03d5f 2159 { 0x0d, 0xf880 }
5b538df9 2160 };
bca03d5f 2161 void __iomem *ioaddr = tp->mmio_addr;
2162 const struct firmware *fw;
5b538df9 2163
4da19633 2164 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2165
daf9df6d 2166 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2167 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2168 { 0x1f, 0x0002 },
2169 { 0x05, 0x669a },
5b538df9 2170 { 0x1f, 0x0005 },
daf9df6d 2171 { 0x05, 0x8330 },
2172 { 0x06, 0x669a },
2173
2174 { 0x1f, 0x0002 }
2175 };
2176 int val;
2177
4da19633 2178 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2179
4da19633 2180 val = rtl_readphy(tp, 0x0d);
daf9df6d 2181 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2182 static const u32 set[] = {
daf9df6d 2183 0x0065, 0x0066, 0x0067, 0x0068,
2184 0x0069, 0x006a, 0x006b, 0x006c
2185 };
2186 int i;
2187
4da19633 2188 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2189
2190 val &= 0xff00;
2191 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2192 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2193 }
2194 } else {
350f7596 2195 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2196 { 0x1f, 0x0002 },
2197 { 0x05, 0x2642 },
5b538df9 2198 { 0x1f, 0x0005 },
daf9df6d 2199 { 0x05, 0x8330 },
2200 { 0x06, 0x2642 }
5b538df9
FR		 2201 };
2202
4da19633 2203 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2204 }
2205
bca03d5f 2206 /* Fine tune PLL performance */
4da19633 2207 rtl_writephy(tp, 0x1f, 0x0002);
2208 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2209 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2210
bca03d5f 2211 /* Switching regulator Slew rate */
4da19633 2212 rtl_writephy(tp, 0x1f, 0x0002);
2213 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2214
4da19633 2215 rtl_writephy(tp, 0x1f, 0x0005);
2216 rtl_writephy(tp, 0x05, 0x001b);
2217 if (rtl_readphy(tp, 0x06) == 0xb300 &&
bca03d5f 2218 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2219 rtl_phy_write_fw(tp, fw);
2220 release_firmware(fw);
2221 } else {
2222 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2223 }
2224
4da19633 2225 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2226}
2227
4da19633 2228static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2229{
350f7596 2230 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2231 { 0x1f, 0x0002 },
2232 { 0x10, 0x0008 },
2233 { 0x0d, 0x006c },
2234
2235 { 0x1f, 0x0000 },
2236 { 0x0d, 0xf880 },
2237
2238 { 0x1f, 0x0001 },
2239 { 0x17, 0x0cc0 },
2240
2241 { 0x1f, 0x0001 },
2242 { 0x0b, 0xa4d8 },
2243 { 0x09, 0x281c },
2244 { 0x07, 0x2883 },
2245 { 0x0a, 0x6b35 },
2246 { 0x1d, 0x3da4 },
2247 { 0x1c, 0xeffd },
2248 { 0x14, 0x7f52 },
2249 { 0x18, 0x7fc6 },
2250 { 0x08, 0x0601 },
2251 { 0x06, 0x4063 },
2252 { 0x10, 0xf074 },
2253 { 0x1f, 0x0003 },
2254 { 0x13, 0x0789 },
2255 { 0x12, 0xf4bd },
2256 { 0x1a, 0x04fd },
2257 { 0x14, 0x84b0 },
2258 { 0x1f, 0x0000 },
2259 { 0x00, 0x9200 },
2260
2261 { 0x1f, 0x0005 },
2262 { 0x01, 0x0340 },
2263 { 0x1f, 0x0001 },
2264 { 0x04, 0x4000 },
2265 { 0x03, 0x1d21 },
2266 { 0x02, 0x0c32 },
2267 { 0x01, 0x0200 },
2268 { 0x00, 0x5554 },
2269 { 0x04, 0x4800 },
2270 { 0x04, 0x4000 },
2271 { 0x04, 0xf000 },
2272 { 0x03, 0xdf01 },
2273 { 0x02, 0xdf20 },
2274 { 0x01, 0x101a },
2275 { 0x00, 0xa0ff },
2276 { 0x04, 0xf800 },
2277 { 0x04, 0xf000 },
2278 { 0x1f, 0x0000 },
2279
2280 { 0x1f, 0x0007 },
2281 { 0x1e, 0x0023 },
2282 { 0x16, 0x0000 },
2283 { 0x1f, 0x0000 }
2284 };
2285
4da19633 2286 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2287}
2288
e6de30d6 2289static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2290{
2291 static const struct phy_reg phy_reg_init[] = {
2292 { 0x1f, 0x0001 },
2293 { 0x17, 0x0cc0 },
2294
2295 { 0x1f, 0x0007 },
2296 { 0x1e, 0x002d },
2297 { 0x18, 0x0040 },
2298 { 0x1f, 0x0000 }
2299 };
2300
2301 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2302 rtl_patchphy(tp, 0x0d, 1 << 5);
2303}
2304
4da19633 2305static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2306{
350f7596 2307 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2308 { 0x1f, 0x0003 },
2309 { 0x08, 0x441d },
2310 { 0x01, 0x9100 },
2311 { 0x1f, 0x0000 }
2312 };
2313
4da19633 2314 rtl_writephy(tp, 0x1f, 0x0000);
2315 rtl_patchphy(tp, 0x11, 1 << 12);
2316 rtl_patchphy(tp, 0x19, 1 << 13);
2317 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2318
4da19633 2319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2320}
2321
5615d9f1
FR		 2322static void rtl_hw_phy_config(struct net_device *dev)
2323{
2324 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2325
2326 rtl8169_print_mac_version(tp);
2327
2328 switch (tp->mac_version) {
2329 case RTL_GIGA_MAC_VER_01:
2330 break;
2331 case RTL_GIGA_MAC_VER_02:
2332 case RTL_GIGA_MAC_VER_03:
4da19633 2333 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2334 break;
2335 case RTL_GIGA_MAC_VER_04:
4da19633 2336 rtl8169sb_hw_phy_config(tp);
5615d9f1 2337 break;
2e955856 2338 case RTL_GIGA_MAC_VER_05:
4da19633 2339 rtl8169scd_hw_phy_config(tp);
2e955856 2340 break;
8c7006aa 2341 case RTL_GIGA_MAC_VER_06:
4da19633 2342 rtl8169sce_hw_phy_config(tp);
8c7006aa 2343 break;
2857ffb7
FR		 2344 case RTL_GIGA_MAC_VER_07:
2345 case RTL_GIGA_MAC_VER_08:
2346 case RTL_GIGA_MAC_VER_09:
4da19633 2347 rtl8102e_hw_phy_config(tp);
2857ffb7 2348 break;
236b8082 2349 case RTL_GIGA_MAC_VER_11:
4da19633 2350 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2351 break;
2352 case RTL_GIGA_MAC_VER_12:
4da19633 2353 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2354 break;
2355 case RTL_GIGA_MAC_VER_17:
4da19633 2356 rtl8168bef_hw_phy_config(tp);
236b8082 2357 break;
867763c1 2358 case RTL_GIGA_MAC_VER_18:
4da19633 2359 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2360 break;
2361 case RTL_GIGA_MAC_VER_19:
4da19633 2362 rtl8168c_1_hw_phy_config(tp);
867763c1 2363 break;
7da97ec9 2364 case RTL_GIGA_MAC_VER_20:
4da19633 2365 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2366 break;
197ff761 2367 case RTL_GIGA_MAC_VER_21:
4da19633 2368 rtl8168c_3_hw_phy_config(tp);
197ff761 2369 break;
6fb07058 2370 case RTL_GIGA_MAC_VER_22:
4da19633 2371 rtl8168c_4_hw_phy_config(tp);
6fb07058 2372 break;
ef3386f0 2373 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2374 case RTL_GIGA_MAC_VER_24:
4da19633 2375 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2376 break;
5b538df9 2377 case RTL_GIGA_MAC_VER_25:
bca03d5f 2378 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2379 break;
2380 case RTL_GIGA_MAC_VER_26:
bca03d5f 2381 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2382 break;
2383 case RTL_GIGA_MAC_VER_27:
4da19633 2384 rtl8168d_3_hw_phy_config(tp);
5b538df9 2385 break;
e6de30d6 2386 case RTL_GIGA_MAC_VER_28:
2387 rtl8168d_4_hw_phy_config(tp);
2388 break;
ef3386f0 2389
5615d9f1
FR		 2390 default:
2391 break;
2392 }
2393}
2394
1da177e4
LT		 2395static void rtl8169_phy_timer(unsigned long __opaque)
2396{
2397 struct net_device *dev = (struct net_device *)__opaque;
2398 struct rtl8169_private *tp = netdev_priv(dev);
2399 struct timer_list *timer = &tp->timer;
2400 void __iomem *ioaddr = tp->mmio_addr;
2401 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2402
bcf0bf90 2403 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2404
64e4bfb4 2405 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2406 return;
2407
2408 spin_lock_irq(&tp->lock);
2409
4da19633 2410 if (tp->phy_reset_pending(tp)) {
5b0384f4 2411 /*
1da177e4
LT		 2412 * A busy loop could burn quite a few cycles on nowadays CPU.
2413 * Let's delay the execution of the timer for a few ticks.
2414 */
2415 timeout = HZ/10;
2416 goto out_mod_timer;
2417 }
2418
2419 if (tp->link_ok(ioaddr))
2420 goto out_unlock;
2421
bf82c189 2422 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2423
4da19633 2424 tp->phy_reset_enable(tp);
1da177e4
LT		 2425
2426out_mod_timer:
2427 mod_timer(timer, jiffies + timeout);
2428out_unlock:
2429 spin_unlock_irq(&tp->lock);
2430}
2431
2432static inline void rtl8169_delete_timer(struct net_device *dev)
2433{
2434 struct rtl8169_private *tp = netdev_priv(dev);
2435 struct timer_list *timer = &tp->timer;
2436
e179bb7b 2437 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2438 return;
2439
2440 del_timer_sync(timer);
2441}
2442
2443static inline void rtl8169_request_timer(struct net_device *dev)
2444{
2445 struct rtl8169_private *tp = netdev_priv(dev);
2446 struct timer_list *timer = &tp->timer;
2447
e179bb7b 2448 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2449 return;
2450
2efa53f3 2451 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2452}
2453
2454#ifdef CONFIG_NET_POLL_CONTROLLER
2455/*
2456 * Polling 'interrupt' - used by things like netconsole to send skbs
2457 * without having to re-enable interrupts. It's not called while
2458 * the interrupt routine is executing.
2459 */
2460static void rtl8169_netpoll(struct net_device *dev)
2461{
2462 struct rtl8169_private *tp = netdev_priv(dev);
2463 struct pci_dev *pdev = tp->pci_dev;
2464
2465 disable_irq(pdev->irq);
7d12e780 2466 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2467 enable_irq(pdev->irq);
2468}
2469#endif
2470
2471static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2472 void __iomem *ioaddr)
2473{
2474 iounmap(ioaddr);
2475 pci_release_regions(pdev);
87aeec76 2476 pci_clear_mwi(pdev);
1da177e4
LT		 2477 pci_disable_device(pdev);
2478 free_netdev(dev);
2479}
2480
bf793295
FR		 2481static void rtl8169_phy_reset(struct net_device *dev,
2482 struct rtl8169_private *tp)
2483{
07d3f51f 2484 unsigned int i;
bf793295 2485
4da19633 2486 tp->phy_reset_enable(tp);
bf793295 2487 for (i = 0; i < 100; i++) {
4da19633 2488 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2489 return;
2490 msleep(1);
2491 }
bf82c189 2492 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2493}
2494
4ff96fa6
FR		 2495static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2496{
2497 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2498
5615d9f1 2499 rtl_hw_phy_config(dev);
4ff96fa6 2500
77332894
MS		 2501 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2502 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2503 RTL_W8(0x82, 0x01);
2504 }
4ff96fa6 2505
6dccd16b
FR		 2506 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2507
2508 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2509 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2510
bcf0bf90 2511 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2512 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2513 RTL_W8(0x82, 0x01);
2514 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2515 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2516 }
2517
bf793295
FR		 2518 rtl8169_phy_reset(dev, tp);
2519
901dda2b
FR		 2520 /*
2521 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2522 * only 8101. Don't panic.
2523 */
2524 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2525
bf82c189
JP		 2526 if (RTL_R8(PHYstatus) & TBI_Enable)
2527 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2528}
2529
773d2021
FR		 2530static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2531{
2532 void __iomem *ioaddr = tp->mmio_addr;
2533 u32 high;
2534 u32 low;
2535
2536 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2537 high = addr[4] | (addr[5] << 8);
2538
2539 spin_lock_irq(&tp->lock);
2540
2541 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2542
773d2021 2543 RTL_W32(MAC4, high);
908ba2bf 2544 RTL_R32(MAC4);
2545
78f1cd02 2546 RTL_W32(MAC0, low);
908ba2bf 2547 RTL_R32(MAC0);
2548
773d2021
FR		 2549 RTL_W8(Cfg9346, Cfg9346_Lock);
2550
2551 spin_unlock_irq(&tp->lock);
2552}
2553
2554static int rtl_set_mac_address(struct net_device *dev, void *p)
2555{
2556 struct rtl8169_private *tp = netdev_priv(dev);
2557 struct sockaddr *addr = p;
2558
2559 if (!is_valid_ether_addr(addr->sa_data))
2560 return -EADDRNOTAVAIL;
2561
2562 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2563
2564 rtl_rar_set(tp, dev->dev_addr);
2565
2566 return 0;
2567}
2568
5f787a1a
FR		 2569static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2570{
2571 struct rtl8169_private *tp = netdev_priv(dev);
2572 struct mii_ioctl_data *data = if_mii(ifr);
2573
8b4ab28d
FR		 2574 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2575}
5f787a1a 2576
8b4ab28d
FR		 2577static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2578{
5f787a1a
FR		 2579 switch (cmd) {
2580 case SIOCGMIIPHY:
2581 data->phy_id = 32; /* Internal PHY */
2582 return 0;
2583
2584 case SIOCGMIIREG:
4da19633 2585 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2586 return 0;
2587
2588 case SIOCSMIIREG:
4da19633 2589 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2590 return 0;
2591 }
2592 return -EOPNOTSUPP;
2593}
2594
8b4ab28d
FR		 2595static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2596{
2597 return -EOPNOTSUPP;
2598}
2599
0e485150
FR		 2600static const struct rtl_cfg_info {
2601 void (*hw_start)(struct net_device *);
2602 unsigned int region;
2603 unsigned int align;
2604 u16 intr_event;
2605 u16 napi_event;
ccdffb9a 2606 unsigned features;
f21b75e9 2607 u8 default_ver;
0e485150
FR		 2608} rtl_cfg_infos [] = {
2609 [RTL_CFG_0] = {
2610 .hw_start = rtl_hw_start_8169,
2611 .region = 1,
e9f63f30 2612 .align = 0,
0e485150
FR		 2613 .intr_event = SYSErr | LinkChg | RxOverflow |
2614 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2615 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2616 .features = RTL_FEATURE_GMII,
2617 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2618 },
2619 [RTL_CFG_1] = {
2620 .hw_start = rtl_hw_start_8168,
2621 .region = 2,
2622 .align = 8,
53f57357 2623 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2624 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2625 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2626 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2627 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2628 },
2629 [RTL_CFG_2] = {
2630 .hw_start = rtl_hw_start_8101,
2631 .region = 2,
2632 .align = 8,
2633 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2634 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2635 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2636 .features = RTL_FEATURE_MSI,
2637 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2638 }
2639};
2640
fbac58fc
FR		 2641/* Cfg9346_Unlock assumed. */
2642static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2643 const struct rtl_cfg_info *cfg)
2644{
2645 unsigned msi = 0;
2646 u8 cfg2;
2647
2648 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2649 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2650 if (pci_enable_msi(pdev)) {
2651 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2652 } else {
2653 cfg2 |= MSIEnable;
2654 msi = RTL_FEATURE_MSI;
2655 }
2656 }
2657 RTL_W8(Config2, cfg2);
2658 return msi;
2659}
2660
2661static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2662{
2663 if (tp->features & RTL_FEATURE_MSI) {
2664 pci_disable_msi(pdev);
2665 tp->features &= ~RTL_FEATURE_MSI;
2666 }
2667}
2668
8b4ab28d
FR		 2669static const struct net_device_ops rtl8169_netdev_ops = {
2670 .ndo_open = rtl8169_open,
2671 .ndo_stop = rtl8169_close,
2672 .ndo_get_stats = rtl8169_get_stats,
00829823 2673 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2674 .ndo_tx_timeout = rtl8169_tx_timeout,
2675 .ndo_validate_addr = eth_validate_addr,
2676 .ndo_change_mtu = rtl8169_change_mtu,
2677 .ndo_set_mac_address = rtl_set_mac_address,
2678 .ndo_do_ioctl = rtl8169_ioctl,
2679 .ndo_set_multicast_list = rtl_set_rx_mode,
2680#ifdef CONFIG_R8169_VLAN
2681 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2682#endif
2683#ifdef CONFIG_NET_POLL_CONTROLLER
2684 .ndo_poll_controller = rtl8169_netpoll,
2685#endif
2686
2687};
2688
c0e45c1c 2689static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2690{
2691 struct mdio_ops *ops = &tp->mdio_ops;
2692
2693 switch (tp->mac_version) {
2694 case RTL_GIGA_MAC_VER_27:
2695 ops->write = r8168dp_1_mdio_write;
2696 ops->read = r8168dp_1_mdio_read;
2697 break;
e6de30d6 2698 case RTL_GIGA_MAC_VER_28:
2699 ops->write = r8168dp_2_mdio_write;
2700 ops->read = r8168dp_2_mdio_read;
2701 break;
c0e45c1c 2702 default:
2703 ops->write = r8169_mdio_write;
2704 ops->read = r8169_mdio_read;
2705 break;
2706 }
2707}
2708
065c27c1 2709static void r810x_phy_power_down(struct rtl8169_private *tp)
2710{
2711 rtl_writephy(tp, 0x1f, 0x0000);
2712 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2713}
2714
2715static void r810x_phy_power_up(struct rtl8169_private *tp)
2716{
2717 rtl_writephy(tp, 0x1f, 0x0000);
2718 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2719}
2720
2721static void r810x_pll_power_down(struct rtl8169_private *tp)
2722{
2723 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2724 rtl_writephy(tp, 0x1f, 0x0000);
2725 rtl_writephy(tp, MII_BMCR, 0x0000);
2726 return;
2727 }
2728
2729 r810x_phy_power_down(tp);
2730}
2731
2732static void r810x_pll_power_up(struct rtl8169_private *tp)
2733{
2734 r810x_phy_power_up(tp);
2735}
2736
2737static void r8168_phy_power_up(struct rtl8169_private *tp)
2738{
2739 rtl_writephy(tp, 0x1f, 0x0000);
2740 rtl_writephy(tp, 0x0e, 0x0000);
2741 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2742}
2743
2744static void r8168_phy_power_down(struct rtl8169_private *tp)
2745{
2746 rtl_writephy(tp, 0x1f, 0x0000);
2747 rtl_writephy(tp, 0x0e, 0x0200);
2748 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2749}
2750
2751static void r8168_pll_power_down(struct rtl8169_private *tp)
2752{
2753 void __iomem *ioaddr = tp->mmio_addr;
2754
2755 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2756 return;
2757
2758 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2759 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2760 (RTL_R16(CPlusCmd) & ASF)) {
2761 return;
2762 }
2763
2764 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2765 rtl_writephy(tp, 0x1f, 0x0000);
2766 rtl_writephy(tp, MII_BMCR, 0x0000);
2767
2768 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2769 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2770 return;
2771 }
2772
2773 r8168_phy_power_down(tp);
2774
2775 switch (tp->mac_version) {
2776 case RTL_GIGA_MAC_VER_25:
2777 case RTL_GIGA_MAC_VER_26:
2778 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2779 break;
2780 }
2781}
2782
2783static void r8168_pll_power_up(struct rtl8169_private *tp)
2784{
2785 void __iomem *ioaddr = tp->mmio_addr;
2786
2787 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2788 return;
2789
2790 switch (tp->mac_version) {
2791 case RTL_GIGA_MAC_VER_25:
2792 case RTL_GIGA_MAC_VER_26:
2793 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2794 break;
2795 }
2796
2797 r8168_phy_power_up(tp);
2798}
2799
2800static void rtl_pll_power_op(struct rtl8169_private *tp,
2801 void (*op)(struct rtl8169_private *))
2802{
2803 if (op)
2804 op(tp);
2805}
2806
2807static void rtl_pll_power_down(struct rtl8169_private *tp)
2808{
2809 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2810}
2811
2812static void rtl_pll_power_up(struct rtl8169_private *tp)
2813{
2814 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2815}
2816
2817static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2818{
2819 struct pll_power_ops *ops = &tp->pll_power_ops;
2820
2821 switch (tp->mac_version) {
2822 case RTL_GIGA_MAC_VER_07:
2823 case RTL_GIGA_MAC_VER_08:
2824 case RTL_GIGA_MAC_VER_09:
2825 case RTL_GIGA_MAC_VER_10:
2826 case RTL_GIGA_MAC_VER_16:
2827 ops->down = r810x_pll_power_down;
2828 ops->up = r810x_pll_power_up;
2829 break;
2830
2831 case RTL_GIGA_MAC_VER_11:
2832 case RTL_GIGA_MAC_VER_12:
2833 case RTL_GIGA_MAC_VER_17:
2834 case RTL_GIGA_MAC_VER_18:
2835 case RTL_GIGA_MAC_VER_19:
2836 case RTL_GIGA_MAC_VER_20:
2837 case RTL_GIGA_MAC_VER_21:
2838 case RTL_GIGA_MAC_VER_22:
2839 case RTL_GIGA_MAC_VER_23:
2840 case RTL_GIGA_MAC_VER_24:
2841 case RTL_GIGA_MAC_VER_25:
2842 case RTL_GIGA_MAC_VER_26:
2843 case RTL_GIGA_MAC_VER_27:
e6de30d6 2844 case RTL_GIGA_MAC_VER_28:
065c27c1 2845 ops->down = r8168_pll_power_down;
2846 ops->up = r8168_pll_power_up;
2847 break;
2848
2849 default:
2850 ops->down = NULL;
2851 ops->up = NULL;
2852 break;
2853 }
2854}
2855
1da177e4 2856static int __devinit
4ff96fa6 2857rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2858{
0e485150
FR		 2859 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2860 const unsigned int region = cfg->region;
1da177e4 2861 struct rtl8169_private *tp;
ccdffb9a 2862 struct mii_if_info *mii;
4ff96fa6
FR		 2863 struct net_device *dev;
2864 void __iomem *ioaddr;
07d3f51f
FR		 2865 unsigned int i;
2866 int rc;
1da177e4 2867
4ff96fa6
FR		 2868 if (netif_msg_drv(&debug)) {
2869 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2870 MODULENAME, RTL8169_VERSION);
2871 }
1da177e4 2872
1da177e4 2873 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2874 if (!dev) {
b57b7e5a 2875 if (netif_msg_drv(&debug))
9b91cf9d 2876 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2877 rc = -ENOMEM;
2878 goto out;
1da177e4
LT		 2879 }
2880
1da177e4 2881 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2882 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2883 tp = netdev_priv(dev);
c4028958 2884 tp->dev = dev;
21e197f2 2885 tp->pci_dev = pdev;
b57b7e5a 2886 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2887
ccdffb9a
FR		 2888 mii = &tp->mii;
2889 mii->dev = dev;
2890 mii->mdio_read = rtl_mdio_read;
2891 mii->mdio_write = rtl_mdio_write;
2892 mii->phy_id_mask = 0x1f;
2893 mii->reg_num_mask = 0x1f;
2894 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2895
1da177e4
LT		 2896 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2897 rc = pci_enable_device(pdev);
b57b7e5a 2898 if (rc < 0) {
bf82c189 2899 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 2900 goto err_out_free_dev_1;
1da177e4
LT		 2901 }
2902
87aeec76 2903 if (pci_set_mwi(pdev) < 0)
2904 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 2905
1da177e4 2906 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2907 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 2908 netif_err(tp, probe, dev,
2909 "region #%d not an MMIO resource, aborting\n",
2910 region);
1da177e4 2911 rc = -ENODEV;
87aeec76 2912 goto err_out_mwi_2;
1da177e4 2913 }
4ff96fa6 2914
1da177e4 2915 /* check for weird/broken PCI region reporting */
bcf0bf90 2916 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 2917 netif_err(tp, probe, dev,
2918 "Invalid PCI region size(s), aborting\n");
1da177e4 2919 rc = -ENODEV;
87aeec76 2920 goto err_out_mwi_2;
1da177e4
LT		 2921 }
2922
2923 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2924 if (rc < 0) {
bf82c189 2925 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 2926 goto err_out_mwi_2;
1da177e4
LT		 2927 }
2928
2929 tp->cp_cmd = PCIMulRW | RxChkSum;
2930
2931 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 2932 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2933 tp->cp_cmd |= PCIDAC;
2934 dev->features |= NETIF_F_HIGHDMA;
2935 } else {
284901a9 2936 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2937 if (rc < 0) {
bf82c189 2938 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 2939 goto err_out_free_res_3;
1da177e4
LT		 2940 }
2941 }
2942
1da177e4 2943 /* ioremap MMIO region */
bcf0bf90 2944 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2945 if (!ioaddr) {
bf82c189 2946 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 2947 rc = -EIO;
87aeec76 2948 goto err_out_free_res_3;
1da177e4
LT		 2949 }
2950
4300e8c7
DM		 2951 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2952 if (!tp->pcie_cap)
2953 netif_info(tp, probe, dev, "no PCI Express capability\n");
2954
d78ad8cb 2955 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2956
2957 /* Soft reset the chip. */
2958 RTL_W8(ChipCmd, CmdReset);
2959
2960 /* Check that the chip has finished the reset. */
07d3f51f 2961 for (i = 0; i < 100; i++) {
1da177e4
LT		 2962 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2963 break;
b518fa8e 2964 msleep_interruptible(1);
1da177e4
LT		 2965 }
2966
d78ad8cb
KW		 2967 RTL_W16(IntrStatus, 0xffff);
2968
ca52efd5 2969 pci_set_master(pdev);
2970
1da177e4
LT		 2971 /* Identify chip attached to board */
2972 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 2973
c0e45c1c 2974 rtl_init_mdio_ops(tp);
065c27c1 2975 rtl_init_pll_power_ops(tp);
c0e45c1c 2976
f21b75e9
JD		 2977 /* Use appropriate default if unknown */
2978 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 2979 netif_notice(tp, probe, dev,
2980 "unknown MAC, using family default\n");
f21b75e9
JD		 2981 tp->mac_version = cfg->default_ver;
2982 }
2983
1da177e4 2984 rtl8169_print_mac_version(tp);
1da177e4 2985
cee60c37 2986 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2987 if (tp->mac_version == rtl_chip_info[i].mac_version)
2988 break;
2989 }
cee60c37 2990 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 2991 dev_err(&pdev->dev,
2992 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 2993 goto err_out_msi_4;
1da177e4
LT		 2994 }
2995 tp->chipset = i;
2996
5d06a99f
FR		 2997 RTL_W8(Cfg9346, Cfg9346_Unlock);
2998 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2999 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3000 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3001 tp->features |= RTL_FEATURE_WOL;
3002 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3003 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3004 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3005 RTL_W8(Cfg9346, Cfg9346_Lock);
3006
66ec5d4f
FR		 3007 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3008 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3009 tp->set_speed = rtl8169_set_speed_tbi;
3010 tp->get_settings = rtl8169_gset_tbi;
3011 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3012 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3013 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3014 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3015
64e4bfb4 3016 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3017 } else {
3018 tp->set_speed = rtl8169_set_speed_xmii;
3019 tp->get_settings = rtl8169_gset_xmii;
3020 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3021 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3022 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3023 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3024 }
3025
df58ef51
FR		 3026 spin_lock_init(&tp->lock);
3027
738e1e69
PV		 3028 tp->mmio_addr = ioaddr;
3029
7bf6bf48 3030 /* Get MAC address */
1da177e4
LT		 3031 for (i = 0; i < MAC_ADDR_LEN; i++)
3032 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3033 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3034
1da177e4 3035 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3036 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3037 dev->irq = pdev->irq;
3038 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3039
bea3348e 3040 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3041
3042#ifdef CONFIG_R8169_VLAN
3043 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3044#endif
2edae08e 3045 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3046
3047 tp->intr_mask = 0xffff;
0e485150
FR		 3048 tp->hw_start = cfg->hw_start;
3049 tp->intr_event = cfg->intr_event;
3050 tp->napi_event = cfg->napi_event;
1da177e4 3051
2efa53f3
FR		 3052 init_timer(&tp->timer);
3053 tp->timer.data = (unsigned long) dev;
3054 tp->timer.function = rtl8169_phy_timer;
3055
1da177e4 3056 rc = register_netdev(dev);
4ff96fa6 3057 if (rc < 0)
87aeec76 3058 goto err_out_msi_4;
1da177e4
LT		 3059
3060 pci_set_drvdata(pdev, dev);
3061
bf82c189
JP		 3062 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3063 rtl_chip_info[tp->chipset].name,
3064 dev->base_addr, dev->dev_addr,
3065 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3066
e6de30d6 3067 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3068 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3069 rtl8168_driver_start(tp);
e6de30d6 3070 }
b646d900 3071
4ff96fa6 3072 rtl8169_init_phy(dev, tp);
05af2142
SW		 3073
3074 /*
3075 * Pretend we are using VLANs; This bypasses a nasty bug where
3076 * Interrupts stop flowing on high load on 8110SCd controllers.
3077 */
3078 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3079 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3080
8b76ab39 3081 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3082
f3ec4f87
AS		 3083 if (pci_dev_run_wake(pdev))
3084 pm_runtime_put_noidle(&pdev->dev);
e1759441 3085
4ff96fa6
FR		 3086out:
3087 return rc;
1da177e4 3088
87aeec76 3089err_out_msi_4:
fbac58fc 3090 rtl_disable_msi(pdev, tp);
4ff96fa6 3091 iounmap(ioaddr);
87aeec76 3092err_out_free_res_3:
4ff96fa6 3093 pci_release_regions(pdev);
87aeec76 3094err_out_mwi_2:
4ff96fa6 3095 pci_clear_mwi(pdev);
4ff96fa6
FR		 3096 pci_disable_device(pdev);
3097err_out_free_dev_1:
3098 free_netdev(dev);
3099 goto out;
1da177e4
LT		 3100}
3101
07d3f51f 3102static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3103{
3104 struct net_device *dev = pci_get_drvdata(pdev);
3105 struct rtl8169_private *tp = netdev_priv(dev);
3106
e6de30d6 3107 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3108 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3109 rtl8168_driver_stop(tp);
e6de30d6 3110 }
b646d900 3111
23f333a2 3112 cancel_delayed_work_sync(&tp->task);
eb2a021c 3113
1da177e4 3114 unregister_netdev(dev);
cc098dc7 3115
f3ec4f87
AS		 3116 if (pci_dev_run_wake(pdev))
3117 pm_runtime_get_noresume(&pdev->dev);
e1759441 3118
cc098dc7
IV		 3119 /* restore original MAC address */
3120 rtl_rar_set(tp, dev->perm_addr);
3121
fbac58fc 3122 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3123 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3124 pci_set_drvdata(pdev, NULL);
3125}
3126
1da177e4
LT		 3127static int rtl8169_open(struct net_device *dev)
3128{
3129 struct rtl8169_private *tp = netdev_priv(dev);
3130 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3131 int retval = -ENOMEM;
1da177e4 3132
e1759441 3133 pm_runtime_get_sync(&pdev->dev);
1da177e4 3134
1da177e4
LT		 3135 /*
3136 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3137 * dma_alloc_coherent provides more.
1da177e4 3138 */
82553bb6
SG		 3139 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3140 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3141 if (!tp->TxDescArray)
e1759441 3142 goto err_pm_runtime_put;
1da177e4 3143
82553bb6
SG		 3144 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3145 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3146 if (!tp->RxDescArray)
99f252b0 3147 goto err_free_tx_0;
1da177e4
LT		 3148
3149 retval = rtl8169_init_ring(dev);
3150 if (retval < 0)
99f252b0 3151 goto err_free_rx_1;
1da177e4 3152
c4028958 3153 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3154
99f252b0
FR		 3155 smp_mb();
3156
fbac58fc
FR		 3157 retval = request_irq(dev->irq, rtl8169_interrupt,
3158 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3159 dev->name, dev);
3160 if (retval < 0)
3161 goto err_release_ring_2;
3162
bea3348e 3163 napi_enable(&tp->napi);
bea3348e 3164
065c27c1 3165 rtl_pll_power_up(tp);
3166
07ce4064 3167 rtl_hw_start(dev);
1da177e4
LT		 3168
3169 rtl8169_request_timer(dev);
3170
e1759441
RW		 3171 tp->saved_wolopts = 0;
3172 pm_runtime_put_noidle(&pdev->dev);
3173
1da177e4
LT		 3174 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3175out:
3176 return retval;
3177
99f252b0
FR		 3178err_release_ring_2:
3179 rtl8169_rx_clear(tp);
3180err_free_rx_1:
82553bb6
SG		 3181 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3182 tp->RxPhyAddr);
e1759441 3183 tp->RxDescArray = NULL;
99f252b0 3184err_free_tx_0:
82553bb6
SG		 3185 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3186 tp->TxPhyAddr);
e1759441
RW		 3187 tp->TxDescArray = NULL;
3188err_pm_runtime_put:
3189 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3190 goto out;
3191}
3192
e6de30d6 3193static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3194{
e6de30d6 3195 void __iomem *ioaddr = tp->mmio_addr;
3196
1da177e4
LT		 3197 /* Disable interrupts */
3198 rtl8169_irq_mask_and_ack(ioaddr);
3199
e6de30d6 3200 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3201 while (RTL_R8(TxPoll) & NPQ)
3202 udelay(20);
3203
3204 }
3205
1da177e4
LT		 3206 /* Reset the chipset */
3207 RTL_W8(ChipCmd, CmdReset);
3208
3209 /* PCI commit */
3210 RTL_R8(ChipCmd);
3211}
3212
7f796d83 3213static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3214{
3215 void __iomem *ioaddr = tp->mmio_addr;
3216 u32 cfg = rtl8169_rx_config;
3217
3218 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3219 RTL_W32(RxConfig, cfg);
3220
3221 /* Set DMA burst size and Interframe Gap Time */
3222 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3223 (InterFrameGap << TxInterFrameGapShift));
3224}
3225
07ce4064 3226static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3227{
3228 struct rtl8169_private *tp = netdev_priv(dev);
3229 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3230 unsigned int i;
1da177e4
LT		 3231
3232 /* Soft reset the chip. */
3233 RTL_W8(ChipCmd, CmdReset);
3234
3235 /* Check that the chip has finished the reset. */
07d3f51f 3236 for (i = 0; i < 100; i++) {
1da177e4
LT		 3237 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3238 break;
b518fa8e 3239 msleep_interruptible(1);
1da177e4
LT		 3240 }
3241
07ce4064
FR		 3242 tp->hw_start(dev);
3243
07ce4064
FR		 3244 netif_start_queue(dev);
3245}
3246
3247
7f796d83
FR		 3248static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3249 void __iomem *ioaddr)
3250{
3251 /*
3252 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3253 * register to be written before TxDescAddrLow to work.
3254 * Switching from MMIO to I/O access fixes the issue as well.
3255 */
3256 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3257 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3258 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3259 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3260}
3261
3262static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3263{
3264 u16 cmd;
3265
3266 cmd = RTL_R16(CPlusCmd);
3267 RTL_W16(CPlusCmd, cmd);
3268 return cmd;
3269}
3270
fdd7b4c3 3271static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3272{
3273 /* Low hurts. Let's disable the filtering. */
207d6e87 3274 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3275}
3276
6dccd16b
FR		 3277static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3278{
350f7596 3279 static const struct {
6dccd16b
FR		 3280 u32 mac_version;
3281 u32 clk;
3282 u32 val;
3283 } cfg2_info [] = {
3284 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3285 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3286 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3287 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3288 }, *p = cfg2_info;
3289 unsigned int i;
3290 u32 clk;
3291
3292 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3293 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3294 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3295 RTL_W32(0x7c, p->val);
3296 break;
3297 }
3298 }
3299}
3300
07ce4064
FR		 3301static void rtl_hw_start_8169(struct net_device *dev)
3302{
3303 struct rtl8169_private *tp = netdev_priv(dev);
3304 void __iomem *ioaddr = tp->mmio_addr;
3305 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3306
9cb427b6
FR		 3307 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3308 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3309 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3310 }
3311
1da177e4 3312 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3313 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3314 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3315 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3316 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3317 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3318
f0298f81 3319 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3320
6f0333b8 3321 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3322
c946b304
FR		 3323 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3324 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3325 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3326 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3327 rtl_set_rx_tx_config_registers(tp);
1da177e4 3328
7f796d83 3329 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3330
bcf0bf90
FR		 3331 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3332 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3333 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3334 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3335 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3336 }
3337
bcf0bf90
FR		 3338 RTL_W16(CPlusCmd, tp->cp_cmd);
3339
6dccd16b
FR		 3340 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3341
1da177e4
LT		 3342 /*
3343 * Undocumented corner. Supposedly:
3344 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3345 */
3346 RTL_W16(IntrMitigate, 0x0000);
3347
7f796d83 3348 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3349
c946b304
FR		 3350 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3351 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3352 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3353 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3354 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3355 rtl_set_rx_tx_config_registers(tp);
3356 }
3357
1da177e4 3358 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3359
3360 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3361 RTL_R8(IntrMask);
1da177e4
LT		 3362
3363 RTL_W32(RxMissed, 0);
3364
07ce4064 3365 rtl_set_rx_mode(dev);
1da177e4
LT		 3366
3367 /* no early-rx interrupts */
3368 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3369
3370 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3371 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3372}
1da177e4 3373
9c14ceaf 3374static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3375{
9c14ceaf
FR		 3376 struct net_device *dev = pci_get_drvdata(pdev);
3377 struct rtl8169_private *tp = netdev_priv(dev);
3378 int cap = tp->pcie_cap;
3379
3380 if (cap) {
3381 u16 ctl;
458a9f61 3382
9c14ceaf
FR		 3383 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3384 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3385 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3386 }
458a9f61
FR		 3387}
3388
650e8d5d 3389static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3390{
3391 u32 csi;
3392
3393 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3394 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3395}
3396
e6de30d6 3397static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3398{
3399 rtl_csi_access_enable(ioaddr, 0x17000000);
3400}
3401
650e8d5d 3402static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3403{
3404 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3405}
3406
3407struct ephy_info {
3408 unsigned int offset;
3409 u16 mask;
3410 u16 bits;
3411};
3412
350f7596 3413static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3414{
3415 u16 w;
3416
3417 while (len-- > 0) {
3418 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3419 rtl_ephy_write(ioaddr, e->offset, w);
3420 e++;
3421 }
3422}
3423
b726e493
FR		 3424static void rtl_disable_clock_request(struct pci_dev *pdev)
3425{
3426 struct net_device *dev = pci_get_drvdata(pdev);
3427 struct rtl8169_private *tp = netdev_priv(dev);
3428 int cap = tp->pcie_cap;
3429
3430 if (cap) {
3431 u16 ctl;
3432
3433 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3434 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3435 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3436 }
3437}
3438
e6de30d6 3439static void rtl_enable_clock_request(struct pci_dev *pdev)
3440{
3441 struct net_device *dev = pci_get_drvdata(pdev);
3442 struct rtl8169_private *tp = netdev_priv(dev);
3443 int cap = tp->pcie_cap;
3444
3445 if (cap) {
3446 u16 ctl;
3447
3448 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3449 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3450 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3451 }
3452}
3453
b726e493
FR		 3454#define R8168_CPCMD_QUIRK_MASK (\
3455 EnableBist | \
3456 Mac_dbgo_oe | \
3457 Force_half_dup | \
3458 Force_rxflow_en | \
3459 Force_txflow_en | \
3460 Cxpl_dbg_sel | \
3461 ASF | \
3462 PktCntrDisable | \
3463 Mac_dbgo_sel)
3464
219a1e9d
FR		 3465static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3466{
b726e493
FR		 3467 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3468
3469 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3470
2e68ae44
FR		 3471 rtl_tx_performance_tweak(pdev,
3472 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3473}
3474
3475static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3476{
3477 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3478
f0298f81 3479 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3480
3481 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3482}
3483
3484static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3485{
b726e493
FR		 3486 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3487
3488 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3489
219a1e9d 3490 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3491
3492 rtl_disable_clock_request(pdev);
3493
3494 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3495}
3496
ef3386f0 3497static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3498{
350f7596 3499 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3500 { 0x01, 0, 0x0001 },
3501 { 0x02, 0x0800, 0x1000 },
3502 { 0x03, 0, 0x0042 },
3503 { 0x06, 0x0080, 0x0000 },
3504 { 0x07, 0, 0x2000 }
3505 };
3506
650e8d5d 3507 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3508
3509 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3510
219a1e9d
FR		 3511 __rtl_hw_start_8168cp(ioaddr, pdev);
3512}
3513
ef3386f0
FR		 3514static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3515{
650e8d5d 3516 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3517
3518 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3519
3520 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3521
3522 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3523}
3524
7f3e3d3a
FR		 3525static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3526{
650e8d5d 3527 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3528
3529 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3530
3531 /* Magic. */
3532 RTL_W8(DBG_REG, 0x20);
3533
f0298f81 3534 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3535
3536 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3537
3538 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3539}
3540
219a1e9d
FR		 3541static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3542{
350f7596 3543 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3544 { 0x02, 0x0800, 0x1000 },
3545 { 0x03, 0, 0x0002 },
3546 { 0x06, 0x0080, 0x0000 }
3547 };
3548
650e8d5d 3549 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3550
3551 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3552
3553 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3554
219a1e9d
FR		 3555 __rtl_hw_start_8168cp(ioaddr, pdev);
3556}
3557
3558static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3559{
350f7596 3560 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3561 { 0x01, 0, 0x0001 },
3562 { 0x03, 0x0400, 0x0220 }
3563 };
3564
650e8d5d 3565 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3566
3567 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3568
219a1e9d
FR		 3569 __rtl_hw_start_8168cp(ioaddr, pdev);
3570}
3571
197ff761
FR		 3572static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3573{
3574 rtl_hw_start_8168c_2(ioaddr, pdev);
3575}
3576
6fb07058
FR		 3577static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3578{
650e8d5d 3579 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3580
3581 __rtl_hw_start_8168cp(ioaddr, pdev);
3582}
3583
5b538df9
FR		 3584static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3585{
650e8d5d 3586 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3587
3588 rtl_disable_clock_request(pdev);
3589
f0298f81 3590 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3591
3592 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3593
3594 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3595}
3596
e6de30d6 3597static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3598{
3599 static const struct ephy_info e_info_8168d_4[] = {
3600 { 0x0b, ~0, 0x48 },
3601 { 0x19, 0x20, 0x50 },
3602 { 0x0c, ~0, 0x20 }
3603 };
3604 int i;
3605
3606 rtl_csi_access_enable_1(ioaddr);
3607
3608 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3609
3610 RTL_W8(MaxTxPacketSize, TxPacketMax);
3611
3612 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3613 const struct ephy_info *e = e_info_8168d_4 + i;
3614 u16 w;
3615
3616 w = rtl_ephy_read(ioaddr, e->offset);
3617 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3618 }
3619
3620 rtl_enable_clock_request(pdev);
3621}
3622
07ce4064
FR		 3623static void rtl_hw_start_8168(struct net_device *dev)
3624{
2dd99530
FR		 3625 struct rtl8169_private *tp = netdev_priv(dev);
3626 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3627 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3628
3629 RTL_W8(Cfg9346, Cfg9346_Unlock);
3630
f0298f81 3631 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3632
6f0333b8 3633 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3634
0e485150 3635 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3636
3637 RTL_W16(CPlusCmd, tp->cp_cmd);
3638
0e485150 3639 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3640
0e485150
FR		 3641 /* Work around for RxFIFO overflow. */
3642 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3643 tp->intr_event |= RxFIFOOver | PCSTimeout;
3644 tp->intr_event &= ~RxOverflow;
3645 }
3646
3647 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3648
b8363901
FR		 3649 rtl_set_rx_mode(dev);
3650
3651 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3652 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3653
3654 RTL_R8(IntrMask);
3655
219a1e9d
FR		 3656 switch (tp->mac_version) {
3657 case RTL_GIGA_MAC_VER_11:
3658 rtl_hw_start_8168bb(ioaddr, pdev);
3659 break;
3660
3661 case RTL_GIGA_MAC_VER_12:
3662 case RTL_GIGA_MAC_VER_17:
3663 rtl_hw_start_8168bef(ioaddr, pdev);
3664 break;
3665
3666 case RTL_GIGA_MAC_VER_18:
ef3386f0 3667 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3668 break;
3669
3670 case RTL_GIGA_MAC_VER_19:
3671 rtl_hw_start_8168c_1(ioaddr, pdev);
3672 break;
3673
3674 case RTL_GIGA_MAC_VER_20:
3675 rtl_hw_start_8168c_2(ioaddr, pdev);
3676 break;
3677
197ff761
FR		 3678 case RTL_GIGA_MAC_VER_21:
3679 rtl_hw_start_8168c_3(ioaddr, pdev);
3680 break;
3681
6fb07058
FR		 3682 case RTL_GIGA_MAC_VER_22:
3683 rtl_hw_start_8168c_4(ioaddr, pdev);
3684 break;
3685
ef3386f0
FR		 3686 case RTL_GIGA_MAC_VER_23:
3687 rtl_hw_start_8168cp_2(ioaddr, pdev);
3688 break;
3689
7f3e3d3a
FR		 3690 case RTL_GIGA_MAC_VER_24:
3691 rtl_hw_start_8168cp_3(ioaddr, pdev);
3692 break;
3693
5b538df9 3694 case RTL_GIGA_MAC_VER_25:
daf9df6d 3695 case RTL_GIGA_MAC_VER_26:
3696 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3697 rtl_hw_start_8168d(ioaddr, pdev);
3698 break;
3699
e6de30d6 3700 case RTL_GIGA_MAC_VER_28:
3701 rtl_hw_start_8168d_4(ioaddr, pdev);
3702 break;
3703
219a1e9d
FR		 3704 default:
3705 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3706 dev->name, tp->mac_version);
3707 break;
3708 }
2dd99530 3709
0e485150
FR		 3710 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3711
b8363901
FR		 3712 RTL_W8(Cfg9346, Cfg9346_Lock);
3713
2dd99530 3714 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3715
0e485150 3716 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3717}
1da177e4 3718
2857ffb7
FR		 3719#define R810X_CPCMD_QUIRK_MASK (\
3720 EnableBist | \
3721 Mac_dbgo_oe | \
3722 Force_half_dup | \
5edcc537 3723 Force_rxflow_en | \
2857ffb7
FR		 3724 Force_txflow_en | \
3725 Cxpl_dbg_sel | \
3726 ASF | \
3727 PktCntrDisable | \
3728 PCIDAC | \
3729 PCIMulRW)
3730
3731static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3732{
350f7596 3733 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3734 { 0x01, 0, 0x6e65 },
3735 { 0x02, 0, 0x091f },
3736 { 0x03, 0, 0xc2f9 },
3737 { 0x06, 0, 0xafb5 },
3738 { 0x07, 0, 0x0e00 },
3739 { 0x19, 0, 0xec80 },
3740 { 0x01, 0, 0x2e65 },
3741 { 0x01, 0, 0x6e65 }
3742 };
3743 u8 cfg1;
3744
650e8d5d 3745 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3746
3747 RTL_W8(DBG_REG, FIX_NAK_1);
3748
3749 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3750
3751 RTL_W8(Config1,
3752 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3753 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3754
3755 cfg1 = RTL_R8(Config1);
3756 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3757 RTL_W8(Config1, cfg1 & ~LEDS0);
3758
3759 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3760
3761 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3762}
3763
3764static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3765{
650e8d5d 3766 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3767
3768 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3769
3770 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3771 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3772
3773 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3774}
3775
3776static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3777{
3778 rtl_hw_start_8102e_2(ioaddr, pdev);
3779
3780 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3781}
3782
07ce4064
FR		 3783static void rtl_hw_start_8101(struct net_device *dev)
3784{
cdf1a608
FR		 3785 struct rtl8169_private *tp = netdev_priv(dev);
3786 void __iomem *ioaddr = tp->mmio_addr;
3787 struct pci_dev *pdev = tp->pci_dev;
3788
e3cf0cc0
FR		 3789 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3790 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3791 int cap = tp->pcie_cap;
3792
3793 if (cap) {
3794 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3795 PCI_EXP_DEVCTL_NOSNOOP_EN);
3796 }
cdf1a608
FR		 3797 }
3798
2857ffb7
FR		 3799 switch (tp->mac_version) {
3800 case RTL_GIGA_MAC_VER_07:
3801 rtl_hw_start_8102e_1(ioaddr, pdev);
3802 break;
3803
3804 case RTL_GIGA_MAC_VER_08:
3805 rtl_hw_start_8102e_3(ioaddr, pdev);
3806 break;
3807
3808 case RTL_GIGA_MAC_VER_09:
3809 rtl_hw_start_8102e_2(ioaddr, pdev);
3810 break;
cdf1a608
FR		 3811 }
3812
3813 RTL_W8(Cfg9346, Cfg9346_Unlock);
3814
f0298f81 3815 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 3816
6f0333b8 3817 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3818
3819 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3820
3821 RTL_W16(CPlusCmd, tp->cp_cmd);
3822
3823 RTL_W16(IntrMitigate, 0x0000);
3824
3825 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3826
3827 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3828 rtl_set_rx_tx_config_registers(tp);
3829
3830 RTL_W8(Cfg9346, Cfg9346_Lock);
3831
3832 RTL_R8(IntrMask);
3833
cdf1a608
FR		 3834 rtl_set_rx_mode(dev);
3835
0e485150
FR		 3836 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3837
cdf1a608 3838 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3839
0e485150 3840 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3841}
3842
3843static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3844{
1da177e4
LT		 3845 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3846 return -EINVAL;
3847
3848 dev->mtu = new_mtu;
323bb685 3849 return 0;
1da177e4
LT		 3850}
3851
3852static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3853{
95e0918d 3854 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3855 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3856}
3857
6f0333b8
ED		 3858static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3859 void **data_buff, struct RxDesc *desc)
1da177e4 3860{
48addcc9 3861 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3862 DMA_FROM_DEVICE);
48addcc9 3863
6f0333b8
ED		 3864 kfree(*data_buff);
3865 *data_buff = NULL;
1da177e4
LT		 3866 rtl8169_make_unusable_by_asic(desc);
3867}
3868
3869static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3870{
3871 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3872
3873 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3874}
3875
3876static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3877 u32 rx_buf_sz)
3878{
3879 desc->addr = cpu_to_le64(mapping);
3880 wmb();
3881 rtl8169_mark_to_asic(desc, rx_buf_sz);
3882}
3883
6f0333b8
ED		 3884static inline void *rtl8169_align(void *data)
3885{
3886 return (void *)ALIGN((long)data, 16);
3887}
3888
0ecbe1ca
SG		 3889static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3890 struct RxDesc *desc)
1da177e4 3891{
6f0333b8 3892 void *data;
1da177e4 3893 dma_addr_t mapping;
48addcc9 3894 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 3895 struct net_device *dev = tp->dev;
6f0333b8 3896 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 3897
6f0333b8
ED		 3898 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3899 if (!data)
3900 return NULL;
e9f63f30 3901
6f0333b8
ED		 3902 if (rtl8169_align(data) != data) {
3903 kfree(data);
3904 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3905 if (!data)
3906 return NULL;
3907 }
3eafe507 3908
48addcc9 3909 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 3910 DMA_FROM_DEVICE);
d827d86b
SG		 3911 if (unlikely(dma_mapping_error(d, mapping))) {
3912 if (net_ratelimit())
3913 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 3914 goto err_out;
d827d86b 3915 }
1da177e4
LT		 3916
3917 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 3918 return data;
3eafe507
SG		 3919
3920err_out:
3921 kfree(data);
3922 return NULL;
1da177e4
LT		 3923}
3924
3925static void rtl8169_rx_clear(struct rtl8169_private *tp)
3926{
07d3f51f 3927 unsigned int i;
1da177e4
LT		 3928
3929 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 3930 if (tp->Rx_databuff[i]) {
3931 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 3932 tp->RxDescArray + i);
3933 }
3934 }
3935}
3936
0ecbe1ca 3937static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 3938{
0ecbe1ca
SG		 3939 desc->opts1 |= cpu_to_le32(RingEnd);
3940}
5b0384f4 3941
0ecbe1ca
SG		 3942static int rtl8169_rx_fill(struct rtl8169_private *tp)
3943{
3944 unsigned int i;
1da177e4 3945
0ecbe1ca
SG		 3946 for (i = 0; i < NUM_RX_DESC; i++) {
3947 void *data;
4ae47c2d 3948
6f0333b8 3949 if (tp->Rx_databuff[i])
1da177e4 3950 continue;
bcf0bf90 3951
0ecbe1ca 3952 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 3953 if (!data) {
3954 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 3955 goto err_out;
6f0333b8
ED		 3956 }
3957 tp->Rx_databuff[i] = data;
1da177e4 3958 }
1da177e4 3959
0ecbe1ca
SG		 3960 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3961 return 0;
3962
3963err_out:
3964 rtl8169_rx_clear(tp);
3965 return -ENOMEM;
1da177e4
LT		 3966}
3967
3968static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3969{
3970 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3971}
3972
3973static int rtl8169_init_ring(struct net_device *dev)
3974{
3975 struct rtl8169_private *tp = netdev_priv(dev);
3976
3977 rtl8169_init_ring_indexes(tp);
3978
3979 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 3980 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 3981
0ecbe1ca 3982 return rtl8169_rx_fill(tp);
1da177e4
LT		 3983}
3984
48addcc9 3985static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 3986 struct TxDesc *desc)
3987{
3988 unsigned int len = tx_skb->len;
3989
48addcc9
SG		 3990 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3991
1da177e4
LT		 3992 desc->opts1 = 0x00;
3993 desc->opts2 = 0x00;
3994 desc->addr = 0x00;
3995 tx_skb->len = 0;
3996}
3997
3eafe507
SG		 3998static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3999 unsigned int n)
1da177e4
LT		 4000{
4001 unsigned int i;
4002
3eafe507
SG		 4003 for (i = 0; i < n; i++) {
4004 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4005 struct ring_info *tx_skb = tp->tx_skb + entry;
4006 unsigned int len = tx_skb->len;
4007
4008 if (len) {
4009 struct sk_buff *skb = tx_skb->skb;
4010
48addcc9 4011 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4012 tp->TxDescArray + entry);
4013 if (skb) {
cac4b22f 4014 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4015 dev_kfree_skb(skb);
4016 tx_skb->skb = NULL;
4017 }
1da177e4
LT		 4018 }
4019 }
3eafe507
SG		 4020}
4021
4022static void rtl8169_tx_clear(struct rtl8169_private *tp)
4023{
4024 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4025 tp->cur_tx = tp->dirty_tx = 0;
4026}
4027
c4028958 4028static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4029{
4030 struct rtl8169_private *tp = netdev_priv(dev);
4031
c4028958 4032 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4033 schedule_delayed_work(&tp->task, 4);
4034}
4035
4036static void rtl8169_wait_for_quiescence(struct net_device *dev)
4037{
4038 struct rtl8169_private *tp = netdev_priv(dev);
4039 void __iomem *ioaddr = tp->mmio_addr;
4040
4041 synchronize_irq(dev->irq);
4042
4043 /* Wait for any pending NAPI task to complete */
bea3348e 4044 napi_disable(&tp->napi);
1da177e4
LT		 4045
4046 rtl8169_irq_mask_and_ack(ioaddr);
4047
d1d08d12
DM		 4048 tp->intr_mask = 0xffff;
4049 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4050 napi_enable(&tp->napi);
1da177e4
LT		 4051}
4052
c4028958 4053static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4054{
c4028958
DH		 4055 struct rtl8169_private *tp =
4056 container_of(work, struct rtl8169_private, task.work);
4057 struct net_device *dev = tp->dev;
1da177e4
LT		 4058 int ret;
4059
eb2a021c
FR		 4060 rtnl_lock();
4061
4062 if (!netif_running(dev))
4063 goto out_unlock;
4064
4065 rtl8169_wait_for_quiescence(dev);
4066 rtl8169_close(dev);
1da177e4
LT		 4067
4068 ret = rtl8169_open(dev);
4069 if (unlikely(ret < 0)) {
bf82c189
JP		 4070 if (net_ratelimit())
4071 netif_err(tp, drv, dev,
4072 "reinit failure (status = %d). Rescheduling\n",
4073 ret);
1da177e4
LT		 4074 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4075 }
eb2a021c
FR		 4076
4077out_unlock:
4078 rtnl_unlock();
1da177e4
LT		 4079}
4080
c4028958 4081static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4082{
c4028958
DH		 4083 struct rtl8169_private *tp =
4084 container_of(work, struct rtl8169_private, task.work);
4085 struct net_device *dev = tp->dev;
1da177e4 4086
eb2a021c
FR		 4087 rtnl_lock();
4088
1da177e4 4089 if (!netif_running(dev))
eb2a021c 4090 goto out_unlock;
1da177e4
LT		 4091
4092 rtl8169_wait_for_quiescence(dev);
4093
bea3348e 4094 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4095 rtl8169_tx_clear(tp);
4096
4097 if (tp->dirty_rx == tp->cur_rx) {
4098 rtl8169_init_ring_indexes(tp);
07ce4064 4099 rtl_hw_start(dev);
1da177e4 4100 netif_wake_queue(dev);
cebf8cc7 4101 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4102 } else {
bf82c189
JP		 4103 if (net_ratelimit())
4104 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4105 rtl8169_schedule_work(dev, rtl8169_reset_task);
4106 }
eb2a021c
FR		 4107
4108out_unlock:
4109 rtnl_unlock();
1da177e4
LT		 4110}
4111
4112static void rtl8169_tx_timeout(struct net_device *dev)
4113{
4114 struct rtl8169_private *tp = netdev_priv(dev);
4115
e6de30d6 4116 rtl8169_hw_reset(tp);
1da177e4
LT		 4117
4118 /* Let's wait a bit while any (async) irq lands on */
4119 rtl8169_schedule_work(dev, rtl8169_reset_task);
4120}
4121
4122static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4123 u32 opts1)
4124{
4125 struct skb_shared_info *info = skb_shinfo(skb);
4126 unsigned int cur_frag, entry;
a6343afb 4127 struct TxDesc * uninitialized_var(txd);
48addcc9 4128 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4129
4130 entry = tp->cur_tx;
4131 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4132 skb_frag_t *frag = info->frags + cur_frag;
4133 dma_addr_t mapping;
4134 u32 status, len;
4135 void *addr;
4136
4137 entry = (entry + 1) % NUM_TX_DESC;
4138
4139 txd = tp->TxDescArray + entry;
4140 len = frag->size;
4141 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4142 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4143 if (unlikely(dma_mapping_error(d, mapping))) {
4144 if (net_ratelimit())
4145 netif_err(tp, drv, tp->dev,
4146 "Failed to map TX fragments DMA!\n");
3eafe507 4147 goto err_out;
d827d86b 4148 }
1da177e4
LT		 4149
4150 /* anti gcc 2.95.3 bugware (sic) */
4151 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4152
4153 txd->opts1 = cpu_to_le32(status);
4154 txd->addr = cpu_to_le64(mapping);
4155
4156 tp->tx_skb[entry].len = len;
4157 }
4158
4159 if (cur_frag) {
4160 tp->tx_skb[entry].skb = skb;
4161 txd->opts1 |= cpu_to_le32(LastFrag);
4162 }
4163
4164 return cur_frag;
3eafe507
SG		 4165
4166err_out:
4167 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4168 return -EIO;
1da177e4
LT		 4169}
4170
4171static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4172{
4173 if (dev->features & NETIF_F_TSO) {
7967168c 4174 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4175
4176 if (mss)
4177 return LargeSend | ((mss & MSSMask) << MSSShift);
4178 }
84fa7933 4179 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4180 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4181
4182 if (ip->protocol == IPPROTO_TCP)
4183 return IPCS | TCPCS;
4184 else if (ip->protocol == IPPROTO_UDP)
4185 return IPCS | UDPCS;
4186 WARN_ON(1); /* we need a WARN() */
4187 }
4188 return 0;
4189}
4190
61357325
SH		 4191static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4192 struct net_device *dev)
1da177e4
LT		 4193{
4194 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4195 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4196 struct TxDesc *txd = tp->TxDescArray + entry;
4197 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4198 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4199 dma_addr_t mapping;
4200 u32 status, len;
4201 u32 opts1;
3eafe507 4202 int frags;
5b0384f4 4203
1da177e4 4204 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4205 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4206 goto err_stop_0;
1da177e4
LT		 4207 }
4208
4209 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4210 goto err_stop_0;
4211
4212 len = skb_headlen(skb);
48addcc9 4213 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4214 if (unlikely(dma_mapping_error(d, mapping))) {
4215 if (net_ratelimit())
4216 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4217 goto err_dma_0;
d827d86b 4218 }
3eafe507
SG		 4219
4220 tp->tx_skb[entry].len = len;
4221 txd->addr = cpu_to_le64(mapping);
4222 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4223
4224 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4225
4226 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4227 if (frags < 0)
4228 goto err_dma_1;
4229 else if (frags)
1da177e4 4230 opts1 |= FirstFrag;
3eafe507 4231 else {
1da177e4
LT		 4232 opts1 |= FirstFrag | LastFrag;
4233 tp->tx_skb[entry].skb = skb;
4234 }
4235
1da177e4
LT		 4236 wmb();
4237
4238 /* anti gcc 2.95.3 bugware (sic) */
4239 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4240 txd->opts1 = cpu_to_le32(status);
4241
1da177e4
LT		 4242 tp->cur_tx += frags + 1;
4243
4c020a96 4244 wmb();
1da177e4 4245
275391a4 4246 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4247
4248 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4249 netif_stop_queue(dev);
4250 smp_rmb();
4251 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4252 netif_wake_queue(dev);
4253 }
4254
61357325 4255 return NETDEV_TX_OK;
1da177e4 4256
3eafe507 4257err_dma_1:
48addcc9 4258 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4259err_dma_0:
4260 dev_kfree_skb(skb);
4261 dev->stats.tx_dropped++;
4262 return NETDEV_TX_OK;
4263
4264err_stop_0:
1da177e4 4265 netif_stop_queue(dev);
cebf8cc7 4266 dev->stats.tx_dropped++;
61357325 4267 return NETDEV_TX_BUSY;
1da177e4
LT		 4268}
4269
4270static void rtl8169_pcierr_interrupt(struct net_device *dev)
4271{
4272 struct rtl8169_private *tp = netdev_priv(dev);
4273 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4274 u16 pci_status, pci_cmd;
4275
4276 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4277 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4278
bf82c189
JP		 4279 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4280 pci_cmd, pci_status);
1da177e4
LT		 4281
4282 /*
4283 * The recovery sequence below admits a very elaborated explanation:
4284 * - it seems to work;
d03902b8
FR		 4285 * - I did not see what else could be done;
4286 * - it makes iop3xx happy.
1da177e4
LT		 4287 *
4288 * Feel free to adjust to your needs.
4289 */
a27993f3 4290 if (pdev->broken_parity_status)
d03902b8
FR		 4291 pci_cmd &= ~PCI_COMMAND_PARITY;
4292 else
4293 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4294
4295 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4296
4297 pci_write_config_word(pdev, PCI_STATUS,
4298 pci_status & (PCI_STATUS_DETECTED_PARITY |
4299 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4300 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4301
4302 /* The infamous DAC f*ckup only happens at boot time */
4303 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4304 void __iomem *ioaddr = tp->mmio_addr;
4305
bf82c189 4306 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4307 tp->cp_cmd &= ~PCIDAC;
4308 RTL_W16(CPlusCmd, tp->cp_cmd);
4309 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4310 }
4311
e6de30d6 4312 rtl8169_hw_reset(tp);
d03902b8
FR		 4313
4314 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4315}
4316
07d3f51f
FR		 4317static void rtl8169_tx_interrupt(struct net_device *dev,
4318 struct rtl8169_private *tp,
4319 void __iomem *ioaddr)
1da177e4
LT		 4320{
4321 unsigned int dirty_tx, tx_left;
4322
1da177e4
LT		 4323 dirty_tx = tp->dirty_tx;
4324 smp_rmb();
4325 tx_left = tp->cur_tx - dirty_tx;
4326
4327 while (tx_left > 0) {
4328 unsigned int entry = dirty_tx % NUM_TX_DESC;
4329 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4330 u32 status;
4331
4332 rmb();
4333 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4334 if (status & DescOwn)
4335 break;
4336
48addcc9
SG		 4337 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4338 tp->TxDescArray + entry);
1da177e4 4339 if (status & LastFrag) {
cac4b22f
SG		 4340 dev->stats.tx_packets++;
4341 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4342 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4343 tx_skb->skb = NULL;
4344 }
4345 dirty_tx++;
4346 tx_left--;
4347 }
4348
4349 if (tp->dirty_tx != dirty_tx) {
4350 tp->dirty_tx = dirty_tx;
4351 smp_wmb();
4352 if (netif_queue_stopped(dev) &&
4353 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4354 netif_wake_queue(dev);
4355 }
d78ae2dc
FR		 4356 /*
4357 * 8168 hack: TxPoll requests are lost when the Tx packets are
4358 * too close. Let's kick an extra TxPoll request when a burst
4359 * of start_xmit activity is detected (if it is not detected,
4360 * it is slow enough). -- FR
4361 */
4362 smp_rmb();
4363 if (tp->cur_tx != dirty_tx)
4364 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4365 }
4366}
4367
126fa4b9
FR		 4368static inline int rtl8169_fragmented_frame(u32 status)
4369{
4370 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4371}
4372
adea1ac7 4373static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4374{
1da177e4
LT		 4375 u32 status = opts1 & RxProtoMask;
4376
4377 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4378 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4379 skb->ip_summed = CHECKSUM_UNNECESSARY;
4380 else
bc8acf2c 4381 skb_checksum_none_assert(skb);
1da177e4
LT		 4382}
4383
6f0333b8
ED		 4384static struct sk_buff *rtl8169_try_rx_copy(void *data,
4385 struct rtl8169_private *tp,
4386 int pkt_size,
4387 dma_addr_t addr)
1da177e4 4388{
b449655f 4389 struct sk_buff *skb;
48addcc9 4390 struct device *d = &tp->pci_dev->dev;
b449655f 4391
6f0333b8 4392 data = rtl8169_align(data);
48addcc9 4393 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4394 prefetch(data);
4395 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4396 if (skb)
4397 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4398 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4399
6f0333b8 4400 return skb;
1da177e4
LT		 4401}
4402
630b943c
ED		 4403/*
4404 * Warning : rtl8169_rx_interrupt() might be called :
4405 * 1) from NAPI (softirq) context
4406 * (polling = 1 : we should call netif_receive_skb())
4407 * 2) from process context (rtl8169_reset_task())
4408 * (polling = 0 : we must call netif_rx() instead)
4409 */
07d3f51f
FR		 4410static int rtl8169_rx_interrupt(struct net_device *dev,
4411 struct rtl8169_private *tp,
bea3348e 4412 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4413{
4414 unsigned int cur_rx, rx_left;
6f0333b8 4415 unsigned int count;
630b943c 4416 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4417
1da177e4
LT		 4418 cur_rx = tp->cur_rx;
4419 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4420 rx_left = min(rx_left, budget);
1da177e4 4421
4dcb7d33 4422 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4423 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4424 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4425 u32 status;
4426
4427 rmb();
126fa4b9 4428 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4429
4430 if (status & DescOwn)
4431 break;
4dcb7d33 4432 if (unlikely(status & RxRES)) {
bf82c189
JP		 4433 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4434 status);
cebf8cc7 4435 dev->stats.rx_errors++;
1da177e4 4436 if (status & (RxRWT | RxRUNT))
cebf8cc7 4437 dev->stats.rx_length_errors++;
1da177e4 4438 if (status & RxCRC)
cebf8cc7 4439 dev->stats.rx_crc_errors++;
9dccf611
FR		 4440 if (status & RxFOVF) {
4441 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4442 dev->stats.rx_fifo_errors++;
9dccf611 4443 }
6f0333b8 4444 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4445 } else {
6f0333b8 4446 struct sk_buff *skb;
b449655f 4447 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4448 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4449
126fa4b9
FR		 4450 /*
4451 * The driver does not support incoming fragmented
4452 * frames. They are seen as a symptom of over-mtu
4453 * sized frames.
4454 */
4455 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4456 dev->stats.rx_dropped++;
4457 dev->stats.rx_length_errors++;
6f0333b8 4458 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4459 continue;
126fa4b9
FR		 4460 }
4461
6f0333b8
ED		 4462 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4463 tp, pkt_size, addr);
4464 rtl8169_mark_to_asic(desc, rx_buf_sz);
4465 if (!skb) {
4466 dev->stats.rx_dropped++;
4467 continue;
1da177e4
LT		 4468 }
4469
adea1ac7 4470 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4471 skb_put(skb, pkt_size);
4472 skb->protocol = eth_type_trans(skb, dev);
4473
630b943c
ED		 4474 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4475 if (likely(polling))
2edae08e 4476 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4477 else
4478 netif_rx(skb);
4479 }
1da177e4 4480
cebf8cc7
FR		 4481 dev->stats.rx_bytes += pkt_size;
4482 dev->stats.rx_packets++;
1da177e4 4483 }
6dccd16b
FR		 4484
4485 /* Work around for AMD plateform. */
95e0918d 4486 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4487 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4488 desc->opts2 = 0;
4489 cur_rx++;
4490 }
1da177e4
LT		 4491 }
4492
4493 count = cur_rx - tp->cur_rx;
4494 tp->cur_rx = cur_rx;
4495
6f0333b8 4496 tp->dirty_rx += count;
1da177e4
LT		 4497
4498 return count;
4499}
4500
07d3f51f 4501static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4502{
07d3f51f 4503 struct net_device *dev = dev_instance;
1da177e4 4504 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4505 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4506 int handled = 0;
865c652d 4507 int status;
1da177e4 4508
f11a377b
DD		 4509 /* loop handling interrupts until we have no new ones or
4510 * we hit a invalid/hotplug case.
4511 */
865c652d 4512 status = RTL_R16(IntrStatus);
f11a377b
DD		 4513 while (status && status != 0xffff) {
4514 handled = 1;
1da177e4 4515
f11a377b
DD		 4516 /* Handle all of the error cases first. These will reset
4517 * the chip, so just exit the loop.
4518 */
4519 if (unlikely(!netif_running(dev))) {
4520 rtl8169_asic_down(ioaddr);
4521 break;
4522 }
1da177e4 4523
f11a377b 4524 /* Work around for rx fifo overflow */
53f57357 4525 if (unlikely(status & RxFIFOOver) &&
4526 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
f11a377b
DD		 4527 netif_stop_queue(dev);
4528 rtl8169_tx_timeout(dev);
4529 break;
4530 }
1da177e4 4531
f11a377b
DD		 4532 if (unlikely(status & SYSErr)) {
4533 rtl8169_pcierr_interrupt(dev);
4534 break;
4535 }
1da177e4 4536
f11a377b 4537 if (status & LinkChg)
e4fbce74 4538 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4539
f11a377b
DD		 4540 /* We need to see the lastest version of tp->intr_mask to
4541 * avoid ignoring an MSI interrupt and having to wait for
4542 * another event which may never come.
4543 */
4544 smp_rmb();
4545 if (status & tp->intr_mask & tp->napi_event) {
4546 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4547 tp->intr_mask = ~tp->napi_event;
4548
4549 if (likely(napi_schedule_prep(&tp->napi)))
4550 __napi_schedule(&tp->napi);
bf82c189
JP		 4551 else
4552 netif_info(tp, intr, dev,
4553 "interrupt %04x in poll\n", status);
f11a377b 4554 }
1da177e4 4555
f11a377b
DD		 4556 /* We only get a new MSI interrupt when all active irq
4557 * sources on the chip have been acknowledged. So, ack
4558 * everything we've seen and check if new sources have become
4559 * active to avoid blocking all interrupts from the chip.
4560 */
4561 RTL_W16(IntrStatus,
4562 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4563 status = RTL_R16(IntrStatus);
865c652d 4564 }
1da177e4 4565
1da177e4
LT		 4566 return IRQ_RETVAL(handled);
4567}
4568
bea3348e 4569static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4570{
bea3348e
SH		 4571 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4572 struct net_device *dev = tp->dev;
1da177e4 4573 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4574 int work_done;
1da177e4 4575
bea3348e 4576 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4577 rtl8169_tx_interrupt(dev, tp, ioaddr);
4578
bea3348e 4579 if (work_done < budget) {
288379f0 4580 napi_complete(napi);
f11a377b
DD		 4581
4582 /* We need for force the visibility of tp->intr_mask
4583 * for other CPUs, as we can loose an MSI interrupt
4584 * and potentially wait for a retransmit timeout if we don't.
4585 * The posted write to IntrMask is safe, as it will
4586 * eventually make it to the chip and we won't loose anything
4587 * until it does.
1da177e4 4588 */
f11a377b 4589 tp->intr_mask = 0xffff;
4c020a96 4590 wmb();
0e485150 4591 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4592 }
4593
bea3348e 4594 return work_done;
1da177e4 4595}
1da177e4 4596
523a6094
FR		 4597static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4598{
4599 struct rtl8169_private *tp = netdev_priv(dev);
4600
4601 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4602 return;
4603
4604 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4605 RTL_W32(RxMissed, 0);
4606}
4607
1da177e4
LT		 4608static void rtl8169_down(struct net_device *dev)
4609{
4610 struct rtl8169_private *tp = netdev_priv(dev);
4611 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4612
4613 rtl8169_delete_timer(dev);
4614
4615 netif_stop_queue(dev);
4616
93dd79e8 4617 napi_disable(&tp->napi);
93dd79e8 4618
1da177e4
LT		 4619 spin_lock_irq(&tp->lock);
4620
4621 rtl8169_asic_down(ioaddr);
323bb685
SG		 4622 /*
4623 * At this point device interrupts can not be enabled in any function,
4624 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4625 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4626 */
523a6094 4627 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4628
4629 spin_unlock_irq(&tp->lock);
4630
4631 synchronize_irq(dev->irq);
4632
1da177e4 4633 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4634 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4635
1da177e4
LT		 4636 rtl8169_tx_clear(tp);
4637
4638 rtl8169_rx_clear(tp);
065c27c1 4639
4640 rtl_pll_power_down(tp);
1da177e4
LT		 4641}
4642
4643static int rtl8169_close(struct net_device *dev)
4644{
4645 struct rtl8169_private *tp = netdev_priv(dev);
4646 struct pci_dev *pdev = tp->pci_dev;
4647
e1759441
RW		 4648 pm_runtime_get_sync(&pdev->dev);
4649
355423d0
IV		 4650 /* update counters before going down */
4651 rtl8169_update_counters(dev);
4652
1da177e4
LT		 4653 rtl8169_down(dev);
4654
4655 free_irq(dev->irq, dev);
4656
82553bb6
SG		 4657 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4658 tp->RxPhyAddr);
4659 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4660 tp->TxPhyAddr);
1da177e4
LT		 4661 tp->TxDescArray = NULL;
4662 tp->RxDescArray = NULL;
4663
e1759441
RW		 4664 pm_runtime_put_sync(&pdev->dev);
4665
1da177e4
LT		 4666 return 0;
4667}
4668
07ce4064 4669static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4670{
4671 struct rtl8169_private *tp = netdev_priv(dev);
4672 void __iomem *ioaddr = tp->mmio_addr;
4673 unsigned long flags;
4674 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4675 int rx_mode;
1da177e4
LT		 4676 u32 tmp = 0;
4677
4678 if (dev->flags & IFF_PROMISC) {
4679 /* Unconditionally log net taps. */
bf82c189 4680 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4681 rx_mode =
4682 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4683 AcceptAllPhys;
4684 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4685 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4686 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4687 /* Too many to filter perfectly -- accept all multicasts. */
4688 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4689 mc_filter[1] = mc_filter[0] = 0xffffffff;
4690 } else {
22bedad3 4691 struct netdev_hw_addr *ha;
07d3f51f 4692
1da177e4
LT		 4693 rx_mode = AcceptBroadcast | AcceptMyPhys;
4694 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4695 netdev_for_each_mc_addr(ha, dev) {
4696 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4697 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4698 rx_mode |= AcceptMulticast;
4699 }
4700 }
4701
4702 spin_lock_irqsave(&tp->lock, flags);
4703
4704 tmp = rtl8169_rx_config | rx_mode |
4705 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4706
f887cce8 4707 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4708 u32 data = mc_filter[0];
4709
4710 mc_filter[0] = swab32(mc_filter[1]);
4711 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4712 }
4713
1da177e4 4714 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4715 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4716
57a9f236
FR		 4717 RTL_W32(RxConfig, tmp);
4718
1da177e4
LT		 4719 spin_unlock_irqrestore(&tp->lock, flags);
4720}
4721
4722/**
4723 * rtl8169_get_stats - Get rtl8169 read/write statistics
4724 * @dev: The Ethernet Device to get statistics for
4725 *
4726 * Get TX/RX statistics for rtl8169
4727 */
4728static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4729{
4730 struct rtl8169_private *tp = netdev_priv(dev);
4731 void __iomem *ioaddr = tp->mmio_addr;
4732 unsigned long flags;
4733
4734 if (netif_running(dev)) {
4735 spin_lock_irqsave(&tp->lock, flags);
523a6094 4736 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4737 spin_unlock_irqrestore(&tp->lock, flags);
4738 }
5b0384f4 4739
cebf8cc7 4740 return &dev->stats;
1da177e4
LT		 4741}
4742
861ab440 4743static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4744{
065c27c1 4745 struct rtl8169_private *tp = netdev_priv(dev);
4746
5d06a99f 4747 if (!netif_running(dev))
861ab440 4748 return;
5d06a99f 4749
065c27c1 4750 rtl_pll_power_down(tp);
4751
5d06a99f
FR		 4752 netif_device_detach(dev);
4753 netif_stop_queue(dev);
861ab440
RW		 4754}
4755
4756#ifdef CONFIG_PM
4757
4758static int rtl8169_suspend(struct device *device)
4759{
4760 struct pci_dev *pdev = to_pci_dev(device);
4761 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4762
861ab440 4763 rtl8169_net_suspend(dev);
1371fa6d 4764
5d06a99f
FR		 4765 return 0;
4766}
4767
e1759441
RW		 4768static void __rtl8169_resume(struct net_device *dev)
4769{
065c27c1 4770 struct rtl8169_private *tp = netdev_priv(dev);
4771
e1759441 4772 netif_device_attach(dev);
065c27c1 4773
4774 rtl_pll_power_up(tp);
4775
e1759441
RW		 4776 rtl8169_schedule_work(dev, rtl8169_reset_task);
4777}
4778
861ab440 4779static int rtl8169_resume(struct device *device)
5d06a99f 4780{
861ab440 4781 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4782 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4783 struct rtl8169_private *tp = netdev_priv(dev);
4784
4785 rtl8169_init_phy(dev, tp);
5d06a99f 4786
e1759441
RW		 4787 if (netif_running(dev))
4788 __rtl8169_resume(dev);
5d06a99f 4789
e1759441
RW		 4790 return 0;
4791}
4792
4793static int rtl8169_runtime_suspend(struct device *device)
4794{
4795 struct pci_dev *pdev = to_pci_dev(device);
4796 struct net_device *dev = pci_get_drvdata(pdev);
4797 struct rtl8169_private *tp = netdev_priv(dev);
4798
4799 if (!tp->TxDescArray)
4800 return 0;
4801
4802 spin_lock_irq(&tp->lock);
4803 tp->saved_wolopts = __rtl8169_get_wol(tp);
4804 __rtl8169_set_wol(tp, WAKE_ANY);
4805 spin_unlock_irq(&tp->lock);
4806
4807 rtl8169_net_suspend(dev);
4808
4809 return 0;
4810}
4811
4812static int rtl8169_runtime_resume(struct device *device)
4813{
4814 struct pci_dev *pdev = to_pci_dev(device);
4815 struct net_device *dev = pci_get_drvdata(pdev);
4816 struct rtl8169_private *tp = netdev_priv(dev);
4817
4818 if (!tp->TxDescArray)
4819 return 0;
4820
4821 spin_lock_irq(&tp->lock);
4822 __rtl8169_set_wol(tp, tp->saved_wolopts);
4823 tp->saved_wolopts = 0;
4824 spin_unlock_irq(&tp->lock);
4825
fccec10b
SG		 4826 rtl8169_init_phy(dev, tp);
4827
e1759441 4828 __rtl8169_resume(dev);
5d06a99f 4829
5d06a99f
FR		 4830 return 0;
4831}
4832
e1759441
RW		 4833static int rtl8169_runtime_idle(struct device *device)
4834{
4835 struct pci_dev *pdev = to_pci_dev(device);
4836 struct net_device *dev = pci_get_drvdata(pdev);
4837 struct rtl8169_private *tp = netdev_priv(dev);
4838
e4fbce74 4839 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4840}
4841
47145210 4842static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4843 .suspend = rtl8169_suspend,
4844 .resume = rtl8169_resume,
4845 .freeze = rtl8169_suspend,
4846 .thaw = rtl8169_resume,
4847 .poweroff = rtl8169_suspend,
4848 .restore = rtl8169_resume,
e1759441
RW		 4849 .runtime_suspend = rtl8169_runtime_suspend,
4850 .runtime_resume = rtl8169_runtime_resume,
4851 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4852};
4853
4854#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4855
4856#else /* !CONFIG_PM */
4857
4858#define RTL8169_PM_OPS NULL
4859
4860#endif /* !CONFIG_PM */
4861
1765f95d
FR		 4862static void rtl_shutdown(struct pci_dev *pdev)
4863{
861ab440 4864 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4865 struct rtl8169_private *tp = netdev_priv(dev);
4866 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4867
4868 rtl8169_net_suspend(dev);
1765f95d 4869
cc098dc7
IV		 4870 /* restore original MAC address */
4871 rtl_rar_set(tp, dev->perm_addr);
4872
4bb3f522 4873 spin_lock_irq(&tp->lock);
4874
4875 rtl8169_asic_down(ioaddr);
4876
4877 spin_unlock_irq(&tp->lock);
4878
861ab440 4879 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4880 /* WoL fails with some 8168 when the receiver is disabled. */
4881 if (tp->features & RTL_FEATURE_WOL) {
4882 pci_clear_master(pdev);
4883
4884 RTL_W8(ChipCmd, CmdRxEnb);
4885 /* PCI commit */
4886 RTL_R8(ChipCmd);
4887 }
4888
861ab440
RW		 4889 pci_wake_from_d3(pdev, true);
4890 pci_set_power_state(pdev, PCI_D3hot);
4891 }
4892}
5d06a99f 4893
1da177e4
LT		 4894static struct pci_driver rtl8169_pci_driver = {
4895 .name = MODULENAME,
4896 .id_table = rtl8169_pci_tbl,
4897 .probe = rtl8169_init_one,
4898 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4899 .shutdown = rtl_shutdown,
861ab440 4900 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4901};
4902
07d3f51f 4903static int __init rtl8169_init_module(void)
1da177e4 4904{
29917620 4905 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4906}
4907
07d3f51f 4908static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4909{
4910 pci_unregister_driver(&rtl8169_pci_driver);
4911}
4912
4913module_init(rtl8169_init_module);
4914module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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