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ethtool: cosmetic: Use ethtool ethtool_cmd_speed API
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
1da177e4 29
99f252b0 30#include <asm/system.h>
1da177e4
LT		 31#include <asm/io.h>
32#include <asm/irq.h>
33
865c652d 34#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 35#define MODULENAME "r8169"
36#define PFX MODULENAME ": "
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 40#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 42#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 43
1da177e4
LT		 44#ifdef RTL8169_DEBUG
45#define assert(expr) \
5b0384f4
FR		 46 if (!(expr)) { \
47 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 48 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 49 }
06fa7358
JP		 50#define dprintk(fmt, args...) \
51 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 52#else
53#define assert(expr) do {} while (0)
54#define dprintk(fmt, args...) do {} while (0)
55#endif /* RTL8169_DEBUG */
56
b57b7e5a 57#define R8169_MSG_DEFAULT \
f0e837d9 58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 59
1da177e4
LT		 60#define TX_BUFFS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
62
1da177e4
LT		 63/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
64 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 65static const int multicast_filter_limit = 32;
1da177e4
LT		 66
67/* MAC address length */
68#define MAC_ADDR_LEN 6
69
9c14ceaf 70#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 71#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
72#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
73#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 74#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
75#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76
77#define R8169_REGS_SIZE 256
78#define R8169_NAPI_WEIGHT 64
79#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
80#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
81#define RX_BUF_SIZE 1536 /* Rx Buffer size */
82#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
83#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
84
85#define RTL8169_TX_TIMEOUT (6*HZ)
86#define RTL8169_PHY_TIMEOUT (10*HZ)
87
ea8dbdd1 88#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
89#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 90#define RTL_EEPROM_SIG_ADDR 0x0000
91
1da177e4
LT		 92/* write/read MMIO register */
93#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
94#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
95#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
96#define RTL_R8(reg) readb (ioaddr + (reg))
97#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 98#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 99
100enum mac_version {
f21b75e9 101 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 102 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
103 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
104 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
105 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
106 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 107 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 108 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
109 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
110 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
111 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 112 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 113 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
114 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
115 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
116 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
117 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
118 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
119 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
120 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 121 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 122 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 123 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 124 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 125 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 126 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
127 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 128 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
129 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
5a5e4443
HW		 130 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
131 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
4804b3b3 132 RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP
01dc7fec 133 RTL_GIGA_MAC_VER_32 = 0x20, // 8168E
134 RTL_GIGA_MAC_VER_33 = 0x21, // 8168E
1da177e4
LT		 135};
136
2b7b4318
FR		 137enum rtl_tx_desc_version {
138 RTL_TD_0 = 0,
139 RTL_TD_1 = 1,
140};
141
142#define _R(NAME,MAC,TD) \
143 { .name = NAME, .mac_version = MAC, .txd_version = TD }
1da177e4 144
3c6bee1d 145static const struct {
1da177e4
LT		 146 const char *name;
147 u8 mac_version;
2b7b4318 148 enum rtl_tx_desc_version txd_version;
1da177e4 149} rtl_chip_info[] = {
2b7b4318
FR		 150 _R("RTL8169", RTL_GIGA_MAC_VER_01, RTL_TD_0), // 8169
151 _R("RTL8169s", RTL_GIGA_MAC_VER_02, RTL_TD_0), // 8169S
152 _R("RTL8110s", RTL_GIGA_MAC_VER_03, RTL_TD_0), // 8110S
153 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, RTL_TD_0), // 8169SB
154 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, RTL_TD_0), // 8110SCd
155 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, RTL_TD_0), // 8110SCe
156 _R("RTL8102e", RTL_GIGA_MAC_VER_07, RTL_TD_1), // PCI-E
157 _R("RTL8102e", RTL_GIGA_MAC_VER_08, RTL_TD_1), // PCI-E
158 _R("RTL8102e", RTL_GIGA_MAC_VER_09, RTL_TD_1), // PCI-E
159 _R("RTL8101e", RTL_GIGA_MAC_VER_10, RTL_TD_0), // PCI-E
160 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, RTL_TD_0), // PCI-E
161 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, RTL_TD_0), // PCI-E
162 _R("RTL8101e", RTL_GIGA_MAC_VER_13, RTL_TD_0), // PCI-E 8139
163 _R("RTL8100e", RTL_GIGA_MAC_VER_14, RTL_TD_0), // PCI-E 8139
164 _R("RTL8100e", RTL_GIGA_MAC_VER_15, RTL_TD_0), // PCI-E 8139
165 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, RTL_TD_0), // PCI-E
166 _R("RTL8101e", RTL_GIGA_MAC_VER_16, RTL_TD_0), // PCI-E
167 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, RTL_TD_1), // PCI-E
168 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, RTL_TD_1), // PCI-E
169 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, RTL_TD_1), // PCI-E
170 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, RTL_TD_1), // PCI-E
171 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, RTL_TD_1), // PCI-E
172 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, RTL_TD_1), // PCI-E
173 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, RTL_TD_1), // PCI-E
174 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, RTL_TD_1), // PCI-E
175 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, RTL_TD_1), // PCI-E
176 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, RTL_TD_1), // PCI-E
177 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, RTL_TD_1), // PCI-E
178 _R("RTL8105e", RTL_GIGA_MAC_VER_29, RTL_TD_1), // PCI-E
179 _R("RTL8105e", RTL_GIGA_MAC_VER_30, RTL_TD_1), // PCI-E
180 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, RTL_TD_1), // PCI-E
181 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, RTL_TD_1), // PCI-E
182 _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, RTL_TD_1) // PCI-E
1da177e4
LT		 183};
184#undef _R
185
953a12cc
FR		 186static const struct rtl_firmware_info {
187 int mac_version;
188 const char *fw_name;
189} rtl_firmware_infos[] = {
190 { .mac_version = RTL_GIGA_MAC_VER_25, .fw_name = FIRMWARE_8168D_1 },
191 { .mac_version = RTL_GIGA_MAC_VER_26, .fw_name = FIRMWARE_8168D_2 },
192 { .mac_version = RTL_GIGA_MAC_VER_29, .fw_name = FIRMWARE_8105E_1 },
2bd93d7a 193 { .mac_version = RTL_GIGA_MAC_VER_30, .fw_name = FIRMWARE_8105E_1 },
15ecd039
FR		 194 { .mac_version = RTL_GIGA_MAC_VER_32, .fw_name = FIRMWARE_8168E_1 },
195 { .mac_version = RTL_GIGA_MAC_VER_33, .fw_name = FIRMWARE_8168E_2 }
953a12cc
FR		 196};
197
bcf0bf90
FR		 198enum cfg_version {
199 RTL_CFG_0 = 0x00,
200 RTL_CFG_1,
201 RTL_CFG_2
202};
203
07ce4064
FR		 204static void rtl_hw_start_8169(struct net_device *);
205static void rtl_hw_start_8168(struct net_device *);
206static void rtl_hw_start_8101(struct net_device *);
207
a3aa1884 208static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 209 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 210 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 211 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 212 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 213 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
214 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 215 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 216 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
217 { PCI_VENDOR_ID_LINKSYS, 0x1032,
218 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 219 { 0x0001, 0x8168,
220 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 221 {0,},
222};
223
224MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
225
6f0333b8 226static int rx_buf_sz = 16383;
4300e8c7 227static int use_dac;
b57b7e5a
SH		 228static struct {
229 u32 msg_enable;
230} debug = { -1 };
1da177e4 231
07d3f51f
FR		 232enum rtl_registers {
233 MAC0 = 0, /* Ethernet hardware address. */
773d2021 234 MAC4 = 4,
07d3f51f
FR		 235 MAR0 = 8, /* Multicast filter. */
236 CounterAddrLow = 0x10,
237 CounterAddrHigh = 0x14,
238 TxDescStartAddrLow = 0x20,
239 TxDescStartAddrHigh = 0x24,
240 TxHDescStartAddrLow = 0x28,
241 TxHDescStartAddrHigh = 0x2c,
242 FLASH = 0x30,
243 ERSR = 0x36,
244 ChipCmd = 0x37,
245 TxPoll = 0x38,
246 IntrMask = 0x3c,
247 IntrStatus = 0x3e,
248 TxConfig = 0x40,
249 RxConfig = 0x44,
2b7b4318
FR		 250
251#define RTL_RX_CONFIG_MASK 0xff7e1880u
252
07d3f51f
FR		 253 RxMissed = 0x4c,
254 Cfg9346 = 0x50,
255 Config0 = 0x51,
256 Config1 = 0x52,
257 Config2 = 0x53,
258 Config3 = 0x54,
259 Config4 = 0x55,
260 Config5 = 0x56,
261 MultiIntr = 0x5c,
262 PHYAR = 0x60,
07d3f51f
FR		 263 PHYstatus = 0x6c,
264 RxMaxSize = 0xda,
265 CPlusCmd = 0xe0,
266 IntrMitigate = 0xe2,
267 RxDescAddrLow = 0xe4,
268 RxDescAddrHigh = 0xe8,
f0298f81 269 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
270
271#define NoEarlyTx 0x3f /* Max value : no early transmit. */
272
273 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
274
275#define TxPacketMax (8064 >> 7)
276
07d3f51f
FR		 277 FuncEvent = 0xf0,
278 FuncEventMask = 0xf4,
279 FuncPresetState = 0xf8,
280 FuncForceEvent = 0xfc,
1da177e4
LT		 281};
282
f162a5d1
FR		 283enum rtl8110_registers {
284 TBICSR = 0x64,
285 TBI_ANAR = 0x68,
286 TBI_LPAR = 0x6a,
287};
288
289enum rtl8168_8101_registers {
290 CSIDR = 0x64,
291 CSIAR = 0x68,
292#define CSIAR_FLAG 0x80000000
293#define CSIAR_WRITE_CMD 0x80000000
294#define CSIAR_BYTE_ENABLE 0x0f
295#define CSIAR_BYTE_ENABLE_SHIFT 12
296#define CSIAR_ADDR_MASK 0x0fff
065c27c1 297 PMCH = 0x6f,
f162a5d1
FR		 298 EPHYAR = 0x80,
299#define EPHYAR_FLAG 0x80000000
300#define EPHYAR_WRITE_CMD 0x80000000
301#define EPHYAR_REG_MASK 0x1f
302#define EPHYAR_REG_SHIFT 16
303#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 304 DLLPR = 0xd0,
305#define PM_SWITCH (1 << 6)
f162a5d1
FR		 306 DBG_REG = 0xd1,
307#define FIX_NAK_1 (1 << 4)
308#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 309 TWSI = 0xd2,
310 MCU = 0xd3,
311#define EN_NDP (1 << 3)
312#define EN_OOB_RESET (1 << 2)
daf9df6d 313 EFUSEAR = 0xdc,
314#define EFUSEAR_FLAG 0x80000000
315#define EFUSEAR_WRITE_CMD 0x80000000
316#define EFUSEAR_READ_CMD 0x00000000
317#define EFUSEAR_REG_MASK 0x03ff
318#define EFUSEAR_REG_SHIFT 8
319#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 320};
321
c0e45c1c 322enum rtl8168_registers {
b646d900 323 ERIDR = 0x70,
324 ERIAR = 0x74,
325#define ERIAR_FLAG 0x80000000
326#define ERIAR_WRITE_CMD 0x80000000
327#define ERIAR_READ_CMD 0x00000000
328#define ERIAR_ADDR_BYTE_ALIGN 4
329#define ERIAR_EXGMAC 0
330#define ERIAR_MSIX 1
331#define ERIAR_ASF 2
332#define ERIAR_TYPE_SHIFT 16
333#define ERIAR_BYTEEN 0x0f
334#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 335 EPHY_RXER_NUM = 0x7c,
336 OCPDR = 0xb0, /* OCP GPHY access */
337#define OCPDR_WRITE_CMD 0x80000000
338#define OCPDR_READ_CMD 0x00000000
339#define OCPDR_REG_MASK 0x7f
340#define OCPDR_GPHY_REG_SHIFT 16
341#define OCPDR_DATA_MASK 0xffff
342 OCPAR = 0xb4,
343#define OCPAR_FLAG 0x80000000
344#define OCPAR_GPHY_WRITE_CMD 0x8000f060
345#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 346 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
347 MISC = 0xf0, /* 8168e only. */
348 txpla_rst = (1 << 29)
c0e45c1c 349};
350
07d3f51f 351enum rtl_register_content {
1da177e4 352 /* InterruptStatusBits */
07d3f51f
FR		 353 SYSErr = 0x8000,
354 PCSTimeout = 0x4000,
355 SWInt = 0x0100,
356 TxDescUnavail = 0x0080,
357 RxFIFOOver = 0x0040,
358 LinkChg = 0x0020,
359 RxOverflow = 0x0010,
360 TxErr = 0x0008,
361 TxOK = 0x0004,
362 RxErr = 0x0002,
363 RxOK = 0x0001,
1da177e4
LT		 364
365 /* RxStatusDesc */
9dccf611
FR		 366 RxFOVF = (1 << 23),
367 RxRWT = (1 << 22),
368 RxRES = (1 << 21),
369 RxRUNT = (1 << 20),
370 RxCRC = (1 << 19),
1da177e4
LT		 371
372 /* ChipCmdBits */
07d3f51f
FR		 373 CmdReset = 0x10,
374 CmdRxEnb = 0x08,
375 CmdTxEnb = 0x04,
376 RxBufEmpty = 0x01,
1da177e4 377
275391a4
FR		 378 /* TXPoll register p.5 */
379 HPQ = 0x80, /* Poll cmd on the high prio queue */
380 NPQ = 0x40, /* Poll cmd on the low prio queue */
381 FSWInt = 0x01, /* Forced software interrupt */
382
1da177e4 383 /* Cfg9346Bits */
07d3f51f
FR		 384 Cfg9346_Lock = 0x00,
385 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 386
387 /* rx_mode_bits */
07d3f51f
FR		 388 AcceptErr = 0x20,
389 AcceptRunt = 0x10,
390 AcceptBroadcast = 0x08,
391 AcceptMulticast = 0x04,
392 AcceptMyPhys = 0x02,
393 AcceptAllPhys = 0x01,
1da177e4
LT		 394
395 /* RxConfigBits */
07d3f51f
FR		 396 RxCfgFIFOShift = 13,
397 RxCfgDMAShift = 8,
1da177e4
LT		 398
399 /* TxConfigBits */
400 TxInterFrameGapShift = 24,
401 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
402
5d06a99f 403 /* Config1 register p.24 */
f162a5d1
FR		 404 LEDS1 = (1 << 7),
405 LEDS0 = (1 << 6),
fbac58fc 406 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 407 Speed_down = (1 << 4),
408 MEMMAP = (1 << 3),
409 IOMAP = (1 << 2),
410 VPD = (1 << 1),
5d06a99f
FR		 411 PMEnable = (1 << 0), /* Power Management Enable */
412
6dccd16b
FR		 413 /* Config2 register p. 25 */
414 PCI_Clock_66MHz = 0x01,
415 PCI_Clock_33MHz = 0x00,
416
61a4dcc2
FR		 417 /* Config3 register p.25 */
418 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
419 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 420 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 421
5d06a99f 422 /* Config5 register p.27 */
61a4dcc2
FR		 423 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
424 MWF = (1 << 5), /* Accept Multicast wakeup frame */
425 UWF = (1 << 4), /* Accept Unicast wakeup frame */
01dc7fec 426 spi_en = (1 << 3),
61a4dcc2 427 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 428 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
429
1da177e4
LT		 430 /* TBICSR p.28 */
431 TBIReset = 0x80000000,
432 TBILoopback = 0x40000000,
433 TBINwEnable = 0x20000000,
434 TBINwRestart = 0x10000000,
435 TBILinkOk = 0x02000000,
436 TBINwComplete = 0x01000000,
437
438 /* CPlusCmd p.31 */
f162a5d1
FR		 439 EnableBist = (1 << 15), // 8168 8101
440 Mac_dbgo_oe = (1 << 14), // 8168 8101
441 Normal_mode = (1 << 13), // unused
442 Force_half_dup = (1 << 12), // 8168 8101
443 Force_rxflow_en = (1 << 11), // 8168 8101
444 Force_txflow_en = (1 << 10), // 8168 8101
445 Cxpl_dbg_sel = (1 << 9), // 8168 8101
446 ASF = (1 << 8), // 8168 8101
447 PktCntrDisable = (1 << 7), // 8168 8101
448 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 449 RxVlan = (1 << 6),
450 RxChkSum = (1 << 5),
451 PCIDAC = (1 << 4),
452 PCIMulRW = (1 << 3),
0e485150
FR		 453 INTT_0 = 0x0000, // 8168
454 INTT_1 = 0x0001, // 8168
455 INTT_2 = 0x0002, // 8168
456 INTT_3 = 0x0003, // 8168
1da177e4
LT		 457
458 /* rtl8169_PHYstatus */
07d3f51f
FR		 459 TBI_Enable = 0x80,
460 TxFlowCtrl = 0x40,
461 RxFlowCtrl = 0x20,
462 _1000bpsF = 0x10,
463 _100bps = 0x08,
464 _10bps = 0x04,
465 LinkStatus = 0x02,
466 FullDup = 0x01,
1da177e4 467
1da177e4 468 /* _TBICSRBit */
07d3f51f 469 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 470
471 /* DumpCounterCommand */
07d3f51f 472 CounterDump = 0x8,
1da177e4
LT		 473};
474
2b7b4318
FR		 475enum rtl_desc_bit {
476 /* First doubleword. */
1da177e4
LT		 477 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
478 RingEnd = (1 << 30), /* End of descriptor ring */
479 FirstFrag = (1 << 29), /* First segment of a packet */
480 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 481};
482
483/* Generic case. */
484enum rtl_tx_desc_bit {
485 /* First doubleword. */
486 TD_LSO = (1 << 27), /* Large Send Offload */
487#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 488
2b7b4318
FR		 489 /* Second doubleword. */
490 TxVlanTag = (1 << 17), /* Add VLAN tag */
491};
492
493/* 8169, 8168b and 810x except 8102e. */
494enum rtl_tx_desc_bit_0 {
495 /* First doubleword. */
496#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
497 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
498 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
499 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
500};
501
502/* 8102e, 8168c and beyond. */
503enum rtl_tx_desc_bit_1 {
504 /* Second doubleword. */
505#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
506 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
507 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
508 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
509};
1da177e4 510
2b7b4318
FR		 511static const struct rtl_tx_desc_info {
512 struct {
513 u32 udp;
514 u32 tcp;
515 } checksum;
516 u16 mss_shift;
517 u16 opts_offset;
518} tx_desc_info [] = {
519 [RTL_TD_0] = {
520 .checksum = {
521 .udp = TD0_IP_CS | TD0_UDP_CS,
522 .tcp = TD0_IP_CS | TD0_TCP_CS
523 },
524 .mss_shift = TD0_MSS_SHIFT,
525 .opts_offset = 0
526 },
527 [RTL_TD_1] = {
528 .checksum = {
529 .udp = TD1_IP_CS | TD1_UDP_CS,
530 .tcp = TD1_IP_CS | TD1_TCP_CS
531 },
532 .mss_shift = TD1_MSS_SHIFT,
533 .opts_offset = 1
534 }
535};
536
537enum rtl_rx_desc_bit {
1da177e4
LT		 538 /* Rx private */
539 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
540 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
541
542#define RxProtoUDP (PID1)
543#define RxProtoTCP (PID0)
544#define RxProtoIP (PID1 | PID0)
545#define RxProtoMask RxProtoIP
546
547 IPFail = (1 << 16), /* IP checksum failed */
548 UDPFail = (1 << 15), /* UDP/IP checksum failed */
549 TCPFail = (1 << 14), /* TCP/IP checksum failed */
550 RxVlanTag = (1 << 16), /* VLAN tag available */
551};
552
553#define RsvdMask 0x3fffc000
554
555struct TxDesc {
6cccd6e7
REB		 556 __le32 opts1;
557 __le32 opts2;
558 __le64 addr;
1da177e4
LT		 559};
560
561struct RxDesc {
6cccd6e7
REB		 562 __le32 opts1;
563 __le32 opts2;
564 __le64 addr;
1da177e4
LT		 565};
566
567struct ring_info {
568 struct sk_buff *skb;
569 u32 len;
570 u8 __pad[sizeof(void *) - sizeof(u32)];
571};
572
f23e7fda 573enum features {
ccdffb9a
FR		 574 RTL_FEATURE_WOL = (1 << 0),
575 RTL_FEATURE_MSI = (1 << 1),
576 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 577};
578
355423d0
IV		 579struct rtl8169_counters {
580 __le64 tx_packets;
581 __le64 rx_packets;
582 __le64 tx_errors;
583 __le32 rx_errors;
584 __le16 rx_missed;
585 __le16 align_errors;
586 __le32 tx_one_collision;
587 __le32 tx_multi_collision;
588 __le64 rx_unicast;
589 __le64 rx_broadcast;
590 __le32 rx_multicast;
591 __le16 tx_aborted;
592 __le16 tx_underun;
593};
594
1da177e4
LT		 595struct rtl8169_private {
596 void __iomem *mmio_addr; /* memory map physical address */
597 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 598 struct net_device *dev;
bea3348e 599 struct napi_struct napi;
1da177e4 600 spinlock_t lock; /* spin lock flag */
b57b7e5a 601 u32 msg_enable;
2b7b4318
FR		 602 u16 txd_version;
603 u16 mac_version;
1da177e4
LT		 604 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
605 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
606 u32 dirty_rx;
607 u32 dirty_tx;
608 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
609 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
610 dma_addr_t TxPhyAddr;
611 dma_addr_t RxPhyAddr;
6f0333b8 612 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 613 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 614 struct timer_list timer;
615 u16 cp_cmd;
0e485150
FR		 616 u16 intr_event;
617 u16 napi_event;
1da177e4 618 u16 intr_mask;
1da177e4 619 int phy_1000_ctrl_reg;
c0e45c1c 620
621 struct mdio_ops {
622 void (*write)(void __iomem *, int, int);
623 int (*read)(void __iomem *, int);
624 } mdio_ops;
625
065c27c1 626 struct pll_power_ops {
627 void (*down)(struct rtl8169_private *);
628 void (*up)(struct rtl8169_private *);
629 } pll_power_ops;
630
54405cde 631 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 632 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 633 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 634 void (*hw_start)(struct net_device *);
4da19633 635 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 636 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 637 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 638 int pcie_cap;
c4028958 639 struct delayed_work task;
f23e7fda 640 unsigned features;
ccdffb9a
FR		 641
642 struct mii_if_info mii;
355423d0 643 struct rtl8169_counters counters;
e1759441 644 u32 saved_wolopts;
f1e02ed1 645
646 const struct firmware *fw;
953a12cc 647#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 648};
649
979b6c13 650MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 651MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 652module_param(use_dac, int, 0);
4300e8c7 653MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 654module_param_named(debug, debug.msg_enable, int, 0);
655MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 656MODULE_LICENSE("GPL");
657MODULE_VERSION(RTL8169_VERSION);
bca03d5f 658MODULE_FIRMWARE(FIRMWARE_8168D_1);
659MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 660MODULE_FIRMWARE(FIRMWARE_8168E_1);
661MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 662MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 663
664static int rtl8169_open(struct net_device *dev);
61357325
SH		 665static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
666 struct net_device *dev);
7d12e780 667static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 668static int rtl8169_init_ring(struct net_device *dev);
07ce4064 669static void rtl_hw_start(struct net_device *dev);
1da177e4 670static int rtl8169_close(struct net_device *dev);
07ce4064 671static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 672static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 673static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 674static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 675 void __iomem *, u32 budget);
4dcb7d33 676static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 677static void rtl8169_down(struct net_device *dev);
99f252b0 678static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 679static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 680
1da177e4 681static const unsigned int rtl8169_rx_config =
5b0384f4 682 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 683
b646d900 684static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
685{
686 void __iomem *ioaddr = tp->mmio_addr;
687 int i;
688
689 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
690 for (i = 0; i < 20; i++) {
691 udelay(100);
692 if (RTL_R32(OCPAR) & OCPAR_FLAG)
693 break;
694 }
695 return RTL_R32(OCPDR);
696}
697
698static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
699{
700 void __iomem *ioaddr = tp->mmio_addr;
701 int i;
702
703 RTL_W32(OCPDR, data);
704 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
705 for (i = 0; i < 20; i++) {
706 udelay(100);
707 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
708 break;
709 }
710}
711
fac5b3ca 712static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 713{
fac5b3ca 714 void __iomem *ioaddr = tp->mmio_addr;
b646d900 715 int i;
716
717 RTL_W8(ERIDR, cmd);
718 RTL_W32(ERIAR, 0x800010e8);
719 msleep(2);
720 for (i = 0; i < 5; i++) {
721 udelay(100);
722 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
723 break;
724 }
725
fac5b3ca 726 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 727}
728
729#define OOB_CMD_RESET 0x00
730#define OOB_CMD_DRIVER_START 0x05
731#define OOB_CMD_DRIVER_STOP 0x06
732
733static void rtl8168_driver_start(struct rtl8169_private *tp)
734{
735 int i;
4804b3b3 736 u32 reg;
b646d900 737
738 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
739
4804b3b3 740 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
741 reg = 0xb8;
742 else
743 reg = 0x10;
744
b646d900 745 for (i = 0; i < 10; i++) {
746 msleep(10);
4804b3b3 747 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 748 break;
749 }
750}
751
752static void rtl8168_driver_stop(struct rtl8169_private *tp)
753{
754 int i;
4804b3b3 755 u32 reg;
b646d900 756
757 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
758
4804b3b3 759 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
760 reg = 0xb8;
761 else
762 reg = 0x10;
763
b646d900 764 for (i = 0; i < 10; i++) {
765 msleep(10);
4804b3b3 766 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 767 break;
768 }
769}
770
4804b3b3 771static int r8168dp_check_dash(struct rtl8169_private *tp)
772{
773 u32 reg;
774
775 if (tp->mac_version == RTL_GIGA_MAC_VER_31)
776 reg = 0xb8;
777 else
778 reg = 0x10;
779
780 if (ocp_read(tp, 0xF, reg) & 0x00008000)
781 return 1;
782 else
783 return 0;
784}
b646d900 785
4da19633 786static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 787{
788 int i;
789
a6baf3af 790 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 791
2371408c 792 for (i = 20; i > 0; i--) {
07d3f51f
FR		 793 /*
794 * Check if the RTL8169 has completed writing to the specified
795 * MII register.
796 */
5b0384f4 797 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 798 break;
2371408c 799 udelay(25);
1da177e4 800 }
024a07ba 801 /*
81a95f04
TT		 802 * According to hardware specs a 20us delay is required after write
803 * complete indication, but before sending next command.
024a07ba 804 */
81a95f04 805 udelay(20);
1da177e4
LT		 806}
807
4da19633 808static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 809{
810 int i, value = -1;
811
a6baf3af 812 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 813
2371408c 814 for (i = 20; i > 0; i--) {
07d3f51f
FR		 815 /*
816 * Check if the RTL8169 has completed retrieving data from
817 * the specified MII register.
818 */
1da177e4 819 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 820 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 821 break;
822 }
2371408c 823 udelay(25);
1da177e4 824 }
81a95f04
TT		 825 /*
826 * According to hardware specs a 20us delay is required after read
827 * complete indication, but before sending next command.
828 */
829 udelay(20);
830
1da177e4
LT		 831 return value;
832}
833
c0e45c1c 834static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
835{
836 int i;
837
838 RTL_W32(OCPDR, data |
839 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
840 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
841 RTL_W32(EPHY_RXER_NUM, 0);
842
843 for (i = 0; i < 100; i++) {
844 mdelay(1);
845 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
846 break;
847 }
848}
849
850static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
851{
852 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
853 (value & OCPDR_DATA_MASK));
854}
855
856static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
857{
858 int i;
859
860 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
861
862 mdelay(1);
863 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
864 RTL_W32(EPHY_RXER_NUM, 0);
865
866 for (i = 0; i < 100; i++) {
867 mdelay(1);
868 if (RTL_R32(OCPAR) & OCPAR_FLAG)
869 break;
870 }
871
872 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
873}
874
e6de30d6 875#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
876
877static void r8168dp_2_mdio_start(void __iomem *ioaddr)
878{
879 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
880}
881
882static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
883{
884 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
885}
886
887static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
888{
889 r8168dp_2_mdio_start(ioaddr);
890
891 r8169_mdio_write(ioaddr, reg_addr, value);
892
893 r8168dp_2_mdio_stop(ioaddr);
894}
895
896static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
897{
898 int value;
899
900 r8168dp_2_mdio_start(ioaddr);
901
902 value = r8169_mdio_read(ioaddr, reg_addr);
903
904 r8168dp_2_mdio_stop(ioaddr);
905
906 return value;
907}
908
4da19633 909static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 910{
c0e45c1c 911 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 912}
913
4da19633 914static int rtl_readphy(struct rtl8169_private *tp, int location)
915{
c0e45c1c 916 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 917}
918
919static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
920{
921 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
922}
923
924static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 925{
926 int val;
927
4da19633 928 val = rtl_readphy(tp, reg_addr);
929 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 930}
931
ccdffb9a
FR		 932static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
933 int val)
934{
935 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 936
4da19633 937 rtl_writephy(tp, location, val);
ccdffb9a
FR		 938}
939
940static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
941{
942 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 943
4da19633 944 return rtl_readphy(tp, location);
ccdffb9a
FR		 945}
946
dacf8154
FR		 947static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
948{
949 unsigned int i;
950
951 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
952 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
953
954 for (i = 0; i < 100; i++) {
955 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
956 break;
957 udelay(10);
958 }
959}
960
961static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
962{
963 u16 value = 0xffff;
964 unsigned int i;
965
966 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
967
968 for (i = 0; i < 100; i++) {
969 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
970 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
971 break;
972 }
973 udelay(10);
974 }
975
976 return value;
977}
978
979static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
980{
981 unsigned int i;
982
983 RTL_W32(CSIDR, value);
984 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
985 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
986
987 for (i = 0; i < 100; i++) {
988 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
989 break;
990 udelay(10);
991 }
992}
993
994static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
995{
996 u32 value = ~0x00;
997 unsigned int i;
998
999 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1000 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1001
1002 for (i = 0; i < 100; i++) {
1003 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1004 value = RTL_R32(CSIDR);
1005 break;
1006 }
1007 udelay(10);
1008 }
1009
1010 return value;
1011}
1012
daf9df6d 1013static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1014{
1015 u8 value = 0xff;
1016 unsigned int i;
1017
1018 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1019
1020 for (i = 0; i < 300; i++) {
1021 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1022 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1023 break;
1024 }
1025 udelay(100);
1026 }
1027
1028 return value;
1029}
1030
1da177e4
LT		 1031static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1032{
1033 RTL_W16(IntrMask, 0x0000);
1034
1035 RTL_W16(IntrStatus, 0xffff);
1036}
1037
1038static void rtl8169_asic_down(void __iomem *ioaddr)
1039{
1040 RTL_W8(ChipCmd, 0x00);
1041 rtl8169_irq_mask_and_ack(ioaddr);
1042 RTL_R16(CPlusCmd);
1043}
1044
4da19633 1045static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1046{
4da19633 1047 void __iomem *ioaddr = tp->mmio_addr;
1048
1da177e4
LT		 1049 return RTL_R32(TBICSR) & TBIReset;
1050}
1051
4da19633 1052static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1053{
4da19633 1054 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1055}
1056
1057static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1058{
1059 return RTL_R32(TBICSR) & TBILinkOk;
1060}
1061
1062static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1063{
1064 return RTL_R8(PHYstatus) & LinkStatus;
1065}
1066
4da19633 1067static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1068{
4da19633 1069 void __iomem *ioaddr = tp->mmio_addr;
1070
1da177e4
LT		 1071 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1072}
1073
4da19633 1074static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1075{
1076 unsigned int val;
1077
4da19633 1078 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1079 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1080}
1081
e4fbce74 1082static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 1083 struct rtl8169_private *tp,
e4fbce74
RW		 1084 void __iomem *ioaddr,
1085 bool pm)
1da177e4
LT		 1086{
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&tp->lock, flags);
1090 if (tp->link_ok(ioaddr)) {
e1759441 1091 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1092 if (pm)
1093 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1094 netif_carrier_on(dev);
1519e57f
FR		 1095 if (net_ratelimit())
1096 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1097 } else {
1da177e4 1098 netif_carrier_off(dev);
bf82c189 1099 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1100 if (pm)
1101 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1102 }
1da177e4
LT		 1103 spin_unlock_irqrestore(&tp->lock, flags);
1104}
1105
e4fbce74
RW		 1106static void rtl8169_check_link_status(struct net_device *dev,
1107 struct rtl8169_private *tp,
1108 void __iomem *ioaddr)
1109{
1110 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1111}
1112
e1759441
RW		 1113#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1114
1115static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1116{
61a4dcc2
FR		 1117 void __iomem *ioaddr = tp->mmio_addr;
1118 u8 options;
e1759441 1119 u32 wolopts = 0;
61a4dcc2
FR		 1120
1121 options = RTL_R8(Config1);
1122 if (!(options & PMEnable))
e1759441 1123 return 0;
61a4dcc2
FR		 1124
1125 options = RTL_R8(Config3);
1126 if (options & LinkUp)
e1759441 1127 wolopts |= WAKE_PHY;
61a4dcc2 1128 if (options & MagicPacket)
e1759441 1129 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1130
1131 options = RTL_R8(Config5);
1132 if (options & UWF)
e1759441 1133 wolopts |= WAKE_UCAST;
61a4dcc2 1134 if (options & BWF)
e1759441 1135 wolopts |= WAKE_BCAST;
61a4dcc2 1136 if (options & MWF)
e1759441 1137 wolopts |= WAKE_MCAST;
61a4dcc2 1138
e1759441 1139 return wolopts;
61a4dcc2
FR		 1140}
1141
e1759441 1142static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1143{
1144 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1145
1146 spin_lock_irq(&tp->lock);
1147
1148 wol->supported = WAKE_ANY;
1149 wol->wolopts = __rtl8169_get_wol(tp);
1150
1151 spin_unlock_irq(&tp->lock);
1152}
1153
1154static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1155{
61a4dcc2 1156 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1157 unsigned int i;
350f7596 1158 static const struct {
61a4dcc2
FR		 1159 u32 opt;
1160 u16 reg;
1161 u8 mask;
1162 } cfg[] = {
1163 { WAKE_ANY, Config1, PMEnable },
1164 { WAKE_PHY, Config3, LinkUp },
1165 { WAKE_MAGIC, Config3, MagicPacket },
1166 { WAKE_UCAST, Config5, UWF },
1167 { WAKE_BCAST, Config5, BWF },
1168 { WAKE_MCAST, Config5, MWF },
1169 { WAKE_ANY, Config5, LanWake }
1170 };
1171
61a4dcc2
FR		 1172 RTL_W8(Cfg9346, Cfg9346_Unlock);
1173
1174 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1175 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1176 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1177 options |= cfg[i].mask;
1178 RTL_W8(cfg[i].reg, options);
1179 }
1180
1181 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1182}
1183
1184static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1185{
1186 struct rtl8169_private *tp = netdev_priv(dev);
1187
1188 spin_lock_irq(&tp->lock);
61a4dcc2 1189
f23e7fda
FR		 1190 if (wol->wolopts)
1191 tp->features |= RTL_FEATURE_WOL;
1192 else
1193 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1194 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1195 spin_unlock_irq(&tp->lock);
1196
ea80907f 1197 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1198
61a4dcc2
FR		 1199 return 0;
1200}
1201
1da177e4
LT		 1202static void rtl8169_get_drvinfo(struct net_device *dev,
1203 struct ethtool_drvinfo *info)
1204{
1205 struct rtl8169_private *tp = netdev_priv(dev);
1206
1207 strcpy(info->driver, MODULENAME);
1208 strcpy(info->version, RTL8169_VERSION);
1209 strcpy(info->bus_info, pci_name(tp->pci_dev));
1210}
1211
1212static int rtl8169_get_regs_len(struct net_device *dev)
1213{
1214 return R8169_REGS_SIZE;
1215}
1216
1217static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1218 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1219{
1220 struct rtl8169_private *tp = netdev_priv(dev);
1221 void __iomem *ioaddr = tp->mmio_addr;
1222 int ret = 0;
1223 u32 reg;
1224
1225 reg = RTL_R32(TBICSR);
1226 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1227 (duplex == DUPLEX_FULL)) {
1228 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1229 } else if (autoneg == AUTONEG_ENABLE)
1230 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1231 else {
bf82c189
JP		 1232 netif_warn(tp, link, dev,
1233 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1234 ret = -EOPNOTSUPP;
1235 }
1236
1237 return ret;
1238}
1239
1240static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1241 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1242{
1243 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1244 int giga_ctrl, bmcr;
54405cde 1245 int rc = -EINVAL;
1da177e4 1246
716b50a3 1247 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1248
1249 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1250 int auto_nego;
1251
4da19633 1252 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1253 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1254 ADVERTISE_100HALF | ADVERTISE_100FULL);
1255
1256 if (adv & ADVERTISED_10baseT_Half)
1257 auto_nego |= ADVERTISE_10HALF;
1258 if (adv & ADVERTISED_10baseT_Full)
1259 auto_nego |= ADVERTISE_10FULL;
1260 if (adv & ADVERTISED_100baseT_Half)
1261 auto_nego |= ADVERTISE_100HALF;
1262 if (adv & ADVERTISED_100baseT_Full)
1263 auto_nego |= ADVERTISE_100FULL;
1264
3577aa1b 1265 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1266
4da19633 1267 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1268 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1269
3577aa1b 1270 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1271 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1272 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1273 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1274 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1275 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1276 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1277 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
5a5e4443
HW		 1278 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1279 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1280 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
54405cde
ON		 1281 if (adv & ADVERTISED_1000baseT_Half)
1282 giga_ctrl |= ADVERTISE_1000HALF;
1283 if (adv & ADVERTISED_1000baseT_Full)
1284 giga_ctrl |= ADVERTISE_1000FULL;
1285 } else if (adv & (ADVERTISED_1000baseT_Half |
1286 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1287 netif_info(tp, link, dev,
1288 "PHY does not support 1000Mbps\n");
54405cde 1289 goto out;
bcf0bf90 1290 }
1da177e4 1291
3577aa1b 1292 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1293
4da19633 1294 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1295 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1296 } else {
1297 giga_ctrl = 0;
1298
1299 if (speed == SPEED_10)
1300 bmcr = 0;
1301 else if (speed == SPEED_100)
1302 bmcr = BMCR_SPEED100;
1303 else
54405cde 1304 goto out;
3577aa1b 1305
1306 if (duplex == DUPLEX_FULL)
1307 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1308 }
1309
1da177e4
LT		 1310 tp->phy_1000_ctrl_reg = giga_ctrl;
1311
4da19633 1312 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1313
1314 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1315 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1316 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1317 rtl_writephy(tp, 0x17, 0x2138);
1318 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1319 } else {
4da19633 1320 rtl_writephy(tp, 0x17, 0x2108);
1321 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1322 }
1323 }
1324
54405cde
ON		 1325 rc = 0;
1326out:
1327 return rc;
1da177e4
LT		 1328}
1329
1330static int rtl8169_set_speed(struct net_device *dev,
54405cde 1331 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1332{
1333 struct rtl8169_private *tp = netdev_priv(dev);
1334 int ret;
1335
54405cde 1336 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1da177e4 1337
64e4bfb4 1338 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1339 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1340
1341 return ret;
1342}
1343
1344static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1345{
1346 struct rtl8169_private *tp = netdev_priv(dev);
1347 unsigned long flags;
1348 int ret;
1349
1350 spin_lock_irqsave(&tp->lock, flags);
54405cde 1351 ret = rtl8169_set_speed(dev,
25db0338
DD		 1352 cmd->autoneg, ethtool_cmd_speed(cmd),
1353 cmd->duplex, cmd->advertising);
1da177e4 1354 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1355
1da177e4
LT		 1356 return ret;
1357}
1358
350fb32a 1359static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1360{
2b7b4318 1361 if (dev->mtu > TD_MSS_MAX)
350fb32a 1362 features &= ~NETIF_F_ALL_TSO;
1da177e4 1363
350fb32a 1364 return features;
1da177e4
LT		 1365}
1366
350fb32a 1367static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1368{
1369 struct rtl8169_private *tp = netdev_priv(dev);
1370 void __iomem *ioaddr = tp->mmio_addr;
1371 unsigned long flags;
1372
1373 spin_lock_irqsave(&tp->lock, flags);
1374
350fb32a 1375 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1376 tp->cp_cmd |= RxChkSum;
1377 else
1378 tp->cp_cmd &= ~RxChkSum;
1379
350fb32a
MM		 1380 if (dev->features & NETIF_F_HW_VLAN_RX)
1381 tp->cp_cmd |= RxVlan;
1382 else
1383 tp->cp_cmd &= ~RxVlan;
1384
1da177e4
LT		 1385 RTL_W16(CPlusCmd, tp->cp_cmd);
1386 RTL_R16(CPlusCmd);
1387
1388 spin_unlock_irqrestore(&tp->lock, flags);
1389
1390 return 0;
1391}
1392
1da177e4
LT		 1393static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1394 struct sk_buff *skb)
1395{
eab6d18d 1396 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1397 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1398}
1399
7a8fc77b 1400static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1401{
1402 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1403
7a8fc77b
FR		 1404 if (opts2 & RxVlanTag)
1405 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1406
1da177e4 1407 desc->opts2 = 0;
1da177e4
LT		 1408}
1409
ccdffb9a 1410static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1411{
1412 struct rtl8169_private *tp = netdev_priv(dev);
1413 void __iomem *ioaddr = tp->mmio_addr;
1414 u32 status;
1415
1416 cmd->supported =
1417 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1418 cmd->port = PORT_FIBRE;
1419 cmd->transceiver = XCVR_INTERNAL;
1420
1421 status = RTL_R32(TBICSR);
1422 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1423 cmd->autoneg = !!(status & TBINwEnable);
1424
70739497 1425 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1426 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1427
1428 return 0;
1da177e4
LT		 1429}
1430
ccdffb9a 1431static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1432{
1433 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1434
1435 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1436}
1437
1438static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1439{
1440 struct rtl8169_private *tp = netdev_priv(dev);
1441 unsigned long flags;
ccdffb9a 1442 int rc;
1da177e4
LT		 1443
1444 spin_lock_irqsave(&tp->lock, flags);
1445
ccdffb9a 1446 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1447
1448 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1449 return rc;
1da177e4
LT		 1450}
1451
1452static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1453 void *p)
1454{
5b0384f4
FR		 1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 unsigned long flags;
1da177e4 1457
5b0384f4
FR		 1458 if (regs->len > R8169_REGS_SIZE)
1459 regs->len = R8169_REGS_SIZE;
1da177e4 1460
5b0384f4
FR		 1461 spin_lock_irqsave(&tp->lock, flags);
1462 memcpy_fromio(p, tp->mmio_addr, regs->len);
1463 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1464}
1465
b57b7e5a
SH		 1466static u32 rtl8169_get_msglevel(struct net_device *dev)
1467{
1468 struct rtl8169_private *tp = netdev_priv(dev);
1469
1470 return tp->msg_enable;
1471}
1472
1473static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1474{
1475 struct rtl8169_private *tp = netdev_priv(dev);
1476
1477 tp->msg_enable = value;
1478}
1479
d4a3a0fc
SH		 1480static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1481 "tx_packets",
1482 "rx_packets",
1483 "tx_errors",
1484 "rx_errors",
1485 "rx_missed",
1486 "align_errors",
1487 "tx_single_collisions",
1488 "tx_multi_collisions",
1489 "unicast",
1490 "broadcast",
1491 "multicast",
1492 "tx_aborted",
1493 "tx_underrun",
1494};
1495
b9f2c044 1496static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1497{
b9f2c044
JG		 1498 switch (sset) {
1499 case ETH_SS_STATS:
1500 return ARRAY_SIZE(rtl8169_gstrings);
1501 default:
1502 return -EOPNOTSUPP;
1503 }
d4a3a0fc
SH		 1504}
1505
355423d0 1506static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1507{
1508 struct rtl8169_private *tp = netdev_priv(dev);
1509 void __iomem *ioaddr = tp->mmio_addr;
1510 struct rtl8169_counters *counters;
1511 dma_addr_t paddr;
1512 u32 cmd;
355423d0 1513 int wait = 1000;
48addcc9 1514 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1515
355423d0
IV		 1516 /*
1517 * Some chips are unable to dump tally counters when the receiver
1518 * is disabled.
1519 */
1520 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1521 return;
d4a3a0fc 1522
48addcc9 1523 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1524 if (!counters)
1525 return;
1526
1527 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1528 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1529 RTL_W32(CounterAddrLow, cmd);
1530 RTL_W32(CounterAddrLow, cmd | CounterDump);
1531
355423d0
IV		 1532 while (wait--) {
1533 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1534 /* copy updated counters */
1535 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1536 break;
355423d0
IV		 1537 }
1538 udelay(10);
d4a3a0fc
SH		 1539 }
1540
1541 RTL_W32(CounterAddrLow, 0);
1542 RTL_W32(CounterAddrHigh, 0);
1543
48addcc9 1544 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1545}
1546
355423d0
IV		 1547static void rtl8169_get_ethtool_stats(struct net_device *dev,
1548 struct ethtool_stats *stats, u64 *data)
1549{
1550 struct rtl8169_private *tp = netdev_priv(dev);
1551
1552 ASSERT_RTNL();
1553
1554 rtl8169_update_counters(dev);
1555
1556 data[0] = le64_to_cpu(tp->counters.tx_packets);
1557 data[1] = le64_to_cpu(tp->counters.rx_packets);
1558 data[2] = le64_to_cpu(tp->counters.tx_errors);
1559 data[3] = le32_to_cpu(tp->counters.rx_errors);
1560 data[4] = le16_to_cpu(tp->counters.rx_missed);
1561 data[5] = le16_to_cpu(tp->counters.align_errors);
1562 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1563 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1564 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1565 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1566 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1567 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1568 data[12] = le16_to_cpu(tp->counters.tx_underun);
1569}
1570
d4a3a0fc
SH		 1571static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1572{
1573 switch(stringset) {
1574 case ETH_SS_STATS:
1575 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1576 break;
1577 }
1578}
1579
7282d491 1580static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1581 .get_drvinfo = rtl8169_get_drvinfo,
1582 .get_regs_len = rtl8169_get_regs_len,
1583 .get_link = ethtool_op_get_link,
1584 .get_settings = rtl8169_get_settings,
1585 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1586 .get_msglevel = rtl8169_get_msglevel,
1587 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1588 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1589 .get_wol = rtl8169_get_wol,
1590 .set_wol = rtl8169_set_wol,
d4a3a0fc 1591 .get_strings = rtl8169_get_strings,
b9f2c044 1592 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1593 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1594};
1595
07d3f51f
FR		 1596static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1597 void __iomem *ioaddr)
1da177e4 1598{
0e485150
FR		 1599 /*
1600 * The driver currently handles the 8168Bf and the 8168Be identically
1601 * but they can be identified more specifically through the test below
1602 * if needed:
1603 *
1604 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1605 *
1606 * Same thing for the 8101Eb and the 8101Ec:
1607 *
1608 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1609 */
350f7596 1610 static const struct {
1da177e4 1611 u32 mask;
e3cf0cc0 1612 u32 val;
1da177e4
LT		 1613 int mac_version;
1614 } mac_info[] = {
01dc7fec 1615 /* 8168E family. */
1616 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1617 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1618 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1619
5b538df9 1620 /* 8168D family. */
daf9df6d 1621 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1622 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1623 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1624
e6de30d6 1625 /* 8168DP family. */
1626 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1627 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1628 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1629
ef808d50 1630 /* 8168C family. */
17c99297 1631 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1632 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1633 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1634 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1635 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1636 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1637 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1638 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1639 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1640
1641 /* 8168B family. */
1642 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1643 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1644 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1645 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1646
1647 /* 8101 family. */
36a0e6c2 1648 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1649 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1650 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1651 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1652 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1653 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1654 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1655 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1656 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1657 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1658 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1659 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1660 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1661 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1662 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1663 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1664 /* FIXME: where did these entries come from ? -- FR */
1665 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1666 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1667
1668 /* 8110 family. */
1669 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1670 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1671 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1672 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1673 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1674 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1675
f21b75e9
JD		 1676 /* Catch-all */
1677 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1678 }, *p = mac_info;
1679 u32 reg;
1680
e3cf0cc0
FR		 1681 reg = RTL_R32(TxConfig);
1682 while ((reg & p->mask) != p->val)
1da177e4
LT		 1683 p++;
1684 tp->mac_version = p->mac_version;
1685}
1686
1687static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1688{
bcf0bf90 1689 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1690}
1691
867763c1
FR		 1692struct phy_reg {
1693 u16 reg;
1694 u16 val;
1695};
1696
4da19633 1697static void rtl_writephy_batch(struct rtl8169_private *tp,
1698 const struct phy_reg *regs, int len)
867763c1
FR		 1699{
1700 while (len-- > 0) {
4da19633 1701 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1702 regs++;
1703 }
1704}
1705
bca03d5f 1706#define PHY_READ 0x00000000
1707#define PHY_DATA_OR 0x10000000
1708#define PHY_DATA_AND 0x20000000
1709#define PHY_BJMPN 0x30000000
1710#define PHY_READ_EFUSE 0x40000000
1711#define PHY_READ_MAC_BYTE 0x50000000
1712#define PHY_WRITE_MAC_BYTE 0x60000000
1713#define PHY_CLEAR_READCOUNT 0x70000000
1714#define PHY_WRITE 0x80000000
1715#define PHY_READCOUNT_EQ_SKIP 0x90000000
1716#define PHY_COMP_EQ_SKIPN 0xa0000000
1717#define PHY_COMP_NEQ_SKIPN 0xb0000000
1718#define PHY_WRITE_PREVIOUS 0xc0000000
1719#define PHY_SKIPN 0xd0000000
1720#define PHY_DELAY_MS 0xe0000000
1721#define PHY_WRITE_ERI_WORD 0xf0000000
1722
1723static void
1724rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1725{
bca03d5f 1726 __le32 *phytable = (__le32 *)fw->data;
1727 struct net_device *dev = tp->dev;
42b82dc1 1728 size_t index, fw_size = fw->size / sizeof(*phytable);
1729 u32 predata, count;
bca03d5f 1730
1731 if (fw->size % sizeof(*phytable)) {
1732 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1733 return;
1734 }
1735
42b82dc1 1736 for (index = 0; index < fw_size; index++) {
1737 u32 action = le32_to_cpu(phytable[index]);
1738 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1739
42b82dc1 1740 switch(action & 0xf0000000) {
1741 case PHY_READ:
1742 case PHY_DATA_OR:
1743 case PHY_DATA_AND:
1744 case PHY_READ_EFUSE:
1745 case PHY_CLEAR_READCOUNT:
1746 case PHY_WRITE:
1747 case PHY_WRITE_PREVIOUS:
1748 case PHY_DELAY_MS:
1749 break;
1750
1751 case PHY_BJMPN:
1752 if (regno > index) {
1753 netif_err(tp, probe, tp->dev,
1754 "Out of range of firmware\n");
1755 return;
1756 }
1757 break;
1758 case PHY_READCOUNT_EQ_SKIP:
1759 if (index + 2 >= fw_size) {
1760 netif_err(tp, probe, tp->dev,
1761 "Out of range of firmware\n");
1762 return;
1763 }
1764 break;
1765 case PHY_COMP_EQ_SKIPN:
1766 case PHY_COMP_NEQ_SKIPN:
1767 case PHY_SKIPN:
1768 if (index + 1 + regno >= fw_size) {
1769 netif_err(tp, probe, tp->dev,
1770 "Out of range of firmware\n");
1771 return;
1772 }
bca03d5f 1773 break;
1774
42b82dc1 1775 case PHY_READ_MAC_BYTE:
1776 case PHY_WRITE_MAC_BYTE:
1777 case PHY_WRITE_ERI_WORD:
1778 default:
1779 netif_err(tp, probe, tp->dev,
1780 "Invalid action 0x%08x\n", action);
bca03d5f 1781 return;
1782 }
1783 }
1784
42b82dc1 1785 predata = 0;
1786 count = 0;
1787
1788 for (index = 0; index < fw_size; ) {
1789 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1790 u32 data = action & 0x0000ffff;
42b82dc1 1791 u32 regno = (action & 0x0fff0000) >> 16;
1792
1793 if (!action)
1794 break;
bca03d5f 1795
1796 switch(action & 0xf0000000) {
42b82dc1 1797 case PHY_READ:
1798 predata = rtl_readphy(tp, regno);
1799 count++;
1800 index++;
1801 break;
1802 case PHY_DATA_OR:
1803 predata |= data;
1804 index++;
1805 break;
1806 case PHY_DATA_AND:
1807 predata &= data;
1808 index++;
1809 break;
1810 case PHY_BJMPN:
1811 index -= regno;
1812 break;
1813 case PHY_READ_EFUSE:
1814 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1815 index++;
1816 break;
1817 case PHY_CLEAR_READCOUNT:
1818 count = 0;
1819 index++;
1820 break;
bca03d5f 1821 case PHY_WRITE:
42b82dc1 1822 rtl_writephy(tp, regno, data);
1823 index++;
1824 break;
1825 case PHY_READCOUNT_EQ_SKIP:
1826 if (count == data)
1827 index += 2;
1828 else
1829 index += 1;
bca03d5f 1830 break;
42b82dc1 1831 case PHY_COMP_EQ_SKIPN:
1832 if (predata == data)
1833 index += regno;
1834 index++;
1835 break;
1836 case PHY_COMP_NEQ_SKIPN:
1837 if (predata != data)
1838 index += regno;
1839 index++;
1840 break;
1841 case PHY_WRITE_PREVIOUS:
1842 rtl_writephy(tp, regno, predata);
1843 index++;
1844 break;
1845 case PHY_SKIPN:
1846 index += regno + 1;
1847 break;
1848 case PHY_DELAY_MS:
1849 mdelay(data);
1850 index++;
1851 break;
1852
1853 case PHY_READ_MAC_BYTE:
1854 case PHY_WRITE_MAC_BYTE:
1855 case PHY_WRITE_ERI_WORD:
bca03d5f 1856 default:
1857 BUG();
1858 }
1859 }
1860}
1861
f1e02ed1 1862static void rtl_release_firmware(struct rtl8169_private *tp)
1863{
953a12cc
FR		 1864 if (!IS_ERR_OR_NULL(tp->fw))
1865 release_firmware(tp->fw);
1866 tp->fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1867}
1868
953a12cc 1869static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1870{
953a12cc 1871 const struct firmware *fw = tp->fw;
f1e02ed1 1872
1873 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
953a12cc
FR		 1874 if (!IS_ERR_OR_NULL(fw))
1875 rtl_phy_write_fw(tp, fw);
1876}
1877
1878static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1879{
1880 if (rtl_readphy(tp, reg) != val)
1881 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1882 else
1883 rtl_apply_firmware(tp);
f1e02ed1 1884}
1885
4da19633 1886static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1887{
350f7596 1888 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1889 { 0x1f, 0x0001 },
1890 { 0x06, 0x006e },
1891 { 0x08, 0x0708 },
1892 { 0x15, 0x4000 },
1893 { 0x18, 0x65c7 },
1da177e4 1894
0b9b571d 1895 { 0x1f, 0x0001 },
1896 { 0x03, 0x00a1 },
1897 { 0x02, 0x0008 },
1898 { 0x01, 0x0120 },
1899 { 0x00, 0x1000 },
1900 { 0x04, 0x0800 },
1901 { 0x04, 0x0000 },
1da177e4 1902
0b9b571d 1903 { 0x03, 0xff41 },
1904 { 0x02, 0xdf60 },
1905 { 0x01, 0x0140 },
1906 { 0x00, 0x0077 },
1907 { 0x04, 0x7800 },
1908 { 0x04, 0x7000 },
1909
1910 { 0x03, 0x802f },
1911 { 0x02, 0x4f02 },
1912 { 0x01, 0x0409 },
1913 { 0x00, 0xf0f9 },
1914 { 0x04, 0x9800 },
1915 { 0x04, 0x9000 },
1916
1917 { 0x03, 0xdf01 },
1918 { 0x02, 0xdf20 },
1919 { 0x01, 0xff95 },
1920 { 0x00, 0xba00 },
1921 { 0x04, 0xa800 },
1922 { 0x04, 0xa000 },
1923
1924 { 0x03, 0xff41 },
1925 { 0x02, 0xdf20 },
1926 { 0x01, 0x0140 },
1927 { 0x00, 0x00bb },
1928 { 0x04, 0xb800 },
1929 { 0x04, 0xb000 },
1930
1931 { 0x03, 0xdf41 },
1932 { 0x02, 0xdc60 },
1933 { 0x01, 0x6340 },
1934 { 0x00, 0x007d },
1935 { 0x04, 0xd800 },
1936 { 0x04, 0xd000 },
1937
1938 { 0x03, 0xdf01 },
1939 { 0x02, 0xdf20 },
1940 { 0x01, 0x100a },
1941 { 0x00, 0xa0ff },
1942 { 0x04, 0xf800 },
1943 { 0x04, 0xf000 },
1944
1945 { 0x1f, 0x0000 },
1946 { 0x0b, 0x0000 },
1947 { 0x00, 0x9200 }
1948 };
1da177e4 1949
4da19633 1950 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1951}
1952
4da19633 1953static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1954{
350f7596 1955 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1956 { 0x1f, 0x0002 },
1957 { 0x01, 0x90d0 },
1958 { 0x1f, 0x0000 }
1959 };
1960
4da19633 1961 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1962}
1963
4da19633 1964static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1965{
1966 struct pci_dev *pdev = tp->pci_dev;
1967 u16 vendor_id, device_id;
1968
1969 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1970 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1971
1972 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1973 return;
1974
4da19633 1975 rtl_writephy(tp, 0x1f, 0x0001);
1976 rtl_writephy(tp, 0x10, 0xf01b);
1977 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1978}
1979
4da19633 1980static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1981{
350f7596 1982 static const struct phy_reg phy_reg_init[] = {
2e955856 1983 { 0x1f, 0x0001 },
1984 { 0x04, 0x0000 },
1985 { 0x03, 0x00a1 },
1986 { 0x02, 0x0008 },
1987 { 0x01, 0x0120 },
1988 { 0x00, 0x1000 },
1989 { 0x04, 0x0800 },
1990 { 0x04, 0x9000 },
1991 { 0x03, 0x802f },
1992 { 0x02, 0x4f02 },
1993 { 0x01, 0x0409 },
1994 { 0x00, 0xf099 },
1995 { 0x04, 0x9800 },
1996 { 0x04, 0xa000 },
1997 { 0x03, 0xdf01 },
1998 { 0x02, 0xdf20 },
1999 { 0x01, 0xff95 },
2000 { 0x00, 0xba00 },
2001 { 0x04, 0xa800 },
2002 { 0x04, 0xf000 },
2003 { 0x03, 0xdf01 },
2004 { 0x02, 0xdf20 },
2005 { 0x01, 0x101a },
2006 { 0x00, 0xa0ff },
2007 { 0x04, 0xf800 },
2008 { 0x04, 0x0000 },
2009 { 0x1f, 0x0000 },
2010
2011 { 0x1f, 0x0001 },
2012 { 0x10, 0xf41b },
2013 { 0x14, 0xfb54 },
2014 { 0x18, 0xf5c7 },
2015 { 0x1f, 0x0000 },
2016
2017 { 0x1f, 0x0001 },
2018 { 0x17, 0x0cc0 },
2019 { 0x1f, 0x0000 }
2020 };
2021
4da19633 2022 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2023
4da19633 2024 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2025}
2026
4da19633 2027static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2028{
350f7596 2029 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2030 { 0x1f, 0x0001 },
2031 { 0x04, 0x0000 },
2032 { 0x03, 0x00a1 },
2033 { 0x02, 0x0008 },
2034 { 0x01, 0x0120 },
2035 { 0x00, 0x1000 },
2036 { 0x04, 0x0800 },
2037 { 0x04, 0x9000 },
2038 { 0x03, 0x802f },
2039 { 0x02, 0x4f02 },
2040 { 0x01, 0x0409 },
2041 { 0x00, 0xf099 },
2042 { 0x04, 0x9800 },
2043 { 0x04, 0xa000 },
2044 { 0x03, 0xdf01 },
2045 { 0x02, 0xdf20 },
2046 { 0x01, 0xff95 },
2047 { 0x00, 0xba00 },
2048 { 0x04, 0xa800 },
2049 { 0x04, 0xf000 },
2050 { 0x03, 0xdf01 },
2051 { 0x02, 0xdf20 },
2052 { 0x01, 0x101a },
2053 { 0x00, 0xa0ff },
2054 { 0x04, 0xf800 },
2055 { 0x04, 0x0000 },
2056 { 0x1f, 0x0000 },
2057
2058 { 0x1f, 0x0001 },
2059 { 0x0b, 0x8480 },
2060 { 0x1f, 0x0000 },
2061
2062 { 0x1f, 0x0001 },
2063 { 0x18, 0x67c7 },
2064 { 0x04, 0x2000 },
2065 { 0x03, 0x002f },
2066 { 0x02, 0x4360 },
2067 { 0x01, 0x0109 },
2068 { 0x00, 0x3022 },
2069 { 0x04, 0x2800 },
2070 { 0x1f, 0x0000 },
2071
2072 { 0x1f, 0x0001 },
2073 { 0x17, 0x0cc0 },
2074 { 0x1f, 0x0000 }
2075 };
2076
4da19633 2077 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2078}
2079
4da19633 2080static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2081{
350f7596 2082 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2083 { 0x10, 0xf41b },
2084 { 0x1f, 0x0000 }
2085 };
2086
4da19633 2087 rtl_writephy(tp, 0x1f, 0x0001);
2088 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2089
4da19633 2090 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2091}
2092
4da19633 2093static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2094{
350f7596 2095 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2096 { 0x1f, 0x0001 },
2097 { 0x10, 0xf41b },
2098 { 0x1f, 0x0000 }
2099 };
2100
4da19633 2101 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2102}
2103
4da19633 2104static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2105{
350f7596 2106 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2107 { 0x1f, 0x0000 },
2108 { 0x1d, 0x0f00 },
2109 { 0x1f, 0x0002 },
2110 { 0x0c, 0x1ec8 },
2111 { 0x1f, 0x0000 }
2112 };
2113
4da19633 2114 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2115}
2116
4da19633 2117static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2118{
350f7596 2119 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2120 { 0x1f, 0x0001 },
2121 { 0x1d, 0x3d98 },
2122 { 0x1f, 0x0000 }
2123 };
2124
4da19633 2125 rtl_writephy(tp, 0x1f, 0x0000);
2126 rtl_patchphy(tp, 0x14, 1 << 5);
2127 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2128
4da19633 2129 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2130}
2131
4da19633 2132static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2133{
350f7596 2134 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2135 { 0x1f, 0x0001 },
2136 { 0x12, 0x2300 },
867763c1
FR		 2137 { 0x1f, 0x0002 },
2138 { 0x00, 0x88d4 },
2139 { 0x01, 0x82b1 },
2140 { 0x03, 0x7002 },
2141 { 0x08, 0x9e30 },
2142 { 0x09, 0x01f0 },
2143 { 0x0a, 0x5500 },
2144 { 0x0c, 0x00c8 },
2145 { 0x1f, 0x0003 },
2146 { 0x12, 0xc096 },
2147 { 0x16, 0x000a },
f50d4275
FR		 2148 { 0x1f, 0x0000 },
2149 { 0x1f, 0x0000 },
2150 { 0x09, 0x2000 },
2151 { 0x09, 0x0000 }
867763c1
FR		 2152 };
2153
4da19633 2154 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2155
4da19633 2156 rtl_patchphy(tp, 0x14, 1 << 5);
2157 rtl_patchphy(tp, 0x0d, 1 << 5);
2158 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2159}
2160
4da19633 2161static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2162{
350f7596 2163 static const struct phy_reg phy_reg_init[] = {
f50d4275 2164 { 0x1f, 0x0001 },
7da97ec9 2165 { 0x12, 0x2300 },
f50d4275
FR		 2166 { 0x03, 0x802f },
2167 { 0x02, 0x4f02 },
2168 { 0x01, 0x0409 },
2169 { 0x00, 0xf099 },
2170 { 0x04, 0x9800 },
2171 { 0x04, 0x9000 },
2172 { 0x1d, 0x3d98 },
7da97ec9
FR		 2173 { 0x1f, 0x0002 },
2174 { 0x0c, 0x7eb8 },
f50d4275
FR		 2175 { 0x06, 0x0761 },
2176 { 0x1f, 0x0003 },
2177 { 0x16, 0x0f0a },
7da97ec9
FR		 2178 { 0x1f, 0x0000 }
2179 };
2180
4da19633 2181 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2182
4da19633 2183 rtl_patchphy(tp, 0x16, 1 << 0);
2184 rtl_patchphy(tp, 0x14, 1 << 5);
2185 rtl_patchphy(tp, 0x0d, 1 << 5);
2186 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2187}
2188
4da19633 2189static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2190{
350f7596 2191 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2192 { 0x1f, 0x0001 },
2193 { 0x12, 0x2300 },
2194 { 0x1d, 0x3d98 },
2195 { 0x1f, 0x0002 },
2196 { 0x0c, 0x7eb8 },
2197 { 0x06, 0x5461 },
2198 { 0x1f, 0x0003 },
2199 { 0x16, 0x0f0a },
2200 { 0x1f, 0x0000 }
2201 };
2202
4da19633 2203 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2204
4da19633 2205 rtl_patchphy(tp, 0x16, 1 << 0);
2206 rtl_patchphy(tp, 0x14, 1 << 5);
2207 rtl_patchphy(tp, 0x0d, 1 << 5);
2208 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2209}
2210
4da19633 2211static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2212{
4da19633 2213 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2214}
2215
bca03d5f 2216static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2217{
350f7596 2218 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2219 /* Channel Estimation */
5b538df9 2220 { 0x1f, 0x0001 },
daf9df6d 2221 { 0x06, 0x4064 },
2222 { 0x07, 0x2863 },
2223 { 0x08, 0x059c },
2224 { 0x09, 0x26b4 },
2225 { 0x0a, 0x6a19 },
2226 { 0x0b, 0xdcc8 },
2227 { 0x10, 0xf06d },
2228 { 0x14, 0x7f68 },
2229 { 0x18, 0x7fd9 },
2230 { 0x1c, 0xf0ff },
2231 { 0x1d, 0x3d9c },
5b538df9 2232 { 0x1f, 0x0003 },
daf9df6d 2233 { 0x12, 0xf49f },
2234 { 0x13, 0x070b },
2235 { 0x1a, 0x05ad },
bca03d5f 2236 { 0x14, 0x94c0 },
2237
2238 /*
2239 * Tx Error Issue
2240 * enhance line driver power
2241 */
5b538df9 2242 { 0x1f, 0x0002 },
daf9df6d 2243 { 0x06, 0x5561 },
2244 { 0x1f, 0x0005 },
2245 { 0x05, 0x8332 },
bca03d5f 2246 { 0x06, 0x5561 },
2247
2248 /*
2249 * Can not link to 1Gbps with bad cable
2250 * Decrease SNR threshold form 21.07dB to 19.04dB
2251 */
2252 { 0x1f, 0x0001 },
2253 { 0x17, 0x0cc0 },
daf9df6d 2254
5b538df9 2255 { 0x1f, 0x0000 },
bca03d5f 2256 { 0x0d, 0xf880 }
daf9df6d 2257 };
bca03d5f 2258 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2259
4da19633 2260 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2261
bca03d5f 2262 /*
2263 * Rx Error Issue
2264 * Fine Tune Switching regulator parameter
2265 */
4da19633 2266 rtl_writephy(tp, 0x1f, 0x0002);
2267 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2268 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2269
daf9df6d 2270 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2271 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2272 { 0x1f, 0x0002 },
2273 { 0x05, 0x669a },
2274 { 0x1f, 0x0005 },
2275 { 0x05, 0x8330 },
2276 { 0x06, 0x669a },
2277 { 0x1f, 0x0002 }
2278 };
2279 int val;
2280
4da19633 2281 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2282
4da19633 2283 val = rtl_readphy(tp, 0x0d);
daf9df6d 2284
2285 if ((val & 0x00ff) != 0x006c) {
350f7596 2286 static const u32 set[] = {
daf9df6d 2287 0x0065, 0x0066, 0x0067, 0x0068,
2288 0x0069, 0x006a, 0x006b, 0x006c
2289 };
2290 int i;
2291
4da19633 2292 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2293
2294 val &= 0xff00;
2295 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2296 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2297 }
2298 } else {
350f7596 2299 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2300 { 0x1f, 0x0002 },
2301 { 0x05, 0x6662 },
2302 { 0x1f, 0x0005 },
2303 { 0x05, 0x8330 },
2304 { 0x06, 0x6662 }
2305 };
2306
4da19633 2307 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2308 }
2309
bca03d5f 2310 /* RSET couple improve */
4da19633 2311 rtl_writephy(tp, 0x1f, 0x0002);
2312 rtl_patchphy(tp, 0x0d, 0x0300);
2313 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2314
bca03d5f 2315 /* Fine tune PLL performance */
4da19633 2316 rtl_writephy(tp, 0x1f, 0x0002);
2317 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2318 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2319
4da19633 2320 rtl_writephy(tp, 0x1f, 0x0005);
2321 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2322
2323 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2324
4da19633 2325 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2326}
2327
bca03d5f 2328static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2329{
350f7596 2330 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2331 /* Channel Estimation */
daf9df6d 2332 { 0x1f, 0x0001 },
2333 { 0x06, 0x4064 },
2334 { 0x07, 0x2863 },
2335 { 0x08, 0x059c },
2336 { 0x09, 0x26b4 },
2337 { 0x0a, 0x6a19 },
2338 { 0x0b, 0xdcc8 },
2339 { 0x10, 0xf06d },
2340 { 0x14, 0x7f68 },
2341 { 0x18, 0x7fd9 },
2342 { 0x1c, 0xf0ff },
2343 { 0x1d, 0x3d9c },
2344 { 0x1f, 0x0003 },
2345 { 0x12, 0xf49f },
2346 { 0x13, 0x070b },
2347 { 0x1a, 0x05ad },
2348 { 0x14, 0x94c0 },
2349
bca03d5f 2350 /*
2351 * Tx Error Issue
2352 * enhance line driver power
2353 */
daf9df6d 2354 { 0x1f, 0x0002 },
2355 { 0x06, 0x5561 },
2356 { 0x1f, 0x0005 },
2357 { 0x05, 0x8332 },
bca03d5f 2358 { 0x06, 0x5561 },
2359
2360 /*
2361 * Can not link to 1Gbps with bad cable
2362 * Decrease SNR threshold form 21.07dB to 19.04dB
2363 */
2364 { 0x1f, 0x0001 },
2365 { 0x17, 0x0cc0 },
daf9df6d 2366
2367 { 0x1f, 0x0000 },
bca03d5f 2368 { 0x0d, 0xf880 }
5b538df9 2369 };
bca03d5f 2370 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2371
4da19633 2372 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2373
daf9df6d 2374 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2375 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2376 { 0x1f, 0x0002 },
2377 { 0x05, 0x669a },
5b538df9 2378 { 0x1f, 0x0005 },
daf9df6d 2379 { 0x05, 0x8330 },
2380 { 0x06, 0x669a },
2381
2382 { 0x1f, 0x0002 }
2383 };
2384 int val;
2385
4da19633 2386 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2387
4da19633 2388 val = rtl_readphy(tp, 0x0d);
daf9df6d 2389 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2390 static const u32 set[] = {
daf9df6d 2391 0x0065, 0x0066, 0x0067, 0x0068,
2392 0x0069, 0x006a, 0x006b, 0x006c
2393 };
2394 int i;
2395
4da19633 2396 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2397
2398 val &= 0xff00;
2399 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2400 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2401 }
2402 } else {
350f7596 2403 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2404 { 0x1f, 0x0002 },
2405 { 0x05, 0x2642 },
5b538df9 2406 { 0x1f, 0x0005 },
daf9df6d 2407 { 0x05, 0x8330 },
2408 { 0x06, 0x2642 }
5b538df9
FR		 2409 };
2410
4da19633 2411 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2412 }
2413
bca03d5f 2414 /* Fine tune PLL performance */
4da19633 2415 rtl_writephy(tp, 0x1f, 0x0002);
2416 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2417 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2418
bca03d5f 2419 /* Switching regulator Slew rate */
4da19633 2420 rtl_writephy(tp, 0x1f, 0x0002);
2421 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2422
4da19633 2423 rtl_writephy(tp, 0x1f, 0x0005);
2424 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2425
2426 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2427
4da19633 2428 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2429}
2430
4da19633 2431static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2432{
350f7596 2433 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2434 { 0x1f, 0x0002 },
2435 { 0x10, 0x0008 },
2436 { 0x0d, 0x006c },
2437
2438 { 0x1f, 0x0000 },
2439 { 0x0d, 0xf880 },
2440
2441 { 0x1f, 0x0001 },
2442 { 0x17, 0x0cc0 },
2443
2444 { 0x1f, 0x0001 },
2445 { 0x0b, 0xa4d8 },
2446 { 0x09, 0x281c },
2447 { 0x07, 0x2883 },
2448 { 0x0a, 0x6b35 },
2449 { 0x1d, 0x3da4 },
2450 { 0x1c, 0xeffd },
2451 { 0x14, 0x7f52 },
2452 { 0x18, 0x7fc6 },
2453 { 0x08, 0x0601 },
2454 { 0x06, 0x4063 },
2455 { 0x10, 0xf074 },
2456 { 0x1f, 0x0003 },
2457 { 0x13, 0x0789 },
2458 { 0x12, 0xf4bd },
2459 { 0x1a, 0x04fd },
2460 { 0x14, 0x84b0 },
2461 { 0x1f, 0x0000 },
2462 { 0x00, 0x9200 },
2463
2464 { 0x1f, 0x0005 },
2465 { 0x01, 0x0340 },
2466 { 0x1f, 0x0001 },
2467 { 0x04, 0x4000 },
2468 { 0x03, 0x1d21 },
2469 { 0x02, 0x0c32 },
2470 { 0x01, 0x0200 },
2471 { 0x00, 0x5554 },
2472 { 0x04, 0x4800 },
2473 { 0x04, 0x4000 },
2474 { 0x04, 0xf000 },
2475 { 0x03, 0xdf01 },
2476 { 0x02, 0xdf20 },
2477 { 0x01, 0x101a },
2478 { 0x00, 0xa0ff },
2479 { 0x04, 0xf800 },
2480 { 0x04, 0xf000 },
2481 { 0x1f, 0x0000 },
2482
2483 { 0x1f, 0x0007 },
2484 { 0x1e, 0x0023 },
2485 { 0x16, 0x0000 },
2486 { 0x1f, 0x0000 }
2487 };
2488
4da19633 2489 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2490}
2491
e6de30d6 2492static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2493{
2494 static const struct phy_reg phy_reg_init[] = {
2495 { 0x1f, 0x0001 },
2496 { 0x17, 0x0cc0 },
2497
2498 { 0x1f, 0x0007 },
2499 { 0x1e, 0x002d },
2500 { 0x18, 0x0040 },
2501 { 0x1f, 0x0000 }
2502 };
2503
2504 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2505 rtl_patchphy(tp, 0x0d, 1 << 5);
2506}
2507
01dc7fec 2508static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2509{
2510 static const struct phy_reg phy_reg_init[] = {
2511 /* Enable Delay cap */
2512 { 0x1f, 0x0005 },
2513 { 0x05, 0x8b80 },
2514 { 0x06, 0xc896 },
2515 { 0x1f, 0x0000 },
2516
2517 /* Channel estimation fine tune */
2518 { 0x1f, 0x0001 },
2519 { 0x0b, 0x6c20 },
2520 { 0x07, 0x2872 },
2521 { 0x1c, 0xefff },
2522 { 0x1f, 0x0003 },
2523 { 0x14, 0x6420 },
2524 { 0x1f, 0x0000 },
2525
2526 /* Update PFM & 10M TX idle timer */
2527 { 0x1f, 0x0007 },
2528 { 0x1e, 0x002f },
2529 { 0x15, 0x1919 },
2530 { 0x1f, 0x0000 },
2531
2532 { 0x1f, 0x0007 },
2533 { 0x1e, 0x00ac },
2534 { 0x18, 0x0006 },
2535 { 0x1f, 0x0000 }
2536 };
2537
15ecd039
FR		 2538 rtl_apply_firmware(tp);
2539
01dc7fec 2540 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2541
2542 /* DCO enable for 10M IDLE Power */
2543 rtl_writephy(tp, 0x1f, 0x0007);
2544 rtl_writephy(tp, 0x1e, 0x0023);
2545 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2546 rtl_writephy(tp, 0x1f, 0x0000);
2547
2548 /* For impedance matching */
2549 rtl_writephy(tp, 0x1f, 0x0002);
2550 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2551 rtl_writephy(tp, 0x1F, 0x0000);
2552
2553 /* PHY auto speed down */
2554 rtl_writephy(tp, 0x1f, 0x0007);
2555 rtl_writephy(tp, 0x1e, 0x002d);
2556 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2557 rtl_writephy(tp, 0x1f, 0x0000);
2558 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2559
2560 rtl_writephy(tp, 0x1f, 0x0005);
2561 rtl_writephy(tp, 0x05, 0x8b86);
2562 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2563 rtl_writephy(tp, 0x1f, 0x0000);
2564
2565 rtl_writephy(tp, 0x1f, 0x0005);
2566 rtl_writephy(tp, 0x05, 0x8b85);
2567 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2568 rtl_writephy(tp, 0x1f, 0x0007);
2569 rtl_writephy(tp, 0x1e, 0x0020);
2570 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2571 rtl_writephy(tp, 0x1f, 0x0006);
2572 rtl_writephy(tp, 0x00, 0x5a00);
2573 rtl_writephy(tp, 0x1f, 0x0000);
2574 rtl_writephy(tp, 0x0d, 0x0007);
2575 rtl_writephy(tp, 0x0e, 0x003c);
2576 rtl_writephy(tp, 0x0d, 0x4007);
2577 rtl_writephy(tp, 0x0e, 0x0000);
2578 rtl_writephy(tp, 0x0d, 0x0000);
2579}
2580
4da19633 2581static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2582{
350f7596 2583 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2584 { 0x1f, 0x0003 },
2585 { 0x08, 0x441d },
2586 { 0x01, 0x9100 },
2587 { 0x1f, 0x0000 }
2588 };
2589
4da19633 2590 rtl_writephy(tp, 0x1f, 0x0000);
2591 rtl_patchphy(tp, 0x11, 1 << 12);
2592 rtl_patchphy(tp, 0x19, 1 << 13);
2593 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2594
4da19633 2595 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2596}
2597
5a5e4443
HW		 2598static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2599{
2600 static const struct phy_reg phy_reg_init[] = {
2601 { 0x1f, 0x0005 },
2602 { 0x1a, 0x0000 },
2603 { 0x1f, 0x0000 },
2604
2605 { 0x1f, 0x0004 },
2606 { 0x1c, 0x0000 },
2607 { 0x1f, 0x0000 },
2608
2609 { 0x1f, 0x0001 },
2610 { 0x15, 0x7701 },
2611 { 0x1f, 0x0000 }
2612 };
2613
2614 /* Disable ALDPS before ram code */
2615 rtl_writephy(tp, 0x1f, 0x0000);
2616 rtl_writephy(tp, 0x18, 0x0310);
2617 msleep(100);
2618
953a12cc 2619 rtl_apply_firmware(tp);
5a5e4443
HW		 2620
2621 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2622}
2623
5615d9f1
FR		 2624static void rtl_hw_phy_config(struct net_device *dev)
2625{
2626 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2627
2628 rtl8169_print_mac_version(tp);
2629
2630 switch (tp->mac_version) {
2631 case RTL_GIGA_MAC_VER_01:
2632 break;
2633 case RTL_GIGA_MAC_VER_02:
2634 case RTL_GIGA_MAC_VER_03:
4da19633 2635 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2636 break;
2637 case RTL_GIGA_MAC_VER_04:
4da19633 2638 rtl8169sb_hw_phy_config(tp);
5615d9f1 2639 break;
2e955856 2640 case RTL_GIGA_MAC_VER_05:
4da19633 2641 rtl8169scd_hw_phy_config(tp);
2e955856 2642 break;
8c7006aa 2643 case RTL_GIGA_MAC_VER_06:
4da19633 2644 rtl8169sce_hw_phy_config(tp);
8c7006aa 2645 break;
2857ffb7
FR		 2646 case RTL_GIGA_MAC_VER_07:
2647 case RTL_GIGA_MAC_VER_08:
2648 case RTL_GIGA_MAC_VER_09:
4da19633 2649 rtl8102e_hw_phy_config(tp);
2857ffb7 2650 break;
236b8082 2651 case RTL_GIGA_MAC_VER_11:
4da19633 2652 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2653 break;
2654 case RTL_GIGA_MAC_VER_12:
4da19633 2655 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2656 break;
2657 case RTL_GIGA_MAC_VER_17:
4da19633 2658 rtl8168bef_hw_phy_config(tp);
236b8082 2659 break;
867763c1 2660 case RTL_GIGA_MAC_VER_18:
4da19633 2661 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2662 break;
2663 case RTL_GIGA_MAC_VER_19:
4da19633 2664 rtl8168c_1_hw_phy_config(tp);
867763c1 2665 break;
7da97ec9 2666 case RTL_GIGA_MAC_VER_20:
4da19633 2667 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2668 break;
197ff761 2669 case RTL_GIGA_MAC_VER_21:
4da19633 2670 rtl8168c_3_hw_phy_config(tp);
197ff761 2671 break;
6fb07058 2672 case RTL_GIGA_MAC_VER_22:
4da19633 2673 rtl8168c_4_hw_phy_config(tp);
6fb07058 2674 break;
ef3386f0 2675 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2676 case RTL_GIGA_MAC_VER_24:
4da19633 2677 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2678 break;
5b538df9 2679 case RTL_GIGA_MAC_VER_25:
bca03d5f 2680 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2681 break;
2682 case RTL_GIGA_MAC_VER_26:
bca03d5f 2683 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2684 break;
2685 case RTL_GIGA_MAC_VER_27:
4da19633 2686 rtl8168d_3_hw_phy_config(tp);
5b538df9 2687 break;
e6de30d6 2688 case RTL_GIGA_MAC_VER_28:
2689 rtl8168d_4_hw_phy_config(tp);
2690 break;
5a5e4443
HW		 2691 case RTL_GIGA_MAC_VER_29:
2692 case RTL_GIGA_MAC_VER_30:
2693 rtl8105e_hw_phy_config(tp);
2694 break;
01dc7fec 2695 case RTL_GIGA_MAC_VER_32:
01dc7fec 2696 case RTL_GIGA_MAC_VER_33:
15ecd039 2697 rtl8168e_hw_phy_config(tp);
01dc7fec 2698 break;
ef3386f0 2699
5615d9f1
FR		 2700 default:
2701 break;
2702 }
2703}
2704
1da177e4
LT		 2705static void rtl8169_phy_timer(unsigned long __opaque)
2706{
2707 struct net_device *dev = (struct net_device *)__opaque;
2708 struct rtl8169_private *tp = netdev_priv(dev);
2709 struct timer_list *timer = &tp->timer;
2710 void __iomem *ioaddr = tp->mmio_addr;
2711 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2712
bcf0bf90 2713 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2714
64e4bfb4 2715 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2716 return;
2717
2718 spin_lock_irq(&tp->lock);
2719
4da19633 2720 if (tp->phy_reset_pending(tp)) {
5b0384f4 2721 /*
1da177e4
LT		 2722 * A busy loop could burn quite a few cycles on nowadays CPU.
2723 * Let's delay the execution of the timer for a few ticks.
2724 */
2725 timeout = HZ/10;
2726 goto out_mod_timer;
2727 }
2728
2729 if (tp->link_ok(ioaddr))
2730 goto out_unlock;
2731
bf82c189 2732 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2733
4da19633 2734 tp->phy_reset_enable(tp);
1da177e4
LT		 2735
2736out_mod_timer:
2737 mod_timer(timer, jiffies + timeout);
2738out_unlock:
2739 spin_unlock_irq(&tp->lock);
2740}
2741
2742static inline void rtl8169_delete_timer(struct net_device *dev)
2743{
2744 struct rtl8169_private *tp = netdev_priv(dev);
2745 struct timer_list *timer = &tp->timer;
2746
e179bb7b 2747 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2748 return;
2749
2750 del_timer_sync(timer);
2751}
2752
2753static inline void rtl8169_request_timer(struct net_device *dev)
2754{
2755 struct rtl8169_private *tp = netdev_priv(dev);
2756 struct timer_list *timer = &tp->timer;
2757
e179bb7b 2758 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2759 return;
2760
2efa53f3 2761 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2762}
2763
2764#ifdef CONFIG_NET_POLL_CONTROLLER
2765/*
2766 * Polling 'interrupt' - used by things like netconsole to send skbs
2767 * without having to re-enable interrupts. It's not called while
2768 * the interrupt routine is executing.
2769 */
2770static void rtl8169_netpoll(struct net_device *dev)
2771{
2772 struct rtl8169_private *tp = netdev_priv(dev);
2773 struct pci_dev *pdev = tp->pci_dev;
2774
2775 disable_irq(pdev->irq);
7d12e780 2776 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2777 enable_irq(pdev->irq);
2778}
2779#endif
2780
2781static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2782 void __iomem *ioaddr)
2783{
2784 iounmap(ioaddr);
2785 pci_release_regions(pdev);
87aeec76 2786 pci_clear_mwi(pdev);
1da177e4
LT		 2787 pci_disable_device(pdev);
2788 free_netdev(dev);
2789}
2790
bf793295
FR		 2791static void rtl8169_phy_reset(struct net_device *dev,
2792 struct rtl8169_private *tp)
2793{
07d3f51f 2794 unsigned int i;
bf793295 2795
4da19633 2796 tp->phy_reset_enable(tp);
bf793295 2797 for (i = 0; i < 100; i++) {
4da19633 2798 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2799 return;
2800 msleep(1);
2801 }
bf82c189 2802 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2803}
2804
4ff96fa6
FR		 2805static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2806{
2807 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2808
5615d9f1 2809 rtl_hw_phy_config(dev);
4ff96fa6 2810
77332894
MS		 2811 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2812 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2813 RTL_W8(0x82, 0x01);
2814 }
4ff96fa6 2815
6dccd16b
FR		 2816 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2817
2818 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2819 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2820
bcf0bf90 2821 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2822 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2823 RTL_W8(0x82, 0x01);
2824 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2825 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2826 }
2827
bf793295
FR		 2828 rtl8169_phy_reset(dev, tp);
2829
54405cde
ON		 2830 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2831 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2832 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
db552b33 2833 (tp->mii.supports_gmii ?
54405cde 2834 ADVERTISED_1000baseT_Half |
db552b33 2835 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2836
bf82c189
JP		 2837 if (RTL_R8(PHYstatus) & TBI_Enable)
2838 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2839}
2840
773d2021
FR		 2841static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2842{
2843 void __iomem *ioaddr = tp->mmio_addr;
2844 u32 high;
2845 u32 low;
2846
2847 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2848 high = addr[4] | (addr[5] << 8);
2849
2850 spin_lock_irq(&tp->lock);
2851
2852 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2853
773d2021 2854 RTL_W32(MAC4, high);
908ba2bf 2855 RTL_R32(MAC4);
2856
78f1cd02 2857 RTL_W32(MAC0, low);
908ba2bf 2858 RTL_R32(MAC0);
2859
773d2021
FR		 2860 RTL_W8(Cfg9346, Cfg9346_Lock);
2861
2862 spin_unlock_irq(&tp->lock);
2863}
2864
2865static int rtl_set_mac_address(struct net_device *dev, void *p)
2866{
2867 struct rtl8169_private *tp = netdev_priv(dev);
2868 struct sockaddr *addr = p;
2869
2870 if (!is_valid_ether_addr(addr->sa_data))
2871 return -EADDRNOTAVAIL;
2872
2873 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2874
2875 rtl_rar_set(tp, dev->dev_addr);
2876
2877 return 0;
2878}
2879
5f787a1a
FR		 2880static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2881{
2882 struct rtl8169_private *tp = netdev_priv(dev);
2883 struct mii_ioctl_data *data = if_mii(ifr);
2884
8b4ab28d
FR		 2885 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2886}
5f787a1a 2887
8b4ab28d
FR		 2888static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2889{
5f787a1a
FR		 2890 switch (cmd) {
2891 case SIOCGMIIPHY:
2892 data->phy_id = 32; /* Internal PHY */
2893 return 0;
2894
2895 case SIOCGMIIREG:
4da19633 2896 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2897 return 0;
2898
2899 case SIOCSMIIREG:
4da19633 2900 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2901 return 0;
2902 }
2903 return -EOPNOTSUPP;
2904}
2905
8b4ab28d
FR		 2906static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2907{
2908 return -EOPNOTSUPP;
2909}
2910
0e485150
FR		 2911static const struct rtl_cfg_info {
2912 void (*hw_start)(struct net_device *);
2913 unsigned int region;
2914 unsigned int align;
2915 u16 intr_event;
2916 u16 napi_event;
ccdffb9a 2917 unsigned features;
f21b75e9 2918 u8 default_ver;
0e485150
FR		 2919} rtl_cfg_infos [] = {
2920 [RTL_CFG_0] = {
2921 .hw_start = rtl_hw_start_8169,
2922 .region = 1,
e9f63f30 2923 .align = 0,
0e485150
FR		 2924 .intr_event = SYSErr | LinkChg | RxOverflow |
2925 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2926 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2927 .features = RTL_FEATURE_GMII,
2928 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2929 },
2930 [RTL_CFG_1] = {
2931 .hw_start = rtl_hw_start_8168,
2932 .region = 2,
2933 .align = 8,
53f57357 2934 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2935 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2936 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2937 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2938 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2939 },
2940 [RTL_CFG_2] = {
2941 .hw_start = rtl_hw_start_8101,
2942 .region = 2,
2943 .align = 8,
2944 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2945 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2946 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2947 .features = RTL_FEATURE_MSI,
2948 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2949 }
2950};
2951
fbac58fc
FR		 2952/* Cfg9346_Unlock assumed. */
2953static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2954 const struct rtl_cfg_info *cfg)
2955{
2956 unsigned msi = 0;
2957 u8 cfg2;
2958
2959 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2960 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2961 if (pci_enable_msi(pdev)) {
2962 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2963 } else {
2964 cfg2 |= MSIEnable;
2965 msi = RTL_FEATURE_MSI;
2966 }
2967 }
2968 RTL_W8(Config2, cfg2);
2969 return msi;
2970}
2971
2972static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2973{
2974 if (tp->features & RTL_FEATURE_MSI) {
2975 pci_disable_msi(pdev);
2976 tp->features &= ~RTL_FEATURE_MSI;
2977 }
2978}
2979
8b4ab28d
FR		 2980static const struct net_device_ops rtl8169_netdev_ops = {
2981 .ndo_open = rtl8169_open,
2982 .ndo_stop = rtl8169_close,
2983 .ndo_get_stats = rtl8169_get_stats,
00829823 2984 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2985 .ndo_tx_timeout = rtl8169_tx_timeout,
2986 .ndo_validate_addr = eth_validate_addr,
2987 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2988 .ndo_fix_features = rtl8169_fix_features,
2989 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2990 .ndo_set_mac_address = rtl_set_mac_address,
2991 .ndo_do_ioctl = rtl8169_ioctl,
2992 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2993#ifdef CONFIG_NET_POLL_CONTROLLER
2994 .ndo_poll_controller = rtl8169_netpoll,
2995#endif
2996
2997};
2998
c0e45c1c 2999static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3000{
3001 struct mdio_ops *ops = &tp->mdio_ops;
3002
3003 switch (tp->mac_version) {
3004 case RTL_GIGA_MAC_VER_27:
3005 ops->write = r8168dp_1_mdio_write;
3006 ops->read = r8168dp_1_mdio_read;
3007 break;
e6de30d6 3008 case RTL_GIGA_MAC_VER_28:
4804b3b3 3009 case RTL_GIGA_MAC_VER_31:
e6de30d6 3010 ops->write = r8168dp_2_mdio_write;
3011 ops->read = r8168dp_2_mdio_read;
3012 break;
c0e45c1c 3013 default:
3014 ops->write = r8169_mdio_write;
3015 ops->read = r8169_mdio_read;
3016 break;
3017 }
3018}
3019
065c27c1 3020static void r810x_phy_power_down(struct rtl8169_private *tp)
3021{
3022 rtl_writephy(tp, 0x1f, 0x0000);
3023 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3024}
3025
3026static void r810x_phy_power_up(struct rtl8169_private *tp)
3027{
3028 rtl_writephy(tp, 0x1f, 0x0000);
3029 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3030}
3031
3032static void r810x_pll_power_down(struct rtl8169_private *tp)
3033{
3034 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3035 rtl_writephy(tp, 0x1f, 0x0000);
3036 rtl_writephy(tp, MII_BMCR, 0x0000);
3037 return;
3038 }
3039
3040 r810x_phy_power_down(tp);
3041}
3042
3043static void r810x_pll_power_up(struct rtl8169_private *tp)
3044{
3045 r810x_phy_power_up(tp);
3046}
3047
3048static void r8168_phy_power_up(struct rtl8169_private *tp)
3049{
3050 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3051 switch (tp->mac_version) {
3052 case RTL_GIGA_MAC_VER_11:
3053 case RTL_GIGA_MAC_VER_12:
3054 case RTL_GIGA_MAC_VER_17:
3055 case RTL_GIGA_MAC_VER_18:
3056 case RTL_GIGA_MAC_VER_19:
3057 case RTL_GIGA_MAC_VER_20:
3058 case RTL_GIGA_MAC_VER_21:
3059 case RTL_GIGA_MAC_VER_22:
3060 case RTL_GIGA_MAC_VER_23:
3061 case RTL_GIGA_MAC_VER_24:
3062 case RTL_GIGA_MAC_VER_25:
3063 case RTL_GIGA_MAC_VER_26:
3064 case RTL_GIGA_MAC_VER_27:
3065 case RTL_GIGA_MAC_VER_28:
3066 case RTL_GIGA_MAC_VER_31:
3067 rtl_writephy(tp, 0x0e, 0x0000);
3068 break;
3069 default:
3070 break;
3071 }
065c27c1 3072 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3073}
3074
3075static void r8168_phy_power_down(struct rtl8169_private *tp)
3076{
3077 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3078 switch (tp->mac_version) {
3079 case RTL_GIGA_MAC_VER_32:
3080 case RTL_GIGA_MAC_VER_33:
3081 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3082 break;
3083
3084 case RTL_GIGA_MAC_VER_11:
3085 case RTL_GIGA_MAC_VER_12:
3086 case RTL_GIGA_MAC_VER_17:
3087 case RTL_GIGA_MAC_VER_18:
3088 case RTL_GIGA_MAC_VER_19:
3089 case RTL_GIGA_MAC_VER_20:
3090 case RTL_GIGA_MAC_VER_21:
3091 case RTL_GIGA_MAC_VER_22:
3092 case RTL_GIGA_MAC_VER_23:
3093 case RTL_GIGA_MAC_VER_24:
3094 case RTL_GIGA_MAC_VER_25:
3095 case RTL_GIGA_MAC_VER_26:
3096 case RTL_GIGA_MAC_VER_27:
3097 case RTL_GIGA_MAC_VER_28:
3098 case RTL_GIGA_MAC_VER_31:
3099 rtl_writephy(tp, 0x0e, 0x0200);
3100 default:
3101 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3102 break;
3103 }
065c27c1 3104}
3105
3106static void r8168_pll_power_down(struct rtl8169_private *tp)
3107{
3108 void __iomem *ioaddr = tp->mmio_addr;
3109
5d2e1957 3110 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3111 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3112 (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3113 r8168dp_check_dash(tp)) {
065c27c1 3114 return;
5d2e1957 3115 }
065c27c1 3116
3117 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
3118 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
3119 (RTL_R16(CPlusCmd) & ASF)) {
3120 return;
3121 }
3122
01dc7fec 3123 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3124 tp->mac_version == RTL_GIGA_MAC_VER_33)
3125 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3126
065c27c1 3127 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3128 rtl_writephy(tp, 0x1f, 0x0000);
3129 rtl_writephy(tp, MII_BMCR, 0x0000);
3130
3131 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3132 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3133 return;
3134 }
3135
3136 r8168_phy_power_down(tp);
3137
3138 switch (tp->mac_version) {
3139 case RTL_GIGA_MAC_VER_25:
3140 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3141 case RTL_GIGA_MAC_VER_27:
3142 case RTL_GIGA_MAC_VER_28:
4804b3b3 3143 case RTL_GIGA_MAC_VER_31:
01dc7fec 3144 case RTL_GIGA_MAC_VER_32:
3145 case RTL_GIGA_MAC_VER_33:
065c27c1 3146 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3147 break;
3148 }
3149}
3150
3151static void r8168_pll_power_up(struct rtl8169_private *tp)
3152{
3153 void __iomem *ioaddr = tp->mmio_addr;
3154
5d2e1957 3155 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3156 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3157 (tp->mac_version == RTL_GIGA_MAC_VER_31)) &&
3158 r8168dp_check_dash(tp)) {
065c27c1 3159 return;
5d2e1957 3160 }
065c27c1 3161
3162 switch (tp->mac_version) {
3163 case RTL_GIGA_MAC_VER_25:
3164 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3165 case RTL_GIGA_MAC_VER_27:
3166 case RTL_GIGA_MAC_VER_28:
4804b3b3 3167 case RTL_GIGA_MAC_VER_31:
01dc7fec 3168 case RTL_GIGA_MAC_VER_32:
3169 case RTL_GIGA_MAC_VER_33:
065c27c1 3170 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3171 break;
3172 }
3173
3174 r8168_phy_power_up(tp);
3175}
3176
3177static void rtl_pll_power_op(struct rtl8169_private *tp,
3178 void (*op)(struct rtl8169_private *))
3179{
3180 if (op)
3181 op(tp);
3182}
3183
3184static void rtl_pll_power_down(struct rtl8169_private *tp)
3185{
3186 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3187}
3188
3189static void rtl_pll_power_up(struct rtl8169_private *tp)
3190{
3191 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3192}
3193
3194static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3195{
3196 struct pll_power_ops *ops = &tp->pll_power_ops;
3197
3198 switch (tp->mac_version) {
3199 case RTL_GIGA_MAC_VER_07:
3200 case RTL_GIGA_MAC_VER_08:
3201 case RTL_GIGA_MAC_VER_09:
3202 case RTL_GIGA_MAC_VER_10:
3203 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3204 case RTL_GIGA_MAC_VER_29:
3205 case RTL_GIGA_MAC_VER_30:
065c27c1 3206 ops->down = r810x_pll_power_down;
3207 ops->up = r810x_pll_power_up;
3208 break;
3209
3210 case RTL_GIGA_MAC_VER_11:
3211 case RTL_GIGA_MAC_VER_12:
3212 case RTL_GIGA_MAC_VER_17:
3213 case RTL_GIGA_MAC_VER_18:
3214 case RTL_GIGA_MAC_VER_19:
3215 case RTL_GIGA_MAC_VER_20:
3216 case RTL_GIGA_MAC_VER_21:
3217 case RTL_GIGA_MAC_VER_22:
3218 case RTL_GIGA_MAC_VER_23:
3219 case RTL_GIGA_MAC_VER_24:
3220 case RTL_GIGA_MAC_VER_25:
3221 case RTL_GIGA_MAC_VER_26:
3222 case RTL_GIGA_MAC_VER_27:
e6de30d6 3223 case RTL_GIGA_MAC_VER_28:
4804b3b3 3224 case RTL_GIGA_MAC_VER_31:
01dc7fec 3225 case RTL_GIGA_MAC_VER_32:
3226 case RTL_GIGA_MAC_VER_33:
065c27c1 3227 ops->down = r8168_pll_power_down;
3228 ops->up = r8168_pll_power_up;
3229 break;
3230
3231 default:
3232 ops->down = NULL;
3233 ops->up = NULL;
3234 break;
3235 }
3236}
3237
1da177e4 3238static int __devinit
4ff96fa6 3239rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3240{
0e485150
FR		 3241 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3242 const unsigned int region = cfg->region;
1da177e4 3243 struct rtl8169_private *tp;
ccdffb9a 3244 struct mii_if_info *mii;
4ff96fa6
FR		 3245 struct net_device *dev;
3246 void __iomem *ioaddr;
2b7b4318 3247 int chipset, i;
07d3f51f 3248 int rc;
1da177e4 3249
4ff96fa6
FR		 3250 if (netif_msg_drv(&debug)) {
3251 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3252 MODULENAME, RTL8169_VERSION);
3253 }
1da177e4 3254
1da177e4 3255 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3256 if (!dev) {
b57b7e5a 3257 if (netif_msg_drv(&debug))
9b91cf9d 3258 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3259 rc = -ENOMEM;
3260 goto out;
1da177e4
LT		 3261 }
3262
1da177e4 3263 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3264 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3265 tp = netdev_priv(dev);
c4028958 3266 tp->dev = dev;
21e197f2 3267 tp->pci_dev = pdev;
b57b7e5a 3268 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3269
ccdffb9a
FR		 3270 mii = &tp->mii;
3271 mii->dev = dev;
3272 mii->mdio_read = rtl_mdio_read;
3273 mii->mdio_write = rtl_mdio_write;
3274 mii->phy_id_mask = 0x1f;
3275 mii->reg_num_mask = 0x1f;
3276 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3277
ba04c7c9
SG		 3278 /* disable ASPM completely as that cause random device stop working
3279 * problems as well as full system hangs for some PCIe devices users */
3280 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3281 PCIE_LINK_STATE_CLKPM);
3282
1da177e4
LT		 3283 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3284 rc = pci_enable_device(pdev);
b57b7e5a 3285 if (rc < 0) {
bf82c189 3286 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3287 goto err_out_free_dev_1;
1da177e4
LT		 3288 }
3289
87aeec76 3290 if (pci_set_mwi(pdev) < 0)
3291 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3292
1da177e4 3293 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3294 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3295 netif_err(tp, probe, dev,
3296 "region #%d not an MMIO resource, aborting\n",
3297 region);
1da177e4 3298 rc = -ENODEV;
87aeec76 3299 goto err_out_mwi_2;
1da177e4 3300 }
4ff96fa6 3301
1da177e4 3302 /* check for weird/broken PCI region reporting */
bcf0bf90 3303 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3304 netif_err(tp, probe, dev,
3305 "Invalid PCI region size(s), aborting\n");
1da177e4 3306 rc = -ENODEV;
87aeec76 3307 goto err_out_mwi_2;
1da177e4
LT		 3308 }
3309
3310 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3311 if (rc < 0) {
bf82c189 3312 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3313 goto err_out_mwi_2;
1da177e4
LT		 3314 }
3315
d24e9aaf 3316 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3317
3318 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3319 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3320 tp->cp_cmd |= PCIDAC;
3321 dev->features |= NETIF_F_HIGHDMA;
3322 } else {
284901a9 3323 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3324 if (rc < 0) {
bf82c189 3325 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3326 goto err_out_free_res_3;
1da177e4
LT		 3327 }
3328 }
3329
1da177e4 3330 /* ioremap MMIO region */
bcf0bf90 3331 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3332 if (!ioaddr) {
bf82c189 3333 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3334 rc = -EIO;
87aeec76 3335 goto err_out_free_res_3;
1da177e4
LT		 3336 }
3337
4300e8c7
DM		 3338 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3339 if (!tp->pcie_cap)
3340 netif_info(tp, probe, dev, "no PCI Express capability\n");
3341
d78ad8cb 3342 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3343
3344 /* Soft reset the chip. */
3345 RTL_W8(ChipCmd, CmdReset);
3346
3347 /* Check that the chip has finished the reset. */
07d3f51f 3348 for (i = 0; i < 100; i++) {
1da177e4
LT		 3349 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3350 break;
b518fa8e 3351 msleep_interruptible(1);
1da177e4
LT		 3352 }
3353
d78ad8cb
KW		 3354 RTL_W16(IntrStatus, 0xffff);
3355
ca52efd5 3356 pci_set_master(pdev);
3357
1da177e4
LT		 3358 /* Identify chip attached to board */
3359 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3360
7a8fc77b
FR		 3361 /*
3362 * Pretend we are using VLANs; This bypasses a nasty bug where
3363 * Interrupts stop flowing on high load on 8110SCd controllers.
3364 */
3365 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3366 tp->cp_cmd |= RxVlan;
3367
c0e45c1c 3368 rtl_init_mdio_ops(tp);
065c27c1 3369 rtl_init_pll_power_ops(tp);
c0e45c1c 3370
f21b75e9
JD		 3371 /* Use appropriate default if unknown */
3372 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3373 netif_notice(tp, probe, dev,
3374 "unknown MAC, using family default\n");
f21b75e9
JD		 3375 tp->mac_version = cfg->default_ver;
3376 }
3377
1da177e4 3378 rtl8169_print_mac_version(tp);
1da177e4 3379
cee60c37 3380 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3381 if (tp->mac_version == rtl_chip_info[i].mac_version)
3382 break;
3383 }
cee60c37 3384 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3385 dev_err(&pdev->dev,
3386 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3387 goto err_out_msi_4;
1da177e4 3388 }
2b7b4318
FR		 3389 chipset = i;
3390 tp->txd_version = rtl_chip_info[chipset].txd_version;
1da177e4 3391
5d06a99f
FR		 3392 RTL_W8(Cfg9346, Cfg9346_Unlock);
3393 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3394 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3395 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3396 tp->features |= RTL_FEATURE_WOL;
3397 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3398 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3399 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3400 RTL_W8(Cfg9346, Cfg9346_Lock);
3401
66ec5d4f
FR		 3402 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3403 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3404 tp->set_speed = rtl8169_set_speed_tbi;
3405 tp->get_settings = rtl8169_gset_tbi;
3406 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3407 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3408 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3409 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3410
64e4bfb4 3411 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3412 } else {
3413 tp->set_speed = rtl8169_set_speed_xmii;
3414 tp->get_settings = rtl8169_gset_xmii;
3415 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3416 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3417 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3418 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3419 }
3420
df58ef51
FR		 3421 spin_lock_init(&tp->lock);
3422
738e1e69
PV		 3423 tp->mmio_addr = ioaddr;
3424
7bf6bf48 3425 /* Get MAC address */
1da177e4
LT		 3426 for (i = 0; i < MAC_ADDR_LEN; i++)
3427 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3428 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3429
1da177e4 3430 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3431 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3432 dev->irq = pdev->irq;
3433 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3434
bea3348e 3435 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3436
350fb32a
MM		 3437 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3438 * properly for all devices */
3439 dev->features |= NETIF_F_RXCSUM |
3440 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3441
3442 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3443 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3444 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3445 NETIF_F_HIGHDMA;
3446
3447 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3448 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3449 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3450
3451 tp->intr_mask = 0xffff;
0e485150
FR		 3452 tp->hw_start = cfg->hw_start;
3453 tp->intr_event = cfg->intr_event;
3454 tp->napi_event = cfg->napi_event;
1da177e4 3455
2efa53f3
FR		 3456 init_timer(&tp->timer);
3457 tp->timer.data = (unsigned long) dev;
3458 tp->timer.function = rtl8169_phy_timer;
3459
953a12cc
FR		 3460 tp->fw = RTL_FIRMWARE_UNKNOWN;
3461
1da177e4 3462 rc = register_netdev(dev);
4ff96fa6 3463 if (rc < 0)
87aeec76 3464 goto err_out_msi_4;
1da177e4
LT		 3465
3466 pci_set_drvdata(pdev, dev);
3467
bf82c189 3468 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2b7b4318 3469 rtl_chip_info[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3470 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3471
e6de30d6 3472 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3473 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3474 (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
b646d900 3475 rtl8168_driver_start(tp);
e6de30d6 3476 }
b646d900 3477
8b76ab39 3478 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3479
f3ec4f87
AS		 3480 if (pci_dev_run_wake(pdev))
3481 pm_runtime_put_noidle(&pdev->dev);
e1759441 3482
0d672e9f
IV		 3483 netif_carrier_off(dev);
3484
4ff96fa6
FR		 3485out:
3486 return rc;
1da177e4 3487
87aeec76 3488err_out_msi_4:
fbac58fc 3489 rtl_disable_msi(pdev, tp);
4ff96fa6 3490 iounmap(ioaddr);
87aeec76 3491err_out_free_res_3:
4ff96fa6 3492 pci_release_regions(pdev);
87aeec76 3493err_out_mwi_2:
4ff96fa6 3494 pci_clear_mwi(pdev);
4ff96fa6
FR		 3495 pci_disable_device(pdev);
3496err_out_free_dev_1:
3497 free_netdev(dev);
3498 goto out;
1da177e4
LT		 3499}
3500
07d3f51f 3501static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3502{
3503 struct net_device *dev = pci_get_drvdata(pdev);
3504 struct rtl8169_private *tp = netdev_priv(dev);
3505
e6de30d6 3506 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
4804b3b3 3507 (tp->mac_version == RTL_GIGA_MAC_VER_28) ||
3508 (tp->mac_version == RTL_GIGA_MAC_VER_31)) {
b646d900 3509 rtl8168_driver_stop(tp);
e6de30d6 3510 }
b646d900 3511
23f333a2 3512 cancel_delayed_work_sync(&tp->task);
eb2a021c 3513
1da177e4 3514 unregister_netdev(dev);
cc098dc7 3515
953a12cc
FR		 3516 rtl_release_firmware(tp);
3517
f3ec4f87
AS		 3518 if (pci_dev_run_wake(pdev))
3519 pm_runtime_get_noresume(&pdev->dev);
e1759441 3520
cc098dc7
IV		 3521 /* restore original MAC address */
3522 rtl_rar_set(tp, dev->perm_addr);
3523
fbac58fc 3524 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3525 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3526 pci_set_drvdata(pdev, NULL);
3527}
3528
953a12cc
FR		 3529static void rtl_request_firmware(struct rtl8169_private *tp)
3530{
3531 int i;
3532
3533 /* Return early if the firmware is already loaded / cached. */
3534 if (!IS_ERR(tp->fw))
3535 goto out;
3536
3537 for (i = 0; i < ARRAY_SIZE(rtl_firmware_infos); i++) {
3538 const struct rtl_firmware_info *info = rtl_firmware_infos + i;
3539
3540 if (info->mac_version == tp->mac_version) {
3541 const char *name = info->fw_name;
3542 int rc;
3543
3544 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3545 if (rc < 0) {
3546 netif_warn(tp, ifup, tp->dev, "unable to load "
3547 "firmware patch %s (%d)\n", name, rc);
3548 goto out_disable_request_firmware;
3549 }
3550 goto out;
3551 }
3552 }
3553
3554out_disable_request_firmware:
3555 tp->fw = NULL;
3556out:
3557 return;
3558}
3559
1da177e4
LT		 3560static int rtl8169_open(struct net_device *dev)
3561{
3562 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3563 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3564 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3565 int retval = -ENOMEM;
1da177e4 3566
e1759441 3567 pm_runtime_get_sync(&pdev->dev);
1da177e4 3568
1da177e4
LT		 3569 /*
3570 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3571 * dma_alloc_coherent provides more.
1da177e4 3572 */
82553bb6
SG		 3573 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3574 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3575 if (!tp->TxDescArray)
e1759441 3576 goto err_pm_runtime_put;
1da177e4 3577
82553bb6
SG		 3578 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3579 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3580 if (!tp->RxDescArray)
99f252b0 3581 goto err_free_tx_0;
1da177e4
LT		 3582
3583 retval = rtl8169_init_ring(dev);
3584 if (retval < 0)
99f252b0 3585 goto err_free_rx_1;
1da177e4 3586
c4028958 3587 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3588
99f252b0
FR		 3589 smp_mb();
3590
953a12cc
FR		 3591 rtl_request_firmware(tp);
3592
fbac58fc
FR		 3593 retval = request_irq(dev->irq, rtl8169_interrupt,
3594 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3595 dev->name, dev);
3596 if (retval < 0)
953a12cc 3597 goto err_release_fw_2;
99f252b0 3598
bea3348e 3599 napi_enable(&tp->napi);
bea3348e 3600
eee3a96c 3601 rtl8169_init_phy(dev, tp);
3602
350fb32a 3603 rtl8169_set_features(dev, dev->features);
eee3a96c 3604
065c27c1 3605 rtl_pll_power_up(tp);
3606
07ce4064 3607 rtl_hw_start(dev);
1da177e4
LT		 3608
3609 rtl8169_request_timer(dev);
3610
e1759441
RW		 3611 tp->saved_wolopts = 0;
3612 pm_runtime_put_noidle(&pdev->dev);
3613
eee3a96c 3614 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3615out:
3616 return retval;
3617
953a12cc
FR		 3618err_release_fw_2:
3619 rtl_release_firmware(tp);
99f252b0
FR		 3620 rtl8169_rx_clear(tp);
3621err_free_rx_1:
82553bb6
SG		 3622 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3623 tp->RxPhyAddr);
e1759441 3624 tp->RxDescArray = NULL;
99f252b0 3625err_free_tx_0:
82553bb6
SG		 3626 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3627 tp->TxPhyAddr);
e1759441
RW		 3628 tp->TxDescArray = NULL;
3629err_pm_runtime_put:
3630 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3631 goto out;
3632}
3633
e6de30d6 3634static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3635{
e6de30d6 3636 void __iomem *ioaddr = tp->mmio_addr;
3637
1da177e4
LT		 3638 /* Disable interrupts */
3639 rtl8169_irq_mask_and_ack(ioaddr);
3640
5d2e1957 3641 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3642 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3643 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3644 while (RTL_R8(TxPoll) & NPQ)
3645 udelay(20);
3646
3647 }
3648
1da177e4
LT		 3649 /* Reset the chipset */
3650 RTL_W8(ChipCmd, CmdReset);
3651
3652 /* PCI commit */
3653 RTL_R8(ChipCmd);
3654}
3655
7f796d83 3656static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3657{
3658 void __iomem *ioaddr = tp->mmio_addr;
3659 u32 cfg = rtl8169_rx_config;
3660
2b7b4318 3661 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3662 RTL_W32(RxConfig, cfg);
3663
3664 /* Set DMA burst size and Interframe Gap Time */
3665 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3666 (InterFrameGap << TxInterFrameGapShift));
3667}
3668
07ce4064 3669static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3670{
3671 struct rtl8169_private *tp = netdev_priv(dev);
3672 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3673 unsigned int i;
1da177e4
LT		 3674
3675 /* Soft reset the chip. */
3676 RTL_W8(ChipCmd, CmdReset);
3677
3678 /* Check that the chip has finished the reset. */
07d3f51f 3679 for (i = 0; i < 100; i++) {
1da177e4
LT		 3680 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3681 break;
b518fa8e 3682 msleep_interruptible(1);
1da177e4
LT		 3683 }
3684
07ce4064
FR		 3685 tp->hw_start(dev);
3686
07ce4064
FR		 3687 netif_start_queue(dev);
3688}
3689
3690
7f796d83
FR		 3691static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3692 void __iomem *ioaddr)
3693{
3694 /*
3695 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3696 * register to be written before TxDescAddrLow to work.
3697 * Switching from MMIO to I/O access fixes the issue as well.
3698 */
3699 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3700 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3701 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3702 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3703}
3704
3705static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3706{
3707 u16 cmd;
3708
3709 cmd = RTL_R16(CPlusCmd);
3710 RTL_W16(CPlusCmd, cmd);
3711 return cmd;
3712}
3713
fdd7b4c3 3714static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3715{
3716 /* Low hurts. Let's disable the filtering. */
207d6e87 3717 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3718}
3719
6dccd16b
FR		 3720static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3721{
350f7596 3722 static const struct {
6dccd16b
FR		 3723 u32 mac_version;
3724 u32 clk;
3725 u32 val;
3726 } cfg2_info [] = {
3727 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3728 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3729 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3730 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3731 }, *p = cfg2_info;
3732 unsigned int i;
3733 u32 clk;
3734
3735 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3736 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3737 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3738 RTL_W32(0x7c, p->val);
3739 break;
3740 }
3741 }
3742}
3743
07ce4064
FR		 3744static void rtl_hw_start_8169(struct net_device *dev)
3745{
3746 struct rtl8169_private *tp = netdev_priv(dev);
3747 void __iomem *ioaddr = tp->mmio_addr;
3748 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3749
9cb427b6
FR		 3750 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3751 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3752 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3753 }
3754
1da177e4 3755 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3756 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3757 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3758 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3759 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3760 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3761
f0298f81 3762 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3763
6f0333b8 3764 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3765
c946b304
FR		 3766 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3767 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3768 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3769 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3770 rtl_set_rx_tx_config_registers(tp);
1da177e4 3771
7f796d83 3772 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3773
bcf0bf90
FR		 3774 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3775 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3776 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3777 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3778 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3779 }
3780
bcf0bf90
FR		 3781 RTL_W16(CPlusCmd, tp->cp_cmd);
3782
6dccd16b
FR		 3783 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3784
1da177e4
LT		 3785 /*
3786 * Undocumented corner. Supposedly:
3787 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3788 */
3789 RTL_W16(IntrMitigate, 0x0000);
3790
7f796d83 3791 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3792
c946b304
FR		 3793 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3794 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3795 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3796 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3797 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3798 rtl_set_rx_tx_config_registers(tp);
3799 }
3800
1da177e4 3801 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3802
3803 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3804 RTL_R8(IntrMask);
1da177e4
LT		 3805
3806 RTL_W32(RxMissed, 0);
3807
07ce4064 3808 rtl_set_rx_mode(dev);
1da177e4
LT		 3809
3810 /* no early-rx interrupts */
3811 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3812
3813 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3814 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3815}
1da177e4 3816
9c14ceaf 3817static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3818{
9c14ceaf
FR		 3819 struct net_device *dev = pci_get_drvdata(pdev);
3820 struct rtl8169_private *tp = netdev_priv(dev);
3821 int cap = tp->pcie_cap;
3822
3823 if (cap) {
3824 u16 ctl;
458a9f61 3825
9c14ceaf
FR		 3826 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3827 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3828 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3829 }
458a9f61
FR		 3830}
3831
650e8d5d 3832static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3833{
3834 u32 csi;
3835
3836 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3837 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3838}
3839
e6de30d6 3840static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3841{
3842 rtl_csi_access_enable(ioaddr, 0x17000000);
3843}
3844
650e8d5d 3845static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3846{
3847 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3848}
3849
3850struct ephy_info {
3851 unsigned int offset;
3852 u16 mask;
3853 u16 bits;
3854};
3855
350f7596 3856static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3857{
3858 u16 w;
3859
3860 while (len-- > 0) {
3861 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3862 rtl_ephy_write(ioaddr, e->offset, w);
3863 e++;
3864 }
3865}
3866
b726e493
FR		 3867static void rtl_disable_clock_request(struct pci_dev *pdev)
3868{
3869 struct net_device *dev = pci_get_drvdata(pdev);
3870 struct rtl8169_private *tp = netdev_priv(dev);
3871 int cap = tp->pcie_cap;
3872
3873 if (cap) {
3874 u16 ctl;
3875
3876 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3877 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3878 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3879 }
3880}
3881
e6de30d6 3882static void rtl_enable_clock_request(struct pci_dev *pdev)
3883{
3884 struct net_device *dev = pci_get_drvdata(pdev);
3885 struct rtl8169_private *tp = netdev_priv(dev);
3886 int cap = tp->pcie_cap;
3887
3888 if (cap) {
3889 u16 ctl;
3890
3891 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3892 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3893 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3894 }
3895}
3896
b726e493
FR		 3897#define R8168_CPCMD_QUIRK_MASK (\
3898 EnableBist | \
3899 Mac_dbgo_oe | \
3900 Force_half_dup | \
3901 Force_rxflow_en | \
3902 Force_txflow_en | \
3903 Cxpl_dbg_sel | \
3904 ASF | \
3905 PktCntrDisable | \
3906 Mac_dbgo_sel)
3907
219a1e9d
FR		 3908static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3909{
b726e493
FR		 3910 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3911
3912 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3913
2e68ae44
FR		 3914 rtl_tx_performance_tweak(pdev,
3915 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3916}
3917
3918static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3919{
3920 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3921
f0298f81 3922 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3923
3924 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3925}
3926
3927static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3928{
b726e493
FR		 3929 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3930
3931 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3932
219a1e9d 3933 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3934
3935 rtl_disable_clock_request(pdev);
3936
3937 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3938}
3939
ef3386f0 3940static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3941{
350f7596 3942 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3943 { 0x01, 0, 0x0001 },
3944 { 0x02, 0x0800, 0x1000 },
3945 { 0x03, 0, 0x0042 },
3946 { 0x06, 0x0080, 0x0000 },
3947 { 0x07, 0, 0x2000 }
3948 };
3949
650e8d5d 3950 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3951
3952 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3953
219a1e9d
FR		 3954 __rtl_hw_start_8168cp(ioaddr, pdev);
3955}
3956
ef3386f0
FR		 3957static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3958{
650e8d5d 3959 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3960
3961 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3962
3963 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3964
3965 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3966}
3967
7f3e3d3a
FR		 3968static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3969{
650e8d5d 3970 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3971
3972 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3973
3974 /* Magic. */
3975 RTL_W8(DBG_REG, 0x20);
3976
f0298f81 3977 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3978
3979 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3980
3981 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3982}
3983
219a1e9d
FR		 3984static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3985{
350f7596 3986 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3987 { 0x02, 0x0800, 0x1000 },
3988 { 0x03, 0, 0x0002 },
3989 { 0x06, 0x0080, 0x0000 }
3990 };
3991
650e8d5d 3992 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3993
3994 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3995
3996 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3997
219a1e9d
FR		 3998 __rtl_hw_start_8168cp(ioaddr, pdev);
3999}
4000
4001static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4002{
350f7596 4003 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4004 { 0x01, 0, 0x0001 },
4005 { 0x03, 0x0400, 0x0220 }
4006 };
4007
650e8d5d 4008 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4009
4010 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4011
219a1e9d
FR		 4012 __rtl_hw_start_8168cp(ioaddr, pdev);
4013}
4014
197ff761
FR		 4015static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4016{
4017 rtl_hw_start_8168c_2(ioaddr, pdev);
4018}
4019
6fb07058
FR		 4020static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4021{
650e8d5d 4022 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4023
4024 __rtl_hw_start_8168cp(ioaddr, pdev);
4025}
4026
5b538df9
FR		 4027static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4028{
650e8d5d 4029 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4030
4031 rtl_disable_clock_request(pdev);
4032
f0298f81 4033 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4034
4035 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4036
4037 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4038}
4039
4804b3b3 4040static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4041{
4042 rtl_csi_access_enable_1(ioaddr);
4043
4044 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4045
4046 RTL_W8(MaxTxPacketSize, TxPacketMax);
4047
4048 rtl_disable_clock_request(pdev);
4049}
4050
e6de30d6 4051static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4052{
4053 static const struct ephy_info e_info_8168d_4[] = {
4054 { 0x0b, ~0, 0x48 },
4055 { 0x19, 0x20, 0x50 },
4056 { 0x0c, ~0, 0x20 }
4057 };
4058 int i;
4059
4060 rtl_csi_access_enable_1(ioaddr);
4061
4062 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4063
4064 RTL_W8(MaxTxPacketSize, TxPacketMax);
4065
4066 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4067 const struct ephy_info *e = e_info_8168d_4 + i;
4068 u16 w;
4069
4070 w = rtl_ephy_read(ioaddr, e->offset);
4071 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4072 }
4073
4074 rtl_enable_clock_request(pdev);
4075}
4076
01dc7fec 4077static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4078{
4079 static const struct ephy_info e_info_8168e[] = {
4080 { 0x00, 0x0200, 0x0100 },
4081 { 0x00, 0x0000, 0x0004 },
4082 { 0x06, 0x0002, 0x0001 },
4083 { 0x06, 0x0000, 0x0030 },
4084 { 0x07, 0x0000, 0x2000 },
4085 { 0x00, 0x0000, 0x0020 },
4086 { 0x03, 0x5800, 0x2000 },
4087 { 0x03, 0x0000, 0x0001 },
4088 { 0x01, 0x0800, 0x1000 },
4089 { 0x07, 0x0000, 0x4000 },
4090 { 0x1e, 0x0000, 0x2000 },
4091 { 0x19, 0xffff, 0xfe6c },
4092 { 0x0a, 0x0000, 0x0040 }
4093 };
4094
4095 rtl_csi_access_enable_2(ioaddr);
4096
4097 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4098
4099 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4100
4101 RTL_W8(MaxTxPacketSize, TxPacketMax);
4102
4103 rtl_disable_clock_request(pdev);
4104
4105 /* Reset tx FIFO pointer */
4106 RTL_W32(MISC, RTL_R32(MISC) | txpla_rst);
4107 RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst);
4108
4109 RTL_W8(Config5, RTL_R8(Config5) & ~spi_en);
4110}
4111
07ce4064
FR		 4112static void rtl_hw_start_8168(struct net_device *dev)
4113{
2dd99530
FR		 4114 struct rtl8169_private *tp = netdev_priv(dev);
4115 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4116 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4117
4118 RTL_W8(Cfg9346, Cfg9346_Unlock);
4119
f0298f81 4120 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4121
6f0333b8 4122 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4123
0e485150 4124 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4125
4126 RTL_W16(CPlusCmd, tp->cp_cmd);
4127
0e485150 4128 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4129
0e485150 4130 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4131 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4132 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4133 tp->intr_event |= RxFIFOOver | PCSTimeout;
4134 tp->intr_event &= ~RxOverflow;
4135 }
4136
4137 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4138
b8363901
FR		 4139 rtl_set_rx_mode(dev);
4140
4141 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4142 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4143
4144 RTL_R8(IntrMask);
4145
219a1e9d
FR		 4146 switch (tp->mac_version) {
4147 case RTL_GIGA_MAC_VER_11:
4148 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4149 break;
219a1e9d
FR		 4150
4151 case RTL_GIGA_MAC_VER_12:
4152 case RTL_GIGA_MAC_VER_17:
4153 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4154 break;
219a1e9d
FR		 4155
4156 case RTL_GIGA_MAC_VER_18:
ef3386f0 4157 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4158 break;
219a1e9d
FR		 4159
4160 case RTL_GIGA_MAC_VER_19:
4161 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4162 break;
219a1e9d
FR		 4163
4164 case RTL_GIGA_MAC_VER_20:
4165 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4166 break;
219a1e9d 4167
197ff761
FR		 4168 case RTL_GIGA_MAC_VER_21:
4169 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4170 break;
197ff761 4171
6fb07058
FR		 4172 case RTL_GIGA_MAC_VER_22:
4173 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4174 break;
6fb07058 4175
ef3386f0
FR		 4176 case RTL_GIGA_MAC_VER_23:
4177 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4178 break;
ef3386f0 4179
7f3e3d3a
FR		 4180 case RTL_GIGA_MAC_VER_24:
4181 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4182 break;
7f3e3d3a 4183
5b538df9 4184 case RTL_GIGA_MAC_VER_25:
daf9df6d 4185 case RTL_GIGA_MAC_VER_26:
4186 case RTL_GIGA_MAC_VER_27:
5b538df9 4187 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4188 break;
5b538df9 4189
e6de30d6 4190 case RTL_GIGA_MAC_VER_28:
4191 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4192 break;
4193 case RTL_GIGA_MAC_VER_31:
4194 rtl_hw_start_8168dp(ioaddr, pdev);
4195 break;
4196
01dc7fec 4197 case RTL_GIGA_MAC_VER_32:
4198 case RTL_GIGA_MAC_VER_33:
4199 rtl_hw_start_8168e(ioaddr, pdev);
4200 break;
e6de30d6 4201
219a1e9d
FR		 4202 default:
4203 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4204 dev->name, tp->mac_version);
4804b3b3 4205 break;
219a1e9d 4206 }
2dd99530 4207
0e485150
FR		 4208 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4209
b8363901
FR		 4210 RTL_W8(Cfg9346, Cfg9346_Lock);
4211
2dd99530 4212 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4213
0e485150 4214 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4215}
1da177e4 4216
2857ffb7
FR		 4217#define R810X_CPCMD_QUIRK_MASK (\
4218 EnableBist | \
4219 Mac_dbgo_oe | \
4220 Force_half_dup | \
5edcc537 4221 Force_rxflow_en | \
2857ffb7
FR		 4222 Force_txflow_en | \
4223 Cxpl_dbg_sel | \
4224 ASF | \
4225 PktCntrDisable | \
d24e9aaf 4226 Mac_dbgo_sel)
2857ffb7
FR		 4227
4228static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4229{
350f7596 4230 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4231 { 0x01, 0, 0x6e65 },
4232 { 0x02, 0, 0x091f },
4233 { 0x03, 0, 0xc2f9 },
4234 { 0x06, 0, 0xafb5 },
4235 { 0x07, 0, 0x0e00 },
4236 { 0x19, 0, 0xec80 },
4237 { 0x01, 0, 0x2e65 },
4238 { 0x01, 0, 0x6e65 }
4239 };
4240 u8 cfg1;
4241
650e8d5d 4242 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4243
4244 RTL_W8(DBG_REG, FIX_NAK_1);
4245
4246 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4247
4248 RTL_W8(Config1,
4249 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4250 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4251
4252 cfg1 = RTL_R8(Config1);
4253 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4254 RTL_W8(Config1, cfg1 & ~LEDS0);
4255
2857ffb7
FR		 4256 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4257}
4258
4259static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4260{
650e8d5d 4261 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4262
4263 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4264
4265 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4266 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4267}
4268
4269static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4270{
4271 rtl_hw_start_8102e_2(ioaddr, pdev);
4272
4273 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4274}
4275
5a5e4443
HW		 4276static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4277{
4278 static const struct ephy_info e_info_8105e_1[] = {
4279 { 0x07, 0, 0x4000 },
4280 { 0x19, 0, 0x0200 },
4281 { 0x19, 0, 0x0020 },
4282 { 0x1e, 0, 0x2000 },
4283 { 0x03, 0, 0x0001 },
4284 { 0x19, 0, 0x0100 },
4285 { 0x19, 0, 0x0004 },
4286 { 0x0a, 0, 0x0020 }
4287 };
4288
4289 /* Force LAN exit from ASPM if Rx/Tx are not idel */
4290 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4291
4292 /* disable Early Tally Counter */
4293 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4294
4295 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4296 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4297
4298 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4299}
4300
4301static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4302{
4303 rtl_hw_start_8105e_1(ioaddr, pdev);
4304 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4305}
4306
07ce4064
FR		 4307static void rtl_hw_start_8101(struct net_device *dev)
4308{
cdf1a608
FR		 4309 struct rtl8169_private *tp = netdev_priv(dev);
4310 void __iomem *ioaddr = tp->mmio_addr;
4311 struct pci_dev *pdev = tp->pci_dev;
4312
e3cf0cc0
FR		 4313 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4314 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 4315 int cap = tp->pcie_cap;
4316
4317 if (cap) {
4318 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4319 PCI_EXP_DEVCTL_NOSNOOP_EN);
4320 }
cdf1a608
FR		 4321 }
4322
d24e9aaf
HW		 4323 RTL_W8(Cfg9346, Cfg9346_Unlock);
4324
2857ffb7
FR		 4325 switch (tp->mac_version) {
4326 case RTL_GIGA_MAC_VER_07:
4327 rtl_hw_start_8102e_1(ioaddr, pdev);
4328 break;
4329
4330 case RTL_GIGA_MAC_VER_08:
4331 rtl_hw_start_8102e_3(ioaddr, pdev);
4332 break;
4333
4334 case RTL_GIGA_MAC_VER_09:
4335 rtl_hw_start_8102e_2(ioaddr, pdev);
4336 break;
5a5e4443
HW		 4337
4338 case RTL_GIGA_MAC_VER_29:
4339 rtl_hw_start_8105e_1(ioaddr, pdev);
4340 break;
4341 case RTL_GIGA_MAC_VER_30:
4342 rtl_hw_start_8105e_2(ioaddr, pdev);
4343 break;
cdf1a608
FR		 4344 }
4345
d24e9aaf 4346 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4347
f0298f81 4348 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4349
6f0333b8 4350 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4351
d24e9aaf 4352 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4353 RTL_W16(CPlusCmd, tp->cp_cmd);
4354
4355 RTL_W16(IntrMitigate, 0x0000);
4356
4357 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4358
4359 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4360 rtl_set_rx_tx_config_registers(tp);
4361
cdf1a608
FR		 4362 RTL_R8(IntrMask);
4363
cdf1a608
FR		 4364 rtl_set_rx_mode(dev);
4365
4366 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4367
0e485150 4368 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4369}
4370
4371static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4372{
1da177e4
LT		 4373 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4374 return -EINVAL;
4375
4376 dev->mtu = new_mtu;
350fb32a
MM		 4377 netdev_update_features(dev);
4378
323bb685 4379 return 0;
1da177e4
LT		 4380}
4381
4382static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4383{
95e0918d 4384 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4385 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4386}
4387
6f0333b8
ED		 4388static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4389 void **data_buff, struct RxDesc *desc)
1da177e4 4390{
48addcc9 4391 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4392 DMA_FROM_DEVICE);
48addcc9 4393
6f0333b8
ED		 4394 kfree(*data_buff);
4395 *data_buff = NULL;
1da177e4
LT		 4396 rtl8169_make_unusable_by_asic(desc);
4397}
4398
4399static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4400{
4401 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4402
4403 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4404}
4405
4406static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4407 u32 rx_buf_sz)
4408{
4409 desc->addr = cpu_to_le64(mapping);
4410 wmb();
4411 rtl8169_mark_to_asic(desc, rx_buf_sz);
4412}
4413
6f0333b8
ED		 4414static inline void *rtl8169_align(void *data)
4415{
4416 return (void *)ALIGN((long)data, 16);
4417}
4418
0ecbe1ca
SG		 4419static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4420 struct RxDesc *desc)
1da177e4 4421{
6f0333b8 4422 void *data;
1da177e4 4423 dma_addr_t mapping;
48addcc9 4424 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4425 struct net_device *dev = tp->dev;
6f0333b8 4426 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4427
6f0333b8
ED		 4428 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4429 if (!data)
4430 return NULL;
e9f63f30 4431
6f0333b8
ED		 4432 if (rtl8169_align(data) != data) {
4433 kfree(data);
4434 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4435 if (!data)
4436 return NULL;
4437 }
3eafe507 4438
48addcc9 4439 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4440 DMA_FROM_DEVICE);
d827d86b
SG		 4441 if (unlikely(dma_mapping_error(d, mapping))) {
4442 if (net_ratelimit())
4443 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4444 goto err_out;
d827d86b 4445 }
1da177e4
LT		 4446
4447 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4448 return data;
3eafe507
SG		 4449
4450err_out:
4451 kfree(data);
4452 return NULL;
1da177e4
LT		 4453}
4454
4455static void rtl8169_rx_clear(struct rtl8169_private *tp)
4456{
07d3f51f 4457 unsigned int i;
1da177e4
LT		 4458
4459 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4460 if (tp->Rx_databuff[i]) {
4461 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4462 tp->RxDescArray + i);
4463 }
4464 }
4465}
4466
0ecbe1ca 4467static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4468{
0ecbe1ca
SG		 4469 desc->opts1 |= cpu_to_le32(RingEnd);
4470}
5b0384f4 4471
0ecbe1ca
SG		 4472static int rtl8169_rx_fill(struct rtl8169_private *tp)
4473{
4474 unsigned int i;
1da177e4 4475
0ecbe1ca
SG		 4476 for (i = 0; i < NUM_RX_DESC; i++) {
4477 void *data;
4ae47c2d 4478
6f0333b8 4479 if (tp->Rx_databuff[i])
1da177e4 4480 continue;
bcf0bf90 4481
0ecbe1ca 4482 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4483 if (!data) {
4484 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4485 goto err_out;
6f0333b8
ED		 4486 }
4487 tp->Rx_databuff[i] = data;
1da177e4 4488 }
1da177e4 4489
0ecbe1ca
SG		 4490 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4491 return 0;
4492
4493err_out:
4494 rtl8169_rx_clear(tp);
4495 return -ENOMEM;
1da177e4
LT		 4496}
4497
4498static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4499{
4500 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4501}
4502
4503static int rtl8169_init_ring(struct net_device *dev)
4504{
4505 struct rtl8169_private *tp = netdev_priv(dev);
4506
4507 rtl8169_init_ring_indexes(tp);
4508
4509 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4510 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4511
0ecbe1ca 4512 return rtl8169_rx_fill(tp);
1da177e4
LT		 4513}
4514
48addcc9 4515static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4516 struct TxDesc *desc)
4517{
4518 unsigned int len = tx_skb->len;
4519
48addcc9
SG		 4520 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4521
1da177e4
LT		 4522 desc->opts1 = 0x00;
4523 desc->opts2 = 0x00;
4524 desc->addr = 0x00;
4525 tx_skb->len = 0;
4526}
4527
3eafe507
SG		 4528static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4529 unsigned int n)
1da177e4
LT		 4530{
4531 unsigned int i;
4532
3eafe507
SG		 4533 for (i = 0; i < n; i++) {
4534 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4535 struct ring_info *tx_skb = tp->tx_skb + entry;
4536 unsigned int len = tx_skb->len;
4537
4538 if (len) {
4539 struct sk_buff *skb = tx_skb->skb;
4540
48addcc9 4541 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4542 tp->TxDescArray + entry);
4543 if (skb) {
cac4b22f 4544 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4545 dev_kfree_skb(skb);
4546 tx_skb->skb = NULL;
4547 }
1da177e4
LT		 4548 }
4549 }
3eafe507
SG		 4550}
4551
4552static void rtl8169_tx_clear(struct rtl8169_private *tp)
4553{
4554 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4555 tp->cur_tx = tp->dirty_tx = 0;
4556}
4557
c4028958 4558static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4559{
4560 struct rtl8169_private *tp = netdev_priv(dev);
4561
c4028958 4562 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4563 schedule_delayed_work(&tp->task, 4);
4564}
4565
4566static void rtl8169_wait_for_quiescence(struct net_device *dev)
4567{
4568 struct rtl8169_private *tp = netdev_priv(dev);
4569 void __iomem *ioaddr = tp->mmio_addr;
4570
4571 synchronize_irq(dev->irq);
4572
4573 /* Wait for any pending NAPI task to complete */
bea3348e 4574 napi_disable(&tp->napi);
1da177e4
LT		 4575
4576 rtl8169_irq_mask_and_ack(ioaddr);
4577
d1d08d12
DM		 4578 tp->intr_mask = 0xffff;
4579 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4580 napi_enable(&tp->napi);
1da177e4
LT		 4581}
4582
c4028958 4583static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4584{
c4028958
DH		 4585 struct rtl8169_private *tp =
4586 container_of(work, struct rtl8169_private, task.work);
4587 struct net_device *dev = tp->dev;
1da177e4
LT		 4588 int ret;
4589
eb2a021c
FR		 4590 rtnl_lock();
4591
4592 if (!netif_running(dev))
4593 goto out_unlock;
4594
4595 rtl8169_wait_for_quiescence(dev);
4596 rtl8169_close(dev);
1da177e4
LT		 4597
4598 ret = rtl8169_open(dev);
4599 if (unlikely(ret < 0)) {
bf82c189
JP		 4600 if (net_ratelimit())
4601 netif_err(tp, drv, dev,
4602 "reinit failure (status = %d). Rescheduling\n",
4603 ret);
1da177e4
LT		 4604 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4605 }
eb2a021c
FR		 4606
4607out_unlock:
4608 rtnl_unlock();
1da177e4
LT		 4609}
4610
c4028958 4611static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4612{
c4028958
DH		 4613 struct rtl8169_private *tp =
4614 container_of(work, struct rtl8169_private, task.work);
4615 struct net_device *dev = tp->dev;
1da177e4 4616
eb2a021c
FR		 4617 rtnl_lock();
4618
1da177e4 4619 if (!netif_running(dev))
eb2a021c 4620 goto out_unlock;
1da177e4
LT		 4621
4622 rtl8169_wait_for_quiescence(dev);
4623
bea3348e 4624 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4625 rtl8169_tx_clear(tp);
4626
4627 if (tp->dirty_rx == tp->cur_rx) {
4628 rtl8169_init_ring_indexes(tp);
07ce4064 4629 rtl_hw_start(dev);
1da177e4 4630 netif_wake_queue(dev);
cebf8cc7 4631 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4632 } else {
bf82c189
JP		 4633 if (net_ratelimit())
4634 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4635 rtl8169_schedule_work(dev, rtl8169_reset_task);
4636 }
eb2a021c
FR		 4637
4638out_unlock:
4639 rtnl_unlock();
1da177e4
LT		 4640}
4641
4642static void rtl8169_tx_timeout(struct net_device *dev)
4643{
4644 struct rtl8169_private *tp = netdev_priv(dev);
4645
e6de30d6 4646 rtl8169_hw_reset(tp);
1da177e4
LT		 4647
4648 /* Let's wait a bit while any (async) irq lands on */
4649 rtl8169_schedule_work(dev, rtl8169_reset_task);
4650}
4651
4652static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4653 u32 *opts)
1da177e4
LT		 4654{
4655 struct skb_shared_info *info = skb_shinfo(skb);
4656 unsigned int cur_frag, entry;
a6343afb 4657 struct TxDesc * uninitialized_var(txd);
48addcc9 4658 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4659
4660 entry = tp->cur_tx;
4661 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4662 skb_frag_t *frag = info->frags + cur_frag;
4663 dma_addr_t mapping;
4664 u32 status, len;
4665 void *addr;
4666
4667 entry = (entry + 1) % NUM_TX_DESC;
4668
4669 txd = tp->TxDescArray + entry;
4670 len = frag->size;
4671 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4672 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4673 if (unlikely(dma_mapping_error(d, mapping))) {
4674 if (net_ratelimit())
4675 netif_err(tp, drv, tp->dev,
4676 "Failed to map TX fragments DMA!\n");
3eafe507 4677 goto err_out;
d827d86b 4678 }
1da177e4
LT		 4679
4680 /* anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4681 status = opts[0] | len |
4682 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4683
4684 txd->opts1 = cpu_to_le32(status);
2b7b4318 4685 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4686 txd->addr = cpu_to_le64(mapping);
4687
4688 tp->tx_skb[entry].len = len;
4689 }
4690
4691 if (cur_frag) {
4692 tp->tx_skb[entry].skb = skb;
4693 txd->opts1 |= cpu_to_le32(LastFrag);
4694 }
4695
4696 return cur_frag;
3eafe507
SG		 4697
4698err_out:
4699 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4700 return -EIO;
1da177e4
LT		 4701}
4702
2b7b4318
FR		 4703static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4704 struct sk_buff *skb, u32 *opts)
1da177e4 4705{
2b7b4318 4706 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4707 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4708 int offset = info->opts_offset;
350fb32a 4709
2b7b4318
FR		 4710 if (mss) {
4711 opts[0] |= TD_LSO;
4712 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4713 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4714 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4715
4716 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4717 opts[offset] |= info->checksum.tcp;
1da177e4 4718 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4719 opts[offset] |= info->checksum.udp;
4720 else
4721 WARN_ON_ONCE(1);
1da177e4 4722 }
1da177e4
LT		 4723}
4724
61357325
SH		 4725static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4726 struct net_device *dev)
1da177e4
LT		 4727{
4728 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4729 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4730 struct TxDesc *txd = tp->TxDescArray + entry;
4731 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4732 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4733 dma_addr_t mapping;
4734 u32 status, len;
2b7b4318 4735 u32 opts[2];
3eafe507 4736 int frags;
5b0384f4 4737
1da177e4 4738 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4739 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4740 goto err_stop_0;
1da177e4
LT		 4741 }
4742
4743 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4744 goto err_stop_0;
4745
4746 len = skb_headlen(skb);
48addcc9 4747 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4748 if (unlikely(dma_mapping_error(d, mapping))) {
4749 if (net_ratelimit())
4750 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4751 goto err_dma_0;
d827d86b 4752 }
3eafe507
SG		 4753
4754 tp->tx_skb[entry].len = len;
4755 txd->addr = cpu_to_le64(mapping);
1da177e4 4756
2b7b4318
FR		 4757 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4758 opts[0] = DescOwn;
1da177e4 4759
2b7b4318
FR		 4760 rtl8169_tso_csum(tp, skb, opts);
4761
4762 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4763 if (frags < 0)
4764 goto err_dma_1;
4765 else if (frags)
2b7b4318 4766 opts[0] |= FirstFrag;
3eafe507 4767 else {
2b7b4318 4768 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4769 tp->tx_skb[entry].skb = skb;
4770 }
4771
2b7b4318
FR		 4772 txd->opts2 = cpu_to_le32(opts[1]);
4773
1da177e4
LT		 4774 wmb();
4775
4776 /* anti gcc 2.95.3 bugware (sic) */
2b7b4318 4777 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4778 txd->opts1 = cpu_to_le32(status);
4779
1da177e4
LT		 4780 tp->cur_tx += frags + 1;
4781
4c020a96 4782 wmb();
1da177e4 4783
275391a4 4784 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4785
4786 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4787 netif_stop_queue(dev);
4788 smp_rmb();
4789 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4790 netif_wake_queue(dev);
4791 }
4792
61357325 4793 return NETDEV_TX_OK;
1da177e4 4794
3eafe507 4795err_dma_1:
48addcc9 4796 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4797err_dma_0:
4798 dev_kfree_skb(skb);
4799 dev->stats.tx_dropped++;
4800 return NETDEV_TX_OK;
4801
4802err_stop_0:
1da177e4 4803 netif_stop_queue(dev);
cebf8cc7 4804 dev->stats.tx_dropped++;
61357325 4805 return NETDEV_TX_BUSY;
1da177e4
LT		 4806}
4807
4808static void rtl8169_pcierr_interrupt(struct net_device *dev)
4809{
4810 struct rtl8169_private *tp = netdev_priv(dev);
4811 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4812 u16 pci_status, pci_cmd;
4813
4814 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4815 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4816
bf82c189
JP		 4817 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4818 pci_cmd, pci_status);
1da177e4
LT		 4819
4820 /*
4821 * The recovery sequence below admits a very elaborated explanation:
4822 * - it seems to work;
d03902b8
FR		 4823 * - I did not see what else could be done;
4824 * - it makes iop3xx happy.
1da177e4
LT		 4825 *
4826 * Feel free to adjust to your needs.
4827 */
a27993f3 4828 if (pdev->broken_parity_status)
d03902b8
FR		 4829 pci_cmd &= ~PCI_COMMAND_PARITY;
4830 else
4831 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4832
4833 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4834
4835 pci_write_config_word(pdev, PCI_STATUS,
4836 pci_status & (PCI_STATUS_DETECTED_PARITY |
4837 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4838 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4839
4840 /* The infamous DAC f*ckup only happens at boot time */
4841 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4842 void __iomem *ioaddr = tp->mmio_addr;
4843
bf82c189 4844 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4845 tp->cp_cmd &= ~PCIDAC;
4846 RTL_W16(CPlusCmd, tp->cp_cmd);
4847 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4848 }
4849
e6de30d6 4850 rtl8169_hw_reset(tp);
d03902b8
FR		 4851
4852 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4853}
4854
07d3f51f
FR		 4855static void rtl8169_tx_interrupt(struct net_device *dev,
4856 struct rtl8169_private *tp,
4857 void __iomem *ioaddr)
1da177e4
LT		 4858{
4859 unsigned int dirty_tx, tx_left;
4860
1da177e4
LT		 4861 dirty_tx = tp->dirty_tx;
4862 smp_rmb();
4863 tx_left = tp->cur_tx - dirty_tx;
4864
4865 while (tx_left > 0) {
4866 unsigned int entry = dirty_tx % NUM_TX_DESC;
4867 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4868 u32 status;
4869
4870 rmb();
4871 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4872 if (status & DescOwn)
4873 break;
4874
48addcc9
SG		 4875 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4876 tp->TxDescArray + entry);
1da177e4 4877 if (status & LastFrag) {
cac4b22f
SG		 4878 dev->stats.tx_packets++;
4879 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4880 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4881 tx_skb->skb = NULL;
4882 }
4883 dirty_tx++;
4884 tx_left--;
4885 }
4886
4887 if (tp->dirty_tx != dirty_tx) {
4888 tp->dirty_tx = dirty_tx;
4889 smp_wmb();
4890 if (netif_queue_stopped(dev) &&
4891 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4892 netif_wake_queue(dev);
4893 }
d78ae2dc
FR		 4894 /*
4895 * 8168 hack: TxPoll requests are lost when the Tx packets are
4896 * too close. Let's kick an extra TxPoll request when a burst
4897 * of start_xmit activity is detected (if it is not detected,
4898 * it is slow enough). -- FR
4899 */
4900 smp_rmb();
4901 if (tp->cur_tx != dirty_tx)
4902 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4903 }
4904}
4905
126fa4b9
FR		 4906static inline int rtl8169_fragmented_frame(u32 status)
4907{
4908 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4909}
4910
adea1ac7 4911static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4912{
1da177e4
LT		 4913 u32 status = opts1 & RxProtoMask;
4914
4915 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4916 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4917 skb->ip_summed = CHECKSUM_UNNECESSARY;
4918 else
bc8acf2c 4919 skb_checksum_none_assert(skb);
1da177e4
LT		 4920}
4921
6f0333b8
ED		 4922static struct sk_buff *rtl8169_try_rx_copy(void *data,
4923 struct rtl8169_private *tp,
4924 int pkt_size,
4925 dma_addr_t addr)
1da177e4 4926{
b449655f 4927 struct sk_buff *skb;
48addcc9 4928 struct device *d = &tp->pci_dev->dev;
b449655f 4929
6f0333b8 4930 data = rtl8169_align(data);
48addcc9 4931 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4932 prefetch(data);
4933 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4934 if (skb)
4935 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4936 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4937
6f0333b8 4938 return skb;
1da177e4
LT		 4939}
4940
630b943c
ED		 4941/*
4942 * Warning : rtl8169_rx_interrupt() might be called :
4943 * 1) from NAPI (softirq) context
4944 * (polling = 1 : we should call netif_receive_skb())
4945 * 2) from process context (rtl8169_reset_task())
4946 * (polling = 0 : we must call netif_rx() instead)
4947 */
07d3f51f
FR		 4948static int rtl8169_rx_interrupt(struct net_device *dev,
4949 struct rtl8169_private *tp,
bea3348e 4950 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4951{
4952 unsigned int cur_rx, rx_left;
6f0333b8 4953 unsigned int count;
630b943c 4954 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4955
1da177e4
LT		 4956 cur_rx = tp->cur_rx;
4957 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4958 rx_left = min(rx_left, budget);
1da177e4 4959
4dcb7d33 4960 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4961 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4962 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4963 u32 status;
4964
4965 rmb();
126fa4b9 4966 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4967
4968 if (status & DescOwn)
4969 break;
4dcb7d33 4970 if (unlikely(status & RxRES)) {
bf82c189
JP		 4971 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4972 status);
cebf8cc7 4973 dev->stats.rx_errors++;
1da177e4 4974 if (status & (RxRWT | RxRUNT))
cebf8cc7 4975 dev->stats.rx_length_errors++;
1da177e4 4976 if (status & RxCRC)
cebf8cc7 4977 dev->stats.rx_crc_errors++;
9dccf611
FR		 4978 if (status & RxFOVF) {
4979 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4980 dev->stats.rx_fifo_errors++;
9dccf611 4981 }
6f0333b8 4982 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4983 } else {
6f0333b8 4984 struct sk_buff *skb;
b449655f 4985 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4986 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4987
126fa4b9
FR		 4988 /*
4989 * The driver does not support incoming fragmented
4990 * frames. They are seen as a symptom of over-mtu
4991 * sized frames.
4992 */
4993 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4994 dev->stats.rx_dropped++;
4995 dev->stats.rx_length_errors++;
6f0333b8 4996 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4997 continue;
126fa4b9
FR		 4998 }
4999
6f0333b8
ED		 5000 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5001 tp, pkt_size, addr);
5002 rtl8169_mark_to_asic(desc, rx_buf_sz);
5003 if (!skb) {
5004 dev->stats.rx_dropped++;
5005 continue;
1da177e4
LT		 5006 }
5007
adea1ac7 5008 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5009 skb_put(skb, pkt_size);
5010 skb->protocol = eth_type_trans(skb, dev);
5011
7a8fc77b
FR		 5012 rtl8169_rx_vlan_tag(desc, skb);
5013
5014 if (likely(polling))
5015 napi_gro_receive(&tp->napi, skb);
5016 else
5017 netif_rx(skb);
1da177e4 5018
cebf8cc7
FR		 5019 dev->stats.rx_bytes += pkt_size;
5020 dev->stats.rx_packets++;
1da177e4 5021 }
6dccd16b
FR		 5022
5023 /* Work around for AMD plateform. */
95e0918d 5024 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5025 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5026 desc->opts2 = 0;
5027 cur_rx++;
5028 }
1da177e4
LT		 5029 }
5030
5031 count = cur_rx - tp->cur_rx;
5032 tp->cur_rx = cur_rx;
5033
6f0333b8 5034 tp->dirty_rx += count;
1da177e4
LT		 5035
5036 return count;
5037}
5038
07d3f51f 5039static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5040{
07d3f51f 5041 struct net_device *dev = dev_instance;
1da177e4 5042 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5043 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5044 int handled = 0;
865c652d 5045 int status;
1da177e4 5046
f11a377b
DD		 5047 /* loop handling interrupts until we have no new ones or
5048 * we hit a invalid/hotplug case.
5049 */
865c652d 5050 status = RTL_R16(IntrStatus);
f11a377b
DD		 5051 while (status && status != 0xffff) {
5052 handled = 1;
1da177e4 5053
f11a377b
DD		 5054 /* Handle all of the error cases first. These will reset
5055 * the chip, so just exit the loop.
5056 */
5057 if (unlikely(!netif_running(dev))) {
5058 rtl8169_asic_down(ioaddr);
5059 break;
5060 }
1da177e4 5061
1519e57f
FR		 5062 if (unlikely(status & RxFIFOOver)) {
5063 switch (tp->mac_version) {
5064 /* Work around for rx fifo overflow */
5065 case RTL_GIGA_MAC_VER_11:
5066 case RTL_GIGA_MAC_VER_22:
5067 case RTL_GIGA_MAC_VER_26:
5068 netif_stop_queue(dev);
5069 rtl8169_tx_timeout(dev);
5070 goto done;
f60ac8e7
FR		 5071 /* Testers needed. */
5072 case RTL_GIGA_MAC_VER_17:
5073 case RTL_GIGA_MAC_VER_19:
5074 case RTL_GIGA_MAC_VER_20:
5075 case RTL_GIGA_MAC_VER_21:
5076 case RTL_GIGA_MAC_VER_23:
5077 case RTL_GIGA_MAC_VER_24:
5078 case RTL_GIGA_MAC_VER_27:
5079 case RTL_GIGA_MAC_VER_28:
4804b3b3 5080 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5081 /* Experimental science. Pktgen proof. */
5082 case RTL_GIGA_MAC_VER_12:
5083 case RTL_GIGA_MAC_VER_25:
5084 if (status == RxFIFOOver)
5085 goto done;
5086 break;
5087 default:
5088 break;
5089 }
f11a377b 5090 }
1da177e4 5091
f11a377b
DD		 5092 if (unlikely(status & SYSErr)) {
5093 rtl8169_pcierr_interrupt(dev);
5094 break;
5095 }
1da177e4 5096
f11a377b 5097 if (status & LinkChg)
e4fbce74 5098 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5099
f11a377b
DD		 5100 /* We need to see the lastest version of tp->intr_mask to
5101 * avoid ignoring an MSI interrupt and having to wait for
5102 * another event which may never come.
5103 */
5104 smp_rmb();
5105 if (status & tp->intr_mask & tp->napi_event) {
5106 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5107 tp->intr_mask = ~tp->napi_event;
5108
5109 if (likely(napi_schedule_prep(&tp->napi)))
5110 __napi_schedule(&tp->napi);
bf82c189
JP		 5111 else
5112 netif_info(tp, intr, dev,
5113 "interrupt %04x in poll\n", status);
f11a377b 5114 }
1da177e4 5115
f11a377b
DD		 5116 /* We only get a new MSI interrupt when all active irq
5117 * sources on the chip have been acknowledged. So, ack
5118 * everything we've seen and check if new sources have become
5119 * active to avoid blocking all interrupts from the chip.
5120 */
5121 RTL_W16(IntrStatus,
5122 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5123 status = RTL_R16(IntrStatus);
865c652d 5124 }
1519e57f 5125done:
1da177e4
LT		 5126 return IRQ_RETVAL(handled);
5127}
5128
bea3348e 5129static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5130{
bea3348e
SH		 5131 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5132 struct net_device *dev = tp->dev;
1da177e4 5133 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5134 int work_done;
1da177e4 5135
bea3348e 5136 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5137 rtl8169_tx_interrupt(dev, tp, ioaddr);
5138
bea3348e 5139 if (work_done < budget) {
288379f0 5140 napi_complete(napi);
f11a377b
DD		 5141
5142 /* We need for force the visibility of tp->intr_mask
5143 * for other CPUs, as we can loose an MSI interrupt
5144 * and potentially wait for a retransmit timeout if we don't.
5145 * The posted write to IntrMask is safe, as it will
5146 * eventually make it to the chip and we won't loose anything
5147 * until it does.
1da177e4 5148 */
f11a377b 5149 tp->intr_mask = 0xffff;
4c020a96 5150 wmb();
0e485150 5151 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5152 }
5153
bea3348e 5154 return work_done;
1da177e4 5155}
1da177e4 5156
523a6094
FR		 5157static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5158{
5159 struct rtl8169_private *tp = netdev_priv(dev);
5160
5161 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5162 return;
5163
5164 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5165 RTL_W32(RxMissed, 0);
5166}
5167
1da177e4
LT		 5168static void rtl8169_down(struct net_device *dev)
5169{
5170 struct rtl8169_private *tp = netdev_priv(dev);
5171 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 5172
5173 rtl8169_delete_timer(dev);
5174
5175 netif_stop_queue(dev);
5176
93dd79e8 5177 napi_disable(&tp->napi);
93dd79e8 5178
1da177e4
LT		 5179 spin_lock_irq(&tp->lock);
5180
5181 rtl8169_asic_down(ioaddr);
323bb685
SG		 5182 /*
5183 * At this point device interrupts can not be enabled in any function,
5184 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5185 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5186 */
523a6094 5187 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5188
5189 spin_unlock_irq(&tp->lock);
5190
5191 synchronize_irq(dev->irq);
5192
1da177e4 5193 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5194 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5195
1da177e4
LT		 5196 rtl8169_tx_clear(tp);
5197
5198 rtl8169_rx_clear(tp);
065c27c1 5199
5200 rtl_pll_power_down(tp);
1da177e4
LT		 5201}
5202
5203static int rtl8169_close(struct net_device *dev)
5204{
5205 struct rtl8169_private *tp = netdev_priv(dev);
5206 struct pci_dev *pdev = tp->pci_dev;
5207
e1759441
RW		 5208 pm_runtime_get_sync(&pdev->dev);
5209
355423d0
IV		 5210 /* update counters before going down */
5211 rtl8169_update_counters(dev);
5212
1da177e4
LT		 5213 rtl8169_down(dev);
5214
5215 free_irq(dev->irq, dev);
5216
82553bb6
SG		 5217 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5218 tp->RxPhyAddr);
5219 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5220 tp->TxPhyAddr);
1da177e4
LT		 5221 tp->TxDescArray = NULL;
5222 tp->RxDescArray = NULL;
5223
e1759441
RW		 5224 pm_runtime_put_sync(&pdev->dev);
5225
1da177e4
LT		 5226 return 0;
5227}
5228
07ce4064 5229static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5230{
5231 struct rtl8169_private *tp = netdev_priv(dev);
5232 void __iomem *ioaddr = tp->mmio_addr;
5233 unsigned long flags;
5234 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5235 int rx_mode;
1da177e4
LT		 5236 u32 tmp = 0;
5237
5238 if (dev->flags & IFF_PROMISC) {
5239 /* Unconditionally log net taps. */
bf82c189 5240 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5241 rx_mode =
5242 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5243 AcceptAllPhys;
5244 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5245 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5246 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5247 /* Too many to filter perfectly -- accept all multicasts. */
5248 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5249 mc_filter[1] = mc_filter[0] = 0xffffffff;
5250 } else {
22bedad3 5251 struct netdev_hw_addr *ha;
07d3f51f 5252
1da177e4
LT		 5253 rx_mode = AcceptBroadcast | AcceptMyPhys;
5254 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5255 netdev_for_each_mc_addr(ha, dev) {
5256 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5257 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5258 rx_mode |= AcceptMulticast;
5259 }
5260 }
5261
5262 spin_lock_irqsave(&tp->lock, flags);
5263
5264 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5265 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5266
f887cce8 5267 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5268 u32 data = mc_filter[0];
5269
5270 mc_filter[0] = swab32(mc_filter[1]);
5271 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5272 }
5273
1da177e4 5274 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5275 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5276
57a9f236
FR		 5277 RTL_W32(RxConfig, tmp);
5278
1da177e4
LT		 5279 spin_unlock_irqrestore(&tp->lock, flags);
5280}
5281
5282/**
5283 * rtl8169_get_stats - Get rtl8169 read/write statistics
5284 * @dev: The Ethernet Device to get statistics for
5285 *
5286 * Get TX/RX statistics for rtl8169
5287 */
5288static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5289{
5290 struct rtl8169_private *tp = netdev_priv(dev);
5291 void __iomem *ioaddr = tp->mmio_addr;
5292 unsigned long flags;
5293
5294 if (netif_running(dev)) {
5295 spin_lock_irqsave(&tp->lock, flags);
523a6094 5296 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5297 spin_unlock_irqrestore(&tp->lock, flags);
5298 }
5b0384f4 5299
cebf8cc7 5300 return &dev->stats;
1da177e4
LT		 5301}
5302
861ab440 5303static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5304{
065c27c1 5305 struct rtl8169_private *tp = netdev_priv(dev);
5306
5d06a99f 5307 if (!netif_running(dev))
861ab440 5308 return;
5d06a99f 5309
065c27c1 5310 rtl_pll_power_down(tp);
5311
5d06a99f
FR		 5312 netif_device_detach(dev);
5313 netif_stop_queue(dev);
861ab440
RW		 5314}
5315
5316#ifdef CONFIG_PM
5317
5318static int rtl8169_suspend(struct device *device)
5319{
5320 struct pci_dev *pdev = to_pci_dev(device);
5321 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5322
861ab440 5323 rtl8169_net_suspend(dev);
1371fa6d 5324
5d06a99f
FR		 5325 return 0;
5326}
5327
e1759441
RW		 5328static void __rtl8169_resume(struct net_device *dev)
5329{
065c27c1 5330 struct rtl8169_private *tp = netdev_priv(dev);
5331
e1759441 5332 netif_device_attach(dev);
065c27c1 5333
5334 rtl_pll_power_up(tp);
5335
e1759441
RW		 5336 rtl8169_schedule_work(dev, rtl8169_reset_task);
5337}
5338
861ab440 5339static int rtl8169_resume(struct device *device)
5d06a99f 5340{
861ab440 5341 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5342 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5343 struct rtl8169_private *tp = netdev_priv(dev);
5344
5345 rtl8169_init_phy(dev, tp);
5d06a99f 5346
e1759441
RW		 5347 if (netif_running(dev))
5348 __rtl8169_resume(dev);
5d06a99f 5349
e1759441
RW		 5350 return 0;
5351}
5352
5353static int rtl8169_runtime_suspend(struct device *device)
5354{
5355 struct pci_dev *pdev = to_pci_dev(device);
5356 struct net_device *dev = pci_get_drvdata(pdev);
5357 struct rtl8169_private *tp = netdev_priv(dev);
5358
5359 if (!tp->TxDescArray)
5360 return 0;
5361
5362 spin_lock_irq(&tp->lock);
5363 tp->saved_wolopts = __rtl8169_get_wol(tp);
5364 __rtl8169_set_wol(tp, WAKE_ANY);
5365 spin_unlock_irq(&tp->lock);
5366
5367 rtl8169_net_suspend(dev);
5368
5369 return 0;
5370}
5371
5372static int rtl8169_runtime_resume(struct device *device)
5373{
5374 struct pci_dev *pdev = to_pci_dev(device);
5375 struct net_device *dev = pci_get_drvdata(pdev);
5376 struct rtl8169_private *tp = netdev_priv(dev);
5377
5378 if (!tp->TxDescArray)
5379 return 0;
5380
5381 spin_lock_irq(&tp->lock);
5382 __rtl8169_set_wol(tp, tp->saved_wolopts);
5383 tp->saved_wolopts = 0;
5384 spin_unlock_irq(&tp->lock);
5385
fccec10b
SG		 5386 rtl8169_init_phy(dev, tp);
5387
e1759441 5388 __rtl8169_resume(dev);
5d06a99f 5389
5d06a99f
FR		 5390 return 0;
5391}
5392
e1759441
RW		 5393static int rtl8169_runtime_idle(struct device *device)
5394{
5395 struct pci_dev *pdev = to_pci_dev(device);
5396 struct net_device *dev = pci_get_drvdata(pdev);
5397 struct rtl8169_private *tp = netdev_priv(dev);
5398
e4fbce74 5399 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5400}
5401
47145210 5402static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 5403 .suspend = rtl8169_suspend,
5404 .resume = rtl8169_resume,
5405 .freeze = rtl8169_suspend,
5406 .thaw = rtl8169_resume,
5407 .poweroff = rtl8169_suspend,
5408 .restore = rtl8169_resume,
e1759441
RW		 5409 .runtime_suspend = rtl8169_runtime_suspend,
5410 .runtime_resume = rtl8169_runtime_resume,
5411 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5412};
5413
5414#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5415
5416#else /* !CONFIG_PM */
5417
5418#define RTL8169_PM_OPS NULL
5419
5420#endif /* !CONFIG_PM */
5421
1765f95d
FR		 5422static void rtl_shutdown(struct pci_dev *pdev)
5423{
861ab440 5424 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5425 struct rtl8169_private *tp = netdev_priv(dev);
5426 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5427
5428 rtl8169_net_suspend(dev);
1765f95d 5429
cc098dc7
IV		 5430 /* restore original MAC address */
5431 rtl_rar_set(tp, dev->perm_addr);
5432
4bb3f522 5433 spin_lock_irq(&tp->lock);
5434
5435 rtl8169_asic_down(ioaddr);
5436
5437 spin_unlock_irq(&tp->lock);
5438
861ab440 5439 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5440 /* WoL fails with some 8168 when the receiver is disabled. */
5441 if (tp->features & RTL_FEATURE_WOL) {
5442 pci_clear_master(pdev);
5443
5444 RTL_W8(ChipCmd, CmdRxEnb);
5445 /* PCI commit */
5446 RTL_R8(ChipCmd);
5447 }
5448
861ab440
RW		 5449 pci_wake_from_d3(pdev, true);
5450 pci_set_power_state(pdev, PCI_D3hot);
5451 }
5452}
5d06a99f 5453
1da177e4
LT		 5454static struct pci_driver rtl8169_pci_driver = {
5455 .name = MODULENAME,
5456 .id_table = rtl8169_pci_tbl,
5457 .probe = rtl8169_init_one,
5458 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5459 .shutdown = rtl_shutdown,
861ab440 5460 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5461};
5462
07d3f51f 5463static int __init rtl8169_init_module(void)
1da177e4 5464{
29917620 5465 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5466}
5467
07d3f51f 5468static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5469{
5470 pci_unregister_driver(&rtl8169_pci_driver);
5471}
5472
5473module_init(rtl8169_init_module);
5474module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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