[deliverable/linux.git] / drivers / net / r8169.c

/*
=========================================================================
 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
 --------------------------------------------------------------------

 History:
 Feb  4 2002	- created initially by ShuChen <shuchen@realtek.com.tw>.
 May 20 2002	- Add link status force-mode and TBI mode support.
	2004	- Massive updates. See kernel SCM system for details.
=========================================================================
  1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
	 Command: 'insmod r8169 media = SET_MEDIA'
	 Ex:	  'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.

	 SET_MEDIA can be:
 		_10_Half	= 0x01
 		_10_Full	= 0x02
 		_100_Half	= 0x04
 		_100_Full	= 0x08
 		_1000_Full	= 0x10

  2. Support TBI mode.
=========================================================================
VERSION 1.1	<2002/10/4>

	The bit4:0 of MII register 4 is called "selector field", and have to be
	00001b to indicate support of IEEE std 802.3 during NWay process of
	exchanging Link Code Word (FLP).

VERSION 1.2	<2002/11/30>

	- Large style cleanup
	- Use ether_crc in stock kernel (linux/crc32.h)
	- Copy mc_filter setup code from 8139cp
	  (includes an optimization, and avoids set_bit use)

VERSION 1.6LK	<2004/04/14>

	- Merge of Realtek's version 1.6
	- Conversion to DMA API
	- Suspend/resume
	- Endianness
	- Misc Rx/Tx bugs

VERSION 2.2LK	<2005/01/25>

	- RX csum, TX csum/SG, TSO
	- VLAN
	- baby (< 7200) Jumbo frames support
	- Merge of Realtek's version 2.2 (new phy)
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>

#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_R8169_NAPI
#define NAPI_SUFFIX	"-NAPI"
#else
#define NAPI_SUFFIX	""
#endif

#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
#define MODULENAME "r8169"
#define PFX MODULENAME ": "

#ifdef RTL8169_DEBUG
#define assert(expr) \
	if (!(expr)) {					\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
		#expr,__FILE__,__FUNCTION__,__LINE__);		\
	}
#define dprintk(fmt, args...)	do { printk(PFX fmt, ## args); } while (0)
#else
#define assert(expr) do {} while (0)
#define dprintk(fmt, args...)	do {} while (0)
#endif /* RTL8169_DEBUG */

#define R8169_MSG_DEFAULT \
	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

#define TX_BUFFS_AVAIL(tp) \
	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

#ifdef CONFIG_R8169_NAPI
#define rtl8169_rx_skb			netif_receive_skb
#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_receive_skb
#define rtl8169_rx_quota(count, quota)	min(count, quota)
#else
#define rtl8169_rx_skb			netif_rx
#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_rx
#define rtl8169_rx_quota(count, quota)	count
#endif

/* media options */
#define MAX_UNITS 8
static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
static int num_media = 0;

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
static const int max_interrupt_work = 20;

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
static const int multicast_filter_limit = 32;

/* MAC address length */
#define MAC_ADDR_LEN	6

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
#define EarlyTxThld 	0x3F	/* 0x3F means NO early transmit */
#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */
#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */
#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
#define R8169_NAPI_WEIGHT	64
#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */
#define RX_BUF_SIZE	1536	/* Rx Buffer size */
#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

#define RTL8169_TX_TIMEOUT	(6*HZ)
#define RTL8169_PHY_TIMEOUT	(10*HZ)

/* write/read MMIO register */
#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)		readb (ioaddr + (reg))
#define RTL_R16(reg)		readw (ioaddr + (reg))
#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

enum mac_version {
	RTL_GIGA_MAC_VER_01 = 0x00,
	RTL_GIGA_MAC_VER_02 = 0x01,
	RTL_GIGA_MAC_VER_03 = 0x02,
	RTL_GIGA_MAC_VER_04 = 0x03,
	RTL_GIGA_MAC_VER_05 = 0x04,
	RTL_GIGA_MAC_VER_11 = 0x0b,
	RTL_GIGA_MAC_VER_12 = 0x0c,
	RTL_GIGA_MAC_VER_13 = 0x0d,
	RTL_GIGA_MAC_VER_14 = 0x0e,
	RTL_GIGA_MAC_VER_15 = 0x0f
};

enum phy_version {
	RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
	RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
	RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
};

#define _R(NAME,MAC,MASK) \
	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

static const struct {
	const char *name;
	u8 mac_version;
	u32 RxConfigMask;	/* Clears the bits supported by this chip */
} rtl_chip_info[] = {
	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880),
	_R("RTL8169s/8110s",	RTL_GIGA_MAC_VER_02, 0xff7e1880),
	_R("RTL8169s/8110s",	RTL_GIGA_MAC_VER_03, 0xff7e1880),
	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880),
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880),
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
};
#undef _R

enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

static const struct {
	unsigned int region;
	unsigned int align;
} rtl_cfg_info[] = {
	[RTL_CFG_0] = { 1, NET_IP_ALIGN },
	[RTL_CFG_1] = { 2, NET_IP_ALIGN },
	[RTL_CFG_2] = { 2, 8 }
};

static struct pci_device_id rtl8169_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_2 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
Commit	Line	Data
1da177e4 LT	1	/*
	2	=========================================================================
	3	r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
	4	--------------------------------------------------------------------
	5
	6	History:
	7	Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
	8	May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4	9	2004 - Massive updates. See kernel SCM system for details.
1da177e4 LT	10	=========================================================================
	11	1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
	12	Command: 'insmod r8169 media = SET_MEDIA'
	13	Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
5b0384f4	14
1da177e4 LT	15	SET_MEDIA can be:
	16	_10_Half = 0x01
	17	_10_Full = 0x02
	18	_100_Half = 0x04
	19	_100_Full = 0x08
	20	_1000_Full = 0x10
5b0384f4	21
1da177e4 LT	22	2. Support TBI mode.
	23	=========================================================================
	24	VERSION 1.1 <2002/10/4>
	25
	26	The bit4:0 of MII register 4 is called "selector field", and have to be
	27	00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4	28	exchanging Link Code Word (FLP).
1da177e4 LT	29
	30	VERSION 1.2 <2002/11/30>
	31
	32	- Large style cleanup
	33	- Use ether_crc in stock kernel (linux/crc32.h)
	34	- Copy mc_filter setup code from 8139cp
	35	(includes an optimization, and avoids set_bit use)
	36
	37	VERSION 1.6LK <2004/04/14>
	38
	39	- Merge of Realtek's version 1.6
	40	- Conversion to DMA API
	41	- Suspend/resume
	42	- Endianness
	43	- Misc Rx/Tx bugs
	44
	45	VERSION 2.2LK <2005/01/25>
	46
	47	- RX csum, TX csum/SG, TSO
	48	- VLAN
	49	- baby (< 7200) Jumbo frames support
	50	- Merge of Realtek's version 2.2 (new phy)
	51	*/
	52
	53	#include <linux/module.h>
	54	#include <linux/moduleparam.h>
	55	#include <linux/pci.h>
	56	#include <linux/netdevice.h>
	57	#include <linux/etherdevice.h>
	58	#include <linux/delay.h>
	59	#include <linux/ethtool.h>
	60	#include <linux/mii.h>
	61	#include <linux/if_vlan.h>
	62	#include <linux/crc32.h>
	63	#include <linux/in.h>
	64	#include <linux/ip.h>
	65	#include <linux/tcp.h>
	66	#include <linux/init.h>
	67	#include <linux/dma-mapping.h>
	68
	69	#include <asm/io.h>
	70	#include <asm/irq.h>
	71
f7ccf420 SH	72	#ifdef CONFIG_R8169_NAPI
	73	#define NAPI_SUFFIX "-NAPI"
	74	#else
	75	#define NAPI_SUFFIX ""
	76	#endif
	77
	78	#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4 LT	79	#define MODULENAME "r8169"
	80	#define PFX MODULENAME ": "
	81
	82	#ifdef RTL8169_DEBUG
	83	#define assert(expr) \
5b0384f4 FR	84	if (!(expr)) { \
	85	printk( "Assertion failed! %s,%s,%s,line=%d\n", \
	86	#expr,__FILE__,__FUNCTION__,__LINE__); \
	87	}
1da177e4 LT	88	#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
	89	#else
	90	#define assert(expr) do {} while (0)
	91	#define dprintk(fmt, args...) do {} while (0)
	92	#endif /* RTL8169_DEBUG */
	93
b57b7e5a	94	#define R8169_MSG_DEFAULT \
f0e837d9	95	(NETIF_MSG_DRV \| NETIF_MSG_PROBE \| NETIF_MSG_IFUP \| NETIF_MSG_IFDOWN)
b57b7e5a	96
1da177e4 LT	97	#define TX_BUFFS_AVAIL(tp) \
	98	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
	99
	100	#ifdef CONFIG_R8169_NAPI
	101	#define rtl8169_rx_skb netif_receive_skb
0b50f81d	102	#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4 LT	103	#define rtl8169_rx_quota(count, quota) min(count, quota)
	104	#else
	105	#define rtl8169_rx_skb netif_rx
0b50f81d	106	#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4 LT	107	#define rtl8169_rx_quota(count, quota) count
	108	#endif
	109
	110	/* media options */
	111	#define MAX_UNITS 8
	112	static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
	113	static int num_media = 0;
	114
	115	/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309	116	static const int max_interrupt_work = 20;
1da177e4 LT	117
	118	/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
	119	The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309	120	static const int multicast_filter_limit = 32;
1da177e4 LT	121
	122	/* MAC address length */
	123	#define MAC_ADDR_LEN 6
	124
	125	#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
	126	#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
	127	#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
	128	#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
	129	#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
	130	#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
	131	#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
	132
	133	#define R8169_REGS_SIZE 256
	134	#define R8169_NAPI_WEIGHT 64
	135	#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
	136	#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
	137	#define RX_BUF_SIZE 1536 /* Rx Buffer size */
	138	#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
	139	#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
	140
	141	#define RTL8169_TX_TIMEOUT (6*HZ)
	142	#define RTL8169_PHY_TIMEOUT (10*HZ)
	143
	144	/* write/read MMIO register */
	145	#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
	146	#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
	147	#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
	148	#define RTL_R8(reg) readb (ioaddr + (reg))
	149	#define RTL_R16(reg) readw (ioaddr + (reg))
	150	#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
	151
	152	enum mac_version {
bcf0bf90 FR	153	RTL_GIGA_MAC_VER_01 = 0x00,
	154	RTL_GIGA_MAC_VER_02 = 0x01,
	155	RTL_GIGA_MAC_VER_03 = 0x02,
	156	RTL_GIGA_MAC_VER_04 = 0x03,
	157	RTL_GIGA_MAC_VER_05 = 0x04,
	158	RTL_GIGA_MAC_VER_11 = 0x0b,
	159	RTL_GIGA_MAC_VER_12 = 0x0c,
	160	RTL_GIGA_MAC_VER_13 = 0x0d,
	161	RTL_GIGA_MAC_VER_14 = 0x0e,
	162	RTL_GIGA_MAC_VER_15 = 0x0f
1da177e4 LT	163	};
	164
	165	enum phy_version {
	166	RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	167	RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	168	RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	169	RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
	170	RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
	171	RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
	172	};
	173
1da177e4 LT	174	#define _R(NAME,MAC,MASK) \
	175	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
	176
3c6bee1d	177	static const struct {
1da177e4 LT	178	const char *name;
	179	u8 mac_version;
	180	u32 RxConfigMask; /* Clears the bits supported by this chip */
	181	} rtl_chip_info[] = {
bcf0bf90 FR	182	_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880),
	183	_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880),
	184	_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880),
	185	_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880),
	186	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880),
	187	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	188	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	189	_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
	190	_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
	191	_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4 LT	192	};
	193	#undef _R
	194
bcf0bf90 FR	195	enum cfg_version {
	196	RTL_CFG_0 = 0x00,
	197	RTL_CFG_1,
	198	RTL_CFG_2
	199	};
	200
	201	static const struct {
	202	unsigned int region;
	203	unsigned int align;
	204	} rtl_cfg_info[] = {
	205	[RTL_CFG_0] = { 1, NET_IP_ALIGN },
	206	[RTL_CFG_1] = { 2, NET_IP_ALIGN },
	207	[RTL_CFG_2] = { 2, 8 }
	208	};
	209
1da177e4	210	static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90	211	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf	212	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551	213	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
bcf0bf90 FR	214	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 },
	215	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
	216	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },