Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | ||
99f252b0 | 27 | #include <asm/system.h> |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/irq.h> | |
30 | ||
f7ccf420 SH |
31 | #ifdef CONFIG_R8169_NAPI |
32 | #define NAPI_SUFFIX "-NAPI" | |
33 | #else | |
34 | #define NAPI_SUFFIX "" | |
35 | #endif | |
36 | ||
37 | #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX | |
1da177e4 LT |
38 | #define MODULENAME "r8169" |
39 | #define PFX MODULENAME ": " | |
40 | ||
41 | #ifdef RTL8169_DEBUG | |
42 | #define assert(expr) \ | |
5b0384f4 FR |
43 | if (!(expr)) { \ |
44 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
45 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
46 | } | |
1da177e4 LT |
47 | #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) |
48 | #else | |
49 | #define assert(expr) do {} while (0) | |
50 | #define dprintk(fmt, args...) do {} while (0) | |
51 | #endif /* RTL8169_DEBUG */ | |
52 | ||
b57b7e5a | 53 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 54 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 55 | |
1da177e4 LT |
56 | #define TX_BUFFS_AVAIL(tp) \ |
57 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
58 | ||
59 | #ifdef CONFIG_R8169_NAPI | |
60 | #define rtl8169_rx_skb netif_receive_skb | |
0b50f81d | 61 | #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb |
1da177e4 LT |
62 | #define rtl8169_rx_quota(count, quota) min(count, quota) |
63 | #else | |
64 | #define rtl8169_rx_skb netif_rx | |
0b50f81d | 65 | #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx |
1da177e4 LT |
66 | #define rtl8169_rx_quota(count, quota) count |
67 | #endif | |
68 | ||
1da177e4 | 69 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
f71e1309 | 70 | static const int max_interrupt_work = 20; |
1da177e4 LT |
71 | |
72 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
73 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 74 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
75 | |
76 | /* MAC address length */ | |
77 | #define MAC_ADDR_LEN 6 | |
78 | ||
79 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ | |
80 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
81 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
07d3f51f | 82 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
1da177e4 LT |
83 | #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
84 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ | |
85 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
86 | ||
87 | #define R8169_REGS_SIZE 256 | |
88 | #define R8169_NAPI_WEIGHT 64 | |
89 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
90 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
91 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
92 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
93 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
94 | ||
95 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
96 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
97 | ||
98 | /* write/read MMIO register */ | |
99 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
100 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
101 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
102 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
103 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
104 | #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) | |
105 | ||
106 | enum mac_version { | |
ba6eb6ee FR |
107 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
108 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
109 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
110 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
111 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 112 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2dd99530 FR |
113 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
114 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf | |
cdf1a608 FR |
115 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec |
116 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 | |
117 | RTL_GIGA_MAC_VER_15 = 0x0f // 8101 | |
1da177e4 LT |
118 | }; |
119 | ||
120 | enum phy_version { | |
121 | RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */ | |
122 | RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */ | |
123 | RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */ | |
124 | RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */ | |
125 | RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */ | |
126 | RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ | |
127 | }; | |
128 | ||
1da177e4 LT |
129 | #define _R(NAME,MAC,MASK) \ |
130 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
131 | ||
3c6bee1d | 132 | static const struct { |
1da177e4 LT |
133 | const char *name; |
134 | u8 mac_version; | |
135 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
136 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
137 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
138 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
139 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
140 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
141 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 142 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
bcf0bf90 FR |
143 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
144 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
145 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
146 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
147 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139 | |
1da177e4 LT |
148 | }; |
149 | #undef _R | |
150 | ||
bcf0bf90 FR |
151 | enum cfg_version { |
152 | RTL_CFG_0 = 0x00, | |
153 | RTL_CFG_1, | |
154 | RTL_CFG_2 | |
155 | }; | |
156 | ||
07ce4064 FR |
157 | static void rtl_hw_start_8169(struct net_device *); |
158 | static void rtl_hw_start_8168(struct net_device *); | |
159 | static void rtl_hw_start_8101(struct net_device *); | |
160 | ||
1da177e4 | 161 | static struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 162 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 163 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 164 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 165 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
166 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
167 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |