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r8169: 8168DP specific MII registers access methods.
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
1da177e4
LT		 40#ifdef RTL8169_DEBUG
41#define assert(expr) \
5b0384f4
FR		 42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 44 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 45 }
06fa7358
JP		 46#define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4
LT		 62
63/* MAC address length */
64#define MAC_ADDR_LEN 6
65
9c14ceaf 66#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 67#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 94#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 95
96enum mac_version {
f21b75e9 97 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
124 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
1da177e4
LT		 125};
126
1da177e4
LT		 127#define _R(NAME,MAC,MASK) \
128 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
129
3c6bee1d 130static const struct {
1da177e4
LT		 131 const char *name;
132 u8 mac_version;
133 u32 RxConfigMask; /* Clears the bits supported by this chip */
134} rtl_chip_info[] = {
ba6eb6ee
FR		 135 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
136 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
137 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
138 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 141 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
142 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 149 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
151 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
152 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 159 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
161 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
1da177e4
LT		 162};
163#undef _R
164
bcf0bf90
FR		 165enum cfg_version {
166 RTL_CFG_0 = 0x00,
167 RTL_CFG_1,
168 RTL_CFG_2
169};
170
07ce4064
FR		 171static void rtl_hw_start_8169(struct net_device *);
172static void rtl_hw_start_8168(struct net_device *);
173static void rtl_hw_start_8101(struct net_device *);
174
a3aa1884 175static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
181 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 182 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 183 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
184 { PCI_VENDOR_ID_LINKSYS, 0x1032,
185 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 186 { 0x0001, 0x8168,
187 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 188 {0,},
189};
190
191MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
192
6f0333b8 193static int rx_buf_sz = 16383;
4300e8c7 194static int use_dac;
b57b7e5a
SH		 195static struct {
196 u32 msg_enable;
197} debug = { -1 };
1da177e4 198
07d3f51f
FR		 199enum rtl_registers {
200 MAC0 = 0, /* Ethernet hardware address. */
773d2021 201 MAC4 = 4,
07d3f51f
FR		 202 MAR0 = 8, /* Multicast filter. */
203 CounterAddrLow = 0x10,
204 CounterAddrHigh = 0x14,
205 TxDescStartAddrLow = 0x20,
206 TxDescStartAddrHigh = 0x24,
207 TxHDescStartAddrLow = 0x28,
208 TxHDescStartAddrHigh = 0x2c,
209 FLASH = 0x30,
210 ERSR = 0x36,
211 ChipCmd = 0x37,
212 TxPoll = 0x38,
213 IntrMask = 0x3c,
214 IntrStatus = 0x3e,
215 TxConfig = 0x40,
216 RxConfig = 0x44,
217 RxMissed = 0x4c,
218 Cfg9346 = 0x50,
219 Config0 = 0x51,
220 Config1 = 0x52,
221 Config2 = 0x53,
222 Config3 = 0x54,
223 Config4 = 0x55,
224 Config5 = 0x56,
225 MultiIntr = 0x5c,
226 PHYAR = 0x60,
07d3f51f
FR		 227 PHYstatus = 0x6c,
228 RxMaxSize = 0xda,
229 CPlusCmd = 0xe0,
230 IntrMitigate = 0xe2,
231 RxDescAddrLow = 0xe4,
232 RxDescAddrHigh = 0xe8,
f0298f81 233 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
234
235#define NoEarlyTx 0x3f /* Max value : no early transmit. */
236
237 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
238
239#define TxPacketMax (8064 >> 7)
240
07d3f51f
FR		 241 FuncEvent = 0xf0,
242 FuncEventMask = 0xf4,
243 FuncPresetState = 0xf8,
244 FuncForceEvent = 0xfc,
1da177e4
LT		 245};
246
f162a5d1
FR		 247enum rtl8110_registers {
248 TBICSR = 0x64,
249 TBI_ANAR = 0x68,
250 TBI_LPAR = 0x6a,
251};
252
253enum rtl8168_8101_registers {
254 CSIDR = 0x64,
255 CSIAR = 0x68,
256#define CSIAR_FLAG 0x80000000
257#define CSIAR_WRITE_CMD 0x80000000
258#define CSIAR_BYTE_ENABLE 0x0f
259#define CSIAR_BYTE_ENABLE_SHIFT 12
260#define CSIAR_ADDR_MASK 0x0fff
261
262 EPHYAR = 0x80,
263#define EPHYAR_FLAG 0x80000000
264#define EPHYAR_WRITE_CMD 0x80000000
265#define EPHYAR_REG_MASK 0x1f
266#define EPHYAR_REG_SHIFT 16
267#define EPHYAR_DATA_MASK 0xffff
268 DBG_REG = 0xd1,
269#define FIX_NAK_1 (1 << 4)
270#define FIX_NAK_2 (1 << 3)
daf9df6d 271 EFUSEAR = 0xdc,
272#define EFUSEAR_FLAG 0x80000000
273#define EFUSEAR_WRITE_CMD 0x80000000
274#define EFUSEAR_READ_CMD 0x00000000
275#define EFUSEAR_REG_MASK 0x03ff
276#define EFUSEAR_REG_SHIFT 8
277#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 278};
279
c0e45c1c 280enum rtl8168_registers {
281 EPHY_RXER_NUM = 0x7c,
282 OCPDR = 0xb0, /* OCP GPHY access */
283#define OCPDR_WRITE_CMD 0x80000000
284#define OCPDR_READ_CMD 0x00000000
285#define OCPDR_REG_MASK 0x7f
286#define OCPDR_GPHY_REG_SHIFT 16
287#define OCPDR_DATA_MASK 0xffff
288 OCPAR = 0xb4,
289#define OCPAR_FLAG 0x80000000
290#define OCPAR_GPHY_WRITE_CMD 0x8000f060
291#define OCPAR_GPHY_READ_CMD 0x0000f060
292};
293
07d3f51f 294enum rtl_register_content {
1da177e4 295 /* InterruptStatusBits */
07d3f51f
FR		 296 SYSErr = 0x8000,
297 PCSTimeout = 0x4000,
298 SWInt = 0x0100,
299 TxDescUnavail = 0x0080,
300 RxFIFOOver = 0x0040,
301 LinkChg = 0x0020,
302 RxOverflow = 0x0010,
303 TxErr = 0x0008,
304 TxOK = 0x0004,
305 RxErr = 0x0002,
306 RxOK = 0x0001,
1da177e4
LT		 307
308 /* RxStatusDesc */
9dccf611
FR		 309 RxFOVF = (1 << 23),
310 RxRWT = (1 << 22),
311 RxRES = (1 << 21),
312 RxRUNT = (1 << 20),
313 RxCRC = (1 << 19),
1da177e4
LT		 314
315 /* ChipCmdBits */
07d3f51f
FR		 316 CmdReset = 0x10,
317 CmdRxEnb = 0x08,
318 CmdTxEnb = 0x04,
319 RxBufEmpty = 0x01,
1da177e4 320
275391a4
FR		 321 /* TXPoll register p.5 */
322 HPQ = 0x80, /* Poll cmd on the high prio queue */
323 NPQ = 0x40, /* Poll cmd on the low prio queue */
324 FSWInt = 0x01, /* Forced software interrupt */
325
1da177e4 326 /* Cfg9346Bits */
07d3f51f
FR		 327 Cfg9346_Lock = 0x00,
328 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 329
330 /* rx_mode_bits */
07d3f51f
FR		 331 AcceptErr = 0x20,
332 AcceptRunt = 0x10,
333 AcceptBroadcast = 0x08,
334 AcceptMulticast = 0x04,
335 AcceptMyPhys = 0x02,
336 AcceptAllPhys = 0x01,
1da177e4
LT		 337
338 /* RxConfigBits */
07d3f51f
FR		 339 RxCfgFIFOShift = 13,
340 RxCfgDMAShift = 8,
1da177e4
LT		 341
342 /* TxConfigBits */
343 TxInterFrameGapShift = 24,
344 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
345
5d06a99f 346 /* Config1 register p.24 */
f162a5d1
FR		 347 LEDS1 = (1 << 7),
348 LEDS0 = (1 << 6),
fbac58fc 349 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 350 Speed_down = (1 << 4),
351 MEMMAP = (1 << 3),
352 IOMAP = (1 << 2),
353 VPD = (1 << 1),
5d06a99f
FR		 354 PMEnable = (1 << 0), /* Power Management Enable */
355
6dccd16b
FR		 356 /* Config2 register p. 25 */
357 PCI_Clock_66MHz = 0x01,
358 PCI_Clock_33MHz = 0x00,
359
61a4dcc2
FR		 360 /* Config3 register p.25 */
361 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
362 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 363 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 364
5d06a99f 365 /* Config5 register p.27 */
61a4dcc2
FR		 366 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
367 MWF = (1 << 5), /* Accept Multicast wakeup frame */
368 UWF = (1 << 4), /* Accept Unicast wakeup frame */
369 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 370 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
371
1da177e4
LT		 372 /* TBICSR p.28 */
373 TBIReset = 0x80000000,
374 TBILoopback = 0x40000000,
375 TBINwEnable = 0x20000000,
376 TBINwRestart = 0x10000000,
377 TBILinkOk = 0x02000000,
378 TBINwComplete = 0x01000000,
379
380 /* CPlusCmd p.31 */
f162a5d1
FR		 381 EnableBist = (1 << 15), // 8168 8101
382 Mac_dbgo_oe = (1 << 14), // 8168 8101
383 Normal_mode = (1 << 13), // unused
384 Force_half_dup = (1 << 12), // 8168 8101
385 Force_rxflow_en = (1 << 11), // 8168 8101
386 Force_txflow_en = (1 << 10), // 8168 8101
387 Cxpl_dbg_sel = (1 << 9), // 8168 8101
388 ASF = (1 << 8), // 8168 8101
389 PktCntrDisable = (1 << 7), // 8168 8101
390 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 391 RxVlan = (1 << 6),
392 RxChkSum = (1 << 5),
393 PCIDAC = (1 << 4),
394 PCIMulRW = (1 << 3),
0e485150
FR		 395 INTT_0 = 0x0000, // 8168
396 INTT_1 = 0x0001, // 8168
397 INTT_2 = 0x0002, // 8168
398 INTT_3 = 0x0003, // 8168
1da177e4
LT		 399
400 /* rtl8169_PHYstatus */
07d3f51f
FR		 401 TBI_Enable = 0x80,
402 TxFlowCtrl = 0x40,
403 RxFlowCtrl = 0x20,
404 _1000bpsF = 0x10,
405 _100bps = 0x08,
406 _10bps = 0x04,
407 LinkStatus = 0x02,
408 FullDup = 0x01,
1da177e4 409
1da177e4 410 /* _TBICSRBit */
07d3f51f 411 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 412
413 /* DumpCounterCommand */
07d3f51f 414 CounterDump = 0x8,
1da177e4
LT		 415};
416
07d3f51f 417enum desc_status_bit {
1da177e4
LT		 418 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
419 RingEnd = (1 << 30), /* End of descriptor ring */
420 FirstFrag = (1 << 29), /* First segment of a packet */
421 LastFrag = (1 << 28), /* Final segment of a packet */
422
423 /* Tx private */
424 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
425 MSSShift = 16, /* MSS value position */
426 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
427 IPCS = (1 << 18), /* Calculate IP checksum */
428 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
429 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
430 TxVlanTag = (1 << 17), /* Add VLAN tag */
431
432 /* Rx private */
433 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
434 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
435
436#define RxProtoUDP (PID1)
437#define RxProtoTCP (PID0)
438#define RxProtoIP (PID1 | PID0)
439#define RxProtoMask RxProtoIP
440
441 IPFail = (1 << 16), /* IP checksum failed */
442 UDPFail = (1 << 15), /* UDP/IP checksum failed */
443 TCPFail = (1 << 14), /* TCP/IP checksum failed */
444 RxVlanTag = (1 << 16), /* VLAN tag available */
445};
446
447#define RsvdMask 0x3fffc000
448
449struct TxDesc {
6cccd6e7
REB		 450 __le32 opts1;
451 __le32 opts2;
452 __le64 addr;
1da177e4
LT		 453};
454
455struct RxDesc {
6cccd6e7
REB		 456 __le32 opts1;
457 __le32 opts2;
458 __le64 addr;
1da177e4
LT		 459};
460
461struct ring_info {
462 struct sk_buff *skb;
463 u32 len;
464 u8 __pad[sizeof(void *) - sizeof(u32)];
465};
466
f23e7fda 467enum features {
ccdffb9a
FR		 468 RTL_FEATURE_WOL = (1 << 0),
469 RTL_FEATURE_MSI = (1 << 1),
470 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 471};
472
355423d0
IV		 473struct rtl8169_counters {
474 __le64 tx_packets;
475 __le64 rx_packets;
476 __le64 tx_errors;
477 __le32 rx_errors;
478 __le16 rx_missed;
479 __le16 align_errors;
480 __le32 tx_one_collision;
481 __le32 tx_multi_collision;
482 __le64 rx_unicast;
483 __le64 rx_broadcast;
484 __le32 rx_multicast;
485 __le16 tx_aborted;
486 __le16 tx_underun;
487};
488
1da177e4
LT		 489struct rtl8169_private {
490 void __iomem *mmio_addr; /* memory map physical address */
491 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 492 struct net_device *dev;
bea3348e 493 struct napi_struct napi;
1da177e4 494 spinlock_t lock; /* spin lock flag */
b57b7e5a 495 u32 msg_enable;
1da177e4
LT		 496 int chipset;
497 int mac_version;
1da177e4
LT		 498 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
499 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
500 u32 dirty_rx;
501 u32 dirty_tx;
502 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
503 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
504 dma_addr_t TxPhyAddr;
505 dma_addr_t RxPhyAddr;
6f0333b8 506 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 507 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 508 struct timer_list timer;
509 u16 cp_cmd;
0e485150
FR		 510 u16 intr_event;
511 u16 napi_event;
1da177e4 512 u16 intr_mask;
1da177e4
LT		 513 int phy_1000_ctrl_reg;
514#ifdef CONFIG_R8169_VLAN
515 struct vlan_group *vlgrp;
516#endif
c0e45c1c 517
518 struct mdio_ops {
519 void (*write)(void __iomem *, int, int);
520 int (*read)(void __iomem *, int);
521 } mdio_ops;
522
1da177e4 523 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 524 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 525 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 526 void (*hw_start)(struct net_device *);
4da19633 527 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 528 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 529 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 530 int pcie_cap;
c4028958 531 struct delayed_work task;
f23e7fda 532 unsigned features;
ccdffb9a
FR		 533
534 struct mii_if_info mii;
355423d0 535 struct rtl8169_counters counters;
e1759441 536 u32 saved_wolopts;
1da177e4
LT		 537};
538
979b6c13 539MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 540MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 541module_param(use_dac, int, 0);
4300e8c7 542MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 543module_param_named(debug, debug.msg_enable, int, 0);
544MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 545MODULE_LICENSE("GPL");
546MODULE_VERSION(RTL8169_VERSION);
bca03d5f 547MODULE_FIRMWARE(FIRMWARE_8168D_1);
548MODULE_FIRMWARE(FIRMWARE_8168D_2);
1da177e4
LT		 549
550static int rtl8169_open(struct net_device *dev);
61357325
SH		 551static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
552 struct net_device *dev);
7d12e780 553static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 554static int rtl8169_init_ring(struct net_device *dev);
07ce4064 555static void rtl_hw_start(struct net_device *dev);
1da177e4 556static int rtl8169_close(struct net_device *dev);
07ce4064 557static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 558static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 559static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 560static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 561 void __iomem *, u32 budget);
4dcb7d33 562static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 563static void rtl8169_down(struct net_device *dev);
99f252b0 564static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 565static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 566
1da177e4 567static const unsigned int rtl8169_rx_config =
5b0384f4 568 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 569
4da19633 570static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 571{
572 int i;
573
a6baf3af 574 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 575
2371408c 576 for (i = 20; i > 0; i--) {
07d3f51f
FR		 577 /*
578 * Check if the RTL8169 has completed writing to the specified
579 * MII register.
580 */
5b0384f4 581 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 582 break;
2371408c 583 udelay(25);
1da177e4 584 }
024a07ba 585 /*
81a95f04
TT		 586 * According to hardware specs a 20us delay is required after write
587 * complete indication, but before sending next command.
024a07ba 588 */
81a95f04 589 udelay(20);
1da177e4
LT		 590}
591
4da19633 592static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 593{
594 int i, value = -1;
595
a6baf3af 596 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 597
2371408c 598 for (i = 20; i > 0; i--) {
07d3f51f
FR		 599 /*
600 * Check if the RTL8169 has completed retrieving data from
601 * the specified MII register.
602 */
1da177e4 603 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 604 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 605 break;
606 }
2371408c 607 udelay(25);
1da177e4 608 }
81a95f04
TT		 609 /*
610 * According to hardware specs a 20us delay is required after read
611 * complete indication, but before sending next command.
612 */
613 udelay(20);
614
1da177e4
LT		 615 return value;
616}
617
c0e45c1c 618static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
619{
620 int i;
621
622 RTL_W32(OCPDR, data |
623 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
624 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
625 RTL_W32(EPHY_RXER_NUM, 0);
626
627 for (i = 0; i < 100; i++) {
628 mdelay(1);
629 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
630 break;
631 }
632}
633
634static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
635{
636 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
637 (value & OCPDR_DATA_MASK));
638}
639
640static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
641{
642 int i;
643
644 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
645
646 mdelay(1);
647 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
648 RTL_W32(EPHY_RXER_NUM, 0);
649
650 for (i = 0; i < 100; i++) {
651 mdelay(1);
652 if (RTL_R32(OCPAR) & OCPAR_FLAG)
653 break;
654 }
655
656 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
657}
658
4da19633 659static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 660{
c0e45c1c 661 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 662}
663
4da19633 664static int rtl_readphy(struct rtl8169_private *tp, int location)
665{
c0e45c1c 666 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 667}
668
669static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
670{
671 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
672}
673
674static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 675{
676 int val;
677
4da19633 678 val = rtl_readphy(tp, reg_addr);
679 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 680}
681
ccdffb9a
FR		 682static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
683 int val)
684{
685 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 686
4da19633 687 rtl_writephy(tp, location, val);
ccdffb9a
FR		 688}
689
690static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
691{
692 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 693
4da19633 694 return rtl_readphy(tp, location);
ccdffb9a
FR		 695}
696
dacf8154
FR		 697static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
698{
699 unsigned int i;
700
701 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
702 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
703
704 for (i = 0; i < 100; i++) {
705 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
706 break;
707 udelay(10);
708 }
709}
710
711static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
712{
713 u16 value = 0xffff;
714 unsigned int i;
715
716 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
717
718 for (i = 0; i < 100; i++) {
719 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
720 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
721 break;
722 }
723 udelay(10);
724 }
725
726 return value;
727}
728
729static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
730{
731 unsigned int i;
732
733 RTL_W32(CSIDR, value);
734 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
735 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
736
737 for (i = 0; i < 100; i++) {
738 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
739 break;
740 udelay(10);
741 }
742}
743
744static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
745{
746 u32 value = ~0x00;
747 unsigned int i;
748
749 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
750 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
751
752 for (i = 0; i < 100; i++) {
753 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
754 value = RTL_R32(CSIDR);
755 break;
756 }
757 udelay(10);
758 }
759
760 return value;
761}
762
daf9df6d 763static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
764{
765 u8 value = 0xff;
766 unsigned int i;
767
768 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
769
770 for (i = 0; i < 300; i++) {
771 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
772 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
773 break;
774 }
775 udelay(100);
776 }
777
778 return value;
779}
780
1da177e4
LT		 781static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
782{
783 RTL_W16(IntrMask, 0x0000);
784
785 RTL_W16(IntrStatus, 0xffff);
786}
787
788static void rtl8169_asic_down(void __iomem *ioaddr)
789{
790 RTL_W8(ChipCmd, 0x00);
791 rtl8169_irq_mask_and_ack(ioaddr);
792 RTL_R16(CPlusCmd);
793}
794
4da19633 795static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 796{
4da19633 797 void __iomem *ioaddr = tp->mmio_addr;
798
1da177e4
LT		 799 return RTL_R32(TBICSR) & TBIReset;
800}
801
4da19633 802static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 803{
4da19633 804 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 805}
806
807static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
808{
809 return RTL_R32(TBICSR) & TBILinkOk;
810}
811
812static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
813{
814 return RTL_R8(PHYstatus) & LinkStatus;
815}
816
4da19633 817static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 818{
4da19633 819 void __iomem *ioaddr = tp->mmio_addr;
820
1da177e4
LT		 821 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
822}
823
4da19633 824static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 825{
826 unsigned int val;
827
4da19633 828 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
829 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 830}
831
e4fbce74 832static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 833 struct rtl8169_private *tp,
e4fbce74
RW		 834 void __iomem *ioaddr,
835 bool pm)
1da177e4
LT		 836{
837 unsigned long flags;
838
839 spin_lock_irqsave(&tp->lock, flags);
840 if (tp->link_ok(ioaddr)) {
e1759441 841 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 842 if (pm)
843 pm_request_resume(&tp->pci_dev->dev);
1da177e4 844 netif_carrier_on(dev);
bf82c189 845 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 846 } else {
1da177e4 847 netif_carrier_off(dev);
bf82c189 848 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 849 if (pm)
850 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 851 }
1da177e4
LT		 852 spin_unlock_irqrestore(&tp->lock, flags);
853}
854
e4fbce74
RW		 855static void rtl8169_check_link_status(struct net_device *dev,
856 struct rtl8169_private *tp,
857 void __iomem *ioaddr)
858{
859 __rtl8169_check_link_status(dev, tp, ioaddr, false);
860}
861
e1759441
RW		 862#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
863
864static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 865{
61a4dcc2
FR		 866 void __iomem *ioaddr = tp->mmio_addr;
867 u8 options;
e1759441 868 u32 wolopts = 0;
61a4dcc2
FR		 869
870 options = RTL_R8(Config1);
871 if (!(options & PMEnable))
e1759441 872 return 0;
61a4dcc2
FR		 873
874 options = RTL_R8(Config3);
875 if (options & LinkUp)
e1759441 876 wolopts |= WAKE_PHY;
61a4dcc2 877 if (options & MagicPacket)
e1759441 878 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 879
880 options = RTL_R8(Config5);
881 if (options & UWF)
e1759441 882 wolopts |= WAKE_UCAST;
61a4dcc2 883 if (options & BWF)
e1759441 884 wolopts |= WAKE_BCAST;
61a4dcc2 885 if (options & MWF)
e1759441 886 wolopts |= WAKE_MCAST;
61a4dcc2 887
e1759441 888 return wolopts;
61a4dcc2
FR		 889}
890
e1759441 891static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 892{
893 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 894
895 spin_lock_irq(&tp->lock);
896
897 wol->supported = WAKE_ANY;
898 wol->wolopts = __rtl8169_get_wol(tp);
899
900 spin_unlock_irq(&tp->lock);
901}
902
903static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
904{
61a4dcc2 905 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 906 unsigned int i;
350f7596 907 static const struct {
61a4dcc2
FR		 908 u32 opt;
909 u16 reg;
910 u8 mask;
911 } cfg[] = {
912 { WAKE_ANY, Config1, PMEnable },
913 { WAKE_PHY, Config3, LinkUp },
914 { WAKE_MAGIC, Config3, MagicPacket },
915 { WAKE_UCAST, Config5, UWF },
916 { WAKE_BCAST, Config5, BWF },
917 { WAKE_MCAST, Config5, MWF },
918 { WAKE_ANY, Config5, LanWake }
919 };
920
61a4dcc2
FR		 921 RTL_W8(Cfg9346, Cfg9346_Unlock);
922
923 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
924 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 925 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 926 options |= cfg[i].mask;
927 RTL_W8(cfg[i].reg, options);
928 }
929
930 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 931}
932
933static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
934{
935 struct rtl8169_private *tp = netdev_priv(dev);
936
937 spin_lock_irq(&tp->lock);
61a4dcc2 938
f23e7fda
FR		 939 if (wol->wolopts)
940 tp->features |= RTL_FEATURE_WOL;
941 else
942 tp->features &= ~RTL_FEATURE_WOL;
e1759441 943 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 944 spin_unlock_irq(&tp->lock);
945
ea80907f 946 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
947
61a4dcc2
FR		 948 return 0;
949}
950
1da177e4
LT		 951static void rtl8169_get_drvinfo(struct net_device *dev,
952 struct ethtool_drvinfo *info)
953{
954 struct rtl8169_private *tp = netdev_priv(dev);
955
956 strcpy(info->driver, MODULENAME);
957 strcpy(info->version, RTL8169_VERSION);
958 strcpy(info->bus_info, pci_name(tp->pci_dev));
959}
960
961static int rtl8169_get_regs_len(struct net_device *dev)
962{
963 return R8169_REGS_SIZE;
964}
965
966static int rtl8169_set_speed_tbi(struct net_device *dev,
967 u8 autoneg, u16 speed, u8 duplex)
968{
969 struct rtl8169_private *tp = netdev_priv(dev);
970 void __iomem *ioaddr = tp->mmio_addr;
971 int ret = 0;
972 u32 reg;
973
974 reg = RTL_R32(TBICSR);
975 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
976 (duplex == DUPLEX_FULL)) {
977 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
978 } else if (autoneg == AUTONEG_ENABLE)
979 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
980 else {
bf82c189
JP		 981 netif_warn(tp, link, dev,
982 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 983 ret = -EOPNOTSUPP;
984 }
985
986 return ret;
987}
988
989static int rtl8169_set_speed_xmii(struct net_device *dev,
990 u8 autoneg, u16 speed, u8 duplex)
991{
992 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 993 int giga_ctrl, bmcr;
1da177e4
LT		 994
995 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 996 int auto_nego;
997
4da19633 998 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
64e4bfb4
FR		 999 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1000 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 1001 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1002
4da19633 1003 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1004 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1005
3577aa1b 1006 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1007 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1008 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1009 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1010 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1011 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1012 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1013 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1014 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1015 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 1016 } else {
1017 netif_info(tp, link, dev,
1018 "PHY does not support 1000Mbps\n");
bcf0bf90 1019 }
1da177e4 1020
3577aa1b 1021 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1022
1023 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1024 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1025 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1026 /*
1027 * Wake up the PHY.
1028 * Vendor specific (0x1f) and reserved (0x0e) MII
1029 * registers.
1030 */
4da19633 1031 rtl_writephy(tp, 0x1f, 0x0000);
1032 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1033 }
1034
4da19633 1035 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1036 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1037 } else {
1038 giga_ctrl = 0;
1039
1040 if (speed == SPEED_10)
1041 bmcr = 0;
1042 else if (speed == SPEED_100)
1043 bmcr = BMCR_SPEED100;
1044 else
1045 return -EINVAL;
1046
1047 if (duplex == DUPLEX_FULL)
1048 bmcr |= BMCR_FULLDPLX;
623a1593 1049
4da19633 1050 rtl_writephy(tp, 0x1f, 0x0000);
2584fbc3
RS		 1051 }
1052
1da177e4
LT		 1053 tp->phy_1000_ctrl_reg = giga_ctrl;
1054
4da19633 1055 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1056
1057 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1058 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1059 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1060 rtl_writephy(tp, 0x17, 0x2138);
1061 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1062 } else {
4da19633 1063 rtl_writephy(tp, 0x17, 0x2108);
1064 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1065 }
1066 }
1067
1da177e4
LT		 1068 return 0;
1069}
1070
1071static int rtl8169_set_speed(struct net_device *dev,
1072 u8 autoneg, u16 speed, u8 duplex)
1073{
1074 struct rtl8169_private *tp = netdev_priv(dev);
1075 int ret;
1076
1077 ret = tp->set_speed(dev, autoneg, speed, duplex);
1078
64e4bfb4 1079 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1080 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1081
1082 return ret;
1083}
1084
1085static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1086{
1087 struct rtl8169_private *tp = netdev_priv(dev);
1088 unsigned long flags;
1089 int ret;
1090
1091 spin_lock_irqsave(&tp->lock, flags);
1092 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1093 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1094
1da177e4
LT		 1095 return ret;
1096}
1097
1098static u32 rtl8169_get_rx_csum(struct net_device *dev)
1099{
1100 struct rtl8169_private *tp = netdev_priv(dev);
1101
1102 return tp->cp_cmd & RxChkSum;
1103}
1104
1105static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1106{
1107 struct rtl8169_private *tp = netdev_priv(dev);
1108 void __iomem *ioaddr = tp->mmio_addr;
1109 unsigned long flags;
1110
1111 spin_lock_irqsave(&tp->lock, flags);
1112
1113 if (data)
1114 tp->cp_cmd |= RxChkSum;
1115 else
1116 tp->cp_cmd &= ~RxChkSum;
1117
1118 RTL_W16(CPlusCmd, tp->cp_cmd);
1119 RTL_R16(CPlusCmd);
1120
1121 spin_unlock_irqrestore(&tp->lock, flags);
1122
1123 return 0;
1124}
1125
1126#ifdef CONFIG_R8169_VLAN
1127
1128static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1129 struct sk_buff *skb)
1130{
eab6d18d 1131 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1132 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1133}
1134
1135static void rtl8169_vlan_rx_register(struct net_device *dev,
1136 struct vlan_group *grp)
1137{
1138 struct rtl8169_private *tp = netdev_priv(dev);
1139 void __iomem *ioaddr = tp->mmio_addr;
1140 unsigned long flags;
1141
1142 spin_lock_irqsave(&tp->lock, flags);
1143 tp->vlgrp = grp;
05af2142
SW		 1144 /*
1145 * Do not disable RxVlan on 8110SCd.
1146 */
1147 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1148 tp->cp_cmd |= RxVlan;
1149 else
1150 tp->cp_cmd &= ~RxVlan;
1151 RTL_W16(CPlusCmd, tp->cp_cmd);
1152 RTL_R16(CPlusCmd);
1153 spin_unlock_irqrestore(&tp->lock, flags);
1154}
1155
1da177e4 1156static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1157 struct sk_buff *skb, int polling)
1da177e4
LT		 1158{
1159 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1160 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1161 int ret;
1162
865c652d 1163 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1164 u16 vtag = swab16(opts2 & 0xffff);
1165
1166 if (likely(polling))
1167 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1168 else
1169 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1170 ret = 0;
1171 } else
1172 ret = -1;
1173 desc->opts2 = 0;
1174 return ret;
1175}
1176
1177#else /* !CONFIG_R8169_VLAN */
1178
1179static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1180 struct sk_buff *skb)
1181{
1182 return 0;
1183}
1184
1185static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1186 struct sk_buff *skb, int polling)
1da177e4
LT		 1187{
1188 return -1;
1189}
1190
1191#endif
1192
ccdffb9a 1193static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1194{
1195 struct rtl8169_private *tp = netdev_priv(dev);
1196 void __iomem *ioaddr = tp->mmio_addr;
1197 u32 status;
1198
1199 cmd->supported =
1200 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1201 cmd->port = PORT_FIBRE;
1202 cmd->transceiver = XCVR_INTERNAL;
1203
1204 status = RTL_R32(TBICSR);
1205 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1206 cmd->autoneg = !!(status & TBINwEnable);
1207
1208 cmd->speed = SPEED_1000;
1209 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1210
1211 return 0;
1da177e4
LT		 1212}
1213
ccdffb9a 1214static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1215{
1216 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1217
1218 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1219}
1220
1221static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1222{
1223 struct rtl8169_private *tp = netdev_priv(dev);
1224 unsigned long flags;
ccdffb9a 1225 int rc;
1da177e4
LT		 1226
1227 spin_lock_irqsave(&tp->lock, flags);
1228
ccdffb9a 1229 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1230
1231 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1232 return rc;
1da177e4
LT		 1233}
1234
1235static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1236 void *p)
1237{
5b0384f4
FR		 1238 struct rtl8169_private *tp = netdev_priv(dev);
1239 unsigned long flags;
1da177e4 1240
5b0384f4
FR		 1241 if (regs->len > R8169_REGS_SIZE)
1242 regs->len = R8169_REGS_SIZE;
1da177e4 1243
5b0384f4
FR		 1244 spin_lock_irqsave(&tp->lock, flags);
1245 memcpy_fromio(p, tp->mmio_addr, regs->len);
1246 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1247}
1248
b57b7e5a
SH		 1249static u32 rtl8169_get_msglevel(struct net_device *dev)
1250{
1251 struct rtl8169_private *tp = netdev_priv(dev);
1252
1253 return tp->msg_enable;
1254}
1255
1256static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1257{
1258 struct rtl8169_private *tp = netdev_priv(dev);
1259
1260 tp->msg_enable = value;
1261}
1262
d4a3a0fc
SH		 1263static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1264 "tx_packets",
1265 "rx_packets",
1266 "tx_errors",
1267 "rx_errors",
1268 "rx_missed",
1269 "align_errors",
1270 "tx_single_collisions",
1271 "tx_multi_collisions",
1272 "unicast",
1273 "broadcast",
1274 "multicast",
1275 "tx_aborted",
1276 "tx_underrun",
1277};
1278
b9f2c044 1279static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1280{
b9f2c044
JG		 1281 switch (sset) {
1282 case ETH_SS_STATS:
1283 return ARRAY_SIZE(rtl8169_gstrings);
1284 default:
1285 return -EOPNOTSUPP;
1286 }
d4a3a0fc
SH		 1287}
1288
355423d0 1289static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1290{
1291 struct rtl8169_private *tp = netdev_priv(dev);
1292 void __iomem *ioaddr = tp->mmio_addr;
1293 struct rtl8169_counters *counters;
1294 dma_addr_t paddr;
1295 u32 cmd;
355423d0 1296 int wait = 1000;
48addcc9 1297 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1298
355423d0
IV		 1299 /*
1300 * Some chips are unable to dump tally counters when the receiver
1301 * is disabled.
1302 */
1303 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1304 return;
d4a3a0fc 1305
48addcc9 1306 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1307 if (!counters)
1308 return;
1309
1310 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1311 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1312 RTL_W32(CounterAddrLow, cmd);
1313 RTL_W32(CounterAddrLow, cmd | CounterDump);
1314
355423d0
IV		 1315 while (wait--) {
1316 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1317 /* copy updated counters */
1318 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1319 break;
355423d0
IV		 1320 }
1321 udelay(10);
d4a3a0fc
SH		 1322 }
1323
1324 RTL_W32(CounterAddrLow, 0);
1325 RTL_W32(CounterAddrHigh, 0);
1326
48addcc9 1327 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1328}
1329
355423d0
IV		 1330static void rtl8169_get_ethtool_stats(struct net_device *dev,
1331 struct ethtool_stats *stats, u64 *data)
1332{
1333 struct rtl8169_private *tp = netdev_priv(dev);
1334
1335 ASSERT_RTNL();
1336
1337 rtl8169_update_counters(dev);
1338
1339 data[0] = le64_to_cpu(tp->counters.tx_packets);
1340 data[1] = le64_to_cpu(tp->counters.rx_packets);
1341 data[2] = le64_to_cpu(tp->counters.tx_errors);
1342 data[3] = le32_to_cpu(tp->counters.rx_errors);
1343 data[4] = le16_to_cpu(tp->counters.rx_missed);
1344 data[5] = le16_to_cpu(tp->counters.align_errors);
1345 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1346 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1347 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1348 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1349 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1350 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1351 data[12] = le16_to_cpu(tp->counters.tx_underun);
1352}
1353
d4a3a0fc
SH		 1354static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1355{
1356 switch(stringset) {
1357 case ETH_SS_STATS:
1358 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1359 break;
1360 }
1361}
1362
7282d491 1363static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1364 .get_drvinfo = rtl8169_get_drvinfo,
1365 .get_regs_len = rtl8169_get_regs_len,
1366 .get_link = ethtool_op_get_link,
1367 .get_settings = rtl8169_get_settings,
1368 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1369 .get_msglevel = rtl8169_get_msglevel,
1370 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1371 .get_rx_csum = rtl8169_get_rx_csum,
1372 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1373 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1374 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1375 .set_tso = ethtool_op_set_tso,
1376 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1377 .get_wol = rtl8169_get_wol,
1378 .set_wol = rtl8169_set_wol,
d4a3a0fc 1379 .get_strings = rtl8169_get_strings,
b9f2c044 1380 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1381 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1382};
1383
07d3f51f
FR		 1384static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1385 void __iomem *ioaddr)
1da177e4 1386{
0e485150
FR		 1387 /*
1388 * The driver currently handles the 8168Bf and the 8168Be identically
1389 * but they can be identified more specifically through the test below
1390 * if needed:
1391 *
1392 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1393 *
1394 * Same thing for the 8101Eb and the 8101Ec:
1395 *
1396 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1397 */
350f7596 1398 static const struct {
1da177e4 1399 u32 mask;
e3cf0cc0 1400 u32 val;
1da177e4
LT		 1401 int mac_version;
1402 } mac_info[] = {
5b538df9 1403 /* 8168D family. */
daf9df6d 1404 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1405 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1406 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1407 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1408
ef808d50 1409 /* 8168C family. */
17c99297 1410 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1411 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1412 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1413 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1414 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1415 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1416 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1417 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1418 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1419
1420 /* 8168B family. */
1421 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1422 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1423 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1424 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1425
1426 /* 8101 family. */
2857ffb7
FR		 1427 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1428 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1429 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1430 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1431 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1432 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1433 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1434 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1435 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1436 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1437 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1438 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1439 /* FIXME: where did these entries come from ? -- FR */
1440 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1441 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1442
1443 /* 8110 family. */
1444 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1445 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1446 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1447 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1448 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1449 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1450
f21b75e9
JD		 1451 /* Catch-all */
1452 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1453 }, *p = mac_info;
1454 u32 reg;
1455
e3cf0cc0
FR		 1456 reg = RTL_R32(TxConfig);
1457 while ((reg & p->mask) != p->val)
1da177e4
LT		 1458 p++;
1459 tp->mac_version = p->mac_version;
1460}
1461
1462static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1463{
bcf0bf90 1464 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1465}
1466
867763c1
FR		 1467struct phy_reg {
1468 u16 reg;
1469 u16 val;
1470};
1471
4da19633 1472static void rtl_writephy_batch(struct rtl8169_private *tp,
1473 const struct phy_reg *regs, int len)
867763c1
FR		 1474{
1475 while (len-- > 0) {
4da19633 1476 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1477 regs++;
1478 }
1479}
1480
bca03d5f 1481#define PHY_READ 0x00000000
1482#define PHY_DATA_OR 0x10000000
1483#define PHY_DATA_AND 0x20000000
1484#define PHY_BJMPN 0x30000000
1485#define PHY_READ_EFUSE 0x40000000
1486#define PHY_READ_MAC_BYTE 0x50000000
1487#define PHY_WRITE_MAC_BYTE 0x60000000
1488#define PHY_CLEAR_READCOUNT 0x70000000
1489#define PHY_WRITE 0x80000000
1490#define PHY_READCOUNT_EQ_SKIP 0x90000000
1491#define PHY_COMP_EQ_SKIPN 0xa0000000
1492#define PHY_COMP_NEQ_SKIPN 0xb0000000
1493#define PHY_WRITE_PREVIOUS 0xc0000000
1494#define PHY_SKIPN 0xd0000000
1495#define PHY_DELAY_MS 0xe0000000
1496#define PHY_WRITE_ERI_WORD 0xf0000000
1497
1498static void
1499rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1500{
bca03d5f 1501 __le32 *phytable = (__le32 *)fw->data;
1502 struct net_device *dev = tp->dev;
1503 size_t i;
1504
1505 if (fw->size % sizeof(*phytable)) {
1506 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1507 return;
1508 }
1509
1510 for (i = 0; i < fw->size / sizeof(*phytable); i++) {
1511 u32 action = le32_to_cpu(phytable[i]);
1512
1513 if (!action)
1514 break;
1515
1516 if ((action & 0xf0000000) != PHY_WRITE) {
1517 netif_err(tp, probe, dev,
1518 "unknown action 0x%08x\n", action);
1519 return;
1520 }
1521 }
1522
1523 while (i-- != 0) {
1524 u32 action = le32_to_cpu(*phytable);
1525 u32 data = action & 0x0000ffff;
1526 u32 reg = (action & 0x0fff0000) >> 16;
1527
1528 switch(action & 0xf0000000) {
1529 case PHY_WRITE:
4da19633 1530 rtl_writephy(tp, reg, data);
bca03d5f 1531 phytable++;
1532 break;
1533 default:
1534 BUG();
1535 }
1536 }
1537}
1538
4da19633 1539static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1540{
350f7596 1541 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1542 { 0x1f, 0x0001 },
1543 { 0x06, 0x006e },
1544 { 0x08, 0x0708 },
1545 { 0x15, 0x4000 },
1546 { 0x18, 0x65c7 },
1da177e4 1547
0b9b571d 1548 { 0x1f, 0x0001 },
1549 { 0x03, 0x00a1 },
1550 { 0x02, 0x0008 },
1551 { 0x01, 0x0120 },
1552 { 0x00, 0x1000 },
1553 { 0x04, 0x0800 },
1554 { 0x04, 0x0000 },
1da177e4 1555
0b9b571d 1556 { 0x03, 0xff41 },
1557 { 0x02, 0xdf60 },
1558 { 0x01, 0x0140 },
1559 { 0x00, 0x0077 },
1560 { 0x04, 0x7800 },
1561 { 0x04, 0x7000 },
1562
1563 { 0x03, 0x802f },
1564 { 0x02, 0x4f02 },
1565 { 0x01, 0x0409 },
1566 { 0x00, 0xf0f9 },
1567 { 0x04, 0x9800 },
1568 { 0x04, 0x9000 },
1569
1570 { 0x03, 0xdf01 },
1571 { 0x02, 0xdf20 },
1572 { 0x01, 0xff95 },
1573 { 0x00, 0xba00 },
1574 { 0x04, 0xa800 },
1575 { 0x04, 0xa000 },
1576
1577 { 0x03, 0xff41 },
1578 { 0x02, 0xdf20 },
1579 { 0x01, 0x0140 },
1580 { 0x00, 0x00bb },
1581 { 0x04, 0xb800 },
1582 { 0x04, 0xb000 },
1583
1584 { 0x03, 0xdf41 },
1585 { 0x02, 0xdc60 },
1586 { 0x01, 0x6340 },
1587 { 0x00, 0x007d },
1588 { 0x04, 0xd800 },
1589 { 0x04, 0xd000 },
1590
1591 { 0x03, 0xdf01 },
1592 { 0x02, 0xdf20 },
1593 { 0x01, 0x100a },
1594 { 0x00, 0xa0ff },
1595 { 0x04, 0xf800 },
1596 { 0x04, 0xf000 },
1597
1598 { 0x1f, 0x0000 },
1599 { 0x0b, 0x0000 },
1600 { 0x00, 0x9200 }
1601 };
1da177e4 1602
4da19633 1603 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1604}
1605
4da19633 1606static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1607{
350f7596 1608 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1609 { 0x1f, 0x0002 },
1610 { 0x01, 0x90d0 },
1611 { 0x1f, 0x0000 }
1612 };
1613
4da19633 1614 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1615}
1616
4da19633 1617static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1618{
1619 struct pci_dev *pdev = tp->pci_dev;
1620 u16 vendor_id, device_id;
1621
1622 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1623 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1624
1625 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1626 return;
1627
4da19633 1628 rtl_writephy(tp, 0x1f, 0x0001);
1629 rtl_writephy(tp, 0x10, 0xf01b);
1630 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1631}
1632
4da19633 1633static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1634{
350f7596 1635 static const struct phy_reg phy_reg_init[] = {
2e955856 1636 { 0x1f, 0x0001 },
1637 { 0x04, 0x0000 },
1638 { 0x03, 0x00a1 },
1639 { 0x02, 0x0008 },
1640 { 0x01, 0x0120 },
1641 { 0x00, 0x1000 },
1642 { 0x04, 0x0800 },
1643 { 0x04, 0x9000 },
1644 { 0x03, 0x802f },
1645 { 0x02, 0x4f02 },
1646 { 0x01, 0x0409 },
1647 { 0x00, 0xf099 },
1648 { 0x04, 0x9800 },
1649 { 0x04, 0xa000 },
1650 { 0x03, 0xdf01 },
1651 { 0x02, 0xdf20 },
1652 { 0x01, 0xff95 },
1653 { 0x00, 0xba00 },
1654 { 0x04, 0xa800 },
1655 { 0x04, 0xf000 },
1656 { 0x03, 0xdf01 },
1657 { 0x02, 0xdf20 },
1658 { 0x01, 0x101a },
1659 { 0x00, 0xa0ff },
1660 { 0x04, 0xf800 },
1661 { 0x04, 0x0000 },
1662 { 0x1f, 0x0000 },
1663
1664 { 0x1f, 0x0001 },
1665 { 0x10, 0xf41b },
1666 { 0x14, 0xfb54 },
1667 { 0x18, 0xf5c7 },
1668 { 0x1f, 0x0000 },
1669
1670 { 0x1f, 0x0001 },
1671 { 0x17, 0x0cc0 },
1672 { 0x1f, 0x0000 }
1673 };
1674
4da19633 1675 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1676
4da19633 1677 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1678}
1679
4da19633 1680static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1681{
350f7596 1682 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1683 { 0x1f, 0x0001 },
1684 { 0x04, 0x0000 },
1685 { 0x03, 0x00a1 },
1686 { 0x02, 0x0008 },
1687 { 0x01, 0x0120 },
1688 { 0x00, 0x1000 },
1689 { 0x04, 0x0800 },
1690 { 0x04, 0x9000 },
1691 { 0x03, 0x802f },
1692 { 0x02, 0x4f02 },
1693 { 0x01, 0x0409 },
1694 { 0x00, 0xf099 },
1695 { 0x04, 0x9800 },
1696 { 0x04, 0xa000 },
1697 { 0x03, 0xdf01 },
1698 { 0x02, 0xdf20 },
1699 { 0x01, 0xff95 },
1700 { 0x00, 0xba00 },
1701 { 0x04, 0xa800 },
1702 { 0x04, 0xf000 },
1703 { 0x03, 0xdf01 },
1704 { 0x02, 0xdf20 },
1705 { 0x01, 0x101a },
1706 { 0x00, 0xa0ff },
1707 { 0x04, 0xf800 },
1708 { 0x04, 0x0000 },
1709 { 0x1f, 0x0000 },
1710
1711 { 0x1f, 0x0001 },
1712 { 0x0b, 0x8480 },
1713 { 0x1f, 0x0000 },
1714
1715 { 0x1f, 0x0001 },
1716 { 0x18, 0x67c7 },
1717 { 0x04, 0x2000 },
1718 { 0x03, 0x002f },
1719 { 0x02, 0x4360 },
1720 { 0x01, 0x0109 },
1721 { 0x00, 0x3022 },
1722 { 0x04, 0x2800 },
1723 { 0x1f, 0x0000 },
1724
1725 { 0x1f, 0x0001 },
1726 { 0x17, 0x0cc0 },
1727 { 0x1f, 0x0000 }
1728 };
1729
4da19633 1730 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 1731}
1732
4da19633 1733static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 1734{
350f7596 1735 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1736 { 0x10, 0xf41b },
1737 { 0x1f, 0x0000 }
1738 };
1739
4da19633 1740 rtl_writephy(tp, 0x1f, 0x0001);
1741 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 1742
4da19633 1743 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1744}
1745
4da19633 1746static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 1747{
350f7596 1748 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1749 { 0x1f, 0x0001 },
1750 { 0x10, 0xf41b },
1751 { 0x1f, 0x0000 }
1752 };
1753
4da19633 1754 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 1755}
1756
4da19633 1757static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1758{
350f7596 1759 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 1760 { 0x1f, 0x0000 },
1761 { 0x1d, 0x0f00 },
1762 { 0x1f, 0x0002 },
1763 { 0x0c, 0x1ec8 },
1764 { 0x1f, 0x0000 }
1765 };
1766
4da19633 1767 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 1768}
1769
4da19633 1770static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 1771{
350f7596 1772 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 1773 { 0x1f, 0x0001 },
1774 { 0x1d, 0x3d98 },
1775 { 0x1f, 0x0000 }
1776 };
1777
4da19633 1778 rtl_writephy(tp, 0x1f, 0x0000);
1779 rtl_patchphy(tp, 0x14, 1 << 5);
1780 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 1781
4da19633 1782 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 1783}
1784
4da19633 1785static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 1786{
350f7596 1787 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1788 { 0x1f, 0x0001 },
1789 { 0x12, 0x2300 },
867763c1
FR		 1790 { 0x1f, 0x0002 },
1791 { 0x00, 0x88d4 },
1792 { 0x01, 0x82b1 },
1793 { 0x03, 0x7002 },
1794 { 0x08, 0x9e30 },
1795 { 0x09, 0x01f0 },
1796 { 0x0a, 0x5500 },
1797 { 0x0c, 0x00c8 },
1798 { 0x1f, 0x0003 },
1799 { 0x12, 0xc096 },
1800 { 0x16, 0x000a },
f50d4275
FR		 1801 { 0x1f, 0x0000 },
1802 { 0x1f, 0x0000 },
1803 { 0x09, 0x2000 },
1804 { 0x09, 0x0000 }
867763c1
FR		 1805 };
1806
4da19633 1807 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 1808
4da19633 1809 rtl_patchphy(tp, 0x14, 1 << 5);
1810 rtl_patchphy(tp, 0x0d, 1 << 5);
1811 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 1812}
1813
4da19633 1814static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 1815{
350f7596 1816 static const struct phy_reg phy_reg_init[] = {
f50d4275 1817 { 0x1f, 0x0001 },
7da97ec9 1818 { 0x12, 0x2300 },
f50d4275
FR		 1819 { 0x03, 0x802f },
1820 { 0x02, 0x4f02 },
1821 { 0x01, 0x0409 },
1822 { 0x00, 0xf099 },
1823 { 0x04, 0x9800 },
1824 { 0x04, 0x9000 },
1825 { 0x1d, 0x3d98 },
7da97ec9
FR		 1826 { 0x1f, 0x0002 },
1827 { 0x0c, 0x7eb8 },
f50d4275
FR		 1828 { 0x06, 0x0761 },
1829 { 0x1f, 0x0003 },
1830 { 0x16, 0x0f0a },
7da97ec9
FR		 1831 { 0x1f, 0x0000 }
1832 };
1833
4da19633 1834 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 1835
4da19633 1836 rtl_patchphy(tp, 0x16, 1 << 0);
1837 rtl_patchphy(tp, 0x14, 1 << 5);
1838 rtl_patchphy(tp, 0x0d, 1 << 5);
1839 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 1840}
1841
4da19633 1842static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 1843{
350f7596 1844 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 1845 { 0x1f, 0x0001 },
1846 { 0x12, 0x2300 },
1847 { 0x1d, 0x3d98 },
1848 { 0x1f, 0x0002 },
1849 { 0x0c, 0x7eb8 },
1850 { 0x06, 0x5461 },
1851 { 0x1f, 0x0003 },
1852 { 0x16, 0x0f0a },
1853 { 0x1f, 0x0000 }
1854 };
1855
4da19633 1856 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 1857
4da19633 1858 rtl_patchphy(tp, 0x16, 1 << 0);
1859 rtl_patchphy(tp, 0x14, 1 << 5);
1860 rtl_patchphy(tp, 0x0d, 1 << 5);
1861 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 1862}
1863
4da19633 1864static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 1865{
4da19633 1866 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 1867}
1868
bca03d5f 1869static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 1870{
350f7596 1871 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 1872 /* Channel Estimation */
5b538df9 1873 { 0x1f, 0x0001 },
daf9df6d 1874 { 0x06, 0x4064 },
1875 { 0x07, 0x2863 },
1876 { 0x08, 0x059c },
1877 { 0x09, 0x26b4 },
1878 { 0x0a, 0x6a19 },
1879 { 0x0b, 0xdcc8 },
1880 { 0x10, 0xf06d },
1881 { 0x14, 0x7f68 },
1882 { 0x18, 0x7fd9 },
1883 { 0x1c, 0xf0ff },
1884 { 0x1d, 0x3d9c },
5b538df9 1885 { 0x1f, 0x0003 },
daf9df6d 1886 { 0x12, 0xf49f },
1887 { 0x13, 0x070b },
1888 { 0x1a, 0x05ad },
bca03d5f 1889 { 0x14, 0x94c0 },
1890
1891 /*
1892 * Tx Error Issue
1893 * enhance line driver power
1894 */
5b538df9 1895 { 0x1f, 0x0002 },
daf9df6d 1896 { 0x06, 0x5561 },
1897 { 0x1f, 0x0005 },
1898 { 0x05, 0x8332 },
bca03d5f 1899 { 0x06, 0x5561 },
1900
1901 /*
1902 * Can not link to 1Gbps with bad cable
1903 * Decrease SNR threshold form 21.07dB to 19.04dB
1904 */
1905 { 0x1f, 0x0001 },
1906 { 0x17, 0x0cc0 },
daf9df6d 1907
5b538df9 1908 { 0x1f, 0x0000 },
bca03d5f 1909 { 0x0d, 0xf880 }
daf9df6d 1910 };
bca03d5f 1911 void __iomem *ioaddr = tp->mmio_addr;
1912 const struct firmware *fw;
daf9df6d 1913
4da19633 1914 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 1915
bca03d5f 1916 /*
1917 * Rx Error Issue
1918 * Fine Tune Switching regulator parameter
1919 */
4da19633 1920 rtl_writephy(tp, 0x1f, 0x0002);
1921 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
1922 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 1923
daf9df6d 1924 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 1925 static const struct phy_reg phy_reg_init[] = {
daf9df6d 1926 { 0x1f, 0x0002 },
1927 { 0x05, 0x669a },
1928 { 0x1f, 0x0005 },
1929 { 0x05, 0x8330 },
1930 { 0x06, 0x669a },
1931 { 0x1f, 0x0002 }
1932 };
1933 int val;
1934
4da19633 1935 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 1936
4da19633 1937 val = rtl_readphy(tp, 0x0d);
daf9df6d 1938
1939 if ((val & 0x00ff) != 0x006c) {
350f7596 1940 static const u32 set[] = {
daf9df6d 1941 0x0065, 0x0066, 0x0067, 0x0068,
1942 0x0069, 0x006a, 0x006b, 0x006c
1943 };
1944 int i;
1945
4da19633 1946 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 1947
1948 val &= 0xff00;
1949 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 1950 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 1951 }
1952 } else {
350f7596 1953 static const struct phy_reg phy_reg_init[] = {
daf9df6d 1954 { 0x1f, 0x0002 },
1955 { 0x05, 0x6662 },
1956 { 0x1f, 0x0005 },
1957 { 0x05, 0x8330 },
1958 { 0x06, 0x6662 }
1959 };
1960
4da19633 1961 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 1962 }
1963
bca03d5f 1964 /* RSET couple improve */
4da19633 1965 rtl_writephy(tp, 0x1f, 0x0002);
1966 rtl_patchphy(tp, 0x0d, 0x0300);
1967 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 1968
bca03d5f 1969 /* Fine tune PLL performance */
4da19633 1970 rtl_writephy(tp, 0x1f, 0x0002);
1971 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
1972 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 1973
4da19633 1974 rtl_writephy(tp, 0x1f, 0x0005);
1975 rtl_writephy(tp, 0x05, 0x001b);
1976 if (rtl_readphy(tp, 0x06) == 0xbf00 &&
bca03d5f 1977 request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
1978 rtl_phy_write_fw(tp, fw);
1979 release_firmware(fw);
1980 } else {
1981 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
1982 }
1983
4da19633 1984 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 1985}
1986
bca03d5f 1987static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 1988{
350f7596 1989 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 1990 /* Channel Estimation */
daf9df6d 1991 { 0x1f, 0x0001 },
1992 { 0x06, 0x4064 },
1993 { 0x07, 0x2863 },
1994 { 0x08, 0x059c },
1995 { 0x09, 0x26b4 },
1996 { 0x0a, 0x6a19 },
1997 { 0x0b, 0xdcc8 },
1998 { 0x10, 0xf06d },
1999 { 0x14, 0x7f68 },
2000 { 0x18, 0x7fd9 },
2001 { 0x1c, 0xf0ff },
2002 { 0x1d, 0x3d9c },
2003 { 0x1f, 0x0003 },
2004 { 0x12, 0xf49f },
2005 { 0x13, 0x070b },
2006 { 0x1a, 0x05ad },
2007 { 0x14, 0x94c0 },
2008
bca03d5f 2009 /*
2010 * Tx Error Issue
2011 * enhance line driver power
2012 */
daf9df6d 2013 { 0x1f, 0x0002 },
2014 { 0x06, 0x5561 },
2015 { 0x1f, 0x0005 },
2016 { 0x05, 0x8332 },
bca03d5f 2017 { 0x06, 0x5561 },
2018
2019 /*
2020 * Can not link to 1Gbps with bad cable
2021 * Decrease SNR threshold form 21.07dB to 19.04dB
2022 */
2023 { 0x1f, 0x0001 },
2024 { 0x17, 0x0cc0 },
daf9df6d 2025
2026 { 0x1f, 0x0000 },
bca03d5f 2027 { 0x0d, 0xf880 }
5b538df9 2028 };
bca03d5f 2029 void __iomem *ioaddr = tp->mmio_addr;
2030 const struct firmware *fw;
5b538df9 2031
4da19633 2032 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2033
daf9df6d 2034 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2035 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2036 { 0x1f, 0x0002 },
2037 { 0x05, 0x669a },
5b538df9 2038 { 0x1f, 0x0005 },
daf9df6d 2039 { 0x05, 0x8330 },
2040 { 0x06, 0x669a },
2041
2042 { 0x1f, 0x0002 }
2043 };
2044 int val;
2045
4da19633 2046 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2047
4da19633 2048 val = rtl_readphy(tp, 0x0d);
daf9df6d 2049 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2050 static const u32 set[] = {
daf9df6d 2051 0x0065, 0x0066, 0x0067, 0x0068,
2052 0x0069, 0x006a, 0x006b, 0x006c
2053 };
2054 int i;
2055
4da19633 2056 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2057
2058 val &= 0xff00;
2059 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2060 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2061 }
2062 } else {
350f7596 2063 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2064 { 0x1f, 0x0002 },
2065 { 0x05, 0x2642 },
5b538df9 2066 { 0x1f, 0x0005 },
daf9df6d 2067 { 0x05, 0x8330 },
2068 { 0x06, 0x2642 }
5b538df9
FR		 2069 };
2070
4da19633 2071 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2072 }
2073
bca03d5f 2074 /* Fine tune PLL performance */
4da19633 2075 rtl_writephy(tp, 0x1f, 0x0002);
2076 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2077 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2078
bca03d5f 2079 /* Switching regulator Slew rate */
4da19633 2080 rtl_writephy(tp, 0x1f, 0x0002);
2081 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2082
4da19633 2083 rtl_writephy(tp, 0x1f, 0x0005);
2084 rtl_writephy(tp, 0x05, 0x001b);
2085 if (rtl_readphy(tp, 0x06) == 0xb300 &&
bca03d5f 2086 request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
2087 rtl_phy_write_fw(tp, fw);
2088 release_firmware(fw);
2089 } else {
2090 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2091 }
2092
4da19633 2093 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2094}
2095
4da19633 2096static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2097{
350f7596 2098 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2099 { 0x1f, 0x0002 },
2100 { 0x10, 0x0008 },
2101 { 0x0d, 0x006c },
2102
2103 { 0x1f, 0x0000 },
2104 { 0x0d, 0xf880 },
2105
2106 { 0x1f, 0x0001 },
2107 { 0x17, 0x0cc0 },
2108
2109 { 0x1f, 0x0001 },
2110 { 0x0b, 0xa4d8 },
2111 { 0x09, 0x281c },
2112 { 0x07, 0x2883 },
2113 { 0x0a, 0x6b35 },
2114 { 0x1d, 0x3da4 },
2115 { 0x1c, 0xeffd },
2116 { 0x14, 0x7f52 },
2117 { 0x18, 0x7fc6 },
2118 { 0x08, 0x0601 },
2119 { 0x06, 0x4063 },
2120 { 0x10, 0xf074 },
2121 { 0x1f, 0x0003 },
2122 { 0x13, 0x0789 },
2123 { 0x12, 0xf4bd },
2124 { 0x1a, 0x04fd },
2125 { 0x14, 0x84b0 },
2126 { 0x1f, 0x0000 },
2127 { 0x00, 0x9200 },
2128
2129 { 0x1f, 0x0005 },
2130 { 0x01, 0x0340 },
2131 { 0x1f, 0x0001 },
2132 { 0x04, 0x4000 },
2133 { 0x03, 0x1d21 },
2134 { 0x02, 0x0c32 },
2135 { 0x01, 0x0200 },
2136 { 0x00, 0x5554 },
2137 { 0x04, 0x4800 },
2138 { 0x04, 0x4000 },
2139 { 0x04, 0xf000 },
2140 { 0x03, 0xdf01 },
2141 { 0x02, 0xdf20 },
2142 { 0x01, 0x101a },
2143 { 0x00, 0xa0ff },
2144 { 0x04, 0xf800 },
2145 { 0x04, 0xf000 },
2146 { 0x1f, 0x0000 },
2147
2148 { 0x1f, 0x0007 },
2149 { 0x1e, 0x0023 },
2150 { 0x16, 0x0000 },
2151 { 0x1f, 0x0000 }
2152 };
2153
4da19633 2154 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2155}
2156
4da19633 2157static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2158{
350f7596 2159 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2160 { 0x1f, 0x0003 },
2161 { 0x08, 0x441d },
2162 { 0x01, 0x9100 },
2163 { 0x1f, 0x0000 }
2164 };
2165
4da19633 2166 rtl_writephy(tp, 0x1f, 0x0000);
2167 rtl_patchphy(tp, 0x11, 1 << 12);
2168 rtl_patchphy(tp, 0x19, 1 << 13);
2169 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2170
4da19633 2171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2172}
2173
5615d9f1
FR		 2174static void rtl_hw_phy_config(struct net_device *dev)
2175{
2176 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2177
2178 rtl8169_print_mac_version(tp);
2179
2180 switch (tp->mac_version) {
2181 case RTL_GIGA_MAC_VER_01:
2182 break;
2183 case RTL_GIGA_MAC_VER_02:
2184 case RTL_GIGA_MAC_VER_03:
4da19633 2185 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2186 break;
2187 case RTL_GIGA_MAC_VER_04:
4da19633 2188 rtl8169sb_hw_phy_config(tp);
5615d9f1 2189 break;
2e955856 2190 case RTL_GIGA_MAC_VER_05:
4da19633 2191 rtl8169scd_hw_phy_config(tp);
2e955856 2192 break;
8c7006aa 2193 case RTL_GIGA_MAC_VER_06:
4da19633 2194 rtl8169sce_hw_phy_config(tp);
8c7006aa 2195 break;
2857ffb7
FR		 2196 case RTL_GIGA_MAC_VER_07:
2197 case RTL_GIGA_MAC_VER_08:
2198 case RTL_GIGA_MAC_VER_09:
4da19633 2199 rtl8102e_hw_phy_config(tp);
2857ffb7 2200 break;
236b8082 2201 case RTL_GIGA_MAC_VER_11:
4da19633 2202 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2203 break;
2204 case RTL_GIGA_MAC_VER_12:
4da19633 2205 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2206 break;
2207 case RTL_GIGA_MAC_VER_17:
4da19633 2208 rtl8168bef_hw_phy_config(tp);
236b8082 2209 break;
867763c1 2210 case RTL_GIGA_MAC_VER_18:
4da19633 2211 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2212 break;
2213 case RTL_GIGA_MAC_VER_19:
4da19633 2214 rtl8168c_1_hw_phy_config(tp);
867763c1 2215 break;
7da97ec9 2216 case RTL_GIGA_MAC_VER_20:
4da19633 2217 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2218 break;
197ff761 2219 case RTL_GIGA_MAC_VER_21:
4da19633 2220 rtl8168c_3_hw_phy_config(tp);
197ff761 2221 break;
6fb07058 2222 case RTL_GIGA_MAC_VER_22:
4da19633 2223 rtl8168c_4_hw_phy_config(tp);
6fb07058 2224 break;
ef3386f0 2225 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2226 case RTL_GIGA_MAC_VER_24:
4da19633 2227 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2228 break;
5b538df9 2229 case RTL_GIGA_MAC_VER_25:
bca03d5f 2230 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2231 break;
2232 case RTL_GIGA_MAC_VER_26:
bca03d5f 2233 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2234 break;
2235 case RTL_GIGA_MAC_VER_27:
4da19633 2236 rtl8168d_3_hw_phy_config(tp);
5b538df9 2237 break;
ef3386f0 2238
5615d9f1
FR		 2239 default:
2240 break;
2241 }
2242}
2243
1da177e4
LT		 2244static void rtl8169_phy_timer(unsigned long __opaque)
2245{
2246 struct net_device *dev = (struct net_device *)__opaque;
2247 struct rtl8169_private *tp = netdev_priv(dev);
2248 struct timer_list *timer = &tp->timer;
2249 void __iomem *ioaddr = tp->mmio_addr;
2250 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2251
bcf0bf90 2252 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2253
64e4bfb4 2254 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2255 return;
2256
2257 spin_lock_irq(&tp->lock);
2258
4da19633 2259 if (tp->phy_reset_pending(tp)) {
5b0384f4 2260 /*
1da177e4
LT		 2261 * A busy loop could burn quite a few cycles on nowadays CPU.
2262 * Let's delay the execution of the timer for a few ticks.
2263 */
2264 timeout = HZ/10;
2265 goto out_mod_timer;
2266 }
2267
2268 if (tp->link_ok(ioaddr))
2269 goto out_unlock;
2270
bf82c189 2271 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2272
4da19633 2273 tp->phy_reset_enable(tp);
1da177e4
LT		 2274
2275out_mod_timer:
2276 mod_timer(timer, jiffies + timeout);
2277out_unlock:
2278 spin_unlock_irq(&tp->lock);
2279}
2280
2281static inline void rtl8169_delete_timer(struct net_device *dev)
2282{
2283 struct rtl8169_private *tp = netdev_priv(dev);
2284 struct timer_list *timer = &tp->timer;
2285
e179bb7b 2286 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2287 return;
2288
2289 del_timer_sync(timer);
2290}
2291
2292static inline void rtl8169_request_timer(struct net_device *dev)
2293{
2294 struct rtl8169_private *tp = netdev_priv(dev);
2295 struct timer_list *timer = &tp->timer;
2296
e179bb7b 2297 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2298 return;
2299
2efa53f3 2300 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2301}
2302
2303#ifdef CONFIG_NET_POLL_CONTROLLER
2304/*
2305 * Polling 'interrupt' - used by things like netconsole to send skbs
2306 * without having to re-enable interrupts. It's not called while
2307 * the interrupt routine is executing.
2308 */
2309static void rtl8169_netpoll(struct net_device *dev)
2310{
2311 struct rtl8169_private *tp = netdev_priv(dev);
2312 struct pci_dev *pdev = tp->pci_dev;
2313
2314 disable_irq(pdev->irq);
7d12e780 2315 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2316 enable_irq(pdev->irq);
2317}
2318#endif
2319
2320static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2321 void __iomem *ioaddr)
2322{
2323 iounmap(ioaddr);
2324 pci_release_regions(pdev);
87aeec76 2325 pci_clear_mwi(pdev);
1da177e4
LT		 2326 pci_disable_device(pdev);
2327 free_netdev(dev);
2328}
2329
bf793295
FR		 2330static void rtl8169_phy_reset(struct net_device *dev,
2331 struct rtl8169_private *tp)
2332{
07d3f51f 2333 unsigned int i;
bf793295 2334
4da19633 2335 tp->phy_reset_enable(tp);
bf793295 2336 for (i = 0; i < 100; i++) {
4da19633 2337 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2338 return;
2339 msleep(1);
2340 }
bf82c189 2341 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2342}
2343
4ff96fa6
FR		 2344static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2345{
2346 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2347
5615d9f1 2348 rtl_hw_phy_config(dev);
4ff96fa6 2349
77332894
MS		 2350 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2351 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2352 RTL_W8(0x82, 0x01);
2353 }
4ff96fa6 2354
6dccd16b
FR		 2355 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2356
2357 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2358 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2359
bcf0bf90 2360 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2361 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2362 RTL_W8(0x82, 0x01);
2363 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2364 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2365 }
2366
bf793295
FR		 2367 rtl8169_phy_reset(dev, tp);
2368
901dda2b
FR		 2369 /*
2370 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2371 * only 8101. Don't panic.
2372 */
2373 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2374
bf82c189
JP		 2375 if (RTL_R8(PHYstatus) & TBI_Enable)
2376 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2377}
2378
773d2021
FR		 2379static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2380{
2381 void __iomem *ioaddr = tp->mmio_addr;
2382 u32 high;
2383 u32 low;
2384
2385 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2386 high = addr[4] | (addr[5] << 8);
2387
2388 spin_lock_irq(&tp->lock);
2389
2390 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2391
773d2021 2392 RTL_W32(MAC4, high);
908ba2bf 2393 RTL_R32(MAC4);
2394
78f1cd02 2395 RTL_W32(MAC0, low);
908ba2bf 2396 RTL_R32(MAC0);
2397
773d2021
FR		 2398 RTL_W8(Cfg9346, Cfg9346_Lock);
2399
2400 spin_unlock_irq(&tp->lock);
2401}
2402
2403static int rtl_set_mac_address(struct net_device *dev, void *p)
2404{
2405 struct rtl8169_private *tp = netdev_priv(dev);
2406 struct sockaddr *addr = p;
2407
2408 if (!is_valid_ether_addr(addr->sa_data))
2409 return -EADDRNOTAVAIL;
2410
2411 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2412
2413 rtl_rar_set(tp, dev->dev_addr);
2414
2415 return 0;
2416}
2417
5f787a1a
FR		 2418static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2419{
2420 struct rtl8169_private *tp = netdev_priv(dev);
2421 struct mii_ioctl_data *data = if_mii(ifr);
2422
8b4ab28d
FR		 2423 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2424}
5f787a1a 2425
8b4ab28d
FR		 2426static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2427{
5f787a1a
FR		 2428 switch (cmd) {
2429 case SIOCGMIIPHY:
2430 data->phy_id = 32; /* Internal PHY */
2431 return 0;
2432
2433 case SIOCGMIIREG:
4da19633 2434 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2435 return 0;
2436
2437 case SIOCSMIIREG:
4da19633 2438 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2439 return 0;
2440 }
2441 return -EOPNOTSUPP;
2442}
2443
8b4ab28d
FR		 2444static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2445{
2446 return -EOPNOTSUPP;
2447}
2448
0e485150
FR		 2449static const struct rtl_cfg_info {
2450 void (*hw_start)(struct net_device *);
2451 unsigned int region;
2452 unsigned int align;
2453 u16 intr_event;
2454 u16 napi_event;
ccdffb9a 2455 unsigned features;
f21b75e9 2456 u8 default_ver;
0e485150
FR		 2457} rtl_cfg_infos [] = {
2458 [RTL_CFG_0] = {
2459 .hw_start = rtl_hw_start_8169,
2460 .region = 1,
e9f63f30 2461 .align = 0,
0e485150
FR		 2462 .intr_event = SYSErr | LinkChg | RxOverflow |
2463 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2464 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2465 .features = RTL_FEATURE_GMII,
2466 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2467 },
2468 [RTL_CFG_1] = {
2469 .hw_start = rtl_hw_start_8168,
2470 .region = 2,
2471 .align = 8,
53f57357 2472 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2473 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2474 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2475 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2476 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2477 },
2478 [RTL_CFG_2] = {
2479 .hw_start = rtl_hw_start_8101,
2480 .region = 2,
2481 .align = 8,
2482 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2483 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2484 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2485 .features = RTL_FEATURE_MSI,
2486 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2487 }
2488};
2489
fbac58fc
FR		 2490/* Cfg9346_Unlock assumed. */
2491static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2492 const struct rtl_cfg_info *cfg)
2493{
2494 unsigned msi = 0;
2495 u8 cfg2;
2496
2497 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2498 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2499 if (pci_enable_msi(pdev)) {
2500 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2501 } else {
2502 cfg2 |= MSIEnable;
2503 msi = RTL_FEATURE_MSI;
2504 }
2505 }
2506 RTL_W8(Config2, cfg2);
2507 return msi;
2508}
2509
2510static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2511{
2512 if (tp->features & RTL_FEATURE_MSI) {
2513 pci_disable_msi(pdev);
2514 tp->features &= ~RTL_FEATURE_MSI;
2515 }
2516}
2517
8b4ab28d
FR		 2518static const struct net_device_ops rtl8169_netdev_ops = {
2519 .ndo_open = rtl8169_open,
2520 .ndo_stop = rtl8169_close,
2521 .ndo_get_stats = rtl8169_get_stats,
00829823 2522 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2523 .ndo_tx_timeout = rtl8169_tx_timeout,
2524 .ndo_validate_addr = eth_validate_addr,
2525 .ndo_change_mtu = rtl8169_change_mtu,
2526 .ndo_set_mac_address = rtl_set_mac_address,
2527 .ndo_do_ioctl = rtl8169_ioctl,
2528 .ndo_set_multicast_list = rtl_set_rx_mode,
2529#ifdef CONFIG_R8169_VLAN
2530 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2531#endif
2532#ifdef CONFIG_NET_POLL_CONTROLLER
2533 .ndo_poll_controller = rtl8169_netpoll,
2534#endif
2535
2536};
2537
c0e45c1c 2538static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2539{
2540 struct mdio_ops *ops = &tp->mdio_ops;
2541
2542 switch (tp->mac_version) {
2543 case RTL_GIGA_MAC_VER_27:
2544 ops->write = r8168dp_1_mdio_write;
2545 ops->read = r8168dp_1_mdio_read;
2546 break;
2547 default:
2548 ops->write = r8169_mdio_write;
2549 ops->read = r8169_mdio_read;
2550 break;
2551 }
2552}
2553
1da177e4 2554static int __devinit
4ff96fa6 2555rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2556{
0e485150
FR		 2557 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2558 const unsigned int region = cfg->region;
1da177e4 2559 struct rtl8169_private *tp;
ccdffb9a 2560 struct mii_if_info *mii;
4ff96fa6
FR		 2561 struct net_device *dev;
2562 void __iomem *ioaddr;
07d3f51f
FR		 2563 unsigned int i;
2564 int rc;
1da177e4 2565
4ff96fa6
FR		 2566 if (netif_msg_drv(&debug)) {
2567 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2568 MODULENAME, RTL8169_VERSION);
2569 }
1da177e4 2570
1da177e4 2571 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2572 if (!dev) {
b57b7e5a 2573 if (netif_msg_drv(&debug))
9b91cf9d 2574 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2575 rc = -ENOMEM;
2576 goto out;
1da177e4
LT		 2577 }
2578
1da177e4 2579 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2580 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 2581 tp = netdev_priv(dev);
c4028958 2582 tp->dev = dev;
21e197f2 2583 tp->pci_dev = pdev;
b57b7e5a 2584 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2585
ccdffb9a
FR		 2586 mii = &tp->mii;
2587 mii->dev = dev;
2588 mii->mdio_read = rtl_mdio_read;
2589 mii->mdio_write = rtl_mdio_write;
2590 mii->phy_id_mask = 0x1f;
2591 mii->reg_num_mask = 0x1f;
2592 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2593
1da177e4
LT		 2594 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2595 rc = pci_enable_device(pdev);
b57b7e5a 2596 if (rc < 0) {
bf82c189 2597 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 2598 goto err_out_free_dev_1;
1da177e4
LT		 2599 }
2600
87aeec76 2601 if (pci_set_mwi(pdev) < 0)
2602 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 2603
1da177e4 2604 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2605 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 2606 netif_err(tp, probe, dev,
2607 "region #%d not an MMIO resource, aborting\n",
2608 region);
1da177e4 2609 rc = -ENODEV;
87aeec76 2610 goto err_out_mwi_2;
1da177e4 2611 }
4ff96fa6 2612
1da177e4 2613 /* check for weird/broken PCI region reporting */
bcf0bf90 2614 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 2615 netif_err(tp, probe, dev,
2616 "Invalid PCI region size(s), aborting\n");
1da177e4 2617 rc = -ENODEV;
87aeec76 2618 goto err_out_mwi_2;
1da177e4
LT		 2619 }
2620
2621 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2622 if (rc < 0) {
bf82c189 2623 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 2624 goto err_out_mwi_2;
1da177e4
LT		 2625 }
2626
2627 tp->cp_cmd = PCIMulRW | RxChkSum;
2628
2629 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 2630 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2631 tp->cp_cmd |= PCIDAC;
2632 dev->features |= NETIF_F_HIGHDMA;
2633 } else {
284901a9 2634 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2635 if (rc < 0) {
bf82c189 2636 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 2637 goto err_out_free_res_3;
1da177e4
LT		 2638 }
2639 }
2640
1da177e4 2641 /* ioremap MMIO region */
bcf0bf90 2642 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2643 if (!ioaddr) {
bf82c189 2644 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 2645 rc = -EIO;
87aeec76 2646 goto err_out_free_res_3;
1da177e4
LT		 2647 }
2648
4300e8c7
DM		 2649 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2650 if (!tp->pcie_cap)
2651 netif_info(tp, probe, dev, "no PCI Express capability\n");
2652
d78ad8cb 2653 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2654
2655 /* Soft reset the chip. */
2656 RTL_W8(ChipCmd, CmdReset);
2657
2658 /* Check that the chip has finished the reset. */
07d3f51f 2659 for (i = 0; i < 100; i++) {
1da177e4
LT		 2660 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2661 break;
b518fa8e 2662 msleep_interruptible(1);
1da177e4
LT		 2663 }
2664
d78ad8cb
KW		 2665 RTL_W16(IntrStatus, 0xffff);
2666
ca52efd5 2667 pci_set_master(pdev);
2668
1da177e4
LT		 2669 /* Identify chip attached to board */
2670 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 2671
c0e45c1c 2672 rtl_init_mdio_ops(tp);
2673
f21b75e9
JD		 2674 /* Use appropriate default if unknown */
2675 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 2676 netif_notice(tp, probe, dev,
2677 "unknown MAC, using family default\n");
f21b75e9
JD		 2678 tp->mac_version = cfg->default_ver;
2679 }
2680
1da177e4 2681 rtl8169_print_mac_version(tp);
1da177e4 2682
cee60c37 2683 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2684 if (tp->mac_version == rtl_chip_info[i].mac_version)
2685 break;
2686 }
cee60c37 2687 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 2688 dev_err(&pdev->dev,
2689 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 2690 goto err_out_msi_4;
1da177e4
LT		 2691 }
2692 tp->chipset = i;
2693
5d06a99f
FR		 2694 RTL_W8(Cfg9346, Cfg9346_Unlock);
2695 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2696 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2697 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2698 tp->features |= RTL_FEATURE_WOL;
2699 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2700 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2701 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2702 RTL_W8(Cfg9346, Cfg9346_Lock);
2703
66ec5d4f
FR		 2704 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2705 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2706 tp->set_speed = rtl8169_set_speed_tbi;
2707 tp->get_settings = rtl8169_gset_tbi;
2708 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2709 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2710 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2711 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2712
64e4bfb4 2713 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2714 } else {
2715 tp->set_speed = rtl8169_set_speed_xmii;
2716 tp->get_settings = rtl8169_gset_xmii;
2717 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2718 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2719 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2720 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2721 }
2722
df58ef51
FR		 2723 spin_lock_init(&tp->lock);
2724
738e1e69
PV		 2725 tp->mmio_addr = ioaddr;
2726
7bf6bf48 2727 /* Get MAC address */
1da177e4
LT		 2728 for (i = 0; i < MAC_ADDR_LEN; i++)
2729 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2730 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2731
1da177e4 2732 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2733 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2734 dev->irq = pdev->irq;
2735 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2736
bea3348e 2737 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2738
2739#ifdef CONFIG_R8169_VLAN
2740 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 2741#endif
2edae08e 2742 dev->features |= NETIF_F_GRO;
1da177e4
LT		 2743
2744 tp->intr_mask = 0xffff;
0e485150
FR		 2745 tp->hw_start = cfg->hw_start;
2746 tp->intr_event = cfg->intr_event;
2747 tp->napi_event = cfg->napi_event;
1da177e4 2748
2efa53f3
FR		 2749 init_timer(&tp->timer);
2750 tp->timer.data = (unsigned long) dev;
2751 tp->timer.function = rtl8169_phy_timer;
2752
1da177e4 2753 rc = register_netdev(dev);
4ff96fa6 2754 if (rc < 0)
87aeec76 2755 goto err_out_msi_4;
1da177e4
LT		 2756
2757 pci_set_drvdata(pdev, dev);
2758
bf82c189
JP		 2759 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
2760 rtl_chip_info[tp->chipset].name,
2761 dev->base_addr, dev->dev_addr,
2762 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 2763
4ff96fa6 2764 rtl8169_init_phy(dev, tp);
05af2142
SW		 2765
2766 /*
2767 * Pretend we are using VLANs; This bypasses a nasty bug where
2768 * Interrupts stop flowing on high load on 8110SCd controllers.
2769 */
2770 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2771 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
2772
8b76ab39 2773 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2774
f3ec4f87
AS		 2775 if (pci_dev_run_wake(pdev))
2776 pm_runtime_put_noidle(&pdev->dev);
e1759441 2777
4ff96fa6
FR		 2778out:
2779 return rc;
1da177e4 2780
87aeec76 2781err_out_msi_4:
fbac58fc 2782 rtl_disable_msi(pdev, tp);
4ff96fa6 2783 iounmap(ioaddr);
87aeec76 2784err_out_free_res_3:
4ff96fa6 2785 pci_release_regions(pdev);
87aeec76 2786err_out_mwi_2:
4ff96fa6 2787 pci_clear_mwi(pdev);
4ff96fa6
FR		 2788 pci_disable_device(pdev);
2789err_out_free_dev_1:
2790 free_netdev(dev);
2791 goto out;
1da177e4
LT		 2792}
2793
07d3f51f 2794static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2795{
2796 struct net_device *dev = pci_get_drvdata(pdev);
2797 struct rtl8169_private *tp = netdev_priv(dev);
2798
23f333a2 2799 cancel_delayed_work_sync(&tp->task);
eb2a021c 2800
1da177e4 2801 unregister_netdev(dev);
cc098dc7 2802
f3ec4f87
AS		 2803 if (pci_dev_run_wake(pdev))
2804 pm_runtime_get_noresume(&pdev->dev);
e1759441 2805
cc098dc7
IV		 2806 /* restore original MAC address */
2807 rtl_rar_set(tp, dev->perm_addr);
2808
fbac58fc 2809 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2810 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2811 pci_set_drvdata(pdev, NULL);
2812}
2813
1da177e4
LT		 2814static int rtl8169_open(struct net_device *dev)
2815{
2816 struct rtl8169_private *tp = netdev_priv(dev);
2817 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2818 int retval = -ENOMEM;
1da177e4 2819
e1759441 2820 pm_runtime_get_sync(&pdev->dev);
1da177e4 2821
1da177e4
LT		 2822 /*
2823 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 2824 * dma_alloc_coherent provides more.
1da177e4 2825 */
82553bb6
SG		 2826 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
2827 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 2828 if (!tp->TxDescArray)
e1759441 2829 goto err_pm_runtime_put;
1da177e4 2830
82553bb6
SG		 2831 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
2832 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 2833 if (!tp->RxDescArray)
99f252b0 2834 goto err_free_tx_0;
1da177e4
LT		 2835
2836 retval = rtl8169_init_ring(dev);
2837 if (retval < 0)
99f252b0 2838 goto err_free_rx_1;
1da177e4 2839
c4028958 2840 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2841
99f252b0
FR		 2842 smp_mb();
2843
fbac58fc
FR		 2844 retval = request_irq(dev->irq, rtl8169_interrupt,
2845 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2846 dev->name, dev);
2847 if (retval < 0)
2848 goto err_release_ring_2;
2849
bea3348e 2850 napi_enable(&tp->napi);
bea3348e 2851
07ce4064 2852 rtl_hw_start(dev);
1da177e4
LT		 2853
2854 rtl8169_request_timer(dev);
2855
e1759441
RW		 2856 tp->saved_wolopts = 0;
2857 pm_runtime_put_noidle(&pdev->dev);
2858
1da177e4
LT		 2859 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2860out:
2861 return retval;
2862
99f252b0
FR		 2863err_release_ring_2:
2864 rtl8169_rx_clear(tp);
2865err_free_rx_1:
82553bb6
SG		 2866 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
2867 tp->RxPhyAddr);
e1759441 2868 tp->RxDescArray = NULL;
99f252b0 2869err_free_tx_0:
82553bb6
SG		 2870 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
2871 tp->TxPhyAddr);
e1759441
RW		 2872 tp->TxDescArray = NULL;
2873err_pm_runtime_put:
2874 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 2875 goto out;
2876}
2877
2878static void rtl8169_hw_reset(void __iomem *ioaddr)
2879{
2880 /* Disable interrupts */
2881 rtl8169_irq_mask_and_ack(ioaddr);
2882
2883 /* Reset the chipset */
2884 RTL_W8(ChipCmd, CmdReset);
2885
2886 /* PCI commit */
2887 RTL_R8(ChipCmd);
2888}
2889
7f796d83 2890static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2891{
2892 void __iomem *ioaddr = tp->mmio_addr;
2893 u32 cfg = rtl8169_rx_config;
2894
2895 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2896 RTL_W32(RxConfig, cfg);
2897
2898 /* Set DMA burst size and Interframe Gap Time */
2899 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2900 (InterFrameGap << TxInterFrameGapShift));
2901}
2902
07ce4064 2903static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2904{
2905 struct rtl8169_private *tp = netdev_priv(dev);
2906 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2907 unsigned int i;
1da177e4
LT		 2908
2909 /* Soft reset the chip. */
2910 RTL_W8(ChipCmd, CmdReset);
2911
2912 /* Check that the chip has finished the reset. */
07d3f51f 2913 for (i = 0; i < 100; i++) {
1da177e4
LT		 2914 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2915 break;
b518fa8e 2916 msleep_interruptible(1);
1da177e4
LT		 2917 }
2918
07ce4064
FR		 2919 tp->hw_start(dev);
2920
07ce4064
FR		 2921 netif_start_queue(dev);
2922}
2923
2924
7f796d83
FR		 2925static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2926 void __iomem *ioaddr)
2927{
2928 /*
2929 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2930 * register to be written before TxDescAddrLow to work.
2931 * Switching from MMIO to I/O access fixes the issue as well.
2932 */
2933 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 2934 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 2935 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 2936 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2937}
2938
2939static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2940{
2941 u16 cmd;
2942
2943 cmd = RTL_R16(CPlusCmd);
2944 RTL_W16(CPlusCmd, cmd);
2945 return cmd;
2946}
2947
fdd7b4c3 2948static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 2949{
2950 /* Low hurts. Let's disable the filtering. */
207d6e87 2951 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 2952}
2953
6dccd16b
FR		 2954static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2955{
350f7596 2956 static const struct {
6dccd16b
FR		 2957 u32 mac_version;
2958 u32 clk;
2959 u32 val;
2960 } cfg2_info [] = {
2961 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2962 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2963 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2964 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2965 }, *p = cfg2_info;
2966 unsigned int i;
2967 u32 clk;
2968
2969 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2970 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2971 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2972 RTL_W32(0x7c, p->val);
2973 break;
2974 }
2975 }
2976}
2977
07ce4064
FR		 2978static void rtl_hw_start_8169(struct net_device *dev)
2979{
2980 struct rtl8169_private *tp = netdev_priv(dev);
2981 void __iomem *ioaddr = tp->mmio_addr;
2982 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2983
9cb427b6
FR		 2984 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2985 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2986 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2987 }
2988
1da177e4 2989 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2990 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2991 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2992 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2993 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2994 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2995
f0298f81 2996 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 2997
6f0333b8 2998 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 2999
c946b304
FR		 3000 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3001 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3002 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3003 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3004 rtl_set_rx_tx_config_registers(tp);
1da177e4 3005
7f796d83 3006 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3007
bcf0bf90
FR		 3008 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3009 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3010 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3011 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3012 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3013 }
3014
bcf0bf90
FR		 3015 RTL_W16(CPlusCmd, tp->cp_cmd);
3016
6dccd16b
FR		 3017 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3018
1da177e4
LT		 3019 /*
3020 * Undocumented corner. Supposedly:
3021 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3022 */
3023 RTL_W16(IntrMitigate, 0x0000);
3024
7f796d83 3025 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3026
c946b304
FR		 3027 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3028 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3029 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3030 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3031 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3032 rtl_set_rx_tx_config_registers(tp);
3033 }
3034
1da177e4 3035 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3036
3037 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3038 RTL_R8(IntrMask);
1da177e4
LT		 3039
3040 RTL_W32(RxMissed, 0);
3041
07ce4064 3042 rtl_set_rx_mode(dev);
1da177e4
LT		 3043
3044 /* no early-rx interrupts */
3045 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3046
3047 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3048 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3049}
1da177e4 3050
9c14ceaf 3051static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3052{
9c14ceaf
FR		 3053 struct net_device *dev = pci_get_drvdata(pdev);
3054 struct rtl8169_private *tp = netdev_priv(dev);
3055 int cap = tp->pcie_cap;
3056
3057 if (cap) {
3058 u16 ctl;
458a9f61 3059
9c14ceaf
FR		 3060 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3061 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3062 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3063 }
458a9f61
FR		 3064}
3065
dacf8154
FR		 3066static void rtl_csi_access_enable(void __iomem *ioaddr)
3067{
3068 u32 csi;
3069
3070 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3071 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3072}
3073
3074struct ephy_info {
3075 unsigned int offset;
3076 u16 mask;
3077 u16 bits;
3078};
3079
350f7596 3080static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3081{
3082 u16 w;
3083
3084 while (len-- > 0) {
3085 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3086 rtl_ephy_write(ioaddr, e->offset, w);
3087 e++;
3088 }
3089}
3090
b726e493
FR		 3091static void rtl_disable_clock_request(struct pci_dev *pdev)
3092{
3093 struct net_device *dev = pci_get_drvdata(pdev);
3094 struct rtl8169_private *tp = netdev_priv(dev);
3095 int cap = tp->pcie_cap;
3096
3097 if (cap) {
3098 u16 ctl;
3099
3100 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3101 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3102 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3103 }
3104}
3105
3106#define R8168_CPCMD_QUIRK_MASK (\
3107 EnableBist | \
3108 Mac_dbgo_oe | \
3109 Force_half_dup | \
3110 Force_rxflow_en | \
3111 Force_txflow_en | \
3112 Cxpl_dbg_sel | \
3113 ASF | \
3114 PktCntrDisable | \
3115 Mac_dbgo_sel)
3116
219a1e9d
FR		 3117static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3118{
b726e493
FR		 3119 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3120
3121 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3122
2e68ae44
FR		 3123 rtl_tx_performance_tweak(pdev,
3124 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3125}
3126
3127static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3128{
3129 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3130
f0298f81 3131 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3132
3133 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3134}
3135
3136static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3137{
b726e493
FR		 3138 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3139
3140 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3141
219a1e9d 3142 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3143
3144 rtl_disable_clock_request(pdev);
3145
3146 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3147}
3148
ef3386f0 3149static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3150{
350f7596 3151 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3152 { 0x01, 0, 0x0001 },
3153 { 0x02, 0x0800, 0x1000 },
3154 { 0x03, 0, 0x0042 },
3155 { 0x06, 0x0080, 0x0000 },
3156 { 0x07, 0, 0x2000 }
3157 };
3158
3159 rtl_csi_access_enable(ioaddr);
3160
3161 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3162
219a1e9d
FR		 3163 __rtl_hw_start_8168cp(ioaddr, pdev);
3164}
3165
ef3386f0
FR		 3166static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3167{
3168 rtl_csi_access_enable(ioaddr);
3169
3170 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3171
3172 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3173
3174 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3175}
3176
7f3e3d3a
FR		 3177static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3178{
3179 rtl_csi_access_enable(ioaddr);
3180
3181 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3182
3183 /* Magic. */
3184 RTL_W8(DBG_REG, 0x20);
3185
f0298f81 3186 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3187
3188 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3189
3190 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3191}
3192
219a1e9d
FR		 3193static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3194{
350f7596 3195 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3196 { 0x02, 0x0800, 0x1000 },
3197 { 0x03, 0, 0x0002 },
3198 { 0x06, 0x0080, 0x0000 }
3199 };
3200
3201 rtl_csi_access_enable(ioaddr);
3202
3203 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3204
3205 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3206
219a1e9d
FR		 3207 __rtl_hw_start_8168cp(ioaddr, pdev);
3208}
3209
3210static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3211{
350f7596 3212 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3213 { 0x01, 0, 0x0001 },
3214 { 0x03, 0x0400, 0x0220 }
3215 };
3216
3217 rtl_csi_access_enable(ioaddr);
3218
3219 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3220
219a1e9d
FR		 3221 __rtl_hw_start_8168cp(ioaddr, pdev);
3222}
3223
197ff761
FR		 3224static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3225{
3226 rtl_hw_start_8168c_2(ioaddr, pdev);
3227}
3228
6fb07058
FR		 3229static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3230{
3231 rtl_csi_access_enable(ioaddr);
3232
3233 __rtl_hw_start_8168cp(ioaddr, pdev);
3234}
3235
5b538df9
FR		 3236static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3237{
3238 rtl_csi_access_enable(ioaddr);
3239
3240 rtl_disable_clock_request(pdev);
3241
f0298f81 3242 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3243
3244 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3245
3246 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3247}
3248
07ce4064
FR		 3249static void rtl_hw_start_8168(struct net_device *dev)
3250{
2dd99530
FR		 3251 struct rtl8169_private *tp = netdev_priv(dev);
3252 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3253 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3254
3255 RTL_W8(Cfg9346, Cfg9346_Unlock);
3256
f0298f81 3257 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3258
6f0333b8 3259 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3260
0e485150 3261 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3262
3263 RTL_W16(CPlusCmd, tp->cp_cmd);
3264
0e485150 3265 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3266
0e485150
FR		 3267 /* Work around for RxFIFO overflow. */
3268 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3269 tp->intr_event |= RxFIFOOver | PCSTimeout;
3270 tp->intr_event &= ~RxOverflow;
3271 }
3272
3273 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3274
b8363901
FR		 3275 rtl_set_rx_mode(dev);
3276
3277 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3278 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3279
3280 RTL_R8(IntrMask);
3281
219a1e9d
FR		 3282 switch (tp->mac_version) {
3283 case RTL_GIGA_MAC_VER_11:
3284 rtl_hw_start_8168bb(ioaddr, pdev);
3285 break;
3286
3287 case RTL_GIGA_MAC_VER_12:
3288 case RTL_GIGA_MAC_VER_17:
3289 rtl_hw_start_8168bef(ioaddr, pdev);
3290 break;
3291
3292 case RTL_GIGA_MAC_VER_18:
ef3386f0 3293 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3294 break;
3295
3296 case RTL_GIGA_MAC_VER_19:
3297 rtl_hw_start_8168c_1(ioaddr, pdev);
3298 break;
3299
3300 case RTL_GIGA_MAC_VER_20:
3301 rtl_hw_start_8168c_2(ioaddr, pdev);
3302 break;
3303
197ff761
FR		 3304 case RTL_GIGA_MAC_VER_21:
3305 rtl_hw_start_8168c_3(ioaddr, pdev);
3306 break;
3307
6fb07058
FR		 3308 case RTL_GIGA_MAC_VER_22:
3309 rtl_hw_start_8168c_4(ioaddr, pdev);
3310 break;
3311
ef3386f0
FR		 3312 case RTL_GIGA_MAC_VER_23:
3313 rtl_hw_start_8168cp_2(ioaddr, pdev);
3314 break;
3315
7f3e3d3a
FR		 3316 case RTL_GIGA_MAC_VER_24:
3317 rtl_hw_start_8168cp_3(ioaddr, pdev);
3318 break;
3319
5b538df9 3320 case RTL_GIGA_MAC_VER_25:
daf9df6d 3321 case RTL_GIGA_MAC_VER_26:
3322 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3323 rtl_hw_start_8168d(ioaddr, pdev);
3324 break;
3325
219a1e9d
FR		 3326 default:
3327 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3328 dev->name, tp->mac_version);
3329 break;
3330 }
2dd99530 3331
0e485150
FR		 3332 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3333
b8363901
FR		 3334 RTL_W8(Cfg9346, Cfg9346_Lock);
3335
2dd99530 3336 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3337
0e485150 3338 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3339}
1da177e4 3340
2857ffb7
FR		 3341#define R810X_CPCMD_QUIRK_MASK (\
3342 EnableBist | \
3343 Mac_dbgo_oe | \
3344 Force_half_dup | \
5edcc537 3345 Force_rxflow_en | \
2857ffb7
FR		 3346 Force_txflow_en | \
3347 Cxpl_dbg_sel | \
3348 ASF | \
3349 PktCntrDisable | \
3350 PCIDAC | \
3351 PCIMulRW)
3352
3353static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3354{
350f7596 3355 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3356 { 0x01, 0, 0x6e65 },
3357 { 0x02, 0, 0x091f },
3358 { 0x03, 0, 0xc2f9 },
3359 { 0x06, 0, 0xafb5 },
3360 { 0x07, 0, 0x0e00 },
3361 { 0x19, 0, 0xec80 },
3362 { 0x01, 0, 0x2e65 },
3363 { 0x01, 0, 0x6e65 }
3364 };
3365 u8 cfg1;
3366
3367 rtl_csi_access_enable(ioaddr);
3368
3369 RTL_W8(DBG_REG, FIX_NAK_1);
3370
3371 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3372
3373 RTL_W8(Config1,
3374 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3375 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3376
3377 cfg1 = RTL_R8(Config1);
3378 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3379 RTL_W8(Config1, cfg1 & ~LEDS0);
3380
3381 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3382
3383 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3384}
3385
3386static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3387{
3388 rtl_csi_access_enable(ioaddr);
3389
3390 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3391
3392 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3393 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3394
3395 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3396}
3397
3398static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3399{
3400 rtl_hw_start_8102e_2(ioaddr, pdev);
3401
3402 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3403}
3404
07ce4064
FR		 3405static void rtl_hw_start_8101(struct net_device *dev)
3406{
cdf1a608
FR		 3407 struct rtl8169_private *tp = netdev_priv(dev);
3408 void __iomem *ioaddr = tp->mmio_addr;
3409 struct pci_dev *pdev = tp->pci_dev;
3410
e3cf0cc0
FR		 3411 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3412 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3413 int cap = tp->pcie_cap;
3414
3415 if (cap) {
3416 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3417 PCI_EXP_DEVCTL_NOSNOOP_EN);
3418 }
cdf1a608
FR		 3419 }
3420
2857ffb7
FR		 3421 switch (tp->mac_version) {
3422 case RTL_GIGA_MAC_VER_07:
3423 rtl_hw_start_8102e_1(ioaddr, pdev);
3424 break;
3425
3426 case RTL_GIGA_MAC_VER_08:
3427 rtl_hw_start_8102e_3(ioaddr, pdev);
3428 break;
3429
3430 case RTL_GIGA_MAC_VER_09:
3431 rtl_hw_start_8102e_2(ioaddr, pdev);
3432 break;
cdf1a608
FR		 3433 }
3434
3435 RTL_W8(Cfg9346, Cfg9346_Unlock);
3436
f0298f81 3437 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 3438
6f0333b8 3439 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3440
3441 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3442
3443 RTL_W16(CPlusCmd, tp->cp_cmd);
3444
3445 RTL_W16(IntrMitigate, 0x0000);
3446
3447 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3448
3449 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3450 rtl_set_rx_tx_config_registers(tp);
3451
3452 RTL_W8(Cfg9346, Cfg9346_Lock);
3453
3454 RTL_R8(IntrMask);
3455
cdf1a608
FR		 3456 rtl_set_rx_mode(dev);
3457
0e485150
FR		 3458 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3459
cdf1a608 3460 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3461
0e485150 3462 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3463}
3464
3465static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3466{
1da177e4
LT		 3467 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3468 return -EINVAL;
3469
3470 dev->mtu = new_mtu;
323bb685 3471 return 0;
1da177e4
LT		 3472}
3473
3474static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3475{
95e0918d 3476 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3477 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3478}
3479
6f0333b8
ED		 3480static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3481 void **data_buff, struct RxDesc *desc)
1da177e4 3482{
48addcc9 3483 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3484 DMA_FROM_DEVICE);
48addcc9 3485
6f0333b8
ED		 3486 kfree(*data_buff);
3487 *data_buff = NULL;
1da177e4
LT		 3488 rtl8169_make_unusable_by_asic(desc);
3489}
3490
3491static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3492{
3493 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3494
3495 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3496}
3497
3498static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3499 u32 rx_buf_sz)
3500{
3501 desc->addr = cpu_to_le64(mapping);
3502 wmb();
3503 rtl8169_mark_to_asic(desc, rx_buf_sz);
3504}
3505
6f0333b8
ED		 3506static inline void *rtl8169_align(void *data)
3507{
3508 return (void *)ALIGN((long)data, 16);
3509}
3510
0ecbe1ca
SG		 3511static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3512 struct RxDesc *desc)
1da177e4 3513{
6f0333b8 3514 void *data;
1da177e4 3515 dma_addr_t mapping;
48addcc9 3516 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 3517 struct net_device *dev = tp->dev;
6f0333b8 3518 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 3519
6f0333b8
ED		 3520 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
3521 if (!data)
3522 return NULL;
e9f63f30 3523
6f0333b8
ED		 3524 if (rtl8169_align(data) != data) {
3525 kfree(data);
3526 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
3527 if (!data)
3528 return NULL;
3529 }
3eafe507 3530
48addcc9 3531 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 3532 DMA_FROM_DEVICE);
d827d86b
SG		 3533 if (unlikely(dma_mapping_error(d, mapping))) {
3534 if (net_ratelimit())
3535 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 3536 goto err_out;
d827d86b 3537 }
1da177e4
LT		 3538
3539 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 3540 return data;
3eafe507
SG		 3541
3542err_out:
3543 kfree(data);
3544 return NULL;
1da177e4
LT		 3545}
3546
3547static void rtl8169_rx_clear(struct rtl8169_private *tp)
3548{
07d3f51f 3549 unsigned int i;
1da177e4
LT		 3550
3551 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 3552 if (tp->Rx_databuff[i]) {
3553 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 3554 tp->RxDescArray + i);
3555 }
3556 }
3557}
3558
0ecbe1ca 3559static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 3560{
0ecbe1ca
SG		 3561 desc->opts1 |= cpu_to_le32(RingEnd);
3562}
5b0384f4 3563
0ecbe1ca
SG		 3564static int rtl8169_rx_fill(struct rtl8169_private *tp)
3565{
3566 unsigned int i;
1da177e4 3567
0ecbe1ca
SG		 3568 for (i = 0; i < NUM_RX_DESC; i++) {
3569 void *data;
4ae47c2d 3570
6f0333b8 3571 if (tp->Rx_databuff[i])
1da177e4 3572 continue;
bcf0bf90 3573
0ecbe1ca 3574 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 3575 if (!data) {
3576 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 3577 goto err_out;
6f0333b8
ED		 3578 }
3579 tp->Rx_databuff[i] = data;
1da177e4 3580 }
1da177e4 3581
0ecbe1ca
SG		 3582 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3583 return 0;
3584
3585err_out:
3586 rtl8169_rx_clear(tp);
3587 return -ENOMEM;
1da177e4
LT		 3588}
3589
3590static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3591{
3592 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3593}
3594
3595static int rtl8169_init_ring(struct net_device *dev)
3596{
3597 struct rtl8169_private *tp = netdev_priv(dev);
3598
3599 rtl8169_init_ring_indexes(tp);
3600
3601 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 3602 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 3603
0ecbe1ca 3604 return rtl8169_rx_fill(tp);
1da177e4
LT		 3605}
3606
48addcc9 3607static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 3608 struct TxDesc *desc)
3609{
3610 unsigned int len = tx_skb->len;
3611
48addcc9
SG		 3612 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3613
1da177e4
LT		 3614 desc->opts1 = 0x00;
3615 desc->opts2 = 0x00;
3616 desc->addr = 0x00;
3617 tx_skb->len = 0;
3618}
3619
3eafe507
SG		 3620static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3621 unsigned int n)
1da177e4
LT		 3622{
3623 unsigned int i;
3624
3eafe507
SG		 3625 for (i = 0; i < n; i++) {
3626 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 3627 struct ring_info *tx_skb = tp->tx_skb + entry;
3628 unsigned int len = tx_skb->len;
3629
3630 if (len) {
3631 struct sk_buff *skb = tx_skb->skb;
3632
48addcc9 3633 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 3634 tp->TxDescArray + entry);
3635 if (skb) {
cac4b22f 3636 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3637 dev_kfree_skb(skb);
3638 tx_skb->skb = NULL;
3639 }
1da177e4
LT		 3640 }
3641 }
3eafe507
SG		 3642}
3643
3644static void rtl8169_tx_clear(struct rtl8169_private *tp)
3645{
3646 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 3647 tp->cur_tx = tp->dirty_tx = 0;
3648}
3649
c4028958 3650static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3651{
3652 struct rtl8169_private *tp = netdev_priv(dev);
3653
c4028958 3654 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3655 schedule_delayed_work(&tp->task, 4);
3656}
3657
3658static void rtl8169_wait_for_quiescence(struct net_device *dev)
3659{
3660 struct rtl8169_private *tp = netdev_priv(dev);
3661 void __iomem *ioaddr = tp->mmio_addr;
3662
3663 synchronize_irq(dev->irq);
3664
3665 /* Wait for any pending NAPI task to complete */
bea3348e 3666 napi_disable(&tp->napi);
1da177e4
LT		 3667
3668 rtl8169_irq_mask_and_ack(ioaddr);
3669
d1d08d12
DM		 3670 tp->intr_mask = 0xffff;
3671 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3672 napi_enable(&tp->napi);
1da177e4
LT		 3673}
3674
c4028958 3675static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3676{
c4028958
DH		 3677 struct rtl8169_private *tp =
3678 container_of(work, struct rtl8169_private, task.work);
3679 struct net_device *dev = tp->dev;
1da177e4
LT		 3680 int ret;
3681
eb2a021c
FR		 3682 rtnl_lock();
3683
3684 if (!netif_running(dev))
3685 goto out_unlock;
3686
3687 rtl8169_wait_for_quiescence(dev);
3688 rtl8169_close(dev);
1da177e4
LT		 3689
3690 ret = rtl8169_open(dev);
3691 if (unlikely(ret < 0)) {
bf82c189
JP		 3692 if (net_ratelimit())
3693 netif_err(tp, drv, dev,
3694 "reinit failure (status = %d). Rescheduling\n",
3695 ret);
1da177e4
LT		 3696 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3697 }
eb2a021c
FR		 3698
3699out_unlock:
3700 rtnl_unlock();
1da177e4
LT		 3701}
3702
c4028958 3703static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3704{
c4028958
DH		 3705 struct rtl8169_private *tp =
3706 container_of(work, struct rtl8169_private, task.work);
3707 struct net_device *dev = tp->dev;
1da177e4 3708
eb2a021c
FR		 3709 rtnl_lock();
3710
1da177e4 3711 if (!netif_running(dev))
eb2a021c 3712 goto out_unlock;
1da177e4
LT		 3713
3714 rtl8169_wait_for_quiescence(dev);
3715
bea3348e 3716 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3717 rtl8169_tx_clear(tp);
3718
3719 if (tp->dirty_rx == tp->cur_rx) {
3720 rtl8169_init_ring_indexes(tp);
07ce4064 3721 rtl_hw_start(dev);
1da177e4 3722 netif_wake_queue(dev);
cebf8cc7 3723 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3724 } else {
bf82c189
JP		 3725 if (net_ratelimit())
3726 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 3727 rtl8169_schedule_work(dev, rtl8169_reset_task);
3728 }
eb2a021c
FR		 3729
3730out_unlock:
3731 rtnl_unlock();
1da177e4
LT		 3732}
3733
3734static void rtl8169_tx_timeout(struct net_device *dev)
3735{
3736 struct rtl8169_private *tp = netdev_priv(dev);
3737
3738 rtl8169_hw_reset(tp->mmio_addr);
3739
3740 /* Let's wait a bit while any (async) irq lands on */
3741 rtl8169_schedule_work(dev, rtl8169_reset_task);
3742}
3743
3744static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3745 u32 opts1)
3746{
3747 struct skb_shared_info *info = skb_shinfo(skb);
3748 unsigned int cur_frag, entry;
a6343afb 3749 struct TxDesc * uninitialized_var(txd);
48addcc9 3750 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 3751
3752 entry = tp->cur_tx;
3753 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3754 skb_frag_t *frag = info->frags + cur_frag;
3755 dma_addr_t mapping;
3756 u32 status, len;
3757 void *addr;
3758
3759 entry = (entry + 1) % NUM_TX_DESC;
3760
3761 txd = tp->TxDescArray + entry;
3762 len = frag->size;
3763 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 3764 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 3765 if (unlikely(dma_mapping_error(d, mapping))) {
3766 if (net_ratelimit())
3767 netif_err(tp, drv, tp->dev,
3768 "Failed to map TX fragments DMA!\n");
3eafe507 3769 goto err_out;
d827d86b 3770 }
1da177e4
LT		 3771
3772 /* anti gcc 2.95.3 bugware (sic) */
3773 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3774
3775 txd->opts1 = cpu_to_le32(status);
3776 txd->addr = cpu_to_le64(mapping);
3777
3778 tp->tx_skb[entry].len = len;
3779 }
3780
3781 if (cur_frag) {
3782 tp->tx_skb[entry].skb = skb;
3783 txd->opts1 |= cpu_to_le32(LastFrag);
3784 }
3785
3786 return cur_frag;
3eafe507
SG		 3787
3788err_out:
3789 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
3790 return -EIO;
1da177e4
LT		 3791}
3792
3793static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3794{
3795 if (dev->features & NETIF_F_TSO) {
7967168c 3796 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3797
3798 if (mss)
3799 return LargeSend | ((mss & MSSMask) << MSSShift);
3800 }
84fa7933 3801 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3802 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3803
3804 if (ip->protocol == IPPROTO_TCP)
3805 return IPCS | TCPCS;
3806 else if (ip->protocol == IPPROTO_UDP)
3807 return IPCS | UDPCS;
3808 WARN_ON(1); /* we need a WARN() */
3809 }
3810 return 0;
3811}
3812
61357325
SH		 3813static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
3814 struct net_device *dev)
1da177e4
LT		 3815{
3816 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 3817 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 3818 struct TxDesc *txd = tp->TxDescArray + entry;
3819 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 3820 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 3821 dma_addr_t mapping;
3822 u32 status, len;
3823 u32 opts1;
3eafe507 3824 int frags;
5b0384f4 3825
1da177e4 3826 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 3827 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 3828 goto err_stop_0;
1da177e4
LT		 3829 }
3830
3831 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 3832 goto err_stop_0;
3833
3834 len = skb_headlen(skb);
48addcc9 3835 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 3836 if (unlikely(dma_mapping_error(d, mapping))) {
3837 if (net_ratelimit())
3838 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 3839 goto err_dma_0;
d827d86b 3840 }
3eafe507
SG		 3841
3842 tp->tx_skb[entry].len = len;
3843 txd->addr = cpu_to_le64(mapping);
3844 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 3845
3846 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3847
3848 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 3849 if (frags < 0)
3850 goto err_dma_1;
3851 else if (frags)
1da177e4 3852 opts1 |= FirstFrag;
3eafe507 3853 else {
1da177e4
LT		 3854 opts1 |= FirstFrag | LastFrag;
3855 tp->tx_skb[entry].skb = skb;
3856 }
3857
1da177e4
LT		 3858 wmb();
3859
3860 /* anti gcc 2.95.3 bugware (sic) */
3861 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3862 txd->opts1 = cpu_to_le32(status);
3863
1da177e4
LT		 3864 tp->cur_tx += frags + 1;
3865
4c020a96 3866 wmb();
1da177e4 3867
275391a4 3868 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3869
3870 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3871 netif_stop_queue(dev);
3872 smp_rmb();
3873 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3874 netif_wake_queue(dev);
3875 }
3876
61357325 3877 return NETDEV_TX_OK;
1da177e4 3878
3eafe507 3879err_dma_1:
48addcc9 3880 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 3881err_dma_0:
3882 dev_kfree_skb(skb);
3883 dev->stats.tx_dropped++;
3884 return NETDEV_TX_OK;
3885
3886err_stop_0:
1da177e4 3887 netif_stop_queue(dev);
cebf8cc7 3888 dev->stats.tx_dropped++;
61357325 3889 return NETDEV_TX_BUSY;
1da177e4
LT		 3890}
3891
3892static void rtl8169_pcierr_interrupt(struct net_device *dev)
3893{
3894 struct rtl8169_private *tp = netdev_priv(dev);
3895 struct pci_dev *pdev = tp->pci_dev;
3896 void __iomem *ioaddr = tp->mmio_addr;
3897 u16 pci_status, pci_cmd;
3898
3899 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3900 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3901
bf82c189
JP		 3902 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
3903 pci_cmd, pci_status);
1da177e4
LT		 3904
3905 /*
3906 * The recovery sequence below admits a very elaborated explanation:
3907 * - it seems to work;
d03902b8
FR		 3908 * - I did not see what else could be done;
3909 * - it makes iop3xx happy.
1da177e4
LT		 3910 *
3911 * Feel free to adjust to your needs.
3912 */
a27993f3 3913 if (pdev->broken_parity_status)
d03902b8
FR		 3914 pci_cmd &= ~PCI_COMMAND_PARITY;
3915 else
3916 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3917
3918 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3919
3920 pci_write_config_word(pdev, PCI_STATUS,
3921 pci_status & (PCI_STATUS_DETECTED_PARITY |
3922 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3923 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3924
3925 /* The infamous DAC f*ckup only happens at boot time */
3926 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
bf82c189 3927 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 3928 tp->cp_cmd &= ~PCIDAC;
3929 RTL_W16(CPlusCmd, tp->cp_cmd);
3930 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3931 }
3932
3933 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3934
3935 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3936}
3937
07d3f51f
FR		 3938static void rtl8169_tx_interrupt(struct net_device *dev,
3939 struct rtl8169_private *tp,
3940 void __iomem *ioaddr)
1da177e4
LT		 3941{
3942 unsigned int dirty_tx, tx_left;
3943
1da177e4
LT		 3944 dirty_tx = tp->dirty_tx;
3945 smp_rmb();
3946 tx_left = tp->cur_tx - dirty_tx;
3947
3948 while (tx_left > 0) {
3949 unsigned int entry = dirty_tx % NUM_TX_DESC;
3950 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 3951 u32 status;
3952
3953 rmb();
3954 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3955 if (status & DescOwn)
3956 break;
3957
48addcc9
SG		 3958 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
3959 tp->TxDescArray + entry);
1da177e4 3960 if (status & LastFrag) {
cac4b22f
SG		 3961 dev->stats.tx_packets++;
3962 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 3963 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 3964 tx_skb->skb = NULL;
3965 }
3966 dirty_tx++;
3967 tx_left--;
3968 }
3969
3970 if (tp->dirty_tx != dirty_tx) {
3971 tp->dirty_tx = dirty_tx;
3972 smp_wmb();
3973 if (netif_queue_stopped(dev) &&
3974 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3975 netif_wake_queue(dev);
3976 }
d78ae2dc
FR		 3977 /*
3978 * 8168 hack: TxPoll requests are lost when the Tx packets are
3979 * too close. Let's kick an extra TxPoll request when a burst
3980 * of start_xmit activity is detected (if it is not detected,
3981 * it is slow enough). -- FR
3982 */
3983 smp_rmb();
3984 if (tp->cur_tx != dirty_tx)
3985 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3986 }
3987}
3988
126fa4b9
FR		 3989static inline int rtl8169_fragmented_frame(u32 status)
3990{
3991 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3992}
3993
adea1ac7 3994static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 3995{
1da177e4
LT		 3996 u32 status = opts1 & RxProtoMask;
3997
3998 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 3999 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4000 skb->ip_summed = CHECKSUM_UNNECESSARY;
4001 else
bc8acf2c 4002 skb_checksum_none_assert(skb);
1da177e4
LT		 4003}
4004
6f0333b8
ED		 4005static struct sk_buff *rtl8169_try_rx_copy(void *data,
4006 struct rtl8169_private *tp,
4007 int pkt_size,
4008 dma_addr_t addr)
1da177e4 4009{
b449655f 4010 struct sk_buff *skb;
48addcc9 4011 struct device *d = &tp->pci_dev->dev;
b449655f 4012
6f0333b8 4013 data = rtl8169_align(data);
48addcc9 4014 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4015 prefetch(data);
4016 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4017 if (skb)
4018 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4019 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4020
6f0333b8 4021 return skb;
1da177e4
LT		 4022}
4023
630b943c
ED		 4024/*
4025 * Warning : rtl8169_rx_interrupt() might be called :
4026 * 1) from NAPI (softirq) context
4027 * (polling = 1 : we should call netif_receive_skb())
4028 * 2) from process context (rtl8169_reset_task())
4029 * (polling = 0 : we must call netif_rx() instead)
4030 */
07d3f51f
FR		 4031static int rtl8169_rx_interrupt(struct net_device *dev,
4032 struct rtl8169_private *tp,
bea3348e 4033 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4034{
4035 unsigned int cur_rx, rx_left;
6f0333b8 4036 unsigned int count;
630b943c 4037 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4038
1da177e4
LT		 4039 cur_rx = tp->cur_rx;
4040 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4041 rx_left = min(rx_left, budget);
1da177e4 4042
4dcb7d33 4043 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4044 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4045 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4046 u32 status;
4047
4048 rmb();
126fa4b9 4049 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4050
4051 if (status & DescOwn)
4052 break;
4dcb7d33 4053 if (unlikely(status & RxRES)) {
bf82c189
JP		 4054 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4055 status);
cebf8cc7 4056 dev->stats.rx_errors++;
1da177e4 4057 if (status & (RxRWT | RxRUNT))
cebf8cc7 4058 dev->stats.rx_length_errors++;
1da177e4 4059 if (status & RxCRC)
cebf8cc7 4060 dev->stats.rx_crc_errors++;
9dccf611
FR		 4061 if (status & RxFOVF) {
4062 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4063 dev->stats.rx_fifo_errors++;
9dccf611 4064 }
6f0333b8 4065 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4066 } else {
6f0333b8 4067 struct sk_buff *skb;
b449655f 4068 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4069 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4070
126fa4b9
FR		 4071 /*
4072 * The driver does not support incoming fragmented
4073 * frames. They are seen as a symptom of over-mtu
4074 * sized frames.
4075 */
4076 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4077 dev->stats.rx_dropped++;
4078 dev->stats.rx_length_errors++;
6f0333b8 4079 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4080 continue;
126fa4b9
FR		 4081 }
4082
6f0333b8
ED		 4083 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4084 tp, pkt_size, addr);
4085 rtl8169_mark_to_asic(desc, rx_buf_sz);
4086 if (!skb) {
4087 dev->stats.rx_dropped++;
4088 continue;
1da177e4
LT		 4089 }
4090
adea1ac7 4091 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4092 skb_put(skb, pkt_size);
4093 skb->protocol = eth_type_trans(skb, dev);
4094
630b943c
ED		 4095 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4096 if (likely(polling))
2edae08e 4097 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4098 else
4099 netif_rx(skb);
4100 }
1da177e4 4101
cebf8cc7
FR		 4102 dev->stats.rx_bytes += pkt_size;
4103 dev->stats.rx_packets++;
1da177e4 4104 }
6dccd16b
FR		 4105
4106 /* Work around for AMD plateform. */
95e0918d 4107 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4108 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4109 desc->opts2 = 0;
4110 cur_rx++;
4111 }
1da177e4
LT		 4112 }
4113
4114 count = cur_rx - tp->cur_rx;
4115 tp->cur_rx = cur_rx;
4116
6f0333b8 4117 tp->dirty_rx += count;
1da177e4
LT		 4118
4119 return count;
4120}
4121
07d3f51f 4122static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4123{
07d3f51f 4124 struct net_device *dev = dev_instance;
1da177e4 4125 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4126 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4127 int handled = 0;
865c652d 4128 int status;
1da177e4 4129
f11a377b
DD		 4130 /* loop handling interrupts until we have no new ones or
4131 * we hit a invalid/hotplug case.
4132 */
865c652d 4133 status = RTL_R16(IntrStatus);
f11a377b
DD		 4134 while (status && status != 0xffff) {
4135 handled = 1;
1da177e4 4136
f11a377b
DD		 4137 /* Handle all of the error cases first. These will reset
4138 * the chip, so just exit the loop.
4139 */
4140 if (unlikely(!netif_running(dev))) {
4141 rtl8169_asic_down(ioaddr);
4142 break;
4143 }
1da177e4 4144
f11a377b 4145 /* Work around for rx fifo overflow */
53f57357 4146 if (unlikely(status & RxFIFOOver) &&
4147 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
f11a377b
DD		 4148 netif_stop_queue(dev);
4149 rtl8169_tx_timeout(dev);
4150 break;
4151 }
1da177e4 4152
f11a377b
DD		 4153 if (unlikely(status & SYSErr)) {
4154 rtl8169_pcierr_interrupt(dev);
4155 break;
4156 }
1da177e4 4157
f11a377b 4158 if (status & LinkChg)
e4fbce74 4159 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4160
f11a377b
DD		 4161 /* We need to see the lastest version of tp->intr_mask to
4162 * avoid ignoring an MSI interrupt and having to wait for
4163 * another event which may never come.
4164 */
4165 smp_rmb();
4166 if (status & tp->intr_mask & tp->napi_event) {
4167 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4168 tp->intr_mask = ~tp->napi_event;
4169
4170 if (likely(napi_schedule_prep(&tp->napi)))
4171 __napi_schedule(&tp->napi);
bf82c189
JP		 4172 else
4173 netif_info(tp, intr, dev,
4174 "interrupt %04x in poll\n", status);
f11a377b 4175 }
1da177e4 4176
f11a377b
DD		 4177 /* We only get a new MSI interrupt when all active irq
4178 * sources on the chip have been acknowledged. So, ack
4179 * everything we've seen and check if new sources have become
4180 * active to avoid blocking all interrupts from the chip.
4181 */
4182 RTL_W16(IntrStatus,
4183 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4184 status = RTL_R16(IntrStatus);
865c652d 4185 }
1da177e4 4186
1da177e4
LT		 4187 return IRQ_RETVAL(handled);
4188}
4189
bea3348e 4190static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4191{
bea3348e
SH		 4192 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4193 struct net_device *dev = tp->dev;
1da177e4 4194 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4195 int work_done;
1da177e4 4196
bea3348e 4197 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4198 rtl8169_tx_interrupt(dev, tp, ioaddr);
4199
bea3348e 4200 if (work_done < budget) {
288379f0 4201 napi_complete(napi);
f11a377b
DD		 4202
4203 /* We need for force the visibility of tp->intr_mask
4204 * for other CPUs, as we can loose an MSI interrupt
4205 * and potentially wait for a retransmit timeout if we don't.
4206 * The posted write to IntrMask is safe, as it will
4207 * eventually make it to the chip and we won't loose anything
4208 * until it does.
1da177e4 4209 */
f11a377b 4210 tp->intr_mask = 0xffff;
4c020a96 4211 wmb();
0e485150 4212 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4213 }
4214
bea3348e 4215 return work_done;
1da177e4 4216}
1da177e4 4217
523a6094
FR		 4218static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4219{
4220 struct rtl8169_private *tp = netdev_priv(dev);
4221
4222 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4223 return;
4224
4225 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4226 RTL_W32(RxMissed, 0);
4227}
4228
1da177e4
LT		 4229static void rtl8169_down(struct net_device *dev)
4230{
4231 struct rtl8169_private *tp = netdev_priv(dev);
4232 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4233
4234 rtl8169_delete_timer(dev);
4235
4236 netif_stop_queue(dev);
4237
93dd79e8 4238 napi_disable(&tp->napi);
93dd79e8 4239
1da177e4
LT		 4240 spin_lock_irq(&tp->lock);
4241
4242 rtl8169_asic_down(ioaddr);
323bb685
SG		 4243 /*
4244 * At this point device interrupts can not be enabled in any function,
4245 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4246 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4247 */
523a6094 4248 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4249
4250 spin_unlock_irq(&tp->lock);
4251
4252 synchronize_irq(dev->irq);
4253
1da177e4 4254 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4255 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4256
1da177e4
LT		 4257 rtl8169_tx_clear(tp);
4258
4259 rtl8169_rx_clear(tp);
4260}
4261
4262static int rtl8169_close(struct net_device *dev)
4263{
4264 struct rtl8169_private *tp = netdev_priv(dev);
4265 struct pci_dev *pdev = tp->pci_dev;
4266
e1759441
RW		 4267 pm_runtime_get_sync(&pdev->dev);
4268
355423d0
IV		 4269 /* update counters before going down */
4270 rtl8169_update_counters(dev);
4271
1da177e4
LT		 4272 rtl8169_down(dev);
4273
4274 free_irq(dev->irq, dev);
4275
82553bb6
SG		 4276 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4277 tp->RxPhyAddr);
4278 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4279 tp->TxPhyAddr);
1da177e4
LT		 4280 tp->TxDescArray = NULL;
4281 tp->RxDescArray = NULL;
4282
e1759441
RW		 4283 pm_runtime_put_sync(&pdev->dev);
4284
1da177e4
LT		 4285 return 0;
4286}
4287
07ce4064 4288static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4289{
4290 struct rtl8169_private *tp = netdev_priv(dev);
4291 void __iomem *ioaddr = tp->mmio_addr;
4292 unsigned long flags;
4293 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4294 int rx_mode;
1da177e4
LT		 4295 u32 tmp = 0;
4296
4297 if (dev->flags & IFF_PROMISC) {
4298 /* Unconditionally log net taps. */
bf82c189 4299 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4300 rx_mode =
4301 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4302 AcceptAllPhys;
4303 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4304 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4305 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4306 /* Too many to filter perfectly -- accept all multicasts. */
4307 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4308 mc_filter[1] = mc_filter[0] = 0xffffffff;
4309 } else {
22bedad3 4310 struct netdev_hw_addr *ha;
07d3f51f 4311
1da177e4
LT		 4312 rx_mode = AcceptBroadcast | AcceptMyPhys;
4313 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4314 netdev_for_each_mc_addr(ha, dev) {
4315 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4316 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4317 rx_mode |= AcceptMulticast;
4318 }
4319 }
4320
4321 spin_lock_irqsave(&tp->lock, flags);
4322
4323 tmp = rtl8169_rx_config | rx_mode |
4324 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4325
f887cce8 4326 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4327 u32 data = mc_filter[0];
4328
4329 mc_filter[0] = swab32(mc_filter[1]);
4330 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4331 }
4332
1da177e4 4333 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4334 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4335
57a9f236
FR		 4336 RTL_W32(RxConfig, tmp);
4337
1da177e4
LT		 4338 spin_unlock_irqrestore(&tp->lock, flags);
4339}
4340
4341/**
4342 * rtl8169_get_stats - Get rtl8169 read/write statistics
4343 * @dev: The Ethernet Device to get statistics for
4344 *
4345 * Get TX/RX statistics for rtl8169
4346 */
4347static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4348{
4349 struct rtl8169_private *tp = netdev_priv(dev);
4350 void __iomem *ioaddr = tp->mmio_addr;
4351 unsigned long flags;
4352
4353 if (netif_running(dev)) {
4354 spin_lock_irqsave(&tp->lock, flags);
523a6094 4355 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4356 spin_unlock_irqrestore(&tp->lock, flags);
4357 }
5b0384f4 4358
cebf8cc7 4359 return &dev->stats;
1da177e4
LT		 4360}
4361
861ab440 4362static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4363{
5d06a99f 4364 if (!netif_running(dev))
861ab440 4365 return;
5d06a99f
FR		 4366
4367 netif_device_detach(dev);
4368 netif_stop_queue(dev);
861ab440
RW		 4369}
4370
4371#ifdef CONFIG_PM
4372
4373static int rtl8169_suspend(struct device *device)
4374{
4375 struct pci_dev *pdev = to_pci_dev(device);
4376 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4377
861ab440 4378 rtl8169_net_suspend(dev);
1371fa6d 4379
5d06a99f
FR		 4380 return 0;
4381}
4382
e1759441
RW		 4383static void __rtl8169_resume(struct net_device *dev)
4384{
4385 netif_device_attach(dev);
4386 rtl8169_schedule_work(dev, rtl8169_reset_task);
4387}
4388
861ab440 4389static int rtl8169_resume(struct device *device)
5d06a99f 4390{
861ab440 4391 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4392 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4393 struct rtl8169_private *tp = netdev_priv(dev);
4394
4395 rtl8169_init_phy(dev, tp);
5d06a99f 4396
e1759441
RW		 4397 if (netif_running(dev))
4398 __rtl8169_resume(dev);
5d06a99f 4399
e1759441
RW		 4400 return 0;
4401}
4402
4403static int rtl8169_runtime_suspend(struct device *device)
4404{
4405 struct pci_dev *pdev = to_pci_dev(device);
4406 struct net_device *dev = pci_get_drvdata(pdev);
4407 struct rtl8169_private *tp = netdev_priv(dev);
4408
4409 if (!tp->TxDescArray)
4410 return 0;
4411
4412 spin_lock_irq(&tp->lock);
4413 tp->saved_wolopts = __rtl8169_get_wol(tp);
4414 __rtl8169_set_wol(tp, WAKE_ANY);
4415 spin_unlock_irq(&tp->lock);
4416
4417 rtl8169_net_suspend(dev);
4418
4419 return 0;
4420}
4421
4422static int rtl8169_runtime_resume(struct device *device)
4423{
4424 struct pci_dev *pdev = to_pci_dev(device);
4425 struct net_device *dev = pci_get_drvdata(pdev);
4426 struct rtl8169_private *tp = netdev_priv(dev);
4427
4428 if (!tp->TxDescArray)
4429 return 0;
4430
4431 spin_lock_irq(&tp->lock);
4432 __rtl8169_set_wol(tp, tp->saved_wolopts);
4433 tp->saved_wolopts = 0;
4434 spin_unlock_irq(&tp->lock);
4435
fccec10b
SG		 4436 rtl8169_init_phy(dev, tp);
4437
e1759441 4438 __rtl8169_resume(dev);
5d06a99f 4439
5d06a99f
FR		 4440 return 0;
4441}
4442
e1759441
RW		 4443static int rtl8169_runtime_idle(struct device *device)
4444{
4445 struct pci_dev *pdev = to_pci_dev(device);
4446 struct net_device *dev = pci_get_drvdata(pdev);
4447 struct rtl8169_private *tp = netdev_priv(dev);
4448
e4fbce74 4449 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4450}
4451
47145210 4452static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4453 .suspend = rtl8169_suspend,
4454 .resume = rtl8169_resume,
4455 .freeze = rtl8169_suspend,
4456 .thaw = rtl8169_resume,
4457 .poweroff = rtl8169_suspend,
4458 .restore = rtl8169_resume,
e1759441
RW		 4459 .runtime_suspend = rtl8169_runtime_suspend,
4460 .runtime_resume = rtl8169_runtime_resume,
4461 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4462};
4463
4464#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4465
4466#else /* !CONFIG_PM */
4467
4468#define RTL8169_PM_OPS NULL
4469
4470#endif /* !CONFIG_PM */
4471
1765f95d
FR		 4472static void rtl_shutdown(struct pci_dev *pdev)
4473{
861ab440 4474 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 4475 struct rtl8169_private *tp = netdev_priv(dev);
4476 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 4477
4478 rtl8169_net_suspend(dev);
1765f95d 4479
cc098dc7
IV		 4480 /* restore original MAC address */
4481 rtl_rar_set(tp, dev->perm_addr);
4482
4bb3f522 4483 spin_lock_irq(&tp->lock);
4484
4485 rtl8169_asic_down(ioaddr);
4486
4487 spin_unlock_irq(&tp->lock);
4488
861ab440 4489 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 4490 /* WoL fails with some 8168 when the receiver is disabled. */
4491 if (tp->features & RTL_FEATURE_WOL) {
4492 pci_clear_master(pdev);
4493
4494 RTL_W8(ChipCmd, CmdRxEnb);
4495 /* PCI commit */
4496 RTL_R8(ChipCmd);
4497 }
4498
861ab440
RW		 4499 pci_wake_from_d3(pdev, true);
4500 pci_set_power_state(pdev, PCI_D3hot);
4501 }
4502}
5d06a99f 4503
1da177e4
LT		 4504static struct pci_driver rtl8169_pci_driver = {
4505 .name = MODULENAME,
4506 .id_table = rtl8169_pci_tbl,
4507 .probe = rtl8169_init_one,
4508 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 4509 .shutdown = rtl_shutdown,
861ab440 4510 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 4511};
4512
07d3f51f 4513static int __init rtl8169_init_module(void)
1da177e4 4514{
29917620 4515 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 4516}
4517
07d3f51f 4518static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 4519{
4520 pci_unregister_driver(&rtl8169_pci_driver);
4521}
4522
4523module_init(rtl8169_init_module);
4524module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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