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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 46
1da177e4
LT		 47#ifdef RTL8169_DEBUG
48#define assert(expr) \
5b0384f4
FR		 49 if (!(expr)) { \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 51 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 52 }
06fa7358
JP		 53#define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 55#else
56#define assert(expr) do {} while (0)
57#define dprintk(fmt, args...) do {} while (0)
58#endif /* RTL8169_DEBUG */
59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63#define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
1da177e4
LT		 66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 68static const int multicast_filter_limit = 32;
1da177e4
LT		 69
70/* MAC address length */
71#define MAC_ADDR_LEN 6
72
9c14ceaf 73#define MAX_READ_REQUEST_SHIFT 12
1da177e4 74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
85bffe6c 136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
85bffe6c
FR		 144#define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 146
3c6bee1d 147static const struct {
1da177e4 148 const char *name;
2b7b4318 149 enum rtl_tx_desc_version txd_version;
953a12cc 150 const char *fw_name;
85bffe6c
FR		 151} rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
70090424
HW		 219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
953a12cc 222};
85bffe6c 223#undef _R
953a12cc 224
bcf0bf90
FR		 225enum cfg_version {
226 RTL_CFG_0 = 0x00,
227 RTL_CFG_1,
228 RTL_CFG_2
229};
230
07ce4064
FR		 231static void rtl_hw_start_8169(struct net_device *);
232static void rtl_hw_start_8168(struct net_device *);
233static void rtl_hw_start_8101(struct net_device *);
234
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 242 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 243 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
244 { PCI_VENDOR_ID_LINKSYS, 0x1032,
245 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 246 { 0x0001, 0x8168,
247 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 248 {0,},
249};
250
251MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
252
6f0333b8 253static int rx_buf_sz = 16383;
4300e8c7 254static int use_dac;
b57b7e5a
SH		 255static struct {
256 u32 msg_enable;
257} debug = { -1 };
1da177e4 258
07d3f51f
FR		 259enum rtl_registers {
260 MAC0 = 0, /* Ethernet hardware address. */
773d2021 261 MAC4 = 4,
07d3f51f
FR		 262 MAR0 = 8, /* Multicast filter. */
263 CounterAddrLow = 0x10,
264 CounterAddrHigh = 0x14,
265 TxDescStartAddrLow = 0x20,
266 TxDescStartAddrHigh = 0x24,
267 TxHDescStartAddrLow = 0x28,
268 TxHDescStartAddrHigh = 0x2c,
269 FLASH = 0x30,
270 ERSR = 0x36,
271 ChipCmd = 0x37,
272 TxPoll = 0x38,
273 IntrMask = 0x3c,
274 IntrStatus = 0x3e,
4f6b00e5 275
07d3f51f 276 TxConfig = 0x40,
4f6b00e5
HW		 277#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
278#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 279
4f6b00e5
HW		 280 RxConfig = 0x44,
281#define RX128_INT_EN (1 << 15) /* 8111c and later */
282#define RX_MULTI_EN (1 << 14) /* 8111c only */
283#define RXCFG_FIFO_SHIFT 13
284 /* No threshold before first PCI xfer */
285#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
286#define RXCFG_DMA_SHIFT 8
287 /* Unlimited maximum PCI burst. */
288#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 289
07d3f51f
FR		 290 RxMissed = 0x4c,
291 Cfg9346 = 0x50,
292 Config0 = 0x51,
293 Config1 = 0x52,
294 Config2 = 0x53,
295 Config3 = 0x54,
296 Config4 = 0x55,
297 Config5 = 0x56,
298 MultiIntr = 0x5c,
299 PHYAR = 0x60,
07d3f51f
FR		 300 PHYstatus = 0x6c,
301 RxMaxSize = 0xda,
302 CPlusCmd = 0xe0,
303 IntrMitigate = 0xe2,
304 RxDescAddrLow = 0xe4,
305 RxDescAddrHigh = 0xe8,
f0298f81 306 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
307
308#define NoEarlyTx 0x3f /* Max value : no early transmit. */
309
310 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
311
312#define TxPacketMax (8064 >> 7)
313
07d3f51f
FR		 314 FuncEvent = 0xf0,
315 FuncEventMask = 0xf4,
316 FuncPresetState = 0xf8,
317 FuncForceEvent = 0xfc,
1da177e4
LT		 318};
319
f162a5d1
FR		 320enum rtl8110_registers {
321 TBICSR = 0x64,
322 TBI_ANAR = 0x68,
323 TBI_LPAR = 0x6a,
324};
325
326enum rtl8168_8101_registers {
327 CSIDR = 0x64,
328 CSIAR = 0x68,
329#define CSIAR_FLAG 0x80000000
330#define CSIAR_WRITE_CMD 0x80000000
331#define CSIAR_BYTE_ENABLE 0x0f
332#define CSIAR_BYTE_ENABLE_SHIFT 12
333#define CSIAR_ADDR_MASK 0x0fff
065c27c1 334 PMCH = 0x6f,
f162a5d1
FR		 335 EPHYAR = 0x80,
336#define EPHYAR_FLAG 0x80000000
337#define EPHYAR_WRITE_CMD 0x80000000
338#define EPHYAR_REG_MASK 0x1f
339#define EPHYAR_REG_SHIFT 16
340#define EPHYAR_DATA_MASK 0xffff
5a5e4443 341 DLLPR = 0xd0,
4f6b00e5 342#define PFM_EN (1 << 6)
f162a5d1
FR		 343 DBG_REG = 0xd1,
344#define FIX_NAK_1 (1 << 4)
345#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 346 TWSI = 0xd2,
347 MCU = 0xd3,
4f6b00e5 348#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 349#define EN_NDP (1 << 3)
350#define EN_OOB_RESET (1 << 2)
daf9df6d 351 EFUSEAR = 0xdc,
352#define EFUSEAR_FLAG 0x80000000
353#define EFUSEAR_WRITE_CMD 0x80000000
354#define EFUSEAR_READ_CMD 0x00000000
355#define EFUSEAR_REG_MASK 0x03ff
356#define EFUSEAR_REG_SHIFT 8
357#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 358};
359
c0e45c1c 360enum rtl8168_registers {
4f6b00e5
HW		 361 LED_FREQ = 0x1a,
362 EEE_LED = 0x1b,
b646d900 363 ERIDR = 0x70,
364 ERIAR = 0x74,
365#define ERIAR_FLAG 0x80000000
366#define ERIAR_WRITE_CMD 0x80000000
367#define ERIAR_READ_CMD 0x00000000
368#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 369#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 370#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
371#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
372#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
373#define ERIAR_MASK_SHIFT 12
374#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 377 EPHY_RXER_NUM = 0x7c,
378 OCPDR = 0xb0, /* OCP GPHY access */
379#define OCPDR_WRITE_CMD 0x80000000
380#define OCPDR_READ_CMD 0x00000000
381#define OCPDR_REG_MASK 0x7f
382#define OCPDR_GPHY_REG_SHIFT 16
383#define OCPDR_DATA_MASK 0xffff
384 OCPAR = 0xb4,
385#define OCPAR_FLAG 0x80000000
386#define OCPAR_GPHY_WRITE_CMD 0x8000f060
387#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 388 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
389 MISC = 0xf0, /* 8168e only. */
cecb5fd7 390#define TXPLA_RST (1 << 29)
4f6b00e5 391#define PWM_EN (1 << 22)
c0e45c1c 392};
393
07d3f51f 394enum rtl_register_content {
1da177e4 395 /* InterruptStatusBits */
07d3f51f
FR		 396 SYSErr = 0x8000,
397 PCSTimeout = 0x4000,
398 SWInt = 0x0100,
399 TxDescUnavail = 0x0080,
400 RxFIFOOver = 0x0040,
401 LinkChg = 0x0020,
402 RxOverflow = 0x0010,
403 TxErr = 0x0008,
404 TxOK = 0x0004,
405 RxErr = 0x0002,
406 RxOK = 0x0001,
1da177e4
LT		 407
408 /* RxStatusDesc */
9dccf611
FR		 409 RxFOVF = (1 << 23),
410 RxRWT = (1 << 22),
411 RxRES = (1 << 21),
412 RxRUNT = (1 << 20),
413 RxCRC = (1 << 19),
1da177e4
LT		 414
415 /* ChipCmdBits */
4f6b00e5 416 StopReq = 0x80,
07d3f51f
FR		 417 CmdReset = 0x10,
418 CmdRxEnb = 0x08,
419 CmdTxEnb = 0x04,
420 RxBufEmpty = 0x01,
1da177e4 421
275391a4
FR		 422 /* TXPoll register p.5 */
423 HPQ = 0x80, /* Poll cmd on the high prio queue */
424 NPQ = 0x40, /* Poll cmd on the low prio queue */
425 FSWInt = 0x01, /* Forced software interrupt */
426
1da177e4 427 /* Cfg9346Bits */
07d3f51f
FR		 428 Cfg9346_Lock = 0x00,
429 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 430
431 /* rx_mode_bits */
07d3f51f
FR		 432 AcceptErr = 0x20,
433 AcceptRunt = 0x10,
434 AcceptBroadcast = 0x08,
435 AcceptMulticast = 0x04,
436 AcceptMyPhys = 0x02,
437 AcceptAllPhys = 0x01,
1687b566 438#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 439
1da177e4
LT		 440 /* TxConfigBits */
441 TxInterFrameGapShift = 24,
442 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
443
5d06a99f 444 /* Config1 register p.24 */
f162a5d1
FR		 445 LEDS1 = (1 << 7),
446 LEDS0 = (1 << 6),
fbac58fc 447 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 448 Speed_down = (1 << 4),
449 MEMMAP = (1 << 3),
450 IOMAP = (1 << 2),
451 VPD = (1 << 1),
5d06a99f
FR		 452 PMEnable = (1 << 0), /* Power Management Enable */
453
6dccd16b
FR		 454 /* Config2 register p. 25 */
455 PCI_Clock_66MHz = 0x01,
456 PCI_Clock_33MHz = 0x00,
457
61a4dcc2
FR		 458 /* Config3 register p.25 */
459 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
460 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 461 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 462
5d06a99f 463 /* Config5 register p.27 */
61a4dcc2
FR		 464 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
465 MWF = (1 << 5), /* Accept Multicast wakeup frame */
466 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 467 Spi_en = (1 << 3),
61a4dcc2 468 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 469 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
470
1da177e4
LT		 471 /* TBICSR p.28 */
472 TBIReset = 0x80000000,
473 TBILoopback = 0x40000000,
474 TBINwEnable = 0x20000000,
475 TBINwRestart = 0x10000000,
476 TBILinkOk = 0x02000000,
477 TBINwComplete = 0x01000000,
478
479 /* CPlusCmd p.31 */
f162a5d1
FR		 480 EnableBist = (1 << 15), // 8168 8101
481 Mac_dbgo_oe = (1 << 14), // 8168 8101
482 Normal_mode = (1 << 13), // unused
483 Force_half_dup = (1 << 12), // 8168 8101
484 Force_rxflow_en = (1 << 11), // 8168 8101
485 Force_txflow_en = (1 << 10), // 8168 8101
486 Cxpl_dbg_sel = (1 << 9), // 8168 8101
487 ASF = (1 << 8), // 8168 8101
488 PktCntrDisable = (1 << 7), // 8168 8101
489 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 490 RxVlan = (1 << 6),
491 RxChkSum = (1 << 5),
492 PCIDAC = (1 << 4),
493 PCIMulRW = (1 << 3),
0e485150
FR		 494 INTT_0 = 0x0000, // 8168
495 INTT_1 = 0x0001, // 8168
496 INTT_2 = 0x0002, // 8168
497 INTT_3 = 0x0003, // 8168
1da177e4
LT		 498
499 /* rtl8169_PHYstatus */
07d3f51f
FR		 500 TBI_Enable = 0x80,
501 TxFlowCtrl = 0x40,
502 RxFlowCtrl = 0x20,
503 _1000bpsF = 0x10,
504 _100bps = 0x08,
505 _10bps = 0x04,
506 LinkStatus = 0x02,
507 FullDup = 0x01,
1da177e4 508
1da177e4 509 /* _TBICSRBit */
07d3f51f 510 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 511
512 /* DumpCounterCommand */
07d3f51f 513 CounterDump = 0x8,
1da177e4
LT		 514};
515
2b7b4318
FR		 516enum rtl_desc_bit {
517 /* First doubleword. */
1da177e4
LT		 518 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
519 RingEnd = (1 << 30), /* End of descriptor ring */
520 FirstFrag = (1 << 29), /* First segment of a packet */
521 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 522};
523
524/* Generic case. */
525enum rtl_tx_desc_bit {
526 /* First doubleword. */
527 TD_LSO = (1 << 27), /* Large Send Offload */
528#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 529
2b7b4318
FR		 530 /* Second doubleword. */
531 TxVlanTag = (1 << 17), /* Add VLAN tag */
532};
533
534/* 8169, 8168b and 810x except 8102e. */
535enum rtl_tx_desc_bit_0 {
536 /* First doubleword. */
537#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
538 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
539 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
540 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
541};
542
543/* 8102e, 8168c and beyond. */
544enum rtl_tx_desc_bit_1 {
545 /* Second doubleword. */
546#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
547 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
548 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
549 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
550};
1da177e4 551
2b7b4318
FR		 552static const struct rtl_tx_desc_info {
553 struct {
554 u32 udp;
555 u32 tcp;
556 } checksum;
557 u16 mss_shift;
558 u16 opts_offset;
559} tx_desc_info [] = {
560 [RTL_TD_0] = {
561 .checksum = {
562 .udp = TD0_IP_CS | TD0_UDP_CS,
563 .tcp = TD0_IP_CS | TD0_TCP_CS
564 },
565 .mss_shift = TD0_MSS_SHIFT,
566 .opts_offset = 0
567 },
568 [RTL_TD_1] = {
569 .checksum = {
570 .udp = TD1_IP_CS | TD1_UDP_CS,
571 .tcp = TD1_IP_CS | TD1_TCP_CS
572 },
573 .mss_shift = TD1_MSS_SHIFT,
574 .opts_offset = 1
575 }
576};
577
578enum rtl_rx_desc_bit {
1da177e4
LT		 579 /* Rx private */
580 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
581 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
582
583#define RxProtoUDP (PID1)
584#define RxProtoTCP (PID0)
585#define RxProtoIP (PID1 | PID0)
586#define RxProtoMask RxProtoIP
587
588 IPFail = (1 << 16), /* IP checksum failed */
589 UDPFail = (1 << 15), /* UDP/IP checksum failed */
590 TCPFail = (1 << 14), /* TCP/IP checksum failed */
591 RxVlanTag = (1 << 16), /* VLAN tag available */
592};
593
594#define RsvdMask 0x3fffc000
595
596struct TxDesc {
6cccd6e7
REB		 597 __le32 opts1;
598 __le32 opts2;
599 __le64 addr;
1da177e4
LT		 600};
601
602struct RxDesc {
6cccd6e7
REB		 603 __le32 opts1;
604 __le32 opts2;
605 __le64 addr;
1da177e4
LT		 606};
607
608struct ring_info {
609 struct sk_buff *skb;
610 u32 len;
611 u8 __pad[sizeof(void *) - sizeof(u32)];
612};
613
f23e7fda 614enum features {
ccdffb9a
FR		 615 RTL_FEATURE_WOL = (1 << 0),
616 RTL_FEATURE_MSI = (1 << 1),
617 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 618};
619
355423d0
IV		 620struct rtl8169_counters {
621 __le64 tx_packets;
622 __le64 rx_packets;
623 __le64 tx_errors;
624 __le32 rx_errors;
625 __le16 rx_missed;
626 __le16 align_errors;
627 __le32 tx_one_collision;
628 __le32 tx_multi_collision;
629 __le64 rx_unicast;
630 __le64 rx_broadcast;
631 __le32 rx_multicast;
632 __le16 tx_aborted;
633 __le16 tx_underun;
634};
635
1da177e4
LT		 636struct rtl8169_private {
637 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 638 struct pci_dev *pci_dev;
c4028958 639 struct net_device *dev;
bea3348e 640 struct napi_struct napi;
cecb5fd7 641 spinlock_t lock;
b57b7e5a 642 u32 msg_enable;
2b7b4318
FR		 643 u16 txd_version;
644 u16 mac_version;
1da177e4
LT		 645 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
646 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
647 u32 dirty_rx;
648 u32 dirty_tx;
649 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
650 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
651 dma_addr_t TxPhyAddr;
652 dma_addr_t RxPhyAddr;
6f0333b8 653 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 654 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 655 struct timer_list timer;
656 u16 cp_cmd;
0e485150
FR		 657 u16 intr_event;
658 u16 napi_event;
1da177e4 659 u16 intr_mask;
c0e45c1c 660
661 struct mdio_ops {
662 void (*write)(void __iomem *, int, int);
663 int (*read)(void __iomem *, int);
664 } mdio_ops;
665
065c27c1 666 struct pll_power_ops {
667 void (*down)(struct rtl8169_private *);
668 void (*up)(struct rtl8169_private *);
669 } pll_power_ops;
670
54405cde 671 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 672 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 673 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 674 void (*hw_start)(struct net_device *);
4da19633 675 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 676 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 677 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 678 struct delayed_work task;
f23e7fda 679 unsigned features;
ccdffb9a
FR		 680
681 struct mii_if_info mii;
355423d0 682 struct rtl8169_counters counters;
e1759441 683 u32 saved_wolopts;
f1e02ed1 684
b6ffd97f
FR		 685 struct rtl_fw {
686 const struct firmware *fw;
1c361efb
FR		 687
688#define RTL_VER_SIZE 32
689
690 char version[RTL_VER_SIZE];
691
692 struct rtl_fw_phy_action {
693 __le32 *code;
694 size_t size;
695 } phy_action;
b6ffd97f 696 } *rtl_fw;
497888cf 697#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 698};
699
979b6c13 700MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 701MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 702module_param(use_dac, int, 0);
4300e8c7 703MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 704module_param_named(debug, debug.msg_enable, int, 0);
705MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 706MODULE_LICENSE("GPL");
707MODULE_VERSION(RTL8169_VERSION);
bca03d5f 708MODULE_FIRMWARE(FIRMWARE_8168D_1);
709MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 710MODULE_FIRMWARE(FIRMWARE_8168E_1);
711MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 712MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 713
714static int rtl8169_open(struct net_device *dev);
61357325
SH		 715static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
716 struct net_device *dev);
7d12e780 717static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 718static int rtl8169_init_ring(struct net_device *dev);
07ce4064 719static void rtl_hw_start(struct net_device *dev);
1da177e4 720static int rtl8169_close(struct net_device *dev);
07ce4064 721static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 722static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 723static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 724static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 725 void __iomem *, u32 budget);
4dcb7d33 726static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 727static void rtl8169_down(struct net_device *dev);
99f252b0 728static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 729static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 730
b646d900 731static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
732{
733 void __iomem *ioaddr = tp->mmio_addr;
734 int i;
735
736 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
737 for (i = 0; i < 20; i++) {
738 udelay(100);
739 if (RTL_R32(OCPAR) & OCPAR_FLAG)
740 break;
741 }
742 return RTL_R32(OCPDR);
743}
744
745static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
746{
747 void __iomem *ioaddr = tp->mmio_addr;
748 int i;
749
750 RTL_W32(OCPDR, data);
751 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
752 for (i = 0; i < 20; i++) {
753 udelay(100);
754 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
755 break;
756 }
757}
758
fac5b3ca 759static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 760{
fac5b3ca 761 void __iomem *ioaddr = tp->mmio_addr;
b646d900 762 int i;
763
764 RTL_W8(ERIDR, cmd);
765 RTL_W32(ERIAR, 0x800010e8);
766 msleep(2);
767 for (i = 0; i < 5; i++) {
768 udelay(100);
1e4e82ba 769 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 770 break;
771 }
772
fac5b3ca 773 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 774}
775
776#define OOB_CMD_RESET 0x00
777#define OOB_CMD_DRIVER_START 0x05
778#define OOB_CMD_DRIVER_STOP 0x06
779
cecb5fd7
FR		 780static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
781{
782 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
783}
784
b646d900 785static void rtl8168_driver_start(struct rtl8169_private *tp)
786{
cecb5fd7 787 u16 reg;
b646d900 788 int i;
789
790 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
791
cecb5fd7 792 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 793
b646d900 794 for (i = 0; i < 10; i++) {
795 msleep(10);
4804b3b3 796 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 797 break;
798 }
799}
800
801static void rtl8168_driver_stop(struct rtl8169_private *tp)
802{
cecb5fd7 803 u16 reg;
b646d900 804 int i;
805
806 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
807
cecb5fd7 808 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 809
b646d900 810 for (i = 0; i < 10; i++) {
811 msleep(10);
4804b3b3 812 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 813 break;
814 }
815}
816
4804b3b3 817static int r8168dp_check_dash(struct rtl8169_private *tp)
818{
cecb5fd7 819 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 820
cecb5fd7 821 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 822}
b646d900 823
4da19633 824static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 825{
826 int i;
827
a6baf3af 828 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 829
2371408c 830 for (i = 20; i > 0; i--) {
07d3f51f
FR		 831 /*
832 * Check if the RTL8169 has completed writing to the specified
833 * MII register.
834 */
5b0384f4 835 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 836 break;
2371408c 837 udelay(25);
1da177e4 838 }
024a07ba 839 /*
81a95f04
TT		 840 * According to hardware specs a 20us delay is required after write
841 * complete indication, but before sending next command.
024a07ba 842 */
81a95f04 843 udelay(20);
1da177e4
LT		 844}
845
4da19633 846static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 847{
848 int i, value = -1;
849
a6baf3af 850 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 851
2371408c 852 for (i = 20; i > 0; i--) {
07d3f51f
FR		 853 /*
854 * Check if the RTL8169 has completed retrieving data from
855 * the specified MII register.
856 */
1da177e4 857 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 858 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 859 break;
860 }
2371408c 861 udelay(25);
1da177e4 862 }
81a95f04
TT		 863 /*
864 * According to hardware specs a 20us delay is required after read
865 * complete indication, but before sending next command.
866 */
867 udelay(20);
868
1da177e4
LT		 869 return value;
870}
871
c0e45c1c 872static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
873{
874 int i;
875
876 RTL_W32(OCPDR, data |
877 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
878 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
879 RTL_W32(EPHY_RXER_NUM, 0);
880
881 for (i = 0; i < 100; i++) {
882 mdelay(1);
883 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
884 break;
885 }
886}
887
888static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
889{
890 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
891 (value & OCPDR_DATA_MASK));
892}
893
894static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
895{
896 int i;
897
898 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
899
900 mdelay(1);
901 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
902 RTL_W32(EPHY_RXER_NUM, 0);
903
904 for (i = 0; i < 100; i++) {
905 mdelay(1);
906 if (RTL_R32(OCPAR) & OCPAR_FLAG)
907 break;
908 }
909
910 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
911}
912
e6de30d6 913#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
914
915static void r8168dp_2_mdio_start(void __iomem *ioaddr)
916{
917 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
918}
919
920static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
921{
922 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
923}
924
925static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
926{
927 r8168dp_2_mdio_start(ioaddr);
928
929 r8169_mdio_write(ioaddr, reg_addr, value);
930
931 r8168dp_2_mdio_stop(ioaddr);
932}
933
934static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
935{
936 int value;
937
938 r8168dp_2_mdio_start(ioaddr);
939
940 value = r8169_mdio_read(ioaddr, reg_addr);
941
942 r8168dp_2_mdio_stop(ioaddr);
943
944 return value;
945}
946
4da19633 947static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 948{
c0e45c1c 949 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 950}
951
4da19633 952static int rtl_readphy(struct rtl8169_private *tp, int location)
953{
c0e45c1c 954 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 955}
956
957static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
958{
959 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
960}
961
962static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 963{
964 int val;
965
4da19633 966 val = rtl_readphy(tp, reg_addr);
967 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 968}
969
ccdffb9a
FR		 970static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
971 int val)
972{
973 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 974
4da19633 975 rtl_writephy(tp, location, val);
ccdffb9a
FR		 976}
977
978static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
979{
980 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 981
4da19633 982 return rtl_readphy(tp, location);
ccdffb9a
FR		 983}
984
dacf8154
FR		 985static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
986{
987 unsigned int i;
988
989 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
990 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
991
992 for (i = 0; i < 100; i++) {
993 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
994 break;
995 udelay(10);
996 }
997}
998
999static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1000{
1001 u16 value = 0xffff;
1002 unsigned int i;
1003
1004 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1005
1006 for (i = 0; i < 100; i++) {
1007 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1008 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1009 break;
1010 }
1011 udelay(10);
1012 }
1013
1014 return value;
1015}
1016
1017static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1018{
1019 unsigned int i;
1020
1021 RTL_W32(CSIDR, value);
1022 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1023 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1024
1025 for (i = 0; i < 100; i++) {
1026 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1027 break;
1028 udelay(10);
1029 }
1030}
1031
1032static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1033{
1034 u32 value = ~0x00;
1035 unsigned int i;
1036
1037 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1038 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1039
1040 for (i = 0; i < 100; i++) {
1041 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1042 value = RTL_R32(CSIDR);
1043 break;
1044 }
1045 udelay(10);
1046 }
1047
1048 return value;
1049}
1050
133ac40a
HW		 1051static
1052void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1053{
1054 unsigned int i;
1055
1056 BUG_ON((addr & 3) || (mask == 0));
1057 RTL_W32(ERIDR, val);
1058 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1059
1060 for (i = 0; i < 100; i++) {
1061 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1062 break;
1063 udelay(100);
1064 }
1065}
1066
1067static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1068{
1069 u32 value = ~0x00;
1070 unsigned int i;
1071
1072 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1073
1074 for (i = 0; i < 100; i++) {
1075 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1076 value = RTL_R32(ERIDR);
1077 break;
1078 }
1079 udelay(100);
1080 }
1081
1082 return value;
1083}
1084
1085static void
1086rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1087{
1088 u32 val;
1089
1090 val = rtl_eri_read(ioaddr, addr, type);
1091 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1092}
1093
daf9df6d 1094static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1095{
1096 u8 value = 0xff;
1097 unsigned int i;
1098
1099 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1100
1101 for (i = 0; i < 300; i++) {
1102 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1103 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1104 break;
1105 }
1106 udelay(100);
1107 }
1108
1109 return value;
1110}
1111
1da177e4
LT		 1112static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1113{
1114 RTL_W16(IntrMask, 0x0000);
1115
1116 RTL_W16(IntrStatus, 0xffff);
1117}
1118
4da19633 1119static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1120{
4da19633 1121 void __iomem *ioaddr = tp->mmio_addr;
1122
1da177e4
LT		 1123 return RTL_R32(TBICSR) & TBIReset;
1124}
1125
4da19633 1126static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1127{
4da19633 1128 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1129}
1130
1131static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1132{
1133 return RTL_R32(TBICSR) & TBILinkOk;
1134}
1135
1136static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1137{
1138 return RTL_R8(PHYstatus) & LinkStatus;
1139}
1140
4da19633 1141static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1142{
4da19633 1143 void __iomem *ioaddr = tp->mmio_addr;
1144
1da177e4
LT		 1145 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1146}
1147
4da19633 1148static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1149{
1150 unsigned int val;
1151
4da19633 1152 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1153 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1154}
1155
70090424
HW		 1156static void rtl_link_chg_patch(struct rtl8169_private *tp)
1157{
1158 void __iomem *ioaddr = tp->mmio_addr;
1159 struct net_device *dev = tp->dev;
1160
1161 if (!netif_running(dev))
1162 return;
1163
1164 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1165 if (RTL_R8(PHYstatus) & _1000bpsF) {
1166 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1167 0x00000011, ERIAR_EXGMAC);
1168 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1169 0x00000005, ERIAR_EXGMAC);
1170 } else if (RTL_R8(PHYstatus) & _100bps) {
1171 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1172 0x0000001f, ERIAR_EXGMAC);
1173 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1174 0x00000005, ERIAR_EXGMAC);
1175 } else {
1176 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1177 0x0000001f, ERIAR_EXGMAC);
1178 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1179 0x0000003f, ERIAR_EXGMAC);
1180 }
1181 /* Reset packet filter */
1182 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1183 ERIAR_EXGMAC);
1184 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1185 ERIAR_EXGMAC);
1186 }
1187}
1188
e4fbce74 1189static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1190 struct rtl8169_private *tp,
1191 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1192{
1193 unsigned long flags;
1194
1195 spin_lock_irqsave(&tp->lock, flags);
1196 if (tp->link_ok(ioaddr)) {
70090424 1197 rtl_link_chg_patch(tp);
e1759441 1198 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1199 if (pm)
1200 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1201 netif_carrier_on(dev);
1519e57f
FR		 1202 if (net_ratelimit())
1203 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1204 } else {
1da177e4 1205 netif_carrier_off(dev);
bf82c189 1206 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1207 if (pm)
1208 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1209 }
1da177e4
LT		 1210 spin_unlock_irqrestore(&tp->lock, flags);
1211}
1212
e4fbce74
RW		 1213static void rtl8169_check_link_status(struct net_device *dev,
1214 struct rtl8169_private *tp,
1215 void __iomem *ioaddr)
1216{
1217 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1218}
1219
e1759441
RW		 1220#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1221
1222static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1223{
61a4dcc2
FR		 1224 void __iomem *ioaddr = tp->mmio_addr;
1225 u8 options;
e1759441 1226 u32 wolopts = 0;
61a4dcc2
FR		 1227
1228 options = RTL_R8(Config1);
1229 if (!(options & PMEnable))
e1759441 1230 return 0;
61a4dcc2
FR		 1231
1232 options = RTL_R8(Config3);
1233 if (options & LinkUp)
e1759441 1234 wolopts |= WAKE_PHY;
61a4dcc2 1235 if (options & MagicPacket)
e1759441 1236 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1237
1238 options = RTL_R8(Config5);
1239 if (options & UWF)
e1759441 1240 wolopts |= WAKE_UCAST;
61a4dcc2 1241 if (options & BWF)
e1759441 1242 wolopts |= WAKE_BCAST;
61a4dcc2 1243 if (options & MWF)
e1759441 1244 wolopts |= WAKE_MCAST;
61a4dcc2 1245
e1759441 1246 return wolopts;
61a4dcc2
FR		 1247}
1248
e1759441 1249static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1250{
1251 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1252
1253 spin_lock_irq(&tp->lock);
1254
1255 wol->supported = WAKE_ANY;
1256 wol->wolopts = __rtl8169_get_wol(tp);
1257
1258 spin_unlock_irq(&tp->lock);
1259}
1260
1261static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1262{
61a4dcc2 1263 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1264 unsigned int i;
350f7596 1265 static const struct {
61a4dcc2
FR		 1266 u32 opt;
1267 u16 reg;
1268 u8 mask;
1269 } cfg[] = {
1270 { WAKE_ANY, Config1, PMEnable },
1271 { WAKE_PHY, Config3, LinkUp },
1272 { WAKE_MAGIC, Config3, MagicPacket },
1273 { WAKE_UCAST, Config5, UWF },
1274 { WAKE_BCAST, Config5, BWF },
1275 { WAKE_MCAST, Config5, MWF },
1276 { WAKE_ANY, Config5, LanWake }
1277 };
1278
61a4dcc2
FR		 1279 RTL_W8(Cfg9346, Cfg9346_Unlock);
1280
1281 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1282 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1283 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1284 options |= cfg[i].mask;
1285 RTL_W8(cfg[i].reg, options);
1286 }
1287
1288 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1289}
1290
1291static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1292{
1293 struct rtl8169_private *tp = netdev_priv(dev);
1294
1295 spin_lock_irq(&tp->lock);
61a4dcc2 1296
f23e7fda
FR		 1297 if (wol->wolopts)
1298 tp->features |= RTL_FEATURE_WOL;
1299 else
1300 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1301 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1302 spin_unlock_irq(&tp->lock);
1303
ea80907f 1304 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1305
61a4dcc2
FR		 1306 return 0;
1307}
1308
31bd204f
FR		 1309static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1310{
85bffe6c 1311 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1312}
1313
1da177e4
LT		 1314static void rtl8169_get_drvinfo(struct net_device *dev,
1315 struct ethtool_drvinfo *info)
1316{
1317 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1318 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1319
1320 strcpy(info->driver, MODULENAME);
1321 strcpy(info->version, RTL8169_VERSION);
1322 strcpy(info->bus_info, pci_name(tp->pci_dev));
1c361efb
FR		 1323 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1324 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1325 rtl_fw->version);
1da177e4
LT		 1326}
1327
1328static int rtl8169_get_regs_len(struct net_device *dev)
1329{
1330 return R8169_REGS_SIZE;
1331}
1332
1333static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1334 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1335{
1336 struct rtl8169_private *tp = netdev_priv(dev);
1337 void __iomem *ioaddr = tp->mmio_addr;
1338 int ret = 0;
1339 u32 reg;
1340
1341 reg = RTL_R32(TBICSR);
1342 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1343 (duplex == DUPLEX_FULL)) {
1344 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1345 } else if (autoneg == AUTONEG_ENABLE)
1346 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1347 else {
bf82c189
JP		 1348 netif_warn(tp, link, dev,
1349 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1350 ret = -EOPNOTSUPP;
1351 }
1352
1353 return ret;
1354}
1355
1356static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1357 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1358{
1359 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1360 int giga_ctrl, bmcr;
54405cde 1361 int rc = -EINVAL;
1da177e4 1362
716b50a3 1363 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1364
1365 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1366 int auto_nego;
1367
4da19633 1368 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1369 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1370 ADVERTISE_100HALF | ADVERTISE_100FULL);
1371
1372 if (adv & ADVERTISED_10baseT_Half)
1373 auto_nego |= ADVERTISE_10HALF;
1374 if (adv & ADVERTISED_10baseT_Full)
1375 auto_nego |= ADVERTISE_10FULL;
1376 if (adv & ADVERTISED_100baseT_Half)
1377 auto_nego |= ADVERTISE_100HALF;
1378 if (adv & ADVERTISED_100baseT_Full)
1379 auto_nego |= ADVERTISE_100FULL;
1380
3577aa1b 1381 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1382
4da19633 1383 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1384 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1385
3577aa1b 1386 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1387 if (tp->mii.supports_gmii) {
54405cde
ON		 1388 if (adv & ADVERTISED_1000baseT_Half)
1389 giga_ctrl |= ADVERTISE_1000HALF;
1390 if (adv & ADVERTISED_1000baseT_Full)
1391 giga_ctrl |= ADVERTISE_1000FULL;
1392 } else if (adv & (ADVERTISED_1000baseT_Half |
1393 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1394 netif_info(tp, link, dev,
1395 "PHY does not support 1000Mbps\n");
54405cde 1396 goto out;
bcf0bf90 1397 }
1da177e4 1398
3577aa1b 1399 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1400
4da19633 1401 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1402 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1403 } else {
1404 giga_ctrl = 0;
1405
1406 if (speed == SPEED_10)
1407 bmcr = 0;
1408 else if (speed == SPEED_100)
1409 bmcr = BMCR_SPEED100;
1410 else
54405cde 1411 goto out;
3577aa1b 1412
1413 if (duplex == DUPLEX_FULL)
1414 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1415 }
1416
4da19633 1417 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1418
cecb5fd7
FR		 1419 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1420 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1421 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1422 rtl_writephy(tp, 0x17, 0x2138);
1423 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1424 } else {
4da19633 1425 rtl_writephy(tp, 0x17, 0x2108);
1426 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1427 }
1428 }
1429
54405cde
ON		 1430 rc = 0;
1431out:
1432 return rc;
1da177e4
LT		 1433}
1434
1435static int rtl8169_set_speed(struct net_device *dev,
54405cde 1436 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1437{
1438 struct rtl8169_private *tp = netdev_priv(dev);
1439 int ret;
1440
54405cde 1441 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1442 if (ret < 0)
1443 goto out;
1da177e4 1444
4876cc1e
FR		 1445 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1446 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1447 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1448 }
1449out:
1da177e4
LT		 1450 return ret;
1451}
1452
1453static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1454{
1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 unsigned long flags;
1457 int ret;
1458
4876cc1e
FR		 1459 del_timer_sync(&tp->timer);
1460
1da177e4 1461 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1462 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1463 cmd->duplex, cmd->advertising);
1da177e4 1464 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1465
1da177e4
LT		 1466 return ret;
1467}
1468
350fb32a 1469static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1470{
2b7b4318 1471 if (dev->mtu > TD_MSS_MAX)
350fb32a 1472 features &= ~NETIF_F_ALL_TSO;
1da177e4 1473
350fb32a 1474 return features;
1da177e4
LT		 1475}
1476
350fb32a 1477static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1478{
1479 struct rtl8169_private *tp = netdev_priv(dev);
1480 void __iomem *ioaddr = tp->mmio_addr;
1481 unsigned long flags;
1482
1483 spin_lock_irqsave(&tp->lock, flags);
1484
350fb32a 1485 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1486 tp->cp_cmd |= RxChkSum;
1487 else
1488 tp->cp_cmd &= ~RxChkSum;
1489
350fb32a
MM		 1490 if (dev->features & NETIF_F_HW_VLAN_RX)
1491 tp->cp_cmd |= RxVlan;
1492 else
1493 tp->cp_cmd &= ~RxVlan;
1494
1da177e4
LT		 1495 RTL_W16(CPlusCmd, tp->cp_cmd);
1496 RTL_R16(CPlusCmd);
1497
1498 spin_unlock_irqrestore(&tp->lock, flags);
1499
1500 return 0;
1501}
1502
1da177e4
LT		 1503static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1504 struct sk_buff *skb)
1505{
eab6d18d 1506 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1507 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1508}
1509
7a8fc77b 1510static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1511{
1512 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1513
7a8fc77b
FR		 1514 if (opts2 & RxVlanTag)
1515 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1516
1da177e4 1517 desc->opts2 = 0;
1da177e4
LT		 1518}
1519
ccdffb9a 1520static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1521{
1522 struct rtl8169_private *tp = netdev_priv(dev);
1523 void __iomem *ioaddr = tp->mmio_addr;
1524 u32 status;
1525
1526 cmd->supported =
1527 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1528 cmd->port = PORT_FIBRE;
1529 cmd->transceiver = XCVR_INTERNAL;
1530
1531 status = RTL_R32(TBICSR);
1532 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1533 cmd->autoneg = !!(status & TBINwEnable);
1534
70739497 1535 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1536 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1537
1538 return 0;
1da177e4
LT		 1539}
1540
ccdffb9a 1541static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1542{
1543 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1544
1545 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1546}
1547
1548static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1549{
1550 struct rtl8169_private *tp = netdev_priv(dev);
1551 unsigned long flags;
ccdffb9a 1552 int rc;
1da177e4
LT		 1553
1554 spin_lock_irqsave(&tp->lock, flags);
1555
ccdffb9a 1556 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1557
1558 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1559 return rc;
1da177e4
LT		 1560}
1561
1562static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1563 void *p)
1564{
5b0384f4
FR		 1565 struct rtl8169_private *tp = netdev_priv(dev);
1566 unsigned long flags;
1da177e4 1567
5b0384f4
FR		 1568 if (regs->len > R8169_REGS_SIZE)
1569 regs->len = R8169_REGS_SIZE;
1da177e4 1570
5b0384f4
FR		 1571 spin_lock_irqsave(&tp->lock, flags);
1572 memcpy_fromio(p, tp->mmio_addr, regs->len);
1573 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1574}
1575
b57b7e5a
SH		 1576static u32 rtl8169_get_msglevel(struct net_device *dev)
1577{
1578 struct rtl8169_private *tp = netdev_priv(dev);
1579
1580 return tp->msg_enable;
1581}
1582
1583static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1584{
1585 struct rtl8169_private *tp = netdev_priv(dev);
1586
1587 tp->msg_enable = value;
1588}
1589
d4a3a0fc
SH		 1590static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1591 "tx_packets",
1592 "rx_packets",
1593 "tx_errors",
1594 "rx_errors",
1595 "rx_missed",
1596 "align_errors",
1597 "tx_single_collisions",
1598 "tx_multi_collisions",
1599 "unicast",
1600 "broadcast",
1601 "multicast",
1602 "tx_aborted",
1603 "tx_underrun",
1604};
1605
b9f2c044 1606static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1607{
b9f2c044
JG		 1608 switch (sset) {
1609 case ETH_SS_STATS:
1610 return ARRAY_SIZE(rtl8169_gstrings);
1611 default:
1612 return -EOPNOTSUPP;
1613 }
d4a3a0fc
SH		 1614}
1615
355423d0 1616static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1617{
1618 struct rtl8169_private *tp = netdev_priv(dev);
1619 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1620 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1621 struct rtl8169_counters *counters;
1622 dma_addr_t paddr;
1623 u32 cmd;
355423d0 1624 int wait = 1000;
d4a3a0fc 1625
355423d0
IV		 1626 /*
1627 * Some chips are unable to dump tally counters when the receiver
1628 * is disabled.
1629 */
1630 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1631 return;
d4a3a0fc 1632
48addcc9 1633 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1634 if (!counters)
1635 return;
1636
1637 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1638 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1639 RTL_W32(CounterAddrLow, cmd);
1640 RTL_W32(CounterAddrLow, cmd | CounterDump);
1641
355423d0
IV		 1642 while (wait--) {
1643 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1644 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1645 break;
355423d0
IV		 1646 }
1647 udelay(10);
d4a3a0fc
SH		 1648 }
1649
1650 RTL_W32(CounterAddrLow, 0);
1651 RTL_W32(CounterAddrHigh, 0);
1652
48addcc9 1653 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1654}
1655
355423d0
IV		 1656static void rtl8169_get_ethtool_stats(struct net_device *dev,
1657 struct ethtool_stats *stats, u64 *data)
1658{
1659 struct rtl8169_private *tp = netdev_priv(dev);
1660
1661 ASSERT_RTNL();
1662
1663 rtl8169_update_counters(dev);
1664
1665 data[0] = le64_to_cpu(tp->counters.tx_packets);
1666 data[1] = le64_to_cpu(tp->counters.rx_packets);
1667 data[2] = le64_to_cpu(tp->counters.tx_errors);
1668 data[3] = le32_to_cpu(tp->counters.rx_errors);
1669 data[4] = le16_to_cpu(tp->counters.rx_missed);
1670 data[5] = le16_to_cpu(tp->counters.align_errors);
1671 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1672 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1673 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1674 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1675 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1676 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1677 data[12] = le16_to_cpu(tp->counters.tx_underun);
1678}
1679
d4a3a0fc
SH		 1680static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1681{
1682 switch(stringset) {
1683 case ETH_SS_STATS:
1684 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1685 break;
1686 }
1687}
1688
7282d491 1689static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1690 .get_drvinfo = rtl8169_get_drvinfo,
1691 .get_regs_len = rtl8169_get_regs_len,
1692 .get_link = ethtool_op_get_link,
1693 .get_settings = rtl8169_get_settings,
1694 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1695 .get_msglevel = rtl8169_get_msglevel,
1696 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1697 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1698 .get_wol = rtl8169_get_wol,
1699 .set_wol = rtl8169_set_wol,
d4a3a0fc 1700 .get_strings = rtl8169_get_strings,
b9f2c044 1701 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1702 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1703};
1704
07d3f51f 1705static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1706 struct net_device *dev, u8 default_version)
1da177e4 1707{
5d320a20 1708 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1709 /*
1710 * The driver currently handles the 8168Bf and the 8168Be identically
1711 * but they can be identified more specifically through the test below
1712 * if needed:
1713 *
1714 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1715 *
1716 * Same thing for the 8101Eb and the 8101Ec:
1717 *
1718 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1719 */
3744100e 1720 static const struct rtl_mac_info {
1da177e4 1721 u32 mask;
e3cf0cc0 1722 u32 val;
1da177e4
LT		 1723 int mac_version;
1724 } mac_info[] = {
01dc7fec 1725 /* 8168E family. */
70090424 1726 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1727 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1728 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1729 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1730
5b538df9 1731 /* 8168D family. */
daf9df6d 1732 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1733 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1734 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1735
e6de30d6 1736 /* 8168DP family. */
1737 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1738 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1739 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1740
ef808d50 1741 /* 8168C family. */
17c99297 1742 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1743 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1744 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1745 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1746 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1747 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1748 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1749 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1750 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1751
1752 /* 8168B family. */
1753 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1754 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1755 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1756 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1757
1758 /* 8101 family. */
36a0e6c2 1759 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1760 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1761 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1762 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1763 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1764 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1765 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1766 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1767 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1768 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1769 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1770 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1771 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1772 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1773 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1774 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1775 /* FIXME: where did these entries come from ? -- FR */
1776 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1777 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1778
1779 /* 8110 family. */
1780 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1781 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1782 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1783 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1784 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1785 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1786
f21b75e9
JD		 1787 /* Catch-all */
1788 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1789 };
1790 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1791 u32 reg;
1792
e3cf0cc0
FR		 1793 reg = RTL_R32(TxConfig);
1794 while ((reg & p->mask) != p->val)
1da177e4
LT		 1795 p++;
1796 tp->mac_version = p->mac_version;
5d320a20
FR		 1797
1798 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1799 netif_notice(tp, probe, dev,
1800 "unknown MAC, using family default\n");
1801 tp->mac_version = default_version;
1802 }
1da177e4
LT		 1803}
1804
1805static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1806{
bcf0bf90 1807 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1808}
1809
867763c1
FR		 1810struct phy_reg {
1811 u16 reg;
1812 u16 val;
1813};
1814
4da19633 1815static void rtl_writephy_batch(struct rtl8169_private *tp,
1816 const struct phy_reg *regs, int len)
867763c1
FR		 1817{
1818 while (len-- > 0) {
4da19633 1819 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1820 regs++;
1821 }
1822}
1823
bca03d5f 1824#define PHY_READ 0x00000000
1825#define PHY_DATA_OR 0x10000000
1826#define PHY_DATA_AND 0x20000000
1827#define PHY_BJMPN 0x30000000
1828#define PHY_READ_EFUSE 0x40000000
1829#define PHY_READ_MAC_BYTE 0x50000000
1830#define PHY_WRITE_MAC_BYTE 0x60000000
1831#define PHY_CLEAR_READCOUNT 0x70000000
1832#define PHY_WRITE 0x80000000
1833#define PHY_READCOUNT_EQ_SKIP 0x90000000
1834#define PHY_COMP_EQ_SKIPN 0xa0000000
1835#define PHY_COMP_NEQ_SKIPN 0xb0000000
1836#define PHY_WRITE_PREVIOUS 0xc0000000
1837#define PHY_SKIPN 0xd0000000
1838#define PHY_DELAY_MS 0xe0000000
1839#define PHY_WRITE_ERI_WORD 0xf0000000
1840
960aee6c
HW		 1841struct fw_info {
1842 u32 magic;
1843 char version[RTL_VER_SIZE];
1844 __le32 fw_start;
1845 __le32 fw_len;
1846 u8 chksum;
1847} __packed;
1848
1c361efb
FR		 1849#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1850
1851static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1852{
b6ffd97f 1853 const struct firmware *fw = rtl_fw->fw;
960aee6c 1854 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1855 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1856 char *version = rtl_fw->version;
1857 bool rc = false;
1858
1859 if (fw->size < FW_OPCODE_SIZE)
1860 goto out;
960aee6c
HW		 1861
1862 if (!fw_info->magic) {
1863 size_t i, size, start;
1864 u8 checksum = 0;
1865
1866 if (fw->size < sizeof(*fw_info))
1867 goto out;
1868
1869 for (i = 0; i < fw->size; i++)
1870 checksum += fw->data[i];
1871 if (checksum != 0)
1872 goto out;
1873
1874 start = le32_to_cpu(fw_info->fw_start);
1875 if (start > fw->size)
1876 goto out;
1877
1878 size = le32_to_cpu(fw_info->fw_len);
1879 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1880 goto out;
1881
1882 memcpy(version, fw_info->version, RTL_VER_SIZE);
1883
1884 pa->code = (__le32 *)(fw->data + start);
1885 pa->size = size;
1886 } else {
1c361efb
FR		 1887 if (fw->size % FW_OPCODE_SIZE)
1888 goto out;
1889
1890 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1891
1892 pa->code = (__le32 *)fw->data;
1893 pa->size = fw->size / FW_OPCODE_SIZE;
1894 }
1895 version[RTL_VER_SIZE - 1] = 0;
1896
1897 rc = true;
1898out:
1899 return rc;
1900}
1901
fd112f2e
FR		 1902static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1903 struct rtl_fw_phy_action *pa)
1c361efb 1904{
fd112f2e 1905 bool rc = false;
1c361efb 1906 size_t index;
bca03d5f 1907
1c361efb
FR		 1908 for (index = 0; index < pa->size; index++) {
1909 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 1910 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1911
42b82dc1 1912 switch(action & 0xf0000000) {
1913 case PHY_READ:
1914 case PHY_DATA_OR:
1915 case PHY_DATA_AND:
1916 case PHY_READ_EFUSE:
1917 case PHY_CLEAR_READCOUNT:
1918 case PHY_WRITE:
1919 case PHY_WRITE_PREVIOUS:
1920 case PHY_DELAY_MS:
1921 break;
1922
1923 case PHY_BJMPN:
1924 if (regno > index) {
fd112f2e 1925 netif_err(tp, ifup, tp->dev,
cecb5fd7 1926 "Out of range of firmware\n");
fd112f2e 1927 goto out;
42b82dc1 1928 }
1929 break;
1930 case PHY_READCOUNT_EQ_SKIP:
1c361efb 1931 if (index + 2 >= pa->size) {
fd112f2e 1932 netif_err(tp, ifup, tp->dev,
cecb5fd7 1933 "Out of range of firmware\n");
fd112f2e 1934 goto out;
42b82dc1 1935 }
1936 break;
1937 case PHY_COMP_EQ_SKIPN:
1938 case PHY_COMP_NEQ_SKIPN:
1939 case PHY_SKIPN:
1c361efb 1940 if (index + 1 + regno >= pa->size) {
fd112f2e 1941 netif_err(tp, ifup, tp->dev,
cecb5fd7 1942 "Out of range of firmware\n");
fd112f2e 1943 goto out;
42b82dc1 1944 }
bca03d5f 1945 break;
1946
42b82dc1 1947 case PHY_READ_MAC_BYTE:
1948 case PHY_WRITE_MAC_BYTE:
1949 case PHY_WRITE_ERI_WORD:
1950 default:
fd112f2e 1951 netif_err(tp, ifup, tp->dev,
42b82dc1 1952 "Invalid action 0x%08x\n", action);
fd112f2e 1953 goto out;
bca03d5f 1954 }
1955 }
fd112f2e
FR		 1956 rc = true;
1957out:
1958 return rc;
1959}
bca03d5f 1960
fd112f2e
FR		 1961static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1962{
1963 struct net_device *dev = tp->dev;
1964 int rc = -EINVAL;
1965
1966 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1967 netif_err(tp, ifup, dev, "invalid firwmare\n");
1968 goto out;
1969 }
1970
1971 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1972 rc = 0;
1973out:
1974 return rc;
1975}
1976
1977static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1978{
1979 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1980 u32 predata, count;
1981 size_t index;
1982
1983 predata = count = 0;
42b82dc1 1984
1c361efb
FR		 1985 for (index = 0; index < pa->size; ) {
1986 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 1987 u32 data = action & 0x0000ffff;
42b82dc1 1988 u32 regno = (action & 0x0fff0000) >> 16;
1989
1990 if (!action)
1991 break;
bca03d5f 1992
1993 switch(action & 0xf0000000) {
42b82dc1 1994 case PHY_READ:
1995 predata = rtl_readphy(tp, regno);
1996 count++;
1997 index++;
1998 break;
1999 case PHY_DATA_OR:
2000 predata |= data;
2001 index++;
2002 break;
2003 case PHY_DATA_AND:
2004 predata &= data;
2005 index++;
2006 break;
2007 case PHY_BJMPN:
2008 index -= regno;
2009 break;
2010 case PHY_READ_EFUSE:
2011 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2012 index++;
2013 break;
2014 case PHY_CLEAR_READCOUNT:
2015 count = 0;
2016 index++;
2017 break;
bca03d5f 2018 case PHY_WRITE:
42b82dc1 2019 rtl_writephy(tp, regno, data);
2020 index++;
2021 break;
2022 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2023 index += (count == data) ? 2 : 1;
bca03d5f 2024 break;
42b82dc1 2025 case PHY_COMP_EQ_SKIPN:
2026 if (predata == data)
2027 index += regno;
2028 index++;
2029 break;
2030 case PHY_COMP_NEQ_SKIPN:
2031 if (predata != data)
2032 index += regno;
2033 index++;
2034 break;
2035 case PHY_WRITE_PREVIOUS:
2036 rtl_writephy(tp, regno, predata);
2037 index++;
2038 break;
2039 case PHY_SKIPN:
2040 index += regno + 1;
2041 break;
2042 case PHY_DELAY_MS:
2043 mdelay(data);
2044 index++;
2045 break;
2046
2047 case PHY_READ_MAC_BYTE:
2048 case PHY_WRITE_MAC_BYTE:
2049 case PHY_WRITE_ERI_WORD:
bca03d5f 2050 default:
2051 BUG();
2052 }
2053 }
2054}
2055
f1e02ed1 2056static void rtl_release_firmware(struct rtl8169_private *tp)
2057{
b6ffd97f
FR		 2058 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2059 release_firmware(tp->rtl_fw->fw);
2060 kfree(tp->rtl_fw);
2061 }
2062 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2063}
2064
953a12cc 2065static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2066{
b6ffd97f 2067 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2068
2069 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2070 if (!IS_ERR_OR_NULL(rtl_fw))
2071 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2072}
2073
2074static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2075{
2076 if (rtl_readphy(tp, reg) != val)
2077 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2078 else
2079 rtl_apply_firmware(tp);
f1e02ed1 2080}
2081
4da19633 2082static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2083{
350f7596 2084 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2085 { 0x1f, 0x0001 },
2086 { 0x06, 0x006e },
2087 { 0x08, 0x0708 },
2088 { 0x15, 0x4000 },
2089 { 0x18, 0x65c7 },
1da177e4 2090
0b9b571d 2091 { 0x1f, 0x0001 },
2092 { 0x03, 0x00a1 },
2093 { 0x02, 0x0008 },
2094 { 0x01, 0x0120 },
2095 { 0x00, 0x1000 },
2096 { 0x04, 0x0800 },
2097 { 0x04, 0x0000 },
1da177e4 2098
0b9b571d 2099 { 0x03, 0xff41 },
2100 { 0x02, 0xdf60 },
2101 { 0x01, 0x0140 },
2102 { 0x00, 0x0077 },
2103 { 0x04, 0x7800 },
2104 { 0x04, 0x7000 },
2105
2106 { 0x03, 0x802f },
2107 { 0x02, 0x4f02 },
2108 { 0x01, 0x0409 },
2109 { 0x00, 0xf0f9 },
2110 { 0x04, 0x9800 },
2111 { 0x04, 0x9000 },
2112
2113 { 0x03, 0xdf01 },
2114 { 0x02, 0xdf20 },
2115 { 0x01, 0xff95 },
2116 { 0x00, 0xba00 },
2117 { 0x04, 0xa800 },
2118 { 0x04, 0xa000 },
2119
2120 { 0x03, 0xff41 },
2121 { 0x02, 0xdf20 },
2122 { 0x01, 0x0140 },
2123 { 0x00, 0x00bb },
2124 { 0x04, 0xb800 },
2125 { 0x04, 0xb000 },
2126
2127 { 0x03, 0xdf41 },
2128 { 0x02, 0xdc60 },
2129 { 0x01, 0x6340 },
2130 { 0x00, 0x007d },
2131 { 0x04, 0xd800 },
2132 { 0x04, 0xd000 },
2133
2134 { 0x03, 0xdf01 },
2135 { 0x02, 0xdf20 },
2136 { 0x01, 0x100a },
2137 { 0x00, 0xa0ff },
2138 { 0x04, 0xf800 },
2139 { 0x04, 0xf000 },
2140
2141 { 0x1f, 0x0000 },
2142 { 0x0b, 0x0000 },
2143 { 0x00, 0x9200 }
2144 };
1da177e4 2145
4da19633 2146 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2147}
2148
4da19633 2149static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2150{
350f7596 2151 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2152 { 0x1f, 0x0002 },
2153 { 0x01, 0x90d0 },
2154 { 0x1f, 0x0000 }
2155 };
2156
4da19633 2157 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2158}
2159
4da19633 2160static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2161{
2162 struct pci_dev *pdev = tp->pci_dev;
2e955856 2163
ccbae55e
SS		 2164 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2165 (pdev->subsystem_device != 0xe000))
2e955856 2166 return;
2167
4da19633 2168 rtl_writephy(tp, 0x1f, 0x0001);
2169 rtl_writephy(tp, 0x10, 0xf01b);
2170 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2171}
2172
4da19633 2173static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2174{
350f7596 2175 static const struct phy_reg phy_reg_init[] = {
2e955856 2176 { 0x1f, 0x0001 },
2177 { 0x04, 0x0000 },
2178 { 0x03, 0x00a1 },
2179 { 0x02, 0x0008 },
2180 { 0x01, 0x0120 },
2181 { 0x00, 0x1000 },
2182 { 0x04, 0x0800 },
2183 { 0x04, 0x9000 },
2184 { 0x03, 0x802f },
2185 { 0x02, 0x4f02 },
2186 { 0x01, 0x0409 },
2187 { 0x00, 0xf099 },
2188 { 0x04, 0x9800 },
2189 { 0x04, 0xa000 },
2190 { 0x03, 0xdf01 },
2191 { 0x02, 0xdf20 },
2192 { 0x01, 0xff95 },
2193 { 0x00, 0xba00 },
2194 { 0x04, 0xa800 },
2195 { 0x04, 0xf000 },
2196 { 0x03, 0xdf01 },
2197 { 0x02, 0xdf20 },
2198 { 0x01, 0x101a },
2199 { 0x00, 0xa0ff },
2200 { 0x04, 0xf800 },
2201 { 0x04, 0x0000 },
2202 { 0x1f, 0x0000 },
2203
2204 { 0x1f, 0x0001 },
2205 { 0x10, 0xf41b },
2206 { 0x14, 0xfb54 },
2207 { 0x18, 0xf5c7 },
2208 { 0x1f, 0x0000 },
2209
2210 { 0x1f, 0x0001 },
2211 { 0x17, 0x0cc0 },
2212 { 0x1f, 0x0000 }
2213 };
2214
4da19633 2215 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2216
4da19633 2217 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2218}
2219
4da19633 2220static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2221{
350f7596 2222 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2223 { 0x1f, 0x0001 },
2224 { 0x04, 0x0000 },
2225 { 0x03, 0x00a1 },
2226 { 0x02, 0x0008 },
2227 { 0x01, 0x0120 },
2228 { 0x00, 0x1000 },
2229 { 0x04, 0x0800 },
2230 { 0x04, 0x9000 },
2231 { 0x03, 0x802f },
2232 { 0x02, 0x4f02 },
2233 { 0x01, 0x0409 },
2234 { 0x00, 0xf099 },
2235 { 0x04, 0x9800 },
2236 { 0x04, 0xa000 },
2237 { 0x03, 0xdf01 },
2238 { 0x02, 0xdf20 },
2239 { 0x01, 0xff95 },
2240 { 0x00, 0xba00 },
2241 { 0x04, 0xa800 },
2242 { 0x04, 0xf000 },
2243 { 0x03, 0xdf01 },
2244 { 0x02, 0xdf20 },
2245 { 0x01, 0x101a },
2246 { 0x00, 0xa0ff },
2247 { 0x04, 0xf800 },
2248 { 0x04, 0x0000 },
2249 { 0x1f, 0x0000 },
2250
2251 { 0x1f, 0x0001 },
2252 { 0x0b, 0x8480 },
2253 { 0x1f, 0x0000 },
2254
2255 { 0x1f, 0x0001 },
2256 { 0x18, 0x67c7 },
2257 { 0x04, 0x2000 },
2258 { 0x03, 0x002f },
2259 { 0x02, 0x4360 },
2260 { 0x01, 0x0109 },
2261 { 0x00, 0x3022 },
2262 { 0x04, 0x2800 },
2263 { 0x1f, 0x0000 },
2264
2265 { 0x1f, 0x0001 },
2266 { 0x17, 0x0cc0 },
2267 { 0x1f, 0x0000 }
2268 };
2269
4da19633 2270 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2271}
2272
4da19633 2273static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2274{
350f7596 2275 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2276 { 0x10, 0xf41b },
2277 { 0x1f, 0x0000 }
2278 };
2279
4da19633 2280 rtl_writephy(tp, 0x1f, 0x0001);
2281 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2282
4da19633 2283 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2284}
2285
4da19633 2286static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2287{
350f7596 2288 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2289 { 0x1f, 0x0001 },
2290 { 0x10, 0xf41b },
2291 { 0x1f, 0x0000 }
2292 };
2293
4da19633 2294 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2295}
2296
4da19633 2297static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2298{
350f7596 2299 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2300 { 0x1f, 0x0000 },
2301 { 0x1d, 0x0f00 },
2302 { 0x1f, 0x0002 },
2303 { 0x0c, 0x1ec8 },
2304 { 0x1f, 0x0000 }
2305 };
2306
4da19633 2307 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2308}
2309
4da19633 2310static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2311{
350f7596 2312 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2313 { 0x1f, 0x0001 },
2314 { 0x1d, 0x3d98 },
2315 { 0x1f, 0x0000 }
2316 };
2317
4da19633 2318 rtl_writephy(tp, 0x1f, 0x0000);
2319 rtl_patchphy(tp, 0x14, 1 << 5);
2320 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2321
4da19633 2322 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2323}
2324
4da19633 2325static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2326{
350f7596 2327 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2328 { 0x1f, 0x0001 },
2329 { 0x12, 0x2300 },
867763c1
FR		 2330 { 0x1f, 0x0002 },
2331 { 0x00, 0x88d4 },
2332 { 0x01, 0x82b1 },
2333 { 0x03, 0x7002 },
2334 { 0x08, 0x9e30 },
2335 { 0x09, 0x01f0 },
2336 { 0x0a, 0x5500 },
2337 { 0x0c, 0x00c8 },
2338 { 0x1f, 0x0003 },
2339 { 0x12, 0xc096 },
2340 { 0x16, 0x000a },
f50d4275
FR		 2341 { 0x1f, 0x0000 },
2342 { 0x1f, 0x0000 },
2343 { 0x09, 0x2000 },
2344 { 0x09, 0x0000 }
867763c1
FR		 2345 };
2346
4da19633 2347 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2348
4da19633 2349 rtl_patchphy(tp, 0x14, 1 << 5);
2350 rtl_patchphy(tp, 0x0d, 1 << 5);
2351 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2352}
2353
4da19633 2354static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2355{
350f7596 2356 static const struct phy_reg phy_reg_init[] = {
f50d4275 2357 { 0x1f, 0x0001 },
7da97ec9 2358 { 0x12, 0x2300 },
f50d4275
FR		 2359 { 0x03, 0x802f },
2360 { 0x02, 0x4f02 },
2361 { 0x01, 0x0409 },
2362 { 0x00, 0xf099 },
2363 { 0x04, 0x9800 },
2364 { 0x04, 0x9000 },
2365 { 0x1d, 0x3d98 },
7da97ec9
FR		 2366 { 0x1f, 0x0002 },
2367 { 0x0c, 0x7eb8 },
f50d4275
FR		 2368 { 0x06, 0x0761 },
2369 { 0x1f, 0x0003 },
2370 { 0x16, 0x0f0a },
7da97ec9
FR		 2371 { 0x1f, 0x0000 }
2372 };
2373
4da19633 2374 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2375
4da19633 2376 rtl_patchphy(tp, 0x16, 1 << 0);
2377 rtl_patchphy(tp, 0x14, 1 << 5);
2378 rtl_patchphy(tp, 0x0d, 1 << 5);
2379 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2380}
2381
4da19633 2382static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2383{
350f7596 2384 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2385 { 0x1f, 0x0001 },
2386 { 0x12, 0x2300 },
2387 { 0x1d, 0x3d98 },
2388 { 0x1f, 0x0002 },
2389 { 0x0c, 0x7eb8 },
2390 { 0x06, 0x5461 },
2391 { 0x1f, 0x0003 },
2392 { 0x16, 0x0f0a },
2393 { 0x1f, 0x0000 }
2394 };
2395
4da19633 2396 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2397
4da19633 2398 rtl_patchphy(tp, 0x16, 1 << 0);
2399 rtl_patchphy(tp, 0x14, 1 << 5);
2400 rtl_patchphy(tp, 0x0d, 1 << 5);
2401 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2402}
2403
4da19633 2404static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2405{
4da19633 2406 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2407}
2408
bca03d5f 2409static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2410{
350f7596 2411 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2412 /* Channel Estimation */
5b538df9 2413 { 0x1f, 0x0001 },
daf9df6d 2414 { 0x06, 0x4064 },
2415 { 0x07, 0x2863 },
2416 { 0x08, 0x059c },
2417 { 0x09, 0x26b4 },
2418 { 0x0a, 0x6a19 },
2419 { 0x0b, 0xdcc8 },
2420 { 0x10, 0xf06d },
2421 { 0x14, 0x7f68 },
2422 { 0x18, 0x7fd9 },
2423 { 0x1c, 0xf0ff },
2424 { 0x1d, 0x3d9c },
5b538df9 2425 { 0x1f, 0x0003 },
daf9df6d 2426 { 0x12, 0xf49f },
2427 { 0x13, 0x070b },
2428 { 0x1a, 0x05ad },
bca03d5f 2429 { 0x14, 0x94c0 },
2430
2431 /*
2432 * Tx Error Issue
cecb5fd7 2433 * Enhance line driver power
bca03d5f 2434 */
5b538df9 2435 { 0x1f, 0x0002 },
daf9df6d 2436 { 0x06, 0x5561 },
2437 { 0x1f, 0x0005 },
2438 { 0x05, 0x8332 },
bca03d5f 2439 { 0x06, 0x5561 },
2440
2441 /*
2442 * Can not link to 1Gbps with bad cable
2443 * Decrease SNR threshold form 21.07dB to 19.04dB
2444 */
2445 { 0x1f, 0x0001 },
2446 { 0x17, 0x0cc0 },
daf9df6d 2447
5b538df9 2448 { 0x1f, 0x0000 },
bca03d5f 2449 { 0x0d, 0xf880 }
daf9df6d 2450 };
bca03d5f 2451 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2452
4da19633 2453 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2454
bca03d5f 2455 /*
2456 * Rx Error Issue
2457 * Fine Tune Switching regulator parameter
2458 */
4da19633 2459 rtl_writephy(tp, 0x1f, 0x0002);
2460 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2461 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2462
daf9df6d 2463 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2464 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2465 { 0x1f, 0x0002 },
2466 { 0x05, 0x669a },
2467 { 0x1f, 0x0005 },
2468 { 0x05, 0x8330 },
2469 { 0x06, 0x669a },
2470 { 0x1f, 0x0002 }
2471 };
2472 int val;
2473
4da19633 2474 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2475
4da19633 2476 val = rtl_readphy(tp, 0x0d);
daf9df6d 2477
2478 if ((val & 0x00ff) != 0x006c) {
350f7596 2479 static const u32 set[] = {
daf9df6d 2480 0x0065, 0x0066, 0x0067, 0x0068,
2481 0x0069, 0x006a, 0x006b, 0x006c
2482 };
2483 int i;
2484
4da19633 2485 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2486
2487 val &= 0xff00;
2488 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2489 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2490 }
2491 } else {
350f7596 2492 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2493 { 0x1f, 0x0002 },
2494 { 0x05, 0x6662 },
2495 { 0x1f, 0x0005 },
2496 { 0x05, 0x8330 },
2497 { 0x06, 0x6662 }
2498 };
2499
4da19633 2500 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2501 }
2502
bca03d5f 2503 /* RSET couple improve */
4da19633 2504 rtl_writephy(tp, 0x1f, 0x0002);
2505 rtl_patchphy(tp, 0x0d, 0x0300);
2506 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2507
bca03d5f 2508 /* Fine tune PLL performance */
4da19633 2509 rtl_writephy(tp, 0x1f, 0x0002);
2510 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2511 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2512
4da19633 2513 rtl_writephy(tp, 0x1f, 0x0005);
2514 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2515
2516 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2517
4da19633 2518 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2519}
2520
bca03d5f 2521static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2522{
350f7596 2523 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2524 /* Channel Estimation */
daf9df6d 2525 { 0x1f, 0x0001 },
2526 { 0x06, 0x4064 },
2527 { 0x07, 0x2863 },
2528 { 0x08, 0x059c },
2529 { 0x09, 0x26b4 },
2530 { 0x0a, 0x6a19 },
2531 { 0x0b, 0xdcc8 },
2532 { 0x10, 0xf06d },
2533 { 0x14, 0x7f68 },
2534 { 0x18, 0x7fd9 },
2535 { 0x1c, 0xf0ff },
2536 { 0x1d, 0x3d9c },
2537 { 0x1f, 0x0003 },
2538 { 0x12, 0xf49f },
2539 { 0x13, 0x070b },
2540 { 0x1a, 0x05ad },
2541 { 0x14, 0x94c0 },
2542
bca03d5f 2543 /*
2544 * Tx Error Issue
cecb5fd7 2545 * Enhance line driver power
bca03d5f 2546 */
daf9df6d 2547 { 0x1f, 0x0002 },
2548 { 0x06, 0x5561 },
2549 { 0x1f, 0x0005 },
2550 { 0x05, 0x8332 },
bca03d5f 2551 { 0x06, 0x5561 },
2552
2553 /*
2554 * Can not link to 1Gbps with bad cable
2555 * Decrease SNR threshold form 21.07dB to 19.04dB
2556 */
2557 { 0x1f, 0x0001 },
2558 { 0x17, 0x0cc0 },
daf9df6d 2559
2560 { 0x1f, 0x0000 },
bca03d5f 2561 { 0x0d, 0xf880 }
5b538df9 2562 };
bca03d5f 2563 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2564
4da19633 2565 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2566
daf9df6d 2567 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2568 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2569 { 0x1f, 0x0002 },
2570 { 0x05, 0x669a },
5b538df9 2571 { 0x1f, 0x0005 },
daf9df6d 2572 { 0x05, 0x8330 },
2573 { 0x06, 0x669a },
2574
2575 { 0x1f, 0x0002 }
2576 };
2577 int val;
2578
4da19633 2579 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2580
4da19633 2581 val = rtl_readphy(tp, 0x0d);
daf9df6d 2582 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2583 static const u32 set[] = {
daf9df6d 2584 0x0065, 0x0066, 0x0067, 0x0068,
2585 0x0069, 0x006a, 0x006b, 0x006c
2586 };
2587 int i;
2588
4da19633 2589 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2590
2591 val &= 0xff00;
2592 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2593 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2594 }
2595 } else {
350f7596 2596 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2597 { 0x1f, 0x0002 },
2598 { 0x05, 0x2642 },
5b538df9 2599 { 0x1f, 0x0005 },
daf9df6d 2600 { 0x05, 0x8330 },
2601 { 0x06, 0x2642 }
5b538df9
FR		 2602 };
2603
4da19633 2604 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2605 }
2606
bca03d5f 2607 /* Fine tune PLL performance */
4da19633 2608 rtl_writephy(tp, 0x1f, 0x0002);
2609 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2610 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2611
bca03d5f 2612 /* Switching regulator Slew rate */
4da19633 2613 rtl_writephy(tp, 0x1f, 0x0002);
2614 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2615
4da19633 2616 rtl_writephy(tp, 0x1f, 0x0005);
2617 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2618
2619 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2620
4da19633 2621 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2622}
2623
4da19633 2624static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2625{
350f7596 2626 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2627 { 0x1f, 0x0002 },
2628 { 0x10, 0x0008 },
2629 { 0x0d, 0x006c },
2630
2631 { 0x1f, 0x0000 },
2632 { 0x0d, 0xf880 },
2633
2634 { 0x1f, 0x0001 },
2635 { 0x17, 0x0cc0 },
2636
2637 { 0x1f, 0x0001 },
2638 { 0x0b, 0xa4d8 },
2639 { 0x09, 0x281c },
2640 { 0x07, 0x2883 },
2641 { 0x0a, 0x6b35 },
2642 { 0x1d, 0x3da4 },
2643 { 0x1c, 0xeffd },
2644 { 0x14, 0x7f52 },
2645 { 0x18, 0x7fc6 },
2646 { 0x08, 0x0601 },
2647 { 0x06, 0x4063 },
2648 { 0x10, 0xf074 },
2649 { 0x1f, 0x0003 },
2650 { 0x13, 0x0789 },
2651 { 0x12, 0xf4bd },
2652 { 0x1a, 0x04fd },
2653 { 0x14, 0x84b0 },
2654 { 0x1f, 0x0000 },
2655 { 0x00, 0x9200 },
2656
2657 { 0x1f, 0x0005 },
2658 { 0x01, 0x0340 },
2659 { 0x1f, 0x0001 },
2660 { 0x04, 0x4000 },
2661 { 0x03, 0x1d21 },
2662 { 0x02, 0x0c32 },
2663 { 0x01, 0x0200 },
2664 { 0x00, 0x5554 },
2665 { 0x04, 0x4800 },
2666 { 0x04, 0x4000 },
2667 { 0x04, 0xf000 },
2668 { 0x03, 0xdf01 },
2669 { 0x02, 0xdf20 },
2670 { 0x01, 0x101a },
2671 { 0x00, 0xa0ff },
2672 { 0x04, 0xf800 },
2673 { 0x04, 0xf000 },
2674 { 0x1f, 0x0000 },
2675
2676 { 0x1f, 0x0007 },
2677 { 0x1e, 0x0023 },
2678 { 0x16, 0x0000 },
2679 { 0x1f, 0x0000 }
2680 };
2681
4da19633 2682 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2683}
2684
e6de30d6 2685static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2686{
2687 static const struct phy_reg phy_reg_init[] = {
2688 { 0x1f, 0x0001 },
2689 { 0x17, 0x0cc0 },
2690
2691 { 0x1f, 0x0007 },
2692 { 0x1e, 0x002d },
2693 { 0x18, 0x0040 },
2694 { 0x1f, 0x0000 }
2695 };
2696
2697 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2698 rtl_patchphy(tp, 0x0d, 1 << 5);
2699}
2700
70090424 2701static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2702{
2703 static const struct phy_reg phy_reg_init[] = {
2704 /* Enable Delay cap */
2705 { 0x1f, 0x0005 },
2706 { 0x05, 0x8b80 },
2707 { 0x06, 0xc896 },
2708 { 0x1f, 0x0000 },
2709
2710 /* Channel estimation fine tune */
2711 { 0x1f, 0x0001 },
2712 { 0x0b, 0x6c20 },
2713 { 0x07, 0x2872 },
2714 { 0x1c, 0xefff },
2715 { 0x1f, 0x0003 },
2716 { 0x14, 0x6420 },
2717 { 0x1f, 0x0000 },
2718
2719 /* Update PFM & 10M TX idle timer */
2720 { 0x1f, 0x0007 },
2721 { 0x1e, 0x002f },
2722 { 0x15, 0x1919 },
2723 { 0x1f, 0x0000 },
2724
2725 { 0x1f, 0x0007 },
2726 { 0x1e, 0x00ac },
2727 { 0x18, 0x0006 },
2728 { 0x1f, 0x0000 }
2729 };
2730
15ecd039
FR		 2731 rtl_apply_firmware(tp);
2732
01dc7fec 2733 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2734
2735 /* DCO enable for 10M IDLE Power */
2736 rtl_writephy(tp, 0x1f, 0x0007);
2737 rtl_writephy(tp, 0x1e, 0x0023);
2738 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2739 rtl_writephy(tp, 0x1f, 0x0000);
2740
2741 /* For impedance matching */
2742 rtl_writephy(tp, 0x1f, 0x0002);
2743 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2744 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2745
2746 /* PHY auto speed down */
2747 rtl_writephy(tp, 0x1f, 0x0007);
2748 rtl_writephy(tp, 0x1e, 0x002d);
2749 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2750 rtl_writephy(tp, 0x1f, 0x0000);
2751 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2752
2753 rtl_writephy(tp, 0x1f, 0x0005);
2754 rtl_writephy(tp, 0x05, 0x8b86);
2755 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2756 rtl_writephy(tp, 0x1f, 0x0000);
2757
2758 rtl_writephy(tp, 0x1f, 0x0005);
2759 rtl_writephy(tp, 0x05, 0x8b85);
2760 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2761 rtl_writephy(tp, 0x1f, 0x0007);
2762 rtl_writephy(tp, 0x1e, 0x0020);
2763 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2764 rtl_writephy(tp, 0x1f, 0x0006);
2765 rtl_writephy(tp, 0x00, 0x5a00);
2766 rtl_writephy(tp, 0x1f, 0x0000);
2767 rtl_writephy(tp, 0x0d, 0x0007);
2768 rtl_writephy(tp, 0x0e, 0x003c);
2769 rtl_writephy(tp, 0x0d, 0x4007);
2770 rtl_writephy(tp, 0x0e, 0x0000);
2771 rtl_writephy(tp, 0x0d, 0x0000);
2772}
2773
70090424
HW		 2774static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2775{
2776 static const struct phy_reg phy_reg_init[] = {
2777 /* Enable Delay cap */
2778 { 0x1f, 0x0004 },
2779 { 0x1f, 0x0007 },
2780 { 0x1e, 0x00ac },
2781 { 0x18, 0x0006 },
2782 { 0x1f, 0x0002 },
2783 { 0x1f, 0x0000 },
2784 { 0x1f, 0x0000 },
2785
2786 /* Channel estimation fine tune */
2787 { 0x1f, 0x0003 },
2788 { 0x09, 0xa20f },
2789 { 0x1f, 0x0000 },
2790 { 0x1f, 0x0000 },
2791
2792 /* Green Setting */
2793 { 0x1f, 0x0005 },
2794 { 0x05, 0x8b5b },
2795 { 0x06, 0x9222 },
2796 { 0x05, 0x8b6d },
2797 { 0x06, 0x8000 },
2798 { 0x05, 0x8b76 },
2799 { 0x06, 0x8000 },
2800 { 0x1f, 0x0000 }
2801 };
2802
2803 rtl_apply_firmware(tp);
2804
2805 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2806
2807 /* For 4-corner performance improve */
2808 rtl_writephy(tp, 0x1f, 0x0005);
2809 rtl_writephy(tp, 0x05, 0x8b80);
2810 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2811 rtl_writephy(tp, 0x1f, 0x0000);
2812
2813 /* PHY auto speed down */
2814 rtl_writephy(tp, 0x1f, 0x0004);
2815 rtl_writephy(tp, 0x1f, 0x0007);
2816 rtl_writephy(tp, 0x1e, 0x002d);
2817 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2818 rtl_writephy(tp, 0x1f, 0x0002);
2819 rtl_writephy(tp, 0x1f, 0x0000);
2820 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2821
2822 /* improve 10M EEE waveform */
2823 rtl_writephy(tp, 0x1f, 0x0005);
2824 rtl_writephy(tp, 0x05, 0x8b86);
2825 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2826 rtl_writephy(tp, 0x1f, 0x0000);
2827
2828 /* Improve 2-pair detection performance */
2829 rtl_writephy(tp, 0x1f, 0x0005);
2830 rtl_writephy(tp, 0x05, 0x8b85);
2831 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2832 rtl_writephy(tp, 0x1f, 0x0000);
2833
2834 /* EEE setting */
2835 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2836 ERIAR_EXGMAC);
2837 rtl_writephy(tp, 0x1f, 0x0005);
2838 rtl_writephy(tp, 0x05, 0x8b85);
2839 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2840 rtl_writephy(tp, 0x1f, 0x0004);
2841 rtl_writephy(tp, 0x1f, 0x0007);
2842 rtl_writephy(tp, 0x1e, 0x0020);
2843 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2844 rtl_writephy(tp, 0x1f, 0x0002);
2845 rtl_writephy(tp, 0x1f, 0x0000);
2846 rtl_writephy(tp, 0x0d, 0x0007);
2847 rtl_writephy(tp, 0x0e, 0x003c);
2848 rtl_writephy(tp, 0x0d, 0x4007);
2849 rtl_writephy(tp, 0x0e, 0x0000);
2850 rtl_writephy(tp, 0x0d, 0x0000);
2851
2852 /* Green feature */
2853 rtl_writephy(tp, 0x1f, 0x0003);
2854 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2855 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2856 rtl_writephy(tp, 0x1f, 0x0000);
2857}
2858
4da19633 2859static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2860{
350f7596 2861 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2862 { 0x1f, 0x0003 },
2863 { 0x08, 0x441d },
2864 { 0x01, 0x9100 },
2865 { 0x1f, 0x0000 }
2866 };
2867
4da19633 2868 rtl_writephy(tp, 0x1f, 0x0000);
2869 rtl_patchphy(tp, 0x11, 1 << 12);
2870 rtl_patchphy(tp, 0x19, 1 << 13);
2871 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2872
4da19633 2873 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2874}
2875
5a5e4443
HW		 2876static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2877{
2878 static const struct phy_reg phy_reg_init[] = {
2879 { 0x1f, 0x0005 },
2880 { 0x1a, 0x0000 },
2881 { 0x1f, 0x0000 },
2882
2883 { 0x1f, 0x0004 },
2884 { 0x1c, 0x0000 },
2885 { 0x1f, 0x0000 },
2886
2887 { 0x1f, 0x0001 },
2888 { 0x15, 0x7701 },
2889 { 0x1f, 0x0000 }
2890 };
2891
2892 /* Disable ALDPS before ram code */
2893 rtl_writephy(tp, 0x1f, 0x0000);
2894 rtl_writephy(tp, 0x18, 0x0310);
2895 msleep(100);
2896
953a12cc 2897 rtl_apply_firmware(tp);
5a5e4443
HW		 2898
2899 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2900}
2901
5615d9f1
FR		 2902static void rtl_hw_phy_config(struct net_device *dev)
2903{
2904 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2905
2906 rtl8169_print_mac_version(tp);
2907
2908 switch (tp->mac_version) {
2909 case RTL_GIGA_MAC_VER_01:
2910 break;
2911 case RTL_GIGA_MAC_VER_02:
2912 case RTL_GIGA_MAC_VER_03:
4da19633 2913 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2914 break;
2915 case RTL_GIGA_MAC_VER_04:
4da19633 2916 rtl8169sb_hw_phy_config(tp);
5615d9f1 2917 break;
2e955856 2918 case RTL_GIGA_MAC_VER_05:
4da19633 2919 rtl8169scd_hw_phy_config(tp);
2e955856 2920 break;
8c7006aa 2921 case RTL_GIGA_MAC_VER_06:
4da19633 2922 rtl8169sce_hw_phy_config(tp);
8c7006aa 2923 break;
2857ffb7
FR		 2924 case RTL_GIGA_MAC_VER_07:
2925 case RTL_GIGA_MAC_VER_08:
2926 case RTL_GIGA_MAC_VER_09:
4da19633 2927 rtl8102e_hw_phy_config(tp);
2857ffb7 2928 break;
236b8082 2929 case RTL_GIGA_MAC_VER_11:
4da19633 2930 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2931 break;
2932 case RTL_GIGA_MAC_VER_12:
4da19633 2933 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2934 break;
2935 case RTL_GIGA_MAC_VER_17:
4da19633 2936 rtl8168bef_hw_phy_config(tp);
236b8082 2937 break;
867763c1 2938 case RTL_GIGA_MAC_VER_18:
4da19633 2939 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2940 break;
2941 case RTL_GIGA_MAC_VER_19:
4da19633 2942 rtl8168c_1_hw_phy_config(tp);
867763c1 2943 break;
7da97ec9 2944 case RTL_GIGA_MAC_VER_20:
4da19633 2945 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2946 break;
197ff761 2947 case RTL_GIGA_MAC_VER_21:
4da19633 2948 rtl8168c_3_hw_phy_config(tp);
197ff761 2949 break;
6fb07058 2950 case RTL_GIGA_MAC_VER_22:
4da19633 2951 rtl8168c_4_hw_phy_config(tp);
6fb07058 2952 break;
ef3386f0 2953 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2954 case RTL_GIGA_MAC_VER_24:
4da19633 2955 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2956 break;
5b538df9 2957 case RTL_GIGA_MAC_VER_25:
bca03d5f 2958 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2959 break;
2960 case RTL_GIGA_MAC_VER_26:
bca03d5f 2961 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2962 break;
2963 case RTL_GIGA_MAC_VER_27:
4da19633 2964 rtl8168d_3_hw_phy_config(tp);
5b538df9 2965 break;
e6de30d6 2966 case RTL_GIGA_MAC_VER_28:
2967 rtl8168d_4_hw_phy_config(tp);
2968 break;
5a5e4443
HW		 2969 case RTL_GIGA_MAC_VER_29:
2970 case RTL_GIGA_MAC_VER_30:
2971 rtl8105e_hw_phy_config(tp);
2972 break;
cecb5fd7
FR		 2973 case RTL_GIGA_MAC_VER_31:
2974 /* None. */
2975 break;
01dc7fec 2976 case RTL_GIGA_MAC_VER_32:
01dc7fec 2977 case RTL_GIGA_MAC_VER_33:
70090424
HW		 2978 rtl8168e_1_hw_phy_config(tp);
2979 break;
2980 case RTL_GIGA_MAC_VER_34:
2981 rtl8168e_2_hw_phy_config(tp);
01dc7fec 2982 break;
ef3386f0 2983
5615d9f1
FR		 2984 default:
2985 break;
2986 }
2987}
2988
1da177e4
LT		 2989static void rtl8169_phy_timer(unsigned long __opaque)
2990{
2991 struct net_device *dev = (struct net_device *)__opaque;
2992 struct rtl8169_private *tp = netdev_priv(dev);
2993 struct timer_list *timer = &tp->timer;
2994 void __iomem *ioaddr = tp->mmio_addr;
2995 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2996
bcf0bf90 2997 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2998
1da177e4
LT		 2999 spin_lock_irq(&tp->lock);
3000
4da19633 3001 if (tp->phy_reset_pending(tp)) {
5b0384f4 3002 /*
1da177e4
LT		 3003 * A busy loop could burn quite a few cycles on nowadays CPU.
3004 * Let's delay the execution of the timer for a few ticks.
3005 */
3006 timeout = HZ/10;
3007 goto out_mod_timer;
3008 }
3009
3010 if (tp->link_ok(ioaddr))
3011 goto out_unlock;
3012
bf82c189 3013 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3014
4da19633 3015 tp->phy_reset_enable(tp);
1da177e4
LT		 3016
3017out_mod_timer:
3018 mod_timer(timer, jiffies + timeout);
3019out_unlock:
3020 spin_unlock_irq(&tp->lock);
3021}
3022
1da177e4
LT		 3023#ifdef CONFIG_NET_POLL_CONTROLLER
3024/*
3025 * Polling 'interrupt' - used by things like netconsole to send skbs
3026 * without having to re-enable interrupts. It's not called while
3027 * the interrupt routine is executing.
3028 */
3029static void rtl8169_netpoll(struct net_device *dev)
3030{
3031 struct rtl8169_private *tp = netdev_priv(dev);
3032 struct pci_dev *pdev = tp->pci_dev;
3033
3034 disable_irq(pdev->irq);
7d12e780 3035 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3036 enable_irq(pdev->irq);
3037}
3038#endif
3039
3040static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3041 void __iomem *ioaddr)
3042{
3043 iounmap(ioaddr);
3044 pci_release_regions(pdev);
87aeec76 3045 pci_clear_mwi(pdev);
1da177e4
LT		 3046 pci_disable_device(pdev);
3047 free_netdev(dev);
3048}
3049
bf793295
FR		 3050static void rtl8169_phy_reset(struct net_device *dev,
3051 struct rtl8169_private *tp)
3052{
07d3f51f 3053 unsigned int i;
bf793295 3054
4da19633 3055 tp->phy_reset_enable(tp);
bf793295 3056 for (i = 0; i < 100; i++) {
4da19633 3057 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3058 return;
3059 msleep(1);
3060 }
bf82c189 3061 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3062}
3063
4ff96fa6
FR		 3064static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3065{
3066 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3067
5615d9f1 3068 rtl_hw_phy_config(dev);
4ff96fa6 3069
77332894
MS		 3070 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3071 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3072 RTL_W8(0x82, 0x01);
3073 }
4ff96fa6 3074
6dccd16b
FR		 3075 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3076
3077 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3078 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3079
bcf0bf90 3080 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3081 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3082 RTL_W8(0x82, 0x01);
3083 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3084 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3085 }
3086
bf793295
FR		 3087 rtl8169_phy_reset(dev, tp);
3088
54405cde 3089 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3090 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3091 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3092 (tp->mii.supports_gmii ?
3093 ADVERTISED_1000baseT_Half |
3094 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3095
bf82c189
JP		 3096 if (RTL_R8(PHYstatus) & TBI_Enable)
3097 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3098}
3099
773d2021
FR		 3100static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3101{
3102 void __iomem *ioaddr = tp->mmio_addr;
3103 u32 high;
3104 u32 low;
3105
3106 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3107 high = addr[4] | (addr[5] << 8);
3108
3109 spin_lock_irq(&tp->lock);
3110
3111 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3112
773d2021 3113 RTL_W32(MAC4, high);
908ba2bf 3114 RTL_R32(MAC4);
3115
78f1cd02 3116 RTL_W32(MAC0, low);
908ba2bf 3117 RTL_R32(MAC0);
3118
773d2021
FR		 3119 RTL_W8(Cfg9346, Cfg9346_Lock);
3120
3121 spin_unlock_irq(&tp->lock);
3122}
3123
3124static int rtl_set_mac_address(struct net_device *dev, void *p)
3125{
3126 struct rtl8169_private *tp = netdev_priv(dev);
3127 struct sockaddr *addr = p;
3128
3129 if (!is_valid_ether_addr(addr->sa_data))
3130 return -EADDRNOTAVAIL;
3131
3132 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3133
3134 rtl_rar_set(tp, dev->dev_addr);
3135
3136 return 0;
3137}
3138
5f787a1a
FR		 3139static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3140{
3141 struct rtl8169_private *tp = netdev_priv(dev);
3142 struct mii_ioctl_data *data = if_mii(ifr);
3143
8b4ab28d
FR		 3144 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3145}
5f787a1a 3146
cecb5fd7
FR		 3147static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3148 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3149{
5f787a1a
FR		 3150 switch (cmd) {
3151 case SIOCGMIIPHY:
3152 data->phy_id = 32; /* Internal PHY */
3153 return 0;
3154
3155 case SIOCGMIIREG:
4da19633 3156 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3157 return 0;
3158
3159 case SIOCSMIIREG:
4da19633 3160 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3161 return 0;
3162 }
3163 return -EOPNOTSUPP;
3164}
3165
8b4ab28d
FR		 3166static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3167{
3168 return -EOPNOTSUPP;
3169}
3170
0e485150
FR		 3171static const struct rtl_cfg_info {
3172 void (*hw_start)(struct net_device *);
3173 unsigned int region;
3174 unsigned int align;
3175 u16 intr_event;
3176 u16 napi_event;
ccdffb9a 3177 unsigned features;
f21b75e9 3178 u8 default_ver;
0e485150
FR		 3179} rtl_cfg_infos [] = {
3180 [RTL_CFG_0] = {
3181 .hw_start = rtl_hw_start_8169,
3182 .region = 1,
e9f63f30 3183 .align = 0,
0e485150
FR		 3184 .intr_event = SYSErr | LinkChg | RxOverflow |
3185 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3186 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3187 .features = RTL_FEATURE_GMII,
3188 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3189 },
3190 [RTL_CFG_1] = {
3191 .hw_start = rtl_hw_start_8168,
3192 .region = 2,
3193 .align = 8,
53f57357 3194 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3195 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3196 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3197 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3198 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3199 },
3200 [RTL_CFG_2] = {
3201 .hw_start = rtl_hw_start_8101,
3202 .region = 2,
3203 .align = 8,
3204 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3205 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3206 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3207 .features = RTL_FEATURE_MSI,
3208 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3209 }
3210};
3211
fbac58fc
FR		 3212/* Cfg9346_Unlock assumed. */
3213static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3214 const struct rtl_cfg_info *cfg)
3215{
3216 unsigned msi = 0;
3217 u8 cfg2;
3218
3219 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3220 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 3221 if (pci_enable_msi(pdev)) {
3222 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3223 } else {
3224 cfg2 |= MSIEnable;
3225 msi = RTL_FEATURE_MSI;
3226 }
3227 }
3228 RTL_W8(Config2, cfg2);
3229 return msi;
3230}
3231
3232static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3233{
3234 if (tp->features & RTL_FEATURE_MSI) {
3235 pci_disable_msi(pdev);
3236 tp->features &= ~RTL_FEATURE_MSI;
3237 }
3238}
3239
8b4ab28d
FR		 3240static const struct net_device_ops rtl8169_netdev_ops = {
3241 .ndo_open = rtl8169_open,
3242 .ndo_stop = rtl8169_close,
3243 .ndo_get_stats = rtl8169_get_stats,
00829823 3244 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3245 .ndo_tx_timeout = rtl8169_tx_timeout,
3246 .ndo_validate_addr = eth_validate_addr,
3247 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3248 .ndo_fix_features = rtl8169_fix_features,
3249 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3250 .ndo_set_mac_address = rtl_set_mac_address,
3251 .ndo_do_ioctl = rtl8169_ioctl,
3252 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 3253#ifdef CONFIG_NET_POLL_CONTROLLER
3254 .ndo_poll_controller = rtl8169_netpoll,
3255#endif
3256
3257};
3258
c0e45c1c 3259static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3260{
3261 struct mdio_ops *ops = &tp->mdio_ops;
3262
3263 switch (tp->mac_version) {
3264 case RTL_GIGA_MAC_VER_27:
3265 ops->write = r8168dp_1_mdio_write;
3266 ops->read = r8168dp_1_mdio_read;
3267 break;
e6de30d6 3268 case RTL_GIGA_MAC_VER_28:
4804b3b3 3269 case RTL_GIGA_MAC_VER_31:
e6de30d6 3270 ops->write = r8168dp_2_mdio_write;
3271 ops->read = r8168dp_2_mdio_read;
3272 break;
c0e45c1c 3273 default:
3274 ops->write = r8169_mdio_write;
3275 ops->read = r8169_mdio_read;
3276 break;
3277 }
3278}
3279
065c27c1 3280static void r810x_phy_power_down(struct rtl8169_private *tp)
3281{
3282 rtl_writephy(tp, 0x1f, 0x0000);
3283 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3284}
3285
3286static void r810x_phy_power_up(struct rtl8169_private *tp)
3287{
3288 rtl_writephy(tp, 0x1f, 0x0000);
3289 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3290}
3291
3292static void r810x_pll_power_down(struct rtl8169_private *tp)
3293{
3294 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3295 rtl_writephy(tp, 0x1f, 0x0000);
3296 rtl_writephy(tp, MII_BMCR, 0x0000);
3297 return;
3298 }
3299
3300 r810x_phy_power_down(tp);
3301}
3302
3303static void r810x_pll_power_up(struct rtl8169_private *tp)
3304{
3305 r810x_phy_power_up(tp);
3306}
3307
3308static void r8168_phy_power_up(struct rtl8169_private *tp)
3309{
3310 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3311 switch (tp->mac_version) {
3312 case RTL_GIGA_MAC_VER_11:
3313 case RTL_GIGA_MAC_VER_12:
3314 case RTL_GIGA_MAC_VER_17:
3315 case RTL_GIGA_MAC_VER_18:
3316 case RTL_GIGA_MAC_VER_19:
3317 case RTL_GIGA_MAC_VER_20:
3318 case RTL_GIGA_MAC_VER_21:
3319 case RTL_GIGA_MAC_VER_22:
3320 case RTL_GIGA_MAC_VER_23:
3321 case RTL_GIGA_MAC_VER_24:
3322 case RTL_GIGA_MAC_VER_25:
3323 case RTL_GIGA_MAC_VER_26:
3324 case RTL_GIGA_MAC_VER_27:
3325 case RTL_GIGA_MAC_VER_28:
3326 case RTL_GIGA_MAC_VER_31:
3327 rtl_writephy(tp, 0x0e, 0x0000);
3328 break;
3329 default:
3330 break;
3331 }
065c27c1 3332 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3333}
3334
3335static void r8168_phy_power_down(struct rtl8169_private *tp)
3336{
3337 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3338 switch (tp->mac_version) {
3339 case RTL_GIGA_MAC_VER_32:
3340 case RTL_GIGA_MAC_VER_33:
3341 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3342 break;
3343
3344 case RTL_GIGA_MAC_VER_11:
3345 case RTL_GIGA_MAC_VER_12:
3346 case RTL_GIGA_MAC_VER_17:
3347 case RTL_GIGA_MAC_VER_18:
3348 case RTL_GIGA_MAC_VER_19:
3349 case RTL_GIGA_MAC_VER_20:
3350 case RTL_GIGA_MAC_VER_21:
3351 case RTL_GIGA_MAC_VER_22:
3352 case RTL_GIGA_MAC_VER_23:
3353 case RTL_GIGA_MAC_VER_24:
3354 case RTL_GIGA_MAC_VER_25:
3355 case RTL_GIGA_MAC_VER_26:
3356 case RTL_GIGA_MAC_VER_27:
3357 case RTL_GIGA_MAC_VER_28:
3358 case RTL_GIGA_MAC_VER_31:
3359 rtl_writephy(tp, 0x0e, 0x0200);
3360 default:
3361 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3362 break;
3363 }
065c27c1 3364}
3365
3366static void r8168_pll_power_down(struct rtl8169_private *tp)
3367{
3368 void __iomem *ioaddr = tp->mmio_addr;
3369
cecb5fd7
FR		 3370 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3371 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3372 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3373 r8168dp_check_dash(tp)) {
065c27c1 3374 return;
5d2e1957 3375 }
065c27c1 3376
cecb5fd7
FR		 3377 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3378 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3379 (RTL_R16(CPlusCmd) & ASF)) {
3380 return;
3381 }
3382
01dc7fec 3383 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3384 tp->mac_version == RTL_GIGA_MAC_VER_33)
3385 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3386
065c27c1 3387 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3388 rtl_writephy(tp, 0x1f, 0x0000);
3389 rtl_writephy(tp, MII_BMCR, 0x0000);
3390
d4ed95d7
HW		 3391 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3392 tp->mac_version == RTL_GIGA_MAC_VER_33)
3393 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3394 AcceptMulticast | AcceptMyPhys);
065c27c1 3395 return;
3396 }
3397
3398 r8168_phy_power_down(tp);
3399
3400 switch (tp->mac_version) {
3401 case RTL_GIGA_MAC_VER_25:
3402 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3403 case RTL_GIGA_MAC_VER_27:
3404 case RTL_GIGA_MAC_VER_28:
4804b3b3 3405 case RTL_GIGA_MAC_VER_31:
01dc7fec 3406 case RTL_GIGA_MAC_VER_32:
3407 case RTL_GIGA_MAC_VER_33:
065c27c1 3408 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3409 break;
3410 }
3411}
3412
3413static void r8168_pll_power_up(struct rtl8169_private *tp)
3414{
3415 void __iomem *ioaddr = tp->mmio_addr;
3416
cecb5fd7
FR		 3417 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3418 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3419 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3420 r8168dp_check_dash(tp)) {
065c27c1 3421 return;
5d2e1957 3422 }
065c27c1 3423
3424 switch (tp->mac_version) {
3425 case RTL_GIGA_MAC_VER_25:
3426 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3427 case RTL_GIGA_MAC_VER_27:
3428 case RTL_GIGA_MAC_VER_28:
4804b3b3 3429 case RTL_GIGA_MAC_VER_31:
01dc7fec 3430 case RTL_GIGA_MAC_VER_32:
3431 case RTL_GIGA_MAC_VER_33:
065c27c1 3432 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3433 break;
3434 }
3435
3436 r8168_phy_power_up(tp);
3437}
3438
3439static void rtl_pll_power_op(struct rtl8169_private *tp,
3440 void (*op)(struct rtl8169_private *))
3441{
3442 if (op)
3443 op(tp);
3444}
3445
3446static void rtl_pll_power_down(struct rtl8169_private *tp)
3447{
3448 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3449}
3450
3451static void rtl_pll_power_up(struct rtl8169_private *tp)
3452{
3453 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3454}
3455
3456static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3457{
3458 struct pll_power_ops *ops = &tp->pll_power_ops;
3459
3460 switch (tp->mac_version) {
3461 case RTL_GIGA_MAC_VER_07:
3462 case RTL_GIGA_MAC_VER_08:
3463 case RTL_GIGA_MAC_VER_09:
3464 case RTL_GIGA_MAC_VER_10:
3465 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3466 case RTL_GIGA_MAC_VER_29:
3467 case RTL_GIGA_MAC_VER_30:
065c27c1 3468 ops->down = r810x_pll_power_down;
3469 ops->up = r810x_pll_power_up;
3470 break;
3471
3472 case RTL_GIGA_MAC_VER_11:
3473 case RTL_GIGA_MAC_VER_12:
3474 case RTL_GIGA_MAC_VER_17:
3475 case RTL_GIGA_MAC_VER_18:
3476 case RTL_GIGA_MAC_VER_19:
3477 case RTL_GIGA_MAC_VER_20:
3478 case RTL_GIGA_MAC_VER_21:
3479 case RTL_GIGA_MAC_VER_22:
3480 case RTL_GIGA_MAC_VER_23:
3481 case RTL_GIGA_MAC_VER_24:
3482 case RTL_GIGA_MAC_VER_25:
3483 case RTL_GIGA_MAC_VER_26:
3484 case RTL_GIGA_MAC_VER_27:
e6de30d6 3485 case RTL_GIGA_MAC_VER_28:
4804b3b3 3486 case RTL_GIGA_MAC_VER_31:
01dc7fec 3487 case RTL_GIGA_MAC_VER_32:
3488 case RTL_GIGA_MAC_VER_33:
70090424 3489 case RTL_GIGA_MAC_VER_34:
065c27c1 3490 ops->down = r8168_pll_power_down;
3491 ops->up = r8168_pll_power_up;
3492 break;
3493
3494 default:
3495 ops->down = NULL;
3496 ops->up = NULL;
3497 break;
3498 }
3499}
3500
e542a226
HW		 3501static void rtl_init_rxcfg(struct rtl8169_private *tp)
3502{
3503 void __iomem *ioaddr = tp->mmio_addr;
3504
3505 switch (tp->mac_version) {
3506 case RTL_GIGA_MAC_VER_01:
3507 case RTL_GIGA_MAC_VER_02:
3508 case RTL_GIGA_MAC_VER_03:
3509 case RTL_GIGA_MAC_VER_04:
3510 case RTL_GIGA_MAC_VER_05:
3511 case RTL_GIGA_MAC_VER_06:
3512 case RTL_GIGA_MAC_VER_10:
3513 case RTL_GIGA_MAC_VER_11:
3514 case RTL_GIGA_MAC_VER_12:
3515 case RTL_GIGA_MAC_VER_13:
3516 case RTL_GIGA_MAC_VER_14:
3517 case RTL_GIGA_MAC_VER_15:
3518 case RTL_GIGA_MAC_VER_16:
3519 case RTL_GIGA_MAC_VER_17:
3520 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3521 break;
3522 case RTL_GIGA_MAC_VER_18:
3523 case RTL_GIGA_MAC_VER_19:
3524 case RTL_GIGA_MAC_VER_20:
3525 case RTL_GIGA_MAC_VER_21:
3526 case RTL_GIGA_MAC_VER_22:
3527 case RTL_GIGA_MAC_VER_23:
3528 case RTL_GIGA_MAC_VER_24:
3529 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3530 break;
3531 default:
3532 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3533 break;
3534 }
3535}
3536
92fc43b4
HW		 3537static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3538{
3539 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3540}
3541
6f43adc8
FR		 3542static void rtl_hw_reset(struct rtl8169_private *tp)
3543{
3544 void __iomem *ioaddr = tp->mmio_addr;
3545 int i;
3546
3547 /* Soft reset the chip. */
3548 RTL_W8(ChipCmd, CmdReset);
3549
3550 /* Check that the chip has finished the reset. */
3551 for (i = 0; i < 100; i++) {
3552 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3553 break;
92fc43b4 3554 udelay(100);
6f43adc8 3555 }
92fc43b4
HW		 3556
3557 rtl8169_init_ring_indexes(tp);
6f43adc8
FR		 3558}
3559
1da177e4 3560static int __devinit
4ff96fa6 3561rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3562{
0e485150
FR		 3563 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3564 const unsigned int region = cfg->region;
1da177e4 3565 struct rtl8169_private *tp;
ccdffb9a 3566 struct mii_if_info *mii;
4ff96fa6
FR		 3567 struct net_device *dev;
3568 void __iomem *ioaddr;
2b7b4318 3569 int chipset, i;
07d3f51f 3570 int rc;
1da177e4 3571
4ff96fa6
FR		 3572 if (netif_msg_drv(&debug)) {
3573 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3574 MODULENAME, RTL8169_VERSION);
3575 }
1da177e4 3576
1da177e4 3577 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3578 if (!dev) {
b57b7e5a 3579 if (netif_msg_drv(&debug))
9b91cf9d 3580 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3581 rc = -ENOMEM;
3582 goto out;
1da177e4
LT		 3583 }
3584
1da177e4 3585 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3586 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3587 tp = netdev_priv(dev);
c4028958 3588 tp->dev = dev;
21e197f2 3589 tp->pci_dev = pdev;
b57b7e5a 3590 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3591
ccdffb9a
FR		 3592 mii = &tp->mii;
3593 mii->dev = dev;
3594 mii->mdio_read = rtl_mdio_read;
3595 mii->mdio_write = rtl_mdio_write;
3596 mii->phy_id_mask = 0x1f;
3597 mii->reg_num_mask = 0x1f;
3598 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3599
ba04c7c9
SG		 3600 /* disable ASPM completely as that cause random device stop working
3601 * problems as well as full system hangs for some PCIe devices users */
3602 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3603 PCIE_LINK_STATE_CLKPM);
3604
1da177e4
LT		 3605 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3606 rc = pci_enable_device(pdev);
b57b7e5a 3607 if (rc < 0) {
bf82c189 3608 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3609 goto err_out_free_dev_1;
1da177e4
LT		 3610 }
3611
87aeec76 3612 if (pci_set_mwi(pdev) < 0)
3613 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3614
1da177e4 3615 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3616 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3617 netif_err(tp, probe, dev,
3618 "region #%d not an MMIO resource, aborting\n",
3619 region);
1da177e4 3620 rc = -ENODEV;
87aeec76 3621 goto err_out_mwi_2;
1da177e4 3622 }
4ff96fa6 3623
1da177e4 3624 /* check for weird/broken PCI region reporting */
bcf0bf90 3625 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3626 netif_err(tp, probe, dev,
3627 "Invalid PCI region size(s), aborting\n");
1da177e4 3628 rc = -ENODEV;
87aeec76 3629 goto err_out_mwi_2;
1da177e4
LT		 3630 }
3631
3632 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3633 if (rc < 0) {
bf82c189 3634 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3635 goto err_out_mwi_2;
1da177e4
LT		 3636 }
3637
d24e9aaf 3638 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3639
3640 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3641 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3642 tp->cp_cmd |= PCIDAC;
3643 dev->features |= NETIF_F_HIGHDMA;
3644 } else {
284901a9 3645 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3646 if (rc < 0) {
bf82c189 3647 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3648 goto err_out_free_res_3;
1da177e4
LT		 3649 }
3650 }
3651
1da177e4 3652 /* ioremap MMIO region */
bcf0bf90 3653 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3654 if (!ioaddr) {
bf82c189 3655 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3656 rc = -EIO;
87aeec76 3657 goto err_out_free_res_3;
1da177e4 3658 }
6f43adc8 3659 tp->mmio_addr = ioaddr;
1da177e4 3660
e44daade
JM		 3661 if (!pci_is_pcie(pdev))
3662 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 3663
e542a226
HW		 3664 /* Identify chip attached to board */
3665 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3666
3667 rtl_init_rxcfg(tp);
3668
d78ad8cb 3669 RTL_W16(IntrMask, 0x0000);
1da177e4 3670
6f43adc8 3671 rtl_hw_reset(tp);
1da177e4 3672
d78ad8cb
KW		 3673 RTL_W16(IntrStatus, 0xffff);
3674
ca52efd5 3675 pci_set_master(pdev);
3676
7a8fc77b
FR		 3677 /*
3678 * Pretend we are using VLANs; This bypasses a nasty bug where
3679 * Interrupts stop flowing on high load on 8110SCd controllers.
3680 */
3681 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3682 tp->cp_cmd |= RxVlan;
3683
c0e45c1c 3684 rtl_init_mdio_ops(tp);
065c27c1 3685 rtl_init_pll_power_ops(tp);
c0e45c1c 3686
1da177e4 3687 rtl8169_print_mac_version(tp);
1da177e4 3688
85bffe6c
FR		 3689 chipset = tp->mac_version;
3690 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3691
5d06a99f
FR		 3692 RTL_W8(Cfg9346, Cfg9346_Unlock);
3693 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3694 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3695 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3696 tp->features |= RTL_FEATURE_WOL;
3697 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3698 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3699 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3700 RTL_W8(Cfg9346, Cfg9346_Lock);
3701
66ec5d4f
FR		 3702 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3703 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3704 tp->set_speed = rtl8169_set_speed_tbi;
3705 tp->get_settings = rtl8169_gset_tbi;
3706 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3707 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3708 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3709 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3710 } else {
3711 tp->set_speed = rtl8169_set_speed_xmii;
3712 tp->get_settings = rtl8169_gset_xmii;
3713 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3714 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3715 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3716 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3717 }
3718
df58ef51
FR		 3719 spin_lock_init(&tp->lock);
3720
7bf6bf48 3721 /* Get MAC address */
1da177e4
LT		 3722 for (i = 0; i < MAC_ADDR_LEN; i++)
3723 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3724 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3725
1da177e4 3726 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3727 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3728 dev->irq = pdev->irq;
3729 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3730
bea3348e 3731 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3732
350fb32a
MM		 3733 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3734 * properly for all devices */
3735 dev->features |= NETIF_F_RXCSUM |
3736 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3737
3738 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3739 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3740 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3741 NETIF_F_HIGHDMA;
3742
3743 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3744 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3745 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3746
3747 tp->intr_mask = 0xffff;
0e485150
FR		 3748 tp->hw_start = cfg->hw_start;
3749 tp->intr_event = cfg->intr_event;
3750 tp->napi_event = cfg->napi_event;
1da177e4 3751
2efa53f3
FR		 3752 init_timer(&tp->timer);
3753 tp->timer.data = (unsigned long) dev;
3754 tp->timer.function = rtl8169_phy_timer;
3755
b6ffd97f 3756 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3757
1da177e4 3758 rc = register_netdev(dev);
4ff96fa6 3759 if (rc < 0)
87aeec76 3760 goto err_out_msi_4;
1da177e4
LT		 3761
3762 pci_set_drvdata(pdev, dev);
3763
bf82c189 3764 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3765 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3766 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3767
cecb5fd7
FR		 3768 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3769 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3770 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3771 rtl8168_driver_start(tp);
e6de30d6 3772 }
b646d900 3773
8b76ab39 3774 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3775
f3ec4f87
AS		 3776 if (pci_dev_run_wake(pdev))
3777 pm_runtime_put_noidle(&pdev->dev);
e1759441 3778
0d672e9f
IV		 3779 netif_carrier_off(dev);
3780
4ff96fa6
FR		 3781out:
3782 return rc;
1da177e4 3783
87aeec76 3784err_out_msi_4:
fbac58fc 3785 rtl_disable_msi(pdev, tp);
4ff96fa6 3786 iounmap(ioaddr);
87aeec76 3787err_out_free_res_3:
4ff96fa6 3788 pci_release_regions(pdev);
87aeec76 3789err_out_mwi_2:
4ff96fa6 3790 pci_clear_mwi(pdev);
4ff96fa6
FR		 3791 pci_disable_device(pdev);
3792err_out_free_dev_1:
3793 free_netdev(dev);
3794 goto out;
1da177e4
LT		 3795}
3796
07d3f51f 3797static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3798{
3799 struct net_device *dev = pci_get_drvdata(pdev);
3800 struct rtl8169_private *tp = netdev_priv(dev);
3801
cecb5fd7
FR		 3802 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3803 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3804 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3805 rtl8168_driver_stop(tp);
e6de30d6 3806 }
b646d900 3807
23f333a2 3808 cancel_delayed_work_sync(&tp->task);
eb2a021c 3809
1da177e4 3810 unregister_netdev(dev);
cc098dc7 3811
953a12cc
FR		 3812 rtl_release_firmware(tp);
3813
f3ec4f87
AS		 3814 if (pci_dev_run_wake(pdev))
3815 pm_runtime_get_noresume(&pdev->dev);
e1759441 3816
cc098dc7
IV		 3817 /* restore original MAC address */
3818 rtl_rar_set(tp, dev->perm_addr);
3819
fbac58fc 3820 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3821 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3822 pci_set_drvdata(pdev, NULL);
3823}
3824
b6ffd97f 3825static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3826{
b6ffd97f
FR		 3827 struct rtl_fw *rtl_fw;
3828 const char *name;
3829 int rc = -ENOMEM;
953a12cc 3830
b6ffd97f
FR		 3831 name = rtl_lookup_firmware_name(tp);
3832 if (!name)
3833 goto out_no_firmware;
953a12cc 3834
b6ffd97f
FR		 3835 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3836 if (!rtl_fw)
3837 goto err_warn;
31bd204f 3838
b6ffd97f
FR		 3839 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3840 if (rc < 0)
3841 goto err_free;
3842
fd112f2e
FR		 3843 rc = rtl_check_firmware(tp, rtl_fw);
3844 if (rc < 0)
3845 goto err_release_firmware;
3846
b6ffd97f
FR		 3847 tp->rtl_fw = rtl_fw;
3848out:
3849 return;
3850
fd112f2e
FR		 3851err_release_firmware:
3852 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3853err_free:
3854 kfree(rtl_fw);
3855err_warn:
3856 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3857 name, rc);
3858out_no_firmware:
3859 tp->rtl_fw = NULL;
3860 goto out;
3861}
3862
3863static void rtl_request_firmware(struct rtl8169_private *tp)
3864{
3865 if (IS_ERR(tp->rtl_fw))
3866 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3867}
3868
1da177e4
LT		 3869static int rtl8169_open(struct net_device *dev)
3870{
3871 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3872 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3873 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3874 int retval = -ENOMEM;
1da177e4 3875
e1759441 3876 pm_runtime_get_sync(&pdev->dev);
1da177e4 3877
1da177e4
LT		 3878 /*
3879 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3880 * dma_alloc_coherent provides more.
1da177e4 3881 */
82553bb6
SG		 3882 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3883 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3884 if (!tp->TxDescArray)
e1759441 3885 goto err_pm_runtime_put;
1da177e4 3886
82553bb6
SG		 3887 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3888 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3889 if (!tp->RxDescArray)
99f252b0 3890 goto err_free_tx_0;
1da177e4
LT		 3891
3892 retval = rtl8169_init_ring(dev);
3893 if (retval < 0)
99f252b0 3894 goto err_free_rx_1;
1da177e4 3895
c4028958 3896 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3897
99f252b0
FR		 3898 smp_mb();
3899
953a12cc
FR		 3900 rtl_request_firmware(tp);
3901
fbac58fc
FR		 3902 retval = request_irq(dev->irq, rtl8169_interrupt,
3903 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3904 dev->name, dev);
3905 if (retval < 0)
953a12cc 3906 goto err_release_fw_2;
99f252b0 3907
bea3348e 3908 napi_enable(&tp->napi);
bea3348e 3909
eee3a96c 3910 rtl8169_init_phy(dev, tp);
3911
350fb32a 3912 rtl8169_set_features(dev, dev->features);
eee3a96c 3913
065c27c1 3914 rtl_pll_power_up(tp);
3915
07ce4064 3916 rtl_hw_start(dev);
1da177e4 3917
e1759441
RW		 3918 tp->saved_wolopts = 0;
3919 pm_runtime_put_noidle(&pdev->dev);
3920
eee3a96c 3921 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3922out:
3923 return retval;
3924
953a12cc
FR		 3925err_release_fw_2:
3926 rtl_release_firmware(tp);
99f252b0
FR		 3927 rtl8169_rx_clear(tp);
3928err_free_rx_1:
82553bb6
SG		 3929 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3930 tp->RxPhyAddr);
e1759441 3931 tp->RxDescArray = NULL;
99f252b0 3932err_free_tx_0:
82553bb6
SG		 3933 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3934 tp->TxPhyAddr);
e1759441
RW		 3935 tp->TxDescArray = NULL;
3936err_pm_runtime_put:
3937 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3938 goto out;
3939}
3940
92fc43b4
HW		 3941static void rtl_rx_close(struct rtl8169_private *tp)
3942{
3943 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 3944
1687b566 3945 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 3946}
3947
e6de30d6 3948static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3949{
e6de30d6 3950 void __iomem *ioaddr = tp->mmio_addr;
3951
1da177e4
LT		 3952 /* Disable interrupts */
3953 rtl8169_irq_mask_and_ack(ioaddr);
3954
92fc43b4
HW		 3955 rtl_rx_close(tp);
3956
5d2e1957 3957 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3958 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3959 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3960 while (RTL_R8(TxPoll) & NPQ)
3961 udelay(20);
70090424
HW		 3962 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3963 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3964 udelay(100);
92fc43b4
HW		 3965 } else {
3966 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3967 udelay(100);
e6de30d6 3968 }
3969
92fc43b4 3970 rtl_hw_reset(tp);
1da177e4
LT		 3971}
3972
7f796d83 3973static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3974{
3975 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 3976
3977 /* Set DMA burst size and Interframe Gap Time */
3978 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3979 (InterFrameGap << TxInterFrameGapShift));
3980}
3981
07ce4064 3982static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3983{
3984 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3985
07ce4064
FR		 3986 tp->hw_start(dev);
3987
07ce4064
FR		 3988 netif_start_queue(dev);
3989}
3990
7f796d83
FR		 3991static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3992 void __iomem *ioaddr)
3993{
3994 /*
3995 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3996 * register to be written before TxDescAddrLow to work.
3997 * Switching from MMIO to I/O access fixes the issue as well.
3998 */
3999 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4000 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4001 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4002 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4003}
4004
4005static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4006{
4007 u16 cmd;
4008
4009 cmd = RTL_R16(CPlusCmd);
4010 RTL_W16(CPlusCmd, cmd);
4011 return cmd;
4012}
4013
fdd7b4c3 4014static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4015{
4016 /* Low hurts. Let's disable the filtering. */
207d6e87 4017 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4018}
4019
6dccd16b
FR		 4020static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4021{
3744100e 4022 static const struct rtl_cfg2_info {
6dccd16b
FR		 4023 u32 mac_version;
4024 u32 clk;
4025 u32 val;
4026 } cfg2_info [] = {
4027 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4028 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4029 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4030 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4031 };
4032 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4033 unsigned int i;
4034 u32 clk;
4035
4036 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4037 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4038 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4039 RTL_W32(0x7c, p->val);
4040 break;
4041 }
4042 }
4043}
4044
07ce4064
FR		 4045static void rtl_hw_start_8169(struct net_device *dev)
4046{
4047 struct rtl8169_private *tp = netdev_priv(dev);
4048 void __iomem *ioaddr = tp->mmio_addr;
4049 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4050
9cb427b6
FR		 4051 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4052 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4053 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4054 }
4055
1da177e4 4056 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4057 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4058 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4059 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4060 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4061 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4062
e542a226
HW		 4063 rtl_init_rxcfg(tp);
4064
f0298f81 4065 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4066
6f0333b8 4067 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4068
cecb5fd7
FR		 4069 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4070 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4071 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4072 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4073 rtl_set_rx_tx_config_registers(tp);
1da177e4 4074
7f796d83 4075 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4076
cecb5fd7
FR		 4077 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4078 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4079 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4080 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4081 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4082 }
4083
bcf0bf90
FR		 4084 RTL_W16(CPlusCmd, tp->cp_cmd);
4085
6dccd16b
FR		 4086 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4087
1da177e4
LT		 4088 /*
4089 * Undocumented corner. Supposedly:
4090 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4091 */
4092 RTL_W16(IntrMitigate, 0x0000);
4093
7f796d83 4094 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4095
cecb5fd7
FR		 4096 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4097 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4098 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4099 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4100 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4101 rtl_set_rx_tx_config_registers(tp);
4102 }
4103
1da177e4 4104 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4105
4106 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4107 RTL_R8(IntrMask);
1da177e4
LT		 4108
4109 RTL_W32(RxMissed, 0);
4110
07ce4064 4111 rtl_set_rx_mode(dev);
1da177e4
LT		 4112
4113 /* no early-rx interrupts */
4114 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 4115
4116 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 4117 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4118}
1da177e4 4119
9c14ceaf 4120static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 4121{
e44daade 4122 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4123
4124 if (cap) {
4125 u16 ctl;
458a9f61 4126
9c14ceaf
FR		 4127 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4128 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4129 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4130 }
458a9f61
FR		 4131}
4132
650e8d5d 4133static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4134{
4135 u32 csi;
4136
4137 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4138 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4139}
4140
e6de30d6 4141static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4142{
4143 rtl_csi_access_enable(ioaddr, 0x17000000);
4144}
4145
650e8d5d 4146static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4147{
4148 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4149}
4150
4151struct ephy_info {
4152 unsigned int offset;
4153 u16 mask;
4154 u16 bits;
4155};
4156
350f7596 4157static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4158{
4159 u16 w;
4160
4161 while (len-- > 0) {
4162 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4163 rtl_ephy_write(ioaddr, e->offset, w);
4164 e++;
4165 }
4166}
4167
b726e493
FR		 4168static void rtl_disable_clock_request(struct pci_dev *pdev)
4169{
e44daade 4170 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4171
4172 if (cap) {
4173 u16 ctl;
4174
4175 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4176 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4177 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4178 }
4179}
4180
e6de30d6 4181static void rtl_enable_clock_request(struct pci_dev *pdev)
4182{
e44daade 4183 int cap = pci_pcie_cap(pdev);
e6de30d6 4184
4185 if (cap) {
4186 u16 ctl;
4187
4188 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4189 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4190 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4191 }
4192}
4193
b726e493
FR		 4194#define R8168_CPCMD_QUIRK_MASK (\
4195 EnableBist | \
4196 Mac_dbgo_oe | \
4197 Force_half_dup | \
4198 Force_rxflow_en | \
4199 Force_txflow_en | \
4200 Cxpl_dbg_sel | \
4201 ASF | \
4202 PktCntrDisable | \
4203 Mac_dbgo_sel)
4204
219a1e9d
FR		 4205static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4206{
b726e493
FR		 4207 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4208
4209 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4210
2e68ae44
FR		 4211 rtl_tx_performance_tweak(pdev,
4212 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4213}
4214
4215static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4216{
4217 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4218
f0298f81 4219 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4220
4221 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4222}
4223
4224static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4225{
b726e493
FR		 4226 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4227
4228 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4229
219a1e9d 4230 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4231
4232 rtl_disable_clock_request(pdev);
4233
4234 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4235}
4236
ef3386f0 4237static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4238{
350f7596 4239 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4240 { 0x01, 0, 0x0001 },
4241 { 0x02, 0x0800, 0x1000 },
4242 { 0x03, 0, 0x0042 },
4243 { 0x06, 0x0080, 0x0000 },
4244 { 0x07, 0, 0x2000 }
4245 };
4246
650e8d5d 4247 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4248
4249 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4250
219a1e9d
FR		 4251 __rtl_hw_start_8168cp(ioaddr, pdev);
4252}
4253
ef3386f0
FR		 4254static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4255{
650e8d5d 4256 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4257
4258 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4259
4260 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4261
4262 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4263}
4264
7f3e3d3a
FR		 4265static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4266{
650e8d5d 4267 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4268
4269 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4270
4271 /* Magic. */
4272 RTL_W8(DBG_REG, 0x20);
4273
f0298f81 4274 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4275
4276 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4277
4278 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4279}
4280
219a1e9d
FR		 4281static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4282{
350f7596 4283 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4284 { 0x02, 0x0800, 0x1000 },
4285 { 0x03, 0, 0x0002 },
4286 { 0x06, 0x0080, 0x0000 }
4287 };
4288
650e8d5d 4289 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4290
4291 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4292
4293 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4294
219a1e9d
FR		 4295 __rtl_hw_start_8168cp(ioaddr, pdev);
4296}
4297
4298static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4299{
350f7596 4300 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4301 { 0x01, 0, 0x0001 },
4302 { 0x03, 0x0400, 0x0220 }
4303 };
4304
650e8d5d 4305 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4306
4307 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4308
219a1e9d
FR		 4309 __rtl_hw_start_8168cp(ioaddr, pdev);
4310}
4311
197ff761
FR		 4312static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4313{
4314 rtl_hw_start_8168c_2(ioaddr, pdev);
4315}
4316
6fb07058
FR		 4317static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4318{
650e8d5d 4319 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4320
4321 __rtl_hw_start_8168cp(ioaddr, pdev);
4322}
4323
5b538df9
FR		 4324static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4325{
650e8d5d 4326 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4327
4328 rtl_disable_clock_request(pdev);
4329
f0298f81 4330 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4331
4332 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4333
4334 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4335}
4336
4804b3b3 4337static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4338{
4339 rtl_csi_access_enable_1(ioaddr);
4340
4341 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4342
4343 RTL_W8(MaxTxPacketSize, TxPacketMax);
4344
4345 rtl_disable_clock_request(pdev);
4346}
4347
e6de30d6 4348static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4349{
4350 static const struct ephy_info e_info_8168d_4[] = {
4351 { 0x0b, ~0, 0x48 },
4352 { 0x19, 0x20, 0x50 },
4353 { 0x0c, ~0, 0x20 }
4354 };
4355 int i;
4356
4357 rtl_csi_access_enable_1(ioaddr);
4358
4359 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4360
4361 RTL_W8(MaxTxPacketSize, TxPacketMax);
4362
4363 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4364 const struct ephy_info *e = e_info_8168d_4 + i;
4365 u16 w;
4366
4367 w = rtl_ephy_read(ioaddr, e->offset);
4368 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4369 }
4370
4371 rtl_enable_clock_request(pdev);
4372}
4373
70090424 4374static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4375{
70090424 4376 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4377 { 0x00, 0x0200, 0x0100 },
4378 { 0x00, 0x0000, 0x0004 },
4379 { 0x06, 0x0002, 0x0001 },
4380 { 0x06, 0x0000, 0x0030 },
4381 { 0x07, 0x0000, 0x2000 },
4382 { 0x00, 0x0000, 0x0020 },
4383 { 0x03, 0x5800, 0x2000 },
4384 { 0x03, 0x0000, 0x0001 },
4385 { 0x01, 0x0800, 0x1000 },
4386 { 0x07, 0x0000, 0x4000 },
4387 { 0x1e, 0x0000, 0x2000 },
4388 { 0x19, 0xffff, 0xfe6c },
4389 { 0x0a, 0x0000, 0x0040 }
4390 };
4391
4392 rtl_csi_access_enable_2(ioaddr);
4393
70090424 4394 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4395
4396 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4397
4398 RTL_W8(MaxTxPacketSize, TxPacketMax);
4399
4400 rtl_disable_clock_request(pdev);
4401
4402 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4403 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4404 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4405
cecb5fd7 4406 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4407}
4408
70090424
HW		 4409static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4410{
4411 static const struct ephy_info e_info_8168e_2[] = {
4412 { 0x09, 0x0000, 0x0080 },
4413 { 0x19, 0x0000, 0x0224 }
4414 };
4415
4416 rtl_csi_access_enable_1(ioaddr);
4417
4418 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4419
4420 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4421
4422 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4423 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4424 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4425 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4426 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4427 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4428 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4429 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4430 ERIAR_EXGMAC);
4431
4432 RTL_W8(MaxTxPacketSize, 0x27);
4433
4434 rtl_disable_clock_request(pdev);
4435
4436 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4437 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4438
4439 /* Adjust EEE LED frequency */
4440 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4441
4442 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4443 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4444 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4445}
4446
07ce4064
FR		 4447static void rtl_hw_start_8168(struct net_device *dev)
4448{
2dd99530
FR		 4449 struct rtl8169_private *tp = netdev_priv(dev);
4450 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4451 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4452
4453 RTL_W8(Cfg9346, Cfg9346_Unlock);
4454
f0298f81 4455 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4456
6f0333b8 4457 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4458
0e485150 4459 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4460
4461 RTL_W16(CPlusCmd, tp->cp_cmd);
4462
0e485150 4463 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4464
0e485150 4465 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4466 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4467 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4468 tp->intr_event |= RxFIFOOver | PCSTimeout;
4469 tp->intr_event &= ~RxOverflow;
4470 }
4471
4472 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4473
b8363901
FR		 4474 rtl_set_rx_mode(dev);
4475
4476 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4477 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4478
4479 RTL_R8(IntrMask);
4480
219a1e9d
FR		 4481 switch (tp->mac_version) {
4482 case RTL_GIGA_MAC_VER_11:
4483 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4484 break;
219a1e9d
FR		 4485
4486 case RTL_GIGA_MAC_VER_12:
4487 case RTL_GIGA_MAC_VER_17:
4488 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4489 break;
219a1e9d
FR		 4490
4491 case RTL_GIGA_MAC_VER_18:
ef3386f0 4492 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4493 break;
219a1e9d
FR		 4494
4495 case RTL_GIGA_MAC_VER_19:
4496 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4497 break;
219a1e9d
FR		 4498
4499 case RTL_GIGA_MAC_VER_20:
4500 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4501 break;
219a1e9d 4502
197ff761
FR		 4503 case RTL_GIGA_MAC_VER_21:
4504 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4505 break;
197ff761 4506
6fb07058
FR		 4507 case RTL_GIGA_MAC_VER_22:
4508 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4509 break;
6fb07058 4510
ef3386f0
FR		 4511 case RTL_GIGA_MAC_VER_23:
4512 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4513 break;
ef3386f0 4514
7f3e3d3a
FR		 4515 case RTL_GIGA_MAC_VER_24:
4516 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4517 break;
7f3e3d3a 4518
5b538df9 4519 case RTL_GIGA_MAC_VER_25:
daf9df6d 4520 case RTL_GIGA_MAC_VER_26:
4521 case RTL_GIGA_MAC_VER_27:
5b538df9 4522 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4523 break;
5b538df9 4524
e6de30d6 4525 case RTL_GIGA_MAC_VER_28:
4526 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4527 break;
cecb5fd7 4528
4804b3b3 4529 case RTL_GIGA_MAC_VER_31:
4530 rtl_hw_start_8168dp(ioaddr, pdev);
4531 break;
4532
01dc7fec 4533 case RTL_GIGA_MAC_VER_32:
4534 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4535 rtl_hw_start_8168e_1(ioaddr, pdev);
4536 break;
4537 case RTL_GIGA_MAC_VER_34:
4538 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4539 break;
e6de30d6 4540
219a1e9d
FR		 4541 default:
4542 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4543 dev->name, tp->mac_version);
4804b3b3 4544 break;
219a1e9d 4545 }
2dd99530 4546
0e485150
FR		 4547 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4548
b8363901
FR		 4549 RTL_W8(Cfg9346, Cfg9346_Lock);
4550
2dd99530 4551 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4552
0e485150 4553 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4554}
1da177e4 4555
2857ffb7
FR		 4556#define R810X_CPCMD_QUIRK_MASK (\
4557 EnableBist | \
4558 Mac_dbgo_oe | \
4559 Force_half_dup | \
5edcc537 4560 Force_rxflow_en | \
2857ffb7
FR		 4561 Force_txflow_en | \
4562 Cxpl_dbg_sel | \
4563 ASF | \
4564 PktCntrDisable | \
d24e9aaf 4565 Mac_dbgo_sel)
2857ffb7
FR		 4566
4567static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4568{
350f7596 4569 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4570 { 0x01, 0, 0x6e65 },
4571 { 0x02, 0, 0x091f },
4572 { 0x03, 0, 0xc2f9 },
4573 { 0x06, 0, 0xafb5 },
4574 { 0x07, 0, 0x0e00 },
4575 { 0x19, 0, 0xec80 },
4576 { 0x01, 0, 0x2e65 },
4577 { 0x01, 0, 0x6e65 }
4578 };
4579 u8 cfg1;
4580
650e8d5d 4581 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4582
4583 RTL_W8(DBG_REG, FIX_NAK_1);
4584
4585 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4586
4587 RTL_W8(Config1,
4588 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4589 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4590
4591 cfg1 = RTL_R8(Config1);
4592 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4593 RTL_W8(Config1, cfg1 & ~LEDS0);
4594
2857ffb7
FR		 4595 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4596}
4597
4598static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4599{
650e8d5d 4600 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4601
4602 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4603
4604 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4605 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4606}
4607
4608static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4609{
4610 rtl_hw_start_8102e_2(ioaddr, pdev);
4611
4612 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4613}
4614
5a5e4443
HW		 4615static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4616{
4617 static const struct ephy_info e_info_8105e_1[] = {
4618 { 0x07, 0, 0x4000 },
4619 { 0x19, 0, 0x0200 },
4620 { 0x19, 0, 0x0020 },
4621 { 0x1e, 0, 0x2000 },
4622 { 0x03, 0, 0x0001 },
4623 { 0x19, 0, 0x0100 },
4624 { 0x19, 0, 0x0004 },
4625 { 0x0a, 0, 0x0020 }
4626 };
4627
cecb5fd7 4628 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4629 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4630
cecb5fd7 4631 /* Disable Early Tally Counter */
5a5e4443
HW		 4632 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4633
4634 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4635 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4636
4637 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4638}
4639
4640static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4641{
4642 rtl_hw_start_8105e_1(ioaddr, pdev);
4643 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4644}
4645
07ce4064
FR		 4646static void rtl_hw_start_8101(struct net_device *dev)
4647{
cdf1a608
FR		 4648 struct rtl8169_private *tp = netdev_priv(dev);
4649 void __iomem *ioaddr = tp->mmio_addr;
4650 struct pci_dev *pdev = tp->pci_dev;
4651
cecb5fd7
FR		 4652 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4653 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4654 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4655
4656 if (cap) {
4657 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4658 PCI_EXP_DEVCTL_NOSNOOP_EN);
4659 }
cdf1a608
FR		 4660 }
4661
d24e9aaf
HW		 4662 RTL_W8(Cfg9346, Cfg9346_Unlock);
4663
2857ffb7
FR		 4664 switch (tp->mac_version) {
4665 case RTL_GIGA_MAC_VER_07:
4666 rtl_hw_start_8102e_1(ioaddr, pdev);
4667 break;
4668
4669 case RTL_GIGA_MAC_VER_08:
4670 rtl_hw_start_8102e_3(ioaddr, pdev);
4671 break;
4672
4673 case RTL_GIGA_MAC_VER_09:
4674 rtl_hw_start_8102e_2(ioaddr, pdev);
4675 break;
5a5e4443
HW		 4676
4677 case RTL_GIGA_MAC_VER_29:
4678 rtl_hw_start_8105e_1(ioaddr, pdev);
4679 break;
4680 case RTL_GIGA_MAC_VER_30:
4681 rtl_hw_start_8105e_2(ioaddr, pdev);
4682 break;
cdf1a608
FR		 4683 }
4684
d24e9aaf 4685 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4686
f0298f81 4687 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4688
6f0333b8 4689 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4690
d24e9aaf 4691 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4692 RTL_W16(CPlusCmd, tp->cp_cmd);
4693
4694 RTL_W16(IntrMitigate, 0x0000);
4695
4696 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4697
4698 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4699 rtl_set_rx_tx_config_registers(tp);
4700
cdf1a608
FR		 4701 RTL_R8(IntrMask);
4702
cdf1a608
FR		 4703 rtl_set_rx_mode(dev);
4704
4705 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4706
0e485150 4707 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4708}
4709
4710static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4711{
1da177e4
LT		 4712 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4713 return -EINVAL;
4714
4715 dev->mtu = new_mtu;
350fb32a
MM		 4716 netdev_update_features(dev);
4717
323bb685 4718 return 0;
1da177e4
LT		 4719}
4720
4721static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4722{
95e0918d 4723 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4724 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4725}
4726
6f0333b8
ED		 4727static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4728 void **data_buff, struct RxDesc *desc)
1da177e4 4729{
48addcc9 4730 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4731 DMA_FROM_DEVICE);
48addcc9 4732
6f0333b8
ED		 4733 kfree(*data_buff);
4734 *data_buff = NULL;
1da177e4
LT		 4735 rtl8169_make_unusable_by_asic(desc);
4736}
4737
4738static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4739{
4740 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4741
4742 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4743}
4744
4745static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4746 u32 rx_buf_sz)
4747{
4748 desc->addr = cpu_to_le64(mapping);
4749 wmb();
4750 rtl8169_mark_to_asic(desc, rx_buf_sz);
4751}
4752
6f0333b8
ED		 4753static inline void *rtl8169_align(void *data)
4754{
4755 return (void *)ALIGN((long)data, 16);
4756}
4757
0ecbe1ca
SG		 4758static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4759 struct RxDesc *desc)
1da177e4 4760{
6f0333b8 4761 void *data;
1da177e4 4762 dma_addr_t mapping;
48addcc9 4763 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4764 struct net_device *dev = tp->dev;
6f0333b8 4765 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4766
6f0333b8
ED		 4767 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4768 if (!data)
4769 return NULL;
e9f63f30 4770
6f0333b8
ED		 4771 if (rtl8169_align(data) != data) {
4772 kfree(data);
4773 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4774 if (!data)
4775 return NULL;
4776 }
3eafe507 4777
48addcc9 4778 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4779 DMA_FROM_DEVICE);
d827d86b
SG		 4780 if (unlikely(dma_mapping_error(d, mapping))) {
4781 if (net_ratelimit())
4782 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4783 goto err_out;
d827d86b 4784 }
1da177e4
LT		 4785
4786 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4787 return data;
3eafe507
SG		 4788
4789err_out:
4790 kfree(data);
4791 return NULL;
1da177e4
LT		 4792}
4793
4794static void rtl8169_rx_clear(struct rtl8169_private *tp)
4795{
07d3f51f 4796 unsigned int i;
1da177e4
LT		 4797
4798 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4799 if (tp->Rx_databuff[i]) {
4800 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4801 tp->RxDescArray + i);
4802 }
4803 }
4804}
4805
0ecbe1ca 4806static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4807{
0ecbe1ca
SG		 4808 desc->opts1 |= cpu_to_le32(RingEnd);
4809}
5b0384f4 4810
0ecbe1ca
SG		 4811static int rtl8169_rx_fill(struct rtl8169_private *tp)
4812{
4813 unsigned int i;
1da177e4 4814
0ecbe1ca
SG		 4815 for (i = 0; i < NUM_RX_DESC; i++) {
4816 void *data;
4ae47c2d 4817
6f0333b8 4818 if (tp->Rx_databuff[i])
1da177e4 4819 continue;
bcf0bf90 4820
0ecbe1ca 4821 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4822 if (!data) {
4823 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4824 goto err_out;
6f0333b8
ED		 4825 }
4826 tp->Rx_databuff[i] = data;
1da177e4 4827 }
1da177e4 4828
0ecbe1ca
SG		 4829 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4830 return 0;
4831
4832err_out:
4833 rtl8169_rx_clear(tp);
4834 return -ENOMEM;
1da177e4
LT		 4835}
4836
1da177e4
LT		 4837static int rtl8169_init_ring(struct net_device *dev)
4838{
4839 struct rtl8169_private *tp = netdev_priv(dev);
4840
4841 rtl8169_init_ring_indexes(tp);
4842
4843 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4844 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4845
0ecbe1ca 4846 return rtl8169_rx_fill(tp);
1da177e4
LT		 4847}
4848
48addcc9 4849static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4850 struct TxDesc *desc)
4851{
4852 unsigned int len = tx_skb->len;
4853
48addcc9
SG		 4854 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4855
1da177e4
LT		 4856 desc->opts1 = 0x00;
4857 desc->opts2 = 0x00;
4858 desc->addr = 0x00;
4859 tx_skb->len = 0;
4860}
4861
3eafe507
SG		 4862static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4863 unsigned int n)
1da177e4
LT		 4864{
4865 unsigned int i;
4866
3eafe507
SG		 4867 for (i = 0; i < n; i++) {
4868 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4869 struct ring_info *tx_skb = tp->tx_skb + entry;
4870 unsigned int len = tx_skb->len;
4871
4872 if (len) {
4873 struct sk_buff *skb = tx_skb->skb;
4874
48addcc9 4875 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4876 tp->TxDescArray + entry);
4877 if (skb) {
cac4b22f 4878 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4879 dev_kfree_skb(skb);
4880 tx_skb->skb = NULL;
4881 }
1da177e4
LT		 4882 }
4883 }
3eafe507
SG		 4884}
4885
4886static void rtl8169_tx_clear(struct rtl8169_private *tp)
4887{
4888 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4889 tp->cur_tx = tp->dirty_tx = 0;
4890}
4891
c4028958 4892static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4893{
4894 struct rtl8169_private *tp = netdev_priv(dev);
4895
c4028958 4896 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4897 schedule_delayed_work(&tp->task, 4);
4898}
4899
4900static void rtl8169_wait_for_quiescence(struct net_device *dev)
4901{
4902 struct rtl8169_private *tp = netdev_priv(dev);
4903 void __iomem *ioaddr = tp->mmio_addr;
4904
4905 synchronize_irq(dev->irq);
4906
4907 /* Wait for any pending NAPI task to complete */
bea3348e 4908 napi_disable(&tp->napi);
1da177e4
LT		 4909
4910 rtl8169_irq_mask_and_ack(ioaddr);
4911
d1d08d12
DM		 4912 tp->intr_mask = 0xffff;
4913 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4914 napi_enable(&tp->napi);
1da177e4
LT		 4915}
4916
c4028958 4917static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4918{
c4028958
DH		 4919 struct rtl8169_private *tp =
4920 container_of(work, struct rtl8169_private, task.work);
4921 struct net_device *dev = tp->dev;
1da177e4
LT		 4922 int ret;
4923
eb2a021c
FR		 4924 rtnl_lock();
4925
4926 if (!netif_running(dev))
4927 goto out_unlock;
4928
4929 rtl8169_wait_for_quiescence(dev);
4930 rtl8169_close(dev);
1da177e4
LT		 4931
4932 ret = rtl8169_open(dev);
4933 if (unlikely(ret < 0)) {
bf82c189
JP		 4934 if (net_ratelimit())
4935 netif_err(tp, drv, dev,
4936 "reinit failure (status = %d). Rescheduling\n",
4937 ret);
1da177e4
LT		 4938 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4939 }
eb2a021c
FR		 4940
4941out_unlock:
4942 rtnl_unlock();
1da177e4
LT		 4943}
4944
c4028958 4945static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4946{
c4028958
DH		 4947 struct rtl8169_private *tp =
4948 container_of(work, struct rtl8169_private, task.work);
4949 struct net_device *dev = tp->dev;
56de414c 4950 int i;
1da177e4 4951
eb2a021c
FR		 4952 rtnl_lock();
4953
1da177e4 4954 if (!netif_running(dev))
eb2a021c 4955 goto out_unlock;
1da177e4
LT		 4956
4957 rtl8169_wait_for_quiescence(dev);
4958
56de414c
FR		 4959 for (i = 0; i < NUM_RX_DESC; i++)
4960 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4961
1da177e4
LT		 4962 rtl8169_tx_clear(tp);
4963
92fc43b4 4964 rtl8169_hw_reset(tp);
56de414c
FR		 4965 rtl_hw_start(dev);
4966 netif_wake_queue(dev);
4967 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4968
4969out_unlock:
4970 rtnl_unlock();
1da177e4
LT		 4971}
4972
4973static void rtl8169_tx_timeout(struct net_device *dev)
4974{
4975 struct rtl8169_private *tp = netdev_priv(dev);
4976
e6de30d6 4977 rtl8169_hw_reset(tp);
1da177e4
LT		 4978
4979 /* Let's wait a bit while any (async) irq lands on */
4980 rtl8169_schedule_work(dev, rtl8169_reset_task);
4981}
4982
4983static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4984 u32 *opts)
1da177e4
LT		 4985{
4986 struct skb_shared_info *info = skb_shinfo(skb);
4987 unsigned int cur_frag, entry;
a6343afb 4988 struct TxDesc * uninitialized_var(txd);
48addcc9 4989 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4990
4991 entry = tp->cur_tx;
4992 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4993 skb_frag_t *frag = info->frags + cur_frag;
4994 dma_addr_t mapping;
4995 u32 status, len;
4996 void *addr;
4997
4998 entry = (entry + 1) % NUM_TX_DESC;
4999
5000 txd = tp->TxDescArray + entry;
5001 len = frag->size;
5002 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 5003 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5004 if (unlikely(dma_mapping_error(d, mapping))) {
5005 if (net_ratelimit())
5006 netif_err(tp, drv, tp->dev,
5007 "Failed to map TX fragments DMA!\n");
3eafe507 5008 goto err_out;
d827d86b 5009 }
1da177e4 5010
cecb5fd7 5011 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5012 status = opts[0] | len |
5013 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5014
5015 txd->opts1 = cpu_to_le32(status);
2b7b4318 5016 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5017 txd->addr = cpu_to_le64(mapping);
5018
5019 tp->tx_skb[entry].len = len;
5020 }
5021
5022 if (cur_frag) {
5023 tp->tx_skb[entry].skb = skb;
5024 txd->opts1 |= cpu_to_le32(LastFrag);
5025 }
5026
5027 return cur_frag;
3eafe507
SG		 5028
5029err_out:
5030 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5031 return -EIO;
1da177e4
LT		 5032}
5033
2b7b4318
FR		 5034static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5035 struct sk_buff *skb, u32 *opts)
1da177e4 5036{
2b7b4318 5037 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5038 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5039 int offset = info->opts_offset;
350fb32a 5040
2b7b4318
FR		 5041 if (mss) {
5042 opts[0] |= TD_LSO;
5043 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5044 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5045 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5046
5047 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5048 opts[offset] |= info->checksum.tcp;
1da177e4 5049 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5050 opts[offset] |= info->checksum.udp;
5051 else
5052 WARN_ON_ONCE(1);
1da177e4 5053 }
1da177e4
LT		 5054}
5055
61357325
SH		 5056static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5057 struct net_device *dev)
1da177e4
LT		 5058{
5059 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5060 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5061 struct TxDesc *txd = tp->TxDescArray + entry;
5062 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5063 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5064 dma_addr_t mapping;
5065 u32 status, len;
2b7b4318 5066 u32 opts[2];
3eafe507 5067 int frags;
5b0384f4 5068
1da177e4 5069 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5070 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5071 goto err_stop_0;
1da177e4
LT		 5072 }
5073
5074 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5075 goto err_stop_0;
5076
5077 len = skb_headlen(skb);
48addcc9 5078 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5079 if (unlikely(dma_mapping_error(d, mapping))) {
5080 if (net_ratelimit())
5081 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5082 goto err_dma_0;
d827d86b 5083 }
3eafe507
SG		 5084
5085 tp->tx_skb[entry].len = len;
5086 txd->addr = cpu_to_le64(mapping);
1da177e4 5087
2b7b4318
FR		 5088 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5089 opts[0] = DescOwn;
1da177e4 5090
2b7b4318
FR		 5091 rtl8169_tso_csum(tp, skb, opts);
5092
5093 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5094 if (frags < 0)
5095 goto err_dma_1;
5096 else if (frags)
2b7b4318 5097 opts[0] |= FirstFrag;
3eafe507 5098 else {
2b7b4318 5099 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5100 tp->tx_skb[entry].skb = skb;
5101 }
5102
2b7b4318
FR		 5103 txd->opts2 = cpu_to_le32(opts[1]);
5104
1da177e4
LT		 5105 wmb();
5106
cecb5fd7 5107 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5108 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5109 txd->opts1 = cpu_to_le32(status);
5110
1da177e4
LT		 5111 tp->cur_tx += frags + 1;
5112
4c020a96 5113 wmb();
1da177e4 5114
cecb5fd7 5115 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5116
5117 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5118 netif_stop_queue(dev);
5119 smp_rmb();
5120 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5121 netif_wake_queue(dev);
5122 }
5123
61357325 5124 return NETDEV_TX_OK;
1da177e4 5125
3eafe507 5126err_dma_1:
48addcc9 5127 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5128err_dma_0:
5129 dev_kfree_skb(skb);
5130 dev->stats.tx_dropped++;
5131 return NETDEV_TX_OK;
5132
5133err_stop_0:
1da177e4 5134 netif_stop_queue(dev);
cebf8cc7 5135 dev->stats.tx_dropped++;
61357325 5136 return NETDEV_TX_BUSY;
1da177e4
LT		 5137}
5138
5139static void rtl8169_pcierr_interrupt(struct net_device *dev)
5140{
5141 struct rtl8169_private *tp = netdev_priv(dev);
5142 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5143 u16 pci_status, pci_cmd;
5144
5145 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5146 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5147
bf82c189
JP		 5148 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5149 pci_cmd, pci_status);
1da177e4
LT		 5150
5151 /*
5152 * The recovery sequence below admits a very elaborated explanation:
5153 * - it seems to work;
d03902b8
FR		 5154 * - I did not see what else could be done;
5155 * - it makes iop3xx happy.
1da177e4
LT		 5156 *
5157 * Feel free to adjust to your needs.
5158 */
a27993f3 5159 if (pdev->broken_parity_status)
d03902b8
FR		 5160 pci_cmd &= ~PCI_COMMAND_PARITY;
5161 else
5162 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5163
5164 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5165
5166 pci_write_config_word(pdev, PCI_STATUS,
5167 pci_status & (PCI_STATUS_DETECTED_PARITY |
5168 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5169 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5170
5171 /* The infamous DAC f*ckup only happens at boot time */
5172 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5173 void __iomem *ioaddr = tp->mmio_addr;
5174
bf82c189 5175 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5176 tp->cp_cmd &= ~PCIDAC;
5177 RTL_W16(CPlusCmd, tp->cp_cmd);
5178 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5179 }
5180
e6de30d6 5181 rtl8169_hw_reset(tp);
d03902b8
FR		 5182
5183 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 5184}
5185
07d3f51f
FR		 5186static void rtl8169_tx_interrupt(struct net_device *dev,
5187 struct rtl8169_private *tp,
5188 void __iomem *ioaddr)
1da177e4
LT		 5189{
5190 unsigned int dirty_tx, tx_left;
5191
1da177e4
LT		 5192 dirty_tx = tp->dirty_tx;
5193 smp_rmb();
5194 tx_left = tp->cur_tx - dirty_tx;
5195
5196 while (tx_left > 0) {
5197 unsigned int entry = dirty_tx % NUM_TX_DESC;
5198 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5199 u32 status;
5200
5201 rmb();
5202 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5203 if (status & DescOwn)
5204 break;
5205
48addcc9
SG		 5206 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5207 tp->TxDescArray + entry);
1da177e4 5208 if (status & LastFrag) {
cac4b22f
SG		 5209 dev->stats.tx_packets++;
5210 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5211 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5212 tx_skb->skb = NULL;
5213 }
5214 dirty_tx++;
5215 tx_left--;
5216 }
5217
5218 if (tp->dirty_tx != dirty_tx) {
5219 tp->dirty_tx = dirty_tx;
5220 smp_wmb();
5221 if (netif_queue_stopped(dev) &&
5222 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5223 netif_wake_queue(dev);
5224 }
d78ae2dc
FR		 5225 /*
5226 * 8168 hack: TxPoll requests are lost when the Tx packets are
5227 * too close. Let's kick an extra TxPoll request when a burst
5228 * of start_xmit activity is detected (if it is not detected,
5229 * it is slow enough). -- FR
5230 */
5231 smp_rmb();
5232 if (tp->cur_tx != dirty_tx)
5233 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5234 }
5235}
5236
126fa4b9
FR		 5237static inline int rtl8169_fragmented_frame(u32 status)
5238{
5239 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5240}
5241
adea1ac7 5242static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5243{
1da177e4
LT		 5244 u32 status = opts1 & RxProtoMask;
5245
5246 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5247 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5248 skb->ip_summed = CHECKSUM_UNNECESSARY;
5249 else
bc8acf2c 5250 skb_checksum_none_assert(skb);
1da177e4
LT		 5251}
5252
6f0333b8
ED		 5253static struct sk_buff *rtl8169_try_rx_copy(void *data,
5254 struct rtl8169_private *tp,
5255 int pkt_size,
5256 dma_addr_t addr)
1da177e4 5257{
b449655f 5258 struct sk_buff *skb;
48addcc9 5259 struct device *d = &tp->pci_dev->dev;
b449655f 5260
6f0333b8 5261 data = rtl8169_align(data);
48addcc9 5262 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5263 prefetch(data);
5264 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5265 if (skb)
5266 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5267 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5268
6f0333b8 5269 return skb;
1da177e4
LT		 5270}
5271
07d3f51f
FR		 5272static int rtl8169_rx_interrupt(struct net_device *dev,
5273 struct rtl8169_private *tp,
bea3348e 5274 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5275{
5276 unsigned int cur_rx, rx_left;
6f0333b8 5277 unsigned int count;
1da177e4 5278
1da177e4
LT		 5279 cur_rx = tp->cur_rx;
5280 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5281 rx_left = min(rx_left, budget);
1da177e4 5282
4dcb7d33 5283 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5284 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5285 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5286 u32 status;
5287
5288 rmb();
126fa4b9 5289 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 5290
5291 if (status & DescOwn)
5292 break;
4dcb7d33 5293 if (unlikely(status & RxRES)) {
bf82c189
JP		 5294 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5295 status);
cebf8cc7 5296 dev->stats.rx_errors++;
1da177e4 5297 if (status & (RxRWT | RxRUNT))
cebf8cc7 5298 dev->stats.rx_length_errors++;
1da177e4 5299 if (status & RxCRC)
cebf8cc7 5300 dev->stats.rx_crc_errors++;
9dccf611
FR		 5301 if (status & RxFOVF) {
5302 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5303 dev->stats.rx_fifo_errors++;
9dccf611 5304 }
6f0333b8 5305 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5306 } else {
6f0333b8 5307 struct sk_buff *skb;
b449655f 5308 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 5309 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 5310
126fa4b9
FR		 5311 /*
5312 * The driver does not support incoming fragmented
5313 * frames. They are seen as a symptom of over-mtu
5314 * sized frames.
5315 */
5316 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5317 dev->stats.rx_dropped++;
5318 dev->stats.rx_length_errors++;
6f0333b8 5319 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5320 continue;
126fa4b9
FR		 5321 }
5322
6f0333b8
ED		 5323 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5324 tp, pkt_size, addr);
5325 rtl8169_mark_to_asic(desc, rx_buf_sz);
5326 if (!skb) {
5327 dev->stats.rx_dropped++;
5328 continue;
1da177e4
LT		 5329 }
5330
adea1ac7 5331 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5332 skb_put(skb, pkt_size);
5333 skb->protocol = eth_type_trans(skb, dev);
5334
7a8fc77b
FR		 5335 rtl8169_rx_vlan_tag(desc, skb);
5336
56de414c 5337 napi_gro_receive(&tp->napi, skb);
1da177e4 5338
cebf8cc7
FR		 5339 dev->stats.rx_bytes += pkt_size;
5340 dev->stats.rx_packets++;
1da177e4 5341 }
6dccd16b
FR		 5342
5343 /* Work around for AMD plateform. */
95e0918d 5344 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5345 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5346 desc->opts2 = 0;
5347 cur_rx++;
5348 }
1da177e4
LT		 5349 }
5350
5351 count = cur_rx - tp->cur_rx;
5352 tp->cur_rx = cur_rx;
5353
6f0333b8 5354 tp->dirty_rx += count;
1da177e4
LT		 5355
5356 return count;
5357}
5358
07d3f51f 5359static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5360{
07d3f51f 5361 struct net_device *dev = dev_instance;
1da177e4 5362 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5363 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5364 int handled = 0;
865c652d 5365 int status;
1da177e4 5366
f11a377b
DD		 5367 /* loop handling interrupts until we have no new ones or
5368 * we hit a invalid/hotplug case.
5369 */
865c652d 5370 status = RTL_R16(IntrStatus);
f11a377b
DD		 5371 while (status && status != 0xffff) {
5372 handled = 1;
1da177e4 5373
f11a377b
DD		 5374 /* Handle all of the error cases first. These will reset
5375 * the chip, so just exit the loop.
5376 */
5377 if (unlikely(!netif_running(dev))) {
92fc43b4 5378 rtl8169_hw_reset(tp);
f11a377b
DD		 5379 break;
5380 }
1da177e4 5381
1519e57f
FR		 5382 if (unlikely(status & RxFIFOOver)) {
5383 switch (tp->mac_version) {
5384 /* Work around for rx fifo overflow */
5385 case RTL_GIGA_MAC_VER_11:
5386 case RTL_GIGA_MAC_VER_22:
5387 case RTL_GIGA_MAC_VER_26:
5388 netif_stop_queue(dev);
5389 rtl8169_tx_timeout(dev);
5390 goto done;
f60ac8e7
FR		 5391 /* Testers needed. */
5392 case RTL_GIGA_MAC_VER_17:
5393 case RTL_GIGA_MAC_VER_19:
5394 case RTL_GIGA_MAC_VER_20:
5395 case RTL_GIGA_MAC_VER_21:
5396 case RTL_GIGA_MAC_VER_23:
5397 case RTL_GIGA_MAC_VER_24:
5398 case RTL_GIGA_MAC_VER_27:
5399 case RTL_GIGA_MAC_VER_28:
4804b3b3 5400 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5401 /* Experimental science. Pktgen proof. */
5402 case RTL_GIGA_MAC_VER_12:
5403 case RTL_GIGA_MAC_VER_25:
5404 if (status == RxFIFOOver)
5405 goto done;
5406 break;
5407 default:
5408 break;
5409 }
f11a377b 5410 }
1da177e4 5411
f11a377b
DD		 5412 if (unlikely(status & SYSErr)) {
5413 rtl8169_pcierr_interrupt(dev);
5414 break;
5415 }
1da177e4 5416
f11a377b 5417 if (status & LinkChg)
e4fbce74 5418 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5419
f11a377b
DD		 5420 /* We need to see the lastest version of tp->intr_mask to
5421 * avoid ignoring an MSI interrupt and having to wait for
5422 * another event which may never come.
5423 */
5424 smp_rmb();
5425 if (status & tp->intr_mask & tp->napi_event) {
5426 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5427 tp->intr_mask = ~tp->napi_event;
5428
5429 if (likely(napi_schedule_prep(&tp->napi)))
5430 __napi_schedule(&tp->napi);
bf82c189
JP		 5431 else
5432 netif_info(tp, intr, dev,
5433 "interrupt %04x in poll\n", status);
f11a377b 5434 }
1da177e4 5435
f11a377b
DD		 5436 /* We only get a new MSI interrupt when all active irq
5437 * sources on the chip have been acknowledged. So, ack
5438 * everything we've seen and check if new sources have become
5439 * active to avoid blocking all interrupts from the chip.
5440 */
5441 RTL_W16(IntrStatus,
5442 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5443 status = RTL_R16(IntrStatus);
865c652d 5444 }
1519e57f 5445done:
1da177e4
LT		 5446 return IRQ_RETVAL(handled);
5447}
5448
bea3348e 5449static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5450{
bea3348e
SH		 5451 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5452 struct net_device *dev = tp->dev;
1da177e4 5453 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5454 int work_done;
1da177e4 5455
bea3348e 5456 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5457 rtl8169_tx_interrupt(dev, tp, ioaddr);
5458
bea3348e 5459 if (work_done < budget) {
288379f0 5460 napi_complete(napi);
f11a377b
DD		 5461
5462 /* We need for force the visibility of tp->intr_mask
5463 * for other CPUs, as we can loose an MSI interrupt
5464 * and potentially wait for a retransmit timeout if we don't.
5465 * The posted write to IntrMask is safe, as it will
5466 * eventually make it to the chip and we won't loose anything
5467 * until it does.
1da177e4 5468 */
f11a377b 5469 tp->intr_mask = 0xffff;
4c020a96 5470 wmb();
0e485150 5471 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5472 }
5473
bea3348e 5474 return work_done;
1da177e4 5475}
1da177e4 5476
523a6094
FR		 5477static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5478{
5479 struct rtl8169_private *tp = netdev_priv(dev);
5480
5481 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5482 return;
5483
5484 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5485 RTL_W32(RxMissed, 0);
5486}
5487
1da177e4
LT		 5488static void rtl8169_down(struct net_device *dev)
5489{
5490 struct rtl8169_private *tp = netdev_priv(dev);
5491 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5492
4876cc1e 5493 del_timer_sync(&tp->timer);
1da177e4
LT		 5494
5495 netif_stop_queue(dev);
5496
93dd79e8 5497 napi_disable(&tp->napi);
93dd79e8 5498
1da177e4
LT		 5499 spin_lock_irq(&tp->lock);
5500
92fc43b4 5501 rtl8169_hw_reset(tp);
323bb685
SG		 5502 /*
5503 * At this point device interrupts can not be enabled in any function,
5504 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5505 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5506 */
523a6094 5507 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5508
5509 spin_unlock_irq(&tp->lock);
5510
5511 synchronize_irq(dev->irq);
5512
1da177e4 5513 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5514 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5515
1da177e4
LT		 5516 rtl8169_tx_clear(tp);
5517
5518 rtl8169_rx_clear(tp);
065c27c1 5519
5520 rtl_pll_power_down(tp);
1da177e4
LT		 5521}
5522
5523static int rtl8169_close(struct net_device *dev)
5524{
5525 struct rtl8169_private *tp = netdev_priv(dev);
5526 struct pci_dev *pdev = tp->pci_dev;
5527
e1759441
RW		 5528 pm_runtime_get_sync(&pdev->dev);
5529
cecb5fd7 5530 /* Update counters before going down */
355423d0
IV		 5531 rtl8169_update_counters(dev);
5532
1da177e4
LT		 5533 rtl8169_down(dev);
5534
5535 free_irq(dev->irq, dev);
5536
82553bb6
SG		 5537 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5538 tp->RxPhyAddr);
5539 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5540 tp->TxPhyAddr);
1da177e4
LT		 5541 tp->TxDescArray = NULL;
5542 tp->RxDescArray = NULL;
5543
e1759441
RW		 5544 pm_runtime_put_sync(&pdev->dev);
5545
1da177e4
LT		 5546 return 0;
5547}
5548
07ce4064 5549static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5550{
5551 struct rtl8169_private *tp = netdev_priv(dev);
5552 void __iomem *ioaddr = tp->mmio_addr;
5553 unsigned long flags;
5554 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5555 int rx_mode;
1da177e4
LT		 5556 u32 tmp = 0;
5557
5558 if (dev->flags & IFF_PROMISC) {
5559 /* Unconditionally log net taps. */
bf82c189 5560 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5561 rx_mode =
5562 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5563 AcceptAllPhys;
5564 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5565 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5566 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5567 /* Too many to filter perfectly -- accept all multicasts. */
5568 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5569 mc_filter[1] = mc_filter[0] = 0xffffffff;
5570 } else {
22bedad3 5571 struct netdev_hw_addr *ha;
07d3f51f 5572
1da177e4
LT		 5573 rx_mode = AcceptBroadcast | AcceptMyPhys;
5574 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5575 netdev_for_each_mc_addr(ha, dev) {
5576 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5577 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5578 rx_mode |= AcceptMulticast;
5579 }
5580 }
5581
5582 spin_lock_irqsave(&tp->lock, flags);
5583
1687b566 5584 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 5585
f887cce8 5586 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5587 u32 data = mc_filter[0];
5588
5589 mc_filter[0] = swab32(mc_filter[1]);
5590 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5591 }
5592
1da177e4 5593 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5594 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5595
57a9f236
FR		 5596 RTL_W32(RxConfig, tmp);
5597
1da177e4
LT		 5598 spin_unlock_irqrestore(&tp->lock, flags);
5599}
5600
5601/**
5602 * rtl8169_get_stats - Get rtl8169 read/write statistics
5603 * @dev: The Ethernet Device to get statistics for
5604 *
5605 * Get TX/RX statistics for rtl8169
5606 */
5607static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5608{
5609 struct rtl8169_private *tp = netdev_priv(dev);
5610 void __iomem *ioaddr = tp->mmio_addr;
5611 unsigned long flags;
5612
5613 if (netif_running(dev)) {
5614 spin_lock_irqsave(&tp->lock, flags);
523a6094 5615 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5616 spin_unlock_irqrestore(&tp->lock, flags);
5617 }
5b0384f4 5618
cebf8cc7 5619 return &dev->stats;
1da177e4
LT		 5620}
5621
861ab440 5622static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5623{
065c27c1 5624 struct rtl8169_private *tp = netdev_priv(dev);
5625
5d06a99f 5626 if (!netif_running(dev))
861ab440 5627 return;
5d06a99f 5628
065c27c1 5629 rtl_pll_power_down(tp);
5630
5d06a99f
FR		 5631 netif_device_detach(dev);
5632 netif_stop_queue(dev);
861ab440
RW		 5633}
5634
5635#ifdef CONFIG_PM
5636
5637static int rtl8169_suspend(struct device *device)
5638{
5639 struct pci_dev *pdev = to_pci_dev(device);
5640 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5641
861ab440 5642 rtl8169_net_suspend(dev);
1371fa6d 5643
5d06a99f
FR		 5644 return 0;
5645}
5646
e1759441
RW		 5647static void __rtl8169_resume(struct net_device *dev)
5648{
065c27c1 5649 struct rtl8169_private *tp = netdev_priv(dev);
5650
e1759441 5651 netif_device_attach(dev);
065c27c1 5652
5653 rtl_pll_power_up(tp);
5654
e1759441
RW		 5655 rtl8169_schedule_work(dev, rtl8169_reset_task);
5656}
5657
861ab440 5658static int rtl8169_resume(struct device *device)
5d06a99f 5659{
861ab440 5660 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5661 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5662 struct rtl8169_private *tp = netdev_priv(dev);
5663
5664 rtl8169_init_phy(dev, tp);
5d06a99f 5665
e1759441
RW		 5666 if (netif_running(dev))
5667 __rtl8169_resume(dev);
5d06a99f 5668
e1759441
RW		 5669 return 0;
5670}
5671
5672static int rtl8169_runtime_suspend(struct device *device)
5673{
5674 struct pci_dev *pdev = to_pci_dev(device);
5675 struct net_device *dev = pci_get_drvdata(pdev);
5676 struct rtl8169_private *tp = netdev_priv(dev);
5677
5678 if (!tp->TxDescArray)
5679 return 0;
5680
5681 spin_lock_irq(&tp->lock);
5682 tp->saved_wolopts = __rtl8169_get_wol(tp);
5683 __rtl8169_set_wol(tp, WAKE_ANY);
5684 spin_unlock_irq(&tp->lock);
5685
5686 rtl8169_net_suspend(dev);
5687
5688 return 0;
5689}
5690
5691static int rtl8169_runtime_resume(struct device *device)
5692{
5693 struct pci_dev *pdev = to_pci_dev(device);
5694 struct net_device *dev = pci_get_drvdata(pdev);
5695 struct rtl8169_private *tp = netdev_priv(dev);
5696
5697 if (!tp->TxDescArray)
5698 return 0;
5699
5700 spin_lock_irq(&tp->lock);
5701 __rtl8169_set_wol(tp, tp->saved_wolopts);
5702 tp->saved_wolopts = 0;
5703 spin_unlock_irq(&tp->lock);
5704
fccec10b
SG		 5705 rtl8169_init_phy(dev, tp);
5706
e1759441 5707 __rtl8169_resume(dev);
5d06a99f 5708
5d06a99f
FR		 5709 return 0;
5710}
5711
e1759441
RW		 5712static int rtl8169_runtime_idle(struct device *device)
5713{
5714 struct pci_dev *pdev = to_pci_dev(device);
5715 struct net_device *dev = pci_get_drvdata(pdev);
5716 struct rtl8169_private *tp = netdev_priv(dev);
5717
e4fbce74 5718 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5719}
5720
47145210 5721static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5722 .suspend = rtl8169_suspend,
5723 .resume = rtl8169_resume,
5724 .freeze = rtl8169_suspend,
5725 .thaw = rtl8169_resume,
5726 .poweroff = rtl8169_suspend,
5727 .restore = rtl8169_resume,
5728 .runtime_suspend = rtl8169_runtime_suspend,
5729 .runtime_resume = rtl8169_runtime_resume,
5730 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5731};
5732
5733#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5734
5735#else /* !CONFIG_PM */
5736
5737#define RTL8169_PM_OPS NULL
5738
5739#endif /* !CONFIG_PM */
5740
1765f95d
FR		 5741static void rtl_shutdown(struct pci_dev *pdev)
5742{
861ab440 5743 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5744 struct rtl8169_private *tp = netdev_priv(dev);
5745 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5746
5747 rtl8169_net_suspend(dev);
1765f95d 5748
cecb5fd7 5749 /* Restore original MAC address */
cc098dc7
IV		 5750 rtl_rar_set(tp, dev->perm_addr);
5751
4bb3f522 5752 spin_lock_irq(&tp->lock);
5753
92fc43b4 5754 rtl8169_hw_reset(tp);
4bb3f522 5755
5756 spin_unlock_irq(&tp->lock);
5757
861ab440 5758 if (system_state == SYSTEM_POWER_OFF) {
aaa89c08
HW		 5759 /* WoL fails with 8168b when the receiver is disabled. */
5760 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5761 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5762 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5763 (tp->features & RTL_FEATURE_WOL)) {
ca52efd5 5764 pci_clear_master(pdev);
5765
5766 RTL_W8(ChipCmd, CmdRxEnb);
5767 /* PCI commit */
5768 RTL_R8(ChipCmd);
5769 }
5770
861ab440
RW		 5771 pci_wake_from_d3(pdev, true);
5772 pci_set_power_state(pdev, PCI_D3hot);
5773 }
5774}
5d06a99f 5775
1da177e4
LT		 5776static struct pci_driver rtl8169_pci_driver = {
5777 .name = MODULENAME,
5778 .id_table = rtl8169_pci_tbl,
5779 .probe = rtl8169_init_one,
5780 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5781 .shutdown = rtl_shutdown,
861ab440 5782 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5783};
5784
07d3f51f 5785static int __init rtl8169_init_module(void)
1da177e4 5786{
29917620 5787 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5788}
5789
07d3f51f 5790static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5791{
5792 pci_unregister_driver(&rtl8169_pci_driver);
5793}
5794
5795module_init(rtl8169_init_module);
5796module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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