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r8169: verbose mac address init
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 113 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 114 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 115 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9
FR		 116 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
117 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
1da177e4
LT		 118};
119
1da177e4
LT		 120#define _R(NAME,MAC,MASK) \
121 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
122
3c6bee1d 123static const struct {
1da177e4
LT		 124 const char *name;
125 u8 mac_version;
126 u32 RxConfigMask; /* Clears the bits supported by this chip */
127} rtl_chip_info[] = {
ba6eb6ee
FR		 128 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
129 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
130 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
131 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
132 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 133 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 134 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
135 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
136 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
137 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
139 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
141 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 142 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
145 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 150 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9
FR		 151 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
152 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
1da177e4
LT		 153};
154#undef _R
155
bcf0bf90
FR		 156enum cfg_version {
157 RTL_CFG_0 = 0x00,
158 RTL_CFG_1,
159 RTL_CFG_2
160};
161
07ce4064
FR		 162static void rtl_hw_start_8169(struct net_device *);
163static void rtl_hw_start_8168(struct net_device *);
164static void rtl_hw_start_8101(struct net_device *);
165
1da177e4 166static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 170 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
172 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 173 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 174 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
175 { PCI_VENDOR_ID_LINKSYS, 0x1032,
176 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 177 { 0x0001, 0x8168,
178 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 179 {0,},
180};
181
182MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
183
184static int rx_copybreak = 200;
185static int use_dac;
b57b7e5a
SH		 186static struct {
187 u32 msg_enable;
188} debug = { -1 };
1da177e4 189
07d3f51f
FR		 190enum rtl_registers {
191 MAC0 = 0, /* Ethernet hardware address. */
773d2021 192 MAC4 = 4,
07d3f51f
FR		 193 MAR0 = 8, /* Multicast filter. */
194 CounterAddrLow = 0x10,
195 CounterAddrHigh = 0x14,
196 TxDescStartAddrLow = 0x20,
197 TxDescStartAddrHigh = 0x24,
198 TxHDescStartAddrLow = 0x28,
199 TxHDescStartAddrHigh = 0x2c,
200 FLASH = 0x30,
201 ERSR = 0x36,
202 ChipCmd = 0x37,
203 TxPoll = 0x38,
204 IntrMask = 0x3c,
205 IntrStatus = 0x3e,
206 TxConfig = 0x40,
207 RxConfig = 0x44,
208 RxMissed = 0x4c,
209 Cfg9346 = 0x50,
210 Config0 = 0x51,
211 Config1 = 0x52,
212 Config2 = 0x53,
213 Config3 = 0x54,
214 Config4 = 0x55,
215 Config5 = 0x56,
216 MultiIntr = 0x5c,
217 PHYAR = 0x60,
07d3f51f
FR		 218 PHYstatus = 0x6c,
219 RxMaxSize = 0xda,
220 CPlusCmd = 0xe0,
221 IntrMitigate = 0xe2,
222 RxDescAddrLow = 0xe4,
223 RxDescAddrHigh = 0xe8,
224 EarlyTxThres = 0xec,
225 FuncEvent = 0xf0,
226 FuncEventMask = 0xf4,
227 FuncPresetState = 0xf8,
228 FuncForceEvent = 0xfc,
1da177e4
LT		 229};
230
f162a5d1
FR		 231enum rtl8110_registers {
232 TBICSR = 0x64,
233 TBI_ANAR = 0x68,
234 TBI_LPAR = 0x6a,
235};
236
237enum rtl8168_8101_registers {
238 CSIDR = 0x64,
239 CSIAR = 0x68,
240#define CSIAR_FLAG 0x80000000
241#define CSIAR_WRITE_CMD 0x80000000
242#define CSIAR_BYTE_ENABLE 0x0f
243#define CSIAR_BYTE_ENABLE_SHIFT 12
244#define CSIAR_ADDR_MASK 0x0fff
245
246 EPHYAR = 0x80,
247#define EPHYAR_FLAG 0x80000000
248#define EPHYAR_WRITE_CMD 0x80000000
249#define EPHYAR_REG_MASK 0x1f
250#define EPHYAR_REG_SHIFT 16
251#define EPHYAR_DATA_MASK 0xffff
252 DBG_REG = 0xd1,
253#define FIX_NAK_1 (1 << 4)
254#define FIX_NAK_2 (1 << 3)
255};
256
07d3f51f 257enum rtl_register_content {
1da177e4 258 /* InterruptStatusBits */
07d3f51f
FR		 259 SYSErr = 0x8000,
260 PCSTimeout = 0x4000,
261 SWInt = 0x0100,
262 TxDescUnavail = 0x0080,
263 RxFIFOOver = 0x0040,
264 LinkChg = 0x0020,
265 RxOverflow = 0x0010,
266 TxErr = 0x0008,
267 TxOK = 0x0004,
268 RxErr = 0x0002,
269 RxOK = 0x0001,
1da177e4
LT		 270
271 /* RxStatusDesc */
9dccf611
FR		 272 RxFOVF = (1 << 23),
273 RxRWT = (1 << 22),
274 RxRES = (1 << 21),
275 RxRUNT = (1 << 20),
276 RxCRC = (1 << 19),
1da177e4
LT		 277
278 /* ChipCmdBits */
07d3f51f
FR		 279 CmdReset = 0x10,
280 CmdRxEnb = 0x08,
281 CmdTxEnb = 0x04,
282 RxBufEmpty = 0x01,
1da177e4 283
275391a4
FR		 284 /* TXPoll register p.5 */
285 HPQ = 0x80, /* Poll cmd on the high prio queue */
286 NPQ = 0x40, /* Poll cmd on the low prio queue */
287 FSWInt = 0x01, /* Forced software interrupt */
288
1da177e4 289 /* Cfg9346Bits */
07d3f51f
FR		 290 Cfg9346_Lock = 0x00,
291 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 292
293 /* rx_mode_bits */
07d3f51f
FR		 294 AcceptErr = 0x20,
295 AcceptRunt = 0x10,
296 AcceptBroadcast = 0x08,
297 AcceptMulticast = 0x04,
298 AcceptMyPhys = 0x02,
299 AcceptAllPhys = 0x01,
1da177e4
LT		 300
301 /* RxConfigBits */
07d3f51f
FR		 302 RxCfgFIFOShift = 13,
303 RxCfgDMAShift = 8,
1da177e4
LT		 304
305 /* TxConfigBits */
306 TxInterFrameGapShift = 24,
307 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
308
5d06a99f 309 /* Config1 register p.24 */
f162a5d1
FR		 310 LEDS1 = (1 << 7),
311 LEDS0 = (1 << 6),
fbac58fc 312 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 313 Speed_down = (1 << 4),
314 MEMMAP = (1 << 3),
315 IOMAP = (1 << 2),
316 VPD = (1 << 1),
5d06a99f
FR		 317 PMEnable = (1 << 0), /* Power Management Enable */
318
6dccd16b
FR		 319 /* Config2 register p. 25 */
320 PCI_Clock_66MHz = 0x01,
321 PCI_Clock_33MHz = 0x00,
322
61a4dcc2
FR		 323 /* Config3 register p.25 */
324 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
325 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 326 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 327
5d06a99f 328 /* Config5 register p.27 */
61a4dcc2
FR		 329 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
330 MWF = (1 << 5), /* Accept Multicast wakeup frame */
331 UWF = (1 << 4), /* Accept Unicast wakeup frame */
332 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 333 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
334
1da177e4
LT		 335 /* TBICSR p.28 */
336 TBIReset = 0x80000000,
337 TBILoopback = 0x40000000,
338 TBINwEnable = 0x20000000,
339 TBINwRestart = 0x10000000,
340 TBILinkOk = 0x02000000,
341 TBINwComplete = 0x01000000,
342
343 /* CPlusCmd p.31 */
f162a5d1
FR		 344 EnableBist = (1 << 15), // 8168 8101
345 Mac_dbgo_oe = (1 << 14), // 8168 8101
346 Normal_mode = (1 << 13), // unused
347 Force_half_dup = (1 << 12), // 8168 8101
348 Force_rxflow_en = (1 << 11), // 8168 8101
349 Force_txflow_en = (1 << 10), // 8168 8101
350 Cxpl_dbg_sel = (1 << 9), // 8168 8101
351 ASF = (1 << 8), // 8168 8101
352 PktCntrDisable = (1 << 7), // 8168 8101
353 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 354 RxVlan = (1 << 6),
355 RxChkSum = (1 << 5),
356 PCIDAC = (1 << 4),
357 PCIMulRW = (1 << 3),
0e485150
FR		 358 INTT_0 = 0x0000, // 8168
359 INTT_1 = 0x0001, // 8168
360 INTT_2 = 0x0002, // 8168
361 INTT_3 = 0x0003, // 8168
1da177e4
LT		 362
363 /* rtl8169_PHYstatus */
07d3f51f
FR		 364 TBI_Enable = 0x80,
365 TxFlowCtrl = 0x40,
366 RxFlowCtrl = 0x20,
367 _1000bpsF = 0x10,
368 _100bps = 0x08,
369 _10bps = 0x04,
370 LinkStatus = 0x02,
371 FullDup = 0x01,
1da177e4 372
1da177e4 373 /* _TBICSRBit */
07d3f51f 374 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 375
376 /* DumpCounterCommand */
07d3f51f 377 CounterDump = 0x8,
1da177e4
LT		 378};
379
07d3f51f 380enum desc_status_bit {
1da177e4
LT		 381 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
382 RingEnd = (1 << 30), /* End of descriptor ring */
383 FirstFrag = (1 << 29), /* First segment of a packet */
384 LastFrag = (1 << 28), /* Final segment of a packet */
385
386 /* Tx private */
387 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
388 MSSShift = 16, /* MSS value position */
389 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
390 IPCS = (1 << 18), /* Calculate IP checksum */
391 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
392 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
393 TxVlanTag = (1 << 17), /* Add VLAN tag */
394
395 /* Rx private */
396 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
397 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
398
399#define RxProtoUDP (PID1)
400#define RxProtoTCP (PID0)
401#define RxProtoIP (PID1 | PID0)
402#define RxProtoMask RxProtoIP
403
404 IPFail = (1 << 16), /* IP checksum failed */
405 UDPFail = (1 << 15), /* UDP/IP checksum failed */
406 TCPFail = (1 << 14), /* TCP/IP checksum failed */
407 RxVlanTag = (1 << 16), /* VLAN tag available */
408};
409
410#define RsvdMask 0x3fffc000
411
412struct TxDesc {
6cccd6e7
REB		 413 __le32 opts1;
414 __le32 opts2;
415 __le64 addr;
1da177e4
LT		 416};
417
418struct RxDesc {
6cccd6e7
REB		 419 __le32 opts1;
420 __le32 opts2;
421 __le64 addr;
1da177e4
LT		 422};
423
424struct ring_info {
425 struct sk_buff *skb;
426 u32 len;
427 u8 __pad[sizeof(void *) - sizeof(u32)];
428};
429
f23e7fda 430enum features {
ccdffb9a
FR		 431 RTL_FEATURE_WOL = (1 << 0),
432 RTL_FEATURE_MSI = (1 << 1),
433 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 434};
435
1da177e4
LT		 436struct rtl8169_private {
437 void __iomem *mmio_addr; /* memory map physical address */
438 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 439 struct net_device *dev;
bea3348e 440 struct napi_struct napi;
1da177e4 441 spinlock_t lock; /* spin lock flag */
b57b7e5a 442 u32 msg_enable;
1da177e4
LT		 443 int chipset;
444 int mac_version;
1da177e4
LT		 445 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
446 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
447 u32 dirty_rx;
448 u32 dirty_tx;
449 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
450 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
451 dma_addr_t TxPhyAddr;
452 dma_addr_t RxPhyAddr;
453 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
454 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 455 unsigned align;
1da177e4
LT		 456 unsigned rx_buf_sz;
457 struct timer_list timer;
458 u16 cp_cmd;
0e485150
FR		 459 u16 intr_event;
460 u16 napi_event;
1da177e4
LT		 461 u16 intr_mask;
462 int phy_auto_nego_reg;
463 int phy_1000_ctrl_reg;
464#ifdef CONFIG_R8169_VLAN
465 struct vlan_group *vlgrp;
466#endif
467 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 468 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 469 void (*phy_reset_enable)(void __iomem *);
07ce4064 470 void (*hw_start)(struct net_device *);
1da177e4
LT		 471 unsigned int (*phy_reset_pending)(void __iomem *);
472 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 473 int pcie_cap;
c4028958 474 struct delayed_work task;
f23e7fda 475 unsigned features;
ccdffb9a
FR		 476
477 struct mii_if_info mii;
1da177e4
LT		 478};
479
979b6c13 480MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 481MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 482module_param(rx_copybreak, int, 0);
1b7efd58 483MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 484module_param(use_dac, int, 0);
485MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 486module_param_named(debug, debug.msg_enable, int, 0);
487MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 488MODULE_LICENSE("GPL");
489MODULE_VERSION(RTL8169_VERSION);
490
491static int rtl8169_open(struct net_device *dev);
492static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 493static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 494static int rtl8169_init_ring(struct net_device *dev);
07ce4064 495static void rtl_hw_start(struct net_device *dev);
1da177e4 496static int rtl8169_close(struct net_device *dev);
07ce4064 497static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 498static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 499static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 500static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 501 void __iomem *, u32 budget);
4dcb7d33 502static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 503static void rtl8169_down(struct net_device *dev);
99f252b0 504static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 505static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 506
1da177e4 507static const unsigned int rtl8169_rx_config =
5b0384f4 508 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 509
07d3f51f 510static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 511{
512 int i;
513
a6baf3af 514 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 515
2371408c 516 for (i = 20; i > 0; i--) {
07d3f51f
FR		 517 /*
518 * Check if the RTL8169 has completed writing to the specified
519 * MII register.
520 */
5b0384f4 521 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 522 break;
2371408c 523 udelay(25);
1da177e4
LT		 524 }
525}
526
07d3f51f 527static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 528{
529 int i, value = -1;
530
a6baf3af 531 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 532
2371408c 533 for (i = 20; i > 0; i--) {
07d3f51f
FR		 534 /*
535 * Check if the RTL8169 has completed retrieving data from
536 * the specified MII register.
537 */
1da177e4 538 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 539 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 540 break;
541 }
2371408c 542 udelay(25);
1da177e4
LT		 543 }
544 return value;
545}
546
dacf8154
FR		 547static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
548{
549 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
550}
551
ccdffb9a
FR		 552static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
553 int val)
554{
555 struct rtl8169_private *tp = netdev_priv(dev);
556 void __iomem *ioaddr = tp->mmio_addr;
557
558 mdio_write(ioaddr, location, val);
559}
560
561static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
562{
563 struct rtl8169_private *tp = netdev_priv(dev);
564 void __iomem *ioaddr = tp->mmio_addr;
565
566 return mdio_read(ioaddr, location);
567}
568
dacf8154
FR		 569static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
570{
571 unsigned int i;
572
573 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
574 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
575
576 for (i = 0; i < 100; i++) {
577 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
578 break;
579 udelay(10);
580 }
581}
582
583static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
584{
585 u16 value = 0xffff;
586 unsigned int i;
587
588 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
589
590 for (i = 0; i < 100; i++) {
591 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
592 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
593 break;
594 }
595 udelay(10);
596 }
597
598 return value;
599}
600
601static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
602{
603 unsigned int i;
604
605 RTL_W32(CSIDR, value);
606 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
607 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
608
609 for (i = 0; i < 100; i++) {
610 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
611 break;
612 udelay(10);
613 }
614}
615
616static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
617{
618 u32 value = ~0x00;
619 unsigned int i;
620
621 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
622 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
623
624 for (i = 0; i < 100; i++) {
625 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
626 value = RTL_R32(CSIDR);
627 break;
628 }
629 udelay(10);
630 }
631
632 return value;
633}
634
1da177e4
LT		 635static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
636{
637 RTL_W16(IntrMask, 0x0000);
638
639 RTL_W16(IntrStatus, 0xffff);
640}
641
642static void rtl8169_asic_down(void __iomem *ioaddr)
643{
644 RTL_W8(ChipCmd, 0x00);
645 rtl8169_irq_mask_and_ack(ioaddr);
646 RTL_R16(CPlusCmd);
647}
648
649static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
650{
651 return RTL_R32(TBICSR) & TBIReset;
652}
653
654static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
655{
64e4bfb4 656 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 657}
658
659static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
660{
661 return RTL_R32(TBICSR) & TBILinkOk;
662}
663
664static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
665{
666 return RTL_R8(PHYstatus) & LinkStatus;
667}
668
669static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
670{
671 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
672}
673
674static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
675{
676 unsigned int val;
677
9e0db8ef
FR		 678 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
679 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 680}
681
682static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 683 struct rtl8169_private *tp,
684 void __iomem *ioaddr)
1da177e4
LT		 685{
686 unsigned long flags;
687
688 spin_lock_irqsave(&tp->lock, flags);
689 if (tp->link_ok(ioaddr)) {
690 netif_carrier_on(dev);
b57b7e5a
SH		 691 if (netif_msg_ifup(tp))
692 printk(KERN_INFO PFX "%s: link up\n", dev->name);
693 } else {
694 if (netif_msg_ifdown(tp))
695 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 696 netif_carrier_off(dev);
b57b7e5a 697 }
1da177e4
LT		 698 spin_unlock_irqrestore(&tp->lock, flags);
699}
700
61a4dcc2
FR		 701static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
702{
703 struct rtl8169_private *tp = netdev_priv(dev);
704 void __iomem *ioaddr = tp->mmio_addr;
705 u8 options;
706
707 wol->wolopts = 0;
708
709#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
710 wol->supported = WAKE_ANY;
711
712 spin_lock_irq(&tp->lock);
713
714 options = RTL_R8(Config1);
715 if (!(options & PMEnable))
716 goto out_unlock;
717
718 options = RTL_R8(Config3);
719 if (options & LinkUp)
720 wol->wolopts |= WAKE_PHY;
721 if (options & MagicPacket)
722 wol->wolopts |= WAKE_MAGIC;
723
724 options = RTL_R8(Config5);
725 if (options & UWF)
726 wol->wolopts |= WAKE_UCAST;
727 if (options & BWF)
5b0384f4 728 wol->wolopts |= WAKE_BCAST;
61a4dcc2 729 if (options & MWF)
5b0384f4 730 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 731
732out_unlock:
733 spin_unlock_irq(&tp->lock);
734}
735
736static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
737{
738 struct rtl8169_private *tp = netdev_priv(dev);
739 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 740 unsigned int i;
61a4dcc2
FR		 741 static struct {
742 u32 opt;
743 u16 reg;
744 u8 mask;
745 } cfg[] = {
746 { WAKE_ANY, Config1, PMEnable },
747 { WAKE_PHY, Config3, LinkUp },
748 { WAKE_MAGIC, Config3, MagicPacket },
749 { WAKE_UCAST, Config5, UWF },
750 { WAKE_BCAST, Config5, BWF },
751 { WAKE_MCAST, Config5, MWF },
752 { WAKE_ANY, Config5, LanWake }
753 };
754
755 spin_lock_irq(&tp->lock);
756
757 RTL_W8(Cfg9346, Cfg9346_Unlock);
758
759 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
760 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
761 if (wol->wolopts & cfg[i].opt)
762 options |= cfg[i].mask;
763 RTL_W8(cfg[i].reg, options);
764 }
765
766 RTL_W8(Cfg9346, Cfg9346_Lock);
767
f23e7fda
FR		 768 if (wol->wolopts)
769 tp->features |= RTL_FEATURE_WOL;
770 else
771 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 772 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 773
774 spin_unlock_irq(&tp->lock);
775
776 return 0;
777}
778
1da177e4
LT		 779static void rtl8169_get_drvinfo(struct net_device *dev,
780 struct ethtool_drvinfo *info)
781{
782 struct rtl8169_private *tp = netdev_priv(dev);
783
784 strcpy(info->driver, MODULENAME);
785 strcpy(info->version, RTL8169_VERSION);
786 strcpy(info->bus_info, pci_name(tp->pci_dev));
787}
788
789static int rtl8169_get_regs_len(struct net_device *dev)
790{
791 return R8169_REGS_SIZE;
792}
793
794static int rtl8169_set_speed_tbi(struct net_device *dev,
795 u8 autoneg, u16 speed, u8 duplex)
796{
797 struct rtl8169_private *tp = netdev_priv(dev);
798 void __iomem *ioaddr = tp->mmio_addr;
799 int ret = 0;
800 u32 reg;
801
802 reg = RTL_R32(TBICSR);
803 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
804 (duplex == DUPLEX_FULL)) {
805 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
806 } else if (autoneg == AUTONEG_ENABLE)
807 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
808 else {
b57b7e5a
SH		 809 if (netif_msg_link(tp)) {
810 printk(KERN_WARNING "%s: "
811 "incorrect speed setting refused in TBI mode\n",
812 dev->name);
813 }
1da177e4
LT		 814 ret = -EOPNOTSUPP;
815 }
816
817 return ret;
818}
819
820static int rtl8169_set_speed_xmii(struct net_device *dev,
821 u8 autoneg, u16 speed, u8 duplex)
822{
823 struct rtl8169_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->mmio_addr;
825 int auto_nego, giga_ctrl;
826
64e4bfb4
FR		 827 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
828 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
829 ADVERTISE_100HALF | ADVERTISE_100FULL);
830 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
831 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 832
833 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 834 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
835 ADVERTISE_100HALF | ADVERTISE_100FULL);
836 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 837 } else {
838 if (speed == SPEED_10)
64e4bfb4 839 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 840 else if (speed == SPEED_100)
64e4bfb4 841 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 842 else if (speed == SPEED_1000)
64e4bfb4 843 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 844
845 if (duplex == DUPLEX_HALF)
64e4bfb4 846 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 847
848 if (duplex == DUPLEX_FULL)
64e4bfb4 849 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 850
851 /* This tweak comes straight from Realtek's driver. */
852 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 853 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
854 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 855 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 856 }
857 }
858
2857ffb7
FR		 859 /* The 8100e/8101e/8102e do Fast Ethernet only. */
860 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
861 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
862 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
863 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
864 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 865 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 866 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
867 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 868 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 869 netif_msg_link(tp)) {
870 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
871 dev->name);
872 }
64e4bfb4 873 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 874 }
875
623a1593
FR		 876 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
877
a2de6b89
FR		 878 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
879 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
880 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
881 /*
882 * Wake up the PHY.
883 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
884 */
2584fbc3
RS		 885 mdio_write(ioaddr, 0x1f, 0x0000);
886 mdio_write(ioaddr, 0x0e, 0x0000);
887 }
888
1da177e4
LT		 889 tp->phy_auto_nego_reg = auto_nego;
890 tp->phy_1000_ctrl_reg = giga_ctrl;
891
64e4bfb4
FR		 892 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
893 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
894 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 895 return 0;
896}
897
898static int rtl8169_set_speed(struct net_device *dev,
899 u8 autoneg, u16 speed, u8 duplex)
900{
901 struct rtl8169_private *tp = netdev_priv(dev);
902 int ret;
903
904 ret = tp->set_speed(dev, autoneg, speed, duplex);
905
64e4bfb4 906 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 907 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
908
909 return ret;
910}
911
912static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
913{
914 struct rtl8169_private *tp = netdev_priv(dev);
915 unsigned long flags;
916 int ret;
917
918 spin_lock_irqsave(&tp->lock, flags);
919 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
920 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 921
1da177e4
LT		 922 return ret;
923}
924
925static u32 rtl8169_get_rx_csum(struct net_device *dev)
926{
927 struct rtl8169_private *tp = netdev_priv(dev);
928
929 return tp->cp_cmd & RxChkSum;
930}
931
932static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
933{
934 struct rtl8169_private *tp = netdev_priv(dev);
935 void __iomem *ioaddr = tp->mmio_addr;
936 unsigned long flags;
937
938 spin_lock_irqsave(&tp->lock, flags);
939
940 if (data)
941 tp->cp_cmd |= RxChkSum;
942 else
943 tp->cp_cmd &= ~RxChkSum;
944
945 RTL_W16(CPlusCmd, tp->cp_cmd);
946 RTL_R16(CPlusCmd);
947
948 spin_unlock_irqrestore(&tp->lock, flags);
949
950 return 0;
951}
952
953#ifdef CONFIG_R8169_VLAN
954
955static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
956 struct sk_buff *skb)
957{
958 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
959 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
960}
961
962static void rtl8169_vlan_rx_register(struct net_device *dev,
963 struct vlan_group *grp)
964{
965 struct rtl8169_private *tp = netdev_priv(dev);
966 void __iomem *ioaddr = tp->mmio_addr;
967 unsigned long flags;
968
969 spin_lock_irqsave(&tp->lock, flags);
970 tp->vlgrp = grp;
971 if (tp->vlgrp)
972 tp->cp_cmd |= RxVlan;
973 else
974 tp->cp_cmd &= ~RxVlan;
975 RTL_W16(CPlusCmd, tp->cp_cmd);
976 RTL_R16(CPlusCmd);
977 spin_unlock_irqrestore(&tp->lock, flags);
978}
979
1da177e4
LT		 980static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
981 struct sk_buff *skb)
982{
983 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 984 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 985 int ret;
986
865c652d
FR		 987 if (vlgrp && (opts2 & RxVlanTag)) {
988 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 989 ret = 0;
990 } else
991 ret = -1;
992 desc->opts2 = 0;
993 return ret;
994}
995
996#else /* !CONFIG_R8169_VLAN */
997
998static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
999 struct sk_buff *skb)
1000{
1001 return 0;
1002}
1003
1004static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1005 struct sk_buff *skb)
1006{
1007 return -1;
1008}
1009
1010#endif
1011
ccdffb9a 1012static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1013{
1014 struct rtl8169_private *tp = netdev_priv(dev);
1015 void __iomem *ioaddr = tp->mmio_addr;
1016 u32 status;
1017
1018 cmd->supported =
1019 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1020 cmd->port = PORT_FIBRE;
1021 cmd->transceiver = XCVR_INTERNAL;
1022
1023 status = RTL_R32(TBICSR);
1024 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1025 cmd->autoneg = !!(status & TBINwEnable);
1026
1027 cmd->speed = SPEED_1000;
1028 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1029
1030 return 0;
1da177e4
LT		 1031}
1032
ccdffb9a 1033static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1034{
1035 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1036
1037 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1038}
1039
1040static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1041{
1042 struct rtl8169_private *tp = netdev_priv(dev);
1043 unsigned long flags;
ccdffb9a 1044 int rc;
1da177e4
LT		 1045
1046 spin_lock_irqsave(&tp->lock, flags);
1047
ccdffb9a 1048 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1049
1050 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1051 return rc;
1da177e4
LT		 1052}
1053
1054static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1055 void *p)
1056{
5b0384f4
FR		 1057 struct rtl8169_private *tp = netdev_priv(dev);
1058 unsigned long flags;
1da177e4 1059
5b0384f4
FR		 1060 if (regs->len > R8169_REGS_SIZE)
1061 regs->len = R8169_REGS_SIZE;
1da177e4 1062
5b0384f4
FR		 1063 spin_lock_irqsave(&tp->lock, flags);
1064 memcpy_fromio(p, tp->mmio_addr, regs->len);
1065 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1066}
1067
b57b7e5a
SH		 1068static u32 rtl8169_get_msglevel(struct net_device *dev)
1069{
1070 struct rtl8169_private *tp = netdev_priv(dev);
1071
1072 return tp->msg_enable;
1073}
1074
1075static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1076{
1077 struct rtl8169_private *tp = netdev_priv(dev);
1078
1079 tp->msg_enable = value;
1080}
1081
d4a3a0fc
SH		 1082static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1083 "tx_packets",
1084 "rx_packets",
1085 "tx_errors",
1086 "rx_errors",
1087 "rx_missed",
1088 "align_errors",
1089 "tx_single_collisions",
1090 "tx_multi_collisions",
1091 "unicast",
1092 "broadcast",
1093 "multicast",
1094 "tx_aborted",
1095 "tx_underrun",
1096};
1097
1098struct rtl8169_counters {
b1eab701
AV		 1099 __le64 tx_packets;
1100 __le64 rx_packets;
1101 __le64 tx_errors;
1102 __le32 rx_errors;
1103 __le16 rx_missed;
1104 __le16 align_errors;
1105 __le32 tx_one_collision;
1106 __le32 tx_multi_collision;
1107 __le64 rx_unicast;
1108 __le64 rx_broadcast;
1109 __le32 rx_multicast;
1110 __le16 tx_aborted;
1111 __le16 tx_underun;
d4a3a0fc
SH		 1112};
1113
b9f2c044 1114static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1115{
b9f2c044
JG		 1116 switch (sset) {
1117 case ETH_SS_STATS:
1118 return ARRAY_SIZE(rtl8169_gstrings);
1119 default:
1120 return -EOPNOTSUPP;
1121 }
d4a3a0fc
SH		 1122}
1123
1124static void rtl8169_get_ethtool_stats(struct net_device *dev,
1125 struct ethtool_stats *stats, u64 *data)
1126{
1127 struct rtl8169_private *tp = netdev_priv(dev);
1128 void __iomem *ioaddr = tp->mmio_addr;
1129 struct rtl8169_counters *counters;
1130 dma_addr_t paddr;
1131 u32 cmd;
1132
1133 ASSERT_RTNL();
1134
1135 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1136 if (!counters)
1137 return;
1138
1139 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1140 cmd = (u64)paddr & DMA_32BIT_MASK;
1141 RTL_W32(CounterAddrLow, cmd);
1142 RTL_W32(CounterAddrLow, cmd | CounterDump);
1143
1144 while (RTL_R32(CounterAddrLow) & CounterDump) {
1145 if (msleep_interruptible(1))
1146 break;
1147 }
1148
1149 RTL_W32(CounterAddrLow, 0);
1150 RTL_W32(CounterAddrHigh, 0);
1151
5b0384f4 1152 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1153 data[1] = le64_to_cpu(counters->rx_packets);
1154 data[2] = le64_to_cpu(counters->tx_errors);
1155 data[3] = le32_to_cpu(counters->rx_errors);
1156 data[4] = le16_to_cpu(counters->rx_missed);
1157 data[5] = le16_to_cpu(counters->align_errors);
1158 data[6] = le32_to_cpu(counters->tx_one_collision);
1159 data[7] = le32_to_cpu(counters->tx_multi_collision);
1160 data[8] = le64_to_cpu(counters->rx_unicast);
1161 data[9] = le64_to_cpu(counters->rx_broadcast);
1162 data[10] = le32_to_cpu(counters->rx_multicast);
1163 data[11] = le16_to_cpu(counters->tx_aborted);
1164 data[12] = le16_to_cpu(counters->tx_underun);
1165
1166 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1167}
1168
1169static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1170{
1171 switch(stringset) {
1172 case ETH_SS_STATS:
1173 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1174 break;
1175 }
1176}
1177
7282d491 1178static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1179 .get_drvinfo = rtl8169_get_drvinfo,
1180 .get_regs_len = rtl8169_get_regs_len,
1181 .get_link = ethtool_op_get_link,
1182 .get_settings = rtl8169_get_settings,
1183 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1184 .get_msglevel = rtl8169_get_msglevel,
1185 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1186 .get_rx_csum = rtl8169_get_rx_csum,
1187 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1188 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1189 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1190 .set_tso = ethtool_op_set_tso,
1191 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1192 .get_wol = rtl8169_get_wol,
1193 .set_wol = rtl8169_set_wol,
d4a3a0fc 1194 .get_strings = rtl8169_get_strings,
b9f2c044 1195 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1196 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1197};
1198
07d3f51f
FR		 1199static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1200 int bitnum, int bitval)
1da177e4
LT		 1201{
1202 int val;
1203
1204 val = mdio_read(ioaddr, reg);
1205 val = (bitval == 1) ?
1206 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1207 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1208}
1209
07d3f51f
FR		 1210static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1211 void __iomem *ioaddr)
1da177e4 1212{
0e485150
FR		 1213 /*
1214 * The driver currently handles the 8168Bf and the 8168Be identically
1215 * but they can be identified more specifically through the test below
1216 * if needed:
1217 *
1218 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1219 *
1220 * Same thing for the 8101Eb and the 8101Ec:
1221 *
1222 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1223 */
1da177e4
LT		 1224 const struct {
1225 u32 mask;
e3cf0cc0 1226 u32 val;
1da177e4
LT		 1227 int mac_version;
1228 } mac_info[] = {
5b538df9
FR		 1229 /* 8168D family. */
1230 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1231
ef808d50 1232 /* 8168C family. */
7f3e3d3a 1233 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1234 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1235 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1236 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1237 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1238 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1239 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1240 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1241 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1242
1243 /* 8168B family. */
1244 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1245 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1246 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1247 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1248
1249 /* 8101 family. */
2857ffb7
FR		 1250 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1251 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1252 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1253 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1254 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1255 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1256 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1257 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1258 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1259 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1260 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1261 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1262 /* FIXME: where did these entries come from ? -- FR */
1263 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1264 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1265
1266 /* 8110 family. */
1267 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1268 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1269 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1270 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1271 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1272 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1273
1274 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1275 }, *p = mac_info;
1276 u32 reg;
1277
e3cf0cc0
FR		 1278 reg = RTL_R32(TxConfig);
1279 while ((reg & p->mask) != p->val)
1da177e4
LT		 1280 p++;
1281 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1282
1283 if (p->mask == 0x00000000) {
1284 struct pci_dev *pdev = tp->pci_dev;
1285
1286 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1287 }
1da177e4
LT		 1288}
1289
1290static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1291{
bcf0bf90 1292 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1293}
1294
867763c1
FR		 1295struct phy_reg {
1296 u16 reg;
1297 u16 val;
1298};
1299
1300static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1301{
1302 while (len-- > 0) {
1303 mdio_write(ioaddr, regs->reg, regs->val);
1304 regs++;
1305 }
1306}
1307
5615d9f1 1308static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1309{
1da177e4
LT		 1310 struct {
1311 u16 regs[5]; /* Beware of bit-sign propagation */
1312 } phy_magic[5] = { {
1313 { 0x0000, //w 4 15 12 0
1314 0x00a1, //w 3 15 0 00a1
1315 0x0008, //w 2 15 0 0008
1316 0x1020, //w 1 15 0 1020
1317 0x1000 } },{ //w 0 15 0 1000
1318 { 0x7000, //w 4 15 12 7
1319 0xff41, //w 3 15 0 ff41
1320 0xde60, //w 2 15 0 de60
1321 0x0140, //w 1 15 0 0140
1322 0x0077 } },{ //w 0 15 0 0077
1323 { 0xa000, //w 4 15 12 a
1324 0xdf01, //w 3 15 0 df01
1325 0xdf20, //w 2 15 0 df20
1326 0xff95, //w 1 15 0 ff95
1327 0xfa00 } },{ //w 0 15 0 fa00
1328 { 0xb000, //w 4 15 12 b
1329 0xff41, //w 3 15 0 ff41
1330 0xde20, //w 2 15 0 de20
1331 0x0140, //w 1 15 0 0140
1332 0x00bb } },{ //w 0 15 0 00bb
1333 { 0xf000, //w 4 15 12 f
1334 0xdf01, //w 3 15 0 df01
1335 0xdf20, //w 2 15 0 df20
1336 0xff95, //w 1 15 0 ff95
1337 0xbf00 } //w 0 15 0 bf00
1338 }
1339 }, *p = phy_magic;
07d3f51f 1340 unsigned int i;
1da177e4 1341
a441d7b6
FR		 1342 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1343 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1344 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1345 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1346
1347 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1348 int val, pos = 4;
1349
1350 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1351 mdio_write(ioaddr, pos, val);
1352 while (--pos >= 0)
1353 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1354 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1355 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1356 }
a441d7b6 1357 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1358}
1359
5615d9f1
FR		 1360static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1361{
a441d7b6
FR		 1362 struct phy_reg phy_reg_init[] = {
1363 { 0x1f, 0x0002 },
1364 { 0x01, 0x90d0 },
1365 { 0x1f, 0x0000 }
1366 };
1367
1368 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1369}
1370
236b8082
FR		 1371static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1372{
1373 struct phy_reg phy_reg_init[] = {
1374 { 0x10, 0xf41b },
1375 { 0x1f, 0x0000 }
1376 };
1377
1378 mdio_write(ioaddr, 0x1f, 0x0001);
1379 mdio_patch(ioaddr, 0x16, 1 << 0);
1380
1381 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1382}
1383
1384static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1385{
1386 struct phy_reg phy_reg_init[] = {
1387 { 0x1f, 0x0001 },
1388 { 0x10, 0xf41b },
1389 { 0x1f, 0x0000 }
1390 };
1391
1392 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1393}
1394
ef3386f0 1395static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1396{
1397 struct phy_reg phy_reg_init[] = {
1398 { 0x1f, 0x0000 },
1399 { 0x1d, 0x0f00 },
1400 { 0x1f, 0x0002 },
1401 { 0x0c, 0x1ec8 },
1402 { 0x1f, 0x0000 }
1403 };
1404
1405 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1406}
1407
ef3386f0
FR		 1408static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1409{
1410 struct phy_reg phy_reg_init[] = {
1411 { 0x1f, 0x0001 },
1412 { 0x1d, 0x3d98 },
1413 { 0x1f, 0x0000 }
1414 };
1415
1416 mdio_write(ioaddr, 0x1f, 0x0000);
1417 mdio_patch(ioaddr, 0x14, 1 << 5);
1418 mdio_patch(ioaddr, 0x0d, 1 << 5);
1419
1420 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1421}
1422
219a1e9d 1423static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1424{
1425 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1426 { 0x1f, 0x0001 },
1427 { 0x12, 0x2300 },
867763c1
FR		 1428 { 0x1f, 0x0002 },
1429 { 0x00, 0x88d4 },
1430 { 0x01, 0x82b1 },
1431 { 0x03, 0x7002 },
1432 { 0x08, 0x9e30 },
1433 { 0x09, 0x01f0 },
1434 { 0x0a, 0x5500 },
1435 { 0x0c, 0x00c8 },
1436 { 0x1f, 0x0003 },
1437 { 0x12, 0xc096 },
1438 { 0x16, 0x000a },
f50d4275
FR		 1439 { 0x1f, 0x0000 },
1440 { 0x1f, 0x0000 },
1441 { 0x09, 0x2000 },
1442 { 0x09, 0x0000 }
867763c1
FR		 1443 };
1444
1445 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1446
1447 mdio_patch(ioaddr, 0x14, 1 << 5);
1448 mdio_patch(ioaddr, 0x0d, 1 << 5);
1449 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1450}
1451
219a1e9d 1452static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1453{
1454 struct phy_reg phy_reg_init[] = {
f50d4275 1455 { 0x1f, 0x0001 },
7da97ec9 1456 { 0x12, 0x2300 },
f50d4275
FR		 1457 { 0x03, 0x802f },
1458 { 0x02, 0x4f02 },
1459 { 0x01, 0x0409 },
1460 { 0x00, 0xf099 },
1461 { 0x04, 0x9800 },
1462 { 0x04, 0x9000 },
1463 { 0x1d, 0x3d98 },
7da97ec9
FR		 1464 { 0x1f, 0x0002 },
1465 { 0x0c, 0x7eb8 },
f50d4275
FR		 1466 { 0x06, 0x0761 },
1467 { 0x1f, 0x0003 },
1468 { 0x16, 0x0f0a },
7da97ec9
FR		 1469 { 0x1f, 0x0000 }
1470 };
1471
1472 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1473
1474 mdio_patch(ioaddr, 0x16, 1 << 0);
1475 mdio_patch(ioaddr, 0x14, 1 << 5);
1476 mdio_patch(ioaddr, 0x0d, 1 << 5);
1477 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1478}
1479
197ff761
FR		 1480static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1481{
1482 struct phy_reg phy_reg_init[] = {
1483 { 0x1f, 0x0001 },
1484 { 0x12, 0x2300 },
1485 { 0x1d, 0x3d98 },
1486 { 0x1f, 0x0002 },
1487 { 0x0c, 0x7eb8 },
1488 { 0x06, 0x5461 },
1489 { 0x1f, 0x0003 },
1490 { 0x16, 0x0f0a },
1491 { 0x1f, 0x0000 }
1492 };
1493
1494 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1495
1496 mdio_patch(ioaddr, 0x16, 1 << 0);
1497 mdio_patch(ioaddr, 0x14, 1 << 5);
1498 mdio_patch(ioaddr, 0x0d, 1 << 5);
1499 mdio_write(ioaddr, 0x1f, 0x0000);
1500}
1501
6fb07058
FR		 1502static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1503{
1504 rtl8168c_3_hw_phy_config(ioaddr);
1505}
1506
5b538df9
FR		 1507static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1508{
1509 struct phy_reg phy_reg_init_0[] = {
1510 { 0x1f, 0x0001 },
1511 { 0x09, 0x2770 },
1512 { 0x08, 0x04d0 },
1513 { 0x0b, 0xad15 },
1514 { 0x0c, 0x5bf0 },
1515 { 0x1c, 0xf101 },
1516 { 0x1f, 0x0003 },
1517 { 0x14, 0x94d7 },
1518 { 0x12, 0xf4d6 },
1519 { 0x09, 0xca0f },
1520 { 0x1f, 0x0002 },
1521 { 0x0b, 0x0b10 },
1522 { 0x0c, 0xd1f7 },
1523 { 0x1f, 0x0002 },
1524 { 0x06, 0x5461 },
1525 { 0x1f, 0x0002 },
1526 { 0x05, 0x6662 },
1527 { 0x1f, 0x0000 },
1528 { 0x14, 0x0060 },
1529 { 0x1f, 0x0000 },
1530 { 0x0d, 0xf8a0 },
1531 { 0x1f, 0x0005 },
1532 { 0x05, 0xffc2 }
1533 };
1534
1535 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1536
1537 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1538 struct phy_reg phy_reg_init_1[] = {
1539 { 0x1f, 0x0005 },
1540 { 0x01, 0x0300 },
1541 { 0x1f, 0x0000 },
1542 { 0x11, 0x401c },
1543 { 0x16, 0x4100 },
1544 { 0x1f, 0x0005 },
1545 { 0x07, 0x0010 },
1546 { 0x05, 0x83dc },
1547 { 0x06, 0x087d },
1548 { 0x05, 0x8300 },
1549 { 0x06, 0x0101 },
1550 { 0x06, 0x05f8 },
1551 { 0x06, 0xf9fa },
1552 { 0x06, 0xfbef },
1553 { 0x06, 0x79e2 },
1554 { 0x06, 0x835f },
1555 { 0x06, 0xe0f8 },
1556 { 0x06, 0x9ae1 },
1557 { 0x06, 0xf89b },
1558 { 0x06, 0xef31 },
1559 { 0x06, 0x3b65 },
1560 { 0x06, 0xaa07 },
1561 { 0x06, 0x81e4 },
1562 { 0x06, 0xf89a },
1563 { 0x06, 0xe5f8 },
1564 { 0x06, 0x9baf },
1565 { 0x06, 0x06ae },
1566 { 0x05, 0x83dc },
1567 { 0x06, 0x8300 },
1568 };
1569
1570 rtl_phy_write(ioaddr, phy_reg_init_1,
1571 ARRAY_SIZE(phy_reg_init_1));
1572 }
1573
1574 mdio_write(ioaddr, 0x1f, 0x0000);
1575}
1576
2857ffb7
FR		 1577static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1578{
1579 struct phy_reg phy_reg_init[] = {
1580 { 0x1f, 0x0003 },
1581 { 0x08, 0x441d },
1582 { 0x01, 0x9100 },
1583 { 0x1f, 0x0000 }
1584 };
1585
1586 mdio_write(ioaddr, 0x1f, 0x0000);
1587 mdio_patch(ioaddr, 0x11, 1 << 12);
1588 mdio_patch(ioaddr, 0x19, 1 << 13);
1589
1590 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1591}
1592
5615d9f1
FR		 1593static void rtl_hw_phy_config(struct net_device *dev)
1594{
1595 struct rtl8169_private *tp = netdev_priv(dev);
1596 void __iomem *ioaddr = tp->mmio_addr;
1597
1598 rtl8169_print_mac_version(tp);
1599
1600 switch (tp->mac_version) {
1601 case RTL_GIGA_MAC_VER_01:
1602 break;
1603 case RTL_GIGA_MAC_VER_02:
1604 case RTL_GIGA_MAC_VER_03:
1605 rtl8169s_hw_phy_config(ioaddr);
1606 break;
1607 case RTL_GIGA_MAC_VER_04:
1608 rtl8169sb_hw_phy_config(ioaddr);
1609 break;
2857ffb7
FR		 1610 case RTL_GIGA_MAC_VER_07:
1611 case RTL_GIGA_MAC_VER_08:
1612 case RTL_GIGA_MAC_VER_09:
1613 rtl8102e_hw_phy_config(ioaddr);
1614 break;
236b8082
FR		 1615 case RTL_GIGA_MAC_VER_11:
1616 rtl8168bb_hw_phy_config(ioaddr);
1617 break;
1618 case RTL_GIGA_MAC_VER_12:
1619 rtl8168bef_hw_phy_config(ioaddr);
1620 break;
1621 case RTL_GIGA_MAC_VER_17:
1622 rtl8168bef_hw_phy_config(ioaddr);
1623 break;
867763c1 1624 case RTL_GIGA_MAC_VER_18:
ef3386f0 1625 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1626 break;
1627 case RTL_GIGA_MAC_VER_19:
219a1e9d 1628 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1629 break;
7da97ec9 1630 case RTL_GIGA_MAC_VER_20:
219a1e9d 1631 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1632 break;
197ff761
FR		 1633 case RTL_GIGA_MAC_VER_21:
1634 rtl8168c_3_hw_phy_config(ioaddr);
1635 break;
6fb07058
FR		 1636 case RTL_GIGA_MAC_VER_22:
1637 rtl8168c_4_hw_phy_config(ioaddr);
1638 break;
ef3386f0 1639 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 1640 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 1641 rtl8168cp_2_hw_phy_config(ioaddr);
1642 break;
5b538df9
FR		 1643 case RTL_GIGA_MAC_VER_25:
1644 rtl8168d_hw_phy_config(ioaddr);
1645 break;
ef3386f0 1646
5615d9f1
FR		 1647 default:
1648 break;
1649 }
1650}
1651
1da177e4
LT		 1652static void rtl8169_phy_timer(unsigned long __opaque)
1653{
1654 struct net_device *dev = (struct net_device *)__opaque;
1655 struct rtl8169_private *tp = netdev_priv(dev);
1656 struct timer_list *timer = &tp->timer;
1657 void __iomem *ioaddr = tp->mmio_addr;
1658 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1659
bcf0bf90 1660 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1661
64e4bfb4 1662 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1663 return;
1664
1665 spin_lock_irq(&tp->lock);
1666
1667 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1668 /*
1da177e4
LT		 1669 * A busy loop could burn quite a few cycles on nowadays CPU.
1670 * Let's delay the execution of the timer for a few ticks.
1671 */
1672 timeout = HZ/10;
1673 goto out_mod_timer;
1674 }
1675
1676 if (tp->link_ok(ioaddr))
1677 goto out_unlock;
1678
b57b7e5a
SH		 1679 if (netif_msg_link(tp))
1680 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1681
1682 tp->phy_reset_enable(ioaddr);
1683
1684out_mod_timer:
1685 mod_timer(timer, jiffies + timeout);
1686out_unlock:
1687 spin_unlock_irq(&tp->lock);
1688}
1689
1690static inline void rtl8169_delete_timer(struct net_device *dev)
1691{
1692 struct rtl8169_private *tp = netdev_priv(dev);
1693 struct timer_list *timer = &tp->timer;
1694
e179bb7b 1695 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1696 return;
1697
1698 del_timer_sync(timer);
1699}
1700
1701static inline void rtl8169_request_timer(struct net_device *dev)
1702{
1703 struct rtl8169_private *tp = netdev_priv(dev);
1704 struct timer_list *timer = &tp->timer;
1705
e179bb7b 1706 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1707 return;
1708
2efa53f3 1709 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1710}
1711
1712#ifdef CONFIG_NET_POLL_CONTROLLER
1713/*
1714 * Polling 'interrupt' - used by things like netconsole to send skbs
1715 * without having to re-enable interrupts. It's not called while
1716 * the interrupt routine is executing.
1717 */
1718static void rtl8169_netpoll(struct net_device *dev)
1719{
1720 struct rtl8169_private *tp = netdev_priv(dev);
1721 struct pci_dev *pdev = tp->pci_dev;
1722
1723 disable_irq(pdev->irq);
7d12e780 1724 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1725 enable_irq(pdev->irq);
1726}
1727#endif
1728
1729static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1730 void __iomem *ioaddr)
1731{
1732 iounmap(ioaddr);
1733 pci_release_regions(pdev);
1734 pci_disable_device(pdev);
1735 free_netdev(dev);
1736}
1737
bf793295
FR		 1738static void rtl8169_phy_reset(struct net_device *dev,
1739 struct rtl8169_private *tp)
1740{
1741 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1742 unsigned int i;
bf793295
FR		 1743
1744 tp->phy_reset_enable(ioaddr);
1745 for (i = 0; i < 100; i++) {
1746 if (!tp->phy_reset_pending(ioaddr))
1747 return;
1748 msleep(1);
1749 }
1750 if (netif_msg_link(tp))
1751 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1752}
1753
4ff96fa6
FR		 1754static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1755{
1756 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1757
5615d9f1 1758 rtl_hw_phy_config(dev);
4ff96fa6 1759
77332894
MS		 1760 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1761 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1762 RTL_W8(0x82, 0x01);
1763 }
4ff96fa6 1764
6dccd16b
FR		 1765 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1766
1767 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1768 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1769
bcf0bf90 1770 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1771 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1772 RTL_W8(0x82, 0x01);
1773 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1774 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1775 }
1776
bf793295
FR		 1777 rtl8169_phy_reset(dev, tp);
1778
901dda2b
FR		 1779 /*
1780 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1781 * only 8101. Don't panic.
1782 */
1783 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1784
1785 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1786 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1787}
1788
773d2021
FR		 1789static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1790{
1791 void __iomem *ioaddr = tp->mmio_addr;
1792 u32 high;
1793 u32 low;
1794
1795 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1796 high = addr[4] | (addr[5] << 8);
1797
1798 spin_lock_irq(&tp->lock);
1799
1800 RTL_W8(Cfg9346, Cfg9346_Unlock);
1801 RTL_W32(MAC0, low);
1802 RTL_W32(MAC4, high);
1803 RTL_W8(Cfg9346, Cfg9346_Lock);
1804
1805 spin_unlock_irq(&tp->lock);
1806}
1807
1808static int rtl_set_mac_address(struct net_device *dev, void *p)
1809{
1810 struct rtl8169_private *tp = netdev_priv(dev);
1811 struct sockaddr *addr = p;
1812
1813 if (!is_valid_ether_addr(addr->sa_data))
1814 return -EADDRNOTAVAIL;
1815
1816 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1817
1818 rtl_rar_set(tp, dev->dev_addr);
1819
1820 return 0;
1821}
1822
5f787a1a
FR		 1823static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1824{
1825 struct rtl8169_private *tp = netdev_priv(dev);
1826 struct mii_ioctl_data *data = if_mii(ifr);
1827
1828 if (!netif_running(dev))
1829 return -ENODEV;
1830
1831 switch (cmd) {
1832 case SIOCGMIIPHY:
1833 data->phy_id = 32; /* Internal PHY */
1834 return 0;
1835
1836 case SIOCGMIIREG:
1837 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1838 return 0;
1839
1840 case SIOCSMIIREG:
1841 if (!capable(CAP_NET_ADMIN))
1842 return -EPERM;
1843 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1844 return 0;
1845 }
1846 return -EOPNOTSUPP;
1847}
1848
0e485150
FR		 1849static const struct rtl_cfg_info {
1850 void (*hw_start)(struct net_device *);
1851 unsigned int region;
1852 unsigned int align;
1853 u16 intr_event;
1854 u16 napi_event;
ccdffb9a 1855 unsigned features;
0e485150
FR		 1856} rtl_cfg_infos [] = {
1857 [RTL_CFG_0] = {
1858 .hw_start = rtl_hw_start_8169,
1859 .region = 1,
e9f63f30 1860 .align = 0,
0e485150
FR		 1861 .intr_event = SYSErr | LinkChg | RxOverflow |
1862 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1863 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1864 .features = RTL_FEATURE_GMII
0e485150
FR		 1865 },
1866 [RTL_CFG_1] = {
1867 .hw_start = rtl_hw_start_8168,
1868 .region = 2,
1869 .align = 8,
1870 .intr_event = SYSErr | LinkChg | RxOverflow |
1871 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1872 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1873 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1874 },
1875 [RTL_CFG_2] = {
1876 .hw_start = rtl_hw_start_8101,
1877 .region = 2,
1878 .align = 8,
1879 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1880 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1881 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1882 .features = RTL_FEATURE_MSI
0e485150
FR		 1883 }
1884};
1885
fbac58fc
FR		 1886/* Cfg9346_Unlock assumed. */
1887static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1888 const struct rtl_cfg_info *cfg)
1889{
1890 unsigned msi = 0;
1891 u8 cfg2;
1892
1893 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1894 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1895 if (pci_enable_msi(pdev)) {
1896 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1897 } else {
1898 cfg2 |= MSIEnable;
1899 msi = RTL_FEATURE_MSI;
1900 }
1901 }
1902 RTL_W8(Config2, cfg2);
1903 return msi;
1904}
1905
1906static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1907{
1908 if (tp->features & RTL_FEATURE_MSI) {
1909 pci_disable_msi(pdev);
1910 tp->features &= ~RTL_FEATURE_MSI;
1911 }
1912}
1913
7bf6bf48
IV		 1914static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1915{
1916 int ret, count = 100;
1917 u16 status = 0;
1918 u32 value;
1919
1920 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1921 if (ret < 0)
1922 return ret;
1923
1924 do {
1925 udelay(10);
1926 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1927 if (ret < 0)
1928 return ret;
1929 } while (!(status & PCI_VPD_ADDR_F) && --count);
1930
1931 if (!(status & PCI_VPD_ADDR_F))
1932 return -ETIMEDOUT;
1933
1934 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1935 if (ret < 0)
1936 return ret;
1937
1938 *val = cpu_to_le32(value);
1939
1940 return 0;
1941}
1942
1943static void rtl_init_mac_address(struct rtl8169_private *tp,
1944 void __iomem *ioaddr)
1945{
1946 struct pci_dev *pdev = tp->pci_dev;
1947 u8 cfg1;
1948 int vpd_cap;
1949 u8 mac[8];
7bf6bf48
IV		 1950
1951 cfg1 = RTL_R8(Config1);
1952 if (!(cfg1 & VPD)) {
cd926c73
FR		 1953 if (netif_msg_probe(tp))
1954 dev_info(&pdev->dev, "VPD access disabled, enabling\n");
7bf6bf48
IV		 1955 RTL_W8(Cfg9346, Cfg9346_Unlock);
1956 RTL_W8(Config1, cfg1 | VPD);
1957 RTL_W8(Cfg9346, Cfg9346_Lock);
1958 }
1959
1960 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1961 if (!vpd_cap)
1962 return;
1963
1964 /* MAC address is stored in EEPROM at offset 0x0e
1965 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1966 * address as defined in the PCI 2.2 Specifications, but the VPD data
1967 * is always consecutive 4-byte data starting from the VPD address
1968 * specified."
1969 */
1970 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1971 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
cd926c73
FR		 1972 if (netif_msg_probe(tp)) {
1973 dev_warn(&pdev->dev,
1974 "reading MAC address from EEPROM failed\n");
1975 }
7bf6bf48
IV		 1976 return;
1977 }
1978
cd926c73
FR		 1979 if (netif_msg_probe(tp)) {
1980 DECLARE_MAC_BUF(buf);
1981
1982 dev_info(&pdev->dev, "MAC address found in EEPROM: %s\n",
1983 print_mac(buf, mac));
1984 }
7bf6bf48
IV		 1985
1986 /* Write MAC address */
1987 rtl_rar_set(tp, mac);
1988}
1989
1da177e4 1990static int __devinit
4ff96fa6 1991rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1992{
0e485150
FR		 1993 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1994 const unsigned int region = cfg->region;
1da177e4 1995 struct rtl8169_private *tp;
ccdffb9a 1996 struct mii_if_info *mii;
4ff96fa6
FR		 1997 struct net_device *dev;
1998 void __iomem *ioaddr;
07d3f51f
FR		 1999 unsigned int i;
2000 int rc;
1da177e4 2001
4ff96fa6
FR		 2002 if (netif_msg_drv(&debug)) {
2003 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2004 MODULENAME, RTL8169_VERSION);
2005 }
1da177e4 2006
1da177e4 2007 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2008 if (!dev) {
b57b7e5a 2009 if (netif_msg_drv(&debug))
9b91cf9d 2010 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2011 rc = -ENOMEM;
2012 goto out;
1da177e4
LT		 2013 }
2014
1da177e4
LT		 2015 SET_NETDEV_DEV(dev, &pdev->dev);
2016 tp = netdev_priv(dev);
c4028958 2017 tp->dev = dev;
21e197f2 2018 tp->pci_dev = pdev;
b57b7e5a 2019 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 2020
ccdffb9a
FR		 2021 mii = &tp->mii;
2022 mii->dev = dev;
2023 mii->mdio_read = rtl_mdio_read;
2024 mii->mdio_write = rtl_mdio_write;
2025 mii->phy_id_mask = 0x1f;
2026 mii->reg_num_mask = 0x1f;
2027 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2028
1da177e4
LT		 2029 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2030 rc = pci_enable_device(pdev);
b57b7e5a 2031 if (rc < 0) {
2e8a538d 2032 if (netif_msg_probe(tp))
9b91cf9d 2033 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 2034 goto err_out_free_dev_1;
1da177e4
LT		 2035 }
2036
2037 rc = pci_set_mwi(pdev);
2038 if (rc < 0)
4ff96fa6 2039 goto err_out_disable_2;
1da177e4 2040
1da177e4 2041 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2042 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 2043 if (netif_msg_probe(tp)) {
9b91cf9d 2044 dev_err(&pdev->dev,
bcf0bf90
FR		 2045 "region #%d not an MMIO resource, aborting\n",
2046 region);
4ff96fa6 2047 }
1da177e4 2048 rc = -ENODEV;
4ff96fa6 2049 goto err_out_mwi_3;
1da177e4 2050 }
4ff96fa6 2051
1da177e4 2052 /* check for weird/broken PCI region reporting */
bcf0bf90 2053 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 2054 if (netif_msg_probe(tp)) {
9b91cf9d 2055 dev_err(&pdev->dev,
4ff96fa6
FR		 2056 "Invalid PCI region size(s), aborting\n");
2057 }
1da177e4 2058 rc = -ENODEV;
4ff96fa6 2059 goto err_out_mwi_3;
1da177e4
LT		 2060 }
2061
2062 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2063 if (rc < 0) {
2e8a538d 2064 if (netif_msg_probe(tp))
9b91cf9d 2065 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 2066 goto err_out_mwi_3;
1da177e4
LT		 2067 }
2068
2069 tp->cp_cmd = PCIMulRW | RxChkSum;
2070
2071 if ((sizeof(dma_addr_t) > 4) &&
2072 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
2073 tp->cp_cmd |= PCIDAC;
2074 dev->features |= NETIF_F_HIGHDMA;
2075 } else {
2076 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2077 if (rc < 0) {
4ff96fa6 2078 if (netif_msg_probe(tp)) {
9b91cf9d 2079 dev_err(&pdev->dev,
4ff96fa6
FR		 2080 "DMA configuration failed.\n");
2081 }
2082 goto err_out_free_res_4;
1da177e4
LT		 2083 }
2084 }
2085
2086 pci_set_master(pdev);
2087
2088 /* ioremap MMIO region */
bcf0bf90 2089 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2090 if (!ioaddr) {
b57b7e5a 2091 if (netif_msg_probe(tp))
9b91cf9d 2092 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2093 rc = -EIO;
4ff96fa6 2094 goto err_out_free_res_4;
1da177e4
LT		 2095 }
2096
9c14ceaf
FR		 2097 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2098 if (!tp->pcie_cap && netif_msg_probe(tp))
2099 dev_info(&pdev->dev, "no PCI Express capability\n");
2100
1da177e4
LT		 2101 /* Unneeded ? Don't mess with Mrs. Murphy. */
2102 rtl8169_irq_mask_and_ack(ioaddr);
2103
2104 /* Soft reset the chip. */
2105 RTL_W8(ChipCmd, CmdReset);
2106
2107 /* Check that the chip has finished the reset. */
07d3f51f 2108 for (i = 0; i < 100; i++) {
1da177e4
LT		 2109 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2110 break;
b518fa8e 2111 msleep_interruptible(1);
1da177e4
LT		 2112 }
2113
2114 /* Identify chip attached to board */
2115 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 2116
2117 rtl8169_print_mac_version(tp);
1da177e4 2118
cee60c37 2119 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2120 if (tp->mac_version == rtl_chip_info[i].mac_version)
2121 break;
2122 }
cee60c37 2123 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 2124 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 2125 if (netif_msg_probe(tp)) {
2e8a538d 2126 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 2127 "unknown chip version, assuming %s\n",
2128 rtl_chip_info[0].name);
b57b7e5a 2129 }
cee60c37 2130 i = 0;
1da177e4
LT		 2131 }
2132 tp->chipset = i;
2133
5d06a99f
FR		 2134 RTL_W8(Cfg9346, Cfg9346_Unlock);
2135 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2136 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2137 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2138 tp->features |= RTL_FEATURE_WOL;
2139 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2140 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2141 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2142 RTL_W8(Cfg9346, Cfg9346_Lock);
2143
66ec5d4f
FR		 2144 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2145 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2146 tp->set_speed = rtl8169_set_speed_tbi;
2147 tp->get_settings = rtl8169_gset_tbi;
2148 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2149 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2150 tp->link_ok = rtl8169_tbi_link_ok;
2151
64e4bfb4 2152 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2153 } else {
2154 tp->set_speed = rtl8169_set_speed_xmii;
2155 tp->get_settings = rtl8169_gset_xmii;
2156 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2157 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2158 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 2159
2160 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 2161 }
2162
df58ef51
FR		 2163 spin_lock_init(&tp->lock);
2164
738e1e69
PV		 2165 tp->mmio_addr = ioaddr;
2166
7bf6bf48
IV		 2167 rtl_init_mac_address(tp, ioaddr);
2168
2169 /* Get MAC address */
1da177e4
LT		 2170 for (i = 0; i < MAC_ADDR_LEN; i++)
2171 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2172 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 2173
2174 dev->open = rtl8169_open;
2175 dev->hard_start_xmit = rtl8169_start_xmit;
2176 dev->get_stats = rtl8169_get_stats;
2177 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2178 dev->stop = rtl8169_close;
2179 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 2180 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 2181 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2182 dev->irq = pdev->irq;
2183 dev->base_addr = (unsigned long) ioaddr;
2184 dev->change_mtu = rtl8169_change_mtu;
773d2021 2185 dev->set_mac_address = rtl_set_mac_address;
1da177e4 2186
bea3348e 2187 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2188
2189#ifdef CONFIG_R8169_VLAN
2190 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2191 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 2192#endif
2193
2194#ifdef CONFIG_NET_POLL_CONTROLLER
2195 dev->poll_controller = rtl8169_netpoll;
2196#endif
2197
2198 tp->intr_mask = 0xffff;
0e485150
FR		 2199 tp->align = cfg->align;
2200 tp->hw_start = cfg->hw_start;
2201 tp->intr_event = cfg->intr_event;
2202 tp->napi_event = cfg->napi_event;
1da177e4 2203
2efa53f3
FR		 2204 init_timer(&tp->timer);
2205 tp->timer.data = (unsigned long) dev;
2206 tp->timer.function = rtl8169_phy_timer;
2207
1da177e4 2208 rc = register_netdev(dev);
4ff96fa6 2209 if (rc < 0)
fbac58fc 2210 goto err_out_msi_5;
1da177e4
LT		 2211
2212 pci_set_drvdata(pdev, dev);
2213
b57b7e5a 2214 if (netif_msg_probe(tp)) {
96b9709c
FR		 2215 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2216
b57b7e5a
SH		 2217 printk(KERN_INFO "%s: %s at 0x%lx, "
2218 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2219 "XID %08x IRQ %d\n",
b57b7e5a 2220 dev->name,
bcf0bf90 2221 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2222 dev->base_addr,
2223 dev->dev_addr[0], dev->dev_addr[1],
2224 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2225 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2226 }
1da177e4 2227
4ff96fa6 2228 rtl8169_init_phy(dev, tp);
8b76ab39 2229 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2230
4ff96fa6
FR		 2231out:
2232 return rc;
1da177e4 2233
fbac58fc
FR		 2234err_out_msi_5:
2235 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2236 iounmap(ioaddr);
2237err_out_free_res_4:
2238 pci_release_regions(pdev);
2239err_out_mwi_3:
2240 pci_clear_mwi(pdev);
2241err_out_disable_2:
2242 pci_disable_device(pdev);
2243err_out_free_dev_1:
2244 free_netdev(dev);
2245 goto out;
1da177e4
LT		 2246}
2247
07d3f51f 2248static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2249{
2250 struct net_device *dev = pci_get_drvdata(pdev);
2251 struct rtl8169_private *tp = netdev_priv(dev);
2252
eb2a021c
FR		 2253 flush_scheduled_work();
2254
1da177e4 2255 unregister_netdev(dev);
fbac58fc 2256 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2257 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2258 pci_set_drvdata(pdev, NULL);
2259}
2260
1da177e4
LT		 2261static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2262 struct net_device *dev)
2263{
2264 unsigned int mtu = dev->mtu;
2265
2266 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2267}
2268
2269static int rtl8169_open(struct net_device *dev)
2270{
2271 struct rtl8169_private *tp = netdev_priv(dev);
2272 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2273 int retval = -ENOMEM;
1da177e4 2274
1da177e4 2275
99f252b0 2276 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2277
2278 /*
2279 * Rx and Tx desscriptors needs 256 bytes alignment.
2280 * pci_alloc_consistent provides more.
2281 */
2282 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2283 &tp->TxPhyAddr);
2284 if (!tp->TxDescArray)
99f252b0 2285 goto out;
1da177e4
LT		 2286
2287 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2288 &tp->RxPhyAddr);
2289 if (!tp->RxDescArray)
99f252b0 2290 goto err_free_tx_0;
1da177e4
LT		 2291
2292 retval = rtl8169_init_ring(dev);
2293 if (retval < 0)
99f252b0 2294 goto err_free_rx_1;
1da177e4 2295
c4028958 2296 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2297
99f252b0
FR		 2298 smp_mb();
2299
fbac58fc
FR		 2300 retval = request_irq(dev->irq, rtl8169_interrupt,
2301 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2302 dev->name, dev);
2303 if (retval < 0)
2304 goto err_release_ring_2;
2305
bea3348e 2306 napi_enable(&tp->napi);
bea3348e 2307
07ce4064 2308 rtl_hw_start(dev);
1da177e4
LT		 2309
2310 rtl8169_request_timer(dev);
2311
2312 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2313out:
2314 return retval;
2315
99f252b0
FR		 2316err_release_ring_2:
2317 rtl8169_rx_clear(tp);
2318err_free_rx_1:
1da177e4
LT		 2319 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2320 tp->RxPhyAddr);
99f252b0 2321err_free_tx_0:
1da177e4
LT		 2322 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2323 tp->TxPhyAddr);
1da177e4
LT		 2324 goto out;
2325}
2326
2327static void rtl8169_hw_reset(void __iomem *ioaddr)
2328{
2329 /* Disable interrupts */
2330 rtl8169_irq_mask_and_ack(ioaddr);
2331
2332 /* Reset the chipset */
2333 RTL_W8(ChipCmd, CmdReset);
2334
2335 /* PCI commit */
2336 RTL_R8(ChipCmd);
2337}
2338
7f796d83 2339static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2340{
2341 void __iomem *ioaddr = tp->mmio_addr;
2342 u32 cfg = rtl8169_rx_config;
2343
2344 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2345 RTL_W32(RxConfig, cfg);
2346
2347 /* Set DMA burst size and Interframe Gap Time */
2348 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2349 (InterFrameGap << TxInterFrameGapShift));
2350}
2351
07ce4064 2352static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2353{
2354 struct rtl8169_private *tp = netdev_priv(dev);
2355 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2356 unsigned int i;
1da177e4
LT		 2357
2358 /* Soft reset the chip. */
2359 RTL_W8(ChipCmd, CmdReset);
2360
2361 /* Check that the chip has finished the reset. */
07d3f51f 2362 for (i = 0; i < 100; i++) {
1da177e4
LT		 2363 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2364 break;
b518fa8e 2365 msleep_interruptible(1);
1da177e4
LT		 2366 }
2367
07ce4064
FR		 2368 tp->hw_start(dev);
2369
07ce4064
FR		 2370 netif_start_queue(dev);
2371}
2372
2373
7f796d83
FR		 2374static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2375 void __iomem *ioaddr)
2376{
2377 /*
2378 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2379 * register to be written before TxDescAddrLow to work.
2380 * Switching from MMIO to I/O access fixes the issue as well.
2381 */
2382 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2383 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2384 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2385 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2386}
2387
2388static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2389{
2390 u16 cmd;
2391
2392 cmd = RTL_R16(CPlusCmd);
2393 RTL_W16(CPlusCmd, cmd);
2394 return cmd;
2395}
2396
2397static void rtl_set_rx_max_size(void __iomem *ioaddr)
2398{
2399 /* Low hurts. Let's disable the filtering. */
2400 RTL_W16(RxMaxSize, 16383);
2401}
2402
6dccd16b
FR		 2403static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2404{
2405 struct {
2406 u32 mac_version;
2407 u32 clk;
2408 u32 val;
2409 } cfg2_info [] = {
2410 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2411 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2412 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2413 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2414 }, *p = cfg2_info;
2415 unsigned int i;
2416 u32 clk;
2417
2418 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2419 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2420 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2421 RTL_W32(0x7c, p->val);
2422 break;
2423 }
2424 }
2425}
2426
07ce4064
FR		 2427static void rtl_hw_start_8169(struct net_device *dev)
2428{
2429 struct rtl8169_private *tp = netdev_priv(dev);
2430 void __iomem *ioaddr = tp->mmio_addr;
2431 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2432
9cb427b6
FR		 2433 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2434 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2435 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2436 }
2437
1da177e4 2438 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2439 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2440 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2441 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2442 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2443 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2444
1da177e4
LT		 2445 RTL_W8(EarlyTxThres, EarlyTxThld);
2446
7f796d83 2447 rtl_set_rx_max_size(ioaddr);
1da177e4 2448
c946b304
FR		 2449 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2450 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2451 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2452 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2453 rtl_set_rx_tx_config_registers(tp);
1da177e4 2454
7f796d83 2455 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2456
bcf0bf90
FR		 2457 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2458 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2459 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2460 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2461 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2462 }
2463
bcf0bf90
FR		 2464 RTL_W16(CPlusCmd, tp->cp_cmd);
2465
6dccd16b
FR		 2466 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2467
1da177e4
LT		 2468 /*
2469 * Undocumented corner. Supposedly:
2470 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2471 */
2472 RTL_W16(IntrMitigate, 0x0000);
2473
7f796d83 2474 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2475
c946b304
FR		 2476 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2477 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2478 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2479 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2480 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2481 rtl_set_rx_tx_config_registers(tp);
2482 }
2483
1da177e4 2484 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2485
2486 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2487 RTL_R8(IntrMask);
1da177e4
LT		 2488
2489 RTL_W32(RxMissed, 0);
2490
07ce4064 2491 rtl_set_rx_mode(dev);
1da177e4
LT		 2492
2493 /* no early-rx interrupts */
2494 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2495
2496 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2497 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2498}
1da177e4 2499
9c14ceaf 2500static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2501{
9c14ceaf
FR		 2502 struct net_device *dev = pci_get_drvdata(pdev);
2503 struct rtl8169_private *tp = netdev_priv(dev);
2504 int cap = tp->pcie_cap;
2505
2506 if (cap) {
2507 u16 ctl;
458a9f61 2508
9c14ceaf
FR		 2509 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2510 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2511 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2512 }
458a9f61
FR		 2513}
2514
dacf8154
FR		 2515static void rtl_csi_access_enable(void __iomem *ioaddr)
2516{
2517 u32 csi;
2518
2519 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2520 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2521}
2522
2523struct ephy_info {
2524 unsigned int offset;
2525 u16 mask;
2526 u16 bits;
2527};
2528
2529static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2530{
2531 u16 w;
2532
2533 while (len-- > 0) {
2534 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2535 rtl_ephy_write(ioaddr, e->offset, w);
2536 e++;
2537 }
2538}
2539
b726e493
FR		 2540static void rtl_disable_clock_request(struct pci_dev *pdev)
2541{
2542 struct net_device *dev = pci_get_drvdata(pdev);
2543 struct rtl8169_private *tp = netdev_priv(dev);
2544 int cap = tp->pcie_cap;
2545
2546 if (cap) {
2547 u16 ctl;
2548
2549 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2550 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2551 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2552 }
2553}
2554
2555#define R8168_CPCMD_QUIRK_MASK (\
2556 EnableBist | \
2557 Mac_dbgo_oe | \
2558 Force_half_dup | \
2559 Force_rxflow_en | \
2560 Force_txflow_en | \
2561 Cxpl_dbg_sel | \
2562 ASF | \
2563 PktCntrDisable | \
2564 Mac_dbgo_sel)
2565
219a1e9d
FR		 2566static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2567{
b726e493
FR		 2568 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2569
2570 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2571
2e68ae44
FR		 2572 rtl_tx_performance_tweak(pdev,
2573 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2574}
2575
2576static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2577{
2578 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2579
2580 RTL_W8(EarlyTxThres, EarlyTxThld);
2581
2582 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2583}
2584
2585static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2586{
b726e493
FR		 2587 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2588
2589 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2590
219a1e9d 2591 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2592
2593 rtl_disable_clock_request(pdev);
2594
2595 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2596}
2597
ef3386f0 2598static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2599{
b726e493
FR		 2600 static struct ephy_info e_info_8168cp[] = {
2601 { 0x01, 0, 0x0001 },
2602 { 0x02, 0x0800, 0x1000 },
2603 { 0x03, 0, 0x0042 },
2604 { 0x06, 0x0080, 0x0000 },
2605 { 0x07, 0, 0x2000 }
2606 };
2607
2608 rtl_csi_access_enable(ioaddr);
2609
2610 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2611
219a1e9d
FR		 2612 __rtl_hw_start_8168cp(ioaddr, pdev);
2613}
2614
ef3386f0
FR		 2615static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2616{
2617 rtl_csi_access_enable(ioaddr);
2618
2619 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2620
2621 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2622
2623 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2624}
2625
7f3e3d3a
FR		 2626static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2627{
2628 rtl_csi_access_enable(ioaddr);
2629
2630 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2631
2632 /* Magic. */
2633 RTL_W8(DBG_REG, 0x20);
2634
2635 RTL_W8(EarlyTxThres, EarlyTxThld);
2636
2637 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2638
2639 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2640}
2641
219a1e9d
FR		 2642static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2643{
b726e493
FR		 2644 static struct ephy_info e_info_8168c_1[] = {
2645 { 0x02, 0x0800, 0x1000 },
2646 { 0x03, 0, 0x0002 },
2647 { 0x06, 0x0080, 0x0000 }
2648 };
2649
2650 rtl_csi_access_enable(ioaddr);
2651
2652 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2653
2654 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2655
219a1e9d
FR		 2656 __rtl_hw_start_8168cp(ioaddr, pdev);
2657}
2658
2659static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2660{
b726e493
FR		 2661 static struct ephy_info e_info_8168c_2[] = {
2662 { 0x01, 0, 0x0001 },
2663 { 0x03, 0x0400, 0x0220 }
2664 };
2665
2666 rtl_csi_access_enable(ioaddr);
2667
2668 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2669
219a1e9d
FR		 2670 __rtl_hw_start_8168cp(ioaddr, pdev);
2671}
2672
197ff761
FR		 2673static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2674{
2675 rtl_hw_start_8168c_2(ioaddr, pdev);
2676}
2677
6fb07058
FR		 2678static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2679{
2680 rtl_csi_access_enable(ioaddr);
2681
2682 __rtl_hw_start_8168cp(ioaddr, pdev);
2683}
2684
5b538df9
FR		 2685static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2686{
2687 rtl_csi_access_enable(ioaddr);
2688
2689 rtl_disable_clock_request(pdev);
2690
2691 RTL_W8(EarlyTxThres, EarlyTxThld);
2692
2693 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2694
2695 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2696}
2697
07ce4064
FR		 2698static void rtl_hw_start_8168(struct net_device *dev)
2699{
2dd99530
FR		 2700 struct rtl8169_private *tp = netdev_priv(dev);
2701 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2702 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2703
2704 RTL_W8(Cfg9346, Cfg9346_Unlock);
2705
2706 RTL_W8(EarlyTxThres, EarlyTxThld);
2707
2708 rtl_set_rx_max_size(ioaddr);
2709
0e485150 2710 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2711
2712 RTL_W16(CPlusCmd, tp->cp_cmd);
2713
0e485150 2714 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2715
0e485150
FR		 2716 /* Work around for RxFIFO overflow. */
2717 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2718 tp->intr_event |= RxFIFOOver | PCSTimeout;
2719 tp->intr_event &= ~RxOverflow;
2720 }
2721
2722 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2723
b8363901
FR		 2724 rtl_set_rx_mode(dev);
2725
2726 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2727 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2728
2729 RTL_R8(IntrMask);
2730
219a1e9d
FR		 2731 switch (tp->mac_version) {
2732 case RTL_GIGA_MAC_VER_11:
2733 rtl_hw_start_8168bb(ioaddr, pdev);
2734 break;
2735
2736 case RTL_GIGA_MAC_VER_12:
2737 case RTL_GIGA_MAC_VER_17:
2738 rtl_hw_start_8168bef(ioaddr, pdev);
2739 break;
2740
2741 case RTL_GIGA_MAC_VER_18:
ef3386f0 2742 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2743 break;
2744
2745 case RTL_GIGA_MAC_VER_19:
2746 rtl_hw_start_8168c_1(ioaddr, pdev);
2747 break;
2748
2749 case RTL_GIGA_MAC_VER_20:
2750 rtl_hw_start_8168c_2(ioaddr, pdev);
2751 break;
2752
197ff761
FR		 2753 case RTL_GIGA_MAC_VER_21:
2754 rtl_hw_start_8168c_3(ioaddr, pdev);
2755 break;
2756
6fb07058
FR		 2757 case RTL_GIGA_MAC_VER_22:
2758 rtl_hw_start_8168c_4(ioaddr, pdev);
2759 break;
2760
ef3386f0
FR		 2761 case RTL_GIGA_MAC_VER_23:
2762 rtl_hw_start_8168cp_2(ioaddr, pdev);
2763 break;
2764
7f3e3d3a
FR		 2765 case RTL_GIGA_MAC_VER_24:
2766 rtl_hw_start_8168cp_3(ioaddr, pdev);
2767 break;
2768
5b538df9
FR		 2769 case RTL_GIGA_MAC_VER_25:
2770 rtl_hw_start_8168d(ioaddr, pdev);
2771 break;
2772
219a1e9d
FR		 2773 default:
2774 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2775 dev->name, tp->mac_version);
2776 break;
2777 }
2dd99530 2778
0e485150
FR		 2779 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2780
b8363901
FR		 2781 RTL_W8(Cfg9346, Cfg9346_Lock);
2782
2dd99530 2783 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2784
0e485150 2785 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2786}
1da177e4 2787
2857ffb7
FR		 2788#define R810X_CPCMD_QUIRK_MASK (\
2789 EnableBist | \
2790 Mac_dbgo_oe | \
2791 Force_half_dup | \
2792 Force_half_dup | \
2793 Force_txflow_en | \
2794 Cxpl_dbg_sel | \
2795 ASF | \
2796 PktCntrDisable | \
2797 PCIDAC | \
2798 PCIMulRW)
2799
2800static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2801{
2802 static struct ephy_info e_info_8102e_1[] = {
2803 { 0x01, 0, 0x6e65 },
2804 { 0x02, 0, 0x091f },
2805 { 0x03, 0, 0xc2f9 },
2806 { 0x06, 0, 0xafb5 },
2807 { 0x07, 0, 0x0e00 },
2808 { 0x19, 0, 0xec80 },
2809 { 0x01, 0, 0x2e65 },
2810 { 0x01, 0, 0x6e65 }
2811 };
2812 u8 cfg1;
2813
2814 rtl_csi_access_enable(ioaddr);
2815
2816 RTL_W8(DBG_REG, FIX_NAK_1);
2817
2818 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2819
2820 RTL_W8(Config1,
2821 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2822 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2823
2824 cfg1 = RTL_R8(Config1);
2825 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2826 RTL_W8(Config1, cfg1 & ~LEDS0);
2827
2828 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2829
2830 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2831}
2832
2833static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2834{
2835 rtl_csi_access_enable(ioaddr);
2836
2837 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2838
2839 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2840 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2841
2842 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2843}
2844
2845static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2846{
2847 rtl_hw_start_8102e_2(ioaddr, pdev);
2848
2849 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2850}
2851
07ce4064
FR		 2852static void rtl_hw_start_8101(struct net_device *dev)
2853{
cdf1a608
FR		 2854 struct rtl8169_private *tp = netdev_priv(dev);
2855 void __iomem *ioaddr = tp->mmio_addr;
2856 struct pci_dev *pdev = tp->pci_dev;
2857
e3cf0cc0
FR		 2858 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2859 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2860 int cap = tp->pcie_cap;
2861
2862 if (cap) {
2863 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2864 PCI_EXP_DEVCTL_NOSNOOP_EN);
2865 }
cdf1a608
FR		 2866 }
2867
2857ffb7
FR		 2868 switch (tp->mac_version) {
2869 case RTL_GIGA_MAC_VER_07:
2870 rtl_hw_start_8102e_1(ioaddr, pdev);
2871 break;
2872
2873 case RTL_GIGA_MAC_VER_08:
2874 rtl_hw_start_8102e_3(ioaddr, pdev);
2875 break;
2876
2877 case RTL_GIGA_MAC_VER_09:
2878 rtl_hw_start_8102e_2(ioaddr, pdev);
2879 break;
cdf1a608
FR		 2880 }
2881
2882 RTL_W8(Cfg9346, Cfg9346_Unlock);
2883
2884 RTL_W8(EarlyTxThres, EarlyTxThld);
2885
2886 rtl_set_rx_max_size(ioaddr);
2887
2888 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2889
2890 RTL_W16(CPlusCmd, tp->cp_cmd);
2891
2892 RTL_W16(IntrMitigate, 0x0000);
2893
2894 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2895
2896 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2897 rtl_set_rx_tx_config_registers(tp);
2898
2899 RTL_W8(Cfg9346, Cfg9346_Lock);
2900
2901 RTL_R8(IntrMask);
2902
cdf1a608
FR		 2903 rtl_set_rx_mode(dev);
2904
0e485150
FR		 2905 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2906
cdf1a608 2907 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2908
0e485150 2909 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2910}
2911
2912static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2913{
2914 struct rtl8169_private *tp = netdev_priv(dev);
2915 int ret = 0;
2916
2917 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2918 return -EINVAL;
2919
2920 dev->mtu = new_mtu;
2921
2922 if (!netif_running(dev))
2923 goto out;
2924
2925 rtl8169_down(dev);
2926
2927 rtl8169_set_rxbufsize(tp, dev);
2928
2929 ret = rtl8169_init_ring(dev);
2930 if (ret < 0)
2931 goto out;
2932
bea3348e 2933 napi_enable(&tp->napi);
1da177e4 2934
07ce4064 2935 rtl_hw_start(dev);
1da177e4
LT		 2936
2937 rtl8169_request_timer(dev);
2938
2939out:
2940 return ret;
2941}
2942
2943static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2944{
95e0918d 2945 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2946 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2947}
2948
2949static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2950 struct sk_buff **sk_buff, struct RxDesc *desc)
2951{
2952 struct pci_dev *pdev = tp->pci_dev;
2953
2954 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2955 PCI_DMA_FROMDEVICE);
2956 dev_kfree_skb(*sk_buff);
2957 *sk_buff = NULL;
2958 rtl8169_make_unusable_by_asic(desc);
2959}
2960
2961static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2962{
2963 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2964
2965 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2966}
2967
2968static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2969 u32 rx_buf_sz)
2970{
2971 desc->addr = cpu_to_le64(mapping);
2972 wmb();
2973 rtl8169_mark_to_asic(desc, rx_buf_sz);
2974}
2975
15d31758
SH		 2976static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2977 struct net_device *dev,
2978 struct RxDesc *desc, int rx_buf_sz,
2979 unsigned int align)
1da177e4
LT		 2980{
2981 struct sk_buff *skb;
2982 dma_addr_t mapping;
e9f63f30 2983 unsigned int pad;
1da177e4 2984
e9f63f30
FR		 2985 pad = align ? align : NET_IP_ALIGN;
2986
2987 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2988 if (!skb)
2989 goto err_out;
2990
e9f63f30 2991 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2992
689be439 2993 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2994 PCI_DMA_FROMDEVICE);
2995
2996 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2997out:
15d31758 2998 return skb;
1da177e4
LT		 2999
3000err_out:
1da177e4
LT		 3001 rtl8169_make_unusable_by_asic(desc);
3002 goto out;
3003}
3004
3005static void rtl8169_rx_clear(struct rtl8169_private *tp)
3006{
07d3f51f 3007 unsigned int i;
1da177e4
LT		 3008
3009 for (i = 0; i < NUM_RX_DESC; i++) {
3010 if (tp->Rx_skbuff[i]) {
3011 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3012 tp->RxDescArray + i);
3013 }
3014 }
3015}
3016
3017static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3018 u32 start, u32 end)
3019{
3020 u32 cur;
5b0384f4 3021
4ae47c2d 3022 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 3023 struct sk_buff *skb;
3024 unsigned int i = cur % NUM_RX_DESC;
1da177e4 3025
4ae47c2d
FR		 3026 WARN_ON((s32)(end - cur) < 0);
3027
1da177e4
LT		 3028 if (tp->Rx_skbuff[i])
3029 continue;
bcf0bf90 3030
15d31758
SH		 3031 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3032 tp->RxDescArray + i,
3033 tp->rx_buf_sz, tp->align);
3034 if (!skb)
1da177e4 3035 break;
15d31758
SH		 3036
3037 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 3038 }
3039 return cur - start;
3040}
3041
3042static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3043{
3044 desc->opts1 |= cpu_to_le32(RingEnd);
3045}
3046
3047static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3048{
3049 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3050}
3051
3052static int rtl8169_init_ring(struct net_device *dev)
3053{
3054 struct rtl8169_private *tp = netdev_priv(dev);
3055
3056 rtl8169_init_ring_indexes(tp);
3057
3058 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3059 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3060
3061 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3062 goto err_out;
3063
3064 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3065
3066 return 0;
3067
3068err_out:
3069 rtl8169_rx_clear(tp);
3070 return -ENOMEM;
3071}
3072
3073static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3074 struct TxDesc *desc)
3075{
3076 unsigned int len = tx_skb->len;
3077
3078 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3079 desc->opts1 = 0x00;
3080 desc->opts2 = 0x00;
3081 desc->addr = 0x00;
3082 tx_skb->len = 0;
3083}
3084
3085static void rtl8169_tx_clear(struct rtl8169_private *tp)
3086{
3087 unsigned int i;
3088
3089 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3090 unsigned int entry = i % NUM_TX_DESC;
3091 struct ring_info *tx_skb = tp->tx_skb + entry;
3092 unsigned int len = tx_skb->len;
3093
3094 if (len) {
3095 struct sk_buff *skb = tx_skb->skb;
3096
3097 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3098 tp->TxDescArray + entry);
3099 if (skb) {
3100 dev_kfree_skb(skb);
3101 tx_skb->skb = NULL;
3102 }
cebf8cc7 3103 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3104 }
3105 }
3106 tp->cur_tx = tp->dirty_tx = 0;
3107}
3108
c4028958 3109static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3110{
3111 struct rtl8169_private *tp = netdev_priv(dev);
3112
c4028958 3113 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3114 schedule_delayed_work(&tp->task, 4);
3115}
3116
3117static void rtl8169_wait_for_quiescence(struct net_device *dev)
3118{
3119 struct rtl8169_private *tp = netdev_priv(dev);
3120 void __iomem *ioaddr = tp->mmio_addr;
3121
3122 synchronize_irq(dev->irq);
3123
3124 /* Wait for any pending NAPI task to complete */
bea3348e 3125 napi_disable(&tp->napi);
1da177e4
LT		 3126
3127 rtl8169_irq_mask_and_ack(ioaddr);
3128
d1d08d12
DM		 3129 tp->intr_mask = 0xffff;
3130 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3131 napi_enable(&tp->napi);
1da177e4
LT		 3132}
3133
c4028958 3134static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3135{
c4028958
DH		 3136 struct rtl8169_private *tp =
3137 container_of(work, struct rtl8169_private, task.work);
3138 struct net_device *dev = tp->dev;
1da177e4
LT		 3139 int ret;
3140
eb2a021c
FR		 3141 rtnl_lock();
3142
3143 if (!netif_running(dev))
3144 goto out_unlock;
3145
3146 rtl8169_wait_for_quiescence(dev);
3147 rtl8169_close(dev);
1da177e4
LT		 3148
3149 ret = rtl8169_open(dev);
3150 if (unlikely(ret < 0)) {
07d3f51f 3151 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3152 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3153 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3154 }
3155 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3156 }
eb2a021c
FR		 3157
3158out_unlock:
3159 rtnl_unlock();
1da177e4
LT		 3160}
3161
c4028958 3162static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3163{
c4028958
DH		 3164 struct rtl8169_private *tp =
3165 container_of(work, struct rtl8169_private, task.work);
3166 struct net_device *dev = tp->dev;
1da177e4 3167
eb2a021c
FR		 3168 rtnl_lock();
3169
1da177e4 3170 if (!netif_running(dev))
eb2a021c 3171 goto out_unlock;
1da177e4
LT		 3172
3173 rtl8169_wait_for_quiescence(dev);
3174
bea3348e 3175 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3176 rtl8169_tx_clear(tp);
3177
3178 if (tp->dirty_rx == tp->cur_rx) {
3179 rtl8169_init_ring_indexes(tp);
07ce4064 3180 rtl_hw_start(dev);
1da177e4 3181 netif_wake_queue(dev);
cebf8cc7 3182 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3183 } else {
07d3f51f 3184 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3185 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3186 dev->name);
1da177e4
LT		 3187 }
3188 rtl8169_schedule_work(dev, rtl8169_reset_task);
3189 }
eb2a021c
FR		 3190
3191out_unlock:
3192 rtnl_unlock();
1da177e4
LT		 3193}
3194
3195static void rtl8169_tx_timeout(struct net_device *dev)
3196{
3197 struct rtl8169_private *tp = netdev_priv(dev);
3198
3199 rtl8169_hw_reset(tp->mmio_addr);
3200
3201 /* Let's wait a bit while any (async) irq lands on */
3202 rtl8169_schedule_work(dev, rtl8169_reset_task);
3203}
3204
3205static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3206 u32 opts1)
3207{
3208 struct skb_shared_info *info = skb_shinfo(skb);
3209 unsigned int cur_frag, entry;
a6343afb 3210 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3211
3212 entry = tp->cur_tx;
3213 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3214 skb_frag_t *frag = info->frags + cur_frag;
3215 dma_addr_t mapping;
3216 u32 status, len;
3217 void *addr;
3218
3219 entry = (entry + 1) % NUM_TX_DESC;
3220
3221 txd = tp->TxDescArray + entry;
3222 len = frag->size;
3223 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3224 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3225
3226 /* anti gcc 2.95.3 bugware (sic) */
3227 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3228
3229 txd->opts1 = cpu_to_le32(status);
3230 txd->addr = cpu_to_le64(mapping);
3231
3232 tp->tx_skb[entry].len = len;
3233 }
3234
3235 if (cur_frag) {
3236 tp->tx_skb[entry].skb = skb;
3237 txd->opts1 |= cpu_to_le32(LastFrag);
3238 }
3239
3240 return cur_frag;
3241}
3242
3243static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3244{
3245 if (dev->features & NETIF_F_TSO) {
7967168c 3246 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3247
3248 if (mss)
3249 return LargeSend | ((mss & MSSMask) << MSSShift);
3250 }
84fa7933 3251 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3252 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3253
3254 if (ip->protocol == IPPROTO_TCP)
3255 return IPCS | TCPCS;
3256 else if (ip->protocol == IPPROTO_UDP)
3257 return IPCS | UDPCS;
3258 WARN_ON(1); /* we need a WARN() */
3259 }
3260 return 0;
3261}
3262
3263static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3264{
3265 struct rtl8169_private *tp = netdev_priv(dev);
3266 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3267 struct TxDesc *txd = tp->TxDescArray + entry;
3268 void __iomem *ioaddr = tp->mmio_addr;
3269 dma_addr_t mapping;
3270 u32 status, len;
3271 u32 opts1;
188f4af0 3272 int ret = NETDEV_TX_OK;
5b0384f4 3273
1da177e4 3274 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3275 if (netif_msg_drv(tp)) {
3276 printk(KERN_ERR
3277 "%s: BUG! Tx Ring full when queue awake!\n",
3278 dev->name);
3279 }
1da177e4
LT		 3280 goto err_stop;
3281 }
3282
3283 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3284 goto err_stop;
3285
3286 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3287
3288 frags = rtl8169_xmit_frags(tp, skb, opts1);
3289 if (frags) {
3290 len = skb_headlen(skb);
3291 opts1 |= FirstFrag;
3292 } else {
3293 len = skb->len;
3294
3295 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 3296 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 3297 goto err_update_stats;
3298 len = ETH_ZLEN;
3299 }
3300
3301 opts1 |= FirstFrag | LastFrag;
3302 tp->tx_skb[entry].skb = skb;
3303 }
3304
3305 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3306
3307 tp->tx_skb[entry].len = len;
3308 txd->addr = cpu_to_le64(mapping);
3309 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3310
3311 wmb();
3312
3313 /* anti gcc 2.95.3 bugware (sic) */
3314 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3315 txd->opts1 = cpu_to_le32(status);
3316
3317 dev->trans_start = jiffies;
3318
3319 tp->cur_tx += frags + 1;
3320
3321 smp_wmb();
3322
275391a4 3323 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3324
3325 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3326 netif_stop_queue(dev);
3327 smp_rmb();
3328 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3329 netif_wake_queue(dev);
3330 }
3331
3332out:
3333 return ret;
3334
3335err_stop:
3336 netif_stop_queue(dev);
188f4af0 3337 ret = NETDEV_TX_BUSY;
1da177e4 3338err_update_stats:
cebf8cc7 3339 dev->stats.tx_dropped++;
1da177e4
LT		 3340 goto out;
3341}
3342
3343static void rtl8169_pcierr_interrupt(struct net_device *dev)
3344{
3345 struct rtl8169_private *tp = netdev_priv(dev);
3346 struct pci_dev *pdev = tp->pci_dev;
3347 void __iomem *ioaddr = tp->mmio_addr;
3348 u16 pci_status, pci_cmd;
3349
3350 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3351 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3352
b57b7e5a
SH		 3353 if (netif_msg_intr(tp)) {
3354 printk(KERN_ERR
3355 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3356 dev->name, pci_cmd, pci_status);
3357 }
1da177e4
LT		 3358
3359 /*
3360 * The recovery sequence below admits a very elaborated explanation:
3361 * - it seems to work;
d03902b8
FR		 3362 * - I did not see what else could be done;
3363 * - it makes iop3xx happy.
1da177e4
LT		 3364 *
3365 * Feel free to adjust to your needs.
3366 */
a27993f3 3367 if (pdev->broken_parity_status)
d03902b8
FR		 3368 pci_cmd &= ~PCI_COMMAND_PARITY;
3369 else
3370 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3371
3372 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3373
3374 pci_write_config_word(pdev, PCI_STATUS,
3375 pci_status & (PCI_STATUS_DETECTED_PARITY |
3376 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3377 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3378
3379 /* The infamous DAC f*ckup only happens at boot time */
3380 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3381 if (netif_msg_intr(tp))
3382 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3383 tp->cp_cmd &= ~PCIDAC;
3384 RTL_W16(CPlusCmd, tp->cp_cmd);
3385 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3386 }
3387
3388 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3389
3390 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3391}
3392
07d3f51f
FR		 3393static void rtl8169_tx_interrupt(struct net_device *dev,
3394 struct rtl8169_private *tp,
3395 void __iomem *ioaddr)
1da177e4
LT		 3396{
3397 unsigned int dirty_tx, tx_left;
3398
1da177e4
LT		 3399 dirty_tx = tp->dirty_tx;
3400 smp_rmb();
3401 tx_left = tp->cur_tx - dirty_tx;
3402
3403 while (tx_left > 0) {
3404 unsigned int entry = dirty_tx % NUM_TX_DESC;
3405 struct ring_info *tx_skb = tp->tx_skb + entry;
3406 u32 len = tx_skb->len;
3407 u32 status;
3408
3409 rmb();
3410 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3411 if (status & DescOwn)
3412 break;
3413
cebf8cc7
FR		 3414 dev->stats.tx_bytes += len;
3415 dev->stats.tx_packets++;
1da177e4
LT		 3416
3417 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3418
3419 if (status & LastFrag) {
3420 dev_kfree_skb_irq(tx_skb->skb);
3421 tx_skb->skb = NULL;
3422 }
3423 dirty_tx++;
3424 tx_left--;
3425 }
3426
3427 if (tp->dirty_tx != dirty_tx) {
3428 tp->dirty_tx = dirty_tx;
3429 smp_wmb();
3430 if (netif_queue_stopped(dev) &&
3431 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3432 netif_wake_queue(dev);
3433 }
d78ae2dc
FR		 3434 /*
3435 * 8168 hack: TxPoll requests are lost when the Tx packets are
3436 * too close. Let's kick an extra TxPoll request when a burst
3437 * of start_xmit activity is detected (if it is not detected,
3438 * it is slow enough). -- FR
3439 */
3440 smp_rmb();
3441 if (tp->cur_tx != dirty_tx)
3442 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3443 }
3444}
3445
126fa4b9
FR		 3446static inline int rtl8169_fragmented_frame(u32 status)
3447{
3448 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3449}
3450
1da177e4
LT		 3451static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3452{
3453 u32 opts1 = le32_to_cpu(desc->opts1);
3454 u32 status = opts1 & RxProtoMask;
3455
3456 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3457 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3458 ((status == RxProtoIP) && !(opts1 & IPFail)))
3459 skb->ip_summed = CHECKSUM_UNNECESSARY;
3460 else
3461 skb->ip_summed = CHECKSUM_NONE;
3462}
3463
07d3f51f
FR		 3464static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3465 struct rtl8169_private *tp, int pkt_size,
3466 dma_addr_t addr)
1da177e4 3467{
b449655f
SH		 3468 struct sk_buff *skb;
3469 bool done = false;
1da177e4 3470
b449655f
SH		 3471 if (pkt_size >= rx_copybreak)
3472 goto out;
1da177e4 3473
07d3f51f 3474 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3475 if (!skb)
3476 goto out;
3477
07d3f51f
FR		 3478 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3479 PCI_DMA_FROMDEVICE);
86402234 3480 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3481 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3482 *sk_buff = skb;
3483 done = true;
3484out:
3485 return done;
1da177e4
LT		 3486}
3487
07d3f51f
FR		 3488static int rtl8169_rx_interrupt(struct net_device *dev,
3489 struct rtl8169_private *tp,
bea3348e 3490 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3491{
3492 unsigned int cur_rx, rx_left;
3493 unsigned int delta, count;
3494
1da177e4
LT		 3495 cur_rx = tp->cur_rx;
3496 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3497 rx_left = min(rx_left, budget);
1da177e4 3498
4dcb7d33 3499 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3500 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3501 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3502 u32 status;
3503
3504 rmb();
126fa4b9 3505 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3506
3507 if (status & DescOwn)
3508 break;
4dcb7d33 3509 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3510 if (netif_msg_rx_err(tp)) {
3511 printk(KERN_INFO
3512 "%s: Rx ERROR. status = %08x\n",
3513 dev->name, status);
3514 }
cebf8cc7 3515 dev->stats.rx_errors++;
1da177e4 3516 if (status & (RxRWT | RxRUNT))
cebf8cc7 3517 dev->stats.rx_length_errors++;
1da177e4 3518 if (status & RxCRC)
cebf8cc7 3519 dev->stats.rx_crc_errors++;
9dccf611
FR		 3520 if (status & RxFOVF) {
3521 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3522 dev->stats.rx_fifo_errors++;
9dccf611 3523 }
126fa4b9 3524 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3525 } else {
1da177e4 3526 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3527 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3528 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3529 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3530
126fa4b9
FR		 3531 /*
3532 * The driver does not support incoming fragmented
3533 * frames. They are seen as a symptom of over-mtu
3534 * sized frames.
3535 */
3536 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3537 dev->stats.rx_dropped++;
3538 dev->stats.rx_length_errors++;
126fa4b9 3539 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3540 continue;
126fa4b9
FR		 3541 }
3542
1da177e4 3543 rtl8169_rx_csum(skb, desc);
bcf0bf90 3544
07d3f51f 3545 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3546 pci_dma_sync_single_for_device(pdev, addr,
3547 pkt_size, PCI_DMA_FROMDEVICE);
3548 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3549 } else {
a866bbf6 3550 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3551 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3552 tp->Rx_skbuff[entry] = NULL;
3553 }
3554
1da177e4
LT		 3555 skb_put(skb, pkt_size);
3556 skb->protocol = eth_type_trans(skb, dev);
3557
3558 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3559 netif_receive_skb(skb);
1da177e4
LT		 3560
3561 dev->last_rx = jiffies;
cebf8cc7
FR		 3562 dev->stats.rx_bytes += pkt_size;
3563 dev->stats.rx_packets++;
1da177e4 3564 }
6dccd16b
FR		 3565
3566 /* Work around for AMD plateform. */
95e0918d 3567 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3568 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3569 desc->opts2 = 0;
3570 cur_rx++;
3571 }
1da177e4
LT		 3572 }
3573
3574 count = cur_rx - tp->cur_rx;
3575 tp->cur_rx = cur_rx;
3576
3577 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3578 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3579 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3580 tp->dirty_rx += delta;
3581
3582 /*
3583 * FIXME: until there is periodic timer to try and refill the ring,
3584 * a temporary shortage may definitely kill the Rx process.
3585 * - disable the asic to try and avoid an overflow and kick it again
3586 * after refill ?
3587 * - how do others driver handle this condition (Uh oh...).
3588 */
b57b7e5a 3589 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3590 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3591
3592 return count;
3593}
3594
07d3f51f 3595static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3596{
07d3f51f 3597 struct net_device *dev = dev_instance;
1da177e4 3598 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3599 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3600 int handled = 0;
865c652d 3601 int status;
1da177e4 3602
865c652d 3603 status = RTL_R16(IntrStatus);
1da177e4 3604
865c652d
FR		 3605 /* hotplug/major error/no more work/shared irq */
3606 if ((status == 0xffff) || !status)
3607 goto out;
1da177e4 3608
865c652d 3609 handled = 1;
1da177e4 3610
865c652d
FR		 3611 if (unlikely(!netif_running(dev))) {
3612 rtl8169_asic_down(ioaddr);
3613 goto out;
3614 }
1da177e4 3615
865c652d
FR		 3616 status &= tp->intr_mask;
3617 RTL_W16(IntrStatus,
3618 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3619
865c652d
FR		 3620 if (!(status & tp->intr_event))
3621 goto out;
0e485150 3622
865c652d
FR		 3623 /* Work around for rx fifo overflow */
3624 if (unlikely(status & RxFIFOOver) &&
3625 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3626 netif_stop_queue(dev);
3627 rtl8169_tx_timeout(dev);
3628 goto out;
3629 }
1da177e4 3630
865c652d
FR		 3631 if (unlikely(status & SYSErr)) {
3632 rtl8169_pcierr_interrupt(dev);
3633 goto out;
3634 }
1da177e4 3635
865c652d
FR		 3636 if (status & LinkChg)
3637 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3638
865c652d
FR		 3639 if (status & tp->napi_event) {
3640 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3641 tp->intr_mask = ~tp->napi_event;
313b0305 3642
bea3348e
SH		 3643 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3644 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 3645 else if (netif_msg_intr(tp)) {
3646 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3647 dev->name, status);
b57b7e5a 3648 }
1da177e4
LT		 3649 }
3650out:
3651 return IRQ_RETVAL(handled);
3652}
3653
bea3348e 3654static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3655{
bea3348e
SH		 3656 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3657 struct net_device *dev = tp->dev;
1da177e4 3658 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3659 int work_done;
1da177e4 3660
bea3348e 3661 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3662 rtl8169_tx_interrupt(dev, tp, ioaddr);
3663
bea3348e
SH		 3664 if (work_done < budget) {
3665 netif_rx_complete(dev, napi);
1da177e4
LT		 3666 tp->intr_mask = 0xffff;
3667 /*
3668 * 20040426: the barrier is not strictly required but the
3669 * behavior of the irq handler could be less predictable
3670 * without it. Btw, the lack of flush for the posted pci
3671 * write is safe - FR
3672 */
3673 smp_wmb();
0e485150 3674 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3675 }
3676
bea3348e 3677 return work_done;
1da177e4 3678}
1da177e4 3679
523a6094
FR		 3680static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3681{
3682 struct rtl8169_private *tp = netdev_priv(dev);
3683
3684 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3685 return;
3686
3687 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3688 RTL_W32(RxMissed, 0);
3689}
3690
1da177e4
LT		 3691static void rtl8169_down(struct net_device *dev)
3692{
3693 struct rtl8169_private *tp = netdev_priv(dev);
3694 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3695 unsigned int intrmask;
1da177e4
LT		 3696
3697 rtl8169_delete_timer(dev);
3698
3699 netif_stop_queue(dev);
3700
93dd79e8 3701 napi_disable(&tp->napi);
93dd79e8 3702
1da177e4
LT		 3703core_down:
3704 spin_lock_irq(&tp->lock);
3705
3706 rtl8169_asic_down(ioaddr);
3707
523a6094 3708 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3709
3710 spin_unlock_irq(&tp->lock);
3711
3712 synchronize_irq(dev->irq);
3713
1da177e4 3714 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3715 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3716
3717 /*
3718 * And now for the 50k$ question: are IRQ disabled or not ?
3719 *
3720 * Two paths lead here:
3721 * 1) dev->close
3722 * -> netif_running() is available to sync the current code and the
3723 * IRQ handler. See rtl8169_interrupt for details.
3724 * 2) dev->change_mtu
3725 * -> rtl8169_poll can not be issued again and re-enable the
3726 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3727 *
3728 * No loop if hotpluged or major error (0xffff).
1da177e4 3729 */
733b736c
AP		 3730 intrmask = RTL_R16(IntrMask);
3731 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3732 goto core_down;
3733
3734 rtl8169_tx_clear(tp);
3735
3736 rtl8169_rx_clear(tp);
3737}
3738
3739static int rtl8169_close(struct net_device *dev)
3740{
3741 struct rtl8169_private *tp = netdev_priv(dev);
3742 struct pci_dev *pdev = tp->pci_dev;
3743
3744 rtl8169_down(dev);
3745
3746 free_irq(dev->irq, dev);
3747
1da177e4
LT		 3748 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3749 tp->RxPhyAddr);
3750 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3751 tp->TxPhyAddr);
3752 tp->TxDescArray = NULL;
3753 tp->RxDescArray = NULL;
3754
3755 return 0;
3756}
3757
07ce4064 3758static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3759{
3760 struct rtl8169_private *tp = netdev_priv(dev);
3761 void __iomem *ioaddr = tp->mmio_addr;
3762 unsigned long flags;
3763 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3764 int rx_mode;
1da177e4
LT		 3765 u32 tmp = 0;
3766
3767 if (dev->flags & IFF_PROMISC) {
3768 /* Unconditionally log net taps. */
b57b7e5a
SH		 3769 if (netif_msg_link(tp)) {
3770 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3771 dev->name);
3772 }
1da177e4
LT		 3773 rx_mode =
3774 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3775 AcceptAllPhys;
3776 mc_filter[1] = mc_filter[0] = 0xffffffff;
3777 } else if ((dev->mc_count > multicast_filter_limit)
3778 || (dev->flags & IFF_ALLMULTI)) {
3779 /* Too many to filter perfectly -- accept all multicasts. */
3780 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3781 mc_filter[1] = mc_filter[0] = 0xffffffff;
3782 } else {
3783 struct dev_mc_list *mclist;
07d3f51f
FR		 3784 unsigned int i;
3785
1da177e4
LT		 3786 rx_mode = AcceptBroadcast | AcceptMyPhys;
3787 mc_filter[1] = mc_filter[0] = 0;
3788 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3789 i++, mclist = mclist->next) {
3790 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3791 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3792 rx_mode |= AcceptMulticast;
3793 }
3794 }
3795
3796 spin_lock_irqsave(&tp->lock, flags);
3797
3798 tmp = rtl8169_rx_config | rx_mode |
3799 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3800
f887cce8 3801 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3802 u32 data = mc_filter[0];
3803
3804 mc_filter[0] = swab32(mc_filter[1]);
3805 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3806 }
3807
1da177e4
LT		 3808 RTL_W32(MAR0 + 0, mc_filter[0]);
3809 RTL_W32(MAR0 + 4, mc_filter[1]);
3810
57a9f236
FR		 3811 RTL_W32(RxConfig, tmp);
3812
1da177e4
LT		 3813 spin_unlock_irqrestore(&tp->lock, flags);
3814}
3815
3816/**
3817 * rtl8169_get_stats - Get rtl8169 read/write statistics
3818 * @dev: The Ethernet Device to get statistics for
3819 *
3820 * Get TX/RX statistics for rtl8169
3821 */
3822static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3823{
3824 struct rtl8169_private *tp = netdev_priv(dev);
3825 void __iomem *ioaddr = tp->mmio_addr;
3826 unsigned long flags;
3827
3828 if (netif_running(dev)) {
3829 spin_lock_irqsave(&tp->lock, flags);
523a6094 3830 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3831 spin_unlock_irqrestore(&tp->lock, flags);
3832 }
5b0384f4 3833
cebf8cc7 3834 return &dev->stats;
1da177e4
LT		 3835}
3836
5d06a99f
FR		 3837#ifdef CONFIG_PM
3838
3839static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3840{
3841 struct net_device *dev = pci_get_drvdata(pdev);
3842 struct rtl8169_private *tp = netdev_priv(dev);
3843 void __iomem *ioaddr = tp->mmio_addr;
3844
3845 if (!netif_running(dev))
1371fa6d 3846 goto out_pci_suspend;
5d06a99f
FR		 3847
3848 netif_device_detach(dev);
3849 netif_stop_queue(dev);
3850
3851 spin_lock_irq(&tp->lock);
3852
3853 rtl8169_asic_down(ioaddr);
3854
523a6094 3855 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3856
3857 spin_unlock_irq(&tp->lock);
3858
1371fa6d 3859out_pci_suspend:
5d06a99f 3860 pci_save_state(pdev);
f23e7fda
FR		 3861 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3862 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3863 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3864
5d06a99f
FR		 3865 return 0;
3866}
3867
3868static int rtl8169_resume(struct pci_dev *pdev)
3869{
3870 struct net_device *dev = pci_get_drvdata(pdev);
3871
1371fa6d
FR		 3872 pci_set_power_state(pdev, PCI_D0);
3873 pci_restore_state(pdev);
3874 pci_enable_wake(pdev, PCI_D0, 0);
3875
5d06a99f
FR		 3876 if (!netif_running(dev))
3877 goto out;
3878
3879 netif_device_attach(dev);
3880
5d06a99f
FR		 3881 rtl8169_schedule_work(dev, rtl8169_reset_task);
3882out:
3883 return 0;
3884}
3885
1765f95d
FR		 3886static void rtl_shutdown(struct pci_dev *pdev)
3887{
3888 rtl8169_suspend(pdev, PMSG_SUSPEND);
3889}
3890
5d06a99f
FR		 3891#endif /* CONFIG_PM */
3892
1da177e4
LT		 3893static struct pci_driver rtl8169_pci_driver = {
3894 .name = MODULENAME,
3895 .id_table = rtl8169_pci_tbl,
3896 .probe = rtl8169_init_one,
3897 .remove = __devexit_p(rtl8169_remove_one),
3898#ifdef CONFIG_PM
3899 .suspend = rtl8169_suspend,
3900 .resume = rtl8169_resume,
1765f95d 3901 .shutdown = rtl_shutdown,
1da177e4
LT		 3902#endif
3903};
3904
07d3f51f 3905static int __init rtl8169_init_module(void)
1da177e4 3906{
29917620 3907 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3908}
3909
07d3f51f 3910static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3911{
3912 pci_unregister_driver(&rtl8169_pci_driver);
3913}
3914
3915module_init(rtl8169_init_module);
3916module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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