Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | ========================================================================= | |
3 | r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x. | |
4 | -------------------------------------------------------------------- | |
5 | ||
6 | History: | |
7 | Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>. | |
8 | May 20 2002 - Add link status force-mode and TBI mode support. | |
5b0384f4 | 9 | 2004 - Massive updates. See kernel SCM system for details. |
1da177e4 LT |
10 | ========================================================================= |
11 | 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes. | |
12 | Command: 'insmod r8169 media = SET_MEDIA' | |
13 | Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex. | |
5b0384f4 | 14 | |
1da177e4 LT |
15 | SET_MEDIA can be: |
16 | _10_Half = 0x01 | |
17 | _10_Full = 0x02 | |
18 | _100_Half = 0x04 | |
19 | _100_Full = 0x08 | |
20 | _1000_Full = 0x10 | |
5b0384f4 | 21 | |
1da177e4 LT |
22 | 2. Support TBI mode. |
23 | ========================================================================= | |
24 | VERSION 1.1 <2002/10/4> | |
25 | ||
26 | The bit4:0 of MII register 4 is called "selector field", and have to be | |
27 | 00001b to indicate support of IEEE std 802.3 during NWay process of | |
5b0384f4 | 28 | exchanging Link Code Word (FLP). |
1da177e4 LT |
29 | |
30 | VERSION 1.2 <2002/11/30> | |
31 | ||
32 | - Large style cleanup | |
33 | - Use ether_crc in stock kernel (linux/crc32.h) | |
34 | - Copy mc_filter setup code from 8139cp | |
35 | (includes an optimization, and avoids set_bit use) | |
36 | ||
37 | VERSION 1.6LK <2004/04/14> | |
38 | ||
39 | - Merge of Realtek's version 1.6 | |
40 | - Conversion to DMA API | |
41 | - Suspend/resume | |
42 | - Endianness | |
43 | - Misc Rx/Tx bugs | |
44 | ||
45 | VERSION 2.2LK <2005/01/25> | |
46 | ||
47 | - RX csum, TX csum/SG, TSO | |
48 | - VLAN | |
49 | - baby (< 7200) Jumbo frames support | |
50 | - Merge of Realtek's version 2.2 (new phy) | |
51 | */ | |
52 | ||
53 | #include <linux/module.h> | |
54 | #include <linux/moduleparam.h> | |
55 | #include <linux/pci.h> | |
56 | #include <linux/netdevice.h> | |
57 | #include <linux/etherdevice.h> | |
58 | #include <linux/delay.h> | |
59 | #include <linux/ethtool.h> | |
60 | #include <linux/mii.h> | |
61 | #include <linux/if_vlan.h> | |
62 | #include <linux/crc32.h> | |
63 | #include <linux/in.h> | |
64 | #include <linux/ip.h> | |
65 | #include <linux/tcp.h> | |
66 | #include <linux/init.h> | |
67 | #include <linux/dma-mapping.h> | |
68 | ||
99f252b0 | 69 | #include <asm/system.h> |
1da177e4 LT |
70 | #include <asm/io.h> |
71 | #include <asm/irq.h> | |
72 | ||
f7ccf420 SH |
73 | #ifdef CONFIG_R8169_NAPI |
74 | #define NAPI_SUFFIX "-NAPI" | |
75 | #else | |
76 | #define NAPI_SUFFIX "" | |
77 | #endif | |
78 | ||
79 | #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX | |
1da177e4 LT |
80 | #define MODULENAME "r8169" |
81 | #define PFX MODULENAME ": " | |
82 | ||
83 | #ifdef RTL8169_DEBUG | |
84 | #define assert(expr) \ | |
5b0384f4 FR |
85 | if (!(expr)) { \ |
86 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
87 | #expr,__FILE__,__FUNCTION__,__LINE__); \ | |
88 | } | |
1da177e4 LT |
89 | #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) |
90 | #else | |
91 | #define assert(expr) do {} while (0) | |
92 | #define dprintk(fmt, args...) do {} while (0) | |
93 | #endif /* RTL8169_DEBUG */ | |
94 | ||
b57b7e5a | 95 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 96 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 97 | |
1da177e4 LT |
98 | #define TX_BUFFS_AVAIL(tp) \ |
99 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
100 | ||
101 | #ifdef CONFIG_R8169_NAPI | |
102 | #define rtl8169_rx_skb netif_receive_skb | |
0b50f81d | 103 | #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb |
1da177e4 LT |
104 | #define rtl8169_rx_quota(count, quota) min(count, quota) |
105 | #else | |
106 | #define rtl8169_rx_skb netif_rx | |
0b50f81d | 107 | #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx |
1da177e4 LT |
108 | #define rtl8169_rx_quota(count, quota) count |
109 | #endif | |
110 | ||
111 | /* media options */ | |
112 | #define MAX_UNITS 8 | |
113 | static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; | |
114 | static int num_media = 0; | |
115 | ||
116 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ | |
f71e1309 | 117 | static const int max_interrupt_work = 20; |
1da177e4 LT |
118 | |
119 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
120 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 121 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
122 | |
123 | /* MAC address length */ | |
124 | #define MAC_ADDR_LEN 6 | |
125 | ||
126 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ | |
127 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
128 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
129 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ | |
130 | #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ | |
131 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ | |
132 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
133 | ||
134 | #define R8169_REGS_SIZE 256 | |
135 | #define R8169_NAPI_WEIGHT 64 | |
136 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
137 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
138 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
139 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
140 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
141 | ||
142 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
143 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
144 | ||
145 | /* write/read MMIO register */ | |
146 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
147 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
148 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
149 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
150 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
151 | #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) | |
152 | ||
153 | enum mac_version { | |
bcf0bf90 FR |
154 | RTL_GIGA_MAC_VER_01 = 0x00, |
155 | RTL_GIGA_MAC_VER_02 = 0x01, | |
156 | RTL_GIGA_MAC_VER_03 = 0x02, | |
157 | RTL_GIGA_MAC_VER_04 = 0x03, | |
158 | RTL_GIGA_MAC_VER_05 = 0x04, | |
2dd99530 FR |
159 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
160 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf | |
cdf1a608 FR |
161 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec |
162 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 | |
163 | RTL_GIGA_MAC_VER_15 = 0x0f // 8101 | |
1da177e4 LT |
164 | }; |
165 | ||
166 | enum phy_version { | |
167 | RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */ | |
168 | RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */ | |
169 | RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */ | |
170 | RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */ | |
171 | RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */ | |
172 | RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ | |
173 | }; | |
174 | ||
1da177e4 LT |
175 | #define _R(NAME,MAC,MASK) \ |
176 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
177 | ||
3c6bee1d | 178 | static const struct { |
1da177e4 LT |
179 | const char *name; |
180 | u8 mac_version; | |
181 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
182 | } rtl_chip_info[] = { | |
bcf0bf90 FR |
183 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), |
184 | _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880), | |
185 | _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), | |
186 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), | |
187 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), | |
188 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E | |
189 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
190 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
191 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
192 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139 | |
1da177e4 LT |
193 | }; |
194 | #undef _R | |
195 | ||
bcf0bf90 FR |
196 | enum cfg_version { |
197 | RTL_CFG_0 = 0x00, | |
198 | RTL_CFG_1, | |
199 | RTL_CFG_2 | |
200 | }; | |
201 | ||
07ce4064 FR |
202 | static void rtl_hw_start_8169(struct net_device *); |
203 | static void rtl_hw_start_8168(struct net_device *); | |
204 | static void rtl_hw_start_8101(struct net_device *); | |
205 | ||
bcf0bf90 | 206 | static const struct { |
07ce4064 | 207 | void (*hw_start)(struct net_device *); |
bcf0bf90 FR |
208 | unsigned int region; |
209 | unsigned int align; | |
210 | } rtl_cfg_info[] = { | |
07ce4064 FR |
211 | [RTL_CFG_0] = { rtl_hw_start_8169, 1, NET_IP_ALIGN }, |
212 | [RTL_CFG_1] = { rtl_hw_start_8168, 2, 8 }, | |
213 | [RTL_CFG_2] = { rtl_hw_start_8101, 2, 8 } | |
bcf0bf90 FR |
214 | }; |
215 | ||
1da177e4 | 216 | static struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 217 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 218 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 219 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 220 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
221 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
222 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |