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r8169: remove erroneous processing of always set bit.
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 46
1da177e4
LT		 47#ifdef RTL8169_DEBUG
48#define assert(expr) \
5b0384f4
FR		 49 if (!(expr)) { \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 51 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 52 }
06fa7358
JP		 53#define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 55#else
56#define assert(expr) do {} while (0)
57#define dprintk(fmt, args...) do {} while (0)
58#endif /* RTL8169_DEBUG */
59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63#define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
1da177e4
LT		 66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 68static const int multicast_filter_limit = 32;
1da177e4
LT		 69
70/* MAC address length */
71#define MAC_ADDR_LEN 6
72
9c14ceaf 73#define MAX_READ_REQUEST_SHIFT 12
1da177e4 74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
85bffe6c 136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
85bffe6c
FR		 144#define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 146
3c6bee1d 147static const struct {
1da177e4 148 const char *name;
2b7b4318 149 enum rtl_tx_desc_version txd_version;
953a12cc 150 const char *fw_name;
85bffe6c
FR		 151} rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
70090424
HW		 219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
953a12cc 222};
85bffe6c 223#undef _R
953a12cc 224
bcf0bf90
FR		 225enum cfg_version {
226 RTL_CFG_0 = 0x00,
227 RTL_CFG_1,
228 RTL_CFG_2
229};
230
07ce4064
FR		 231static void rtl_hw_start_8169(struct net_device *);
232static void rtl_hw_start_8168(struct net_device *);
233static void rtl_hw_start_8101(struct net_device *);
234
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 242 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 243 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 244 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
245 { PCI_VENDOR_ID_LINKSYS, 0x1032,
246 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 247 { 0x0001, 0x8168,
248 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 249 {0,},
250};
251
252MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
253
6f0333b8 254static int rx_buf_sz = 16383;
4300e8c7 255static int use_dac;
b57b7e5a
SH		 256static struct {
257 u32 msg_enable;
258} debug = { -1 };
1da177e4 259
07d3f51f
FR		 260enum rtl_registers {
261 MAC0 = 0, /* Ethernet hardware address. */
773d2021 262 MAC4 = 4,
07d3f51f
FR		 263 MAR0 = 8, /* Multicast filter. */
264 CounterAddrLow = 0x10,
265 CounterAddrHigh = 0x14,
266 TxDescStartAddrLow = 0x20,
267 TxDescStartAddrHigh = 0x24,
268 TxHDescStartAddrLow = 0x28,
269 TxHDescStartAddrHigh = 0x2c,
270 FLASH = 0x30,
271 ERSR = 0x36,
272 ChipCmd = 0x37,
273 TxPoll = 0x38,
274 IntrMask = 0x3c,
275 IntrStatus = 0x3e,
4f6b00e5 276
07d3f51f 277 TxConfig = 0x40,
4f6b00e5
HW		 278#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
279#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 280
4f6b00e5
HW		 281 RxConfig = 0x44,
282#define RX128_INT_EN (1 << 15) /* 8111c and later */
283#define RX_MULTI_EN (1 << 14) /* 8111c only */
284#define RXCFG_FIFO_SHIFT 13
285 /* No threshold before first PCI xfer */
286#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
287#define RXCFG_DMA_SHIFT 8
288 /* Unlimited maximum PCI burst. */
289#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 290
07d3f51f
FR		 291 RxMissed = 0x4c,
292 Cfg9346 = 0x50,
293 Config0 = 0x51,
294 Config1 = 0x52,
295 Config2 = 0x53,
296 Config3 = 0x54,
297 Config4 = 0x55,
298 Config5 = 0x56,
299 MultiIntr = 0x5c,
300 PHYAR = 0x60,
07d3f51f
FR		 301 PHYstatus = 0x6c,
302 RxMaxSize = 0xda,
303 CPlusCmd = 0xe0,
304 IntrMitigate = 0xe2,
305 RxDescAddrLow = 0xe4,
306 RxDescAddrHigh = 0xe8,
f0298f81 307 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
308
309#define NoEarlyTx 0x3f /* Max value : no early transmit. */
310
311 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
312
313#define TxPacketMax (8064 >> 7)
314
07d3f51f
FR		 315 FuncEvent = 0xf0,
316 FuncEventMask = 0xf4,
317 FuncPresetState = 0xf8,
318 FuncForceEvent = 0xfc,
1da177e4
LT		 319};
320
f162a5d1
FR		 321enum rtl8110_registers {
322 TBICSR = 0x64,
323 TBI_ANAR = 0x68,
324 TBI_LPAR = 0x6a,
325};
326
327enum rtl8168_8101_registers {
328 CSIDR = 0x64,
329 CSIAR = 0x68,
330#define CSIAR_FLAG 0x80000000
331#define CSIAR_WRITE_CMD 0x80000000
332#define CSIAR_BYTE_ENABLE 0x0f
333#define CSIAR_BYTE_ENABLE_SHIFT 12
334#define CSIAR_ADDR_MASK 0x0fff
065c27c1 335 PMCH = 0x6f,
f162a5d1
FR		 336 EPHYAR = 0x80,
337#define EPHYAR_FLAG 0x80000000
338#define EPHYAR_WRITE_CMD 0x80000000
339#define EPHYAR_REG_MASK 0x1f
340#define EPHYAR_REG_SHIFT 16
341#define EPHYAR_DATA_MASK 0xffff
5a5e4443 342 DLLPR = 0xd0,
4f6b00e5 343#define PFM_EN (1 << 6)
f162a5d1
FR		 344 DBG_REG = 0xd1,
345#define FIX_NAK_1 (1 << 4)
346#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 347 TWSI = 0xd2,
348 MCU = 0xd3,
4f6b00e5 349#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 350#define EN_NDP (1 << 3)
351#define EN_OOB_RESET (1 << 2)
daf9df6d 352 EFUSEAR = 0xdc,
353#define EFUSEAR_FLAG 0x80000000
354#define EFUSEAR_WRITE_CMD 0x80000000
355#define EFUSEAR_READ_CMD 0x00000000
356#define EFUSEAR_REG_MASK 0x03ff
357#define EFUSEAR_REG_SHIFT 8
358#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 359};
360
c0e45c1c 361enum rtl8168_registers {
4f6b00e5
HW		 362 LED_FREQ = 0x1a,
363 EEE_LED = 0x1b,
b646d900 364 ERIDR = 0x70,
365 ERIAR = 0x74,
366#define ERIAR_FLAG 0x80000000
367#define ERIAR_WRITE_CMD 0x80000000
368#define ERIAR_READ_CMD 0x00000000
369#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 370#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 371#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374#define ERIAR_MASK_SHIFT 12
375#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380#define OCPDR_WRITE_CMD 0x80000000
381#define OCPDR_READ_CMD 0x00000000
382#define OCPDR_REG_MASK 0x7f
383#define OCPDR_GPHY_REG_SHIFT 16
384#define OCPDR_DATA_MASK 0xffff
385 OCPAR = 0xb4,
386#define OCPAR_FLAG 0x80000000
387#define OCPAR_GPHY_WRITE_CMD 0x8000f060
388#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
cecb5fd7 391#define TXPLA_RST (1 << 29)
4f6b00e5 392#define PWM_EN (1 << 22)
c0e45c1c 393};
394
07d3f51f 395enum rtl_register_content {
1da177e4 396 /* InterruptStatusBits */
07d3f51f
FR		 397 SYSErr = 0x8000,
398 PCSTimeout = 0x4000,
399 SWInt = 0x0100,
400 TxDescUnavail = 0x0080,
401 RxFIFOOver = 0x0040,
402 LinkChg = 0x0020,
403 RxOverflow = 0x0010,
404 TxErr = 0x0008,
405 TxOK = 0x0004,
406 RxErr = 0x0002,
407 RxOK = 0x0001,
1da177e4
LT		 408
409 /* RxStatusDesc */
e03f33af 410 RxBOVF = (1 << 24),
9dccf611
FR		 411 RxFOVF = (1 << 23),
412 RxRWT = (1 << 22),
413 RxRES = (1 << 21),
414 RxRUNT = (1 << 20),
415 RxCRC = (1 << 19),
1da177e4
LT		 416
417 /* ChipCmdBits */
4f6b00e5 418 StopReq = 0x80,
07d3f51f
FR		 419 CmdReset = 0x10,
420 CmdRxEnb = 0x08,
421 CmdTxEnb = 0x04,
422 RxBufEmpty = 0x01,
1da177e4 423
275391a4
FR		 424 /* TXPoll register p.5 */
425 HPQ = 0x80, /* Poll cmd on the high prio queue */
426 NPQ = 0x40, /* Poll cmd on the low prio queue */
427 FSWInt = 0x01, /* Forced software interrupt */
428
1da177e4 429 /* Cfg9346Bits */
07d3f51f
FR		 430 Cfg9346_Lock = 0x00,
431 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 432
433 /* rx_mode_bits */
07d3f51f
FR		 434 AcceptErr = 0x20,
435 AcceptRunt = 0x10,
436 AcceptBroadcast = 0x08,
437 AcceptMulticast = 0x04,
438 AcceptMyPhys = 0x02,
439 AcceptAllPhys = 0x01,
1687b566 440#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 441
1da177e4
LT		 442 /* TxConfigBits */
443 TxInterFrameGapShift = 24,
444 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
445
5d06a99f 446 /* Config1 register p.24 */
f162a5d1
FR		 447 LEDS1 = (1 << 7),
448 LEDS0 = (1 << 6),
fbac58fc 449 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 450 Speed_down = (1 << 4),
451 MEMMAP = (1 << 3),
452 IOMAP = (1 << 2),
453 VPD = (1 << 1),
5d06a99f
FR		 454 PMEnable = (1 << 0), /* Power Management Enable */
455
6dccd16b
FR		 456 /* Config2 register p. 25 */
457 PCI_Clock_66MHz = 0x01,
458 PCI_Clock_33MHz = 0x00,
459
61a4dcc2
FR		 460 /* Config3 register p.25 */
461 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
462 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 463 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 464
5d06a99f 465 /* Config5 register p.27 */
61a4dcc2
FR		 466 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
467 MWF = (1 << 5), /* Accept Multicast wakeup frame */
468 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 469 Spi_en = (1 << 3),
61a4dcc2 470 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 471 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
472
1da177e4
LT		 473 /* TBICSR p.28 */
474 TBIReset = 0x80000000,
475 TBILoopback = 0x40000000,
476 TBINwEnable = 0x20000000,
477 TBINwRestart = 0x10000000,
478 TBILinkOk = 0x02000000,
479 TBINwComplete = 0x01000000,
480
481 /* CPlusCmd p.31 */
f162a5d1
FR		 482 EnableBist = (1 << 15), // 8168 8101
483 Mac_dbgo_oe = (1 << 14), // 8168 8101
484 Normal_mode = (1 << 13), // unused
485 Force_half_dup = (1 << 12), // 8168 8101
486 Force_rxflow_en = (1 << 11), // 8168 8101
487 Force_txflow_en = (1 << 10), // 8168 8101
488 Cxpl_dbg_sel = (1 << 9), // 8168 8101
489 ASF = (1 << 8), // 8168 8101
490 PktCntrDisable = (1 << 7), // 8168 8101
491 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 492 RxVlan = (1 << 6),
493 RxChkSum = (1 << 5),
494 PCIDAC = (1 << 4),
495 PCIMulRW = (1 << 3),
0e485150
FR		 496 INTT_0 = 0x0000, // 8168
497 INTT_1 = 0x0001, // 8168
498 INTT_2 = 0x0002, // 8168
499 INTT_3 = 0x0003, // 8168
1da177e4
LT		 500
501 /* rtl8169_PHYstatus */
07d3f51f
FR		 502 TBI_Enable = 0x80,
503 TxFlowCtrl = 0x40,
504 RxFlowCtrl = 0x20,
505 _1000bpsF = 0x10,
506 _100bps = 0x08,
507 _10bps = 0x04,
508 LinkStatus = 0x02,
509 FullDup = 0x01,
1da177e4 510
1da177e4 511 /* _TBICSRBit */
07d3f51f 512 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 513
514 /* DumpCounterCommand */
07d3f51f 515 CounterDump = 0x8,
1da177e4
LT		 516};
517
2b7b4318
FR		 518enum rtl_desc_bit {
519 /* First doubleword. */
1da177e4
LT		 520 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
521 RingEnd = (1 << 30), /* End of descriptor ring */
522 FirstFrag = (1 << 29), /* First segment of a packet */
523 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 524};
525
526/* Generic case. */
527enum rtl_tx_desc_bit {
528 /* First doubleword. */
529 TD_LSO = (1 << 27), /* Large Send Offload */
530#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 531
2b7b4318
FR		 532 /* Second doubleword. */
533 TxVlanTag = (1 << 17), /* Add VLAN tag */
534};
535
536/* 8169, 8168b and 810x except 8102e. */
537enum rtl_tx_desc_bit_0 {
538 /* First doubleword. */
539#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
540 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
541 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
542 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
543};
544
545/* 8102e, 8168c and beyond. */
546enum rtl_tx_desc_bit_1 {
547 /* Second doubleword. */
548#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
549 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
550 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
551 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
552};
1da177e4 553
2b7b4318
FR		 554static const struct rtl_tx_desc_info {
555 struct {
556 u32 udp;
557 u32 tcp;
558 } checksum;
559 u16 mss_shift;
560 u16 opts_offset;
561} tx_desc_info [] = {
562 [RTL_TD_0] = {
563 .checksum = {
564 .udp = TD0_IP_CS | TD0_UDP_CS,
565 .tcp = TD0_IP_CS | TD0_TCP_CS
566 },
567 .mss_shift = TD0_MSS_SHIFT,
568 .opts_offset = 0
569 },
570 [RTL_TD_1] = {
571 .checksum = {
572 .udp = TD1_IP_CS | TD1_UDP_CS,
573 .tcp = TD1_IP_CS | TD1_TCP_CS
574 },
575 .mss_shift = TD1_MSS_SHIFT,
576 .opts_offset = 1
577 }
578};
579
580enum rtl_rx_desc_bit {
1da177e4
LT		 581 /* Rx private */
582 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
583 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
584
585#define RxProtoUDP (PID1)
586#define RxProtoTCP (PID0)
587#define RxProtoIP (PID1 | PID0)
588#define RxProtoMask RxProtoIP
589
590 IPFail = (1 << 16), /* IP checksum failed */
591 UDPFail = (1 << 15), /* UDP/IP checksum failed */
592 TCPFail = (1 << 14), /* TCP/IP checksum failed */
593 RxVlanTag = (1 << 16), /* VLAN tag available */
594};
595
596#define RsvdMask 0x3fffc000
597
598struct TxDesc {
6cccd6e7
REB		 599 __le32 opts1;
600 __le32 opts2;
601 __le64 addr;
1da177e4
LT		 602};
603
604struct RxDesc {
6cccd6e7
REB		 605 __le32 opts1;
606 __le32 opts2;
607 __le64 addr;
1da177e4
LT		 608};
609
610struct ring_info {
611 struct sk_buff *skb;
612 u32 len;
613 u8 __pad[sizeof(void *) - sizeof(u32)];
614};
615
f23e7fda 616enum features {
ccdffb9a
FR		 617 RTL_FEATURE_WOL = (1 << 0),
618 RTL_FEATURE_MSI = (1 << 1),
619 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 620};
621
355423d0
IV		 622struct rtl8169_counters {
623 __le64 tx_packets;
624 __le64 rx_packets;
625 __le64 tx_errors;
626 __le32 rx_errors;
627 __le16 rx_missed;
628 __le16 align_errors;
629 __le32 tx_one_collision;
630 __le32 tx_multi_collision;
631 __le64 rx_unicast;
632 __le64 rx_broadcast;
633 __le32 rx_multicast;
634 __le16 tx_aborted;
635 __le16 tx_underun;
636};
637
1da177e4
LT		 638struct rtl8169_private {
639 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 640 struct pci_dev *pci_dev;
c4028958 641 struct net_device *dev;
bea3348e 642 struct napi_struct napi;
cecb5fd7 643 spinlock_t lock;
b57b7e5a 644 u32 msg_enable;
2b7b4318
FR		 645 u16 txd_version;
646 u16 mac_version;
1da177e4
LT		 647 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
648 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
649 u32 dirty_rx;
650 u32 dirty_tx;
651 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
652 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
653 dma_addr_t TxPhyAddr;
654 dma_addr_t RxPhyAddr;
6f0333b8 655 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 656 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 657 struct timer_list timer;
658 u16 cp_cmd;
0e485150
FR		 659 u16 intr_event;
660 u16 napi_event;
1da177e4 661 u16 intr_mask;
c0e45c1c 662
663 struct mdio_ops {
664 void (*write)(void __iomem *, int, int);
665 int (*read)(void __iomem *, int);
666 } mdio_ops;
667
065c27c1 668 struct pll_power_ops {
669 void (*down)(struct rtl8169_private *);
670 void (*up)(struct rtl8169_private *);
671 } pll_power_ops;
672
54405cde 673 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 674 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 675 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 676 void (*hw_start)(struct net_device *);
4da19633 677 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 678 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 679 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 680 struct delayed_work task;
f23e7fda 681 unsigned features;
ccdffb9a
FR		 682
683 struct mii_if_info mii;
355423d0 684 struct rtl8169_counters counters;
e1759441 685 u32 saved_wolopts;
e03f33af 686 u32 opts1_mask;
f1e02ed1 687
b6ffd97f
FR		 688 struct rtl_fw {
689 const struct firmware *fw;
1c361efb
FR		 690
691#define RTL_VER_SIZE 32
692
693 char version[RTL_VER_SIZE];
694
695 struct rtl_fw_phy_action {
696 __le32 *code;
697 size_t size;
698 } phy_action;
b6ffd97f 699 } *rtl_fw;
497888cf 700#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 701};
702
979b6c13 703MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 704MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 705module_param(use_dac, int, 0);
4300e8c7 706MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 707module_param_named(debug, debug.msg_enable, int, 0);
708MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 709MODULE_LICENSE("GPL");
710MODULE_VERSION(RTL8169_VERSION);
bca03d5f 711MODULE_FIRMWARE(FIRMWARE_8168D_1);
712MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 713MODULE_FIRMWARE(FIRMWARE_8168E_1);
714MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 715MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 716MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 717
718static int rtl8169_open(struct net_device *dev);
61357325
SH		 719static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
720 struct net_device *dev);
7d12e780 721static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 722static int rtl8169_init_ring(struct net_device *dev);
07ce4064 723static void rtl_hw_start(struct net_device *dev);
1da177e4 724static int rtl8169_close(struct net_device *dev);
07ce4064 725static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 726static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 727static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 728static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 729 void __iomem *, u32 budget);
4dcb7d33 730static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 731static void rtl8169_down(struct net_device *dev);
99f252b0 732static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 733static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 734
b646d900 735static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
736{
737 void __iomem *ioaddr = tp->mmio_addr;
738 int i;
739
740 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
741 for (i = 0; i < 20; i++) {
742 udelay(100);
743 if (RTL_R32(OCPAR) & OCPAR_FLAG)
744 break;
745 }
746 return RTL_R32(OCPDR);
747}
748
749static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
750{
751 void __iomem *ioaddr = tp->mmio_addr;
752 int i;
753
754 RTL_W32(OCPDR, data);
755 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
756 for (i = 0; i < 20; i++) {
757 udelay(100);
758 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
759 break;
760 }
761}
762
fac5b3ca 763static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 764{
fac5b3ca 765 void __iomem *ioaddr = tp->mmio_addr;
b646d900 766 int i;
767
768 RTL_W8(ERIDR, cmd);
769 RTL_W32(ERIAR, 0x800010e8);
770 msleep(2);
771 for (i = 0; i < 5; i++) {
772 udelay(100);
1e4e82ba 773 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 774 break;
775 }
776
fac5b3ca 777 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 778}
779
780#define OOB_CMD_RESET 0x00
781#define OOB_CMD_DRIVER_START 0x05
782#define OOB_CMD_DRIVER_STOP 0x06
783
cecb5fd7
FR		 784static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
785{
786 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
787}
788
b646d900 789static void rtl8168_driver_start(struct rtl8169_private *tp)
790{
cecb5fd7 791 u16 reg;
b646d900 792 int i;
793
794 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
795
cecb5fd7 796 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 797
b646d900 798 for (i = 0; i < 10; i++) {
799 msleep(10);
4804b3b3 800 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 801 break;
802 }
803}
804
805static void rtl8168_driver_stop(struct rtl8169_private *tp)
806{
cecb5fd7 807 u16 reg;
b646d900 808 int i;
809
810 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
811
cecb5fd7 812 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 813
b646d900 814 for (i = 0; i < 10; i++) {
815 msleep(10);
4804b3b3 816 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 817 break;
818 }
819}
820
4804b3b3 821static int r8168dp_check_dash(struct rtl8169_private *tp)
822{
cecb5fd7 823 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 824
cecb5fd7 825 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 826}
b646d900 827
4da19633 828static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 829{
830 int i;
831
a6baf3af 832 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 833
2371408c 834 for (i = 20; i > 0; i--) {
07d3f51f
FR		 835 /*
836 * Check if the RTL8169 has completed writing to the specified
837 * MII register.
838 */
5b0384f4 839 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 840 break;
2371408c 841 udelay(25);
1da177e4 842 }
024a07ba 843 /*
81a95f04
TT		 844 * According to hardware specs a 20us delay is required after write
845 * complete indication, but before sending next command.
024a07ba 846 */
81a95f04 847 udelay(20);
1da177e4
LT		 848}
849
4da19633 850static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 851{
852 int i, value = -1;
853
a6baf3af 854 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 855
2371408c 856 for (i = 20; i > 0; i--) {
07d3f51f
FR		 857 /*
858 * Check if the RTL8169 has completed retrieving data from
859 * the specified MII register.
860 */
1da177e4 861 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 862 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 863 break;
864 }
2371408c 865 udelay(25);
1da177e4 866 }
81a95f04
TT		 867 /*
868 * According to hardware specs a 20us delay is required after read
869 * complete indication, but before sending next command.
870 */
871 udelay(20);
872
1da177e4
LT		 873 return value;
874}
875
c0e45c1c 876static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
877{
878 int i;
879
880 RTL_W32(OCPDR, data |
881 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
882 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
883 RTL_W32(EPHY_RXER_NUM, 0);
884
885 for (i = 0; i < 100; i++) {
886 mdelay(1);
887 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
888 break;
889 }
890}
891
892static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
893{
894 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
895 (value & OCPDR_DATA_MASK));
896}
897
898static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
899{
900 int i;
901
902 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
903
904 mdelay(1);
905 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
906 RTL_W32(EPHY_RXER_NUM, 0);
907
908 for (i = 0; i < 100; i++) {
909 mdelay(1);
910 if (RTL_R32(OCPAR) & OCPAR_FLAG)
911 break;
912 }
913
914 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
915}
916
e6de30d6 917#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
918
919static void r8168dp_2_mdio_start(void __iomem *ioaddr)
920{
921 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
922}
923
924static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
925{
926 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
927}
928
929static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
930{
931 r8168dp_2_mdio_start(ioaddr);
932
933 r8169_mdio_write(ioaddr, reg_addr, value);
934
935 r8168dp_2_mdio_stop(ioaddr);
936}
937
938static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
939{
940 int value;
941
942 r8168dp_2_mdio_start(ioaddr);
943
944 value = r8169_mdio_read(ioaddr, reg_addr);
945
946 r8168dp_2_mdio_stop(ioaddr);
947
948 return value;
949}
950
4da19633 951static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 952{
c0e45c1c 953 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 954}
955
4da19633 956static int rtl_readphy(struct rtl8169_private *tp, int location)
957{
c0e45c1c 958 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 959}
960
961static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
962{
963 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
964}
965
966static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 967{
968 int val;
969
4da19633 970 val = rtl_readphy(tp, reg_addr);
971 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 972}
973
ccdffb9a
FR		 974static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
975 int val)
976{
977 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 978
4da19633 979 rtl_writephy(tp, location, val);
ccdffb9a
FR		 980}
981
982static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
983{
984 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 985
4da19633 986 return rtl_readphy(tp, location);
ccdffb9a
FR		 987}
988
dacf8154
FR		 989static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
990{
991 unsigned int i;
992
993 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
994 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
995
996 for (i = 0; i < 100; i++) {
997 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
998 break;
999 udelay(10);
1000 }
1001}
1002
1003static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1004{
1005 u16 value = 0xffff;
1006 unsigned int i;
1007
1008 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1009
1010 for (i = 0; i < 100; i++) {
1011 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1012 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1013 break;
1014 }
1015 udelay(10);
1016 }
1017
1018 return value;
1019}
1020
1021static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1022{
1023 unsigned int i;
1024
1025 RTL_W32(CSIDR, value);
1026 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1027 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1028
1029 for (i = 0; i < 100; i++) {
1030 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1031 break;
1032 udelay(10);
1033 }
1034}
1035
1036static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1037{
1038 u32 value = ~0x00;
1039 unsigned int i;
1040
1041 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1042 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1043
1044 for (i = 0; i < 100; i++) {
1045 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1046 value = RTL_R32(CSIDR);
1047 break;
1048 }
1049 udelay(10);
1050 }
1051
1052 return value;
1053}
1054
133ac40a
HW		 1055static
1056void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1057{
1058 unsigned int i;
1059
1060 BUG_ON((addr & 3) || (mask == 0));
1061 RTL_W32(ERIDR, val);
1062 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1063
1064 for (i = 0; i < 100; i++) {
1065 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1066 break;
1067 udelay(100);
1068 }
1069}
1070
1071static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1072{
1073 u32 value = ~0x00;
1074 unsigned int i;
1075
1076 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1077
1078 for (i = 0; i < 100; i++) {
1079 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1080 value = RTL_R32(ERIDR);
1081 break;
1082 }
1083 udelay(100);
1084 }
1085
1086 return value;
1087}
1088
1089static void
1090rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1091{
1092 u32 val;
1093
1094 val = rtl_eri_read(ioaddr, addr, type);
1095 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1096}
1097
c28aa385 1098struct exgmac_reg {
1099 u16 addr;
1100 u16 mask;
1101 u32 val;
1102};
1103
1104static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1105 const struct exgmac_reg *r, int len)
1106{
1107 while (len-- > 0) {
1108 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1109 r++;
1110 }
1111}
1112
daf9df6d 1113static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1114{
1115 u8 value = 0xff;
1116 unsigned int i;
1117
1118 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1119
1120 for (i = 0; i < 300; i++) {
1121 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1122 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1123 break;
1124 }
1125 udelay(100);
1126 }
1127
1128 return value;
1129}
1130
1da177e4
LT		 1131static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1132{
1133 RTL_W16(IntrMask, 0x0000);
1134
1135 RTL_W16(IntrStatus, 0xffff);
1136}
1137
4da19633 1138static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1139{
4da19633 1140 void __iomem *ioaddr = tp->mmio_addr;
1141
1da177e4
LT		 1142 return RTL_R32(TBICSR) & TBIReset;
1143}
1144
4da19633 1145static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1146{
4da19633 1147 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1148}
1149
1150static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1151{
1152 return RTL_R32(TBICSR) & TBILinkOk;
1153}
1154
1155static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1156{
1157 return RTL_R8(PHYstatus) & LinkStatus;
1158}
1159
4da19633 1160static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1161{
4da19633 1162 void __iomem *ioaddr = tp->mmio_addr;
1163
1da177e4
LT		 1164 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1165}
1166
4da19633 1167static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1168{
1169 unsigned int val;
1170
4da19633 1171 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1172 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1173}
1174
70090424
HW		 1175static void rtl_link_chg_patch(struct rtl8169_private *tp)
1176{
1177 void __iomem *ioaddr = tp->mmio_addr;
1178 struct net_device *dev = tp->dev;
1179
1180 if (!netif_running(dev))
1181 return;
1182
1183 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1184 if (RTL_R8(PHYstatus) & _1000bpsF) {
1185 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1186 0x00000011, ERIAR_EXGMAC);
1187 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1188 0x00000005, ERIAR_EXGMAC);
1189 } else if (RTL_R8(PHYstatus) & _100bps) {
1190 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1191 0x0000001f, ERIAR_EXGMAC);
1192 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1193 0x00000005, ERIAR_EXGMAC);
1194 } else {
1195 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1196 0x0000001f, ERIAR_EXGMAC);
1197 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1198 0x0000003f, ERIAR_EXGMAC);
1199 }
1200 /* Reset packet filter */
1201 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1202 ERIAR_EXGMAC);
1203 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1204 ERIAR_EXGMAC);
1205 }
1206}
1207
e4fbce74 1208static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1209 struct rtl8169_private *tp,
1210 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1211{
1212 unsigned long flags;
1213
1214 spin_lock_irqsave(&tp->lock, flags);
1215 if (tp->link_ok(ioaddr)) {
70090424 1216 rtl_link_chg_patch(tp);
e1759441 1217 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1218 if (pm)
1219 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1220 netif_carrier_on(dev);
1519e57f
FR		 1221 if (net_ratelimit())
1222 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1223 } else {
1da177e4 1224 netif_carrier_off(dev);
bf82c189 1225 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1226 if (pm)
1227 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1228 }
1da177e4
LT		 1229 spin_unlock_irqrestore(&tp->lock, flags);
1230}
1231
e4fbce74
RW		 1232static void rtl8169_check_link_status(struct net_device *dev,
1233 struct rtl8169_private *tp,
1234 void __iomem *ioaddr)
1235{
1236 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1237}
1238
e1759441
RW		 1239#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1240
1241static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1242{
61a4dcc2
FR		 1243 void __iomem *ioaddr = tp->mmio_addr;
1244 u8 options;
e1759441 1245 u32 wolopts = 0;
61a4dcc2
FR		 1246
1247 options = RTL_R8(Config1);
1248 if (!(options & PMEnable))
e1759441 1249 return 0;
61a4dcc2
FR		 1250
1251 options = RTL_R8(Config3);
1252 if (options & LinkUp)
e1759441 1253 wolopts |= WAKE_PHY;
61a4dcc2 1254 if (options & MagicPacket)
e1759441 1255 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1256
1257 options = RTL_R8(Config5);
1258 if (options & UWF)
e1759441 1259 wolopts |= WAKE_UCAST;
61a4dcc2 1260 if (options & BWF)
e1759441 1261 wolopts |= WAKE_BCAST;
61a4dcc2 1262 if (options & MWF)
e1759441 1263 wolopts |= WAKE_MCAST;
61a4dcc2 1264
e1759441 1265 return wolopts;
61a4dcc2
FR		 1266}
1267
e1759441 1268static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1269{
1270 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1271
1272 spin_lock_irq(&tp->lock);
1273
1274 wol->supported = WAKE_ANY;
1275 wol->wolopts = __rtl8169_get_wol(tp);
1276
1277 spin_unlock_irq(&tp->lock);
1278}
1279
1280static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1281{
61a4dcc2 1282 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1283 unsigned int i;
350f7596 1284 static const struct {
61a4dcc2
FR		 1285 u32 opt;
1286 u16 reg;
1287 u8 mask;
1288 } cfg[] = {
1289 { WAKE_ANY, Config1, PMEnable },
1290 { WAKE_PHY, Config3, LinkUp },
1291 { WAKE_MAGIC, Config3, MagicPacket },
1292 { WAKE_UCAST, Config5, UWF },
1293 { WAKE_BCAST, Config5, BWF },
1294 { WAKE_MCAST, Config5, MWF },
1295 { WAKE_ANY, Config5, LanWake }
1296 };
1297
61a4dcc2
FR		 1298 RTL_W8(Cfg9346, Cfg9346_Unlock);
1299
1300 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1301 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1302 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1303 options |= cfg[i].mask;
1304 RTL_W8(cfg[i].reg, options);
1305 }
1306
1307 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1308}
1309
1310static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1311{
1312 struct rtl8169_private *tp = netdev_priv(dev);
1313
1314 spin_lock_irq(&tp->lock);
61a4dcc2 1315
f23e7fda
FR		 1316 if (wol->wolopts)
1317 tp->features |= RTL_FEATURE_WOL;
1318 else
1319 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1320 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1321 spin_unlock_irq(&tp->lock);
1322
ea80907f 1323 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1324
61a4dcc2
FR		 1325 return 0;
1326}
1327
31bd204f
FR		 1328static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1329{
85bffe6c 1330 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1331}
1332
1da177e4
LT		 1333static void rtl8169_get_drvinfo(struct net_device *dev,
1334 struct ethtool_drvinfo *info)
1335{
1336 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1337 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1338
1339 strcpy(info->driver, MODULENAME);
1340 strcpy(info->version, RTL8169_VERSION);
1341 strcpy(info->bus_info, pci_name(tp->pci_dev));
1c361efb
FR		 1342 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1343 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1344 rtl_fw->version);
1da177e4
LT		 1345}
1346
1347static int rtl8169_get_regs_len(struct net_device *dev)
1348{
1349 return R8169_REGS_SIZE;
1350}
1351
1352static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1353 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1354{
1355 struct rtl8169_private *tp = netdev_priv(dev);
1356 void __iomem *ioaddr = tp->mmio_addr;
1357 int ret = 0;
1358 u32 reg;
1359
1360 reg = RTL_R32(TBICSR);
1361 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1362 (duplex == DUPLEX_FULL)) {
1363 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1364 } else if (autoneg == AUTONEG_ENABLE)
1365 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1366 else {
bf82c189
JP		 1367 netif_warn(tp, link, dev,
1368 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1369 ret = -EOPNOTSUPP;
1370 }
1371
1372 return ret;
1373}
1374
1375static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1376 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1377{
1378 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1379 int giga_ctrl, bmcr;
54405cde 1380 int rc = -EINVAL;
1da177e4 1381
716b50a3 1382 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1383
1384 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1385 int auto_nego;
1386
4da19633 1387 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1388 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1389 ADVERTISE_100HALF | ADVERTISE_100FULL);
1390
1391 if (adv & ADVERTISED_10baseT_Half)
1392 auto_nego |= ADVERTISE_10HALF;
1393 if (adv & ADVERTISED_10baseT_Full)
1394 auto_nego |= ADVERTISE_10FULL;
1395 if (adv & ADVERTISED_100baseT_Half)
1396 auto_nego |= ADVERTISE_100HALF;
1397 if (adv & ADVERTISED_100baseT_Full)
1398 auto_nego |= ADVERTISE_100FULL;
1399
3577aa1b 1400 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1401
4da19633 1402 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1403 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1404
3577aa1b 1405 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1406 if (tp->mii.supports_gmii) {
54405cde
ON		 1407 if (adv & ADVERTISED_1000baseT_Half)
1408 giga_ctrl |= ADVERTISE_1000HALF;
1409 if (adv & ADVERTISED_1000baseT_Full)
1410 giga_ctrl |= ADVERTISE_1000FULL;
1411 } else if (adv & (ADVERTISED_1000baseT_Half |
1412 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1413 netif_info(tp, link, dev,
1414 "PHY does not support 1000Mbps\n");
54405cde 1415 goto out;
bcf0bf90 1416 }
1da177e4 1417
3577aa1b 1418 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1419
4da19633 1420 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1421 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1422 } else {
1423 giga_ctrl = 0;
1424
1425 if (speed == SPEED_10)
1426 bmcr = 0;
1427 else if (speed == SPEED_100)
1428 bmcr = BMCR_SPEED100;
1429 else
54405cde 1430 goto out;
3577aa1b 1431
1432 if (duplex == DUPLEX_FULL)
1433 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1434 }
1435
4da19633 1436 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1437
cecb5fd7
FR		 1438 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1439 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1440 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1441 rtl_writephy(tp, 0x17, 0x2138);
1442 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1443 } else {
4da19633 1444 rtl_writephy(tp, 0x17, 0x2108);
1445 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1446 }
1447 }
1448
54405cde
ON		 1449 rc = 0;
1450out:
1451 return rc;
1da177e4
LT		 1452}
1453
1454static int rtl8169_set_speed(struct net_device *dev,
54405cde 1455 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1456{
1457 struct rtl8169_private *tp = netdev_priv(dev);
1458 int ret;
1459
54405cde 1460 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1461 if (ret < 0)
1462 goto out;
1da177e4 1463
4876cc1e
FR		 1464 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1465 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1466 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1467 }
1468out:
1da177e4
LT		 1469 return ret;
1470}
1471
1472static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1473{
1474 struct rtl8169_private *tp = netdev_priv(dev);
1475 unsigned long flags;
1476 int ret;
1477
4876cc1e
FR		 1478 del_timer_sync(&tp->timer);
1479
1da177e4 1480 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1481 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1482 cmd->duplex, cmd->advertising);
1da177e4 1483 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1484
1da177e4
LT		 1485 return ret;
1486}
1487
350fb32a 1488static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1489{
2b7b4318 1490 if (dev->mtu > TD_MSS_MAX)
350fb32a 1491 features &= ~NETIF_F_ALL_TSO;
1da177e4 1492
350fb32a 1493 return features;
1da177e4
LT		 1494}
1495
350fb32a 1496static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1497{
1498 struct rtl8169_private *tp = netdev_priv(dev);
1499 void __iomem *ioaddr = tp->mmio_addr;
1500 unsigned long flags;
1501
1502 spin_lock_irqsave(&tp->lock, flags);
1503
350fb32a 1504 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1505 tp->cp_cmd |= RxChkSum;
1506 else
1507 tp->cp_cmd &= ~RxChkSum;
1508
350fb32a
MM		 1509 if (dev->features & NETIF_F_HW_VLAN_RX)
1510 tp->cp_cmd |= RxVlan;
1511 else
1512 tp->cp_cmd &= ~RxVlan;
1513
1da177e4
LT		 1514 RTL_W16(CPlusCmd, tp->cp_cmd);
1515 RTL_R16(CPlusCmd);
1516
1517 spin_unlock_irqrestore(&tp->lock, flags);
1518
1519 return 0;
1520}
1521
1da177e4
LT		 1522static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1523 struct sk_buff *skb)
1524{
eab6d18d 1525 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1526 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1527}
1528
7a8fc77b 1529static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1530{
1531 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1532
7a8fc77b
FR		 1533 if (opts2 & RxVlanTag)
1534 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1535
1da177e4 1536 desc->opts2 = 0;
1da177e4
LT		 1537}
1538
ccdffb9a 1539static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1540{
1541 struct rtl8169_private *tp = netdev_priv(dev);
1542 void __iomem *ioaddr = tp->mmio_addr;
1543 u32 status;
1544
1545 cmd->supported =
1546 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1547 cmd->port = PORT_FIBRE;
1548 cmd->transceiver = XCVR_INTERNAL;
1549
1550 status = RTL_R32(TBICSR);
1551 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1552 cmd->autoneg = !!(status & TBINwEnable);
1553
70739497 1554 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1555 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1556
1557 return 0;
1da177e4
LT		 1558}
1559
ccdffb9a 1560static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1561{
1562 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1563
1564 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1565}
1566
1567static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1568{
1569 struct rtl8169_private *tp = netdev_priv(dev);
1570 unsigned long flags;
ccdffb9a 1571 int rc;
1da177e4
LT		 1572
1573 spin_lock_irqsave(&tp->lock, flags);
1574
ccdffb9a 1575 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1576
1577 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1578 return rc;
1da177e4
LT		 1579}
1580
1581static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1582 void *p)
1583{
5b0384f4
FR		 1584 struct rtl8169_private *tp = netdev_priv(dev);
1585 unsigned long flags;
1da177e4 1586
5b0384f4
FR		 1587 if (regs->len > R8169_REGS_SIZE)
1588 regs->len = R8169_REGS_SIZE;
1da177e4 1589
5b0384f4
FR		 1590 spin_lock_irqsave(&tp->lock, flags);
1591 memcpy_fromio(p, tp->mmio_addr, regs->len);
1592 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1593}
1594
b57b7e5a
SH		 1595static u32 rtl8169_get_msglevel(struct net_device *dev)
1596{
1597 struct rtl8169_private *tp = netdev_priv(dev);
1598
1599 return tp->msg_enable;
1600}
1601
1602static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1603{
1604 struct rtl8169_private *tp = netdev_priv(dev);
1605
1606 tp->msg_enable = value;
1607}
1608
d4a3a0fc
SH		 1609static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1610 "tx_packets",
1611 "rx_packets",
1612 "tx_errors",
1613 "rx_errors",
1614 "rx_missed",
1615 "align_errors",
1616 "tx_single_collisions",
1617 "tx_multi_collisions",
1618 "unicast",
1619 "broadcast",
1620 "multicast",
1621 "tx_aborted",
1622 "tx_underrun",
1623};
1624
b9f2c044 1625static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1626{
b9f2c044
JG		 1627 switch (sset) {
1628 case ETH_SS_STATS:
1629 return ARRAY_SIZE(rtl8169_gstrings);
1630 default:
1631 return -EOPNOTSUPP;
1632 }
d4a3a0fc
SH		 1633}
1634
355423d0 1635static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1636{
1637 struct rtl8169_private *tp = netdev_priv(dev);
1638 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1639 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1640 struct rtl8169_counters *counters;
1641 dma_addr_t paddr;
1642 u32 cmd;
355423d0 1643 int wait = 1000;
d4a3a0fc 1644
355423d0
IV		 1645 /*
1646 * Some chips are unable to dump tally counters when the receiver
1647 * is disabled.
1648 */
1649 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1650 return;
d4a3a0fc 1651
48addcc9 1652 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1653 if (!counters)
1654 return;
1655
1656 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1657 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1658 RTL_W32(CounterAddrLow, cmd);
1659 RTL_W32(CounterAddrLow, cmd | CounterDump);
1660
355423d0
IV		 1661 while (wait--) {
1662 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1663 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1664 break;
355423d0
IV		 1665 }
1666 udelay(10);
d4a3a0fc
SH		 1667 }
1668
1669 RTL_W32(CounterAddrLow, 0);
1670 RTL_W32(CounterAddrHigh, 0);
1671
48addcc9 1672 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1673}
1674
355423d0
IV		 1675static void rtl8169_get_ethtool_stats(struct net_device *dev,
1676 struct ethtool_stats *stats, u64 *data)
1677{
1678 struct rtl8169_private *tp = netdev_priv(dev);
1679
1680 ASSERT_RTNL();
1681
1682 rtl8169_update_counters(dev);
1683
1684 data[0] = le64_to_cpu(tp->counters.tx_packets);
1685 data[1] = le64_to_cpu(tp->counters.rx_packets);
1686 data[2] = le64_to_cpu(tp->counters.tx_errors);
1687 data[3] = le32_to_cpu(tp->counters.rx_errors);
1688 data[4] = le16_to_cpu(tp->counters.rx_missed);
1689 data[5] = le16_to_cpu(tp->counters.align_errors);
1690 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1691 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1692 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1693 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1694 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1695 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1696 data[12] = le16_to_cpu(tp->counters.tx_underun);
1697}
1698
d4a3a0fc
SH		 1699static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1700{
1701 switch(stringset) {
1702 case ETH_SS_STATS:
1703 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1704 break;
1705 }
1706}
1707
7282d491 1708static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1709 .get_drvinfo = rtl8169_get_drvinfo,
1710 .get_regs_len = rtl8169_get_regs_len,
1711 .get_link = ethtool_op_get_link,
1712 .get_settings = rtl8169_get_settings,
1713 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1714 .get_msglevel = rtl8169_get_msglevel,
1715 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1716 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1717 .get_wol = rtl8169_get_wol,
1718 .set_wol = rtl8169_set_wol,
d4a3a0fc 1719 .get_strings = rtl8169_get_strings,
b9f2c044 1720 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1721 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1722};
1723
07d3f51f 1724static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1725 struct net_device *dev, u8 default_version)
1da177e4 1726{
5d320a20 1727 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1728 /*
1729 * The driver currently handles the 8168Bf and the 8168Be identically
1730 * but they can be identified more specifically through the test below
1731 * if needed:
1732 *
1733 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1734 *
1735 * Same thing for the 8101Eb and the 8101Ec:
1736 *
1737 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1738 */
3744100e 1739 static const struct rtl_mac_info {
1da177e4 1740 u32 mask;
e3cf0cc0 1741 u32 val;
1da177e4
LT		 1742 int mac_version;
1743 } mac_info[] = {
01dc7fec 1744 /* 8168E family. */
70090424 1745 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1746 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1747 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1748 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1749
5b538df9 1750 /* 8168D family. */
daf9df6d 1751 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1752 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1753 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1754
e6de30d6 1755 /* 8168DP family. */
1756 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1757 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1758 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1759
ef808d50 1760 /* 8168C family. */
17c99297 1761 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1762 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1763 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1764 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1765 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1766 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1767 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1768 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1769 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1770
1771 /* 8168B family. */
1772 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1773 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1774 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1775 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1776
1777 /* 8101 family. */
36a0e6c2 1778 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1779 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1780 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1781 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1782 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1783 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1784 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1785 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1786 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1787 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1788 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1789 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1790 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1791 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1792 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1793 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1794 /* FIXME: where did these entries come from ? -- FR */
1795 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1796 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1797
1798 /* 8110 family. */
1799 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1800 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1801 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1802 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1803 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1804 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1805
f21b75e9
JD		 1806 /* Catch-all */
1807 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1808 };
1809 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1810 u32 reg;
1811
e3cf0cc0
FR		 1812 reg = RTL_R32(TxConfig);
1813 while ((reg & p->mask) != p->val)
1da177e4
LT		 1814 p++;
1815 tp->mac_version = p->mac_version;
5d320a20
FR		 1816
1817 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1818 netif_notice(tp, probe, dev,
1819 "unknown MAC, using family default\n");
1820 tp->mac_version = default_version;
1821 }
1da177e4
LT		 1822}
1823
1824static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1825{
bcf0bf90 1826 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1827}
1828
867763c1
FR		 1829struct phy_reg {
1830 u16 reg;
1831 u16 val;
1832};
1833
4da19633 1834static void rtl_writephy_batch(struct rtl8169_private *tp,
1835 const struct phy_reg *regs, int len)
867763c1
FR		 1836{
1837 while (len-- > 0) {
4da19633 1838 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1839 regs++;
1840 }
1841}
1842
bca03d5f 1843#define PHY_READ 0x00000000
1844#define PHY_DATA_OR 0x10000000
1845#define PHY_DATA_AND 0x20000000
1846#define PHY_BJMPN 0x30000000
1847#define PHY_READ_EFUSE 0x40000000
1848#define PHY_READ_MAC_BYTE 0x50000000
1849#define PHY_WRITE_MAC_BYTE 0x60000000
1850#define PHY_CLEAR_READCOUNT 0x70000000
1851#define PHY_WRITE 0x80000000
1852#define PHY_READCOUNT_EQ_SKIP 0x90000000
1853#define PHY_COMP_EQ_SKIPN 0xa0000000
1854#define PHY_COMP_NEQ_SKIPN 0xb0000000
1855#define PHY_WRITE_PREVIOUS 0xc0000000
1856#define PHY_SKIPN 0xd0000000
1857#define PHY_DELAY_MS 0xe0000000
1858#define PHY_WRITE_ERI_WORD 0xf0000000
1859
960aee6c
HW		 1860struct fw_info {
1861 u32 magic;
1862 char version[RTL_VER_SIZE];
1863 __le32 fw_start;
1864 __le32 fw_len;
1865 u8 chksum;
1866} __packed;
1867
1c361efb
FR		 1868#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1869
1870static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1871{
b6ffd97f 1872 const struct firmware *fw = rtl_fw->fw;
960aee6c 1873 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1874 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1875 char *version = rtl_fw->version;
1876 bool rc = false;
1877
1878 if (fw->size < FW_OPCODE_SIZE)
1879 goto out;
960aee6c
HW		 1880
1881 if (!fw_info->magic) {
1882 size_t i, size, start;
1883 u8 checksum = 0;
1884
1885 if (fw->size < sizeof(*fw_info))
1886 goto out;
1887
1888 for (i = 0; i < fw->size; i++)
1889 checksum += fw->data[i];
1890 if (checksum != 0)
1891 goto out;
1892
1893 start = le32_to_cpu(fw_info->fw_start);
1894 if (start > fw->size)
1895 goto out;
1896
1897 size = le32_to_cpu(fw_info->fw_len);
1898 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1899 goto out;
1900
1901 memcpy(version, fw_info->version, RTL_VER_SIZE);
1902
1903 pa->code = (__le32 *)(fw->data + start);
1904 pa->size = size;
1905 } else {
1c361efb
FR		 1906 if (fw->size % FW_OPCODE_SIZE)
1907 goto out;
1908
1909 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1910
1911 pa->code = (__le32 *)fw->data;
1912 pa->size = fw->size / FW_OPCODE_SIZE;
1913 }
1914 version[RTL_VER_SIZE - 1] = 0;
1915
1916 rc = true;
1917out:
1918 return rc;
1919}
1920
fd112f2e
FR		 1921static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1922 struct rtl_fw_phy_action *pa)
1c361efb 1923{
fd112f2e 1924 bool rc = false;
1c361efb 1925 size_t index;
bca03d5f 1926
1c361efb
FR		 1927 for (index = 0; index < pa->size; index++) {
1928 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 1929 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1930
42b82dc1 1931 switch(action & 0xf0000000) {
1932 case PHY_READ:
1933 case PHY_DATA_OR:
1934 case PHY_DATA_AND:
1935 case PHY_READ_EFUSE:
1936 case PHY_CLEAR_READCOUNT:
1937 case PHY_WRITE:
1938 case PHY_WRITE_PREVIOUS:
1939 case PHY_DELAY_MS:
1940 break;
1941
1942 case PHY_BJMPN:
1943 if (regno > index) {
fd112f2e 1944 netif_err(tp, ifup, tp->dev,
cecb5fd7 1945 "Out of range of firmware\n");
fd112f2e 1946 goto out;
42b82dc1 1947 }
1948 break;
1949 case PHY_READCOUNT_EQ_SKIP:
1c361efb 1950 if (index + 2 >= pa->size) {
fd112f2e 1951 netif_err(tp, ifup, tp->dev,
cecb5fd7 1952 "Out of range of firmware\n");
fd112f2e 1953 goto out;
42b82dc1 1954 }
1955 break;
1956 case PHY_COMP_EQ_SKIPN:
1957 case PHY_COMP_NEQ_SKIPN:
1958 case PHY_SKIPN:
1c361efb 1959 if (index + 1 + regno >= pa->size) {
fd112f2e 1960 netif_err(tp, ifup, tp->dev,
cecb5fd7 1961 "Out of range of firmware\n");
fd112f2e 1962 goto out;
42b82dc1 1963 }
bca03d5f 1964 break;
1965
42b82dc1 1966 case PHY_READ_MAC_BYTE:
1967 case PHY_WRITE_MAC_BYTE:
1968 case PHY_WRITE_ERI_WORD:
1969 default:
fd112f2e 1970 netif_err(tp, ifup, tp->dev,
42b82dc1 1971 "Invalid action 0x%08x\n", action);
fd112f2e 1972 goto out;
bca03d5f 1973 }
1974 }
fd112f2e
FR		 1975 rc = true;
1976out:
1977 return rc;
1978}
bca03d5f 1979
fd112f2e
FR		 1980static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1981{
1982 struct net_device *dev = tp->dev;
1983 int rc = -EINVAL;
1984
1985 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1986 netif_err(tp, ifup, dev, "invalid firwmare\n");
1987 goto out;
1988 }
1989
1990 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1991 rc = 0;
1992out:
1993 return rc;
1994}
1995
1996static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1997{
1998 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1999 u32 predata, count;
2000 size_t index;
2001
2002 predata = count = 0;
42b82dc1 2003
1c361efb
FR		 2004 for (index = 0; index < pa->size; ) {
2005 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2006 u32 data = action & 0x0000ffff;
42b82dc1 2007 u32 regno = (action & 0x0fff0000) >> 16;
2008
2009 if (!action)
2010 break;
bca03d5f 2011
2012 switch(action & 0xf0000000) {
42b82dc1 2013 case PHY_READ:
2014 predata = rtl_readphy(tp, regno);
2015 count++;
2016 index++;
2017 break;
2018 case PHY_DATA_OR:
2019 predata |= data;
2020 index++;
2021 break;
2022 case PHY_DATA_AND:
2023 predata &= data;
2024 index++;
2025 break;
2026 case PHY_BJMPN:
2027 index -= regno;
2028 break;
2029 case PHY_READ_EFUSE:
2030 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2031 index++;
2032 break;
2033 case PHY_CLEAR_READCOUNT:
2034 count = 0;
2035 index++;
2036 break;
bca03d5f 2037 case PHY_WRITE:
42b82dc1 2038 rtl_writephy(tp, regno, data);
2039 index++;
2040 break;
2041 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2042 index += (count == data) ? 2 : 1;
bca03d5f 2043 break;
42b82dc1 2044 case PHY_COMP_EQ_SKIPN:
2045 if (predata == data)
2046 index += regno;
2047 index++;
2048 break;
2049 case PHY_COMP_NEQ_SKIPN:
2050 if (predata != data)
2051 index += regno;
2052 index++;
2053 break;
2054 case PHY_WRITE_PREVIOUS:
2055 rtl_writephy(tp, regno, predata);
2056 index++;
2057 break;
2058 case PHY_SKIPN:
2059 index += regno + 1;
2060 break;
2061 case PHY_DELAY_MS:
2062 mdelay(data);
2063 index++;
2064 break;
2065
2066 case PHY_READ_MAC_BYTE:
2067 case PHY_WRITE_MAC_BYTE:
2068 case PHY_WRITE_ERI_WORD:
bca03d5f 2069 default:
2070 BUG();
2071 }
2072 }
2073}
2074
f1e02ed1 2075static void rtl_release_firmware(struct rtl8169_private *tp)
2076{
b6ffd97f
FR		 2077 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2078 release_firmware(tp->rtl_fw->fw);
2079 kfree(tp->rtl_fw);
2080 }
2081 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2082}
2083
953a12cc 2084static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2085{
b6ffd97f 2086 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2087
2088 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2089 if (!IS_ERR_OR_NULL(rtl_fw))
2090 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2091}
2092
2093static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2094{
2095 if (rtl_readphy(tp, reg) != val)
2096 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2097 else
2098 rtl_apply_firmware(tp);
f1e02ed1 2099}
2100
4da19633 2101static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2102{
350f7596 2103 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2104 { 0x1f, 0x0001 },
2105 { 0x06, 0x006e },
2106 { 0x08, 0x0708 },
2107 { 0x15, 0x4000 },
2108 { 0x18, 0x65c7 },
1da177e4 2109
0b9b571d 2110 { 0x1f, 0x0001 },
2111 { 0x03, 0x00a1 },
2112 { 0x02, 0x0008 },
2113 { 0x01, 0x0120 },
2114 { 0x00, 0x1000 },
2115 { 0x04, 0x0800 },
2116 { 0x04, 0x0000 },
1da177e4 2117
0b9b571d 2118 { 0x03, 0xff41 },
2119 { 0x02, 0xdf60 },
2120 { 0x01, 0x0140 },
2121 { 0x00, 0x0077 },
2122 { 0x04, 0x7800 },
2123 { 0x04, 0x7000 },
2124
2125 { 0x03, 0x802f },
2126 { 0x02, 0x4f02 },
2127 { 0x01, 0x0409 },
2128 { 0x00, 0xf0f9 },
2129 { 0x04, 0x9800 },
2130 { 0x04, 0x9000 },
2131
2132 { 0x03, 0xdf01 },
2133 { 0x02, 0xdf20 },
2134 { 0x01, 0xff95 },
2135 { 0x00, 0xba00 },
2136 { 0x04, 0xa800 },
2137 { 0x04, 0xa000 },
2138
2139 { 0x03, 0xff41 },
2140 { 0x02, 0xdf20 },
2141 { 0x01, 0x0140 },
2142 { 0x00, 0x00bb },
2143 { 0x04, 0xb800 },
2144 { 0x04, 0xb000 },
2145
2146 { 0x03, 0xdf41 },
2147 { 0x02, 0xdc60 },
2148 { 0x01, 0x6340 },
2149 { 0x00, 0x007d },
2150 { 0x04, 0xd800 },
2151 { 0x04, 0xd000 },
2152
2153 { 0x03, 0xdf01 },
2154 { 0x02, 0xdf20 },
2155 { 0x01, 0x100a },
2156 { 0x00, 0xa0ff },
2157 { 0x04, 0xf800 },
2158 { 0x04, 0xf000 },
2159
2160 { 0x1f, 0x0000 },
2161 { 0x0b, 0x0000 },
2162 { 0x00, 0x9200 }
2163 };
1da177e4 2164
4da19633 2165 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2166}
2167
4da19633 2168static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2169{
350f7596 2170 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2171 { 0x1f, 0x0002 },
2172 { 0x01, 0x90d0 },
2173 { 0x1f, 0x0000 }
2174 };
2175
4da19633 2176 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2177}
2178
4da19633 2179static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2180{
2181 struct pci_dev *pdev = tp->pci_dev;
2e955856 2182
ccbae55e
SS		 2183 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2184 (pdev->subsystem_device != 0xe000))
2e955856 2185 return;
2186
4da19633 2187 rtl_writephy(tp, 0x1f, 0x0001);
2188 rtl_writephy(tp, 0x10, 0xf01b);
2189 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2190}
2191
4da19633 2192static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2193{
350f7596 2194 static const struct phy_reg phy_reg_init[] = {
2e955856 2195 { 0x1f, 0x0001 },
2196 { 0x04, 0x0000 },
2197 { 0x03, 0x00a1 },
2198 { 0x02, 0x0008 },
2199 { 0x01, 0x0120 },
2200 { 0x00, 0x1000 },
2201 { 0x04, 0x0800 },
2202 { 0x04, 0x9000 },
2203 { 0x03, 0x802f },
2204 { 0x02, 0x4f02 },
2205 { 0x01, 0x0409 },
2206 { 0x00, 0xf099 },
2207 { 0x04, 0x9800 },
2208 { 0x04, 0xa000 },
2209 { 0x03, 0xdf01 },
2210 { 0x02, 0xdf20 },
2211 { 0x01, 0xff95 },
2212 { 0x00, 0xba00 },
2213 { 0x04, 0xa800 },
2214 { 0x04, 0xf000 },
2215 { 0x03, 0xdf01 },
2216 { 0x02, 0xdf20 },
2217 { 0x01, 0x101a },
2218 { 0x00, 0xa0ff },
2219 { 0x04, 0xf800 },
2220 { 0x04, 0x0000 },
2221 { 0x1f, 0x0000 },
2222
2223 { 0x1f, 0x0001 },
2224 { 0x10, 0xf41b },
2225 { 0x14, 0xfb54 },
2226 { 0x18, 0xf5c7 },
2227 { 0x1f, 0x0000 },
2228
2229 { 0x1f, 0x0001 },
2230 { 0x17, 0x0cc0 },
2231 { 0x1f, 0x0000 }
2232 };
2233
4da19633 2234 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2235
4da19633 2236 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2237}
2238
4da19633 2239static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2240{
350f7596 2241 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2242 { 0x1f, 0x0001 },
2243 { 0x04, 0x0000 },
2244 { 0x03, 0x00a1 },
2245 { 0x02, 0x0008 },
2246 { 0x01, 0x0120 },
2247 { 0x00, 0x1000 },
2248 { 0x04, 0x0800 },
2249 { 0x04, 0x9000 },
2250 { 0x03, 0x802f },
2251 { 0x02, 0x4f02 },
2252 { 0x01, 0x0409 },
2253 { 0x00, 0xf099 },
2254 { 0x04, 0x9800 },
2255 { 0x04, 0xa000 },
2256 { 0x03, 0xdf01 },
2257 { 0x02, 0xdf20 },
2258 { 0x01, 0xff95 },
2259 { 0x00, 0xba00 },
2260 { 0x04, 0xa800 },
2261 { 0x04, 0xf000 },
2262 { 0x03, 0xdf01 },
2263 { 0x02, 0xdf20 },
2264 { 0x01, 0x101a },
2265 { 0x00, 0xa0ff },
2266 { 0x04, 0xf800 },
2267 { 0x04, 0x0000 },
2268 { 0x1f, 0x0000 },
2269
2270 { 0x1f, 0x0001 },
2271 { 0x0b, 0x8480 },
2272 { 0x1f, 0x0000 },
2273
2274 { 0x1f, 0x0001 },
2275 { 0x18, 0x67c7 },
2276 { 0x04, 0x2000 },
2277 { 0x03, 0x002f },
2278 { 0x02, 0x4360 },
2279 { 0x01, 0x0109 },
2280 { 0x00, 0x3022 },
2281 { 0x04, 0x2800 },
2282 { 0x1f, 0x0000 },
2283
2284 { 0x1f, 0x0001 },
2285 { 0x17, 0x0cc0 },
2286 { 0x1f, 0x0000 }
2287 };
2288
4da19633 2289 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2290}
2291
4da19633 2292static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2293{
350f7596 2294 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2295 { 0x10, 0xf41b },
2296 { 0x1f, 0x0000 }
2297 };
2298
4da19633 2299 rtl_writephy(tp, 0x1f, 0x0001);
2300 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2301
4da19633 2302 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2303}
2304
4da19633 2305static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2306{
350f7596 2307 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2308 { 0x1f, 0x0001 },
2309 { 0x10, 0xf41b },
2310 { 0x1f, 0x0000 }
2311 };
2312
4da19633 2313 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2314}
2315
4da19633 2316static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2317{
350f7596 2318 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2319 { 0x1f, 0x0000 },
2320 { 0x1d, 0x0f00 },
2321 { 0x1f, 0x0002 },
2322 { 0x0c, 0x1ec8 },
2323 { 0x1f, 0x0000 }
2324 };
2325
4da19633 2326 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2327}
2328
4da19633 2329static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2330{
350f7596 2331 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2332 { 0x1f, 0x0001 },
2333 { 0x1d, 0x3d98 },
2334 { 0x1f, 0x0000 }
2335 };
2336
4da19633 2337 rtl_writephy(tp, 0x1f, 0x0000);
2338 rtl_patchphy(tp, 0x14, 1 << 5);
2339 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2340
4da19633 2341 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2342}
2343
4da19633 2344static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2345{
350f7596 2346 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2347 { 0x1f, 0x0001 },
2348 { 0x12, 0x2300 },
867763c1
FR		 2349 { 0x1f, 0x0002 },
2350 { 0x00, 0x88d4 },
2351 { 0x01, 0x82b1 },
2352 { 0x03, 0x7002 },
2353 { 0x08, 0x9e30 },
2354 { 0x09, 0x01f0 },
2355 { 0x0a, 0x5500 },
2356 { 0x0c, 0x00c8 },
2357 { 0x1f, 0x0003 },
2358 { 0x12, 0xc096 },
2359 { 0x16, 0x000a },
f50d4275
FR		 2360 { 0x1f, 0x0000 },
2361 { 0x1f, 0x0000 },
2362 { 0x09, 0x2000 },
2363 { 0x09, 0x0000 }
867763c1
FR		 2364 };
2365
4da19633 2366 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2367
4da19633 2368 rtl_patchphy(tp, 0x14, 1 << 5);
2369 rtl_patchphy(tp, 0x0d, 1 << 5);
2370 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2371}
2372
4da19633 2373static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2374{
350f7596 2375 static const struct phy_reg phy_reg_init[] = {
f50d4275 2376 { 0x1f, 0x0001 },
7da97ec9 2377 { 0x12, 0x2300 },
f50d4275
FR		 2378 { 0x03, 0x802f },
2379 { 0x02, 0x4f02 },
2380 { 0x01, 0x0409 },
2381 { 0x00, 0xf099 },
2382 { 0x04, 0x9800 },
2383 { 0x04, 0x9000 },
2384 { 0x1d, 0x3d98 },
7da97ec9
FR		 2385 { 0x1f, 0x0002 },
2386 { 0x0c, 0x7eb8 },
f50d4275
FR		 2387 { 0x06, 0x0761 },
2388 { 0x1f, 0x0003 },
2389 { 0x16, 0x0f0a },
7da97ec9
FR		 2390 { 0x1f, 0x0000 }
2391 };
2392
4da19633 2393 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2394
4da19633 2395 rtl_patchphy(tp, 0x16, 1 << 0);
2396 rtl_patchphy(tp, 0x14, 1 << 5);
2397 rtl_patchphy(tp, 0x0d, 1 << 5);
2398 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2399}
2400
4da19633 2401static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2402{
350f7596 2403 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2404 { 0x1f, 0x0001 },
2405 { 0x12, 0x2300 },
2406 { 0x1d, 0x3d98 },
2407 { 0x1f, 0x0002 },
2408 { 0x0c, 0x7eb8 },
2409 { 0x06, 0x5461 },
2410 { 0x1f, 0x0003 },
2411 { 0x16, 0x0f0a },
2412 { 0x1f, 0x0000 }
2413 };
2414
4da19633 2415 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2416
4da19633 2417 rtl_patchphy(tp, 0x16, 1 << 0);
2418 rtl_patchphy(tp, 0x14, 1 << 5);
2419 rtl_patchphy(tp, 0x0d, 1 << 5);
2420 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2421}
2422
4da19633 2423static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2424{
4da19633 2425 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2426}
2427
bca03d5f 2428static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2429{
350f7596 2430 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2431 /* Channel Estimation */
5b538df9 2432 { 0x1f, 0x0001 },
daf9df6d 2433 { 0x06, 0x4064 },
2434 { 0x07, 0x2863 },
2435 { 0x08, 0x059c },
2436 { 0x09, 0x26b4 },
2437 { 0x0a, 0x6a19 },
2438 { 0x0b, 0xdcc8 },
2439 { 0x10, 0xf06d },
2440 { 0x14, 0x7f68 },
2441 { 0x18, 0x7fd9 },
2442 { 0x1c, 0xf0ff },
2443 { 0x1d, 0x3d9c },
5b538df9 2444 { 0x1f, 0x0003 },
daf9df6d 2445 { 0x12, 0xf49f },
2446 { 0x13, 0x070b },
2447 { 0x1a, 0x05ad },
bca03d5f 2448 { 0x14, 0x94c0 },
2449
2450 /*
2451 * Tx Error Issue
cecb5fd7 2452 * Enhance line driver power
bca03d5f 2453 */
5b538df9 2454 { 0x1f, 0x0002 },
daf9df6d 2455 { 0x06, 0x5561 },
2456 { 0x1f, 0x0005 },
2457 { 0x05, 0x8332 },
bca03d5f 2458 { 0x06, 0x5561 },
2459
2460 /*
2461 * Can not link to 1Gbps with bad cable
2462 * Decrease SNR threshold form 21.07dB to 19.04dB
2463 */
2464 { 0x1f, 0x0001 },
2465 { 0x17, 0x0cc0 },
daf9df6d 2466
5b538df9 2467 { 0x1f, 0x0000 },
bca03d5f 2468 { 0x0d, 0xf880 }
daf9df6d 2469 };
bca03d5f 2470 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2471
4da19633 2472 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2473
bca03d5f 2474 /*
2475 * Rx Error Issue
2476 * Fine Tune Switching regulator parameter
2477 */
4da19633 2478 rtl_writephy(tp, 0x1f, 0x0002);
2479 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2480 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2481
daf9df6d 2482 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2483 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2484 { 0x1f, 0x0002 },
2485 { 0x05, 0x669a },
2486 { 0x1f, 0x0005 },
2487 { 0x05, 0x8330 },
2488 { 0x06, 0x669a },
2489 { 0x1f, 0x0002 }
2490 };
2491 int val;
2492
4da19633 2493 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2494
4da19633 2495 val = rtl_readphy(tp, 0x0d);
daf9df6d 2496
2497 if ((val & 0x00ff) != 0x006c) {
350f7596 2498 static const u32 set[] = {
daf9df6d 2499 0x0065, 0x0066, 0x0067, 0x0068,
2500 0x0069, 0x006a, 0x006b, 0x006c
2501 };
2502 int i;
2503
4da19633 2504 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2505
2506 val &= 0xff00;
2507 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2508 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2509 }
2510 } else {
350f7596 2511 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2512 { 0x1f, 0x0002 },
2513 { 0x05, 0x6662 },
2514 { 0x1f, 0x0005 },
2515 { 0x05, 0x8330 },
2516 { 0x06, 0x6662 }
2517 };
2518
4da19633 2519 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2520 }
2521
bca03d5f 2522 /* RSET couple improve */
4da19633 2523 rtl_writephy(tp, 0x1f, 0x0002);
2524 rtl_patchphy(tp, 0x0d, 0x0300);
2525 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2526
bca03d5f 2527 /* Fine tune PLL performance */
4da19633 2528 rtl_writephy(tp, 0x1f, 0x0002);
2529 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2530 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2531
4da19633 2532 rtl_writephy(tp, 0x1f, 0x0005);
2533 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2534
2535 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2536
4da19633 2537 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2538}
2539
bca03d5f 2540static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2541{
350f7596 2542 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2543 /* Channel Estimation */
daf9df6d 2544 { 0x1f, 0x0001 },
2545 { 0x06, 0x4064 },
2546 { 0x07, 0x2863 },
2547 { 0x08, 0x059c },
2548 { 0x09, 0x26b4 },
2549 { 0x0a, 0x6a19 },
2550 { 0x0b, 0xdcc8 },
2551 { 0x10, 0xf06d },
2552 { 0x14, 0x7f68 },
2553 { 0x18, 0x7fd9 },
2554 { 0x1c, 0xf0ff },
2555 { 0x1d, 0x3d9c },
2556 { 0x1f, 0x0003 },
2557 { 0x12, 0xf49f },
2558 { 0x13, 0x070b },
2559 { 0x1a, 0x05ad },
2560 { 0x14, 0x94c0 },
2561
bca03d5f 2562 /*
2563 * Tx Error Issue
cecb5fd7 2564 * Enhance line driver power
bca03d5f 2565 */
daf9df6d 2566 { 0x1f, 0x0002 },
2567 { 0x06, 0x5561 },
2568 { 0x1f, 0x0005 },
2569 { 0x05, 0x8332 },
bca03d5f 2570 { 0x06, 0x5561 },
2571
2572 /*
2573 * Can not link to 1Gbps with bad cable
2574 * Decrease SNR threshold form 21.07dB to 19.04dB
2575 */
2576 { 0x1f, 0x0001 },
2577 { 0x17, 0x0cc0 },
daf9df6d 2578
2579 { 0x1f, 0x0000 },
bca03d5f 2580 { 0x0d, 0xf880 }
5b538df9 2581 };
bca03d5f 2582 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2583
4da19633 2584 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2585
daf9df6d 2586 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2587 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2588 { 0x1f, 0x0002 },
2589 { 0x05, 0x669a },
5b538df9 2590 { 0x1f, 0x0005 },
daf9df6d 2591 { 0x05, 0x8330 },
2592 { 0x06, 0x669a },
2593
2594 { 0x1f, 0x0002 }
2595 };
2596 int val;
2597
4da19633 2598 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2599
4da19633 2600 val = rtl_readphy(tp, 0x0d);
daf9df6d 2601 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2602 static const u32 set[] = {
daf9df6d 2603 0x0065, 0x0066, 0x0067, 0x0068,
2604 0x0069, 0x006a, 0x006b, 0x006c
2605 };
2606 int i;
2607
4da19633 2608 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2609
2610 val &= 0xff00;
2611 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2612 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2613 }
2614 } else {
350f7596 2615 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2616 { 0x1f, 0x0002 },
2617 { 0x05, 0x2642 },
5b538df9 2618 { 0x1f, 0x0005 },
daf9df6d 2619 { 0x05, 0x8330 },
2620 { 0x06, 0x2642 }
5b538df9
FR		 2621 };
2622
4da19633 2623 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2624 }
2625
bca03d5f 2626 /* Fine tune PLL performance */
4da19633 2627 rtl_writephy(tp, 0x1f, 0x0002);
2628 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2629 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2630
bca03d5f 2631 /* Switching regulator Slew rate */
4da19633 2632 rtl_writephy(tp, 0x1f, 0x0002);
2633 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2634
4da19633 2635 rtl_writephy(tp, 0x1f, 0x0005);
2636 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2637
2638 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2639
4da19633 2640 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2641}
2642
4da19633 2643static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2644{
350f7596 2645 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2646 { 0x1f, 0x0002 },
2647 { 0x10, 0x0008 },
2648 { 0x0d, 0x006c },
2649
2650 { 0x1f, 0x0000 },
2651 { 0x0d, 0xf880 },
2652
2653 { 0x1f, 0x0001 },
2654 { 0x17, 0x0cc0 },
2655
2656 { 0x1f, 0x0001 },
2657 { 0x0b, 0xa4d8 },
2658 { 0x09, 0x281c },
2659 { 0x07, 0x2883 },
2660 { 0x0a, 0x6b35 },
2661 { 0x1d, 0x3da4 },
2662 { 0x1c, 0xeffd },
2663 { 0x14, 0x7f52 },
2664 { 0x18, 0x7fc6 },
2665 { 0x08, 0x0601 },
2666 { 0x06, 0x4063 },
2667 { 0x10, 0xf074 },
2668 { 0x1f, 0x0003 },
2669 { 0x13, 0x0789 },
2670 { 0x12, 0xf4bd },
2671 { 0x1a, 0x04fd },
2672 { 0x14, 0x84b0 },
2673 { 0x1f, 0x0000 },
2674 { 0x00, 0x9200 },
2675
2676 { 0x1f, 0x0005 },
2677 { 0x01, 0x0340 },
2678 { 0x1f, 0x0001 },
2679 { 0x04, 0x4000 },
2680 { 0x03, 0x1d21 },
2681 { 0x02, 0x0c32 },
2682 { 0x01, 0x0200 },
2683 { 0x00, 0x5554 },
2684 { 0x04, 0x4800 },
2685 { 0x04, 0x4000 },
2686 { 0x04, 0xf000 },
2687 { 0x03, 0xdf01 },
2688 { 0x02, 0xdf20 },
2689 { 0x01, 0x101a },
2690 { 0x00, 0xa0ff },
2691 { 0x04, 0xf800 },
2692 { 0x04, 0xf000 },
2693 { 0x1f, 0x0000 },
2694
2695 { 0x1f, 0x0007 },
2696 { 0x1e, 0x0023 },
2697 { 0x16, 0x0000 },
2698 { 0x1f, 0x0000 }
2699 };
2700
4da19633 2701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2702}
2703
e6de30d6 2704static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2705{
2706 static const struct phy_reg phy_reg_init[] = {
2707 { 0x1f, 0x0001 },
2708 { 0x17, 0x0cc0 },
2709
2710 { 0x1f, 0x0007 },
2711 { 0x1e, 0x002d },
2712 { 0x18, 0x0040 },
2713 { 0x1f, 0x0000 }
2714 };
2715
2716 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2717 rtl_patchphy(tp, 0x0d, 1 << 5);
2718}
2719
70090424 2720static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2721{
2722 static const struct phy_reg phy_reg_init[] = {
2723 /* Enable Delay cap */
2724 { 0x1f, 0x0005 },
2725 { 0x05, 0x8b80 },
2726 { 0x06, 0xc896 },
2727 { 0x1f, 0x0000 },
2728
2729 /* Channel estimation fine tune */
2730 { 0x1f, 0x0001 },
2731 { 0x0b, 0x6c20 },
2732 { 0x07, 0x2872 },
2733 { 0x1c, 0xefff },
2734 { 0x1f, 0x0003 },
2735 { 0x14, 0x6420 },
2736 { 0x1f, 0x0000 },
2737
2738 /* Update PFM & 10M TX idle timer */
2739 { 0x1f, 0x0007 },
2740 { 0x1e, 0x002f },
2741 { 0x15, 0x1919 },
2742 { 0x1f, 0x0000 },
2743
2744 { 0x1f, 0x0007 },
2745 { 0x1e, 0x00ac },
2746 { 0x18, 0x0006 },
2747 { 0x1f, 0x0000 }
2748 };
2749
15ecd039
FR		 2750 rtl_apply_firmware(tp);
2751
01dc7fec 2752 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2753
2754 /* DCO enable for 10M IDLE Power */
2755 rtl_writephy(tp, 0x1f, 0x0007);
2756 rtl_writephy(tp, 0x1e, 0x0023);
2757 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2758 rtl_writephy(tp, 0x1f, 0x0000);
2759
2760 /* For impedance matching */
2761 rtl_writephy(tp, 0x1f, 0x0002);
2762 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2763 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2764
2765 /* PHY auto speed down */
2766 rtl_writephy(tp, 0x1f, 0x0007);
2767 rtl_writephy(tp, 0x1e, 0x002d);
2768 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2769 rtl_writephy(tp, 0x1f, 0x0000);
2770 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2771
2772 rtl_writephy(tp, 0x1f, 0x0005);
2773 rtl_writephy(tp, 0x05, 0x8b86);
2774 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2775 rtl_writephy(tp, 0x1f, 0x0000);
2776
2777 rtl_writephy(tp, 0x1f, 0x0005);
2778 rtl_writephy(tp, 0x05, 0x8b85);
2779 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2780 rtl_writephy(tp, 0x1f, 0x0007);
2781 rtl_writephy(tp, 0x1e, 0x0020);
2782 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2783 rtl_writephy(tp, 0x1f, 0x0006);
2784 rtl_writephy(tp, 0x00, 0x5a00);
2785 rtl_writephy(tp, 0x1f, 0x0000);
2786 rtl_writephy(tp, 0x0d, 0x0007);
2787 rtl_writephy(tp, 0x0e, 0x003c);
2788 rtl_writephy(tp, 0x0d, 0x4007);
2789 rtl_writephy(tp, 0x0e, 0x0000);
2790 rtl_writephy(tp, 0x0d, 0x0000);
2791}
2792
70090424
HW		 2793static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2794{
2795 static const struct phy_reg phy_reg_init[] = {
2796 /* Enable Delay cap */
2797 { 0x1f, 0x0004 },
2798 { 0x1f, 0x0007 },
2799 { 0x1e, 0x00ac },
2800 { 0x18, 0x0006 },
2801 { 0x1f, 0x0002 },
2802 { 0x1f, 0x0000 },
2803 { 0x1f, 0x0000 },
2804
2805 /* Channel estimation fine tune */
2806 { 0x1f, 0x0003 },
2807 { 0x09, 0xa20f },
2808 { 0x1f, 0x0000 },
2809 { 0x1f, 0x0000 },
2810
2811 /* Green Setting */
2812 { 0x1f, 0x0005 },
2813 { 0x05, 0x8b5b },
2814 { 0x06, 0x9222 },
2815 { 0x05, 0x8b6d },
2816 { 0x06, 0x8000 },
2817 { 0x05, 0x8b76 },
2818 { 0x06, 0x8000 },
2819 { 0x1f, 0x0000 }
2820 };
2821
2822 rtl_apply_firmware(tp);
2823
2824 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2825
2826 /* For 4-corner performance improve */
2827 rtl_writephy(tp, 0x1f, 0x0005);
2828 rtl_writephy(tp, 0x05, 0x8b80);
2829 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2830 rtl_writephy(tp, 0x1f, 0x0000);
2831
2832 /* PHY auto speed down */
2833 rtl_writephy(tp, 0x1f, 0x0004);
2834 rtl_writephy(tp, 0x1f, 0x0007);
2835 rtl_writephy(tp, 0x1e, 0x002d);
2836 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2837 rtl_writephy(tp, 0x1f, 0x0002);
2838 rtl_writephy(tp, 0x1f, 0x0000);
2839 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2840
2841 /* improve 10M EEE waveform */
2842 rtl_writephy(tp, 0x1f, 0x0005);
2843 rtl_writephy(tp, 0x05, 0x8b86);
2844 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2845 rtl_writephy(tp, 0x1f, 0x0000);
2846
2847 /* Improve 2-pair detection performance */
2848 rtl_writephy(tp, 0x1f, 0x0005);
2849 rtl_writephy(tp, 0x05, 0x8b85);
2850 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2851 rtl_writephy(tp, 0x1f, 0x0000);
2852
2853 /* EEE setting */
2854 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2855 ERIAR_EXGMAC);
2856 rtl_writephy(tp, 0x1f, 0x0005);
2857 rtl_writephy(tp, 0x05, 0x8b85);
2858 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2859 rtl_writephy(tp, 0x1f, 0x0004);
2860 rtl_writephy(tp, 0x1f, 0x0007);
2861 rtl_writephy(tp, 0x1e, 0x0020);
2862 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2863 rtl_writephy(tp, 0x1f, 0x0002);
2864 rtl_writephy(tp, 0x1f, 0x0000);
2865 rtl_writephy(tp, 0x0d, 0x0007);
2866 rtl_writephy(tp, 0x0e, 0x003c);
2867 rtl_writephy(tp, 0x0d, 0x4007);
2868 rtl_writephy(tp, 0x0e, 0x0000);
2869 rtl_writephy(tp, 0x0d, 0x0000);
2870
2871 /* Green feature */
2872 rtl_writephy(tp, 0x1f, 0x0003);
2873 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2874 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2875 rtl_writephy(tp, 0x1f, 0x0000);
2876}
2877
4da19633 2878static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2879{
350f7596 2880 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2881 { 0x1f, 0x0003 },
2882 { 0x08, 0x441d },
2883 { 0x01, 0x9100 },
2884 { 0x1f, 0x0000 }
2885 };
2886
4da19633 2887 rtl_writephy(tp, 0x1f, 0x0000);
2888 rtl_patchphy(tp, 0x11, 1 << 12);
2889 rtl_patchphy(tp, 0x19, 1 << 13);
2890 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2891
4da19633 2892 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2893}
2894
5a5e4443
HW		 2895static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2896{
2897 static const struct phy_reg phy_reg_init[] = {
2898 { 0x1f, 0x0005 },
2899 { 0x1a, 0x0000 },
2900 { 0x1f, 0x0000 },
2901
2902 { 0x1f, 0x0004 },
2903 { 0x1c, 0x0000 },
2904 { 0x1f, 0x0000 },
2905
2906 { 0x1f, 0x0001 },
2907 { 0x15, 0x7701 },
2908 { 0x1f, 0x0000 }
2909 };
2910
2911 /* Disable ALDPS before ram code */
2912 rtl_writephy(tp, 0x1f, 0x0000);
2913 rtl_writephy(tp, 0x18, 0x0310);
2914 msleep(100);
2915
953a12cc 2916 rtl_apply_firmware(tp);
5a5e4443
HW		 2917
2918 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2919}
2920
5615d9f1
FR		 2921static void rtl_hw_phy_config(struct net_device *dev)
2922{
2923 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2924
2925 rtl8169_print_mac_version(tp);
2926
2927 switch (tp->mac_version) {
2928 case RTL_GIGA_MAC_VER_01:
2929 break;
2930 case RTL_GIGA_MAC_VER_02:
2931 case RTL_GIGA_MAC_VER_03:
4da19633 2932 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2933 break;
2934 case RTL_GIGA_MAC_VER_04:
4da19633 2935 rtl8169sb_hw_phy_config(tp);
5615d9f1 2936 break;
2e955856 2937 case RTL_GIGA_MAC_VER_05:
4da19633 2938 rtl8169scd_hw_phy_config(tp);
2e955856 2939 break;
8c7006aa 2940 case RTL_GIGA_MAC_VER_06:
4da19633 2941 rtl8169sce_hw_phy_config(tp);
8c7006aa 2942 break;
2857ffb7
FR		 2943 case RTL_GIGA_MAC_VER_07:
2944 case RTL_GIGA_MAC_VER_08:
2945 case RTL_GIGA_MAC_VER_09:
4da19633 2946 rtl8102e_hw_phy_config(tp);
2857ffb7 2947 break;
236b8082 2948 case RTL_GIGA_MAC_VER_11:
4da19633 2949 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2950 break;
2951 case RTL_GIGA_MAC_VER_12:
4da19633 2952 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2953 break;
2954 case RTL_GIGA_MAC_VER_17:
4da19633 2955 rtl8168bef_hw_phy_config(tp);
236b8082 2956 break;
867763c1 2957 case RTL_GIGA_MAC_VER_18:
4da19633 2958 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2959 break;
2960 case RTL_GIGA_MAC_VER_19:
4da19633 2961 rtl8168c_1_hw_phy_config(tp);
867763c1 2962 break;
7da97ec9 2963 case RTL_GIGA_MAC_VER_20:
4da19633 2964 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2965 break;
197ff761 2966 case RTL_GIGA_MAC_VER_21:
4da19633 2967 rtl8168c_3_hw_phy_config(tp);
197ff761 2968 break;
6fb07058 2969 case RTL_GIGA_MAC_VER_22:
4da19633 2970 rtl8168c_4_hw_phy_config(tp);
6fb07058 2971 break;
ef3386f0 2972 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2973 case RTL_GIGA_MAC_VER_24:
4da19633 2974 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2975 break;
5b538df9 2976 case RTL_GIGA_MAC_VER_25:
bca03d5f 2977 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2978 break;
2979 case RTL_GIGA_MAC_VER_26:
bca03d5f 2980 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2981 break;
2982 case RTL_GIGA_MAC_VER_27:
4da19633 2983 rtl8168d_3_hw_phy_config(tp);
5b538df9 2984 break;
e6de30d6 2985 case RTL_GIGA_MAC_VER_28:
2986 rtl8168d_4_hw_phy_config(tp);
2987 break;
5a5e4443
HW		 2988 case RTL_GIGA_MAC_VER_29:
2989 case RTL_GIGA_MAC_VER_30:
2990 rtl8105e_hw_phy_config(tp);
2991 break;
cecb5fd7
FR		 2992 case RTL_GIGA_MAC_VER_31:
2993 /* None. */
2994 break;
01dc7fec 2995 case RTL_GIGA_MAC_VER_32:
01dc7fec 2996 case RTL_GIGA_MAC_VER_33:
70090424
HW		 2997 rtl8168e_1_hw_phy_config(tp);
2998 break;
2999 case RTL_GIGA_MAC_VER_34:
3000 rtl8168e_2_hw_phy_config(tp);
01dc7fec 3001 break;
ef3386f0 3002
5615d9f1
FR		 3003 default:
3004 break;
3005 }
3006}
3007
1da177e4
LT		 3008static void rtl8169_phy_timer(unsigned long __opaque)
3009{
3010 struct net_device *dev = (struct net_device *)__opaque;
3011 struct rtl8169_private *tp = netdev_priv(dev);
3012 struct timer_list *timer = &tp->timer;
3013 void __iomem *ioaddr = tp->mmio_addr;
3014 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3015
bcf0bf90 3016 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3017
1da177e4
LT		 3018 spin_lock_irq(&tp->lock);
3019
4da19633 3020 if (tp->phy_reset_pending(tp)) {
5b0384f4 3021 /*
1da177e4
LT		 3022 * A busy loop could burn quite a few cycles on nowadays CPU.
3023 * Let's delay the execution of the timer for a few ticks.
3024 */
3025 timeout = HZ/10;
3026 goto out_mod_timer;
3027 }
3028
3029 if (tp->link_ok(ioaddr))
3030 goto out_unlock;
3031
bf82c189 3032 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3033
4da19633 3034 tp->phy_reset_enable(tp);
1da177e4
LT		 3035
3036out_mod_timer:
3037 mod_timer(timer, jiffies + timeout);
3038out_unlock:
3039 spin_unlock_irq(&tp->lock);
3040}
3041
1da177e4
LT		 3042#ifdef CONFIG_NET_POLL_CONTROLLER
3043/*
3044 * Polling 'interrupt' - used by things like netconsole to send skbs
3045 * without having to re-enable interrupts. It's not called while
3046 * the interrupt routine is executing.
3047 */
3048static void rtl8169_netpoll(struct net_device *dev)
3049{
3050 struct rtl8169_private *tp = netdev_priv(dev);
3051 struct pci_dev *pdev = tp->pci_dev;
3052
3053 disable_irq(pdev->irq);
7d12e780 3054 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3055 enable_irq(pdev->irq);
3056}
3057#endif
3058
3059static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3060 void __iomem *ioaddr)
3061{
3062 iounmap(ioaddr);
3063 pci_release_regions(pdev);
87aeec76 3064 pci_clear_mwi(pdev);
1da177e4
LT		 3065 pci_disable_device(pdev);
3066 free_netdev(dev);
3067}
3068
bf793295
FR		 3069static void rtl8169_phy_reset(struct net_device *dev,
3070 struct rtl8169_private *tp)
3071{
07d3f51f 3072 unsigned int i;
bf793295 3073
4da19633 3074 tp->phy_reset_enable(tp);
bf793295 3075 for (i = 0; i < 100; i++) {
4da19633 3076 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3077 return;
3078 msleep(1);
3079 }
bf82c189 3080 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3081}
3082
4ff96fa6
FR		 3083static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3084{
3085 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3086
5615d9f1 3087 rtl_hw_phy_config(dev);
4ff96fa6 3088
77332894
MS		 3089 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3090 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3091 RTL_W8(0x82, 0x01);
3092 }
4ff96fa6 3093
6dccd16b
FR		 3094 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3095
3096 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3097 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3098
bcf0bf90 3099 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3100 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3101 RTL_W8(0x82, 0x01);
3102 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3103 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3104 }
3105
bf793295
FR		 3106 rtl8169_phy_reset(dev, tp);
3107
54405cde 3108 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3109 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3110 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3111 (tp->mii.supports_gmii ?
3112 ADVERTISED_1000baseT_Half |
3113 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3114
bf82c189
JP		 3115 if (RTL_R8(PHYstatus) & TBI_Enable)
3116 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3117}
3118
773d2021
FR		 3119static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3120{
3121 void __iomem *ioaddr = tp->mmio_addr;
3122 u32 high;
3123 u32 low;
3124
3125 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3126 high = addr[4] | (addr[5] << 8);
3127
3128 spin_lock_irq(&tp->lock);
3129
3130 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3131
773d2021 3132 RTL_W32(MAC4, high);
908ba2bf 3133 RTL_R32(MAC4);
3134
78f1cd02 3135 RTL_W32(MAC0, low);
908ba2bf 3136 RTL_R32(MAC0);
3137
c28aa385 3138 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3139 const struct exgmac_reg e[] = {
3140 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3141 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3142 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3143 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3144 low >> 16 },
3145 };
3146
3147 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3148 }
3149
773d2021
FR		 3150 RTL_W8(Cfg9346, Cfg9346_Lock);
3151
3152 spin_unlock_irq(&tp->lock);
3153}
3154
3155static int rtl_set_mac_address(struct net_device *dev, void *p)
3156{
3157 struct rtl8169_private *tp = netdev_priv(dev);
3158 struct sockaddr *addr = p;
3159
3160 if (!is_valid_ether_addr(addr->sa_data))
3161 return -EADDRNOTAVAIL;
3162
3163 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3164
3165 rtl_rar_set(tp, dev->dev_addr);
3166
3167 return 0;
3168}
3169
5f787a1a
FR		 3170static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3171{
3172 struct rtl8169_private *tp = netdev_priv(dev);
3173 struct mii_ioctl_data *data = if_mii(ifr);
3174
8b4ab28d
FR		 3175 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3176}
5f787a1a 3177
cecb5fd7
FR		 3178static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3179 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3180{
5f787a1a
FR		 3181 switch (cmd) {
3182 case SIOCGMIIPHY:
3183 data->phy_id = 32; /* Internal PHY */
3184 return 0;
3185
3186 case SIOCGMIIREG:
4da19633 3187 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3188 return 0;
3189
3190 case SIOCSMIIREG:
4da19633 3191 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3192 return 0;
3193 }
3194 return -EOPNOTSUPP;
3195}
3196
8b4ab28d
FR		 3197static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3198{
3199 return -EOPNOTSUPP;
3200}
3201
0e485150
FR		 3202static const struct rtl_cfg_info {
3203 void (*hw_start)(struct net_device *);
3204 unsigned int region;
3205 unsigned int align;
3206 u16 intr_event;
3207 u16 napi_event;
ccdffb9a 3208 unsigned features;
f21b75e9 3209 u8 default_ver;
0e485150
FR		 3210} rtl_cfg_infos [] = {
3211 [RTL_CFG_0] = {
3212 .hw_start = rtl_hw_start_8169,
3213 .region = 1,
e9f63f30 3214 .align = 0,
0e485150
FR		 3215 .intr_event = SYSErr | LinkChg | RxOverflow |
3216 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3217 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3218 .features = RTL_FEATURE_GMII,
3219 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3220 },
3221 [RTL_CFG_1] = {
3222 .hw_start = rtl_hw_start_8168,
3223 .region = 2,
3224 .align = 8,
53f57357 3225 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3226 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3227 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3228 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3229 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3230 },
3231 [RTL_CFG_2] = {
3232 .hw_start = rtl_hw_start_8101,
3233 .region = 2,
3234 .align = 8,
3235 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3236 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3237 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3238 .features = RTL_FEATURE_MSI,
3239 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3240 }
3241};
3242
fbac58fc
FR		 3243/* Cfg9346_Unlock assumed. */
3244static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3245 const struct rtl_cfg_info *cfg)
3246{
3247 unsigned msi = 0;
3248 u8 cfg2;
3249
3250 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3251 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 3252 if (pci_enable_msi(pdev)) {
3253 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3254 } else {
3255 cfg2 |= MSIEnable;
3256 msi = RTL_FEATURE_MSI;
3257 }
3258 }
3259 RTL_W8(Config2, cfg2);
3260 return msi;
3261}
3262
3263static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3264{
3265 if (tp->features & RTL_FEATURE_MSI) {
3266 pci_disable_msi(pdev);
3267 tp->features &= ~RTL_FEATURE_MSI;
3268 }
3269}
3270
8b4ab28d
FR		 3271static const struct net_device_ops rtl8169_netdev_ops = {
3272 .ndo_open = rtl8169_open,
3273 .ndo_stop = rtl8169_close,
3274 .ndo_get_stats = rtl8169_get_stats,
00829823 3275 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3276 .ndo_tx_timeout = rtl8169_tx_timeout,
3277 .ndo_validate_addr = eth_validate_addr,
3278 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3279 .ndo_fix_features = rtl8169_fix_features,
3280 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3281 .ndo_set_mac_address = rtl_set_mac_address,
3282 .ndo_do_ioctl = rtl8169_ioctl,
3283 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 3284#ifdef CONFIG_NET_POLL_CONTROLLER
3285 .ndo_poll_controller = rtl8169_netpoll,
3286#endif
3287
3288};
3289
c0e45c1c 3290static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3291{
3292 struct mdio_ops *ops = &tp->mdio_ops;
3293
3294 switch (tp->mac_version) {
3295 case RTL_GIGA_MAC_VER_27:
3296 ops->write = r8168dp_1_mdio_write;
3297 ops->read = r8168dp_1_mdio_read;
3298 break;
e6de30d6 3299 case RTL_GIGA_MAC_VER_28:
4804b3b3 3300 case RTL_GIGA_MAC_VER_31:
e6de30d6 3301 ops->write = r8168dp_2_mdio_write;
3302 ops->read = r8168dp_2_mdio_read;
3303 break;
c0e45c1c 3304 default:
3305 ops->write = r8169_mdio_write;
3306 ops->read = r8169_mdio_read;
3307 break;
3308 }
3309}
3310
065c27c1 3311static void r810x_phy_power_down(struct rtl8169_private *tp)
3312{
3313 rtl_writephy(tp, 0x1f, 0x0000);
3314 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3315}
3316
3317static void r810x_phy_power_up(struct rtl8169_private *tp)
3318{
3319 rtl_writephy(tp, 0x1f, 0x0000);
3320 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3321}
3322
3323static void r810x_pll_power_down(struct rtl8169_private *tp)
3324{
10663389
HW		 3325 void __iomem *ioaddr = tp->mmio_addr;
3326
065c27c1 3327 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3328 rtl_writephy(tp, 0x1f, 0x0000);
3329 rtl_writephy(tp, MII_BMCR, 0x0000);
10663389
HW		 3330
3331 if (tp->mac_version == RTL_GIGA_MAC_VER_29 ||
3332 tp->mac_version == RTL_GIGA_MAC_VER_30)
3333 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3334 AcceptMulticast | AcceptMyPhys);
065c27c1 3335 return;
3336 }
3337
3338 r810x_phy_power_down(tp);
3339}
3340
3341static void r810x_pll_power_up(struct rtl8169_private *tp)
3342{
3343 r810x_phy_power_up(tp);
3344}
3345
3346static void r8168_phy_power_up(struct rtl8169_private *tp)
3347{
3348 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3349 switch (tp->mac_version) {
3350 case RTL_GIGA_MAC_VER_11:
3351 case RTL_GIGA_MAC_VER_12:
3352 case RTL_GIGA_MAC_VER_17:
3353 case RTL_GIGA_MAC_VER_18:
3354 case RTL_GIGA_MAC_VER_19:
3355 case RTL_GIGA_MAC_VER_20:
3356 case RTL_GIGA_MAC_VER_21:
3357 case RTL_GIGA_MAC_VER_22:
3358 case RTL_GIGA_MAC_VER_23:
3359 case RTL_GIGA_MAC_VER_24:
3360 case RTL_GIGA_MAC_VER_25:
3361 case RTL_GIGA_MAC_VER_26:
3362 case RTL_GIGA_MAC_VER_27:
3363 case RTL_GIGA_MAC_VER_28:
3364 case RTL_GIGA_MAC_VER_31:
3365 rtl_writephy(tp, 0x0e, 0x0000);
3366 break;
3367 default:
3368 break;
3369 }
065c27c1 3370 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3371}
3372
3373static void r8168_phy_power_down(struct rtl8169_private *tp)
3374{
3375 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3376 switch (tp->mac_version) {
3377 case RTL_GIGA_MAC_VER_32:
3378 case RTL_GIGA_MAC_VER_33:
3379 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3380 break;
3381
3382 case RTL_GIGA_MAC_VER_11:
3383 case RTL_GIGA_MAC_VER_12:
3384 case RTL_GIGA_MAC_VER_17:
3385 case RTL_GIGA_MAC_VER_18:
3386 case RTL_GIGA_MAC_VER_19:
3387 case RTL_GIGA_MAC_VER_20:
3388 case RTL_GIGA_MAC_VER_21:
3389 case RTL_GIGA_MAC_VER_22:
3390 case RTL_GIGA_MAC_VER_23:
3391 case RTL_GIGA_MAC_VER_24:
3392 case RTL_GIGA_MAC_VER_25:
3393 case RTL_GIGA_MAC_VER_26:
3394 case RTL_GIGA_MAC_VER_27:
3395 case RTL_GIGA_MAC_VER_28:
3396 case RTL_GIGA_MAC_VER_31:
3397 rtl_writephy(tp, 0x0e, 0x0200);
3398 default:
3399 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3400 break;
3401 }
065c27c1 3402}
3403
3404static void r8168_pll_power_down(struct rtl8169_private *tp)
3405{
3406 void __iomem *ioaddr = tp->mmio_addr;
3407
cecb5fd7
FR		 3408 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3409 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3410 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3411 r8168dp_check_dash(tp)) {
065c27c1 3412 return;
5d2e1957 3413 }
065c27c1 3414
cecb5fd7
FR		 3415 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3416 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3417 (RTL_R16(CPlusCmd) & ASF)) {
3418 return;
3419 }
3420
01dc7fec 3421 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3422 tp->mac_version == RTL_GIGA_MAC_VER_33)
3423 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3424
065c27c1 3425 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3426 rtl_writephy(tp, 0x1f, 0x0000);
3427 rtl_writephy(tp, MII_BMCR, 0x0000);
3428
d4ed95d7 3429 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
10663389
HW		 3430 tp->mac_version == RTL_GIGA_MAC_VER_33 ||
3431 tp->mac_version == RTL_GIGA_MAC_VER_34)
d4ed95d7
HW		 3432 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3433 AcceptMulticast | AcceptMyPhys);
065c27c1 3434 return;
3435 }
3436
3437 r8168_phy_power_down(tp);
3438
3439 switch (tp->mac_version) {
3440 case RTL_GIGA_MAC_VER_25:
3441 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3442 case RTL_GIGA_MAC_VER_27:
3443 case RTL_GIGA_MAC_VER_28:
4804b3b3 3444 case RTL_GIGA_MAC_VER_31:
01dc7fec 3445 case RTL_GIGA_MAC_VER_32:
3446 case RTL_GIGA_MAC_VER_33:
065c27c1 3447 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3448 break;
3449 }
3450}
3451
3452static void r8168_pll_power_up(struct rtl8169_private *tp)
3453{
3454 void __iomem *ioaddr = tp->mmio_addr;
3455
cecb5fd7
FR		 3456 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3457 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3458 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3459 r8168dp_check_dash(tp)) {
065c27c1 3460 return;
5d2e1957 3461 }
065c27c1 3462
3463 switch (tp->mac_version) {
3464 case RTL_GIGA_MAC_VER_25:
3465 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3466 case RTL_GIGA_MAC_VER_27:
3467 case RTL_GIGA_MAC_VER_28:
4804b3b3 3468 case RTL_GIGA_MAC_VER_31:
01dc7fec 3469 case RTL_GIGA_MAC_VER_32:
3470 case RTL_GIGA_MAC_VER_33:
065c27c1 3471 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3472 break;
3473 }
3474
3475 r8168_phy_power_up(tp);
3476}
3477
3478static void rtl_pll_power_op(struct rtl8169_private *tp,
3479 void (*op)(struct rtl8169_private *))
3480{
3481 if (op)
3482 op(tp);
3483}
3484
3485static void rtl_pll_power_down(struct rtl8169_private *tp)
3486{
3487 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3488}
3489
3490static void rtl_pll_power_up(struct rtl8169_private *tp)
3491{
3492 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3493}
3494
3495static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3496{
3497 struct pll_power_ops *ops = &tp->pll_power_ops;
3498
3499 switch (tp->mac_version) {
3500 case RTL_GIGA_MAC_VER_07:
3501 case RTL_GIGA_MAC_VER_08:
3502 case RTL_GIGA_MAC_VER_09:
3503 case RTL_GIGA_MAC_VER_10:
3504 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3505 case RTL_GIGA_MAC_VER_29:
3506 case RTL_GIGA_MAC_VER_30:
065c27c1 3507 ops->down = r810x_pll_power_down;
3508 ops->up = r810x_pll_power_up;
3509 break;
3510
3511 case RTL_GIGA_MAC_VER_11:
3512 case RTL_GIGA_MAC_VER_12:
3513 case RTL_GIGA_MAC_VER_17:
3514 case RTL_GIGA_MAC_VER_18:
3515 case RTL_GIGA_MAC_VER_19:
3516 case RTL_GIGA_MAC_VER_20:
3517 case RTL_GIGA_MAC_VER_21:
3518 case RTL_GIGA_MAC_VER_22:
3519 case RTL_GIGA_MAC_VER_23:
3520 case RTL_GIGA_MAC_VER_24:
3521 case RTL_GIGA_MAC_VER_25:
3522 case RTL_GIGA_MAC_VER_26:
3523 case RTL_GIGA_MAC_VER_27:
e6de30d6 3524 case RTL_GIGA_MAC_VER_28:
4804b3b3 3525 case RTL_GIGA_MAC_VER_31:
01dc7fec 3526 case RTL_GIGA_MAC_VER_32:
3527 case RTL_GIGA_MAC_VER_33:
70090424 3528 case RTL_GIGA_MAC_VER_34:
065c27c1 3529 ops->down = r8168_pll_power_down;
3530 ops->up = r8168_pll_power_up;
3531 break;
3532
3533 default:
3534 ops->down = NULL;
3535 ops->up = NULL;
3536 break;
3537 }
3538}
3539
e542a226
HW		 3540static void rtl_init_rxcfg(struct rtl8169_private *tp)
3541{
3542 void __iomem *ioaddr = tp->mmio_addr;
3543
3544 switch (tp->mac_version) {
3545 case RTL_GIGA_MAC_VER_01:
3546 case RTL_GIGA_MAC_VER_02:
3547 case RTL_GIGA_MAC_VER_03:
3548 case RTL_GIGA_MAC_VER_04:
3549 case RTL_GIGA_MAC_VER_05:
3550 case RTL_GIGA_MAC_VER_06:
3551 case RTL_GIGA_MAC_VER_10:
3552 case RTL_GIGA_MAC_VER_11:
3553 case RTL_GIGA_MAC_VER_12:
3554 case RTL_GIGA_MAC_VER_13:
3555 case RTL_GIGA_MAC_VER_14:
3556 case RTL_GIGA_MAC_VER_15:
3557 case RTL_GIGA_MAC_VER_16:
3558 case RTL_GIGA_MAC_VER_17:
3559 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3560 break;
3561 case RTL_GIGA_MAC_VER_18:
3562 case RTL_GIGA_MAC_VER_19:
3563 case RTL_GIGA_MAC_VER_20:
3564 case RTL_GIGA_MAC_VER_21:
3565 case RTL_GIGA_MAC_VER_22:
3566 case RTL_GIGA_MAC_VER_23:
3567 case RTL_GIGA_MAC_VER_24:
3568 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3569 break;
3570 default:
3571 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3572 break;
3573 }
3574}
3575
92fc43b4
HW		 3576static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3577{
3578 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3579}
3580
6f43adc8
FR		 3581static void rtl_hw_reset(struct rtl8169_private *tp)
3582{
3583 void __iomem *ioaddr = tp->mmio_addr;
3584 int i;
3585
3586 /* Soft reset the chip. */
3587 RTL_W8(ChipCmd, CmdReset);
3588
3589 /* Check that the chip has finished the reset. */
3590 for (i = 0; i < 100; i++) {
3591 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3592 break;
92fc43b4 3593 udelay(100);
6f43adc8 3594 }
92fc43b4
HW		 3595
3596 rtl8169_init_ring_indexes(tp);
6f43adc8
FR		 3597}
3598
1da177e4 3599static int __devinit
4ff96fa6 3600rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3601{
0e485150
FR		 3602 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3603 const unsigned int region = cfg->region;
1da177e4 3604 struct rtl8169_private *tp;
ccdffb9a 3605 struct mii_if_info *mii;
4ff96fa6
FR		 3606 struct net_device *dev;
3607 void __iomem *ioaddr;
2b7b4318 3608 int chipset, i;
07d3f51f 3609 int rc;
1da177e4 3610
4ff96fa6
FR		 3611 if (netif_msg_drv(&debug)) {
3612 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3613 MODULENAME, RTL8169_VERSION);
3614 }
1da177e4 3615
1da177e4 3616 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3617 if (!dev) {
b57b7e5a 3618 if (netif_msg_drv(&debug))
9b91cf9d 3619 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3620 rc = -ENOMEM;
3621 goto out;
1da177e4
LT		 3622 }
3623
1da177e4 3624 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3625 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3626 tp = netdev_priv(dev);
c4028958 3627 tp->dev = dev;
21e197f2 3628 tp->pci_dev = pdev;
b57b7e5a 3629 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3630
ccdffb9a
FR		 3631 mii = &tp->mii;
3632 mii->dev = dev;
3633 mii->mdio_read = rtl_mdio_read;
3634 mii->mdio_write = rtl_mdio_write;
3635 mii->phy_id_mask = 0x1f;
3636 mii->reg_num_mask = 0x1f;
3637 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3638
ba04c7c9
SG		 3639 /* disable ASPM completely as that cause random device stop working
3640 * problems as well as full system hangs for some PCIe devices users */
3641 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3642 PCIE_LINK_STATE_CLKPM);
3643
1da177e4
LT		 3644 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3645 rc = pci_enable_device(pdev);
b57b7e5a 3646 if (rc < 0) {
bf82c189 3647 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3648 goto err_out_free_dev_1;
1da177e4
LT		 3649 }
3650
87aeec76 3651 if (pci_set_mwi(pdev) < 0)
3652 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3653
1da177e4 3654 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3655 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3656 netif_err(tp, probe, dev,
3657 "region #%d not an MMIO resource, aborting\n",
3658 region);
1da177e4 3659 rc = -ENODEV;
87aeec76 3660 goto err_out_mwi_2;
1da177e4 3661 }
4ff96fa6 3662
1da177e4 3663 /* check for weird/broken PCI region reporting */
bcf0bf90 3664 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3665 netif_err(tp, probe, dev,
3666 "Invalid PCI region size(s), aborting\n");
1da177e4 3667 rc = -ENODEV;
87aeec76 3668 goto err_out_mwi_2;
1da177e4
LT		 3669 }
3670
3671 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3672 if (rc < 0) {
bf82c189 3673 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3674 goto err_out_mwi_2;
1da177e4
LT		 3675 }
3676
d24e9aaf 3677 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3678
3679 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3680 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3681 tp->cp_cmd |= PCIDAC;
3682 dev->features |= NETIF_F_HIGHDMA;
3683 } else {
284901a9 3684 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3685 if (rc < 0) {
bf82c189 3686 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3687 goto err_out_free_res_3;
1da177e4
LT		 3688 }
3689 }
3690
1da177e4 3691 /* ioremap MMIO region */
bcf0bf90 3692 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3693 if (!ioaddr) {
bf82c189 3694 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3695 rc = -EIO;
87aeec76 3696 goto err_out_free_res_3;
1da177e4 3697 }
6f43adc8 3698 tp->mmio_addr = ioaddr;
1da177e4 3699
e44daade
JM		 3700 if (!pci_is_pcie(pdev))
3701 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 3702
e542a226
HW		 3703 /* Identify chip attached to board */
3704 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3705
3706 rtl_init_rxcfg(tp);
3707
d78ad8cb 3708 RTL_W16(IntrMask, 0x0000);
1da177e4 3709
6f43adc8 3710 rtl_hw_reset(tp);
1da177e4 3711
d78ad8cb
KW		 3712 RTL_W16(IntrStatus, 0xffff);
3713
ca52efd5 3714 pci_set_master(pdev);
3715
7a8fc77b
FR		 3716 /*
3717 * Pretend we are using VLANs; This bypasses a nasty bug where
3718 * Interrupts stop flowing on high load on 8110SCd controllers.
3719 */
3720 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3721 tp->cp_cmd |= RxVlan;
3722
c0e45c1c 3723 rtl_init_mdio_ops(tp);
065c27c1 3724 rtl_init_pll_power_ops(tp);
c0e45c1c 3725
1da177e4 3726 rtl8169_print_mac_version(tp);
1da177e4 3727
85bffe6c
FR		 3728 chipset = tp->mac_version;
3729 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3730
5d06a99f
FR		 3731 RTL_W8(Cfg9346, Cfg9346_Unlock);
3732 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3733 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3734 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3735 tp->features |= RTL_FEATURE_WOL;
3736 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3737 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3738 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3739 RTL_W8(Cfg9346, Cfg9346_Lock);
3740
66ec5d4f
FR		 3741 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3742 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3743 tp->set_speed = rtl8169_set_speed_tbi;
3744 tp->get_settings = rtl8169_gset_tbi;
3745 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3746 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3747 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3748 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3749 } else {
3750 tp->set_speed = rtl8169_set_speed_xmii;
3751 tp->get_settings = rtl8169_gset_xmii;
3752 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3753 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3754 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3755 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3756 }
3757
df58ef51
FR		 3758 spin_lock_init(&tp->lock);
3759
7bf6bf48 3760 /* Get MAC address */
1da177e4
LT		 3761 for (i = 0; i < MAC_ADDR_LEN; i++)
3762 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3763 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3764
1da177e4 3765 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3766 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3767 dev->irq = pdev->irq;
3768 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3769
bea3348e 3770 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3771
350fb32a
MM		 3772 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3773 * properly for all devices */
3774 dev->features |= NETIF_F_RXCSUM |
3775 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3776
3777 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3778 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3779 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3780 NETIF_F_HIGHDMA;
3781
3782 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3783 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3784 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3785
3786 tp->intr_mask = 0xffff;
0e485150
FR		 3787 tp->hw_start = cfg->hw_start;
3788 tp->intr_event = cfg->intr_event;
3789 tp->napi_event = cfg->napi_event;
1da177e4 3790
e03f33af
FR		 3791 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
3792 ~(RxBOVF | RxFOVF) : ~0;
3793
2efa53f3
FR		 3794 init_timer(&tp->timer);
3795 tp->timer.data = (unsigned long) dev;
3796 tp->timer.function = rtl8169_phy_timer;
3797
b6ffd97f 3798 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3799
1da177e4 3800 rc = register_netdev(dev);
4ff96fa6 3801 if (rc < 0)
87aeec76 3802 goto err_out_msi_4;
1da177e4
LT		 3803
3804 pci_set_drvdata(pdev, dev);
3805
bf82c189 3806 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3807 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3808 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3809
cecb5fd7
FR		 3810 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3811 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3812 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3813 rtl8168_driver_start(tp);
e6de30d6 3814 }
b646d900 3815
8b76ab39 3816 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3817
f3ec4f87
AS		 3818 if (pci_dev_run_wake(pdev))
3819 pm_runtime_put_noidle(&pdev->dev);
e1759441 3820
0d672e9f
IV		 3821 netif_carrier_off(dev);
3822
4ff96fa6
FR		 3823out:
3824 return rc;
1da177e4 3825
87aeec76 3826err_out_msi_4:
fbac58fc 3827 rtl_disable_msi(pdev, tp);
4ff96fa6 3828 iounmap(ioaddr);
87aeec76 3829err_out_free_res_3:
4ff96fa6 3830 pci_release_regions(pdev);
87aeec76 3831err_out_mwi_2:
4ff96fa6 3832 pci_clear_mwi(pdev);
4ff96fa6
FR		 3833 pci_disable_device(pdev);
3834err_out_free_dev_1:
3835 free_netdev(dev);
3836 goto out;
1da177e4
LT		 3837}
3838
07d3f51f 3839static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3840{
3841 struct net_device *dev = pci_get_drvdata(pdev);
3842 struct rtl8169_private *tp = netdev_priv(dev);
3843
cecb5fd7
FR		 3844 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3845 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3846 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3847 rtl8168_driver_stop(tp);
e6de30d6 3848 }
b646d900 3849
23f333a2 3850 cancel_delayed_work_sync(&tp->task);
eb2a021c 3851
1da177e4 3852 unregister_netdev(dev);
cc098dc7 3853
953a12cc
FR		 3854 rtl_release_firmware(tp);
3855
f3ec4f87
AS		 3856 if (pci_dev_run_wake(pdev))
3857 pm_runtime_get_noresume(&pdev->dev);
e1759441 3858
cc098dc7
IV		 3859 /* restore original MAC address */
3860 rtl_rar_set(tp, dev->perm_addr);
3861
fbac58fc 3862 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3863 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3864 pci_set_drvdata(pdev, NULL);
3865}
3866
b6ffd97f 3867static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3868{
b6ffd97f
FR		 3869 struct rtl_fw *rtl_fw;
3870 const char *name;
3871 int rc = -ENOMEM;
953a12cc 3872
b6ffd97f
FR		 3873 name = rtl_lookup_firmware_name(tp);
3874 if (!name)
3875 goto out_no_firmware;
953a12cc 3876
b6ffd97f
FR		 3877 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3878 if (!rtl_fw)
3879 goto err_warn;
31bd204f 3880
b6ffd97f
FR		 3881 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3882 if (rc < 0)
3883 goto err_free;
3884
fd112f2e
FR		 3885 rc = rtl_check_firmware(tp, rtl_fw);
3886 if (rc < 0)
3887 goto err_release_firmware;
3888
b6ffd97f
FR		 3889 tp->rtl_fw = rtl_fw;
3890out:
3891 return;
3892
fd112f2e
FR		 3893err_release_firmware:
3894 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3895err_free:
3896 kfree(rtl_fw);
3897err_warn:
3898 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3899 name, rc);
3900out_no_firmware:
3901 tp->rtl_fw = NULL;
3902 goto out;
3903}
3904
3905static void rtl_request_firmware(struct rtl8169_private *tp)
3906{
3907 if (IS_ERR(tp->rtl_fw))
3908 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3909}
3910
1da177e4
LT		 3911static int rtl8169_open(struct net_device *dev)
3912{
3913 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3914 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3915 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3916 int retval = -ENOMEM;
1da177e4 3917
e1759441 3918 pm_runtime_get_sync(&pdev->dev);
1da177e4 3919
1da177e4
LT		 3920 /*
3921 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3922 * dma_alloc_coherent provides more.
1da177e4 3923 */
82553bb6
SG		 3924 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3925 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3926 if (!tp->TxDescArray)
e1759441 3927 goto err_pm_runtime_put;
1da177e4 3928
82553bb6
SG		 3929 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3930 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3931 if (!tp->RxDescArray)
99f252b0 3932 goto err_free_tx_0;
1da177e4
LT		 3933
3934 retval = rtl8169_init_ring(dev);
3935 if (retval < 0)
99f252b0 3936 goto err_free_rx_1;
1da177e4 3937
c4028958 3938 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3939
99f252b0
FR		 3940 smp_mb();
3941
953a12cc
FR		 3942 rtl_request_firmware(tp);
3943
fbac58fc
FR		 3944 retval = request_irq(dev->irq, rtl8169_interrupt,
3945 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3946 dev->name, dev);
3947 if (retval < 0)
953a12cc 3948 goto err_release_fw_2;
99f252b0 3949
bea3348e 3950 napi_enable(&tp->napi);
bea3348e 3951
eee3a96c 3952 rtl8169_init_phy(dev, tp);
3953
350fb32a 3954 rtl8169_set_features(dev, dev->features);
eee3a96c 3955
065c27c1 3956 rtl_pll_power_up(tp);
3957
07ce4064 3958 rtl_hw_start(dev);
1da177e4 3959
e1759441
RW		 3960 tp->saved_wolopts = 0;
3961 pm_runtime_put_noidle(&pdev->dev);
3962
eee3a96c 3963 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3964out:
3965 return retval;
3966
953a12cc
FR		 3967err_release_fw_2:
3968 rtl_release_firmware(tp);
99f252b0
FR		 3969 rtl8169_rx_clear(tp);
3970err_free_rx_1:
82553bb6
SG		 3971 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3972 tp->RxPhyAddr);
e1759441 3973 tp->RxDescArray = NULL;
99f252b0 3974err_free_tx_0:
82553bb6
SG		 3975 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3976 tp->TxPhyAddr);
e1759441
RW		 3977 tp->TxDescArray = NULL;
3978err_pm_runtime_put:
3979 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3980 goto out;
3981}
3982
92fc43b4
HW		 3983static void rtl_rx_close(struct rtl8169_private *tp)
3984{
3985 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 3986
1687b566 3987 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 3988}
3989
e6de30d6 3990static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3991{
e6de30d6 3992 void __iomem *ioaddr = tp->mmio_addr;
3993
1da177e4
LT		 3994 /* Disable interrupts */
3995 rtl8169_irq_mask_and_ack(ioaddr);
3996
92fc43b4
HW		 3997 rtl_rx_close(tp);
3998
5d2e1957 3999 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 4000 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4001 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 4002 while (RTL_R8(TxPoll) & NPQ)
4003 udelay(20);
70090424 4004 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
c2b0c1e7 4005 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4006 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4007 udelay(100);
92fc43b4
HW		 4008 } else {
4009 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4010 udelay(100);
e6de30d6 4011 }
4012
92fc43b4 4013 rtl_hw_reset(tp);
1da177e4
LT		 4014}
4015
7f796d83 4016static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4017{
4018 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4019
4020 /* Set DMA burst size and Interframe Gap Time */
4021 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4022 (InterFrameGap << TxInterFrameGapShift));
4023}
4024
07ce4064 4025static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4026{
4027 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4028
07ce4064
FR		 4029 tp->hw_start(dev);
4030
07ce4064
FR		 4031 netif_start_queue(dev);
4032}
4033
7f796d83
FR		 4034static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4035 void __iomem *ioaddr)
4036{
4037 /*
4038 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4039 * register to be written before TxDescAddrLow to work.
4040 * Switching from MMIO to I/O access fixes the issue as well.
4041 */
4042 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4043 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4044 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4045 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4046}
4047
4048static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4049{
4050 u16 cmd;
4051
4052 cmd = RTL_R16(CPlusCmd);
4053 RTL_W16(CPlusCmd, cmd);
4054 return cmd;
4055}
4056
fdd7b4c3 4057static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4058{
4059 /* Low hurts. Let's disable the filtering. */
207d6e87 4060 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4061}
4062
6dccd16b
FR		 4063static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4064{
3744100e 4065 static const struct rtl_cfg2_info {
6dccd16b
FR		 4066 u32 mac_version;
4067 u32 clk;
4068 u32 val;
4069 } cfg2_info [] = {
4070 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4071 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4072 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4073 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4074 };
4075 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4076 unsigned int i;
4077 u32 clk;
4078
4079 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4080 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4081 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4082 RTL_W32(0x7c, p->val);
4083 break;
4084 }
4085 }
4086}
4087
07ce4064
FR		 4088static void rtl_hw_start_8169(struct net_device *dev)
4089{
4090 struct rtl8169_private *tp = netdev_priv(dev);
4091 void __iomem *ioaddr = tp->mmio_addr;
4092 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4093
9cb427b6
FR		 4094 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4095 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4096 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4097 }
4098
1da177e4 4099 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4100 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4101 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4102 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4103 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4104 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4105
e542a226
HW		 4106 rtl_init_rxcfg(tp);
4107
f0298f81 4108 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4109
6f0333b8 4110 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4111
cecb5fd7
FR		 4112 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4113 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4114 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4115 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4116 rtl_set_rx_tx_config_registers(tp);
1da177e4 4117
7f796d83 4118 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4119
cecb5fd7
FR		 4120 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4121 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4122 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4123 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4124 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4125 }
4126
bcf0bf90
FR		 4127 RTL_W16(CPlusCmd, tp->cp_cmd);
4128
6dccd16b
FR		 4129 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4130
1da177e4
LT		 4131 /*
4132 * Undocumented corner. Supposedly:
4133 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4134 */
4135 RTL_W16(IntrMitigate, 0x0000);
4136
7f796d83 4137 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4138
cecb5fd7
FR		 4139 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4140 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4141 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4142 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4143 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4144 rtl_set_rx_tx_config_registers(tp);
4145 }
4146
1da177e4 4147 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4148
4149 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4150 RTL_R8(IntrMask);
1da177e4
LT		 4151
4152 RTL_W32(RxMissed, 0);
4153
07ce4064 4154 rtl_set_rx_mode(dev);
1da177e4
LT		 4155
4156 /* no early-rx interrupts */
4157 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 4158
4159 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 4160 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4161}
1da177e4 4162
9c14ceaf 4163static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 4164{
e44daade 4165 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4166
4167 if (cap) {
4168 u16 ctl;
458a9f61 4169
9c14ceaf
FR		 4170 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4171 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4172 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4173 }
458a9f61
FR		 4174}
4175
650e8d5d 4176static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4177{
4178 u32 csi;
4179
4180 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4181 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4182}
4183
e6de30d6 4184static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4185{
4186 rtl_csi_access_enable(ioaddr, 0x17000000);
4187}
4188
650e8d5d 4189static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4190{
4191 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4192}
4193
4194struct ephy_info {
4195 unsigned int offset;
4196 u16 mask;
4197 u16 bits;
4198};
4199
350f7596 4200static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4201{
4202 u16 w;
4203
4204 while (len-- > 0) {
4205 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4206 rtl_ephy_write(ioaddr, e->offset, w);
4207 e++;
4208 }
4209}
4210
b726e493
FR		 4211static void rtl_disable_clock_request(struct pci_dev *pdev)
4212{
e44daade 4213 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4214
4215 if (cap) {
4216 u16 ctl;
4217
4218 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4219 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4220 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4221 }
4222}
4223
e6de30d6 4224static void rtl_enable_clock_request(struct pci_dev *pdev)
4225{
e44daade 4226 int cap = pci_pcie_cap(pdev);
e6de30d6 4227
4228 if (cap) {
4229 u16 ctl;
4230
4231 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4232 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4233 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4234 }
4235}
4236
b726e493
FR		 4237#define R8168_CPCMD_QUIRK_MASK (\
4238 EnableBist | \
4239 Mac_dbgo_oe | \
4240 Force_half_dup | \
4241 Force_rxflow_en | \
4242 Force_txflow_en | \
4243 Cxpl_dbg_sel | \
4244 ASF | \
4245 PktCntrDisable | \
4246 Mac_dbgo_sel)
4247
219a1e9d
FR		 4248static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4249{
b726e493
FR		 4250 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4251
4252 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4253
2e68ae44
FR		 4254 rtl_tx_performance_tweak(pdev,
4255 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4256}
4257
4258static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4259{
4260 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4261
f0298f81 4262 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4263
4264 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4265}
4266
4267static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4268{
b726e493
FR		 4269 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4270
4271 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4272
219a1e9d 4273 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4274
4275 rtl_disable_clock_request(pdev);
4276
4277 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4278}
4279
ef3386f0 4280static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4281{
350f7596 4282 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4283 { 0x01, 0, 0x0001 },
4284 { 0x02, 0x0800, 0x1000 },
4285 { 0x03, 0, 0x0042 },
4286 { 0x06, 0x0080, 0x0000 },
4287 { 0x07, 0, 0x2000 }
4288 };
4289
650e8d5d 4290 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4291
4292 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4293
219a1e9d
FR		 4294 __rtl_hw_start_8168cp(ioaddr, pdev);
4295}
4296
ef3386f0
FR		 4297static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4298{
650e8d5d 4299 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4300
4301 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4302
4303 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4304
4305 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4306}
4307
7f3e3d3a
FR		 4308static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4309{
650e8d5d 4310 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4311
4312 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4313
4314 /* Magic. */
4315 RTL_W8(DBG_REG, 0x20);
4316
f0298f81 4317 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4318
4319 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4320
4321 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4322}
4323
219a1e9d
FR		 4324static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4325{
350f7596 4326 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4327 { 0x02, 0x0800, 0x1000 },
4328 { 0x03, 0, 0x0002 },
4329 { 0x06, 0x0080, 0x0000 }
4330 };
4331
650e8d5d 4332 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4333
4334 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4335
4336 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4337
219a1e9d
FR		 4338 __rtl_hw_start_8168cp(ioaddr, pdev);
4339}
4340
4341static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4342{
350f7596 4343 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4344 { 0x01, 0, 0x0001 },
4345 { 0x03, 0x0400, 0x0220 }
4346 };
4347
650e8d5d 4348 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4349
4350 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4351
219a1e9d
FR		 4352 __rtl_hw_start_8168cp(ioaddr, pdev);
4353}
4354
197ff761
FR		 4355static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4356{
4357 rtl_hw_start_8168c_2(ioaddr, pdev);
4358}
4359
6fb07058
FR		 4360static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4361{
650e8d5d 4362 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4363
4364 __rtl_hw_start_8168cp(ioaddr, pdev);
4365}
4366
5b538df9
FR		 4367static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4368{
650e8d5d 4369 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4370
4371 rtl_disable_clock_request(pdev);
4372
f0298f81 4373 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4374
4375 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4376
4377 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4378}
4379
4804b3b3 4380static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4381{
4382 rtl_csi_access_enable_1(ioaddr);
4383
4384 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4385
4386 RTL_W8(MaxTxPacketSize, TxPacketMax);
4387
4388 rtl_disable_clock_request(pdev);
4389}
4390
e6de30d6 4391static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4392{
4393 static const struct ephy_info e_info_8168d_4[] = {
4394 { 0x0b, ~0, 0x48 },
4395 { 0x19, 0x20, 0x50 },
4396 { 0x0c, ~0, 0x20 }
4397 };
4398 int i;
4399
4400 rtl_csi_access_enable_1(ioaddr);
4401
4402 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4403
4404 RTL_W8(MaxTxPacketSize, TxPacketMax);
4405
4406 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4407 const struct ephy_info *e = e_info_8168d_4 + i;
4408 u16 w;
4409
4410 w = rtl_ephy_read(ioaddr, e->offset);
4411 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4412 }
4413
4414 rtl_enable_clock_request(pdev);
4415}
4416
70090424 4417static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4418{
70090424 4419 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4420 { 0x00, 0x0200, 0x0100 },
4421 { 0x00, 0x0000, 0x0004 },
4422 { 0x06, 0x0002, 0x0001 },
4423 { 0x06, 0x0000, 0x0030 },
4424 { 0x07, 0x0000, 0x2000 },
4425 { 0x00, 0x0000, 0x0020 },
4426 { 0x03, 0x5800, 0x2000 },
4427 { 0x03, 0x0000, 0x0001 },
4428 { 0x01, 0x0800, 0x1000 },
4429 { 0x07, 0x0000, 0x4000 },
4430 { 0x1e, 0x0000, 0x2000 },
4431 { 0x19, 0xffff, 0xfe6c },
4432 { 0x0a, 0x0000, 0x0040 }
4433 };
4434
4435 rtl_csi_access_enable_2(ioaddr);
4436
70090424 4437 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4438
4439 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4440
4441 RTL_W8(MaxTxPacketSize, TxPacketMax);
4442
4443 rtl_disable_clock_request(pdev);
4444
4445 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4446 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4447 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4448
cecb5fd7 4449 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4450}
4451
70090424
HW		 4452static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4453{
4454 static const struct ephy_info e_info_8168e_2[] = {
4455 { 0x09, 0x0000, 0x0080 },
4456 { 0x19, 0x0000, 0x0224 }
4457 };
4458
4459 rtl_csi_access_enable_1(ioaddr);
4460
4461 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4462
4463 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4464
4465 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4466 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4467 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4468 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4469 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4470 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4471 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4472 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4473 ERIAR_EXGMAC);
4474
4475 RTL_W8(MaxTxPacketSize, 0x27);
4476
4477 rtl_disable_clock_request(pdev);
4478
4479 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4480 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4481
4482 /* Adjust EEE LED frequency */
4483 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4484
4485 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4486 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4487 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4488}
4489
07ce4064
FR		 4490static void rtl_hw_start_8168(struct net_device *dev)
4491{
2dd99530
FR		 4492 struct rtl8169_private *tp = netdev_priv(dev);
4493 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4494 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4495
4496 RTL_W8(Cfg9346, Cfg9346_Unlock);
4497
f0298f81 4498 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4499
6f0333b8 4500 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4501
0e485150 4502 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4503
4504 RTL_W16(CPlusCmd, tp->cp_cmd);
4505
0e485150 4506 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4507
0e485150 4508 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4509 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4510 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4511 tp->intr_event |= RxFIFOOver | PCSTimeout;
4512 tp->intr_event &= ~RxOverflow;
4513 }
4514
4515 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4516
b8363901
FR		 4517 rtl_set_rx_mode(dev);
4518
4519 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4520 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4521
4522 RTL_R8(IntrMask);
4523
219a1e9d
FR		 4524 switch (tp->mac_version) {
4525 case RTL_GIGA_MAC_VER_11:
4526 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4527 break;
219a1e9d
FR		 4528
4529 case RTL_GIGA_MAC_VER_12:
4530 case RTL_GIGA_MAC_VER_17:
4531 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4532 break;
219a1e9d
FR		 4533
4534 case RTL_GIGA_MAC_VER_18:
ef3386f0 4535 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4536 break;
219a1e9d
FR		 4537
4538 case RTL_GIGA_MAC_VER_19:
4539 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4540 break;
219a1e9d
FR		 4541
4542 case RTL_GIGA_MAC_VER_20:
4543 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4544 break;
219a1e9d 4545
197ff761
FR		 4546 case RTL_GIGA_MAC_VER_21:
4547 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4548 break;
197ff761 4549
6fb07058
FR		 4550 case RTL_GIGA_MAC_VER_22:
4551 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4552 break;
6fb07058 4553
ef3386f0
FR		 4554 case RTL_GIGA_MAC_VER_23:
4555 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4556 break;
ef3386f0 4557
7f3e3d3a
FR		 4558 case RTL_GIGA_MAC_VER_24:
4559 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4560 break;
7f3e3d3a 4561
5b538df9 4562 case RTL_GIGA_MAC_VER_25:
daf9df6d 4563 case RTL_GIGA_MAC_VER_26:
4564 case RTL_GIGA_MAC_VER_27:
5b538df9 4565 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4566 break;
5b538df9 4567
e6de30d6 4568 case RTL_GIGA_MAC_VER_28:
4569 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4570 break;
cecb5fd7 4571
4804b3b3 4572 case RTL_GIGA_MAC_VER_31:
4573 rtl_hw_start_8168dp(ioaddr, pdev);
4574 break;
4575
01dc7fec 4576 case RTL_GIGA_MAC_VER_32:
4577 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4578 rtl_hw_start_8168e_1(ioaddr, pdev);
4579 break;
4580 case RTL_GIGA_MAC_VER_34:
4581 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4582 break;
e6de30d6 4583
219a1e9d
FR		 4584 default:
4585 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4586 dev->name, tp->mac_version);
4804b3b3 4587 break;
219a1e9d 4588 }
2dd99530 4589
0e485150
FR		 4590 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4591
b8363901
FR		 4592 RTL_W8(Cfg9346, Cfg9346_Lock);
4593
2dd99530 4594 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4595
0e485150 4596 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4597}
1da177e4 4598
2857ffb7
FR		 4599#define R810X_CPCMD_QUIRK_MASK (\
4600 EnableBist | \
4601 Mac_dbgo_oe | \
4602 Force_half_dup | \
5edcc537 4603 Force_rxflow_en | \
2857ffb7
FR		 4604 Force_txflow_en | \
4605 Cxpl_dbg_sel | \
4606 ASF | \
4607 PktCntrDisable | \
d24e9aaf 4608 Mac_dbgo_sel)
2857ffb7
FR		 4609
4610static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4611{
350f7596 4612 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4613 { 0x01, 0, 0x6e65 },
4614 { 0x02, 0, 0x091f },
4615 { 0x03, 0, 0xc2f9 },
4616 { 0x06, 0, 0xafb5 },
4617 { 0x07, 0, 0x0e00 },
4618 { 0x19, 0, 0xec80 },
4619 { 0x01, 0, 0x2e65 },
4620 { 0x01, 0, 0x6e65 }
4621 };
4622 u8 cfg1;
4623
650e8d5d 4624 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4625
4626 RTL_W8(DBG_REG, FIX_NAK_1);
4627
4628 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4629
4630 RTL_W8(Config1,
4631 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4632 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4633
4634 cfg1 = RTL_R8(Config1);
4635 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4636 RTL_W8(Config1, cfg1 & ~LEDS0);
4637
2857ffb7
FR		 4638 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4639}
4640
4641static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4642{
650e8d5d 4643 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4644
4645 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4646
4647 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4648 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4649}
4650
4651static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4652{
4653 rtl_hw_start_8102e_2(ioaddr, pdev);
4654
4655 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4656}
4657
5a5e4443
HW		 4658static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4659{
4660 static const struct ephy_info e_info_8105e_1[] = {
4661 { 0x07, 0, 0x4000 },
4662 { 0x19, 0, 0x0200 },
4663 { 0x19, 0, 0x0020 },
4664 { 0x1e, 0, 0x2000 },
4665 { 0x03, 0, 0x0001 },
4666 { 0x19, 0, 0x0100 },
4667 { 0x19, 0, 0x0004 },
4668 { 0x0a, 0, 0x0020 }
4669 };
4670
cecb5fd7 4671 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4672 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4673
cecb5fd7 4674 /* Disable Early Tally Counter */
5a5e4443
HW		 4675 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4676
4677 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4678 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4679
4680 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4681}
4682
4683static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4684{
4685 rtl_hw_start_8105e_1(ioaddr, pdev);
4686 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4687}
4688
07ce4064
FR		 4689static void rtl_hw_start_8101(struct net_device *dev)
4690{
cdf1a608
FR		 4691 struct rtl8169_private *tp = netdev_priv(dev);
4692 void __iomem *ioaddr = tp->mmio_addr;
4693 struct pci_dev *pdev = tp->pci_dev;
4694
cecb5fd7
FR		 4695 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4696 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4697 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4698
4699 if (cap) {
4700 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4701 PCI_EXP_DEVCTL_NOSNOOP_EN);
4702 }
cdf1a608
FR		 4703 }
4704
d24e9aaf
HW		 4705 RTL_W8(Cfg9346, Cfg9346_Unlock);
4706
2857ffb7
FR		 4707 switch (tp->mac_version) {
4708 case RTL_GIGA_MAC_VER_07:
4709 rtl_hw_start_8102e_1(ioaddr, pdev);
4710 break;
4711
4712 case RTL_GIGA_MAC_VER_08:
4713 rtl_hw_start_8102e_3(ioaddr, pdev);
4714 break;
4715
4716 case RTL_GIGA_MAC_VER_09:
4717 rtl_hw_start_8102e_2(ioaddr, pdev);
4718 break;
5a5e4443
HW		 4719
4720 case RTL_GIGA_MAC_VER_29:
4721 rtl_hw_start_8105e_1(ioaddr, pdev);
4722 break;
4723 case RTL_GIGA_MAC_VER_30:
4724 rtl_hw_start_8105e_2(ioaddr, pdev);
4725 break;
cdf1a608
FR		 4726 }
4727
d24e9aaf 4728 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4729
f0298f81 4730 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4731
6f0333b8 4732 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4733
d24e9aaf 4734 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4735 RTL_W16(CPlusCmd, tp->cp_cmd);
4736
4737 RTL_W16(IntrMitigate, 0x0000);
4738
4739 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4740
4741 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4742 rtl_set_rx_tx_config_registers(tp);
4743
cdf1a608
FR		 4744 RTL_R8(IntrMask);
4745
cdf1a608
FR		 4746 rtl_set_rx_mode(dev);
4747
4748 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4749
0e485150 4750 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4751}
4752
4753static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4754{
1da177e4
LT		 4755 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4756 return -EINVAL;
4757
4758 dev->mtu = new_mtu;
350fb32a
MM		 4759 netdev_update_features(dev);
4760
323bb685 4761 return 0;
1da177e4
LT		 4762}
4763
4764static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4765{
95e0918d 4766 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4767 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4768}
4769
6f0333b8
ED		 4770static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4771 void **data_buff, struct RxDesc *desc)
1da177e4 4772{
48addcc9 4773 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4774 DMA_FROM_DEVICE);
48addcc9 4775
6f0333b8
ED		 4776 kfree(*data_buff);
4777 *data_buff = NULL;
1da177e4
LT		 4778 rtl8169_make_unusable_by_asic(desc);
4779}
4780
4781static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4782{
4783 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4784
4785 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4786}
4787
4788static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4789 u32 rx_buf_sz)
4790{
4791 desc->addr = cpu_to_le64(mapping);
4792 wmb();
4793 rtl8169_mark_to_asic(desc, rx_buf_sz);
4794}
4795
6f0333b8
ED		 4796static inline void *rtl8169_align(void *data)
4797{
4798 return (void *)ALIGN((long)data, 16);
4799}
4800
0ecbe1ca
SG		 4801static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4802 struct RxDesc *desc)
1da177e4 4803{
6f0333b8 4804 void *data;
1da177e4 4805 dma_addr_t mapping;
48addcc9 4806 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4807 struct net_device *dev = tp->dev;
6f0333b8 4808 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4809
6f0333b8
ED		 4810 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4811 if (!data)
4812 return NULL;
e9f63f30 4813
6f0333b8
ED		 4814 if (rtl8169_align(data) != data) {
4815 kfree(data);
4816 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4817 if (!data)
4818 return NULL;
4819 }
3eafe507 4820
48addcc9 4821 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4822 DMA_FROM_DEVICE);
d827d86b
SG		 4823 if (unlikely(dma_mapping_error(d, mapping))) {
4824 if (net_ratelimit())
4825 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4826 goto err_out;
d827d86b 4827 }
1da177e4
LT		 4828
4829 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4830 return data;
3eafe507
SG		 4831
4832err_out:
4833 kfree(data);
4834 return NULL;
1da177e4
LT		 4835}
4836
4837static void rtl8169_rx_clear(struct rtl8169_private *tp)
4838{
07d3f51f 4839 unsigned int i;
1da177e4
LT		 4840
4841 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4842 if (tp->Rx_databuff[i]) {
4843 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4844 tp->RxDescArray + i);
4845 }
4846 }
4847}
4848
0ecbe1ca 4849static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4850{
0ecbe1ca
SG		 4851 desc->opts1 |= cpu_to_le32(RingEnd);
4852}
5b0384f4 4853
0ecbe1ca
SG		 4854static int rtl8169_rx_fill(struct rtl8169_private *tp)
4855{
4856 unsigned int i;
1da177e4 4857
0ecbe1ca
SG		 4858 for (i = 0; i < NUM_RX_DESC; i++) {
4859 void *data;
4ae47c2d 4860
6f0333b8 4861 if (tp->Rx_databuff[i])
1da177e4 4862 continue;
bcf0bf90 4863
0ecbe1ca 4864 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4865 if (!data) {
4866 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4867 goto err_out;
6f0333b8
ED		 4868 }
4869 tp->Rx_databuff[i] = data;
1da177e4 4870 }
1da177e4 4871
0ecbe1ca
SG		 4872 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4873 return 0;
4874
4875err_out:
4876 rtl8169_rx_clear(tp);
4877 return -ENOMEM;
1da177e4
LT		 4878}
4879
1da177e4
LT		 4880static int rtl8169_init_ring(struct net_device *dev)
4881{
4882 struct rtl8169_private *tp = netdev_priv(dev);
4883
4884 rtl8169_init_ring_indexes(tp);
4885
4886 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4887 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4888
0ecbe1ca 4889 return rtl8169_rx_fill(tp);
1da177e4
LT		 4890}
4891
48addcc9 4892static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4893 struct TxDesc *desc)
4894{
4895 unsigned int len = tx_skb->len;
4896
48addcc9
SG		 4897 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4898
1da177e4
LT		 4899 desc->opts1 = 0x00;
4900 desc->opts2 = 0x00;
4901 desc->addr = 0x00;
4902 tx_skb->len = 0;
4903}
4904
3eafe507
SG		 4905static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4906 unsigned int n)
1da177e4
LT		 4907{
4908 unsigned int i;
4909
3eafe507
SG		 4910 for (i = 0; i < n; i++) {
4911 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4912 struct ring_info *tx_skb = tp->tx_skb + entry;
4913 unsigned int len = tx_skb->len;
4914
4915 if (len) {
4916 struct sk_buff *skb = tx_skb->skb;
4917
48addcc9 4918 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4919 tp->TxDescArray + entry);
4920 if (skb) {
cac4b22f 4921 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4922 dev_kfree_skb(skb);
4923 tx_skb->skb = NULL;
4924 }
1da177e4
LT		 4925 }
4926 }
3eafe507
SG		 4927}
4928
4929static void rtl8169_tx_clear(struct rtl8169_private *tp)
4930{
4931 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4932 tp->cur_tx = tp->dirty_tx = 0;
4933}
4934
c4028958 4935static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4936{
4937 struct rtl8169_private *tp = netdev_priv(dev);
4938
c4028958 4939 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4940 schedule_delayed_work(&tp->task, 4);
4941}
4942
4943static void rtl8169_wait_for_quiescence(struct net_device *dev)
4944{
4945 struct rtl8169_private *tp = netdev_priv(dev);
4946 void __iomem *ioaddr = tp->mmio_addr;
4947
4948 synchronize_irq(dev->irq);
4949
4950 /* Wait for any pending NAPI task to complete */
bea3348e 4951 napi_disable(&tp->napi);
1da177e4
LT		 4952
4953 rtl8169_irq_mask_and_ack(ioaddr);
4954
d1d08d12
DM		 4955 tp->intr_mask = 0xffff;
4956 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4957 napi_enable(&tp->napi);
1da177e4
LT		 4958}
4959
c4028958 4960static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4961{
c4028958
DH		 4962 struct rtl8169_private *tp =
4963 container_of(work, struct rtl8169_private, task.work);
4964 struct net_device *dev = tp->dev;
1da177e4
LT		 4965 int ret;
4966
eb2a021c
FR		 4967 rtnl_lock();
4968
4969 if (!netif_running(dev))
4970 goto out_unlock;
4971
4972 rtl8169_wait_for_quiescence(dev);
4973 rtl8169_close(dev);
1da177e4
LT		 4974
4975 ret = rtl8169_open(dev);
4976 if (unlikely(ret < 0)) {
bf82c189
JP		 4977 if (net_ratelimit())
4978 netif_err(tp, drv, dev,
4979 "reinit failure (status = %d). Rescheduling\n",
4980 ret);
1da177e4
LT		 4981 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4982 }
eb2a021c
FR		 4983
4984out_unlock:
4985 rtnl_unlock();
1da177e4
LT		 4986}
4987
c4028958 4988static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4989{
c4028958
DH		 4990 struct rtl8169_private *tp =
4991 container_of(work, struct rtl8169_private, task.work);
4992 struct net_device *dev = tp->dev;
56de414c 4993 int i;
1da177e4 4994
eb2a021c
FR		 4995 rtnl_lock();
4996
1da177e4 4997 if (!netif_running(dev))
eb2a021c 4998 goto out_unlock;
1da177e4
LT		 4999
5000 rtl8169_wait_for_quiescence(dev);
5001
56de414c
FR		 5002 for (i = 0; i < NUM_RX_DESC; i++)
5003 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5004
1da177e4
LT		 5005 rtl8169_tx_clear(tp);
5006
92fc43b4 5007 rtl8169_hw_reset(tp);
56de414c
FR		 5008 rtl_hw_start(dev);
5009 netif_wake_queue(dev);
5010 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 5011
5012out_unlock:
5013 rtnl_unlock();
1da177e4
LT		 5014}
5015
5016static void rtl8169_tx_timeout(struct net_device *dev)
5017{
5018 struct rtl8169_private *tp = netdev_priv(dev);
5019
e6de30d6 5020 rtl8169_hw_reset(tp);
1da177e4
LT		 5021
5022 /* Let's wait a bit while any (async) irq lands on */
5023 rtl8169_schedule_work(dev, rtl8169_reset_task);
5024}
5025
5026static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5027 u32 *opts)
1da177e4
LT		 5028{
5029 struct skb_shared_info *info = skb_shinfo(skb);
5030 unsigned int cur_frag, entry;
a6343afb 5031 struct TxDesc * uninitialized_var(txd);
48addcc9 5032 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5033
5034 entry = tp->cur_tx;
5035 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5036 skb_frag_t *frag = info->frags + cur_frag;
5037 dma_addr_t mapping;
5038 u32 status, len;
5039 void *addr;
5040
5041 entry = (entry + 1) % NUM_TX_DESC;
5042
5043 txd = tp->TxDescArray + entry;
5044 len = frag->size;
5045 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 5046 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5047 if (unlikely(dma_mapping_error(d, mapping))) {
5048 if (net_ratelimit())
5049 netif_err(tp, drv, tp->dev,
5050 "Failed to map TX fragments DMA!\n");
3eafe507 5051 goto err_out;
d827d86b 5052 }
1da177e4 5053
cecb5fd7 5054 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5055 status = opts[0] | len |
5056 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5057
5058 txd->opts1 = cpu_to_le32(status);
2b7b4318 5059 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5060 txd->addr = cpu_to_le64(mapping);
5061
5062 tp->tx_skb[entry].len = len;
5063 }
5064
5065 if (cur_frag) {
5066 tp->tx_skb[entry].skb = skb;
5067 txd->opts1 |= cpu_to_le32(LastFrag);
5068 }
5069
5070 return cur_frag;
3eafe507
SG		 5071
5072err_out:
5073 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5074 return -EIO;
1da177e4
LT		 5075}
5076
2b7b4318
FR		 5077static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5078 struct sk_buff *skb, u32 *opts)
1da177e4 5079{
2b7b4318 5080 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5081 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5082 int offset = info->opts_offset;
350fb32a 5083
2b7b4318
FR		 5084 if (mss) {
5085 opts[0] |= TD_LSO;
5086 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5087 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5088 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5089
5090 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5091 opts[offset] |= info->checksum.tcp;
1da177e4 5092 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5093 opts[offset] |= info->checksum.udp;
5094 else
5095 WARN_ON_ONCE(1);
1da177e4 5096 }
1da177e4
LT		 5097}
5098
61357325
SH		 5099static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5100 struct net_device *dev)
1da177e4
LT		 5101{
5102 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5103 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5104 struct TxDesc *txd = tp->TxDescArray + entry;
5105 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5106 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5107 dma_addr_t mapping;
5108 u32 status, len;
2b7b4318 5109 u32 opts[2];
3eafe507 5110 int frags;
5b0384f4 5111
1da177e4 5112 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5113 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5114 goto err_stop_0;
1da177e4
LT		 5115 }
5116
5117 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5118 goto err_stop_0;
5119
5120 len = skb_headlen(skb);
48addcc9 5121 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5122 if (unlikely(dma_mapping_error(d, mapping))) {
5123 if (net_ratelimit())
5124 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5125 goto err_dma_0;
d827d86b 5126 }
3eafe507
SG		 5127
5128 tp->tx_skb[entry].len = len;
5129 txd->addr = cpu_to_le64(mapping);
1da177e4 5130
2b7b4318
FR		 5131 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5132 opts[0] = DescOwn;
1da177e4 5133
2b7b4318
FR		 5134 rtl8169_tso_csum(tp, skb, opts);
5135
5136 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5137 if (frags < 0)
5138 goto err_dma_1;
5139 else if (frags)
2b7b4318 5140 opts[0] |= FirstFrag;
3eafe507 5141 else {
2b7b4318 5142 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5143 tp->tx_skb[entry].skb = skb;
5144 }
5145
2b7b4318
FR		 5146 txd->opts2 = cpu_to_le32(opts[1]);
5147
1da177e4
LT		 5148 wmb();
5149
cecb5fd7 5150 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5151 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5152 txd->opts1 = cpu_to_le32(status);
5153
1da177e4
LT		 5154 tp->cur_tx += frags + 1;
5155
4c020a96 5156 wmb();
1da177e4 5157
cecb5fd7 5158 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5159
5160 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5161 netif_stop_queue(dev);
5162 smp_rmb();
5163 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5164 netif_wake_queue(dev);
5165 }
5166
61357325 5167 return NETDEV_TX_OK;
1da177e4 5168
3eafe507 5169err_dma_1:
48addcc9 5170 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5171err_dma_0:
5172 dev_kfree_skb(skb);
5173 dev->stats.tx_dropped++;
5174 return NETDEV_TX_OK;
5175
5176err_stop_0:
1da177e4 5177 netif_stop_queue(dev);
cebf8cc7 5178 dev->stats.tx_dropped++;
61357325 5179 return NETDEV_TX_BUSY;
1da177e4
LT		 5180}
5181
5182static void rtl8169_pcierr_interrupt(struct net_device *dev)
5183{
5184 struct rtl8169_private *tp = netdev_priv(dev);
5185 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5186 u16 pci_status, pci_cmd;
5187
5188 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5189 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5190
bf82c189
JP		 5191 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5192 pci_cmd, pci_status);
1da177e4
LT		 5193
5194 /*
5195 * The recovery sequence below admits a very elaborated explanation:
5196 * - it seems to work;
d03902b8
FR		 5197 * - I did not see what else could be done;
5198 * - it makes iop3xx happy.
1da177e4
LT		 5199 *
5200 * Feel free to adjust to your needs.
5201 */
a27993f3 5202 if (pdev->broken_parity_status)
d03902b8
FR		 5203 pci_cmd &= ~PCI_COMMAND_PARITY;
5204 else
5205 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5206
5207 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5208
5209 pci_write_config_word(pdev, PCI_STATUS,
5210 pci_status & (PCI_STATUS_DETECTED_PARITY |
5211 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5212 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5213
5214 /* The infamous DAC f*ckup only happens at boot time */
5215 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5216 void __iomem *ioaddr = tp->mmio_addr;
5217
bf82c189 5218 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5219 tp->cp_cmd &= ~PCIDAC;
5220 RTL_W16(CPlusCmd, tp->cp_cmd);
5221 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5222 }
5223
e6de30d6 5224 rtl8169_hw_reset(tp);
d03902b8
FR		 5225
5226 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 5227}
5228
07d3f51f
FR		 5229static void rtl8169_tx_interrupt(struct net_device *dev,
5230 struct rtl8169_private *tp,
5231 void __iomem *ioaddr)
1da177e4
LT		 5232{
5233 unsigned int dirty_tx, tx_left;
5234
1da177e4
LT		 5235 dirty_tx = tp->dirty_tx;
5236 smp_rmb();
5237 tx_left = tp->cur_tx - dirty_tx;
5238
5239 while (tx_left > 0) {
5240 unsigned int entry = dirty_tx % NUM_TX_DESC;
5241 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5242 u32 status;
5243
5244 rmb();
5245 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5246 if (status & DescOwn)
5247 break;
5248
48addcc9
SG		 5249 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5250 tp->TxDescArray + entry);
1da177e4 5251 if (status & LastFrag) {
cac4b22f
SG		 5252 dev->stats.tx_packets++;
5253 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5254 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5255 tx_skb->skb = NULL;
5256 }
5257 dirty_tx++;
5258 tx_left--;
5259 }
5260
5261 if (tp->dirty_tx != dirty_tx) {
5262 tp->dirty_tx = dirty_tx;
5263 smp_wmb();
5264 if (netif_queue_stopped(dev) &&
5265 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5266 netif_wake_queue(dev);
5267 }
d78ae2dc
FR		 5268 /*
5269 * 8168 hack: TxPoll requests are lost when the Tx packets are
5270 * too close. Let's kick an extra TxPoll request when a burst
5271 * of start_xmit activity is detected (if it is not detected,
5272 * it is slow enough). -- FR
5273 */
5274 smp_rmb();
5275 if (tp->cur_tx != dirty_tx)
5276 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5277 }
5278}
5279
126fa4b9
FR		 5280static inline int rtl8169_fragmented_frame(u32 status)
5281{
5282 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5283}
5284
adea1ac7 5285static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5286{
1da177e4
LT		 5287 u32 status = opts1 & RxProtoMask;
5288
5289 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5290 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5291 skb->ip_summed = CHECKSUM_UNNECESSARY;
5292 else
bc8acf2c 5293 skb_checksum_none_assert(skb);
1da177e4
LT		 5294}
5295
6f0333b8
ED		 5296static struct sk_buff *rtl8169_try_rx_copy(void *data,
5297 struct rtl8169_private *tp,
5298 int pkt_size,
5299 dma_addr_t addr)
1da177e4 5300{
b449655f 5301 struct sk_buff *skb;
48addcc9 5302 struct device *d = &tp->pci_dev->dev;
b449655f 5303
6f0333b8 5304 data = rtl8169_align(data);
48addcc9 5305 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5306 prefetch(data);
5307 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5308 if (skb)
5309 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5310 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5311
6f0333b8 5312 return skb;
1da177e4
LT		 5313}
5314
07d3f51f
FR		 5315static int rtl8169_rx_interrupt(struct net_device *dev,
5316 struct rtl8169_private *tp,
bea3348e 5317 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5318{
5319 unsigned int cur_rx, rx_left;
6f0333b8 5320 unsigned int count;
1da177e4 5321
1da177e4
LT		 5322 cur_rx = tp->cur_rx;
5323 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5324 rx_left = min(rx_left, budget);
1da177e4 5325
4dcb7d33 5326 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5327 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5328 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5329 u32 status;
5330
5331 rmb();
e03f33af 5332 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
1da177e4
LT		 5333
5334 if (status & DescOwn)
5335 break;
4dcb7d33 5336 if (unlikely(status & RxRES)) {
bf82c189
JP		 5337 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5338 status);
cebf8cc7 5339 dev->stats.rx_errors++;
1da177e4 5340 if (status & (RxRWT | RxRUNT))
cebf8cc7 5341 dev->stats.rx_length_errors++;
1da177e4 5342 if (status & RxCRC)
cebf8cc7 5343 dev->stats.rx_crc_errors++;
9dccf611
FR		 5344 if (status & RxFOVF) {
5345 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5346 dev->stats.rx_fifo_errors++;
9dccf611 5347 }
6f0333b8 5348 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5349 } else {
6f0333b8 5350 struct sk_buff *skb;
b449655f 5351 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 5352 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 5353
126fa4b9
FR		 5354 /*
5355 * The driver does not support incoming fragmented
5356 * frames. They are seen as a symptom of over-mtu
5357 * sized frames.
5358 */
5359 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5360 dev->stats.rx_dropped++;
5361 dev->stats.rx_length_errors++;
6f0333b8 5362 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5363 continue;
126fa4b9
FR		 5364 }
5365
6f0333b8
ED		 5366 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5367 tp, pkt_size, addr);
5368 rtl8169_mark_to_asic(desc, rx_buf_sz);
5369 if (!skb) {
5370 dev->stats.rx_dropped++;
5371 continue;
1da177e4
LT		 5372 }
5373
adea1ac7 5374 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5375 skb_put(skb, pkt_size);
5376 skb->protocol = eth_type_trans(skb, dev);
5377
7a8fc77b
FR		 5378 rtl8169_rx_vlan_tag(desc, skb);
5379
56de414c 5380 napi_gro_receive(&tp->napi, skb);
1da177e4 5381
cebf8cc7
FR		 5382 dev->stats.rx_bytes += pkt_size;
5383 dev->stats.rx_packets++;
1da177e4 5384 }
6dccd16b
FR		 5385
5386 /* Work around for AMD plateform. */
95e0918d 5387 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5388 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5389 desc->opts2 = 0;
5390 cur_rx++;
5391 }
1da177e4
LT		 5392 }
5393
5394 count = cur_rx - tp->cur_rx;
5395 tp->cur_rx = cur_rx;
5396
6f0333b8 5397 tp->dirty_rx += count;
1da177e4
LT		 5398
5399 return count;
5400}
5401
07d3f51f 5402static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5403{
07d3f51f 5404 struct net_device *dev = dev_instance;
1da177e4 5405 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5406 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5407 int handled = 0;
865c652d 5408 int status;
1da177e4 5409
f11a377b
DD		 5410 /* loop handling interrupts until we have no new ones or
5411 * we hit a invalid/hotplug case.
5412 */
865c652d 5413 status = RTL_R16(IntrStatus);
f11a377b
DD		 5414 while (status && status != 0xffff) {
5415 handled = 1;
1da177e4 5416
f11a377b
DD		 5417 /* Handle all of the error cases first. These will reset
5418 * the chip, so just exit the loop.
5419 */
5420 if (unlikely(!netif_running(dev))) {
92fc43b4 5421 rtl8169_hw_reset(tp);
f11a377b
DD		 5422 break;
5423 }
1da177e4 5424
1519e57f
FR		 5425 if (unlikely(status & RxFIFOOver)) {
5426 switch (tp->mac_version) {
5427 /* Work around for rx fifo overflow */
5428 case RTL_GIGA_MAC_VER_11:
5429 case RTL_GIGA_MAC_VER_22:
5430 case RTL_GIGA_MAC_VER_26:
5431 netif_stop_queue(dev);
5432 rtl8169_tx_timeout(dev);
5433 goto done;
f60ac8e7
FR		 5434 /* Testers needed. */
5435 case RTL_GIGA_MAC_VER_17:
5436 case RTL_GIGA_MAC_VER_19:
5437 case RTL_GIGA_MAC_VER_20:
5438 case RTL_GIGA_MAC_VER_21:
5439 case RTL_GIGA_MAC_VER_23:
5440 case RTL_GIGA_MAC_VER_24:
5441 case RTL_GIGA_MAC_VER_27:
5442 case RTL_GIGA_MAC_VER_28:
4804b3b3 5443 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5444 /* Experimental science. Pktgen proof. */
5445 case RTL_GIGA_MAC_VER_12:
5446 case RTL_GIGA_MAC_VER_25:
5447 if (status == RxFIFOOver)
5448 goto done;
5449 break;
5450 default:
5451 break;
5452 }
f11a377b 5453 }
1da177e4 5454
f11a377b
DD		 5455 if (unlikely(status & SYSErr)) {
5456 rtl8169_pcierr_interrupt(dev);
5457 break;
5458 }
1da177e4 5459
f11a377b 5460 if (status & LinkChg)
e4fbce74 5461 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5462
f11a377b
DD		 5463 /* We need to see the lastest version of tp->intr_mask to
5464 * avoid ignoring an MSI interrupt and having to wait for
5465 * another event which may never come.
5466 */
5467 smp_rmb();
5468 if (status & tp->intr_mask & tp->napi_event) {
5469 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5470 tp->intr_mask = ~tp->napi_event;
5471
5472 if (likely(napi_schedule_prep(&tp->napi)))
5473 __napi_schedule(&tp->napi);
bf82c189
JP		 5474 else
5475 netif_info(tp, intr, dev,
5476 "interrupt %04x in poll\n", status);
f11a377b 5477 }
1da177e4 5478
f11a377b
DD		 5479 /* We only get a new MSI interrupt when all active irq
5480 * sources on the chip have been acknowledged. So, ack
5481 * everything we've seen and check if new sources have become
5482 * active to avoid blocking all interrupts from the chip.
5483 */
5484 RTL_W16(IntrStatus,
5485 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5486 status = RTL_R16(IntrStatus);
865c652d 5487 }
1519e57f 5488done:
1da177e4
LT		 5489 return IRQ_RETVAL(handled);
5490}
5491
bea3348e 5492static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5493{
bea3348e
SH		 5494 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5495 struct net_device *dev = tp->dev;
1da177e4 5496 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5497 int work_done;
1da177e4 5498
bea3348e 5499 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5500 rtl8169_tx_interrupt(dev, tp, ioaddr);
5501
bea3348e 5502 if (work_done < budget) {
288379f0 5503 napi_complete(napi);
f11a377b
DD		 5504
5505 /* We need for force the visibility of tp->intr_mask
5506 * for other CPUs, as we can loose an MSI interrupt
5507 * and potentially wait for a retransmit timeout if we don't.
5508 * The posted write to IntrMask is safe, as it will
5509 * eventually make it to the chip and we won't loose anything
5510 * until it does.
1da177e4 5511 */
f11a377b 5512 tp->intr_mask = 0xffff;
4c020a96 5513 wmb();
0e485150 5514 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5515 }
5516
bea3348e 5517 return work_done;
1da177e4 5518}
1da177e4 5519
523a6094
FR		 5520static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5521{
5522 struct rtl8169_private *tp = netdev_priv(dev);
5523
5524 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5525 return;
5526
5527 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5528 RTL_W32(RxMissed, 0);
5529}
5530
1da177e4
LT		 5531static void rtl8169_down(struct net_device *dev)
5532{
5533 struct rtl8169_private *tp = netdev_priv(dev);
5534 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5535
4876cc1e 5536 del_timer_sync(&tp->timer);
1da177e4
LT		 5537
5538 netif_stop_queue(dev);
5539
93dd79e8 5540 napi_disable(&tp->napi);
93dd79e8 5541
1da177e4
LT		 5542 spin_lock_irq(&tp->lock);
5543
92fc43b4 5544 rtl8169_hw_reset(tp);
323bb685
SG		 5545 /*
5546 * At this point device interrupts can not be enabled in any function,
5547 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5548 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5549 */
523a6094 5550 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5551
5552 spin_unlock_irq(&tp->lock);
5553
5554 synchronize_irq(dev->irq);
5555
1da177e4 5556 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5557 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5558
1da177e4
LT		 5559 rtl8169_tx_clear(tp);
5560
5561 rtl8169_rx_clear(tp);
065c27c1 5562
5563 rtl_pll_power_down(tp);
1da177e4
LT		 5564}
5565
5566static int rtl8169_close(struct net_device *dev)
5567{
5568 struct rtl8169_private *tp = netdev_priv(dev);
5569 struct pci_dev *pdev = tp->pci_dev;
5570
e1759441
RW		 5571 pm_runtime_get_sync(&pdev->dev);
5572
cecb5fd7 5573 /* Update counters before going down */
355423d0
IV		 5574 rtl8169_update_counters(dev);
5575
1da177e4
LT		 5576 rtl8169_down(dev);
5577
5578 free_irq(dev->irq, dev);
5579
82553bb6
SG		 5580 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5581 tp->RxPhyAddr);
5582 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5583 tp->TxPhyAddr);
1da177e4
LT		 5584 tp->TxDescArray = NULL;
5585 tp->RxDescArray = NULL;
5586
e1759441
RW		 5587 pm_runtime_put_sync(&pdev->dev);
5588
1da177e4
LT		 5589 return 0;
5590}
5591
07ce4064 5592static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5593{
5594 struct rtl8169_private *tp = netdev_priv(dev);
5595 void __iomem *ioaddr = tp->mmio_addr;
5596 unsigned long flags;
5597 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5598 int rx_mode;
1da177e4
LT		 5599 u32 tmp = 0;
5600
5601 if (dev->flags & IFF_PROMISC) {
5602 /* Unconditionally log net taps. */
bf82c189 5603 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5604 rx_mode =
5605 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5606 AcceptAllPhys;
5607 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5608 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5609 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5610 /* Too many to filter perfectly -- accept all multicasts. */
5611 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5612 mc_filter[1] = mc_filter[0] = 0xffffffff;
5613 } else {
22bedad3 5614 struct netdev_hw_addr *ha;
07d3f51f 5615
1da177e4
LT		 5616 rx_mode = AcceptBroadcast | AcceptMyPhys;
5617 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5618 netdev_for_each_mc_addr(ha, dev) {
5619 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5620 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5621 rx_mode |= AcceptMulticast;
5622 }
5623 }
5624
5625 spin_lock_irqsave(&tp->lock, flags);
5626
1687b566 5627 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 5628
f887cce8 5629 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5630 u32 data = mc_filter[0];
5631
5632 mc_filter[0] = swab32(mc_filter[1]);
5633 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5634 }
5635
1da177e4 5636 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5637 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5638
57a9f236
FR		 5639 RTL_W32(RxConfig, tmp);
5640
1da177e4
LT		 5641 spin_unlock_irqrestore(&tp->lock, flags);
5642}
5643
5644/**
5645 * rtl8169_get_stats - Get rtl8169 read/write statistics
5646 * @dev: The Ethernet Device to get statistics for
5647 *
5648 * Get TX/RX statistics for rtl8169
5649 */
5650static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5651{
5652 struct rtl8169_private *tp = netdev_priv(dev);
5653 void __iomem *ioaddr = tp->mmio_addr;
5654 unsigned long flags;
5655
5656 if (netif_running(dev)) {
5657 spin_lock_irqsave(&tp->lock, flags);
523a6094 5658 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5659 spin_unlock_irqrestore(&tp->lock, flags);
5660 }
5b0384f4 5661
cebf8cc7 5662 return &dev->stats;
1da177e4
LT		 5663}
5664
861ab440 5665static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5666{
065c27c1 5667 struct rtl8169_private *tp = netdev_priv(dev);
5668
5d06a99f 5669 if (!netif_running(dev))
861ab440 5670 return;
5d06a99f 5671
065c27c1 5672 rtl_pll_power_down(tp);
5673
5d06a99f
FR		 5674 netif_device_detach(dev);
5675 netif_stop_queue(dev);
861ab440
RW		 5676}
5677
5678#ifdef CONFIG_PM
5679
5680static int rtl8169_suspend(struct device *device)
5681{
5682 struct pci_dev *pdev = to_pci_dev(device);
5683 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5684
861ab440 5685 rtl8169_net_suspend(dev);
1371fa6d 5686
5d06a99f
FR		 5687 return 0;
5688}
5689
e1759441
RW		 5690static void __rtl8169_resume(struct net_device *dev)
5691{
065c27c1 5692 struct rtl8169_private *tp = netdev_priv(dev);
5693
e1759441 5694 netif_device_attach(dev);
065c27c1 5695
5696 rtl_pll_power_up(tp);
5697
e1759441
RW		 5698 rtl8169_schedule_work(dev, rtl8169_reset_task);
5699}
5700
861ab440 5701static int rtl8169_resume(struct device *device)
5d06a99f 5702{
861ab440 5703 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5704 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5705 struct rtl8169_private *tp = netdev_priv(dev);
5706
5707 rtl8169_init_phy(dev, tp);
5d06a99f 5708
e1759441
RW		 5709 if (netif_running(dev))
5710 __rtl8169_resume(dev);
5d06a99f 5711
e1759441
RW		 5712 return 0;
5713}
5714
5715static int rtl8169_runtime_suspend(struct device *device)
5716{
5717 struct pci_dev *pdev = to_pci_dev(device);
5718 struct net_device *dev = pci_get_drvdata(pdev);
5719 struct rtl8169_private *tp = netdev_priv(dev);
5720
5721 if (!tp->TxDescArray)
5722 return 0;
5723
5724 spin_lock_irq(&tp->lock);
5725 tp->saved_wolopts = __rtl8169_get_wol(tp);
5726 __rtl8169_set_wol(tp, WAKE_ANY);
5727 spin_unlock_irq(&tp->lock);
5728
5729 rtl8169_net_suspend(dev);
5730
5731 return 0;
5732}
5733
5734static int rtl8169_runtime_resume(struct device *device)
5735{
5736 struct pci_dev *pdev = to_pci_dev(device);
5737 struct net_device *dev = pci_get_drvdata(pdev);
5738 struct rtl8169_private *tp = netdev_priv(dev);
5739
5740 if (!tp->TxDescArray)
5741 return 0;
5742
5743 spin_lock_irq(&tp->lock);
5744 __rtl8169_set_wol(tp, tp->saved_wolopts);
5745 tp->saved_wolopts = 0;
5746 spin_unlock_irq(&tp->lock);
5747
fccec10b
SG		 5748 rtl8169_init_phy(dev, tp);
5749
e1759441 5750 __rtl8169_resume(dev);
5d06a99f 5751
5d06a99f
FR		 5752 return 0;
5753}
5754
e1759441
RW		 5755static int rtl8169_runtime_idle(struct device *device)
5756{
5757 struct pci_dev *pdev = to_pci_dev(device);
5758 struct net_device *dev = pci_get_drvdata(pdev);
5759 struct rtl8169_private *tp = netdev_priv(dev);
5760
e4fbce74 5761 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5762}
5763
47145210 5764static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5765 .suspend = rtl8169_suspend,
5766 .resume = rtl8169_resume,
5767 .freeze = rtl8169_suspend,
5768 .thaw = rtl8169_resume,
5769 .poweroff = rtl8169_suspend,
5770 .restore = rtl8169_resume,
5771 .runtime_suspend = rtl8169_runtime_suspend,
5772 .runtime_resume = rtl8169_runtime_resume,
5773 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5774};
5775
5776#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5777
5778#else /* !CONFIG_PM */
5779
5780#define RTL8169_PM_OPS NULL
5781
5782#endif /* !CONFIG_PM */
5783
1765f95d
FR		 5784static void rtl_shutdown(struct pci_dev *pdev)
5785{
861ab440 5786 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5787 struct rtl8169_private *tp = netdev_priv(dev);
5788 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5789
5790 rtl8169_net_suspend(dev);
1765f95d 5791
cecb5fd7 5792 /* Restore original MAC address */
cc098dc7
IV		 5793 rtl_rar_set(tp, dev->perm_addr);
5794
4bb3f522 5795 spin_lock_irq(&tp->lock);
5796
92fc43b4 5797 rtl8169_hw_reset(tp);
4bb3f522 5798
5799 spin_unlock_irq(&tp->lock);
5800
861ab440 5801 if (system_state == SYSTEM_POWER_OFF) {
aaa89c08
HW		 5802 /* WoL fails with 8168b when the receiver is disabled. */
5803 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5804 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5805 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5806 (tp->features & RTL_FEATURE_WOL)) {
ca52efd5 5807 pci_clear_master(pdev);
5808
5809 RTL_W8(ChipCmd, CmdRxEnb);
5810 /* PCI commit */
5811 RTL_R8(ChipCmd);
5812 }
5813
861ab440
RW		 5814 pci_wake_from_d3(pdev, true);
5815 pci_set_power_state(pdev, PCI_D3hot);
5816 }
5817}
5d06a99f 5818
1da177e4
LT		 5819static struct pci_driver rtl8169_pci_driver = {
5820 .name = MODULENAME,
5821 .id_table = rtl8169_pci_tbl,
5822 .probe = rtl8169_init_one,
5823 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5824 .shutdown = rtl_shutdown,
861ab440 5825 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5826};
5827
07d3f51f 5828static int __init rtl8169_init_module(void)
1da177e4 5829{
29917620 5830 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5831}
5832
07d3f51f 5833static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5834{
5835 pci_unregister_driver(&rtl8169_pci_driver);
5836}
5837
5838module_init(rtl8169_init_module);
5839module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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