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Merge branch 'integration' into for-linus
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
1da177e4 30
99f252b0 31#include <asm/system.h>
1da177e4
LT		 32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 44
1da177e4
LT		 45#ifdef RTL8169_DEBUG
46#define assert(expr) \
5b0384f4
FR		 47 if (!(expr)) { \
48 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 49 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 50 }
06fa7358
JP		 51#define dprintk(fmt, args...) \
52 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 53#else
54#define assert(expr) do {} while (0)
55#define dprintk(fmt, args...) do {} while (0)
56#endif /* RTL8169_DEBUG */
57
b57b7e5a 58#define R8169_MSG_DEFAULT \
f0e837d9 59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 60
1da177e4
LT		 61#define TX_BUFFS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
63
1da177e4
LT		 64/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 66static const int multicast_filter_limit = 32;
1da177e4
LT		 67
68/* MAC address length */
69#define MAC_ADDR_LEN 6
70
9c14ceaf 71#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 72#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
73#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
135 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 136};
137
2b7b4318
FR		 138enum rtl_tx_desc_version {
139 RTL_TD_0 = 0,
140 RTL_TD_1 = 1,
141};
142
85bffe6c
FR		 143#define _R(NAME,TD,FW) \
144 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 145
3c6bee1d 146static const struct {
1da177e4 147 const char *name;
2b7b4318 148 enum rtl_tx_desc_version txd_version;
953a12cc 149 const char *fw_name;
85bffe6c
FR		 150} rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_01] =
153 _R("RTL8169", RTL_TD_0, NULL),
154 [RTL_GIGA_MAC_VER_02] =
155 _R("RTL8169s", RTL_TD_0, NULL),
156 [RTL_GIGA_MAC_VER_03] =
157 _R("RTL8110s", RTL_TD_0, NULL),
158 [RTL_GIGA_MAC_VER_04] =
159 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
160 [RTL_GIGA_MAC_VER_05] =
161 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
162 [RTL_GIGA_MAC_VER_06] =
163 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
164 /* PCI-E devices. */
165 [RTL_GIGA_MAC_VER_07] =
166 _R("RTL8102e", RTL_TD_1, NULL),
167 [RTL_GIGA_MAC_VER_08] =
168 _R("RTL8102e", RTL_TD_1, NULL),
169 [RTL_GIGA_MAC_VER_09] =
170 _R("RTL8102e", RTL_TD_1, NULL),
171 [RTL_GIGA_MAC_VER_10] =
172 _R("RTL8101e", RTL_TD_0, NULL),
173 [RTL_GIGA_MAC_VER_11] =
174 _R("RTL8168b/8111b", RTL_TD_0, NULL),
175 [RTL_GIGA_MAC_VER_12] =
176 _R("RTL8168b/8111b", RTL_TD_0, NULL),
177 [RTL_GIGA_MAC_VER_13] =
178 _R("RTL8101e", RTL_TD_0, NULL),
179 [RTL_GIGA_MAC_VER_14] =
180 _R("RTL8100e", RTL_TD_0, NULL),
181 [RTL_GIGA_MAC_VER_15] =
182 _R("RTL8100e", RTL_TD_0, NULL),
183 [RTL_GIGA_MAC_VER_16] =
184 _R("RTL8101e", RTL_TD_0, NULL),
185 [RTL_GIGA_MAC_VER_17] =
186 _R("RTL8168b/8111b", RTL_TD_0, NULL),
187 [RTL_GIGA_MAC_VER_18] =
188 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
189 [RTL_GIGA_MAC_VER_19] =
190 _R("RTL8168c/8111c", RTL_TD_1, NULL),
191 [RTL_GIGA_MAC_VER_20] =
192 _R("RTL8168c/8111c", RTL_TD_1, NULL),
193 [RTL_GIGA_MAC_VER_21] =
194 _R("RTL8168c/8111c", RTL_TD_1, NULL),
195 [RTL_GIGA_MAC_VER_22] =
196 _R("RTL8168c/8111c", RTL_TD_1, NULL),
197 [RTL_GIGA_MAC_VER_23] =
198 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
199 [RTL_GIGA_MAC_VER_24] =
200 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
201 [RTL_GIGA_MAC_VER_25] =
202 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
203 [RTL_GIGA_MAC_VER_26] =
204 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
205 [RTL_GIGA_MAC_VER_27] =
206 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
207 [RTL_GIGA_MAC_VER_28] =
208 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
209 [RTL_GIGA_MAC_VER_29] =
210 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
211 [RTL_GIGA_MAC_VER_30] =
212 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
213 [RTL_GIGA_MAC_VER_31] =
214 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
215 [RTL_GIGA_MAC_VER_32] =
216 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
217 [RTL_GIGA_MAC_VER_33] =
218 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
953a12cc 219};
85bffe6c 220#undef _R
953a12cc 221
bcf0bf90
FR		 222enum cfg_version {
223 RTL_CFG_0 = 0x00,
224 RTL_CFG_1,
225 RTL_CFG_2
226};
227
07ce4064
FR		 228static void rtl_hw_start_8169(struct net_device *);
229static void rtl_hw_start_8168(struct net_device *);
230static void rtl_hw_start_8101(struct net_device *);
231
a3aa1884 232static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 233 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
238 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 239 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 240 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
241 { PCI_VENDOR_ID_LINKSYS, 0x1032,
242 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 243 { 0x0001, 0x8168,
244 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 245 {0,},
246};
247
248MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
249
6f0333b8 250static int rx_buf_sz = 16383;
4300e8c7 251static int use_dac;
b57b7e5a
SH		 252static struct {
253 u32 msg_enable;
254} debug = { -1 };
1da177e4 255
07d3f51f
FR		 256enum rtl_registers {
257 MAC0 = 0, /* Ethernet hardware address. */
773d2021 258 MAC4 = 4,
07d3f51f
FR		 259 MAR0 = 8, /* Multicast filter. */
260 CounterAddrLow = 0x10,
261 CounterAddrHigh = 0x14,
262 TxDescStartAddrLow = 0x20,
263 TxDescStartAddrHigh = 0x24,
264 TxHDescStartAddrLow = 0x28,
265 TxHDescStartAddrHigh = 0x2c,
266 FLASH = 0x30,
267 ERSR = 0x36,
268 ChipCmd = 0x37,
269 TxPoll = 0x38,
270 IntrMask = 0x3c,
271 IntrStatus = 0x3e,
272 TxConfig = 0x40,
273 RxConfig = 0x44,
2b7b4318
FR		 274
275#define RTL_RX_CONFIG_MASK 0xff7e1880u
276
07d3f51f
FR		 277 RxMissed = 0x4c,
278 Cfg9346 = 0x50,
279 Config0 = 0x51,
280 Config1 = 0x52,
281 Config2 = 0x53,
282 Config3 = 0x54,
283 Config4 = 0x55,
284 Config5 = 0x56,
285 MultiIntr = 0x5c,
286 PHYAR = 0x60,
07d3f51f
FR		 287 PHYstatus = 0x6c,
288 RxMaxSize = 0xda,
289 CPlusCmd = 0xe0,
290 IntrMitigate = 0xe2,
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
f0298f81 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295#define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299#define TxPacketMax (8064 >> 7)
300
07d3f51f
FR		 301 FuncEvent = 0xf0,
302 FuncEventMask = 0xf4,
303 FuncPresetState = 0xf8,
304 FuncForceEvent = 0xfc,
1da177e4
LT		 305};
306
f162a5d1
FR		 307enum rtl8110_registers {
308 TBICSR = 0x64,
309 TBI_ANAR = 0x68,
310 TBI_LPAR = 0x6a,
311};
312
313enum rtl8168_8101_registers {
314 CSIDR = 0x64,
315 CSIAR = 0x68,
316#define CSIAR_FLAG 0x80000000
317#define CSIAR_WRITE_CMD 0x80000000
318#define CSIAR_BYTE_ENABLE 0x0f
319#define CSIAR_BYTE_ENABLE_SHIFT 12
320#define CSIAR_ADDR_MASK 0x0fff
065c27c1 321 PMCH = 0x6f,
f162a5d1
FR		 322 EPHYAR = 0x80,
323#define EPHYAR_FLAG 0x80000000
324#define EPHYAR_WRITE_CMD 0x80000000
325#define EPHYAR_REG_MASK 0x1f
326#define EPHYAR_REG_SHIFT 16
327#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 328 DLLPR = 0xd0,
329#define PM_SWITCH (1 << 6)
f162a5d1
FR		 330 DBG_REG = 0xd1,
331#define FIX_NAK_1 (1 << 4)
332#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 333 TWSI = 0xd2,
334 MCU = 0xd3,
335#define EN_NDP (1 << 3)
336#define EN_OOB_RESET (1 << 2)
daf9df6d 337 EFUSEAR = 0xdc,
338#define EFUSEAR_FLAG 0x80000000
339#define EFUSEAR_WRITE_CMD 0x80000000
340#define EFUSEAR_READ_CMD 0x00000000
341#define EFUSEAR_REG_MASK 0x03ff
342#define EFUSEAR_REG_SHIFT 8
343#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 344};
345
c0e45c1c 346enum rtl8168_registers {
b646d900 347 ERIDR = 0x70,
348 ERIAR = 0x74,
349#define ERIAR_FLAG 0x80000000
350#define ERIAR_WRITE_CMD 0x80000000
351#define ERIAR_READ_CMD 0x00000000
352#define ERIAR_ADDR_BYTE_ALIGN 4
353#define ERIAR_EXGMAC 0
354#define ERIAR_MSIX 1
355#define ERIAR_ASF 2
356#define ERIAR_TYPE_SHIFT 16
357#define ERIAR_BYTEEN 0x0f
358#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 359 EPHY_RXER_NUM = 0x7c,
360 OCPDR = 0xb0, /* OCP GPHY access */
361#define OCPDR_WRITE_CMD 0x80000000
362#define OCPDR_READ_CMD 0x00000000
363#define OCPDR_REG_MASK 0x7f
364#define OCPDR_GPHY_REG_SHIFT 16
365#define OCPDR_DATA_MASK 0xffff
366 OCPAR = 0xb4,
367#define OCPAR_FLAG 0x80000000
368#define OCPAR_GPHY_WRITE_CMD 0x8000f060
369#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 370 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
371 MISC = 0xf0, /* 8168e only. */
cecb5fd7 372#define TXPLA_RST (1 << 29)
c0e45c1c 373};
374
07d3f51f 375enum rtl_register_content {
1da177e4 376 /* InterruptStatusBits */
07d3f51f
FR		 377 SYSErr = 0x8000,
378 PCSTimeout = 0x4000,
379 SWInt = 0x0100,
380 TxDescUnavail = 0x0080,
381 RxFIFOOver = 0x0040,
382 LinkChg = 0x0020,
383 RxOverflow = 0x0010,
384 TxErr = 0x0008,
385 TxOK = 0x0004,
386 RxErr = 0x0002,
387 RxOK = 0x0001,
1da177e4
LT		 388
389 /* RxStatusDesc */
9dccf611
FR		 390 RxFOVF = (1 << 23),
391 RxRWT = (1 << 22),
392 RxRES = (1 << 21),
393 RxRUNT = (1 << 20),
394 RxCRC = (1 << 19),
1da177e4
LT		 395
396 /* ChipCmdBits */
07d3f51f
FR		 397 CmdReset = 0x10,
398 CmdRxEnb = 0x08,
399 CmdTxEnb = 0x04,
400 RxBufEmpty = 0x01,
1da177e4 401
275391a4
FR		 402 /* TXPoll register p.5 */
403 HPQ = 0x80, /* Poll cmd on the high prio queue */
404 NPQ = 0x40, /* Poll cmd on the low prio queue */
405 FSWInt = 0x01, /* Forced software interrupt */
406
1da177e4 407 /* Cfg9346Bits */
07d3f51f
FR		 408 Cfg9346_Lock = 0x00,
409 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 410
411 /* rx_mode_bits */
07d3f51f
FR		 412 AcceptErr = 0x20,
413 AcceptRunt = 0x10,
414 AcceptBroadcast = 0x08,
415 AcceptMulticast = 0x04,
416 AcceptMyPhys = 0x02,
417 AcceptAllPhys = 0x01,
1da177e4
LT		 418
419 /* RxConfigBits */
07d3f51f
FR		 420 RxCfgFIFOShift = 13,
421 RxCfgDMAShift = 8,
1da177e4
LT		 422
423 /* TxConfigBits */
424 TxInterFrameGapShift = 24,
425 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
426
5d06a99f 427 /* Config1 register p.24 */
f162a5d1
FR		 428 LEDS1 = (1 << 7),
429 LEDS0 = (1 << 6),
fbac58fc 430 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 431 Speed_down = (1 << 4),
432 MEMMAP = (1 << 3),
433 IOMAP = (1 << 2),
434 VPD = (1 << 1),
5d06a99f
FR		 435 PMEnable = (1 << 0), /* Power Management Enable */
436
6dccd16b
FR		 437 /* Config2 register p. 25 */
438 PCI_Clock_66MHz = 0x01,
439 PCI_Clock_33MHz = 0x00,
440
61a4dcc2
FR		 441 /* Config3 register p.25 */
442 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
443 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 444 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 445
5d06a99f 446 /* Config5 register p.27 */
61a4dcc2
FR		 447 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
448 MWF = (1 << 5), /* Accept Multicast wakeup frame */
449 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 450 Spi_en = (1 << 3),
61a4dcc2 451 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 452 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
453
1da177e4
LT		 454 /* TBICSR p.28 */
455 TBIReset = 0x80000000,
456 TBILoopback = 0x40000000,
457 TBINwEnable = 0x20000000,
458 TBINwRestart = 0x10000000,
459 TBILinkOk = 0x02000000,
460 TBINwComplete = 0x01000000,
461
462 /* CPlusCmd p.31 */
f162a5d1
FR		 463 EnableBist = (1 << 15), // 8168 8101
464 Mac_dbgo_oe = (1 << 14), // 8168 8101
465 Normal_mode = (1 << 13), // unused
466 Force_half_dup = (1 << 12), // 8168 8101
467 Force_rxflow_en = (1 << 11), // 8168 8101
468 Force_txflow_en = (1 << 10), // 8168 8101
469 Cxpl_dbg_sel = (1 << 9), // 8168 8101
470 ASF = (1 << 8), // 8168 8101
471 PktCntrDisable = (1 << 7), // 8168 8101
472 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 473 RxVlan = (1 << 6),
474 RxChkSum = (1 << 5),
475 PCIDAC = (1 << 4),
476 PCIMulRW = (1 << 3),
0e485150
FR		 477 INTT_0 = 0x0000, // 8168
478 INTT_1 = 0x0001, // 8168
479 INTT_2 = 0x0002, // 8168
480 INTT_3 = 0x0003, // 8168
1da177e4
LT		 481
482 /* rtl8169_PHYstatus */
07d3f51f
FR		 483 TBI_Enable = 0x80,
484 TxFlowCtrl = 0x40,
485 RxFlowCtrl = 0x20,
486 _1000bpsF = 0x10,
487 _100bps = 0x08,
488 _10bps = 0x04,
489 LinkStatus = 0x02,
490 FullDup = 0x01,
1da177e4 491
1da177e4 492 /* _TBICSRBit */
07d3f51f 493 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 494
495 /* DumpCounterCommand */
07d3f51f 496 CounterDump = 0x8,
1da177e4
LT		 497};
498
2b7b4318
FR		 499enum rtl_desc_bit {
500 /* First doubleword. */
1da177e4
LT		 501 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
502 RingEnd = (1 << 30), /* End of descriptor ring */
503 FirstFrag = (1 << 29), /* First segment of a packet */
504 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 505};
506
507/* Generic case. */
508enum rtl_tx_desc_bit {
509 /* First doubleword. */
510 TD_LSO = (1 << 27), /* Large Send Offload */
511#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 512
2b7b4318
FR		 513 /* Second doubleword. */
514 TxVlanTag = (1 << 17), /* Add VLAN tag */
515};
516
517/* 8169, 8168b and 810x except 8102e. */
518enum rtl_tx_desc_bit_0 {
519 /* First doubleword. */
520#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
521 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
522 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
523 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
524};
525
526/* 8102e, 8168c and beyond. */
527enum rtl_tx_desc_bit_1 {
528 /* Second doubleword. */
529#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
530 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
531 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
532 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
533};
1da177e4 534
2b7b4318
FR		 535static const struct rtl_tx_desc_info {
536 struct {
537 u32 udp;
538 u32 tcp;
539 } checksum;
540 u16 mss_shift;
541 u16 opts_offset;
542} tx_desc_info [] = {
543 [RTL_TD_0] = {
544 .checksum = {
545 .udp = TD0_IP_CS | TD0_UDP_CS,
546 .tcp = TD0_IP_CS | TD0_TCP_CS
547 },
548 .mss_shift = TD0_MSS_SHIFT,
549 .opts_offset = 0
550 },
551 [RTL_TD_1] = {
552 .checksum = {
553 .udp = TD1_IP_CS | TD1_UDP_CS,
554 .tcp = TD1_IP_CS | TD1_TCP_CS
555 },
556 .mss_shift = TD1_MSS_SHIFT,
557 .opts_offset = 1
558 }
559};
560
561enum rtl_rx_desc_bit {
1da177e4
LT		 562 /* Rx private */
563 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
564 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
565
566#define RxProtoUDP (PID1)
567#define RxProtoTCP (PID0)
568#define RxProtoIP (PID1 | PID0)
569#define RxProtoMask RxProtoIP
570
571 IPFail = (1 << 16), /* IP checksum failed */
572 UDPFail = (1 << 15), /* UDP/IP checksum failed */
573 TCPFail = (1 << 14), /* TCP/IP checksum failed */
574 RxVlanTag = (1 << 16), /* VLAN tag available */
575};
576
577#define RsvdMask 0x3fffc000
578
579struct TxDesc {
6cccd6e7
REB		 580 __le32 opts1;
581 __le32 opts2;
582 __le64 addr;
1da177e4
LT		 583};
584
585struct RxDesc {
6cccd6e7
REB		 586 __le32 opts1;
587 __le32 opts2;
588 __le64 addr;
1da177e4
LT		 589};
590
591struct ring_info {
592 struct sk_buff *skb;
593 u32 len;
594 u8 __pad[sizeof(void *) - sizeof(u32)];
595};
596
f23e7fda 597enum features {
ccdffb9a
FR		 598 RTL_FEATURE_WOL = (1 << 0),
599 RTL_FEATURE_MSI = (1 << 1),
600 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 601};
602
355423d0
IV		 603struct rtl8169_counters {
604 __le64 tx_packets;
605 __le64 rx_packets;
606 __le64 tx_errors;
607 __le32 rx_errors;
608 __le16 rx_missed;
609 __le16 align_errors;
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
612 __le64 rx_unicast;
613 __le64 rx_broadcast;
614 __le32 rx_multicast;
615 __le16 tx_aborted;
616 __le16 tx_underun;
617};
618
1da177e4
LT		 619struct rtl8169_private {
620 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 621 struct pci_dev *pci_dev;
c4028958 622 struct net_device *dev;
bea3348e 623 struct napi_struct napi;
cecb5fd7 624 spinlock_t lock;
b57b7e5a 625 u32 msg_enable;
2b7b4318
FR		 626 u16 txd_version;
627 u16 mac_version;
1da177e4
LT		 628 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
629 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
630 u32 dirty_rx;
631 u32 dirty_tx;
632 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
633 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
634 dma_addr_t TxPhyAddr;
635 dma_addr_t RxPhyAddr;
6f0333b8 636 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 637 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 638 struct timer_list timer;
639 u16 cp_cmd;
0e485150
FR		 640 u16 intr_event;
641 u16 napi_event;
1da177e4 642 u16 intr_mask;
c0e45c1c 643
644 struct mdio_ops {
645 void (*write)(void __iomem *, int, int);
646 int (*read)(void __iomem *, int);
647 } mdio_ops;
648
065c27c1 649 struct pll_power_ops {
650 void (*down)(struct rtl8169_private *);
651 void (*up)(struct rtl8169_private *);
652 } pll_power_ops;
653
54405cde 654 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 655 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 656 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 657 void (*hw_start)(struct net_device *);
4da19633 658 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 659 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 660 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 661 int pcie_cap;
c4028958 662 struct delayed_work task;
f23e7fda 663 unsigned features;
ccdffb9a
FR		 664
665 struct mii_if_info mii;
355423d0 666 struct rtl8169_counters counters;
e1759441 667 u32 saved_wolopts;
f1e02ed1 668
669 const struct firmware *fw;
953a12cc 670#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 671};
672
979b6c13 673MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 674MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 675module_param(use_dac, int, 0);
4300e8c7 676MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 677module_param_named(debug, debug.msg_enable, int, 0);
678MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 679MODULE_LICENSE("GPL");
680MODULE_VERSION(RTL8169_VERSION);
bca03d5f 681MODULE_FIRMWARE(FIRMWARE_8168D_1);
682MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 683MODULE_FIRMWARE(FIRMWARE_8168E_1);
684MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 685MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 686
687static int rtl8169_open(struct net_device *dev);
61357325
SH		 688static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
689 struct net_device *dev);
7d12e780 690static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 691static int rtl8169_init_ring(struct net_device *dev);
07ce4064 692static void rtl_hw_start(struct net_device *dev);
1da177e4 693static int rtl8169_close(struct net_device *dev);
07ce4064 694static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 695static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 696static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 697static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 698 void __iomem *, u32 budget);
4dcb7d33 699static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 700static void rtl8169_down(struct net_device *dev);
99f252b0 701static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 702static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 703
1da177e4 704static const unsigned int rtl8169_rx_config =
5b0384f4 705 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 706
b646d900 707static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
708{
709 void __iomem *ioaddr = tp->mmio_addr;
710 int i;
711
712 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
713 for (i = 0; i < 20; i++) {
714 udelay(100);
715 if (RTL_R32(OCPAR) & OCPAR_FLAG)
716 break;
717 }
718 return RTL_R32(OCPDR);
719}
720
721static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
722{
723 void __iomem *ioaddr = tp->mmio_addr;
724 int i;
725
726 RTL_W32(OCPDR, data);
727 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
728 for (i = 0; i < 20; i++) {
729 udelay(100);
730 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
731 break;
732 }
733}
734
fac5b3ca 735static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 736{
fac5b3ca 737 void __iomem *ioaddr = tp->mmio_addr;
b646d900 738 int i;
739
740 RTL_W8(ERIDR, cmd);
741 RTL_W32(ERIAR, 0x800010e8);
742 msleep(2);
743 for (i = 0; i < 5; i++) {
744 udelay(100);
1e4e82ba 745 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 746 break;
747 }
748
fac5b3ca 749 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 750}
751
752#define OOB_CMD_RESET 0x00
753#define OOB_CMD_DRIVER_START 0x05
754#define OOB_CMD_DRIVER_STOP 0x06
755
cecb5fd7
FR		 756static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
757{
758 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
759}
760
b646d900 761static void rtl8168_driver_start(struct rtl8169_private *tp)
762{
cecb5fd7 763 u16 reg;
b646d900 764 int i;
765
766 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
767
cecb5fd7 768 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 769
b646d900 770 for (i = 0; i < 10; i++) {
771 msleep(10);
4804b3b3 772 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 773 break;
774 }
775}
776
777static void rtl8168_driver_stop(struct rtl8169_private *tp)
778{
cecb5fd7 779 u16 reg;
b646d900 780 int i;
781
782 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
783
cecb5fd7 784 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 785
b646d900 786 for (i = 0; i < 10; i++) {
787 msleep(10);
4804b3b3 788 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 789 break;
790 }
791}
792
4804b3b3 793static int r8168dp_check_dash(struct rtl8169_private *tp)
794{
cecb5fd7 795 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 796
cecb5fd7 797 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 798}
b646d900 799
4da19633 800static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 801{
802 int i;
803
a6baf3af 804 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 805
2371408c 806 for (i = 20; i > 0; i--) {
07d3f51f
FR		 807 /*
808 * Check if the RTL8169 has completed writing to the specified
809 * MII register.
810 */
5b0384f4 811 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 812 break;
2371408c 813 udelay(25);
1da177e4 814 }
024a07ba 815 /*
81a95f04
TT		 816 * According to hardware specs a 20us delay is required after write
817 * complete indication, but before sending next command.
024a07ba 818 */
81a95f04 819 udelay(20);
1da177e4
LT		 820}
821
4da19633 822static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 823{
824 int i, value = -1;
825
a6baf3af 826 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 827
2371408c 828 for (i = 20; i > 0; i--) {
07d3f51f
FR		 829 /*
830 * Check if the RTL8169 has completed retrieving data from
831 * the specified MII register.
832 */
1da177e4 833 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 834 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 835 break;
836 }
2371408c 837 udelay(25);
1da177e4 838 }
81a95f04
TT		 839 /*
840 * According to hardware specs a 20us delay is required after read
841 * complete indication, but before sending next command.
842 */
843 udelay(20);
844
1da177e4
LT		 845 return value;
846}
847
c0e45c1c 848static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
849{
850 int i;
851
852 RTL_W32(OCPDR, data |
853 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
854 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
855 RTL_W32(EPHY_RXER_NUM, 0);
856
857 for (i = 0; i < 100; i++) {
858 mdelay(1);
859 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
860 break;
861 }
862}
863
864static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
865{
866 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
867 (value & OCPDR_DATA_MASK));
868}
869
870static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
871{
872 int i;
873
874 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
875
876 mdelay(1);
877 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
878 RTL_W32(EPHY_RXER_NUM, 0);
879
880 for (i = 0; i < 100; i++) {
881 mdelay(1);
882 if (RTL_R32(OCPAR) & OCPAR_FLAG)
883 break;
884 }
885
886 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
887}
888
e6de30d6 889#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
890
891static void r8168dp_2_mdio_start(void __iomem *ioaddr)
892{
893 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
894}
895
896static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
897{
898 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
899}
900
901static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
902{
903 r8168dp_2_mdio_start(ioaddr);
904
905 r8169_mdio_write(ioaddr, reg_addr, value);
906
907 r8168dp_2_mdio_stop(ioaddr);
908}
909
910static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
911{
912 int value;
913
914 r8168dp_2_mdio_start(ioaddr);
915
916 value = r8169_mdio_read(ioaddr, reg_addr);
917
918 r8168dp_2_mdio_stop(ioaddr);
919
920 return value;
921}
922
4da19633 923static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 924{
c0e45c1c 925 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 926}
927
4da19633 928static int rtl_readphy(struct rtl8169_private *tp, int location)
929{
c0e45c1c 930 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 931}
932
933static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
934{
935 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
936}
937
938static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 939{
940 int val;
941
4da19633 942 val = rtl_readphy(tp, reg_addr);
943 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 944}
945
ccdffb9a
FR		 946static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
947 int val)
948{
949 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 950
4da19633 951 rtl_writephy(tp, location, val);
ccdffb9a
FR		 952}
953
954static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
955{
956 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 957
4da19633 958 return rtl_readphy(tp, location);
ccdffb9a
FR		 959}
960
dacf8154
FR		 961static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
962{
963 unsigned int i;
964
965 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
966 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
967
968 for (i = 0; i < 100; i++) {
969 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
970 break;
971 udelay(10);
972 }
973}
974
975static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
976{
977 u16 value = 0xffff;
978 unsigned int i;
979
980 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
981
982 for (i = 0; i < 100; i++) {
983 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
984 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
985 break;
986 }
987 udelay(10);
988 }
989
990 return value;
991}
992
993static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
994{
995 unsigned int i;
996
997 RTL_W32(CSIDR, value);
998 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
999 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1000
1001 for (i = 0; i < 100; i++) {
1002 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1003 break;
1004 udelay(10);
1005 }
1006}
1007
1008static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1009{
1010 u32 value = ~0x00;
1011 unsigned int i;
1012
1013 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1014 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1015
1016 for (i = 0; i < 100; i++) {
1017 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1018 value = RTL_R32(CSIDR);
1019 break;
1020 }
1021 udelay(10);
1022 }
1023
1024 return value;
1025}
1026
daf9df6d 1027static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1028{
1029 u8 value = 0xff;
1030 unsigned int i;
1031
1032 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1033
1034 for (i = 0; i < 300; i++) {
1035 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1036 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1037 break;
1038 }
1039 udelay(100);
1040 }
1041
1042 return value;
1043}
1044
1da177e4
LT		 1045static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1046{
1047 RTL_W16(IntrMask, 0x0000);
1048
1049 RTL_W16(IntrStatus, 0xffff);
1050}
1051
1052static void rtl8169_asic_down(void __iomem *ioaddr)
1053{
1054 RTL_W8(ChipCmd, 0x00);
1055 rtl8169_irq_mask_and_ack(ioaddr);
1056 RTL_R16(CPlusCmd);
1057}
1058
4da19633 1059static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1060{
4da19633 1061 void __iomem *ioaddr = tp->mmio_addr;
1062
1da177e4
LT		 1063 return RTL_R32(TBICSR) & TBIReset;
1064}
1065
4da19633 1066static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1067{
4da19633 1068 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1069}
1070
1071static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1072{
1073 return RTL_R32(TBICSR) & TBILinkOk;
1074}
1075
1076static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1077{
1078 return RTL_R8(PHYstatus) & LinkStatus;
1079}
1080
4da19633 1081static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1082{
4da19633 1083 void __iomem *ioaddr = tp->mmio_addr;
1084
1da177e4
LT		 1085 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1086}
1087
4da19633 1088static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1089{
1090 unsigned int val;
1091
4da19633 1092 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1093 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1094}
1095
e4fbce74 1096static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1097 struct rtl8169_private *tp,
1098 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1099{
1100 unsigned long flags;
1101
1102 spin_lock_irqsave(&tp->lock, flags);
1103 if (tp->link_ok(ioaddr)) {
e1759441 1104 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1105 if (pm)
1106 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1107 netif_carrier_on(dev);
1519e57f
FR		 1108 if (net_ratelimit())
1109 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1110 } else {
1da177e4 1111 netif_carrier_off(dev);
bf82c189 1112 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1113 if (pm)
1114 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1115 }
1da177e4
LT		 1116 spin_unlock_irqrestore(&tp->lock, flags);
1117}
1118
e4fbce74
RW		 1119static void rtl8169_check_link_status(struct net_device *dev,
1120 struct rtl8169_private *tp,
1121 void __iomem *ioaddr)
1122{
1123 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1124}
1125
e1759441
RW		 1126#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1127
1128static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1129{
61a4dcc2
FR		 1130 void __iomem *ioaddr = tp->mmio_addr;
1131 u8 options;
e1759441 1132 u32 wolopts = 0;
61a4dcc2
FR		 1133
1134 options = RTL_R8(Config1);
1135 if (!(options & PMEnable))
e1759441 1136 return 0;
61a4dcc2
FR		 1137
1138 options = RTL_R8(Config3);
1139 if (options & LinkUp)
e1759441 1140 wolopts |= WAKE_PHY;
61a4dcc2 1141 if (options & MagicPacket)
e1759441 1142 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1143
1144 options = RTL_R8(Config5);
1145 if (options & UWF)
e1759441 1146 wolopts |= WAKE_UCAST;
61a4dcc2 1147 if (options & BWF)
e1759441 1148 wolopts |= WAKE_BCAST;
61a4dcc2 1149 if (options & MWF)
e1759441 1150 wolopts |= WAKE_MCAST;
61a4dcc2 1151
e1759441 1152 return wolopts;
61a4dcc2
FR		 1153}
1154
e1759441 1155static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1156{
1157 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1158
1159 spin_lock_irq(&tp->lock);
1160
1161 wol->supported = WAKE_ANY;
1162 wol->wolopts = __rtl8169_get_wol(tp);
1163
1164 spin_unlock_irq(&tp->lock);
1165}
1166
1167static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1168{
61a4dcc2 1169 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1170 unsigned int i;
350f7596 1171 static const struct {
61a4dcc2
FR		 1172 u32 opt;
1173 u16 reg;
1174 u8 mask;
1175 } cfg[] = {
1176 { WAKE_ANY, Config1, PMEnable },
1177 { WAKE_PHY, Config3, LinkUp },
1178 { WAKE_MAGIC, Config3, MagicPacket },
1179 { WAKE_UCAST, Config5, UWF },
1180 { WAKE_BCAST, Config5, BWF },
1181 { WAKE_MCAST, Config5, MWF },
1182 { WAKE_ANY, Config5, LanWake }
1183 };
1184
61a4dcc2
FR		 1185 RTL_W8(Cfg9346, Cfg9346_Unlock);
1186
1187 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1188 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1189 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1190 options |= cfg[i].mask;
1191 RTL_W8(cfg[i].reg, options);
1192 }
1193
1194 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1195}
1196
1197static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1198{
1199 struct rtl8169_private *tp = netdev_priv(dev);
1200
1201 spin_lock_irq(&tp->lock);
61a4dcc2 1202
f23e7fda
FR		 1203 if (wol->wolopts)
1204 tp->features |= RTL_FEATURE_WOL;
1205 else
1206 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1207 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1208 spin_unlock_irq(&tp->lock);
1209
ea80907f 1210 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1211
61a4dcc2
FR		 1212 return 0;
1213}
1214
31bd204f
FR		 1215static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1216{
85bffe6c 1217 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1218}
1219
1da177e4
LT		 1220static void rtl8169_get_drvinfo(struct net_device *dev,
1221 struct ethtool_drvinfo *info)
1222{
1223 struct rtl8169_private *tp = netdev_priv(dev);
1224
1225 strcpy(info->driver, MODULENAME);
1226 strcpy(info->version, RTL8169_VERSION);
1227 strcpy(info->bus_info, pci_name(tp->pci_dev));
31bd204f
FR		 1228 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1229 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1da177e4
LT		 1230}
1231
1232static int rtl8169_get_regs_len(struct net_device *dev)
1233{
1234 return R8169_REGS_SIZE;
1235}
1236
1237static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1238 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1239{
1240 struct rtl8169_private *tp = netdev_priv(dev);
1241 void __iomem *ioaddr = tp->mmio_addr;
1242 int ret = 0;
1243 u32 reg;
1244
1245 reg = RTL_R32(TBICSR);
1246 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1247 (duplex == DUPLEX_FULL)) {
1248 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1249 } else if (autoneg == AUTONEG_ENABLE)
1250 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1251 else {
bf82c189
JP		 1252 netif_warn(tp, link, dev,
1253 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1254 ret = -EOPNOTSUPP;
1255 }
1256
1257 return ret;
1258}
1259
1260static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1261 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1262{
1263 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1264 int giga_ctrl, bmcr;
54405cde 1265 int rc = -EINVAL;
1da177e4 1266
716b50a3 1267 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1268
1269 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1270 int auto_nego;
1271
4da19633 1272 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1273 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1274 ADVERTISE_100HALF | ADVERTISE_100FULL);
1275
1276 if (adv & ADVERTISED_10baseT_Half)
1277 auto_nego |= ADVERTISE_10HALF;
1278 if (adv & ADVERTISED_10baseT_Full)
1279 auto_nego |= ADVERTISE_10FULL;
1280 if (adv & ADVERTISED_100baseT_Half)
1281 auto_nego |= ADVERTISE_100HALF;
1282 if (adv & ADVERTISED_100baseT_Full)
1283 auto_nego |= ADVERTISE_100FULL;
1284
3577aa1b 1285 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1286
4da19633 1287 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1288 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1289
3577aa1b 1290 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1291 if (tp->mii.supports_gmii) {
54405cde
ON		 1292 if (adv & ADVERTISED_1000baseT_Half)
1293 giga_ctrl |= ADVERTISE_1000HALF;
1294 if (adv & ADVERTISED_1000baseT_Full)
1295 giga_ctrl |= ADVERTISE_1000FULL;
1296 } else if (adv & (ADVERTISED_1000baseT_Half |
1297 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1298 netif_info(tp, link, dev,
1299 "PHY does not support 1000Mbps\n");
54405cde 1300 goto out;
bcf0bf90 1301 }
1da177e4 1302
3577aa1b 1303 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1304
4da19633 1305 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1306 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1307 } else {
1308 giga_ctrl = 0;
1309
1310 if (speed == SPEED_10)
1311 bmcr = 0;
1312 else if (speed == SPEED_100)
1313 bmcr = BMCR_SPEED100;
1314 else
54405cde 1315 goto out;
3577aa1b 1316
1317 if (duplex == DUPLEX_FULL)
1318 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1319 }
1320
4da19633 1321 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1322
cecb5fd7
FR		 1323 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1324 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1325 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1326 rtl_writephy(tp, 0x17, 0x2138);
1327 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1328 } else {
4da19633 1329 rtl_writephy(tp, 0x17, 0x2108);
1330 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1331 }
1332 }
1333
54405cde
ON		 1334 rc = 0;
1335out:
1336 return rc;
1da177e4
LT		 1337}
1338
1339static int rtl8169_set_speed(struct net_device *dev,
54405cde 1340 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1341{
1342 struct rtl8169_private *tp = netdev_priv(dev);
1343 int ret;
1344
54405cde 1345 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1346 if (ret < 0)
1347 goto out;
1da177e4 1348
4876cc1e
FR		 1349 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1350 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1351 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1352 }
1353out:
1da177e4
LT		 1354 return ret;
1355}
1356
1357static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1358{
1359 struct rtl8169_private *tp = netdev_priv(dev);
1360 unsigned long flags;
1361 int ret;
1362
4876cc1e
FR		 1363 del_timer_sync(&tp->timer);
1364
1da177e4 1365 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1366 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1367 cmd->duplex, cmd->advertising);
1da177e4 1368 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1369
1da177e4
LT		 1370 return ret;
1371}
1372
350fb32a 1373static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1374{
2b7b4318 1375 if (dev->mtu > TD_MSS_MAX)
350fb32a 1376 features &= ~NETIF_F_ALL_TSO;
1da177e4 1377
350fb32a 1378 return features;
1da177e4
LT		 1379}
1380
350fb32a 1381static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1382{
1383 struct rtl8169_private *tp = netdev_priv(dev);
1384 void __iomem *ioaddr = tp->mmio_addr;
1385 unsigned long flags;
1386
1387 spin_lock_irqsave(&tp->lock, flags);
1388
350fb32a 1389 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1390 tp->cp_cmd |= RxChkSum;
1391 else
1392 tp->cp_cmd &= ~RxChkSum;
1393
350fb32a
MM		 1394 if (dev->features & NETIF_F_HW_VLAN_RX)
1395 tp->cp_cmd |= RxVlan;
1396 else
1397 tp->cp_cmd &= ~RxVlan;
1398
1da177e4
LT		 1399 RTL_W16(CPlusCmd, tp->cp_cmd);
1400 RTL_R16(CPlusCmd);
1401
1402 spin_unlock_irqrestore(&tp->lock, flags);
1403
1404 return 0;
1405}
1406
1da177e4
LT		 1407static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1408 struct sk_buff *skb)
1409{
eab6d18d 1410 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1411 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1412}
1413
7a8fc77b 1414static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1415{
1416 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1417
7a8fc77b
FR		 1418 if (opts2 & RxVlanTag)
1419 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1420
1da177e4 1421 desc->opts2 = 0;
1da177e4
LT		 1422}
1423
ccdffb9a 1424static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1425{
1426 struct rtl8169_private *tp = netdev_priv(dev);
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 u32 status;
1429
1430 cmd->supported =
1431 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1432 cmd->port = PORT_FIBRE;
1433 cmd->transceiver = XCVR_INTERNAL;
1434
1435 status = RTL_R32(TBICSR);
1436 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1437 cmd->autoneg = !!(status & TBINwEnable);
1438
70739497 1439 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1440 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1441
1442 return 0;
1da177e4
LT		 1443}
1444
ccdffb9a 1445static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1446{
1447 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1448
1449 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1450}
1451
1452static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453{
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455 unsigned long flags;
ccdffb9a 1456 int rc;
1da177e4
LT		 1457
1458 spin_lock_irqsave(&tp->lock, flags);
1459
ccdffb9a 1460 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1461
1462 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1463 return rc;
1da177e4
LT		 1464}
1465
1466static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1467 void *p)
1468{
5b0384f4
FR		 1469 struct rtl8169_private *tp = netdev_priv(dev);
1470 unsigned long flags;
1da177e4 1471
5b0384f4
FR		 1472 if (regs->len > R8169_REGS_SIZE)
1473 regs->len = R8169_REGS_SIZE;
1da177e4 1474
5b0384f4
FR		 1475 spin_lock_irqsave(&tp->lock, flags);
1476 memcpy_fromio(p, tp->mmio_addr, regs->len);
1477 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1478}
1479
b57b7e5a
SH		 1480static u32 rtl8169_get_msglevel(struct net_device *dev)
1481{
1482 struct rtl8169_private *tp = netdev_priv(dev);
1483
1484 return tp->msg_enable;
1485}
1486
1487static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1488{
1489 struct rtl8169_private *tp = netdev_priv(dev);
1490
1491 tp->msg_enable = value;
1492}
1493
d4a3a0fc
SH		 1494static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1495 "tx_packets",
1496 "rx_packets",
1497 "tx_errors",
1498 "rx_errors",
1499 "rx_missed",
1500 "align_errors",
1501 "tx_single_collisions",
1502 "tx_multi_collisions",
1503 "unicast",
1504 "broadcast",
1505 "multicast",
1506 "tx_aborted",
1507 "tx_underrun",
1508};
1509
b9f2c044 1510static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1511{
b9f2c044
JG		 1512 switch (sset) {
1513 case ETH_SS_STATS:
1514 return ARRAY_SIZE(rtl8169_gstrings);
1515 default:
1516 return -EOPNOTSUPP;
1517 }
d4a3a0fc
SH		 1518}
1519
355423d0 1520static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1521{
1522 struct rtl8169_private *tp = netdev_priv(dev);
1523 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1524 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1525 struct rtl8169_counters *counters;
1526 dma_addr_t paddr;
1527 u32 cmd;
355423d0 1528 int wait = 1000;
d4a3a0fc 1529
355423d0
IV		 1530 /*
1531 * Some chips are unable to dump tally counters when the receiver
1532 * is disabled.
1533 */
1534 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1535 return;
d4a3a0fc 1536
48addcc9 1537 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1538 if (!counters)
1539 return;
1540
1541 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1542 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1543 RTL_W32(CounterAddrLow, cmd);
1544 RTL_W32(CounterAddrLow, cmd | CounterDump);
1545
355423d0
IV		 1546 while (wait--) {
1547 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1548 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1549 break;
355423d0
IV		 1550 }
1551 udelay(10);
d4a3a0fc
SH		 1552 }
1553
1554 RTL_W32(CounterAddrLow, 0);
1555 RTL_W32(CounterAddrHigh, 0);
1556
48addcc9 1557 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1558}
1559
355423d0
IV		 1560static void rtl8169_get_ethtool_stats(struct net_device *dev,
1561 struct ethtool_stats *stats, u64 *data)
1562{
1563 struct rtl8169_private *tp = netdev_priv(dev);
1564
1565 ASSERT_RTNL();
1566
1567 rtl8169_update_counters(dev);
1568
1569 data[0] = le64_to_cpu(tp->counters.tx_packets);
1570 data[1] = le64_to_cpu(tp->counters.rx_packets);
1571 data[2] = le64_to_cpu(tp->counters.tx_errors);
1572 data[3] = le32_to_cpu(tp->counters.rx_errors);
1573 data[4] = le16_to_cpu(tp->counters.rx_missed);
1574 data[5] = le16_to_cpu(tp->counters.align_errors);
1575 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1576 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1577 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1578 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1579 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1580 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1581 data[12] = le16_to_cpu(tp->counters.tx_underun);
1582}
1583
d4a3a0fc
SH		 1584static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1585{
1586 switch(stringset) {
1587 case ETH_SS_STATS:
1588 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1589 break;
1590 }
1591}
1592
7282d491 1593static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1594 .get_drvinfo = rtl8169_get_drvinfo,
1595 .get_regs_len = rtl8169_get_regs_len,
1596 .get_link = ethtool_op_get_link,
1597 .get_settings = rtl8169_get_settings,
1598 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1599 .get_msglevel = rtl8169_get_msglevel,
1600 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1601 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1602 .get_wol = rtl8169_get_wol,
1603 .set_wol = rtl8169_set_wol,
d4a3a0fc 1604 .get_strings = rtl8169_get_strings,
b9f2c044 1605 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1606 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1607};
1608
07d3f51f 1609static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1610 struct net_device *dev, u8 default_version)
1da177e4 1611{
5d320a20 1612 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1613 /*
1614 * The driver currently handles the 8168Bf and the 8168Be identically
1615 * but they can be identified more specifically through the test below
1616 * if needed:
1617 *
1618 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1619 *
1620 * Same thing for the 8101Eb and the 8101Ec:
1621 *
1622 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1623 */
3744100e 1624 static const struct rtl_mac_info {
1da177e4 1625 u32 mask;
e3cf0cc0 1626 u32 val;
1da177e4
LT		 1627 int mac_version;
1628 } mac_info[] = {
01dc7fec 1629 /* 8168E family. */
1630 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1631 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1632 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1633
5b538df9 1634 /* 8168D family. */
daf9df6d 1635 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1636 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1637 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1638
e6de30d6 1639 /* 8168DP family. */
1640 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1641 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1642 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1643
ef808d50 1644 /* 8168C family. */
17c99297 1645 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1646 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1647 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1648 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1649 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1650 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1651 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1652 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1653 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1654
1655 /* 8168B family. */
1656 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1657 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1658 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1659 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1660
1661 /* 8101 family. */
36a0e6c2 1662 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1663 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1664 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1665 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1666 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1667 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1668 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1669 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1670 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1671 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1672 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1673 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1674 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1675 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1676 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1677 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1678 /* FIXME: where did these entries come from ? -- FR */
1679 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1680 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1681
1682 /* 8110 family. */
1683 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1684 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1685 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1686 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1687 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1688 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1689
f21b75e9
JD		 1690 /* Catch-all */
1691 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1692 };
1693 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1694 u32 reg;
1695
e3cf0cc0
FR		 1696 reg = RTL_R32(TxConfig);
1697 while ((reg & p->mask) != p->val)
1da177e4
LT		 1698 p++;
1699 tp->mac_version = p->mac_version;
5d320a20
FR		 1700
1701 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1702 netif_notice(tp, probe, dev,
1703 "unknown MAC, using family default\n");
1704 tp->mac_version = default_version;
1705 }
1da177e4
LT		 1706}
1707
1708static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1709{
bcf0bf90 1710 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1711}
1712
867763c1
FR		 1713struct phy_reg {
1714 u16 reg;
1715 u16 val;
1716};
1717
4da19633 1718static void rtl_writephy_batch(struct rtl8169_private *tp,
1719 const struct phy_reg *regs, int len)
867763c1
FR		 1720{
1721 while (len-- > 0) {
4da19633 1722 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1723 regs++;
1724 }
1725}
1726
bca03d5f 1727#define PHY_READ 0x00000000
1728#define PHY_DATA_OR 0x10000000
1729#define PHY_DATA_AND 0x20000000
1730#define PHY_BJMPN 0x30000000
1731#define PHY_READ_EFUSE 0x40000000
1732#define PHY_READ_MAC_BYTE 0x50000000
1733#define PHY_WRITE_MAC_BYTE 0x60000000
1734#define PHY_CLEAR_READCOUNT 0x70000000
1735#define PHY_WRITE 0x80000000
1736#define PHY_READCOUNT_EQ_SKIP 0x90000000
1737#define PHY_COMP_EQ_SKIPN 0xa0000000
1738#define PHY_COMP_NEQ_SKIPN 0xb0000000
1739#define PHY_WRITE_PREVIOUS 0xc0000000
1740#define PHY_SKIPN 0xd0000000
1741#define PHY_DELAY_MS 0xe0000000
1742#define PHY_WRITE_ERI_WORD 0xf0000000
1743
1744static void
1745rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1746{
bca03d5f 1747 __le32 *phytable = (__le32 *)fw->data;
1748 struct net_device *dev = tp->dev;
42b82dc1 1749 size_t index, fw_size = fw->size / sizeof(*phytable);
1750 u32 predata, count;
bca03d5f 1751
1752 if (fw->size % sizeof(*phytable)) {
1753 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1754 return;
1755 }
1756
42b82dc1 1757 for (index = 0; index < fw_size; index++) {
1758 u32 action = le32_to_cpu(phytable[index]);
1759 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1760
42b82dc1 1761 switch(action & 0xf0000000) {
1762 case PHY_READ:
1763 case PHY_DATA_OR:
1764 case PHY_DATA_AND:
1765 case PHY_READ_EFUSE:
1766 case PHY_CLEAR_READCOUNT:
1767 case PHY_WRITE:
1768 case PHY_WRITE_PREVIOUS:
1769 case PHY_DELAY_MS:
1770 break;
1771
1772 case PHY_BJMPN:
1773 if (regno > index) {
1774 netif_err(tp, probe, tp->dev,
cecb5fd7 1775 "Out of range of firmware\n");
42b82dc1 1776 return;
1777 }
1778 break;
1779 case PHY_READCOUNT_EQ_SKIP:
1780 if (index + 2 >= fw_size) {
1781 netif_err(tp, probe, tp->dev,
cecb5fd7 1782 "Out of range of firmware\n");
42b82dc1 1783 return;
1784 }
1785 break;
1786 case PHY_COMP_EQ_SKIPN:
1787 case PHY_COMP_NEQ_SKIPN:
1788 case PHY_SKIPN:
1789 if (index + 1 + regno >= fw_size) {
1790 netif_err(tp, probe, tp->dev,
cecb5fd7 1791 "Out of range of firmware\n");
42b82dc1 1792 return;
1793 }
bca03d5f 1794 break;
1795
42b82dc1 1796 case PHY_READ_MAC_BYTE:
1797 case PHY_WRITE_MAC_BYTE:
1798 case PHY_WRITE_ERI_WORD:
1799 default:
1800 netif_err(tp, probe, tp->dev,
1801 "Invalid action 0x%08x\n", action);
bca03d5f 1802 return;
1803 }
1804 }
1805
42b82dc1 1806 predata = 0;
1807 count = 0;
1808
1809 for (index = 0; index < fw_size; ) {
1810 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1811 u32 data = action & 0x0000ffff;
42b82dc1 1812 u32 regno = (action & 0x0fff0000) >> 16;
1813
1814 if (!action)
1815 break;
bca03d5f 1816
1817 switch(action & 0xf0000000) {
42b82dc1 1818 case PHY_READ:
1819 predata = rtl_readphy(tp, regno);
1820 count++;
1821 index++;
1822 break;
1823 case PHY_DATA_OR:
1824 predata |= data;
1825 index++;
1826 break;
1827 case PHY_DATA_AND:
1828 predata &= data;
1829 index++;
1830 break;
1831 case PHY_BJMPN:
1832 index -= regno;
1833 break;
1834 case PHY_READ_EFUSE:
1835 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1836 index++;
1837 break;
1838 case PHY_CLEAR_READCOUNT:
1839 count = 0;
1840 index++;
1841 break;
bca03d5f 1842 case PHY_WRITE:
42b82dc1 1843 rtl_writephy(tp, regno, data);
1844 index++;
1845 break;
1846 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 1847 index += (count == data) ? 2 : 1;
bca03d5f 1848 break;
42b82dc1 1849 case PHY_COMP_EQ_SKIPN:
1850 if (predata == data)
1851 index += regno;
1852 index++;
1853 break;
1854 case PHY_COMP_NEQ_SKIPN:
1855 if (predata != data)
1856 index += regno;
1857 index++;
1858 break;
1859 case PHY_WRITE_PREVIOUS:
1860 rtl_writephy(tp, regno, predata);
1861 index++;
1862 break;
1863 case PHY_SKIPN:
1864 index += regno + 1;
1865 break;
1866 case PHY_DELAY_MS:
1867 mdelay(data);
1868 index++;
1869 break;
1870
1871 case PHY_READ_MAC_BYTE:
1872 case PHY_WRITE_MAC_BYTE:
1873 case PHY_WRITE_ERI_WORD:
bca03d5f 1874 default:
1875 BUG();
1876 }
1877 }
1878}
1879
f1e02ed1 1880static void rtl_release_firmware(struct rtl8169_private *tp)
1881{
953a12cc
FR		 1882 if (!IS_ERR_OR_NULL(tp->fw))
1883 release_firmware(tp->fw);
1884 tp->fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1885}
1886
953a12cc 1887static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1888{
953a12cc 1889 const struct firmware *fw = tp->fw;
f1e02ed1 1890
1891 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
953a12cc
FR		 1892 if (!IS_ERR_OR_NULL(fw))
1893 rtl_phy_write_fw(tp, fw);
1894}
1895
1896static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1897{
1898 if (rtl_readphy(tp, reg) != val)
1899 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1900 else
1901 rtl_apply_firmware(tp);
f1e02ed1 1902}
1903
4da19633 1904static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1905{
350f7596 1906 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1907 { 0x1f, 0x0001 },
1908 { 0x06, 0x006e },
1909 { 0x08, 0x0708 },
1910 { 0x15, 0x4000 },
1911 { 0x18, 0x65c7 },
1da177e4 1912
0b9b571d 1913 { 0x1f, 0x0001 },
1914 { 0x03, 0x00a1 },
1915 { 0x02, 0x0008 },
1916 { 0x01, 0x0120 },
1917 { 0x00, 0x1000 },
1918 { 0x04, 0x0800 },
1919 { 0x04, 0x0000 },
1da177e4 1920
0b9b571d 1921 { 0x03, 0xff41 },
1922 { 0x02, 0xdf60 },
1923 { 0x01, 0x0140 },
1924 { 0x00, 0x0077 },
1925 { 0x04, 0x7800 },
1926 { 0x04, 0x7000 },
1927
1928 { 0x03, 0x802f },
1929 { 0x02, 0x4f02 },
1930 { 0x01, 0x0409 },
1931 { 0x00, 0xf0f9 },
1932 { 0x04, 0x9800 },
1933 { 0x04, 0x9000 },
1934
1935 { 0x03, 0xdf01 },
1936 { 0x02, 0xdf20 },
1937 { 0x01, 0xff95 },
1938 { 0x00, 0xba00 },
1939 { 0x04, 0xa800 },
1940 { 0x04, 0xa000 },
1941
1942 { 0x03, 0xff41 },
1943 { 0x02, 0xdf20 },
1944 { 0x01, 0x0140 },
1945 { 0x00, 0x00bb },
1946 { 0x04, 0xb800 },
1947 { 0x04, 0xb000 },
1948
1949 { 0x03, 0xdf41 },
1950 { 0x02, 0xdc60 },
1951 { 0x01, 0x6340 },
1952 { 0x00, 0x007d },
1953 { 0x04, 0xd800 },
1954 { 0x04, 0xd000 },
1955
1956 { 0x03, 0xdf01 },
1957 { 0x02, 0xdf20 },
1958 { 0x01, 0x100a },
1959 { 0x00, 0xa0ff },
1960 { 0x04, 0xf800 },
1961 { 0x04, 0xf000 },
1962
1963 { 0x1f, 0x0000 },
1964 { 0x0b, 0x0000 },
1965 { 0x00, 0x9200 }
1966 };
1da177e4 1967
4da19633 1968 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1969}
1970
4da19633 1971static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1972{
350f7596 1973 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1974 { 0x1f, 0x0002 },
1975 { 0x01, 0x90d0 },
1976 { 0x1f, 0x0000 }
1977 };
1978
4da19633 1979 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1980}
1981
4da19633 1982static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1983{
1984 struct pci_dev *pdev = tp->pci_dev;
1985 u16 vendor_id, device_id;
1986
1987 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1988 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1989
1990 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1991 return;
1992
4da19633 1993 rtl_writephy(tp, 0x1f, 0x0001);
1994 rtl_writephy(tp, 0x10, 0xf01b);
1995 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1996}
1997
4da19633 1998static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1999{
350f7596 2000 static const struct phy_reg phy_reg_init[] = {
2e955856 2001 { 0x1f, 0x0001 },
2002 { 0x04, 0x0000 },
2003 { 0x03, 0x00a1 },
2004 { 0x02, 0x0008 },
2005 { 0x01, 0x0120 },
2006 { 0x00, 0x1000 },
2007 { 0x04, 0x0800 },
2008 { 0x04, 0x9000 },
2009 { 0x03, 0x802f },
2010 { 0x02, 0x4f02 },
2011 { 0x01, 0x0409 },
2012 { 0x00, 0xf099 },
2013 { 0x04, 0x9800 },
2014 { 0x04, 0xa000 },
2015 { 0x03, 0xdf01 },
2016 { 0x02, 0xdf20 },
2017 { 0x01, 0xff95 },
2018 { 0x00, 0xba00 },
2019 { 0x04, 0xa800 },
2020 { 0x04, 0xf000 },
2021 { 0x03, 0xdf01 },
2022 { 0x02, 0xdf20 },
2023 { 0x01, 0x101a },
2024 { 0x00, 0xa0ff },
2025 { 0x04, 0xf800 },
2026 { 0x04, 0x0000 },
2027 { 0x1f, 0x0000 },
2028
2029 { 0x1f, 0x0001 },
2030 { 0x10, 0xf41b },
2031 { 0x14, 0xfb54 },
2032 { 0x18, 0xf5c7 },
2033 { 0x1f, 0x0000 },
2034
2035 { 0x1f, 0x0001 },
2036 { 0x17, 0x0cc0 },
2037 { 0x1f, 0x0000 }
2038 };
2039
4da19633 2040 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2041
4da19633 2042 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2043}
2044
4da19633 2045static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2046{
350f7596 2047 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2048 { 0x1f, 0x0001 },
2049 { 0x04, 0x0000 },
2050 { 0x03, 0x00a1 },
2051 { 0x02, 0x0008 },
2052 { 0x01, 0x0120 },
2053 { 0x00, 0x1000 },
2054 { 0x04, 0x0800 },
2055 { 0x04, 0x9000 },
2056 { 0x03, 0x802f },
2057 { 0x02, 0x4f02 },
2058 { 0x01, 0x0409 },
2059 { 0x00, 0xf099 },
2060 { 0x04, 0x9800 },
2061 { 0x04, 0xa000 },
2062 { 0x03, 0xdf01 },
2063 { 0x02, 0xdf20 },
2064 { 0x01, 0xff95 },
2065 { 0x00, 0xba00 },
2066 { 0x04, 0xa800 },
2067 { 0x04, 0xf000 },
2068 { 0x03, 0xdf01 },
2069 { 0x02, 0xdf20 },
2070 { 0x01, 0x101a },
2071 { 0x00, 0xa0ff },
2072 { 0x04, 0xf800 },
2073 { 0x04, 0x0000 },
2074 { 0x1f, 0x0000 },
2075
2076 { 0x1f, 0x0001 },
2077 { 0x0b, 0x8480 },
2078 { 0x1f, 0x0000 },
2079
2080 { 0x1f, 0x0001 },
2081 { 0x18, 0x67c7 },
2082 { 0x04, 0x2000 },
2083 { 0x03, 0x002f },
2084 { 0x02, 0x4360 },
2085 { 0x01, 0x0109 },
2086 { 0x00, 0x3022 },
2087 { 0x04, 0x2800 },
2088 { 0x1f, 0x0000 },
2089
2090 { 0x1f, 0x0001 },
2091 { 0x17, 0x0cc0 },
2092 { 0x1f, 0x0000 }
2093 };
2094
4da19633 2095 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2096}
2097
4da19633 2098static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2099{
350f7596 2100 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2101 { 0x10, 0xf41b },
2102 { 0x1f, 0x0000 }
2103 };
2104
4da19633 2105 rtl_writephy(tp, 0x1f, 0x0001);
2106 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2107
4da19633 2108 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2109}
2110
4da19633 2111static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2112{
350f7596 2113 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2114 { 0x1f, 0x0001 },
2115 { 0x10, 0xf41b },
2116 { 0x1f, 0x0000 }
2117 };
2118
4da19633 2119 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2120}
2121
4da19633 2122static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2123{
350f7596 2124 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2125 { 0x1f, 0x0000 },
2126 { 0x1d, 0x0f00 },
2127 { 0x1f, 0x0002 },
2128 { 0x0c, 0x1ec8 },
2129 { 0x1f, 0x0000 }
2130 };
2131
4da19633 2132 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2133}
2134
4da19633 2135static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2136{
350f7596 2137 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2138 { 0x1f, 0x0001 },
2139 { 0x1d, 0x3d98 },
2140 { 0x1f, 0x0000 }
2141 };
2142
4da19633 2143 rtl_writephy(tp, 0x1f, 0x0000);
2144 rtl_patchphy(tp, 0x14, 1 << 5);
2145 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2146
4da19633 2147 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2148}
2149
4da19633 2150static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2151{
350f7596 2152 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2153 { 0x1f, 0x0001 },
2154 { 0x12, 0x2300 },
867763c1
FR		 2155 { 0x1f, 0x0002 },
2156 { 0x00, 0x88d4 },
2157 { 0x01, 0x82b1 },
2158 { 0x03, 0x7002 },
2159 { 0x08, 0x9e30 },
2160 { 0x09, 0x01f0 },
2161 { 0x0a, 0x5500 },
2162 { 0x0c, 0x00c8 },
2163 { 0x1f, 0x0003 },
2164 { 0x12, 0xc096 },
2165 { 0x16, 0x000a },
f50d4275
FR		 2166 { 0x1f, 0x0000 },
2167 { 0x1f, 0x0000 },
2168 { 0x09, 0x2000 },
2169 { 0x09, 0x0000 }
867763c1
FR		 2170 };
2171
4da19633 2172 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2173
4da19633 2174 rtl_patchphy(tp, 0x14, 1 << 5);
2175 rtl_patchphy(tp, 0x0d, 1 << 5);
2176 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2177}
2178
4da19633 2179static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2180{
350f7596 2181 static const struct phy_reg phy_reg_init[] = {
f50d4275 2182 { 0x1f, 0x0001 },
7da97ec9 2183 { 0x12, 0x2300 },
f50d4275
FR		 2184 { 0x03, 0x802f },
2185 { 0x02, 0x4f02 },
2186 { 0x01, 0x0409 },
2187 { 0x00, 0xf099 },
2188 { 0x04, 0x9800 },
2189 { 0x04, 0x9000 },
2190 { 0x1d, 0x3d98 },
7da97ec9
FR		 2191 { 0x1f, 0x0002 },
2192 { 0x0c, 0x7eb8 },
f50d4275
FR		 2193 { 0x06, 0x0761 },
2194 { 0x1f, 0x0003 },
2195 { 0x16, 0x0f0a },
7da97ec9
FR		 2196 { 0x1f, 0x0000 }
2197 };
2198
4da19633 2199 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2200
4da19633 2201 rtl_patchphy(tp, 0x16, 1 << 0);
2202 rtl_patchphy(tp, 0x14, 1 << 5);
2203 rtl_patchphy(tp, 0x0d, 1 << 5);
2204 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2205}
2206
4da19633 2207static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2208{
350f7596 2209 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2210 { 0x1f, 0x0001 },
2211 { 0x12, 0x2300 },
2212 { 0x1d, 0x3d98 },
2213 { 0x1f, 0x0002 },
2214 { 0x0c, 0x7eb8 },
2215 { 0x06, 0x5461 },
2216 { 0x1f, 0x0003 },
2217 { 0x16, 0x0f0a },
2218 { 0x1f, 0x0000 }
2219 };
2220
4da19633 2221 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2222
4da19633 2223 rtl_patchphy(tp, 0x16, 1 << 0);
2224 rtl_patchphy(tp, 0x14, 1 << 5);
2225 rtl_patchphy(tp, 0x0d, 1 << 5);
2226 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2227}
2228
4da19633 2229static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2230{
4da19633 2231 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2232}
2233
bca03d5f 2234static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2235{
350f7596 2236 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2237 /* Channel Estimation */
5b538df9 2238 { 0x1f, 0x0001 },
daf9df6d 2239 { 0x06, 0x4064 },
2240 { 0x07, 0x2863 },
2241 { 0x08, 0x059c },
2242 { 0x09, 0x26b4 },
2243 { 0x0a, 0x6a19 },
2244 { 0x0b, 0xdcc8 },
2245 { 0x10, 0xf06d },
2246 { 0x14, 0x7f68 },
2247 { 0x18, 0x7fd9 },
2248 { 0x1c, 0xf0ff },
2249 { 0x1d, 0x3d9c },
5b538df9 2250 { 0x1f, 0x0003 },
daf9df6d 2251 { 0x12, 0xf49f },
2252 { 0x13, 0x070b },
2253 { 0x1a, 0x05ad },
bca03d5f 2254 { 0x14, 0x94c0 },
2255
2256 /*
2257 * Tx Error Issue
cecb5fd7 2258 * Enhance line driver power
bca03d5f 2259 */
5b538df9 2260 { 0x1f, 0x0002 },
daf9df6d 2261 { 0x06, 0x5561 },
2262 { 0x1f, 0x0005 },
2263 { 0x05, 0x8332 },
bca03d5f 2264 { 0x06, 0x5561 },
2265
2266 /*
2267 * Can not link to 1Gbps with bad cable
2268 * Decrease SNR threshold form 21.07dB to 19.04dB
2269 */
2270 { 0x1f, 0x0001 },
2271 { 0x17, 0x0cc0 },
daf9df6d 2272
5b538df9 2273 { 0x1f, 0x0000 },
bca03d5f 2274 { 0x0d, 0xf880 }
daf9df6d 2275 };
bca03d5f 2276 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2277
4da19633 2278 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2279
bca03d5f 2280 /*
2281 * Rx Error Issue
2282 * Fine Tune Switching regulator parameter
2283 */
4da19633 2284 rtl_writephy(tp, 0x1f, 0x0002);
2285 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2286 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2287
daf9df6d 2288 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2289 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2290 { 0x1f, 0x0002 },
2291 { 0x05, 0x669a },
2292 { 0x1f, 0x0005 },
2293 { 0x05, 0x8330 },
2294 { 0x06, 0x669a },
2295 { 0x1f, 0x0002 }
2296 };
2297 int val;
2298
4da19633 2299 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2300
4da19633 2301 val = rtl_readphy(tp, 0x0d);
daf9df6d 2302
2303 if ((val & 0x00ff) != 0x006c) {
350f7596 2304 static const u32 set[] = {
daf9df6d 2305 0x0065, 0x0066, 0x0067, 0x0068,
2306 0x0069, 0x006a, 0x006b, 0x006c
2307 };
2308 int i;
2309
4da19633 2310 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2311
2312 val &= 0xff00;
2313 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2314 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2315 }
2316 } else {
350f7596 2317 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2318 { 0x1f, 0x0002 },
2319 { 0x05, 0x6662 },
2320 { 0x1f, 0x0005 },
2321 { 0x05, 0x8330 },
2322 { 0x06, 0x6662 }
2323 };
2324
4da19633 2325 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2326 }
2327
bca03d5f 2328 /* RSET couple improve */
4da19633 2329 rtl_writephy(tp, 0x1f, 0x0002);
2330 rtl_patchphy(tp, 0x0d, 0x0300);
2331 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2332
bca03d5f 2333 /* Fine tune PLL performance */
4da19633 2334 rtl_writephy(tp, 0x1f, 0x0002);
2335 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2336 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2337
4da19633 2338 rtl_writephy(tp, 0x1f, 0x0005);
2339 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2340
2341 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2342
4da19633 2343 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2344}
2345
bca03d5f 2346static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2347{
350f7596 2348 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2349 /* Channel Estimation */
daf9df6d 2350 { 0x1f, 0x0001 },
2351 { 0x06, 0x4064 },
2352 { 0x07, 0x2863 },
2353 { 0x08, 0x059c },
2354 { 0x09, 0x26b4 },
2355 { 0x0a, 0x6a19 },
2356 { 0x0b, 0xdcc8 },
2357 { 0x10, 0xf06d },
2358 { 0x14, 0x7f68 },
2359 { 0x18, 0x7fd9 },
2360 { 0x1c, 0xf0ff },
2361 { 0x1d, 0x3d9c },
2362 { 0x1f, 0x0003 },
2363 { 0x12, 0xf49f },
2364 { 0x13, 0x070b },
2365 { 0x1a, 0x05ad },
2366 { 0x14, 0x94c0 },
2367
bca03d5f 2368 /*
2369 * Tx Error Issue
cecb5fd7 2370 * Enhance line driver power
bca03d5f 2371 */
daf9df6d 2372 { 0x1f, 0x0002 },
2373 { 0x06, 0x5561 },
2374 { 0x1f, 0x0005 },
2375 { 0x05, 0x8332 },
bca03d5f 2376 { 0x06, 0x5561 },
2377
2378 /*
2379 * Can not link to 1Gbps with bad cable
2380 * Decrease SNR threshold form 21.07dB to 19.04dB
2381 */
2382 { 0x1f, 0x0001 },
2383 { 0x17, 0x0cc0 },
daf9df6d 2384
2385 { 0x1f, 0x0000 },
bca03d5f 2386 { 0x0d, 0xf880 }
5b538df9 2387 };
bca03d5f 2388 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2389
4da19633 2390 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2391
daf9df6d 2392 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2393 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2394 { 0x1f, 0x0002 },
2395 { 0x05, 0x669a },
5b538df9 2396 { 0x1f, 0x0005 },
daf9df6d 2397 { 0x05, 0x8330 },
2398 { 0x06, 0x669a },
2399
2400 { 0x1f, 0x0002 }
2401 };
2402 int val;
2403
4da19633 2404 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2405
4da19633 2406 val = rtl_readphy(tp, 0x0d);
daf9df6d 2407 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2408 static const u32 set[] = {
daf9df6d 2409 0x0065, 0x0066, 0x0067, 0x0068,
2410 0x0069, 0x006a, 0x006b, 0x006c
2411 };
2412 int i;
2413
4da19633 2414 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2415
2416 val &= 0xff00;
2417 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2418 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2419 }
2420 } else {
350f7596 2421 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2422 { 0x1f, 0x0002 },
2423 { 0x05, 0x2642 },
5b538df9 2424 { 0x1f, 0x0005 },
daf9df6d 2425 { 0x05, 0x8330 },
2426 { 0x06, 0x2642 }
5b538df9
FR		 2427 };
2428
4da19633 2429 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2430 }
2431
bca03d5f 2432 /* Fine tune PLL performance */
4da19633 2433 rtl_writephy(tp, 0x1f, 0x0002);
2434 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2435 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2436
bca03d5f 2437 /* Switching regulator Slew rate */
4da19633 2438 rtl_writephy(tp, 0x1f, 0x0002);
2439 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2440
4da19633 2441 rtl_writephy(tp, 0x1f, 0x0005);
2442 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2443
2444 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2445
4da19633 2446 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2447}
2448
4da19633 2449static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2450{
350f7596 2451 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2452 { 0x1f, 0x0002 },
2453 { 0x10, 0x0008 },
2454 { 0x0d, 0x006c },
2455
2456 { 0x1f, 0x0000 },
2457 { 0x0d, 0xf880 },
2458
2459 { 0x1f, 0x0001 },
2460 { 0x17, 0x0cc0 },
2461
2462 { 0x1f, 0x0001 },
2463 { 0x0b, 0xa4d8 },
2464 { 0x09, 0x281c },
2465 { 0x07, 0x2883 },
2466 { 0x0a, 0x6b35 },
2467 { 0x1d, 0x3da4 },
2468 { 0x1c, 0xeffd },
2469 { 0x14, 0x7f52 },
2470 { 0x18, 0x7fc6 },
2471 { 0x08, 0x0601 },
2472 { 0x06, 0x4063 },
2473 { 0x10, 0xf074 },
2474 { 0x1f, 0x0003 },
2475 { 0x13, 0x0789 },
2476 { 0x12, 0xf4bd },
2477 { 0x1a, 0x04fd },
2478 { 0x14, 0x84b0 },
2479 { 0x1f, 0x0000 },
2480 { 0x00, 0x9200 },
2481
2482 { 0x1f, 0x0005 },
2483 { 0x01, 0x0340 },
2484 { 0x1f, 0x0001 },
2485 { 0x04, 0x4000 },
2486 { 0x03, 0x1d21 },
2487 { 0x02, 0x0c32 },
2488 { 0x01, 0x0200 },
2489 { 0x00, 0x5554 },
2490 { 0x04, 0x4800 },
2491 { 0x04, 0x4000 },
2492 { 0x04, 0xf000 },
2493 { 0x03, 0xdf01 },
2494 { 0x02, 0xdf20 },
2495 { 0x01, 0x101a },
2496 { 0x00, 0xa0ff },
2497 { 0x04, 0xf800 },
2498 { 0x04, 0xf000 },
2499 { 0x1f, 0x0000 },
2500
2501 { 0x1f, 0x0007 },
2502 { 0x1e, 0x0023 },
2503 { 0x16, 0x0000 },
2504 { 0x1f, 0x0000 }
2505 };
2506
4da19633 2507 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2508}
2509
e6de30d6 2510static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2511{
2512 static const struct phy_reg phy_reg_init[] = {
2513 { 0x1f, 0x0001 },
2514 { 0x17, 0x0cc0 },
2515
2516 { 0x1f, 0x0007 },
2517 { 0x1e, 0x002d },
2518 { 0x18, 0x0040 },
2519 { 0x1f, 0x0000 }
2520 };
2521
2522 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2523 rtl_patchphy(tp, 0x0d, 1 << 5);
2524}
2525
01dc7fec 2526static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2527{
2528 static const struct phy_reg phy_reg_init[] = {
2529 /* Enable Delay cap */
2530 { 0x1f, 0x0005 },
2531 { 0x05, 0x8b80 },
2532 { 0x06, 0xc896 },
2533 { 0x1f, 0x0000 },
2534
2535 /* Channel estimation fine tune */
2536 { 0x1f, 0x0001 },
2537 { 0x0b, 0x6c20 },
2538 { 0x07, 0x2872 },
2539 { 0x1c, 0xefff },
2540 { 0x1f, 0x0003 },
2541 { 0x14, 0x6420 },
2542 { 0x1f, 0x0000 },
2543
2544 /* Update PFM & 10M TX idle timer */
2545 { 0x1f, 0x0007 },
2546 { 0x1e, 0x002f },
2547 { 0x15, 0x1919 },
2548 { 0x1f, 0x0000 },
2549
2550 { 0x1f, 0x0007 },
2551 { 0x1e, 0x00ac },
2552 { 0x18, 0x0006 },
2553 { 0x1f, 0x0000 }
2554 };
2555
15ecd039
FR		 2556 rtl_apply_firmware(tp);
2557
01dc7fec 2558 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559
2560 /* DCO enable for 10M IDLE Power */
2561 rtl_writephy(tp, 0x1f, 0x0007);
2562 rtl_writephy(tp, 0x1e, 0x0023);
2563 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2564 rtl_writephy(tp, 0x1f, 0x0000);
2565
2566 /* For impedance matching */
2567 rtl_writephy(tp, 0x1f, 0x0002);
2568 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2569 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2570
2571 /* PHY auto speed down */
2572 rtl_writephy(tp, 0x1f, 0x0007);
2573 rtl_writephy(tp, 0x1e, 0x002d);
2574 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2575 rtl_writephy(tp, 0x1f, 0x0000);
2576 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2577
2578 rtl_writephy(tp, 0x1f, 0x0005);
2579 rtl_writephy(tp, 0x05, 0x8b86);
2580 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2581 rtl_writephy(tp, 0x1f, 0x0000);
2582
2583 rtl_writephy(tp, 0x1f, 0x0005);
2584 rtl_writephy(tp, 0x05, 0x8b85);
2585 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2586 rtl_writephy(tp, 0x1f, 0x0007);
2587 rtl_writephy(tp, 0x1e, 0x0020);
2588 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2589 rtl_writephy(tp, 0x1f, 0x0006);
2590 rtl_writephy(tp, 0x00, 0x5a00);
2591 rtl_writephy(tp, 0x1f, 0x0000);
2592 rtl_writephy(tp, 0x0d, 0x0007);
2593 rtl_writephy(tp, 0x0e, 0x003c);
2594 rtl_writephy(tp, 0x0d, 0x4007);
2595 rtl_writephy(tp, 0x0e, 0x0000);
2596 rtl_writephy(tp, 0x0d, 0x0000);
2597}
2598
4da19633 2599static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2600{
350f7596 2601 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2602 { 0x1f, 0x0003 },
2603 { 0x08, 0x441d },
2604 { 0x01, 0x9100 },
2605 { 0x1f, 0x0000 }
2606 };
2607
4da19633 2608 rtl_writephy(tp, 0x1f, 0x0000);
2609 rtl_patchphy(tp, 0x11, 1 << 12);
2610 rtl_patchphy(tp, 0x19, 1 << 13);
2611 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2612
4da19633 2613 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2614}
2615
5a5e4443
HW		 2616static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2617{
2618 static const struct phy_reg phy_reg_init[] = {
2619 { 0x1f, 0x0005 },
2620 { 0x1a, 0x0000 },
2621 { 0x1f, 0x0000 },
2622
2623 { 0x1f, 0x0004 },
2624 { 0x1c, 0x0000 },
2625 { 0x1f, 0x0000 },
2626
2627 { 0x1f, 0x0001 },
2628 { 0x15, 0x7701 },
2629 { 0x1f, 0x0000 }
2630 };
2631
2632 /* Disable ALDPS before ram code */
2633 rtl_writephy(tp, 0x1f, 0x0000);
2634 rtl_writephy(tp, 0x18, 0x0310);
2635 msleep(100);
2636
953a12cc 2637 rtl_apply_firmware(tp);
5a5e4443
HW		 2638
2639 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2640}
2641
5615d9f1
FR		 2642static void rtl_hw_phy_config(struct net_device *dev)
2643{
2644 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2645
2646 rtl8169_print_mac_version(tp);
2647
2648 switch (tp->mac_version) {
2649 case RTL_GIGA_MAC_VER_01:
2650 break;
2651 case RTL_GIGA_MAC_VER_02:
2652 case RTL_GIGA_MAC_VER_03:
4da19633 2653 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2654 break;
2655 case RTL_GIGA_MAC_VER_04:
4da19633 2656 rtl8169sb_hw_phy_config(tp);
5615d9f1 2657 break;
2e955856 2658 case RTL_GIGA_MAC_VER_05:
4da19633 2659 rtl8169scd_hw_phy_config(tp);
2e955856 2660 break;
8c7006aa 2661 case RTL_GIGA_MAC_VER_06:
4da19633 2662 rtl8169sce_hw_phy_config(tp);
8c7006aa 2663 break;
2857ffb7
FR		 2664 case RTL_GIGA_MAC_VER_07:
2665 case RTL_GIGA_MAC_VER_08:
2666 case RTL_GIGA_MAC_VER_09:
4da19633 2667 rtl8102e_hw_phy_config(tp);
2857ffb7 2668 break;
236b8082 2669 case RTL_GIGA_MAC_VER_11:
4da19633 2670 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2671 break;
2672 case RTL_GIGA_MAC_VER_12:
4da19633 2673 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2674 break;
2675 case RTL_GIGA_MAC_VER_17:
4da19633 2676 rtl8168bef_hw_phy_config(tp);
236b8082 2677 break;
867763c1 2678 case RTL_GIGA_MAC_VER_18:
4da19633 2679 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2680 break;
2681 case RTL_GIGA_MAC_VER_19:
4da19633 2682 rtl8168c_1_hw_phy_config(tp);
867763c1 2683 break;
7da97ec9 2684 case RTL_GIGA_MAC_VER_20:
4da19633 2685 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2686 break;
197ff761 2687 case RTL_GIGA_MAC_VER_21:
4da19633 2688 rtl8168c_3_hw_phy_config(tp);
197ff761 2689 break;
6fb07058 2690 case RTL_GIGA_MAC_VER_22:
4da19633 2691 rtl8168c_4_hw_phy_config(tp);
6fb07058 2692 break;
ef3386f0 2693 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2694 case RTL_GIGA_MAC_VER_24:
4da19633 2695 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2696 break;
5b538df9 2697 case RTL_GIGA_MAC_VER_25:
bca03d5f 2698 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2699 break;
2700 case RTL_GIGA_MAC_VER_26:
bca03d5f 2701 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2702 break;
2703 case RTL_GIGA_MAC_VER_27:
4da19633 2704 rtl8168d_3_hw_phy_config(tp);
5b538df9 2705 break;
e6de30d6 2706 case RTL_GIGA_MAC_VER_28:
2707 rtl8168d_4_hw_phy_config(tp);
2708 break;
5a5e4443
HW		 2709 case RTL_GIGA_MAC_VER_29:
2710 case RTL_GIGA_MAC_VER_30:
2711 rtl8105e_hw_phy_config(tp);
2712 break;
cecb5fd7
FR		 2713 case RTL_GIGA_MAC_VER_31:
2714 /* None. */
2715 break;
01dc7fec 2716 case RTL_GIGA_MAC_VER_32:
01dc7fec 2717 case RTL_GIGA_MAC_VER_33:
15ecd039 2718 rtl8168e_hw_phy_config(tp);
01dc7fec 2719 break;
ef3386f0 2720
5615d9f1
FR		 2721 default:
2722 break;
2723 }
2724}
2725
1da177e4
LT		 2726static void rtl8169_phy_timer(unsigned long __opaque)
2727{
2728 struct net_device *dev = (struct net_device *)__opaque;
2729 struct rtl8169_private *tp = netdev_priv(dev);
2730 struct timer_list *timer = &tp->timer;
2731 void __iomem *ioaddr = tp->mmio_addr;
2732 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2733
bcf0bf90 2734 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2735
1da177e4
LT		 2736 spin_lock_irq(&tp->lock);
2737
4da19633 2738 if (tp->phy_reset_pending(tp)) {
5b0384f4 2739 /*
1da177e4
LT		 2740 * A busy loop could burn quite a few cycles on nowadays CPU.
2741 * Let's delay the execution of the timer for a few ticks.
2742 */
2743 timeout = HZ/10;
2744 goto out_mod_timer;
2745 }
2746
2747 if (tp->link_ok(ioaddr))
2748 goto out_unlock;
2749
bf82c189 2750 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2751
4da19633 2752 tp->phy_reset_enable(tp);
1da177e4
LT		 2753
2754out_mod_timer:
2755 mod_timer(timer, jiffies + timeout);
2756out_unlock:
2757 spin_unlock_irq(&tp->lock);
2758}
2759
1da177e4
LT		 2760#ifdef CONFIG_NET_POLL_CONTROLLER
2761/*
2762 * Polling 'interrupt' - used by things like netconsole to send skbs
2763 * without having to re-enable interrupts. It's not called while
2764 * the interrupt routine is executing.
2765 */
2766static void rtl8169_netpoll(struct net_device *dev)
2767{
2768 struct rtl8169_private *tp = netdev_priv(dev);
2769 struct pci_dev *pdev = tp->pci_dev;
2770
2771 disable_irq(pdev->irq);
7d12e780 2772 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2773 enable_irq(pdev->irq);
2774}
2775#endif
2776
2777static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2778 void __iomem *ioaddr)
2779{
2780 iounmap(ioaddr);
2781 pci_release_regions(pdev);
87aeec76 2782 pci_clear_mwi(pdev);
1da177e4
LT		 2783 pci_disable_device(pdev);
2784 free_netdev(dev);
2785}
2786
bf793295
FR		 2787static void rtl8169_phy_reset(struct net_device *dev,
2788 struct rtl8169_private *tp)
2789{
07d3f51f 2790 unsigned int i;
bf793295 2791
4da19633 2792 tp->phy_reset_enable(tp);
bf793295 2793 for (i = 0; i < 100; i++) {
4da19633 2794 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2795 return;
2796 msleep(1);
2797 }
bf82c189 2798 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2799}
2800
4ff96fa6
FR		 2801static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2802{
2803 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2804
5615d9f1 2805 rtl_hw_phy_config(dev);
4ff96fa6 2806
77332894
MS		 2807 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2808 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2809 RTL_W8(0x82, 0x01);
2810 }
4ff96fa6 2811
6dccd16b
FR		 2812 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2813
2814 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2815 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2816
bcf0bf90 2817 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2818 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2819 RTL_W8(0x82, 0x01);
2820 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2821 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2822 }
2823
bf793295
FR		 2824 rtl8169_phy_reset(dev, tp);
2825
54405cde 2826 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 2827 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2828 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2829 (tp->mii.supports_gmii ?
2830 ADVERTISED_1000baseT_Half |
2831 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2832
bf82c189
JP		 2833 if (RTL_R8(PHYstatus) & TBI_Enable)
2834 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2835}
2836
773d2021
FR		 2837static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2838{
2839 void __iomem *ioaddr = tp->mmio_addr;
2840 u32 high;
2841 u32 low;
2842
2843 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2844 high = addr[4] | (addr[5] << 8);
2845
2846 spin_lock_irq(&tp->lock);
2847
2848 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2849
773d2021 2850 RTL_W32(MAC4, high);
908ba2bf 2851 RTL_R32(MAC4);
2852
78f1cd02 2853 RTL_W32(MAC0, low);
908ba2bf 2854 RTL_R32(MAC0);
2855
773d2021
FR		 2856 RTL_W8(Cfg9346, Cfg9346_Lock);
2857
2858 spin_unlock_irq(&tp->lock);
2859}
2860
2861static int rtl_set_mac_address(struct net_device *dev, void *p)
2862{
2863 struct rtl8169_private *tp = netdev_priv(dev);
2864 struct sockaddr *addr = p;
2865
2866 if (!is_valid_ether_addr(addr->sa_data))
2867 return -EADDRNOTAVAIL;
2868
2869 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2870
2871 rtl_rar_set(tp, dev->dev_addr);
2872
2873 return 0;
2874}
2875
5f787a1a
FR		 2876static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2877{
2878 struct rtl8169_private *tp = netdev_priv(dev);
2879 struct mii_ioctl_data *data = if_mii(ifr);
2880
8b4ab28d
FR		 2881 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2882}
5f787a1a 2883
cecb5fd7
FR		 2884static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2885 struct mii_ioctl_data *data, int cmd)
8b4ab28d 2886{
5f787a1a
FR		 2887 switch (cmd) {
2888 case SIOCGMIIPHY:
2889 data->phy_id = 32; /* Internal PHY */
2890 return 0;
2891
2892 case SIOCGMIIREG:
4da19633 2893 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2894 return 0;
2895
2896 case SIOCSMIIREG:
4da19633 2897 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2898 return 0;
2899 }
2900 return -EOPNOTSUPP;
2901}
2902
8b4ab28d
FR		 2903static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2904{
2905 return -EOPNOTSUPP;
2906}
2907
0e485150
FR		 2908static const struct rtl_cfg_info {
2909 void (*hw_start)(struct net_device *);
2910 unsigned int region;
2911 unsigned int align;
2912 u16 intr_event;
2913 u16 napi_event;
ccdffb9a 2914 unsigned features;
f21b75e9 2915 u8 default_ver;
0e485150
FR		 2916} rtl_cfg_infos [] = {
2917 [RTL_CFG_0] = {
2918 .hw_start = rtl_hw_start_8169,
2919 .region = 1,
e9f63f30 2920 .align = 0,
0e485150
FR		 2921 .intr_event = SYSErr | LinkChg | RxOverflow |
2922 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2923 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2924 .features = RTL_FEATURE_GMII,
2925 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2926 },
2927 [RTL_CFG_1] = {
2928 .hw_start = rtl_hw_start_8168,
2929 .region = 2,
2930 .align = 8,
53f57357 2931 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2932 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2933 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2934 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2935 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2936 },
2937 [RTL_CFG_2] = {
2938 .hw_start = rtl_hw_start_8101,
2939 .region = 2,
2940 .align = 8,
2941 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2942 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2943 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2944 .features = RTL_FEATURE_MSI,
2945 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2946 }
2947};
2948
fbac58fc
FR		 2949/* Cfg9346_Unlock assumed. */
2950static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2951 const struct rtl_cfg_info *cfg)
2952{
2953 unsigned msi = 0;
2954 u8 cfg2;
2955
2956 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2957 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2958 if (pci_enable_msi(pdev)) {
2959 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2960 } else {
2961 cfg2 |= MSIEnable;
2962 msi = RTL_FEATURE_MSI;
2963 }
2964 }
2965 RTL_W8(Config2, cfg2);
2966 return msi;
2967}
2968
2969static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2970{
2971 if (tp->features & RTL_FEATURE_MSI) {
2972 pci_disable_msi(pdev);
2973 tp->features &= ~RTL_FEATURE_MSI;
2974 }
2975}
2976
8b4ab28d
FR		 2977static const struct net_device_ops rtl8169_netdev_ops = {
2978 .ndo_open = rtl8169_open,
2979 .ndo_stop = rtl8169_close,
2980 .ndo_get_stats = rtl8169_get_stats,
00829823 2981 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2982 .ndo_tx_timeout = rtl8169_tx_timeout,
2983 .ndo_validate_addr = eth_validate_addr,
2984 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2985 .ndo_fix_features = rtl8169_fix_features,
2986 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2987 .ndo_set_mac_address = rtl_set_mac_address,
2988 .ndo_do_ioctl = rtl8169_ioctl,
2989 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2990#ifdef CONFIG_NET_POLL_CONTROLLER
2991 .ndo_poll_controller = rtl8169_netpoll,
2992#endif
2993
2994};
2995
c0e45c1c 2996static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2997{
2998 struct mdio_ops *ops = &tp->mdio_ops;
2999
3000 switch (tp->mac_version) {
3001 case RTL_GIGA_MAC_VER_27:
3002 ops->write = r8168dp_1_mdio_write;
3003 ops->read = r8168dp_1_mdio_read;
3004 break;
e6de30d6 3005 case RTL_GIGA_MAC_VER_28:
4804b3b3 3006 case RTL_GIGA_MAC_VER_31:
e6de30d6 3007 ops->write = r8168dp_2_mdio_write;
3008 ops->read = r8168dp_2_mdio_read;
3009 break;
c0e45c1c 3010 default:
3011 ops->write = r8169_mdio_write;
3012 ops->read = r8169_mdio_read;
3013 break;
3014 }
3015}
3016
065c27c1 3017static void r810x_phy_power_down(struct rtl8169_private *tp)
3018{
3019 rtl_writephy(tp, 0x1f, 0x0000);
3020 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3021}
3022
3023static void r810x_phy_power_up(struct rtl8169_private *tp)
3024{
3025 rtl_writephy(tp, 0x1f, 0x0000);
3026 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3027}
3028
3029static void r810x_pll_power_down(struct rtl8169_private *tp)
3030{
3031 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3032 rtl_writephy(tp, 0x1f, 0x0000);
3033 rtl_writephy(tp, MII_BMCR, 0x0000);
3034 return;
3035 }
3036
3037 r810x_phy_power_down(tp);
3038}
3039
3040static void r810x_pll_power_up(struct rtl8169_private *tp)
3041{
3042 r810x_phy_power_up(tp);
3043}
3044
3045static void r8168_phy_power_up(struct rtl8169_private *tp)
3046{
3047 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3048 switch (tp->mac_version) {
3049 case RTL_GIGA_MAC_VER_11:
3050 case RTL_GIGA_MAC_VER_12:
3051 case RTL_GIGA_MAC_VER_17:
3052 case RTL_GIGA_MAC_VER_18:
3053 case RTL_GIGA_MAC_VER_19:
3054 case RTL_GIGA_MAC_VER_20:
3055 case RTL_GIGA_MAC_VER_21:
3056 case RTL_GIGA_MAC_VER_22:
3057 case RTL_GIGA_MAC_VER_23:
3058 case RTL_GIGA_MAC_VER_24:
3059 case RTL_GIGA_MAC_VER_25:
3060 case RTL_GIGA_MAC_VER_26:
3061 case RTL_GIGA_MAC_VER_27:
3062 case RTL_GIGA_MAC_VER_28:
3063 case RTL_GIGA_MAC_VER_31:
3064 rtl_writephy(tp, 0x0e, 0x0000);
3065 break;
3066 default:
3067 break;
3068 }
065c27c1 3069 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3070}
3071
3072static void r8168_phy_power_down(struct rtl8169_private *tp)
3073{
3074 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3075 switch (tp->mac_version) {
3076 case RTL_GIGA_MAC_VER_32:
3077 case RTL_GIGA_MAC_VER_33:
3078 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3079 break;
3080
3081 case RTL_GIGA_MAC_VER_11:
3082 case RTL_GIGA_MAC_VER_12:
3083 case RTL_GIGA_MAC_VER_17:
3084 case RTL_GIGA_MAC_VER_18:
3085 case RTL_GIGA_MAC_VER_19:
3086 case RTL_GIGA_MAC_VER_20:
3087 case RTL_GIGA_MAC_VER_21:
3088 case RTL_GIGA_MAC_VER_22:
3089 case RTL_GIGA_MAC_VER_23:
3090 case RTL_GIGA_MAC_VER_24:
3091 case RTL_GIGA_MAC_VER_25:
3092 case RTL_GIGA_MAC_VER_26:
3093 case RTL_GIGA_MAC_VER_27:
3094 case RTL_GIGA_MAC_VER_28:
3095 case RTL_GIGA_MAC_VER_31:
3096 rtl_writephy(tp, 0x0e, 0x0200);
3097 default:
3098 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3099 break;
3100 }
065c27c1 3101}
3102
3103static void r8168_pll_power_down(struct rtl8169_private *tp)
3104{
3105 void __iomem *ioaddr = tp->mmio_addr;
3106
cecb5fd7
FR		 3107 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3108 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3109 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3110 r8168dp_check_dash(tp)) {
065c27c1 3111 return;
5d2e1957 3112 }
065c27c1 3113
cecb5fd7
FR		 3114 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3115 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3116 (RTL_R16(CPlusCmd) & ASF)) {
3117 return;
3118 }
3119
01dc7fec 3120 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3121 tp->mac_version == RTL_GIGA_MAC_VER_33)
3122 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3123
065c27c1 3124 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3125 rtl_writephy(tp, 0x1f, 0x0000);
3126 rtl_writephy(tp, MII_BMCR, 0x0000);
3127
3128 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3129 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3130 return;
3131 }
3132
3133 r8168_phy_power_down(tp);
3134
3135 switch (tp->mac_version) {
3136 case RTL_GIGA_MAC_VER_25:
3137 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3138 case RTL_GIGA_MAC_VER_27:
3139 case RTL_GIGA_MAC_VER_28:
4804b3b3 3140 case RTL_GIGA_MAC_VER_31:
01dc7fec 3141 case RTL_GIGA_MAC_VER_32:
3142 case RTL_GIGA_MAC_VER_33:
065c27c1 3143 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3144 break;
3145 }
3146}
3147
3148static void r8168_pll_power_up(struct rtl8169_private *tp)
3149{
3150 void __iomem *ioaddr = tp->mmio_addr;
3151
cecb5fd7
FR		 3152 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3153 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3154 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3155 r8168dp_check_dash(tp)) {
065c27c1 3156 return;
5d2e1957 3157 }
065c27c1 3158
3159 switch (tp->mac_version) {
3160 case RTL_GIGA_MAC_VER_25:
3161 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3162 case RTL_GIGA_MAC_VER_27:
3163 case RTL_GIGA_MAC_VER_28:
4804b3b3 3164 case RTL_GIGA_MAC_VER_31:
01dc7fec 3165 case RTL_GIGA_MAC_VER_32:
3166 case RTL_GIGA_MAC_VER_33:
065c27c1 3167 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3168 break;
3169 }
3170
3171 r8168_phy_power_up(tp);
3172}
3173
3174static void rtl_pll_power_op(struct rtl8169_private *tp,
3175 void (*op)(struct rtl8169_private *))
3176{
3177 if (op)
3178 op(tp);
3179}
3180
3181static void rtl_pll_power_down(struct rtl8169_private *tp)
3182{
3183 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3184}
3185
3186static void rtl_pll_power_up(struct rtl8169_private *tp)
3187{
3188 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3189}
3190
3191static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3192{
3193 struct pll_power_ops *ops = &tp->pll_power_ops;
3194
3195 switch (tp->mac_version) {
3196 case RTL_GIGA_MAC_VER_07:
3197 case RTL_GIGA_MAC_VER_08:
3198 case RTL_GIGA_MAC_VER_09:
3199 case RTL_GIGA_MAC_VER_10:
3200 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3201 case RTL_GIGA_MAC_VER_29:
3202 case RTL_GIGA_MAC_VER_30:
065c27c1 3203 ops->down = r810x_pll_power_down;
3204 ops->up = r810x_pll_power_up;
3205 break;
3206
3207 case RTL_GIGA_MAC_VER_11:
3208 case RTL_GIGA_MAC_VER_12:
3209 case RTL_GIGA_MAC_VER_17:
3210 case RTL_GIGA_MAC_VER_18:
3211 case RTL_GIGA_MAC_VER_19:
3212 case RTL_GIGA_MAC_VER_20:
3213 case RTL_GIGA_MAC_VER_21:
3214 case RTL_GIGA_MAC_VER_22:
3215 case RTL_GIGA_MAC_VER_23:
3216 case RTL_GIGA_MAC_VER_24:
3217 case RTL_GIGA_MAC_VER_25:
3218 case RTL_GIGA_MAC_VER_26:
3219 case RTL_GIGA_MAC_VER_27:
e6de30d6 3220 case RTL_GIGA_MAC_VER_28:
4804b3b3 3221 case RTL_GIGA_MAC_VER_31:
01dc7fec 3222 case RTL_GIGA_MAC_VER_32:
3223 case RTL_GIGA_MAC_VER_33:
065c27c1 3224 ops->down = r8168_pll_power_down;
3225 ops->up = r8168_pll_power_up;
3226 break;
3227
3228 default:
3229 ops->down = NULL;
3230 ops->up = NULL;
3231 break;
3232 }
3233}
3234
6f43adc8
FR		 3235static void rtl_hw_reset(struct rtl8169_private *tp)
3236{
3237 void __iomem *ioaddr = tp->mmio_addr;
3238 int i;
3239
3240 /* Soft reset the chip. */
3241 RTL_W8(ChipCmd, CmdReset);
3242
3243 /* Check that the chip has finished the reset. */
3244 for (i = 0; i < 100; i++) {
3245 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3246 break;
3247 msleep_interruptible(1);
3248 }
3249}
3250
1da177e4 3251static int __devinit
4ff96fa6 3252rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3253{
0e485150
FR		 3254 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3255 const unsigned int region = cfg->region;
1da177e4 3256 struct rtl8169_private *tp;
ccdffb9a 3257 struct mii_if_info *mii;
4ff96fa6
FR		 3258 struct net_device *dev;
3259 void __iomem *ioaddr;
2b7b4318 3260 int chipset, i;
07d3f51f 3261 int rc;
1da177e4 3262
4ff96fa6
FR		 3263 if (netif_msg_drv(&debug)) {
3264 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3265 MODULENAME, RTL8169_VERSION);
3266 }
1da177e4 3267
1da177e4 3268 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3269 if (!dev) {
b57b7e5a 3270 if (netif_msg_drv(&debug))
9b91cf9d 3271 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3272 rc = -ENOMEM;
3273 goto out;
1da177e4
LT		 3274 }
3275
1da177e4 3276 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3277 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3278 tp = netdev_priv(dev);
c4028958 3279 tp->dev = dev;
21e197f2 3280 tp->pci_dev = pdev;
b57b7e5a 3281 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3282
ccdffb9a
FR		 3283 mii = &tp->mii;
3284 mii->dev = dev;
3285 mii->mdio_read = rtl_mdio_read;
3286 mii->mdio_write = rtl_mdio_write;
3287 mii->phy_id_mask = 0x1f;
3288 mii->reg_num_mask = 0x1f;
3289 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3290
ba04c7c9
SG		 3291 /* disable ASPM completely as that cause random device stop working
3292 * problems as well as full system hangs for some PCIe devices users */
3293 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3294 PCIE_LINK_STATE_CLKPM);
3295
1da177e4
LT		 3296 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3297 rc = pci_enable_device(pdev);
b57b7e5a 3298 if (rc < 0) {
bf82c189 3299 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3300 goto err_out_free_dev_1;
1da177e4
LT		 3301 }
3302
87aeec76 3303 if (pci_set_mwi(pdev) < 0)
3304 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3305
1da177e4 3306 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3307 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3308 netif_err(tp, probe, dev,
3309 "region #%d not an MMIO resource, aborting\n",
3310 region);
1da177e4 3311 rc = -ENODEV;
87aeec76 3312 goto err_out_mwi_2;
1da177e4 3313 }
4ff96fa6 3314
1da177e4 3315 /* check for weird/broken PCI region reporting */
bcf0bf90 3316 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3317 netif_err(tp, probe, dev,
3318 "Invalid PCI region size(s), aborting\n");
1da177e4 3319 rc = -ENODEV;
87aeec76 3320 goto err_out_mwi_2;
1da177e4
LT		 3321 }
3322
3323 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3324 if (rc < 0) {
bf82c189 3325 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3326 goto err_out_mwi_2;
1da177e4
LT		 3327 }
3328
d24e9aaf 3329 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3330
3331 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3332 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3333 tp->cp_cmd |= PCIDAC;
3334 dev->features |= NETIF_F_HIGHDMA;
3335 } else {
284901a9 3336 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3337 if (rc < 0) {
bf82c189 3338 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3339 goto err_out_free_res_3;
1da177e4
LT		 3340 }
3341 }
3342
1da177e4 3343 /* ioremap MMIO region */
bcf0bf90 3344 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3345 if (!ioaddr) {
bf82c189 3346 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3347 rc = -EIO;
87aeec76 3348 goto err_out_free_res_3;
1da177e4 3349 }
6f43adc8 3350 tp->mmio_addr = ioaddr;
1da177e4 3351
4300e8c7
DM		 3352 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3353 if (!tp->pcie_cap)
3354 netif_info(tp, probe, dev, "no PCI Express capability\n");
3355
d78ad8cb 3356 RTL_W16(IntrMask, 0x0000);
1da177e4 3357
6f43adc8 3358 rtl_hw_reset(tp);
1da177e4 3359
d78ad8cb
KW		 3360 RTL_W16(IntrStatus, 0xffff);
3361
ca52efd5 3362 pci_set_master(pdev);
3363
1da177e4 3364 /* Identify chip attached to board */
5d320a20 3365 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
1da177e4 3366
7a8fc77b
FR		 3367 /*
3368 * Pretend we are using VLANs; This bypasses a nasty bug where
3369 * Interrupts stop flowing on high load on 8110SCd controllers.
3370 */
3371 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3372 tp->cp_cmd |= RxVlan;
3373
c0e45c1c 3374 rtl_init_mdio_ops(tp);
065c27c1 3375 rtl_init_pll_power_ops(tp);
c0e45c1c 3376
1da177e4 3377 rtl8169_print_mac_version(tp);
1da177e4 3378
85bffe6c
FR		 3379 chipset = tp->mac_version;
3380 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3381
5d06a99f
FR		 3382 RTL_W8(Cfg9346, Cfg9346_Unlock);
3383 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3384 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3385 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3386 tp->features |= RTL_FEATURE_WOL;
3387 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3388 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3389 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3390 RTL_W8(Cfg9346, Cfg9346_Lock);
3391
66ec5d4f
FR		 3392 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3393 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3394 tp->set_speed = rtl8169_set_speed_tbi;
3395 tp->get_settings = rtl8169_gset_tbi;
3396 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3397 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3398 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3399 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3400 } else {
3401 tp->set_speed = rtl8169_set_speed_xmii;
3402 tp->get_settings = rtl8169_gset_xmii;
3403 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3404 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3405 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3406 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3407 }
3408
df58ef51
FR		 3409 spin_lock_init(&tp->lock);
3410
7bf6bf48 3411 /* Get MAC address */
1da177e4
LT		 3412 for (i = 0; i < MAC_ADDR_LEN; i++)
3413 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3414 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3415
1da177e4 3416 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3417 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3418 dev->irq = pdev->irq;
3419 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3420
bea3348e 3421 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3422
350fb32a
MM		 3423 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3424 * properly for all devices */
3425 dev->features |= NETIF_F_RXCSUM |
3426 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3427
3428 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3429 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3430 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3431 NETIF_F_HIGHDMA;
3432
3433 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3434 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3435 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3436
3437 tp->intr_mask = 0xffff;
0e485150
FR		 3438 tp->hw_start = cfg->hw_start;
3439 tp->intr_event = cfg->intr_event;
3440 tp->napi_event = cfg->napi_event;
1da177e4 3441
2efa53f3
FR		 3442 init_timer(&tp->timer);
3443 tp->timer.data = (unsigned long) dev;
3444 tp->timer.function = rtl8169_phy_timer;
3445
953a12cc
FR		 3446 tp->fw = RTL_FIRMWARE_UNKNOWN;
3447
1da177e4 3448 rc = register_netdev(dev);
4ff96fa6 3449 if (rc < 0)
87aeec76 3450 goto err_out_msi_4;
1da177e4
LT		 3451
3452 pci_set_drvdata(pdev, dev);
3453
bf82c189 3454 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3455 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3456 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3457
cecb5fd7
FR		 3458 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3459 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3460 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3461 rtl8168_driver_start(tp);
e6de30d6 3462 }
b646d900 3463
8b76ab39 3464 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3465
f3ec4f87
AS		 3466 if (pci_dev_run_wake(pdev))
3467 pm_runtime_put_noidle(&pdev->dev);
e1759441 3468
0d672e9f
IV		 3469 netif_carrier_off(dev);
3470
4ff96fa6
FR		 3471out:
3472 return rc;
1da177e4 3473
87aeec76 3474err_out_msi_4:
fbac58fc 3475 rtl_disable_msi(pdev, tp);
4ff96fa6 3476 iounmap(ioaddr);
87aeec76 3477err_out_free_res_3:
4ff96fa6 3478 pci_release_regions(pdev);
87aeec76 3479err_out_mwi_2:
4ff96fa6 3480 pci_clear_mwi(pdev);
4ff96fa6
FR		 3481 pci_disable_device(pdev);
3482err_out_free_dev_1:
3483 free_netdev(dev);
3484 goto out;
1da177e4
LT		 3485}
3486
07d3f51f 3487static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3488{
3489 struct net_device *dev = pci_get_drvdata(pdev);
3490 struct rtl8169_private *tp = netdev_priv(dev);
3491
cecb5fd7
FR		 3492 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3493 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3494 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3495 rtl8168_driver_stop(tp);
e6de30d6 3496 }
b646d900 3497
23f333a2 3498 cancel_delayed_work_sync(&tp->task);
eb2a021c 3499
1da177e4 3500 unregister_netdev(dev);
cc098dc7 3501
953a12cc
FR		 3502 rtl_release_firmware(tp);
3503
f3ec4f87
AS		 3504 if (pci_dev_run_wake(pdev))
3505 pm_runtime_get_noresume(&pdev->dev);
e1759441 3506
cc098dc7
IV		 3507 /* restore original MAC address */
3508 rtl_rar_set(tp, dev->perm_addr);
3509
fbac58fc 3510 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3511 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3512 pci_set_drvdata(pdev, NULL);
3513}
3514
953a12cc
FR		 3515static void rtl_request_firmware(struct rtl8169_private *tp)
3516{
953a12cc 3517 /* Return early if the firmware is already loaded / cached. */
31bd204f
FR		 3518 if (IS_ERR(tp->fw)) {
3519 const char *name;
953a12cc 3520
31bd204f
FR		 3521 name = rtl_lookup_firmware_name(tp);
3522 if (name) {
953a12cc
FR		 3523 int rc;
3524
3525 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
31bd204f
FR		 3526 if (rc >= 0)
3527 return;
3528
3529 netif_warn(tp, ifup, tp->dev, "unable to load "
3530 "firmware patch %s (%d)\n", name, rc);
953a12cc 3531 }
31bd204f 3532 tp->fw = NULL;
953a12cc 3533 }
953a12cc
FR		 3534}
3535
1da177e4
LT		 3536static int rtl8169_open(struct net_device *dev)
3537{
3538 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3539 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3540 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3541 int retval = -ENOMEM;
1da177e4 3542
e1759441 3543 pm_runtime_get_sync(&pdev->dev);
1da177e4 3544
1da177e4
LT		 3545 /*
3546 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3547 * dma_alloc_coherent provides more.
1da177e4 3548 */
82553bb6
SG		 3549 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3550 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3551 if (!tp->TxDescArray)
e1759441 3552 goto err_pm_runtime_put;
1da177e4 3553
82553bb6
SG		 3554 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3555 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3556 if (!tp->RxDescArray)
99f252b0 3557 goto err_free_tx_0;
1da177e4
LT		 3558
3559 retval = rtl8169_init_ring(dev);
3560 if (retval < 0)
99f252b0 3561 goto err_free_rx_1;
1da177e4 3562
c4028958 3563 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3564
99f252b0
FR		 3565 smp_mb();
3566
953a12cc
FR		 3567 rtl_request_firmware(tp);
3568
fbac58fc
FR		 3569 retval = request_irq(dev->irq, rtl8169_interrupt,
3570 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3571 dev->name, dev);
3572 if (retval < 0)
953a12cc 3573 goto err_release_fw_2;
99f252b0 3574
bea3348e 3575 napi_enable(&tp->napi);
bea3348e 3576
eee3a96c 3577 rtl8169_init_phy(dev, tp);
3578
350fb32a 3579 rtl8169_set_features(dev, dev->features);
eee3a96c 3580
065c27c1 3581 rtl_pll_power_up(tp);
3582
07ce4064 3583 rtl_hw_start(dev);
1da177e4 3584
e1759441
RW		 3585 tp->saved_wolopts = 0;
3586 pm_runtime_put_noidle(&pdev->dev);
3587
eee3a96c 3588 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3589out:
3590 return retval;
3591
953a12cc
FR		 3592err_release_fw_2:
3593 rtl_release_firmware(tp);
99f252b0
FR		 3594 rtl8169_rx_clear(tp);
3595err_free_rx_1:
82553bb6
SG		 3596 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3597 tp->RxPhyAddr);
e1759441 3598 tp->RxDescArray = NULL;
99f252b0 3599err_free_tx_0:
82553bb6
SG		 3600 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3601 tp->TxPhyAddr);
e1759441
RW		 3602 tp->TxDescArray = NULL;
3603err_pm_runtime_put:
3604 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3605 goto out;
3606}
3607
e6de30d6 3608static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3609{
e6de30d6 3610 void __iomem *ioaddr = tp->mmio_addr;
3611
1da177e4
LT		 3612 /* Disable interrupts */
3613 rtl8169_irq_mask_and_ack(ioaddr);
3614
5d2e1957 3615 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3616 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3617 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3618 while (RTL_R8(TxPoll) & NPQ)
3619 udelay(20);
3620
3621 }
3622
1da177e4
LT		 3623 /* Reset the chipset */
3624 RTL_W8(ChipCmd, CmdReset);
3625
3626 /* PCI commit */
3627 RTL_R8(ChipCmd);
3628}
3629
7f796d83 3630static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3631{
3632 void __iomem *ioaddr = tp->mmio_addr;
3633 u32 cfg = rtl8169_rx_config;
3634
2b7b4318 3635 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3636 RTL_W32(RxConfig, cfg);
3637
3638 /* Set DMA burst size and Interframe Gap Time */
3639 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3640 (InterFrameGap << TxInterFrameGapShift));
3641}
3642
07ce4064 3643static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3644{
3645 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3646
6f43adc8 3647 rtl_hw_reset(tp);
1da177e4 3648
07ce4064
FR		 3649 tp->hw_start(dev);
3650
07ce4064
FR		 3651 netif_start_queue(dev);
3652}
3653
7f796d83
FR		 3654static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3655 void __iomem *ioaddr)
3656{
3657 /*
3658 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3659 * register to be written before TxDescAddrLow to work.
3660 * Switching from MMIO to I/O access fixes the issue as well.
3661 */
3662 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3663 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3664 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3665 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3666}
3667
3668static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3669{
3670 u16 cmd;
3671
3672 cmd = RTL_R16(CPlusCmd);
3673 RTL_W16(CPlusCmd, cmd);
3674 return cmd;
3675}
3676
fdd7b4c3 3677static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3678{
3679 /* Low hurts. Let's disable the filtering. */
207d6e87 3680 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3681}
3682
6dccd16b
FR		 3683static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3684{
3744100e 3685 static const struct rtl_cfg2_info {
6dccd16b
FR		 3686 u32 mac_version;
3687 u32 clk;
3688 u32 val;
3689 } cfg2_info [] = {
3690 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3691 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3692 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3693 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 3694 };
3695 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 3696 unsigned int i;
3697 u32 clk;
3698
3699 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3700 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3701 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3702 RTL_W32(0x7c, p->val);
3703 break;
3704 }
3705 }
3706}
3707
07ce4064
FR		 3708static void rtl_hw_start_8169(struct net_device *dev)
3709{
3710 struct rtl8169_private *tp = netdev_priv(dev);
3711 void __iomem *ioaddr = tp->mmio_addr;
3712 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3713
9cb427b6
FR		 3714 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3715 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3716 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3717 }
3718
1da177e4 3719 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 3720 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3721 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3722 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3723 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 3724 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3725
f0298f81 3726 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3727
6f0333b8 3728 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3729
cecb5fd7
FR		 3730 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3731 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3732 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3733 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 3734 rtl_set_rx_tx_config_registers(tp);
1da177e4 3735
7f796d83 3736 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3737
cecb5fd7
FR		 3738 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3739 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 3740 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3741 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3742 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3743 }
3744
bcf0bf90
FR		 3745 RTL_W16(CPlusCmd, tp->cp_cmd);
3746
6dccd16b
FR		 3747 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3748
1da177e4
LT		 3749 /*
3750 * Undocumented corner. Supposedly:
3751 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3752 */
3753 RTL_W16(IntrMitigate, 0x0000);
3754
7f796d83 3755 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3756
cecb5fd7
FR		 3757 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3758 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3759 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3760 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 3761 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3762 rtl_set_rx_tx_config_registers(tp);
3763 }
3764
1da177e4 3765 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3766
3767 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3768 RTL_R8(IntrMask);
1da177e4
LT		 3769
3770 RTL_W32(RxMissed, 0);
3771
07ce4064 3772 rtl_set_rx_mode(dev);
1da177e4
LT		 3773
3774 /* no early-rx interrupts */
3775 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3776
3777 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3778 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3779}
1da177e4 3780
9c14ceaf 3781static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3782{
9c14ceaf
FR		 3783 struct net_device *dev = pci_get_drvdata(pdev);
3784 struct rtl8169_private *tp = netdev_priv(dev);
3785 int cap = tp->pcie_cap;
3786
3787 if (cap) {
3788 u16 ctl;
458a9f61 3789
9c14ceaf
FR		 3790 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3791 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3792 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3793 }
458a9f61
FR		 3794}
3795
650e8d5d 3796static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3797{
3798 u32 csi;
3799
3800 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3801 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3802}
3803
e6de30d6 3804static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3805{
3806 rtl_csi_access_enable(ioaddr, 0x17000000);
3807}
3808
650e8d5d 3809static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3810{
3811 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3812}
3813
3814struct ephy_info {
3815 unsigned int offset;
3816 u16 mask;
3817 u16 bits;
3818};
3819
350f7596 3820static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3821{
3822 u16 w;
3823
3824 while (len-- > 0) {
3825 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3826 rtl_ephy_write(ioaddr, e->offset, w);
3827 e++;
3828 }
3829}
3830
b726e493
FR		 3831static void rtl_disable_clock_request(struct pci_dev *pdev)
3832{
3833 struct net_device *dev = pci_get_drvdata(pdev);
3834 struct rtl8169_private *tp = netdev_priv(dev);
3835 int cap = tp->pcie_cap;
3836
3837 if (cap) {
3838 u16 ctl;
3839
3840 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3841 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3842 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3843 }
3844}
3845
e6de30d6 3846static void rtl_enable_clock_request(struct pci_dev *pdev)
3847{
3848 struct net_device *dev = pci_get_drvdata(pdev);
3849 struct rtl8169_private *tp = netdev_priv(dev);
3850 int cap = tp->pcie_cap;
3851
3852 if (cap) {
3853 u16 ctl;
3854
3855 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3856 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3857 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3858 }
3859}
3860
b726e493
FR		 3861#define R8168_CPCMD_QUIRK_MASK (\
3862 EnableBist | \
3863 Mac_dbgo_oe | \
3864 Force_half_dup | \
3865 Force_rxflow_en | \
3866 Force_txflow_en | \
3867 Cxpl_dbg_sel | \
3868 ASF | \
3869 PktCntrDisable | \
3870 Mac_dbgo_sel)
3871
219a1e9d
FR		 3872static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3873{
b726e493
FR		 3874 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3875
3876 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3877
2e68ae44
FR		 3878 rtl_tx_performance_tweak(pdev,
3879 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3880}
3881
3882static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3883{
3884 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3885
f0298f81 3886 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3887
3888 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3889}
3890
3891static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3892{
b726e493
FR		 3893 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3894
3895 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3896
219a1e9d 3897 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3898
3899 rtl_disable_clock_request(pdev);
3900
3901 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3902}
3903
ef3386f0 3904static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3905{
350f7596 3906 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3907 { 0x01, 0, 0x0001 },
3908 { 0x02, 0x0800, 0x1000 },
3909 { 0x03, 0, 0x0042 },
3910 { 0x06, 0x0080, 0x0000 },
3911 { 0x07, 0, 0x2000 }
3912 };
3913
650e8d5d 3914 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3915
3916 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3917
219a1e9d
FR		 3918 __rtl_hw_start_8168cp(ioaddr, pdev);
3919}
3920
ef3386f0
FR		 3921static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3922{
650e8d5d 3923 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3924
3925 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3926
3927 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3928
3929 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3930}
3931
7f3e3d3a
FR		 3932static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3933{
650e8d5d 3934 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3935
3936 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3937
3938 /* Magic. */
3939 RTL_W8(DBG_REG, 0x20);
3940
f0298f81 3941 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3942
3943 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3944
3945 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3946}
3947
219a1e9d
FR		 3948static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3949{
350f7596 3950 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3951 { 0x02, 0x0800, 0x1000 },
3952 { 0x03, 0, 0x0002 },
3953 { 0x06, 0x0080, 0x0000 }
3954 };
3955
650e8d5d 3956 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3957
3958 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3959
3960 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3961
219a1e9d
FR		 3962 __rtl_hw_start_8168cp(ioaddr, pdev);
3963}
3964
3965static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3966{
350f7596 3967 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3968 { 0x01, 0, 0x0001 },
3969 { 0x03, 0x0400, 0x0220 }
3970 };
3971
650e8d5d 3972 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3973
3974 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3975
219a1e9d
FR		 3976 __rtl_hw_start_8168cp(ioaddr, pdev);
3977}
3978
197ff761
FR		 3979static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3980{
3981 rtl_hw_start_8168c_2(ioaddr, pdev);
3982}
3983
6fb07058
FR		 3984static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3985{
650e8d5d 3986 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3987
3988 __rtl_hw_start_8168cp(ioaddr, pdev);
3989}
3990
5b538df9
FR		 3991static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3992{
650e8d5d 3993 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3994
3995 rtl_disable_clock_request(pdev);
3996
f0298f81 3997 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3998
3999 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4000
4001 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4002}
4003
4804b3b3 4004static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4005{
4006 rtl_csi_access_enable_1(ioaddr);
4007
4008 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4009
4010 RTL_W8(MaxTxPacketSize, TxPacketMax);
4011
4012 rtl_disable_clock_request(pdev);
4013}
4014
e6de30d6 4015static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4016{
4017 static const struct ephy_info e_info_8168d_4[] = {
4018 { 0x0b, ~0, 0x48 },
4019 { 0x19, 0x20, 0x50 },
4020 { 0x0c, ~0, 0x20 }
4021 };
4022 int i;
4023
4024 rtl_csi_access_enable_1(ioaddr);
4025
4026 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4027
4028 RTL_W8(MaxTxPacketSize, TxPacketMax);
4029
4030 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4031 const struct ephy_info *e = e_info_8168d_4 + i;
4032 u16 w;
4033
4034 w = rtl_ephy_read(ioaddr, e->offset);
4035 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4036 }
4037
4038 rtl_enable_clock_request(pdev);
4039}
4040
01dc7fec 4041static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4042{
4043 static const struct ephy_info e_info_8168e[] = {
4044 { 0x00, 0x0200, 0x0100 },
4045 { 0x00, 0x0000, 0x0004 },
4046 { 0x06, 0x0002, 0x0001 },
4047 { 0x06, 0x0000, 0x0030 },
4048 { 0x07, 0x0000, 0x2000 },
4049 { 0x00, 0x0000, 0x0020 },
4050 { 0x03, 0x5800, 0x2000 },
4051 { 0x03, 0x0000, 0x0001 },
4052 { 0x01, 0x0800, 0x1000 },
4053 { 0x07, 0x0000, 0x4000 },
4054 { 0x1e, 0x0000, 0x2000 },
4055 { 0x19, 0xffff, 0xfe6c },
4056 { 0x0a, 0x0000, 0x0040 }
4057 };
4058
4059 rtl_csi_access_enable_2(ioaddr);
4060
4061 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4062
4063 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4064
4065 RTL_W8(MaxTxPacketSize, TxPacketMax);
4066
4067 rtl_disable_clock_request(pdev);
4068
4069 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4070 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4071 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4072
cecb5fd7 4073 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4074}
4075
07ce4064
FR		 4076static void rtl_hw_start_8168(struct net_device *dev)
4077{
2dd99530
FR		 4078 struct rtl8169_private *tp = netdev_priv(dev);
4079 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4080 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4081
4082 RTL_W8(Cfg9346, Cfg9346_Unlock);
4083
f0298f81 4084 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4085
6f0333b8 4086 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4087
0e485150 4088 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4089
4090 RTL_W16(CPlusCmd, tp->cp_cmd);
4091
0e485150 4092 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4093
0e485150 4094 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4095 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4096 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4097 tp->intr_event |= RxFIFOOver | PCSTimeout;
4098 tp->intr_event &= ~RxOverflow;
4099 }
4100
4101 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4102
b8363901
FR		 4103 rtl_set_rx_mode(dev);
4104
4105 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4106 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4107
4108 RTL_R8(IntrMask);
4109
219a1e9d
FR		 4110 switch (tp->mac_version) {
4111 case RTL_GIGA_MAC_VER_11:
4112 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4113 break;
219a1e9d
FR		 4114
4115 case RTL_GIGA_MAC_VER_12:
4116 case RTL_GIGA_MAC_VER_17:
4117 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4118 break;
219a1e9d
FR		 4119
4120 case RTL_GIGA_MAC_VER_18:
ef3386f0 4121 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4122 break;
219a1e9d
FR		 4123
4124 case RTL_GIGA_MAC_VER_19:
4125 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4126 break;
219a1e9d
FR		 4127
4128 case RTL_GIGA_MAC_VER_20:
4129 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4130 break;
219a1e9d 4131
197ff761
FR		 4132 case RTL_GIGA_MAC_VER_21:
4133 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4134 break;
197ff761 4135
6fb07058
FR		 4136 case RTL_GIGA_MAC_VER_22:
4137 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4138 break;
6fb07058 4139
ef3386f0
FR		 4140 case RTL_GIGA_MAC_VER_23:
4141 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4142 break;
ef3386f0 4143
7f3e3d3a
FR		 4144 case RTL_GIGA_MAC_VER_24:
4145 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4146 break;
7f3e3d3a 4147
5b538df9 4148 case RTL_GIGA_MAC_VER_25:
daf9df6d 4149 case RTL_GIGA_MAC_VER_26:
4150 case RTL_GIGA_MAC_VER_27:
5b538df9 4151 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4152 break;
5b538df9 4153
e6de30d6 4154 case RTL_GIGA_MAC_VER_28:
4155 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4156 break;
cecb5fd7 4157
4804b3b3 4158 case RTL_GIGA_MAC_VER_31:
4159 rtl_hw_start_8168dp(ioaddr, pdev);
4160 break;
4161
01dc7fec 4162 case RTL_GIGA_MAC_VER_32:
4163 case RTL_GIGA_MAC_VER_33:
4164 rtl_hw_start_8168e(ioaddr, pdev);
4165 break;
e6de30d6 4166
219a1e9d
FR		 4167 default:
4168 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4169 dev->name, tp->mac_version);
4804b3b3 4170 break;
219a1e9d 4171 }
2dd99530 4172
0e485150
FR		 4173 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4174
b8363901
FR		 4175 RTL_W8(Cfg9346, Cfg9346_Lock);
4176
2dd99530 4177 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4178
0e485150 4179 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4180}
1da177e4 4181
2857ffb7
FR		 4182#define R810X_CPCMD_QUIRK_MASK (\
4183 EnableBist | \
4184 Mac_dbgo_oe | \
4185 Force_half_dup | \
5edcc537 4186 Force_rxflow_en | \
2857ffb7
FR		 4187 Force_txflow_en | \
4188 Cxpl_dbg_sel | \
4189 ASF | \
4190 PktCntrDisable | \
d24e9aaf 4191 Mac_dbgo_sel)
2857ffb7
FR		 4192
4193static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4194{
350f7596 4195 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4196 { 0x01, 0, 0x6e65 },
4197 { 0x02, 0, 0x091f },
4198 { 0x03, 0, 0xc2f9 },
4199 { 0x06, 0, 0xafb5 },
4200 { 0x07, 0, 0x0e00 },
4201 { 0x19, 0, 0xec80 },
4202 { 0x01, 0, 0x2e65 },
4203 { 0x01, 0, 0x6e65 }
4204 };
4205 u8 cfg1;
4206
650e8d5d 4207 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4208
4209 RTL_W8(DBG_REG, FIX_NAK_1);
4210
4211 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4212
4213 RTL_W8(Config1,
4214 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4215 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4216
4217 cfg1 = RTL_R8(Config1);
4218 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4219 RTL_W8(Config1, cfg1 & ~LEDS0);
4220
2857ffb7
FR		 4221 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4222}
4223
4224static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4225{
650e8d5d 4226 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4227
4228 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4229
4230 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4231 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4232}
4233
4234static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4235{
4236 rtl_hw_start_8102e_2(ioaddr, pdev);
4237
4238 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4239}
4240
5a5e4443
HW		 4241static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4242{
4243 static const struct ephy_info e_info_8105e_1[] = {
4244 { 0x07, 0, 0x4000 },
4245 { 0x19, 0, 0x0200 },
4246 { 0x19, 0, 0x0020 },
4247 { 0x1e, 0, 0x2000 },
4248 { 0x03, 0, 0x0001 },
4249 { 0x19, 0, 0x0100 },
4250 { 0x19, 0, 0x0004 },
4251 { 0x0a, 0, 0x0020 }
4252 };
4253
cecb5fd7 4254 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4255 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4256
cecb5fd7 4257 /* Disable Early Tally Counter */
5a5e4443
HW		 4258 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4259
4260 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4261 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4262
4263 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4264}
4265
4266static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4267{
4268 rtl_hw_start_8105e_1(ioaddr, pdev);
4269 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4270}
4271
07ce4064
FR		 4272static void rtl_hw_start_8101(struct net_device *dev)
4273{
cdf1a608
FR		 4274 struct rtl8169_private *tp = netdev_priv(dev);
4275 void __iomem *ioaddr = tp->mmio_addr;
4276 struct pci_dev *pdev = tp->pci_dev;
4277
cecb5fd7
FR		 4278 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4279 tp->mac_version == RTL_GIGA_MAC_VER_16) {
9c14ceaf
FR		 4280 int cap = tp->pcie_cap;
4281
4282 if (cap) {
4283 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4284 PCI_EXP_DEVCTL_NOSNOOP_EN);
4285 }
cdf1a608
FR		 4286 }
4287
d24e9aaf
HW		 4288 RTL_W8(Cfg9346, Cfg9346_Unlock);
4289
2857ffb7
FR		 4290 switch (tp->mac_version) {
4291 case RTL_GIGA_MAC_VER_07:
4292 rtl_hw_start_8102e_1(ioaddr, pdev);
4293 break;
4294
4295 case RTL_GIGA_MAC_VER_08:
4296 rtl_hw_start_8102e_3(ioaddr, pdev);
4297 break;
4298
4299 case RTL_GIGA_MAC_VER_09:
4300 rtl_hw_start_8102e_2(ioaddr, pdev);
4301 break;
5a5e4443
HW		 4302
4303 case RTL_GIGA_MAC_VER_29:
4304 rtl_hw_start_8105e_1(ioaddr, pdev);
4305 break;
4306 case RTL_GIGA_MAC_VER_30:
4307 rtl_hw_start_8105e_2(ioaddr, pdev);
4308 break;
cdf1a608
FR		 4309 }
4310
d24e9aaf 4311 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4312
f0298f81 4313 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4314
6f0333b8 4315 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4316
d24e9aaf 4317 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4318 RTL_W16(CPlusCmd, tp->cp_cmd);
4319
4320 RTL_W16(IntrMitigate, 0x0000);
4321
4322 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4323
4324 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4325 rtl_set_rx_tx_config_registers(tp);
4326
cdf1a608
FR		 4327 RTL_R8(IntrMask);
4328
cdf1a608
FR		 4329 rtl_set_rx_mode(dev);
4330
4331 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4332
0e485150 4333 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4334}
4335
4336static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4337{
1da177e4
LT		 4338 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4339 return -EINVAL;
4340
4341 dev->mtu = new_mtu;
350fb32a
MM		 4342 netdev_update_features(dev);
4343
323bb685 4344 return 0;
1da177e4
LT		 4345}
4346
4347static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4348{
95e0918d 4349 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4350 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4351}
4352
6f0333b8
ED		 4353static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4354 void **data_buff, struct RxDesc *desc)
1da177e4 4355{
48addcc9 4356 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4357 DMA_FROM_DEVICE);
48addcc9 4358
6f0333b8
ED		 4359 kfree(*data_buff);
4360 *data_buff = NULL;
1da177e4
LT		 4361 rtl8169_make_unusable_by_asic(desc);
4362}
4363
4364static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4365{
4366 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4367
4368 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4369}
4370
4371static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4372 u32 rx_buf_sz)
4373{
4374 desc->addr = cpu_to_le64(mapping);
4375 wmb();
4376 rtl8169_mark_to_asic(desc, rx_buf_sz);
4377}
4378
6f0333b8
ED		 4379static inline void *rtl8169_align(void *data)
4380{
4381 return (void *)ALIGN((long)data, 16);
4382}
4383
0ecbe1ca
SG		 4384static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4385 struct RxDesc *desc)
1da177e4 4386{
6f0333b8 4387 void *data;
1da177e4 4388 dma_addr_t mapping;
48addcc9 4389 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4390 struct net_device *dev = tp->dev;
6f0333b8 4391 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4392
6f0333b8
ED		 4393 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4394 if (!data)
4395 return NULL;
e9f63f30 4396
6f0333b8
ED		 4397 if (rtl8169_align(data) != data) {
4398 kfree(data);
4399 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4400 if (!data)
4401 return NULL;
4402 }
3eafe507 4403
48addcc9 4404 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4405 DMA_FROM_DEVICE);
d827d86b
SG		 4406 if (unlikely(dma_mapping_error(d, mapping))) {
4407 if (net_ratelimit())
4408 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4409 goto err_out;
d827d86b 4410 }
1da177e4
LT		 4411
4412 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4413 return data;
3eafe507
SG		 4414
4415err_out:
4416 kfree(data);
4417 return NULL;
1da177e4
LT		 4418}
4419
4420static void rtl8169_rx_clear(struct rtl8169_private *tp)
4421{
07d3f51f 4422 unsigned int i;
1da177e4
LT		 4423
4424 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4425 if (tp->Rx_databuff[i]) {
4426 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4427 tp->RxDescArray + i);
4428 }
4429 }
4430}
4431
0ecbe1ca 4432static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4433{
0ecbe1ca
SG		 4434 desc->opts1 |= cpu_to_le32(RingEnd);
4435}
5b0384f4 4436
0ecbe1ca
SG		 4437static int rtl8169_rx_fill(struct rtl8169_private *tp)
4438{
4439 unsigned int i;
1da177e4 4440
0ecbe1ca
SG		 4441 for (i = 0; i < NUM_RX_DESC; i++) {
4442 void *data;
4ae47c2d 4443
6f0333b8 4444 if (tp->Rx_databuff[i])
1da177e4 4445 continue;
bcf0bf90 4446
0ecbe1ca 4447 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4448 if (!data) {
4449 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4450 goto err_out;
6f0333b8
ED		 4451 }
4452 tp->Rx_databuff[i] = data;
1da177e4 4453 }
1da177e4 4454
0ecbe1ca
SG		 4455 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4456 return 0;
4457
4458err_out:
4459 rtl8169_rx_clear(tp);
4460 return -ENOMEM;
1da177e4
LT		 4461}
4462
4463static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4464{
4465 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4466}
4467
4468static int rtl8169_init_ring(struct net_device *dev)
4469{
4470 struct rtl8169_private *tp = netdev_priv(dev);
4471
4472 rtl8169_init_ring_indexes(tp);
4473
4474 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4475 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4476
0ecbe1ca 4477 return rtl8169_rx_fill(tp);
1da177e4
LT		 4478}
4479
48addcc9 4480static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4481 struct TxDesc *desc)
4482{
4483 unsigned int len = tx_skb->len;
4484
48addcc9
SG		 4485 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4486
1da177e4
LT		 4487 desc->opts1 = 0x00;
4488 desc->opts2 = 0x00;
4489 desc->addr = 0x00;
4490 tx_skb->len = 0;
4491}
4492
3eafe507
SG		 4493static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4494 unsigned int n)
1da177e4
LT		 4495{
4496 unsigned int i;
4497
3eafe507
SG		 4498 for (i = 0; i < n; i++) {
4499 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4500 struct ring_info *tx_skb = tp->tx_skb + entry;
4501 unsigned int len = tx_skb->len;
4502
4503 if (len) {
4504 struct sk_buff *skb = tx_skb->skb;
4505
48addcc9 4506 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4507 tp->TxDescArray + entry);
4508 if (skb) {
cac4b22f 4509 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4510 dev_kfree_skb(skb);
4511 tx_skb->skb = NULL;
4512 }
1da177e4
LT		 4513 }
4514 }
3eafe507
SG		 4515}
4516
4517static void rtl8169_tx_clear(struct rtl8169_private *tp)
4518{
4519 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4520 tp->cur_tx = tp->dirty_tx = 0;
4521}
4522
c4028958 4523static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4524{
4525 struct rtl8169_private *tp = netdev_priv(dev);
4526
c4028958 4527 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4528 schedule_delayed_work(&tp->task, 4);
4529}
4530
4531static void rtl8169_wait_for_quiescence(struct net_device *dev)
4532{
4533 struct rtl8169_private *tp = netdev_priv(dev);
4534 void __iomem *ioaddr = tp->mmio_addr;
4535
4536 synchronize_irq(dev->irq);
4537
4538 /* Wait for any pending NAPI task to complete */
bea3348e 4539 napi_disable(&tp->napi);
1da177e4
LT		 4540
4541 rtl8169_irq_mask_and_ack(ioaddr);
4542
d1d08d12
DM		 4543 tp->intr_mask = 0xffff;
4544 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4545 napi_enable(&tp->napi);
1da177e4
LT		 4546}
4547
c4028958 4548static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4549{
c4028958
DH		 4550 struct rtl8169_private *tp =
4551 container_of(work, struct rtl8169_private, task.work);
4552 struct net_device *dev = tp->dev;
1da177e4
LT		 4553 int ret;
4554
eb2a021c
FR		 4555 rtnl_lock();
4556
4557 if (!netif_running(dev))
4558 goto out_unlock;
4559
4560 rtl8169_wait_for_quiescence(dev);
4561 rtl8169_close(dev);
1da177e4
LT		 4562
4563 ret = rtl8169_open(dev);
4564 if (unlikely(ret < 0)) {
bf82c189
JP		 4565 if (net_ratelimit())
4566 netif_err(tp, drv, dev,
4567 "reinit failure (status = %d). Rescheduling\n",
4568 ret);
1da177e4
LT		 4569 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4570 }
eb2a021c
FR		 4571
4572out_unlock:
4573 rtnl_unlock();
1da177e4
LT		 4574}
4575
c4028958 4576static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4577{
c4028958
DH		 4578 struct rtl8169_private *tp =
4579 container_of(work, struct rtl8169_private, task.work);
4580 struct net_device *dev = tp->dev;
56de414c 4581 int i;
1da177e4 4582
eb2a021c
FR		 4583 rtnl_lock();
4584
1da177e4 4585 if (!netif_running(dev))
eb2a021c 4586 goto out_unlock;
1da177e4
LT		 4587
4588 rtl8169_wait_for_quiescence(dev);
4589
56de414c
FR		 4590 for (i = 0; i < NUM_RX_DESC; i++)
4591 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4592
1da177e4
LT		 4593 rtl8169_tx_clear(tp);
4594
56de414c
FR		 4595 rtl8169_init_ring_indexes(tp);
4596 rtl_hw_start(dev);
4597 netif_wake_queue(dev);
4598 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4599
4600out_unlock:
4601 rtnl_unlock();
1da177e4
LT		 4602}
4603
4604static void rtl8169_tx_timeout(struct net_device *dev)
4605{
4606 struct rtl8169_private *tp = netdev_priv(dev);
4607
e6de30d6 4608 rtl8169_hw_reset(tp);
1da177e4
LT		 4609
4610 /* Let's wait a bit while any (async) irq lands on */
4611 rtl8169_schedule_work(dev, rtl8169_reset_task);
4612}
4613
4614static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4615 u32 *opts)
1da177e4
LT		 4616{
4617 struct skb_shared_info *info = skb_shinfo(skb);
4618 unsigned int cur_frag, entry;
a6343afb 4619 struct TxDesc * uninitialized_var(txd);
48addcc9 4620 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4621
4622 entry = tp->cur_tx;
4623 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4624 skb_frag_t *frag = info->frags + cur_frag;
4625 dma_addr_t mapping;
4626 u32 status, len;
4627 void *addr;
4628
4629 entry = (entry + 1) % NUM_TX_DESC;
4630
4631 txd = tp->TxDescArray + entry;
4632 len = frag->size;
4633 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4634 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4635 if (unlikely(dma_mapping_error(d, mapping))) {
4636 if (net_ratelimit())
4637 netif_err(tp, drv, tp->dev,
4638 "Failed to map TX fragments DMA!\n");
3eafe507 4639 goto err_out;
d827d86b 4640 }
1da177e4 4641
cecb5fd7 4642 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4643 status = opts[0] | len |
4644 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4645
4646 txd->opts1 = cpu_to_le32(status);
2b7b4318 4647 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4648 txd->addr = cpu_to_le64(mapping);
4649
4650 tp->tx_skb[entry].len = len;
4651 }
4652
4653 if (cur_frag) {
4654 tp->tx_skb[entry].skb = skb;
4655 txd->opts1 |= cpu_to_le32(LastFrag);
4656 }
4657
4658 return cur_frag;
3eafe507
SG		 4659
4660err_out:
4661 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4662 return -EIO;
1da177e4
LT		 4663}
4664
2b7b4318
FR		 4665static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4666 struct sk_buff *skb, u32 *opts)
1da177e4 4667{
2b7b4318 4668 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4669 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4670 int offset = info->opts_offset;
350fb32a 4671
2b7b4318
FR		 4672 if (mss) {
4673 opts[0] |= TD_LSO;
4674 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4675 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4676 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4677
4678 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4679 opts[offset] |= info->checksum.tcp;
1da177e4 4680 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4681 opts[offset] |= info->checksum.udp;
4682 else
4683 WARN_ON_ONCE(1);
1da177e4 4684 }
1da177e4
LT		 4685}
4686
61357325
SH		 4687static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4688 struct net_device *dev)
1da177e4
LT		 4689{
4690 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4691 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4692 struct TxDesc *txd = tp->TxDescArray + entry;
4693 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4694 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4695 dma_addr_t mapping;
4696 u32 status, len;
2b7b4318 4697 u32 opts[2];
3eafe507 4698 int frags;
5b0384f4 4699
1da177e4 4700 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4701 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4702 goto err_stop_0;
1da177e4
LT		 4703 }
4704
4705 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4706 goto err_stop_0;
4707
4708 len = skb_headlen(skb);
48addcc9 4709 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4710 if (unlikely(dma_mapping_error(d, mapping))) {
4711 if (net_ratelimit())
4712 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4713 goto err_dma_0;
d827d86b 4714 }
3eafe507
SG		 4715
4716 tp->tx_skb[entry].len = len;
4717 txd->addr = cpu_to_le64(mapping);
1da177e4 4718
2b7b4318
FR		 4719 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4720 opts[0] = DescOwn;
1da177e4 4721
2b7b4318
FR		 4722 rtl8169_tso_csum(tp, skb, opts);
4723
4724 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4725 if (frags < 0)
4726 goto err_dma_1;
4727 else if (frags)
2b7b4318 4728 opts[0] |= FirstFrag;
3eafe507 4729 else {
2b7b4318 4730 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4731 tp->tx_skb[entry].skb = skb;
4732 }
4733
2b7b4318
FR		 4734 txd->opts2 = cpu_to_le32(opts[1]);
4735
1da177e4
LT		 4736 wmb();
4737
cecb5fd7 4738 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 4739 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4740 txd->opts1 = cpu_to_le32(status);
4741
1da177e4
LT		 4742 tp->cur_tx += frags + 1;
4743
4c020a96 4744 wmb();
1da177e4 4745
cecb5fd7 4746 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4747
4748 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4749 netif_stop_queue(dev);
4750 smp_rmb();
4751 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4752 netif_wake_queue(dev);
4753 }
4754
61357325 4755 return NETDEV_TX_OK;
1da177e4 4756
3eafe507 4757err_dma_1:
48addcc9 4758 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4759err_dma_0:
4760 dev_kfree_skb(skb);
4761 dev->stats.tx_dropped++;
4762 return NETDEV_TX_OK;
4763
4764err_stop_0:
1da177e4 4765 netif_stop_queue(dev);
cebf8cc7 4766 dev->stats.tx_dropped++;
61357325 4767 return NETDEV_TX_BUSY;
1da177e4
LT		 4768}
4769
4770static void rtl8169_pcierr_interrupt(struct net_device *dev)
4771{
4772 struct rtl8169_private *tp = netdev_priv(dev);
4773 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4774 u16 pci_status, pci_cmd;
4775
4776 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4777 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4778
bf82c189
JP		 4779 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4780 pci_cmd, pci_status);
1da177e4
LT		 4781
4782 /*
4783 * The recovery sequence below admits a very elaborated explanation:
4784 * - it seems to work;
d03902b8
FR		 4785 * - I did not see what else could be done;
4786 * - it makes iop3xx happy.
1da177e4
LT		 4787 *
4788 * Feel free to adjust to your needs.
4789 */
a27993f3 4790 if (pdev->broken_parity_status)
d03902b8
FR		 4791 pci_cmd &= ~PCI_COMMAND_PARITY;
4792 else
4793 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4794
4795 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4796
4797 pci_write_config_word(pdev, PCI_STATUS,
4798 pci_status & (PCI_STATUS_DETECTED_PARITY |
4799 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4800 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4801
4802 /* The infamous DAC f*ckup only happens at boot time */
4803 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4804 void __iomem *ioaddr = tp->mmio_addr;
4805
bf82c189 4806 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4807 tp->cp_cmd &= ~PCIDAC;
4808 RTL_W16(CPlusCmd, tp->cp_cmd);
4809 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4810 }
4811
e6de30d6 4812 rtl8169_hw_reset(tp);
d03902b8
FR		 4813
4814 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4815}
4816
07d3f51f
FR		 4817static void rtl8169_tx_interrupt(struct net_device *dev,
4818 struct rtl8169_private *tp,
4819 void __iomem *ioaddr)
1da177e4
LT		 4820{
4821 unsigned int dirty_tx, tx_left;
4822
1da177e4
LT		 4823 dirty_tx = tp->dirty_tx;
4824 smp_rmb();
4825 tx_left = tp->cur_tx - dirty_tx;
4826
4827 while (tx_left > 0) {
4828 unsigned int entry = dirty_tx % NUM_TX_DESC;
4829 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4830 u32 status;
4831
4832 rmb();
4833 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4834 if (status & DescOwn)
4835 break;
4836
48addcc9
SG		 4837 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4838 tp->TxDescArray + entry);
1da177e4 4839 if (status & LastFrag) {
cac4b22f
SG		 4840 dev->stats.tx_packets++;
4841 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4842 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4843 tx_skb->skb = NULL;
4844 }
4845 dirty_tx++;
4846 tx_left--;
4847 }
4848
4849 if (tp->dirty_tx != dirty_tx) {
4850 tp->dirty_tx = dirty_tx;
4851 smp_wmb();
4852 if (netif_queue_stopped(dev) &&
4853 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4854 netif_wake_queue(dev);
4855 }
d78ae2dc
FR		 4856 /*
4857 * 8168 hack: TxPoll requests are lost when the Tx packets are
4858 * too close. Let's kick an extra TxPoll request when a burst
4859 * of start_xmit activity is detected (if it is not detected,
4860 * it is slow enough). -- FR
4861 */
4862 smp_rmb();
4863 if (tp->cur_tx != dirty_tx)
4864 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4865 }
4866}
4867
126fa4b9
FR		 4868static inline int rtl8169_fragmented_frame(u32 status)
4869{
4870 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4871}
4872
adea1ac7 4873static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4874{
1da177e4
LT		 4875 u32 status = opts1 & RxProtoMask;
4876
4877 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4878 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4879 skb->ip_summed = CHECKSUM_UNNECESSARY;
4880 else
bc8acf2c 4881 skb_checksum_none_assert(skb);
1da177e4
LT		 4882}
4883
6f0333b8
ED		 4884static struct sk_buff *rtl8169_try_rx_copy(void *data,
4885 struct rtl8169_private *tp,
4886 int pkt_size,
4887 dma_addr_t addr)
1da177e4 4888{
b449655f 4889 struct sk_buff *skb;
48addcc9 4890 struct device *d = &tp->pci_dev->dev;
b449655f 4891
6f0333b8 4892 data = rtl8169_align(data);
48addcc9 4893 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4894 prefetch(data);
4895 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4896 if (skb)
4897 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4898 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4899
6f0333b8 4900 return skb;
1da177e4
LT		 4901}
4902
07d3f51f
FR		 4903static int rtl8169_rx_interrupt(struct net_device *dev,
4904 struct rtl8169_private *tp,
bea3348e 4905 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4906{
4907 unsigned int cur_rx, rx_left;
6f0333b8 4908 unsigned int count;
1da177e4 4909
1da177e4
LT		 4910 cur_rx = tp->cur_rx;
4911 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4912 rx_left = min(rx_left, budget);
1da177e4 4913
4dcb7d33 4914 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4915 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4916 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4917 u32 status;
4918
4919 rmb();
126fa4b9 4920 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4921
4922 if (status & DescOwn)
4923 break;
4dcb7d33 4924 if (unlikely(status & RxRES)) {
bf82c189
JP		 4925 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4926 status);
cebf8cc7 4927 dev->stats.rx_errors++;
1da177e4 4928 if (status & (RxRWT | RxRUNT))
cebf8cc7 4929 dev->stats.rx_length_errors++;
1da177e4 4930 if (status & RxCRC)
cebf8cc7 4931 dev->stats.rx_crc_errors++;
9dccf611
FR		 4932 if (status & RxFOVF) {
4933 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4934 dev->stats.rx_fifo_errors++;
9dccf611 4935 }
6f0333b8 4936 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4937 } else {
6f0333b8 4938 struct sk_buff *skb;
b449655f 4939 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4940 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4941
126fa4b9
FR		 4942 /*
4943 * The driver does not support incoming fragmented
4944 * frames. They are seen as a symptom of over-mtu
4945 * sized frames.
4946 */
4947 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4948 dev->stats.rx_dropped++;
4949 dev->stats.rx_length_errors++;
6f0333b8 4950 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4951 continue;
126fa4b9
FR		 4952 }
4953
6f0333b8
ED		 4954 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4955 tp, pkt_size, addr);
4956 rtl8169_mark_to_asic(desc, rx_buf_sz);
4957 if (!skb) {
4958 dev->stats.rx_dropped++;
4959 continue;
1da177e4
LT		 4960 }
4961
adea1ac7 4962 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4963 skb_put(skb, pkt_size);
4964 skb->protocol = eth_type_trans(skb, dev);
4965
7a8fc77b
FR		 4966 rtl8169_rx_vlan_tag(desc, skb);
4967
56de414c 4968 napi_gro_receive(&tp->napi, skb);
1da177e4 4969
cebf8cc7
FR		 4970 dev->stats.rx_bytes += pkt_size;
4971 dev->stats.rx_packets++;
1da177e4 4972 }
6dccd16b
FR		 4973
4974 /* Work around for AMD plateform. */
95e0918d 4975 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4976 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4977 desc->opts2 = 0;
4978 cur_rx++;
4979 }
1da177e4
LT		 4980 }
4981
4982 count = cur_rx - tp->cur_rx;
4983 tp->cur_rx = cur_rx;
4984
6f0333b8 4985 tp->dirty_rx += count;
1da177e4
LT		 4986
4987 return count;
4988}
4989
07d3f51f 4990static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4991{
07d3f51f 4992 struct net_device *dev = dev_instance;
1da177e4 4993 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4994 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4995 int handled = 0;
865c652d 4996 int status;
1da177e4 4997
f11a377b
DD		 4998 /* loop handling interrupts until we have no new ones or
4999 * we hit a invalid/hotplug case.
5000 */
865c652d 5001 status = RTL_R16(IntrStatus);
f11a377b
DD		 5002 while (status && status != 0xffff) {
5003 handled = 1;
1da177e4 5004
f11a377b
DD		 5005 /* Handle all of the error cases first. These will reset
5006 * the chip, so just exit the loop.
5007 */
5008 if (unlikely(!netif_running(dev))) {
5009 rtl8169_asic_down(ioaddr);
5010 break;
5011 }
1da177e4 5012
1519e57f
FR		 5013 if (unlikely(status & RxFIFOOver)) {
5014 switch (tp->mac_version) {
5015 /* Work around for rx fifo overflow */
5016 case RTL_GIGA_MAC_VER_11:
5017 case RTL_GIGA_MAC_VER_22:
5018 case RTL_GIGA_MAC_VER_26:
5019 netif_stop_queue(dev);
5020 rtl8169_tx_timeout(dev);
5021 goto done;
f60ac8e7
FR		 5022 /* Testers needed. */
5023 case RTL_GIGA_MAC_VER_17:
5024 case RTL_GIGA_MAC_VER_19:
5025 case RTL_GIGA_MAC_VER_20:
5026 case RTL_GIGA_MAC_VER_21:
5027 case RTL_GIGA_MAC_VER_23:
5028 case RTL_GIGA_MAC_VER_24:
5029 case RTL_GIGA_MAC_VER_27:
5030 case RTL_GIGA_MAC_VER_28:
4804b3b3 5031 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5032 /* Experimental science. Pktgen proof. */
5033 case RTL_GIGA_MAC_VER_12:
5034 case RTL_GIGA_MAC_VER_25:
5035 if (status == RxFIFOOver)
5036 goto done;
5037 break;
5038 default:
5039 break;
5040 }
f11a377b 5041 }
1da177e4 5042
f11a377b
DD		 5043 if (unlikely(status & SYSErr)) {
5044 rtl8169_pcierr_interrupt(dev);
5045 break;
5046 }
1da177e4 5047
f11a377b 5048 if (status & LinkChg)
e4fbce74 5049 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5050
f11a377b
DD		 5051 /* We need to see the lastest version of tp->intr_mask to
5052 * avoid ignoring an MSI interrupt and having to wait for
5053 * another event which may never come.
5054 */
5055 smp_rmb();
5056 if (status & tp->intr_mask & tp->napi_event) {
5057 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5058 tp->intr_mask = ~tp->napi_event;
5059
5060 if (likely(napi_schedule_prep(&tp->napi)))
5061 __napi_schedule(&tp->napi);
bf82c189
JP		 5062 else
5063 netif_info(tp, intr, dev,
5064 "interrupt %04x in poll\n", status);
f11a377b 5065 }
1da177e4 5066
f11a377b
DD		 5067 /* We only get a new MSI interrupt when all active irq
5068 * sources on the chip have been acknowledged. So, ack
5069 * everything we've seen and check if new sources have become
5070 * active to avoid blocking all interrupts from the chip.
5071 */
5072 RTL_W16(IntrStatus,
5073 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5074 status = RTL_R16(IntrStatus);
865c652d 5075 }
1519e57f 5076done:
1da177e4
LT		 5077 return IRQ_RETVAL(handled);
5078}
5079
bea3348e 5080static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5081{
bea3348e
SH		 5082 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5083 struct net_device *dev = tp->dev;
1da177e4 5084 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5085 int work_done;
1da177e4 5086
bea3348e 5087 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5088 rtl8169_tx_interrupt(dev, tp, ioaddr);
5089
bea3348e 5090 if (work_done < budget) {
288379f0 5091 napi_complete(napi);
f11a377b
DD		 5092
5093 /* We need for force the visibility of tp->intr_mask
5094 * for other CPUs, as we can loose an MSI interrupt
5095 * and potentially wait for a retransmit timeout if we don't.
5096 * The posted write to IntrMask is safe, as it will
5097 * eventually make it to the chip and we won't loose anything
5098 * until it does.
1da177e4 5099 */
f11a377b 5100 tp->intr_mask = 0xffff;
4c020a96 5101 wmb();
0e485150 5102 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5103 }
5104
bea3348e 5105 return work_done;
1da177e4 5106}
1da177e4 5107
523a6094
FR		 5108static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5109{
5110 struct rtl8169_private *tp = netdev_priv(dev);
5111
5112 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5113 return;
5114
5115 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5116 RTL_W32(RxMissed, 0);
5117}
5118
1da177e4
LT		 5119static void rtl8169_down(struct net_device *dev)
5120{
5121 struct rtl8169_private *tp = netdev_priv(dev);
5122 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5123
4876cc1e 5124 del_timer_sync(&tp->timer);
1da177e4
LT		 5125
5126 netif_stop_queue(dev);
5127
93dd79e8 5128 napi_disable(&tp->napi);
93dd79e8 5129
1da177e4
LT		 5130 spin_lock_irq(&tp->lock);
5131
5132 rtl8169_asic_down(ioaddr);
323bb685
SG		 5133 /*
5134 * At this point device interrupts can not be enabled in any function,
5135 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5136 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5137 */
523a6094 5138 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5139
5140 spin_unlock_irq(&tp->lock);
5141
5142 synchronize_irq(dev->irq);
5143
1da177e4 5144 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5145 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5146
1da177e4
LT		 5147 rtl8169_tx_clear(tp);
5148
5149 rtl8169_rx_clear(tp);
065c27c1 5150
5151 rtl_pll_power_down(tp);
1da177e4
LT		 5152}
5153
5154static int rtl8169_close(struct net_device *dev)
5155{
5156 struct rtl8169_private *tp = netdev_priv(dev);
5157 struct pci_dev *pdev = tp->pci_dev;
5158
e1759441
RW		 5159 pm_runtime_get_sync(&pdev->dev);
5160
cecb5fd7 5161 /* Update counters before going down */
355423d0
IV		 5162 rtl8169_update_counters(dev);
5163
1da177e4
LT		 5164 rtl8169_down(dev);
5165
5166 free_irq(dev->irq, dev);
5167
82553bb6
SG		 5168 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5169 tp->RxPhyAddr);
5170 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5171 tp->TxPhyAddr);
1da177e4
LT		 5172 tp->TxDescArray = NULL;
5173 tp->RxDescArray = NULL;
5174
e1759441
RW		 5175 pm_runtime_put_sync(&pdev->dev);
5176
1da177e4
LT		 5177 return 0;
5178}
5179
07ce4064 5180static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5181{
5182 struct rtl8169_private *tp = netdev_priv(dev);
5183 void __iomem *ioaddr = tp->mmio_addr;
5184 unsigned long flags;
5185 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5186 int rx_mode;
1da177e4
LT		 5187 u32 tmp = 0;
5188
5189 if (dev->flags & IFF_PROMISC) {
5190 /* Unconditionally log net taps. */
bf82c189 5191 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5192 rx_mode =
5193 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5194 AcceptAllPhys;
5195 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5196 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5197 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5198 /* Too many to filter perfectly -- accept all multicasts. */
5199 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5200 mc_filter[1] = mc_filter[0] = 0xffffffff;
5201 } else {
22bedad3 5202 struct netdev_hw_addr *ha;
07d3f51f 5203
1da177e4
LT		 5204 rx_mode = AcceptBroadcast | AcceptMyPhys;
5205 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5206 netdev_for_each_mc_addr(ha, dev) {
5207 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5208 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5209 rx_mode |= AcceptMulticast;
5210 }
5211 }
5212
5213 spin_lock_irqsave(&tp->lock, flags);
5214
5215 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5216 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5217
f887cce8 5218 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5219 u32 data = mc_filter[0];
5220
5221 mc_filter[0] = swab32(mc_filter[1]);
5222 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5223 }
5224
1da177e4 5225 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5226 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5227
57a9f236
FR		 5228 RTL_W32(RxConfig, tmp);
5229
1da177e4
LT		 5230 spin_unlock_irqrestore(&tp->lock, flags);
5231}
5232
5233/**
5234 * rtl8169_get_stats - Get rtl8169 read/write statistics
5235 * @dev: The Ethernet Device to get statistics for
5236 *
5237 * Get TX/RX statistics for rtl8169
5238 */
5239static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5240{
5241 struct rtl8169_private *tp = netdev_priv(dev);
5242 void __iomem *ioaddr = tp->mmio_addr;
5243 unsigned long flags;
5244
5245 if (netif_running(dev)) {
5246 spin_lock_irqsave(&tp->lock, flags);
523a6094 5247 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5248 spin_unlock_irqrestore(&tp->lock, flags);
5249 }
5b0384f4 5250
cebf8cc7 5251 return &dev->stats;
1da177e4
LT		 5252}
5253
861ab440 5254static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5255{
065c27c1 5256 struct rtl8169_private *tp = netdev_priv(dev);
5257
5d06a99f 5258 if (!netif_running(dev))
861ab440 5259 return;
5d06a99f 5260
065c27c1 5261 rtl_pll_power_down(tp);
5262
5d06a99f
FR		 5263 netif_device_detach(dev);
5264 netif_stop_queue(dev);
861ab440
RW		 5265}
5266
5267#ifdef CONFIG_PM
5268
5269static int rtl8169_suspend(struct device *device)
5270{
5271 struct pci_dev *pdev = to_pci_dev(device);
5272 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5273
861ab440 5274 rtl8169_net_suspend(dev);
1371fa6d 5275
5d06a99f
FR		 5276 return 0;
5277}
5278
e1759441
RW		 5279static void __rtl8169_resume(struct net_device *dev)
5280{
065c27c1 5281 struct rtl8169_private *tp = netdev_priv(dev);
5282
e1759441 5283 netif_device_attach(dev);
065c27c1 5284
5285 rtl_pll_power_up(tp);
5286
e1759441
RW		 5287 rtl8169_schedule_work(dev, rtl8169_reset_task);
5288}
5289
861ab440 5290static int rtl8169_resume(struct device *device)
5d06a99f 5291{
861ab440 5292 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5293 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5294 struct rtl8169_private *tp = netdev_priv(dev);
5295
5296 rtl8169_init_phy(dev, tp);
5d06a99f 5297
e1759441
RW		 5298 if (netif_running(dev))
5299 __rtl8169_resume(dev);
5d06a99f 5300
e1759441
RW		 5301 return 0;
5302}
5303
5304static int rtl8169_runtime_suspend(struct device *device)
5305{
5306 struct pci_dev *pdev = to_pci_dev(device);
5307 struct net_device *dev = pci_get_drvdata(pdev);
5308 struct rtl8169_private *tp = netdev_priv(dev);
5309
5310 if (!tp->TxDescArray)
5311 return 0;
5312
5313 spin_lock_irq(&tp->lock);
5314 tp->saved_wolopts = __rtl8169_get_wol(tp);
5315 __rtl8169_set_wol(tp, WAKE_ANY);
5316 spin_unlock_irq(&tp->lock);
5317
5318 rtl8169_net_suspend(dev);
5319
5320 return 0;
5321}
5322
5323static int rtl8169_runtime_resume(struct device *device)
5324{
5325 struct pci_dev *pdev = to_pci_dev(device);
5326 struct net_device *dev = pci_get_drvdata(pdev);
5327 struct rtl8169_private *tp = netdev_priv(dev);
5328
5329 if (!tp->TxDescArray)
5330 return 0;
5331
5332 spin_lock_irq(&tp->lock);
5333 __rtl8169_set_wol(tp, tp->saved_wolopts);
5334 tp->saved_wolopts = 0;
5335 spin_unlock_irq(&tp->lock);
5336
fccec10b
SG		 5337 rtl8169_init_phy(dev, tp);
5338
e1759441 5339 __rtl8169_resume(dev);
5d06a99f 5340
5d06a99f
FR		 5341 return 0;
5342}
5343
e1759441
RW		 5344static int rtl8169_runtime_idle(struct device *device)
5345{
5346 struct pci_dev *pdev = to_pci_dev(device);
5347 struct net_device *dev = pci_get_drvdata(pdev);
5348 struct rtl8169_private *tp = netdev_priv(dev);
5349
e4fbce74 5350 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5351}
5352
47145210 5353static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5354 .suspend = rtl8169_suspend,
5355 .resume = rtl8169_resume,
5356 .freeze = rtl8169_suspend,
5357 .thaw = rtl8169_resume,
5358 .poweroff = rtl8169_suspend,
5359 .restore = rtl8169_resume,
5360 .runtime_suspend = rtl8169_runtime_suspend,
5361 .runtime_resume = rtl8169_runtime_resume,
5362 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5363};
5364
5365#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5366
5367#else /* !CONFIG_PM */
5368
5369#define RTL8169_PM_OPS NULL
5370
5371#endif /* !CONFIG_PM */
5372
1765f95d
FR		 5373static void rtl_shutdown(struct pci_dev *pdev)
5374{
861ab440 5375 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5376 struct rtl8169_private *tp = netdev_priv(dev);
5377 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5378
5379 rtl8169_net_suspend(dev);
1765f95d 5380
cecb5fd7 5381 /* Restore original MAC address */
cc098dc7
IV		 5382 rtl_rar_set(tp, dev->perm_addr);
5383
4bb3f522 5384 spin_lock_irq(&tp->lock);
5385
5386 rtl8169_asic_down(ioaddr);
5387
5388 spin_unlock_irq(&tp->lock);
5389
861ab440 5390 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5391 /* WoL fails with some 8168 when the receiver is disabled. */
5392 if (tp->features & RTL_FEATURE_WOL) {
5393 pci_clear_master(pdev);
5394
5395 RTL_W8(ChipCmd, CmdRxEnb);
5396 /* PCI commit */
5397 RTL_R8(ChipCmd);
5398 }
5399
861ab440
RW		 5400 pci_wake_from_d3(pdev, true);
5401 pci_set_power_state(pdev, PCI_D3hot);
5402 }
5403}
5d06a99f 5404
1da177e4
LT		 5405static struct pci_driver rtl8169_pci_driver = {
5406 .name = MODULENAME,
5407 .id_table = rtl8169_pci_tbl,
5408 .probe = rtl8169_init_one,
5409 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5410 .shutdown = rtl_shutdown,
861ab440 5411 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5412};
5413
07d3f51f 5414static int __init rtl8169_init_module(void)
1da177e4 5415{
29917620 5416 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5417}
5418
07d3f51f 5419static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5420{
5421 pci_unregister_driver(&rtl8169_pci_driver);
5422}
5423
5424module_init(rtl8169_init_module);
5425module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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