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signals: consolidate checks for whether or not to ignore a signal
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
66#include <linux/skbuff.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/stddef.h>
70#include <linux/ioctl.h>
71#include <linux/timex.h>
1da177e4 72#include <linux/ethtool.h>
1da177e4 73#include <linux/workqueue.h>
be3a6b02 74#include <linux/if_vlan.h>
7d3d0439
RA		 75#include <linux/ip.h>
76#include <linux/tcp.h>
77#include <net/tcp.h>
1da177e4 78
1da177e4
LT		 79#include <asm/system.h>
80#include <asm/uaccess.h>
20346722 81#include <asm/io.h>
fe931395 82#include <asm/div64.h>
330ce0de 83#include <asm/irq.h>
1da177e4
LT		 84
85/* local include */
86#include "s2io.h"
87#include "s2io-regs.h"
88
10371b5e 89#define DRV_VERSION "2.0.26.22"
6c1792f4 90
1da177e4 91/* S2io Driver name & version. */
20346722 92static char s2io_driver_name[] = "Neterion";
6c1792f4 93static char s2io_driver_version[] = DRV_VERSION;
1da177e4 94
6d517a27
VP		 95static int rxd_size[2] = {32,48};
96static int rxd_count[2] = {127,85};
da6971d8 97
1ee6dd77 98static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 99{
100 int ret;
101
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105 return ret;
106}
107
20346722 108/*
1da177e4
LT		 109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
112 */
541ae68f 113#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 117
118#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 120
92b84437
SS		 121static inline int is_s2io_card_up(const struct s2io_nic * sp)
122{
123 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
124}
125
1da177e4
LT		 126/* Ethtool related variables and Macros. */
127static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133};
134
fa1f0cb3 135static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
1da177e4 145 {"tmac_any_err_frms"},
bd1034f0 146 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
bd1034f0 161 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
1da177e4 168 {"rmac_discarded_frms"},
bd1034f0
AR		 169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
1da177e4
LT		 172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
bd1034f0
AR		 176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
bd1034f0
AR		 190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
1da177e4 207 {"rmac_pause_cnt"},
bd1034f0
AR		 208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
bd1034f0
AR		 212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
fa1f0cb3
SS		 229 {"rxf_wr_cnt"}
230};
231
232static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 233 {"rmac_ttl_1519_4095_frms"},
234 {"rmac_ttl_4096_8191_frms"},
235 {"rmac_ttl_8192_max_frms"},
236 {"rmac_ttl_gt_max_frms"},
237 {"rmac_osized_alt_frms"},
238 {"rmac_jabber_alt_frms"},
239 {"rmac_gt_max_alt_frms"},
240 {"rmac_vlan_frms"},
241 {"rmac_len_discard"},
242 {"rmac_fcs_discard"},
243 {"rmac_pf_discard"},
244 {"rmac_da_discard"},
245 {"rmac_red_discard"},
246 {"rmac_rts_discard"},
247 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 248 {"link_fault_cnt"}
249};
250
251static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 252 {"\n DRIVER STATISTICS"},
253 {"single_bit_ecc_errs"},
254 {"double_bit_ecc_errs"},
bd1034f0
AR		 255 {"parity_err_cnt"},
256 {"serious_err_cnt"},
257 {"soft_reset_cnt"},
258 {"fifo_full_cnt"},
8116f3cf
SS		 259 {"ring_0_full_cnt"},
260 {"ring_1_full_cnt"},
261 {"ring_2_full_cnt"},
262 {"ring_3_full_cnt"},
263 {"ring_4_full_cnt"},
264 {"ring_5_full_cnt"},
265 {"ring_6_full_cnt"},
266 {"ring_7_full_cnt"},
43b7c451
SH		 267 {"alarm_transceiver_temp_high"},
268 {"alarm_transceiver_temp_low"},
269 {"alarm_laser_bias_current_high"},
270 {"alarm_laser_bias_current_low"},
271 {"alarm_laser_output_power_high"},
272 {"alarm_laser_output_power_low"},
273 {"warn_transceiver_temp_high"},
274 {"warn_transceiver_temp_low"},
275 {"warn_laser_bias_current_high"},
276 {"warn_laser_bias_current_low"},
277 {"warn_laser_output_power_high"},
278 {"warn_laser_output_power_low"},
279 {"lro_aggregated_pkts"},
280 {"lro_flush_both_count"},
281 {"lro_out_of_sequence_pkts"},
282 {"lro_flush_due_to_max_pkts"},
283 {"lro_avg_aggr_pkts"},
284 {"mem_alloc_fail_cnt"},
285 {"pci_map_fail_cnt"},
286 {"watchdog_timer_cnt"},
287 {"mem_allocated"},
288 {"mem_freed"},
289 {"link_up_cnt"},
290 {"link_down_cnt"},
291 {"link_up_time"},
292 {"link_down_time"},
293 {"tx_tcode_buf_abort_cnt"},
294 {"tx_tcode_desc_abort_cnt"},
295 {"tx_tcode_parity_err_cnt"},
296 {"tx_tcode_link_loss_cnt"},
297 {"tx_tcode_list_proc_err_cnt"},
298 {"rx_tcode_parity_err_cnt"},
299 {"rx_tcode_abort_cnt"},
300 {"rx_tcode_parity_abort_cnt"},
301 {"rx_tcode_rda_fail_cnt"},
302 {"rx_tcode_unkn_prot_cnt"},
303 {"rx_tcode_fcs_err_cnt"},
304 {"rx_tcode_buf_size_err_cnt"},
305 {"rx_tcode_rxd_corrupt_cnt"},
306 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 307 {"tda_err_cnt"},
308 {"pfc_err_cnt"},
309 {"pcc_err_cnt"},
310 {"tti_err_cnt"},
311 {"tpa_err_cnt"},
312 {"sm_err_cnt"},
313 {"lso_err_cnt"},
314 {"mac_tmac_err_cnt"},
315 {"mac_rmac_err_cnt"},
316 {"xgxs_txgxs_err_cnt"},
317 {"xgxs_rxgxs_err_cnt"},
318 {"rc_err_cnt"},
319 {"prc_pcix_err_cnt"},
320 {"rpa_err_cnt"},
321 {"rda_err_cnt"},
322 {"rti_err_cnt"},
323 {"mc_err_cnt"}
1da177e4
LT		 324};
325
4c3616cd
AMR		 326#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
327#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
328#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 329
330#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
331#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
332
333#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
334#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 335
4c3616cd 336#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 337#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
338
25fff88e 339#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
340 init_timer(&timer); \
341 timer.function = handle; \
342 timer.data = (unsigned long) arg; \
343 mod_timer(&timer, (jiffies + exp)) \
344
2fd37688
SS		 345/* copy mac addr to def_mac_addr array */
346static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
347{
348 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
349 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
350 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
351 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
352 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
353 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
354}
be3a6b02 355/* Add the vlan */
356static void s2io_vlan_rx_register(struct net_device *dev,
357 struct vlan_group *grp)
358{
2fda096d 359 int i;
1ee6dd77 360 struct s2io_nic *nic = dev->priv;
2fda096d
SR		 361 unsigned long flags[MAX_TX_FIFOS];
362 struct mac_info *mac_control = &nic->mac_control;
363 struct config_param *config = &nic->config;
364
365 for (i = 0; i < config->tx_fifo_num; i++)
366 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
be3a6b02 367
be3a6b02 368 nic->vlgrp = grp;
2fda096d
SR		 369 for (i = config->tx_fifo_num - 1; i >= 0; i--)
370 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
371 flags[i]);
be3a6b02 372}
373
926930b2 374/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 375static int vlan_strip_flag;
926930b2 376
cdb5bf02
SH		 377/* Unregister the vlan */
378static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
379{
380 int i;
381 struct s2io_nic *nic = dev->priv;
382 unsigned long flags[MAX_TX_FIFOS];
383 struct mac_info *mac_control = &nic->mac_control;
384 struct config_param *config = &nic->config;
385
386 for (i = 0; i < config->tx_fifo_num; i++)
387 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
388
389 if (nic->vlgrp)
390 vlan_group_set_device(nic->vlgrp, vid, NULL);
391
392 for (i = config->tx_fifo_num - 1; i >= 0; i--)
393 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
394 flags[i]);
395}
396
20346722 397/*
1da177e4
LT		 398 * Constants to be programmed into the Xena's registers, to configure
399 * the XAUI.
400 */
401
1da177e4 402#define END_SIGN 0x0
f71e1309 403static const u64 herc_act_dtx_cfg[] = {
541ae68f 404 /* Set address */
e960fc5c 405 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 406 /* Write data */
e960fc5c 407 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 408 /* Set address */
409 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
410 /* Write data */
411 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
412 /* Set address */
e960fc5c 413 0x801205150D440000ULL, 0x801205150D4400E0ULL,
414 /* Write data */
415 0x801205150D440004ULL, 0x801205150D4400E4ULL,
416 /* Set address */
541ae68f 417 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
418 /* Write data */
419 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
420 /* Done */
421 END_SIGN
422};
423
f71e1309 424static const u64 xena_dtx_cfg[] = {
c92ca04b 425 /* Set address */
1da177e4 426 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 427 /* Write data */
428 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
429 /* Set address */
430 0x8001051500000000ULL, 0x80010515000000E0ULL,
431 /* Write data */
432 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
433 /* Set address */
1da177e4 434 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 435 /* Write data */
436 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 437 END_SIGN
438};
439
20346722 440/*
1da177e4
LT		 441 * Constants for Fixing the MacAddress problem seen mostly on
442 * Alpha machines.
443 */
f71e1309 444static const u64 fix_mac[] = {
1da177e4
LT		 445 0x0060000000000000ULL, 0x0060600000000000ULL,
446 0x0040600000000000ULL, 0x0000600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0060600000000000ULL,
450 0x0020600000000000ULL, 0x0060600000000000ULL,
451 0x0020600000000000ULL, 0x0060600000000000ULL,
452 0x0020600000000000ULL, 0x0060600000000000ULL,
453 0x0020600000000000ULL, 0x0060600000000000ULL,
454 0x0020600000000000ULL, 0x0060600000000000ULL,
455 0x0020600000000000ULL, 0x0060600000000000ULL,
456 0x0020600000000000ULL, 0x0060600000000000ULL,
457 0x0020600000000000ULL, 0x0000600000000000ULL,
458 0x0040600000000000ULL, 0x0060600000000000ULL,
459 END_SIGN
460};
461
b41477f3
AR		 462MODULE_LICENSE("GPL");
463MODULE_VERSION(DRV_VERSION);
464
465
1da177e4 466/* Module Loadable parameters. */
6cfc482b 467S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 468S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 469S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 470S2IO_PARM_INT(rx_ring_mode, 1);
471S2IO_PARM_INT(use_continuous_tx_intrs, 1);
472S2IO_PARM_INT(rmac_pause_time, 0x100);
473S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
474S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
475S2IO_PARM_INT(shared_splits, 0);
476S2IO_PARM_INT(tmac_util_period, 5);
477S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 478S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 479/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
480S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 481/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 482S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 483/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 484S2IO_PARM_INT(intr_type, 2);
7d3d0439 485/* Large receive offload feature */
43b7c451
SH		 486static unsigned int lro_enable;
487module_param_named(lro, lro_enable, uint, 0);
488
7d3d0439
RA		 489/* Max pkts to be aggregated by LRO at one time. If not specified,
490 * aggregation happens until we hit max IP pkt size(64K)
491 */
b41477f3 492S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 493S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 494
495S2IO_PARM_INT(napi, 1);
496S2IO_PARM_INT(ufo, 0);
926930b2 497S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 498
499static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
500 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
501static unsigned int rx_ring_sz[MAX_RX_RINGS] =
502 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
503static unsigned int rts_frm_len[MAX_RX_RINGS] =
504 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
505
506module_param_array(tx_fifo_len, uint, NULL, 0);
507module_param_array(rx_ring_sz, uint, NULL, 0);
508module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 509
20346722 510/*
1da177e4 511 * S2IO device table.
20346722 512 * This table lists all the devices that this driver supports.
1da177e4
LT		 513 */
514static struct pci_device_id s2io_tbl[] __devinitdata = {
515 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
516 PCI_ANY_ID, PCI_ANY_ID},
517 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
518 PCI_ANY_ID, PCI_ANY_ID},
519 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722 520 PCI_ANY_ID, PCI_ANY_ID},
521 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
522 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 523 {0,}
524};
525
526MODULE_DEVICE_TABLE(pci, s2io_tbl);
527
d796fdb7
LV		 528static struct pci_error_handlers s2io_err_handler = {
529 .error_detected = s2io_io_error_detected,
530 .slot_reset = s2io_io_slot_reset,
531 .resume = s2io_io_resume,
532};
533
1da177e4
LT		 534static struct pci_driver s2io_driver = {
535 .name = "S2IO",
536 .id_table = s2io_tbl,
537 .probe = s2io_init_nic,
538 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 539 .err_handler = &s2io_err_handler,
1da177e4
LT		 540};
541
542/* A simplifier macro used both by init and free shared_mem Fns(). */
543#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
544
3a3d5756
SH		 545/* netqueue manipulation helper functions */
546static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
547{
548 int i;
549#ifdef CONFIG_NETDEVICES_MULTIQUEUE
550 if (sp->config.multiq) {
551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 netif_stop_subqueue(sp->dev, i);
553 } else
554#endif
555 {
556 for (i = 0; i < sp->config.tx_fifo_num; i++)
557 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
558 netif_stop_queue(sp->dev);
559 }
560}
561
562static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
563{
564#ifdef CONFIG_NETDEVICES_MULTIQUEUE
565 if (sp->config.multiq)
566 netif_stop_subqueue(sp->dev, fifo_no);
567 else
568#endif
569 {
570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
572 netif_stop_queue(sp->dev);
573 }
574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
578 int i;
579#ifdef CONFIG_NETDEVICES_MULTIQUEUE
580 if (sp->config.multiq) {
581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 netif_start_subqueue(sp->dev, i);
583 } else
584#endif
585 {
586 for (i = 0; i < sp->config.tx_fifo_num; i++)
587 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
588 netif_start_queue(sp->dev);
589 }
590}
591
592static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
593{
594#ifdef CONFIG_NETDEVICES_MULTIQUEUE
595 if (sp->config.multiq)
596 netif_start_subqueue(sp->dev, fifo_no);
597 else
598#endif
599 {
600 sp->mac_control.fifos[fifo_no].queue_state =
601 FIFO_QUEUE_START;
602 netif_start_queue(sp->dev);
603 }
604}
605
606static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
607{
608 int i;
609#ifdef CONFIG_NETDEVICES_MULTIQUEUE
610 if (sp->config.multiq) {
611 for (i = 0; i < sp->config.tx_fifo_num; i++)
612 netif_wake_subqueue(sp->dev, i);
613 } else
614#endif
615 {
616 for (i = 0; i < sp->config.tx_fifo_num; i++)
617 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
618 netif_wake_queue(sp->dev);
619 }
620}
621
622static inline void s2io_wake_tx_queue(
623 struct fifo_info *fifo, int cnt, u8 multiq)
624{
625
626#ifdef CONFIG_NETDEVICES_MULTIQUEUE
627 if (multiq) {
628 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
629 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
630 } else
631#endif
632 if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
633 if (netif_queue_stopped(fifo->dev)) {
634 fifo->queue_state = FIFO_QUEUE_START;
635 netif_wake_queue(fifo->dev);
636 }
637 }
638}
639
1da177e4
LT		 640/**
641 * init_shared_mem - Allocation and Initialization of Memory
642 * @nic: Device private variable.
20346722 643 * Description: The function allocates all the memory areas shared
644 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 645 * Rx descriptors and the statistics block.
646 */
647
648static int init_shared_mem(struct s2io_nic *nic)
649{
650 u32 size;
651 void *tmp_v_addr, *tmp_v_addr_next;
652 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 653 struct RxD_block *pre_rxd_blk = NULL;
372cc597 654 int i, j, blk_cnt;
1da177e4
LT		 655 int lst_size, lst_per_page;
656 struct net_device *dev = nic->dev;
8ae418cf 657 unsigned long tmp;
1ee6dd77 658 struct buffAdd *ba;
1da177e4 659
1ee6dd77 660 struct mac_info *mac_control;
1da177e4 661 struct config_param *config;
491976b2 662 unsigned long long mem_allocated = 0;
1da177e4
LT		 663
664 mac_control = &nic->mac_control;
665 config = &nic->config;
666
667
668 /* Allocation and initialization of TXDLs in FIOFs */
669 size = 0;
670 for (i = 0; i < config->tx_fifo_num; i++) {
671 size += config->tx_cfg[i].fifo_len;
672 }
673 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 674 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 675 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 676 return -EINVAL;
1da177e4
LT		 677 }
678
2fda096d
SR		 679 size = 0;
680 for (i = 0; i < config->tx_fifo_num; i++) {
681 size = config->tx_cfg[i].fifo_len;
682 /*
683 * Legal values are from 2 to 8192
684 */
685 if (size < 2) {
686 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
687 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
688 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
689 "are 2 to 8192\n");
690 return -EINVAL;
691 }
692 }
693
1ee6dd77 694 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 695 lst_per_page = PAGE_SIZE / lst_size;
696
697 for (i = 0; i < config->tx_fifo_num; i++) {
698 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 699 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 700 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722 701 GFP_KERNEL);
702 if (!mac_control->fifos[i].list_info) {
0c61ed5f 703 DBG_PRINT(INFO_DBG,
1da177e4
LT		 704 "Malloc failed for list_info\n");
705 return -ENOMEM;
706 }
491976b2 707 mem_allocated += list_holder_size;
1da177e4
LT		 708 }
709 for (i = 0; i < config->tx_fifo_num; i++) {
710 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
711 lst_per_page);
20346722 712 mac_control->fifos[i].tx_curr_put_info.offset = 0;
713 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 714 config->tx_cfg[i].fifo_len - 1;
20346722 715 mac_control->fifos[i].tx_curr_get_info.offset = 0;
716 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 717 config->tx_cfg[i].fifo_len - 1;
20346722 718 mac_control->fifos[i].fifo_no = i;
719 mac_control->fifos[i].nic = nic;
fed5eccd 720 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
3a3d5756 721 mac_control->fifos[i].dev = dev;
20346722 722
1da177e4
LT		 723 for (j = 0; j < page_num; j++) {
724 int k = 0;
725 dma_addr_t tmp_p;
726 void *tmp_v;
727 tmp_v = pci_alloc_consistent(nic->pdev,
728 PAGE_SIZE, &tmp_p);
729 if (!tmp_v) {
0c61ed5f 730 DBG_PRINT(INFO_DBG,
1da177e4 731 "pci_alloc_consistent ");
0c61ed5f 732 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 733 return -ENOMEM;
734 }
776bd20f 735 /* If we got a zero DMA address(can happen on
736 * certain platforms like PPC), reallocate.
737 * Store virtual address of page we don't want,
738 * to be freed later.
739 */
740 if (!tmp_p) {
741 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 742 DBG_PRINT(INIT_DBG,
776bd20f 743 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 744 DBG_PRINT(INIT_DBG,
6b4d617d 745 "Virtual address %p\n", tmp_v);
776bd20f 746 tmp_v = pci_alloc_consistent(nic->pdev,
747 PAGE_SIZE, &tmp_p);
748 if (!tmp_v) {
0c61ed5f 749 DBG_PRINT(INFO_DBG,
776bd20f 750 "pci_alloc_consistent ");
0c61ed5f 751 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 752 return -ENOMEM;
753 }
491976b2 754 mem_allocated += PAGE_SIZE;
776bd20f 755 }
1da177e4
LT		 756 while (k < lst_per_page) {
757 int l = (j * lst_per_page) + k;
758 if (l == config->tx_cfg[i].fifo_len)
20346722 759 break;
760 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 761 tmp_v + (k * lst_size);
20346722 762 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 763 tmp_p + (k * lst_size);
764 k++;
765 }
766 }
767 }
1da177e4 768
2fda096d
SR		 769 for (i = 0; i < config->tx_fifo_num; i++) {
770 size = config->tx_cfg[i].fifo_len;
771 mac_control->fifos[i].ufo_in_band_v
772 = kcalloc(size, sizeof(u64), GFP_KERNEL);
773 if (!mac_control->fifos[i].ufo_in_band_v)
774 return -ENOMEM;
775 mem_allocated += (size * sizeof(u64));
776 }
fed5eccd 777
1da177e4
LT		 778 /* Allocation and initialization of RXDs in Rings */
779 size = 0;
780 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 781 if (config->rx_cfg[i].num_rxd %
782 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 783 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
784 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
785 i);
786 DBG_PRINT(ERR_DBG, "RxDs per Block");
787 return FAILURE;
788 }
789 size += config->rx_cfg[i].num_rxd;
20346722 790 mac_control->rings[i].block_count =
da6971d8
AR		 791 config->rx_cfg[i].num_rxd /
792 (rxd_count[nic->rxd_mode] + 1 );
793 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
794 mac_control->rings[i].block_count;
1da177e4 795 }
da6971d8 796 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 797 size = (size * (sizeof(struct RxD1)));
da6971d8 798 else
1ee6dd77 799 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 800
801 for (i = 0; i < config->rx_ring_num; i++) {
20346722 802 mac_control->rings[i].rx_curr_get_info.block_index = 0;
803 mac_control->rings[i].rx_curr_get_info.offset = 0;
804 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 805 config->rx_cfg[i].num_rxd - 1;
20346722 806 mac_control->rings[i].rx_curr_put_info.block_index = 0;
807 mac_control->rings[i].rx_curr_put_info.offset = 0;
808 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 809 config->rx_cfg[i].num_rxd - 1;
20346722 810 mac_control->rings[i].nic = nic;
811 mac_control->rings[i].ring_no = i;
812
da6971d8
AR		 813 blk_cnt = config->rx_cfg[i].num_rxd /
814 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 815 /* Allocating all the Rx blocks */
816 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 817 struct rx_block_info *rx_blocks;
da6971d8
AR		 818 int l;
819
820 rx_blocks = &mac_control->rings[i].rx_blocks[j];
821 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 822 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
823 &tmp_p_addr);
824 if (tmp_v_addr == NULL) {
825 /*
20346722 826 * In case of failure, free_shared_mem()
827 * is called, which should free any
828 * memory that was alloced till the
1da177e4
LT		 829 * failure happened.
830 */
da6971d8 831 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 832 return -ENOMEM;
833 }
491976b2 834 mem_allocated += size;
1da177e4 835 memset(tmp_v_addr, 0, size);
da6971d8
AR		 836 rx_blocks->block_virt_addr = tmp_v_addr;
837 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 838 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 839 rxd_count[nic->rxd_mode],
840 GFP_KERNEL);
372cc597
SS		 841 if (!rx_blocks->rxds)
842 return -ENOMEM;
8a4bdbaa 843 mem_allocated +=
491976b2 844 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 845 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
846 rx_blocks->rxds[l].virt_addr =
847 rx_blocks->block_virt_addr +
848 (rxd_size[nic->rxd_mode] * l);
849 rx_blocks->rxds[l].dma_addr =
850 rx_blocks->block_dma_addr +
851 (rxd_size[nic->rxd_mode] * l);
852 }
1da177e4
LT		 853 }
854 /* Interlinking all Rx Blocks */
855 for (j = 0; j < blk_cnt; j++) {
20346722 856 tmp_v_addr =
857 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 858 tmp_v_addr_next =
20346722 859 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 860 blk_cnt].block_virt_addr;
20346722 861 tmp_p_addr =
862 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 863 tmp_p_addr_next =
20346722 864 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 865 blk_cnt].block_dma_addr;
866
1ee6dd77 867 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 868 pre_rxd_blk->reserved_2_pNext_RxD_block =
869 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 870 pre_rxd_blk->pNext_RxD_Blk_physical =
871 (u64) tmp_p_addr_next;
872 }
873 }
6d517a27 874 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 875 /*
876 * Allocation of Storages for buffer addresses in 2BUFF mode
877 * and the buffers as well.
878 */
879 for (i = 0; i < config->rx_ring_num; i++) {
880 blk_cnt = config->rx_cfg[i].num_rxd /
881 (rxd_count[nic->rxd_mode]+ 1);
882 mac_control->rings[i].ba =
1ee6dd77 883 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 884 GFP_KERNEL);
da6971d8 885 if (!mac_control->rings[i].ba)
1da177e4 886 return -ENOMEM;
491976b2 887 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 888 for (j = 0; j < blk_cnt; j++) {
889 int k = 0;
890 mac_control->rings[i].ba[j] =
1ee6dd77 891 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 892 (rxd_count[nic->rxd_mode] + 1)),
893 GFP_KERNEL);
894 if (!mac_control->rings[i].ba[j])
1da177e4 895 return -ENOMEM;
491976b2
SH		 896 mem_allocated += (sizeof(struct buffAdd) * \
897 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 898 while (k != rxd_count[nic->rxd_mode]) {
899 ba = &mac_control->rings[i].ba[j][k];
900
901 ba->ba_0_org = (void *) kmalloc
902 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
903 if (!ba->ba_0_org)
904 return -ENOMEM;
8a4bdbaa 905 mem_allocated +=
491976b2 906 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 907 tmp = (unsigned long)ba->ba_0_org;
908 tmp += ALIGN_SIZE;
909 tmp &= ~((unsigned long) ALIGN_SIZE);
910 ba->ba_0 = (void *) tmp;
911
912 ba->ba_1_org = (void *) kmalloc
913 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
914 if (!ba->ba_1_org)
915 return -ENOMEM;
8a4bdbaa 916 mem_allocated
491976b2 917 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 918 tmp = (unsigned long) ba->ba_1_org;
919 tmp += ALIGN_SIZE;
920 tmp &= ~((unsigned long) ALIGN_SIZE);
921 ba->ba_1 = (void *) tmp;
922 k++;
923 }
1da177e4
LT		 924 }
925 }
926 }
1da177e4
LT		 927
928 /* Allocation and initialization of Statistics block */
1ee6dd77 929 size = sizeof(struct stat_block);
1da177e4
LT		 930 mac_control->stats_mem = pci_alloc_consistent
931 (nic->pdev, size, &mac_control->stats_mem_phy);
932
933 if (!mac_control->stats_mem) {
20346722 934 /*
935 * In case of failure, free_shared_mem() is called, which
936 * should free any memory that was alloced till the
1da177e4
LT		 937 * failure happened.
938 */
939 return -ENOMEM;
940 }
491976b2 941 mem_allocated += size;
1da177e4
LT		 942 mac_control->stats_mem_sz = size;
943
944 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 945 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 946 memset(tmp_v_addr, 0, size);
1da177e4
LT		 947 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
948 (unsigned long long) tmp_p_addr);
491976b2 949 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 950 return SUCCESS;
951}
952
20346722 953/**
954 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 955 * @nic: Device private variable.
956 * Description: This function is to free all memory locations allocated by
957 * the init_shared_mem() function and return it to the kernel.
958 */
959
960static void free_shared_mem(struct s2io_nic *nic)
961{
962 int i, j, blk_cnt, size;
963 void *tmp_v_addr;
964 dma_addr_t tmp_p_addr;
1ee6dd77 965 struct mac_info *mac_control;
1da177e4
LT		 966 struct config_param *config;
967 int lst_size, lst_per_page;
8910b49f 968 struct net_device *dev;
491976b2 969 int page_num = 0;
1da177e4
LT		 970
971 if (!nic)
972 return;
973
8910b49f
MG		 974 dev = nic->dev;
975
1da177e4
LT		 976 mac_control = &nic->mac_control;
977 config = &nic->config;
978
1ee6dd77 979 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 980 lst_per_page = PAGE_SIZE / lst_size;
981
982 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 983 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
984 lst_per_page);
1da177e4
LT		 985 for (j = 0; j < page_num; j++) {
986 int mem_blks = (j * lst_per_page);
776bd20f 987 if (!mac_control->fifos[i].list_info)
6aa20a22 988 return;
776bd20f 989 if (!mac_control->fifos[i].list_info[mem_blks].
990 list_virt_addr)
1da177e4
LT		 991 break;
992 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722 993 mac_control->fifos[i].
994 list_info[mem_blks].
1da177e4 995 list_virt_addr,
20346722 996 mac_control->fifos[i].
997 list_info[mem_blks].
1da177e4 998 list_phy_addr);
8a4bdbaa 999 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 1000 += PAGE_SIZE;
1da177e4 1001 }
776bd20f 1002 /* If we got a zero DMA address during allocation,
1003 * free the page now
1004 */
1005 if (mac_control->zerodma_virt_addr) {
1006 pci_free_consistent(nic->pdev, PAGE_SIZE,
1007 mac_control->zerodma_virt_addr,
1008 (dma_addr_t)0);
6aa20a22 1009 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 1010 "%s: Freeing TxDL with zero DMA addr. ",
1011 dev->name);
1012 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1013 mac_control->zerodma_virt_addr);
8a4bdbaa 1014 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 1015 += PAGE_SIZE;
776bd20f 1016 }
20346722 1017 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 1018 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1019 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 1020 }
1021
1da177e4 1022 size = SIZE_OF_BLOCK;
1da177e4 1023 for (i = 0; i < config->rx_ring_num; i++) {
20346722 1024 blk_cnt = mac_control->rings[i].block_count;
1da177e4 1025 for (j = 0; j < blk_cnt; j++) {
20346722 1026 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1027 block_virt_addr;
1028 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1029 block_dma_addr;
1da177e4
LT		 1030 if (tmp_v_addr == NULL)
1031 break;
1032 pci_free_consistent(nic->pdev, size,
1033 tmp_v_addr, tmp_p_addr);
491976b2 1034 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 1035 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 1036 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1037 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1038 }
1039 }
1040
6d517a27 1041 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1042 /* Freeing buffer storage addresses in 2BUFF mode. */
1043 for (i = 0; i < config->rx_ring_num; i++) {
1044 blk_cnt = config->rx_cfg[i].num_rxd /
1045 (rxd_count[nic->rxd_mode] + 1);
1046 for (j = 0; j < blk_cnt; j++) {
1047 int k = 0;
1048 if (!mac_control->rings[i].ba[j])
1049 continue;
1050 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 1051 struct buffAdd *ba =
da6971d8
AR		 1052 &mac_control->rings[i].ba[j][k];
1053 kfree(ba->ba_0_org);
491976b2
SH		 1054 nic->mac_control.stats_info->sw_stat.\
1055 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1056 kfree(ba->ba_1_org);
491976b2
SH		 1057 nic->mac_control.stats_info->sw_stat.\
1058 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1059 k++;
1060 }
1061 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 1062 nic->mac_control.stats_info->sw_stat.mem_freed +=
1063 (sizeof(struct buffAdd) *
1064 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1065 }
da6971d8 1066 kfree(mac_control->rings[i].ba);
8a4bdbaa 1067 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1068 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1069 }
1da177e4 1070 }
1da177e4 1071
2fda096d
SR		 1072 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1073 if (mac_control->fifos[i].ufo_in_band_v) {
1074 nic->mac_control.stats_info->sw_stat.mem_freed
1075 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1076 kfree(mac_control->fifos[i].ufo_in_band_v);
1077 }
1078 }
1079
1da177e4 1080 if (mac_control->stats_mem) {
2fda096d
SR		 1081 nic->mac_control.stats_info->sw_stat.mem_freed +=
1082 mac_control->stats_mem_sz;
1da177e4
LT		 1083 pci_free_consistent(nic->pdev,
1084 mac_control->stats_mem_sz,
1085 mac_control->stats_mem,
1086 mac_control->stats_mem_phy);
491976b2 1087 }
1da177e4
LT		 1088}
1089
541ae68f 1090/**
1091 * s2io_verify_pci_mode -
1092 */
1093
1ee6dd77 1094static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1095{
1ee6dd77 1096 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1097 register u64 val64 = 0;
1098 int mode;
1099
1100 val64 = readq(&bar0->pci_mode);
1101 mode = (u8)GET_PCI_MODE(val64);
1102
1103 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1104 return -1; /* Unknown PCI mode */
1105 return mode;
1106}
1107
c92ca04b
AR		 1108#define NEC_VENID 0x1033
1109#define NEC_DEVID 0x0125
1110static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1111{
1112 struct pci_dev *tdev = NULL;
26d36b64
AC		 1113 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1114 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 1115 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 1116 pci_dev_put(tdev);
c92ca04b
AR		 1117 return 1;
1118 }
1119 }
1120 return 0;
1121}
541ae68f 1122
7b32a312 1123static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1124/**
1125 * s2io_print_pci_mode -
1126 */
1ee6dd77 1127static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1128{
1ee6dd77 1129 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1130 register u64 val64 = 0;
1131 int mode;
1132 struct config_param *config = &nic->config;
1133
1134 val64 = readq(&bar0->pci_mode);
1135 mode = (u8)GET_PCI_MODE(val64);
1136
1137 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1138 return -1; /* Unknown PCI mode */
1139
c92ca04b
AR		 1140 config->bus_speed = bus_speed[mode];
1141
1142 if (s2io_on_nec_bridge(nic->pdev)) {
1143 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1144 nic->dev->name);
1145 return mode;
1146 }
1147
541ae68f 1148 if (val64 & PCI_MODE_32_BITS) {
1149 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1150 } else {
1151 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1152 }
1153
1154 switch(mode) {
1155 case PCI_MODE_PCI_33:
1156 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f 1157 break;
1158 case PCI_MODE_PCI_66:
1159 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f 1160 break;
1161 case PCI_MODE_PCIX_M1_66:
1162 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f 1163 break;
1164 case PCI_MODE_PCIX_M1_100:
1165 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f 1166 break;
1167 case PCI_MODE_PCIX_M1_133:
1168 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f 1169 break;
1170 case PCI_MODE_PCIX_M2_66:
1171 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f 1172 break;
1173 case PCI_MODE_PCIX_M2_100:
1174 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f 1175 break;
1176 case PCI_MODE_PCIX_M2_133:
1177 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f 1178 break;
1179 default:
1180 return -1; /* Unsupported bus speed */
1181 }
1182
1183 return mode;
1184}
1185
b7c5678f
RV		 1186/**
1187 * init_tti - Initialization transmit traffic interrupt scheme
1188 * @nic: device private variable
1189 * @link: link status (UP/DOWN) used to enable/disable continuous
1190 * transmit interrupts
1191 * Description: The function configures transmit traffic interrupts
1192 * Return Value: SUCCESS on success and
1193 * '-1' on failure
1194 */
1195
0d66afe7 1196static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1197{
1198 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1199 register u64 val64 = 0;
1200 int i;
1201 struct config_param *config;
1202
1203 config = &nic->config;
1204
1205 for (i = 0; i < config->tx_fifo_num; i++) {
1206 /*
1207 * TTI Initialization. Default Tx timer gets us about
1208 * 250 interrupts per sec. Continuous interrupts are enabled
1209 * by default.
1210 */
1211 if (nic->device_type == XFRAME_II_DEVICE) {
1212 int count = (nic->config.bus_speed * 125)/2;
1213 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1214 } else
1215 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1216
1217 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1218 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1219 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1220 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1221
1222 if (use_continuous_tx_intrs && (link == LINK_UP))
1223 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1224 writeq(val64, &bar0->tti_data1_mem);
1225
1226 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1227 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1228 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1229 TTI_DATA2_MEM_TX_UFC_D(0x80);
1230
1231 writeq(val64, &bar0->tti_data2_mem);
1232
1233 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1234 TTI_CMD_MEM_OFFSET(i);
1235 writeq(val64, &bar0->tti_command_mem);
1236
1237 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1238 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1239 return FAILURE;
1240 }
1241
1242 return SUCCESS;
1243}
1244
20346722 1245/**
1246 * init_nic - Initialization of hardware
b7c5678f 1247 * @nic: device private variable
20346722 1248 * Description: The function sequentially configures every block
1249 * of the H/W from their reset values.
1250 * Return Value: SUCCESS on success and
1da177e4
LT		 1251 * '-1' on failure (endian settings incorrect).
1252 */
1253
1254static int init_nic(struct s2io_nic *nic)
1255{
1ee6dd77 1256 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1257 struct net_device *dev = nic->dev;
1258 register u64 val64 = 0;
1259 void __iomem *add;
1260 u32 time;
1261 int i, j;
1ee6dd77 1262 struct mac_info *mac_control;
1da177e4 1263 struct config_param *config;
c92ca04b 1264 int dtx_cnt = 0;
1da177e4 1265 unsigned long long mem_share;
20346722 1266 int mem_size;
1da177e4
LT		 1267
1268 mac_control = &nic->mac_control;
1269 config = &nic->config;
1270
5e25b9dd 1271 /* to set the swapper controle on the card */
20346722 1272 if(s2io_set_swapper(nic)) {
1da177e4 1273 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1274 return -EIO;
1da177e4
LT		 1275 }
1276
541ae68f 1277 /*
1278 * Herc requires EOI to be removed from reset before XGXS, so..
1279 */
1280 if (nic->device_type & XFRAME_II_DEVICE) {
1281 val64 = 0xA500000000ULL;
1282 writeq(val64, &bar0->sw_reset);
1283 msleep(500);
1284 val64 = readq(&bar0->sw_reset);
1285 }
1286
1da177e4
LT		 1287 /* Remove XGXS from reset state */
1288 val64 = 0;
1289 writeq(val64, &bar0->sw_reset);
1da177e4 1290 msleep(500);
20346722 1291 val64 = readq(&bar0->sw_reset);
1da177e4 1292
7962024e
SH		 1293 /* Ensure that it's safe to access registers by checking
1294 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1295 */
1296 if (nic->device_type == XFRAME_II_DEVICE) {
1297 for (i = 0; i < 50; i++) {
1298 val64 = readq(&bar0->adapter_status);
1299 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1300 break;
1301 msleep(10);
1302 }
1303 if (i == 50)
1304 return -ENODEV;
1305 }
1306
1da177e4
LT		 1307 /* Enable Receiving broadcasts */
1308 add = &bar0->mac_cfg;
1309 val64 = readq(&bar0->mac_cfg);
1310 val64 |= MAC_RMAC_BCAST_ENABLE;
1311 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1312 writel((u32) val64, add);
1313 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1314 writel((u32) (val64 >> 32), (add + 4));
1315
1316 /* Read registers in all blocks */
1317 val64 = readq(&bar0->mac_int_mask);
1318 val64 = readq(&bar0->mc_int_mask);
1319 val64 = readq(&bar0->xgxs_int_mask);
1320
1321 /* Set MTU */
1322 val64 = dev->mtu;
1323 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1324
541ae68f 1325 if (nic->device_type & XFRAME_II_DEVICE) {
1326 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1327 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1328 &bar0->dtx_control, UF);
541ae68f 1329 if (dtx_cnt & 0x1)
1330 msleep(1); /* Necessary!! */
1da177e4
LT		 1331 dtx_cnt++;
1332 }
541ae68f 1333 } else {
c92ca04b
AR		 1334 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1335 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1336 &bar0->dtx_control, UF);
1337 val64 = readq(&bar0->dtx_control);
1338 dtx_cnt++;
1da177e4
LT		 1339 }
1340 }
1341
1342 /* Tx DMA Initialization */
1343 val64 = 0;
1344 writeq(val64, &bar0->tx_fifo_partition_0);
1345 writeq(val64, &bar0->tx_fifo_partition_1);
1346 writeq(val64, &bar0->tx_fifo_partition_2);
1347 writeq(val64, &bar0->tx_fifo_partition_3);
1348
1349
1350 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1351 val64 |=
b7c5678f 1352 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1da177e4 1353 13) | vBIT(config->tx_cfg[i].fifo_priority,
b7c5678f 1354 ((j * 32) + 5), 3);
1da177e4
LT		 1355
1356 if (i == (config->tx_fifo_num - 1)) {
1357 if (i % 2 == 0)
1358 i++;
1359 }
1360
1361 switch (i) {
1362 case 1:
1363 writeq(val64, &bar0->tx_fifo_partition_0);
1364 val64 = 0;
b7c5678f 1365 j = 0;
1da177e4
LT		 1366 break;
1367 case 3:
1368 writeq(val64, &bar0->tx_fifo_partition_1);
1369 val64 = 0;
b7c5678f 1370 j = 0;
1da177e4
LT		 1371 break;
1372 case 5:
1373 writeq(val64, &bar0->tx_fifo_partition_2);
1374 val64 = 0;
b7c5678f 1375 j = 0;
1da177e4
LT		 1376 break;
1377 case 7:
1378 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1379 val64 = 0;
1380 j = 0;
1381 break;
1382 default:
1383 j++;
1da177e4
LT		 1384 break;
1385 }
1386 }
1387
5e25b9dd 1388 /*
1389 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1390 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1391 */
541ae68f 1392 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1393 (nic->pdev->revision < 4))
5e25b9dd 1394 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1395
1da177e4
LT		 1396 val64 = readq(&bar0->tx_fifo_partition_0);
1397 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1398 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1399
20346722 1400 /*
1401 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1402 * integrity checking.
1403 */
1404 val64 = readq(&bar0->tx_pa_cfg);
1405 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1406 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1407 writeq(val64, &bar0->tx_pa_cfg);
1408
1409 /* Rx DMA intialization. */
1410 val64 = 0;
1411 for (i = 0; i < config->rx_ring_num; i++) {
1412 val64 |=
1413 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1414 3);
1415 }
1416 writeq(val64, &bar0->rx_queue_priority);
1417
20346722 1418 /*
1419 * Allocating equal share of memory to all the
1da177e4
LT		 1420 * configured Rings.
1421 */
1422 val64 = 0;
541ae68f 1423 if (nic->device_type & XFRAME_II_DEVICE)
1424 mem_size = 32;
1425 else
1426 mem_size = 64;
1427
1da177e4
LT		 1428 for (i = 0; i < config->rx_ring_num; i++) {
1429 switch (i) {
1430 case 0:
20346722 1431 mem_share = (mem_size / config->rx_ring_num +
1432 mem_size % config->rx_ring_num);
1da177e4
LT		 1433 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1434 continue;
1435 case 1:
20346722 1436 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1437 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1438 continue;
1439 case 2:
20346722 1440 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1442 continue;
1443 case 3:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1446 continue;
1447 case 4:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1450 continue;
1451 case 5:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1454 continue;
1455 case 6:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1458 continue;
1459 case 7:
20346722 1460 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1461 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1462 continue;
1463 }
1464 }
1465 writeq(val64, &bar0->rx_queue_cfg);
1466
20346722 1467 /*
5e25b9dd 1468 * Filling Tx round robin registers
b7c5678f 1469 * as per the number of FIFOs for equal scheduling priority
1da177e4 1470 */
5e25b9dd 1471 switch (config->tx_fifo_num) {
1472 case 1:
b7c5678f 1473 val64 = 0x0;
5e25b9dd 1474 writeq(val64, &bar0->tx_w_round_robin_0);
1475 writeq(val64, &bar0->tx_w_round_robin_1);
1476 writeq(val64, &bar0->tx_w_round_robin_2);
1477 writeq(val64, &bar0->tx_w_round_robin_3);
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1479 break;
1480 case 2:
b7c5678f 1481 val64 = 0x0001000100010001ULL;
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1485 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1486 val64 = 0x0001000100000000ULL;
5e25b9dd 1487 writeq(val64, &bar0->tx_w_round_robin_4);
1488 break;
1489 case 3:
b7c5678f 1490 val64 = 0x0001020001020001ULL;
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1492 val64 = 0x0200010200010200ULL;
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1494 val64 = 0x0102000102000102ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1496 val64 = 0x0001020001020001ULL;
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1498 val64 = 0x0200010200000000ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_4);
1500 break;
1501 case 4:
b7c5678f 1502 val64 = 0x0001020300010203ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1506 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1507 val64 = 0x0001020300000000ULL;
5e25b9dd 1508 writeq(val64, &bar0->tx_w_round_robin_4);
1509 break;
1510 case 5:
b7c5678f 1511 val64 = 0x0001020304000102ULL;
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1513 val64 = 0x0304000102030400ULL;
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1515 val64 = 0x0102030400010203ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1517 val64 = 0x0400010203040001ULL;
5e25b9dd 1518 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1519 val64 = 0x0203040000000000ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_4);
1521 break;
1522 case 6:
b7c5678f 1523 val64 = 0x0001020304050001ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1525 val64 = 0x0203040500010203ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1527 val64 = 0x0405000102030405ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1529 val64 = 0x0001020304050001ULL;
5e25b9dd 1530 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1531 val64 = 0x0203040500000000ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_4);
1533 break;
1534 case 7:
b7c5678f 1535 val64 = 0x0001020304050600ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1537 val64 = 0x0102030405060001ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1539 val64 = 0x0203040506000102ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1541 val64 = 0x0304050600010203ULL;
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1543 val64 = 0x0405060000000000ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_4);
1545 break;
1546 case 8:
b7c5678f 1547 val64 = 0x0001020304050607ULL;
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1551 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1552 val64 = 0x0001020300000000ULL;
5e25b9dd 1553 writeq(val64, &bar0->tx_w_round_robin_4);
1554 break;
1555 }
1556
b41477f3 1557 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1558 val64 = readq(&bar0->tx_fifo_partition_0);
1559 val64 |= (TX_FIFO_PARTITION_EN);
1560 writeq(val64, &bar0->tx_fifo_partition_0);
1561
5e25b9dd 1562 /* Filling the Rx round robin registers as per the
1563 * number of Rings and steering based on QoS.
1564 */
1565 switch (config->rx_ring_num) {
1566 case 1:
1567 val64 = 0x8080808080808080ULL;
1568 writeq(val64, &bar0->rts_qos_steering);
1569 break;
1570 case 2:
1571 val64 = 0x0000010000010000ULL;
1572 writeq(val64, &bar0->rx_w_round_robin_0);
1573 val64 = 0x0100000100000100ULL;
1574 writeq(val64, &bar0->rx_w_round_robin_1);
1575 val64 = 0x0001000001000001ULL;
1576 writeq(val64, &bar0->rx_w_round_robin_2);
1577 val64 = 0x0000010000010000ULL;
1578 writeq(val64, &bar0->rx_w_round_robin_3);
1579 val64 = 0x0100000000000000ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_4);
1581
1582 val64 = 0x8080808040404040ULL;
1583 writeq(val64, &bar0->rts_qos_steering);
1584 break;
1585 case 3:
1586 val64 = 0x0001000102000001ULL;
1587 writeq(val64, &bar0->rx_w_round_robin_0);
1588 val64 = 0x0001020000010001ULL;
1589 writeq(val64, &bar0->rx_w_round_robin_1);
1590 val64 = 0x0200000100010200ULL;
1591 writeq(val64, &bar0->rx_w_round_robin_2);
1592 val64 = 0x0001000102000001ULL;
1593 writeq(val64, &bar0->rx_w_round_robin_3);
1594 val64 = 0x0001020000000000ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_4);
1596
1597 val64 = 0x8080804040402020ULL;
1598 writeq(val64, &bar0->rts_qos_steering);
1599 break;
1600 case 4:
1601 val64 = 0x0001020300010200ULL;
1602 writeq(val64, &bar0->rx_w_round_robin_0);
1603 val64 = 0x0100000102030001ULL;
1604 writeq(val64, &bar0->rx_w_round_robin_1);
1605 val64 = 0x0200010000010203ULL;
1606 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1607 val64 = 0x0001020001000001ULL;
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_3);
1609 val64 = 0x0203000100000000ULL;
1610 writeq(val64, &bar0->rx_w_round_robin_4);
1611
1612 val64 = 0x8080404020201010ULL;
1613 writeq(val64, &bar0->rts_qos_steering);
1614 break;
1615 case 5:
1616 val64 = 0x0001000203000102ULL;
1617 writeq(val64, &bar0->rx_w_round_robin_0);
1618 val64 = 0x0001020001030004ULL;
1619 writeq(val64, &bar0->rx_w_round_robin_1);
1620 val64 = 0x0001000203000102ULL;
1621 writeq(val64, &bar0->rx_w_round_robin_2);
1622 val64 = 0x0001020001030004ULL;
1623 writeq(val64, &bar0->rx_w_round_robin_3);
1624 val64 = 0x0001000000000000ULL;
1625 writeq(val64, &bar0->rx_w_round_robin_4);
1626
1627 val64 = 0x8080404020201008ULL;
1628 writeq(val64, &bar0->rts_qos_steering);
1629 break;
1630 case 6:
1631 val64 = 0x0001020304000102ULL;
1632 writeq(val64, &bar0->rx_w_round_robin_0);
1633 val64 = 0x0304050001020001ULL;
1634 writeq(val64, &bar0->rx_w_round_robin_1);
1635 val64 = 0x0203000100000102ULL;
1636 writeq(val64, &bar0->rx_w_round_robin_2);
1637 val64 = 0x0304000102030405ULL;
1638 writeq(val64, &bar0->rx_w_round_robin_3);
1639 val64 = 0x0001000200000000ULL;
1640 writeq(val64, &bar0->rx_w_round_robin_4);
1641
1642 val64 = 0x8080404020100804ULL;
1643 writeq(val64, &bar0->rts_qos_steering);
1644 break;
1645 case 7:
1646 val64 = 0x0001020001020300ULL;
1647 writeq(val64, &bar0->rx_w_round_robin_0);
1648 val64 = 0x0102030400010203ULL;
1649 writeq(val64, &bar0->rx_w_round_robin_1);
1650 val64 = 0x0405060001020001ULL;
1651 writeq(val64, &bar0->rx_w_round_robin_2);
1652 val64 = 0x0304050000010200ULL;
1653 writeq(val64, &bar0->rx_w_round_robin_3);
1654 val64 = 0x0102030000000000ULL;
1655 writeq(val64, &bar0->rx_w_round_robin_4);
1656
1657 val64 = 0x8080402010080402ULL;
1658 writeq(val64, &bar0->rts_qos_steering);
1659 break;
1660 case 8:
1661 val64 = 0x0001020300040105ULL;
1662 writeq(val64, &bar0->rx_w_round_robin_0);
1663 val64 = 0x0200030106000204ULL;
1664 writeq(val64, &bar0->rx_w_round_robin_1);
1665 val64 = 0x0103000502010007ULL;
1666 writeq(val64, &bar0->rx_w_round_robin_2);
1667 val64 = 0x0304010002060500ULL;
1668 writeq(val64, &bar0->rx_w_round_robin_3);
1669 val64 = 0x0103020400000000ULL;
1670 writeq(val64, &bar0->rx_w_round_robin_4);
1671
1672 val64 = 0x8040201008040201ULL;
1673 writeq(val64, &bar0->rts_qos_steering);
1674 break;
1675 }
1da177e4
LT		 1676
1677 /* UDP Fix */
1678 val64 = 0;
20346722 1679 for (i = 0; i < 8; i++)
1da177e4
LT		 1680 writeq(val64, &bar0->rts_frm_len_n[i]);
1681
5e25b9dd 1682 /* Set the default rts frame length for the rings configured */
1683 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1684 for (i = 0 ; i < config->rx_ring_num ; i++)
1685 writeq(val64, &bar0->rts_frm_len_n[i]);
1686
1687 /* Set the frame length for the configured rings
1688 * desired by the user
1689 */
1690 for (i = 0; i < config->rx_ring_num; i++) {
1691 /* If rts_frm_len[i] == 0 then it is assumed that user not
1692 * specified frame length steering.
1693 * If the user provides the frame length then program
1694 * the rts_frm_len register for those values or else
1695 * leave it as it is.
1696 */
1697 if (rts_frm_len[i] != 0) {
1698 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1699 &bar0->rts_frm_len_n[i]);
1700 }
1701 }
8a4bdbaa 1702
9fc93a41
SS		 1703 /* Disable differentiated services steering logic */
1704 for (i = 0; i < 64; i++) {
1705 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1706 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1707 dev->name);
1708 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1709 return -ENODEV;
9fc93a41
SS		 1710 }
1711 }
1712
20346722 1713 /* Program statistics memory */
1da177e4 1714 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1715
541ae68f 1716 if (nic->device_type == XFRAME_II_DEVICE) {
1717 val64 = STAT_BC(0x320);
1718 writeq(val64, &bar0->stat_byte_cnt);
1719 }
1720
20346722 1721 /*
1da177e4
LT		 1722 * Initializing the sampling rate for the device to calculate the
1723 * bandwidth utilization.
1724 */
1725 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1726 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1727 writeq(val64, &bar0->mac_link_util);
1728
20346722 1729 /*
1730 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1731 * Scheme.
1732 */
1da177e4 1733
b7c5678f
RV		 1734 /* Initialize TTI */
1735 if (SUCCESS != init_tti(nic, nic->last_link_state))
1736 return -ENODEV;
1da177e4 1737
8a4bdbaa
SS		 1738 /* RTI Initialization */
1739 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1740 /*
8a4bdbaa
SS		 1741 * Programmed to generate Apprx 500 Intrs per
1742 * second
1743 */
1744 int count = (nic->config.bus_speed * 125)/4;
1745 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1746 } else
1747 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1748 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1749 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1750 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1751
1752 writeq(val64, &bar0->rti_data1_mem);
1753
1754 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1755 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1756 if (nic->config.intr_type == MSI_X)
1757 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1758 RTI_DATA2_MEM_RX_UFC_D(0x40));
1759 else
1760 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1761 RTI_DATA2_MEM_RX_UFC_D(0x80));
1762 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1763
8a4bdbaa
SS		 1764 for (i = 0; i < config->rx_ring_num; i++) {
1765 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1766 | RTI_CMD_MEM_OFFSET(i);
1767 writeq(val64, &bar0->rti_command_mem);
1da177e4 1768
8a4bdbaa
SS		 1769 /*
1770 * Once the operation completes, the Strobe bit of the
1771 * command register will be reset. We poll for this
1772 * particular condition. We wait for a maximum of 500ms
1773 * for the operation to complete, if it's not complete
1774 * by then we return error.
1775 */
1776 time = 0;
1777 while (TRUE) {
1778 val64 = readq(&bar0->rti_command_mem);
1779 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1780 break;
b6e3f982 1781
8a4bdbaa
SS		 1782 if (time > 10) {
1783 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1784 dev->name);
9f74ffde 1785 return -ENODEV;
b6e3f982 1786 }
8a4bdbaa
SS		 1787 time++;
1788 msleep(50);
1da177e4 1789 }
1da177e4
LT		 1790 }
1791
20346722 1792 /*
1793 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1794 * the 8 Queues on Rx side.
1795 */
1796 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1798
1799 /* Disable RMAC PAD STRIPPING */
509a2671 1800 add = &bar0->mac_cfg;
1da177e4
LT		 1801 val64 = readq(&bar0->mac_cfg);
1802 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1803 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1804 writel((u32) (val64), add);
1805 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1806 writel((u32) (val64 >> 32), (add + 4));
1807 val64 = readq(&bar0->mac_cfg);
1808
7d3d0439
RA		 1809 /* Enable FCS stripping by adapter */
1810 add = &bar0->mac_cfg;
1811 val64 = readq(&bar0->mac_cfg);
1812 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1813 if (nic->device_type == XFRAME_II_DEVICE)
1814 writeq(val64, &bar0->mac_cfg);
1815 else {
1816 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1817 writel((u32) (val64), add);
1818 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1819 writel((u32) (val64 >> 32), (add + 4));
1820 }
1821
20346722 1822 /*
1823 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1824 * generated by xena.
1825 */
1826 val64 = readq(&bar0->rmac_pause_cfg);
1827 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1828 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1829 writeq(val64, &bar0->rmac_pause_cfg);
1830
20346722 1831 /*
1da177e4
LT		 1832 * Set the Threshold Limit for Generating the pause frame
1833 * If the amount of data in any Queue exceeds ratio of
1834 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1835 * pause frame is generated
1836 */
1837 val64 = 0;
1838 for (i = 0; i < 4; i++) {
1839 val64 |=
1840 (((u64) 0xFF00 | nic->mac_control.
1841 mc_pause_threshold_q0q3)
1842 << (i * 2 * 8));
1843 }
1844 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1845
1846 val64 = 0;
1847 for (i = 0; i < 4; i++) {
1848 val64 |=
1849 (((u64) 0xFF00 | nic->mac_control.
1850 mc_pause_threshold_q4q7)
1851 << (i * 2 * 8));
1852 }
1853 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1854
20346722 1855 /*
1856 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1857 * exceeded the limit pointed by shared_splits
1858 */
1859 val64 = readq(&bar0->pic_control);
1860 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1861 writeq(val64, &bar0->pic_control);
1862
863c11a9
AR		 1863 if (nic->config.bus_speed == 266) {
1864 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1865 writeq(0x0, &bar0->read_retry_delay);
1866 writeq(0x0, &bar0->write_retry_delay);
1867 }
1868
541ae68f 1869 /*
1870 * Programming the Herc to split every write transaction
1871 * that does not start on an ADB to reduce disconnects.
1872 */
1873 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1874 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1875 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1876 writeq(val64, &bar0->misc_control);
1877 val64 = readq(&bar0->pic_control2);
b7b5a128 1878 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1879 writeq(val64, &bar0->pic_control2);
541ae68f 1880 }
c92ca04b
AR		 1881 if (strstr(nic->product_name, "CX4")) {
1882 val64 = TMAC_AVG_IPG(0x17);
1883 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1884 }
1885
1da177e4
LT		 1886 return SUCCESS;
1887}
a371a07d 1888#define LINK_UP_DOWN_INTERRUPT 1
1889#define MAC_RMAC_ERR_TIMER 2
1890
1ee6dd77 1891static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1892{
eaae7f72 1893 if (nic->config.intr_type != INTA)
cc6e7c44 1894 return MAC_RMAC_ERR_TIMER;
a371a07d 1895 if (nic->device_type == XFRAME_II_DEVICE)
1896 return LINK_UP_DOWN_INTERRUPT;
1897 else
1898 return MAC_RMAC_ERR_TIMER;
1899}
8116f3cf 1900
9caab458
SS		 1901/**
1902 * do_s2io_write_bits - update alarm bits in alarm register
1903 * @value: alarm bits
1904 * @flag: interrupt status
1905 * @addr: address value
1906 * Description: update alarm bits in alarm register
1907 * Return Value:
1908 * NONE.
1909 */
1910static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1911{
1912 u64 temp64;
1913
1914 temp64 = readq(addr);
1915
1916 if(flag == ENABLE_INTRS)
1917 temp64 &= ~((u64) value);
1918 else
1919 temp64 |= ((u64) value);
1920 writeq(temp64, addr);
1921}
1da177e4 1922
43b7c451 1923static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1924{
1925 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1926 register u64 gen_int_mask = 0;
1927
1928 if (mask & TX_DMA_INTR) {
1929
1930 gen_int_mask |= TXDMA_INT_M;
1931
1932 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1933 TXDMA_PCC_INT | TXDMA_TTI_INT |
1934 TXDMA_LSO_INT | TXDMA_TPA_INT |
1935 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1936
1937 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1938 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1939 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1940 &bar0->pfc_err_mask);
1941
1942 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1943 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1944 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1945
1946 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1947 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1948 PCC_N_SERR | PCC_6_COF_OV_ERR |
1949 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1950 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1951 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1952
1953 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1954 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1955
1956 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1957 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1958 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1959 flag, &bar0->lso_err_mask);
1960
1961 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1962 flag, &bar0->tpa_err_mask);
1963
1964 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1965
1966 }
1967
1968 if (mask & TX_MAC_INTR) {
1969 gen_int_mask |= TXMAC_INT_M;
1970 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1971 &bar0->mac_int_mask);
1972 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1973 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1974 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1975 flag, &bar0->mac_tmac_err_mask);
1976 }
1977
1978 if (mask & TX_XGXS_INTR) {
1979 gen_int_mask |= TXXGXS_INT_M;
1980 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1981 &bar0->xgxs_int_mask);
1982 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1983 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1984 flag, &bar0->xgxs_txgxs_err_mask);
1985 }
1986
1987 if (mask & RX_DMA_INTR) {
1988 gen_int_mask |= RXDMA_INT_M;
1989 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1990 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1991 flag, &bar0->rxdma_int_mask);
1992 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1993 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1994 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1995 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1996 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1997 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1998 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1999 &bar0->prc_pcix_err_mask);
2000 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2001 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2002 &bar0->rpa_err_mask);
2003 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2004 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2005 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2006 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2007 flag, &bar0->rda_err_mask);
2008 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2009 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2010 flag, &bar0->rti_err_mask);
2011 }
2012
2013 if (mask & RX_MAC_INTR) {
2014 gen_int_mask |= RXMAC_INT_M;
2015 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2016 &bar0->mac_int_mask);
2017 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2018 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2019 RMAC_DOUBLE_ECC_ERR |
2020 RMAC_LINK_STATE_CHANGE_INT,
2021 flag, &bar0->mac_rmac_err_mask);
2022 }
2023
2024 if (mask & RX_XGXS_INTR)
2025 {
2026 gen_int_mask |= RXXGXS_INT_M;
2027 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2028 &bar0->xgxs_int_mask);
2029 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2030 &bar0->xgxs_rxgxs_err_mask);
2031 }
2032
2033 if (mask & MC_INTR) {
2034 gen_int_mask |= MC_INT_M;
2035 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2036 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2037 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2038 &bar0->mc_err_mask);
2039 }
2040 nic->general_int_mask = gen_int_mask;
2041
2042 /* Remove this line when alarm interrupts are enabled */
2043 nic->general_int_mask = 0;
2044}
20346722 2045/**
2046 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2047 * @nic: device private variable,
2048 * @mask: A mask indicating which Intr block must be modified and,
2049 * @flag: A flag indicating whether to enable or disable the Intrs.
2050 * Description: This function will either disable or enable the interrupts
20346722 2051 * depending on the flag argument. The mask argument can be used to
2052 * enable/disable any Intr block.
1da177e4
LT		 2053 * Return Value: NONE.
2054 */
2055
2056static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2057{
1ee6dd77 2058 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2059 register u64 temp64 = 0, intr_mask = 0;
2060
2061 intr_mask = nic->general_int_mask;
1da177e4
LT		 2062
2063 /* Top level interrupt classification */
2064 /* PIC Interrupts */
9caab458 2065 if (mask & TX_PIC_INTR) {
1da177e4 2066 /* Enable PIC Intrs in the general intr mask register */
9caab458 2067 intr_mask |= TXPIC_INT_M;
1da177e4 2068 if (flag == ENABLE_INTRS) {
20346722 2069 /*
a371a07d 2070 * If Hercules adapter enable GPIO otherwise
b41477f3 2071 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2072 * interrupts for now.
2073 * TODO
1da177e4 2074 */
a371a07d 2075 if (s2io_link_fault_indication(nic) ==
2076 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2077 do_s2io_write_bits(PIC_INT_GPIO, flag,
2078 &bar0->pic_int_mask);
2079 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2080 &bar0->gpio_int_mask);
2081 } else
a371a07d 2082 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2083 } else if (flag == DISABLE_INTRS) {
20346722 2084 /*
2085 * Disable PIC Intrs in the general
2086 * intr mask register
1da177e4
LT		 2087 */
2088 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2089 }
2090 }
2091
1da177e4
LT		 2092 /* Tx traffic interrupts */
2093 if (mask & TX_TRAFFIC_INTR) {
9caab458 2094 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2095 if (flag == ENABLE_INTRS) {
20346722 2096 /*
1da177e4 2097 * Enable all the Tx side interrupts
20346722 2098 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2099 */
2100 writeq(0x0, &bar0->tx_traffic_mask);
2101 } else if (flag == DISABLE_INTRS) {
20346722 2102 /*
2103 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2104 * register.
2105 */
2106 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2107 }
2108 }
2109
2110 /* Rx traffic interrupts */
2111 if (mask & RX_TRAFFIC_INTR) {
9caab458 2112 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2113 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2114 /* writing 0 Enables all 8 RX interrupt levels */
2115 writeq(0x0, &bar0->rx_traffic_mask);
2116 } else if (flag == DISABLE_INTRS) {
20346722 2117 /*
2118 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2119 * register.
2120 */
2121 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2122 }
2123 }
9caab458
SS		 2124
2125 temp64 = readq(&bar0->general_int_mask);
2126 if (flag == ENABLE_INTRS)
2127 temp64 &= ~((u64) intr_mask);
2128 else
2129 temp64 = DISABLE_ALL_INTRS;
2130 writeq(temp64, &bar0->general_int_mask);
2131
2132 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2133}
2134
19a60522
SS		 2135/**
2136 * verify_pcc_quiescent- Checks for PCC quiescent state
2137 * Return: 1 If PCC is quiescence
2138 * 0 If PCC is not quiescence
2139 */
1ee6dd77 2140static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2141{
19a60522 2142 int ret = 0, herc;
1ee6dd77 2143 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2144 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2145
19a60522 2146 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2147
2148 if (flag == FALSE) {
44c10138 2149 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2150 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2151 ret = 1;
19a60522
SS		 2152 } else {
2153 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2154 ret = 1;
20346722 2155 }
2156 } else {
44c10138 2157 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2158 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2159 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2160 ret = 1;
5e25b9dd 2161 } else {
2162 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2163 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2164 ret = 1;
20346722 2165 }
2166 }
2167
2168 return ret;
2169}
2170/**
2171 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2172 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2173 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2174 * differs and the calling function passes the input argument flag to
2175 * indicate this.
20346722 2176 * Return: 1 If xena is quiescence
1da177e4
LT		 2177 * 0 If Xena is not quiescence
2178 */
2179
1ee6dd77 2180static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2181{
19a60522 2182 int mode;
1ee6dd77 2183 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2184 u64 val64 = readq(&bar0->adapter_status);
2185 mode = s2io_verify_pci_mode(sp);
1da177e4 2186
19a60522
SS		 2187 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2188 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2189 return 0;
2190 }
2191 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2192 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2193 return 0;
2194 }
2195 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2196 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2197 return 0;
2198 }
2199 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2201 return 0;
2202 }
2203 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2204 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2205 return 0;
2206 }
2207 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2208 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2209 return 0;
2210 }
2211 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2212 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2213 return 0;
2214 }
2215 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2216 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2217 return 0;
1da177e4
LT		 2218 }
2219
19a60522
SS		 2220 /*
2221 * In PCI 33 mode, the P_PLL is not used, and therefore,
2222 * the the P_PLL_LOCK bit in the adapter_status register will
2223 * not be asserted.
2224 */
2225 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2226 sp->device_type == XFRAME_II_DEVICE && mode !=
2227 PCI_MODE_PCI_33) {
2228 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2229 return 0;
2230 }
2231 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2232 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2233 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2234 return 0;
2235 }
2236 return 1;
1da177e4
LT		 2237}
2238
2239/**
2240 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2241 * @sp: Pointer to device specifc structure
20346722 2242 * Description :
1da177e4
LT		 2243 * New procedure to clear mac address reading problems on Alpha platforms
2244 *
2245 */
2246
1ee6dd77 2247static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2248{
1ee6dd77 2249 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2250 u64 val64;
2251 int i = 0;
2252
2253 while (fix_mac[i] != END_SIGN) {
2254 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2255 udelay(10);
1da177e4
LT		 2256 val64 = readq(&bar0->gpio_control);
2257 }
2258}
2259
2260/**
20346722 2261 * start_nic - Turns the device on
1da177e4 2262 * @nic : device private variable.
20346722 2263 * Description:
2264 * This function actually turns the device on. Before this function is
2265 * called,all Registers are configured from their reset states
2266 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2267 * calling this function, the device interrupts are cleared and the NIC is
2268 * literally switched on by writing into the adapter control register.
20346722 2269 * Return Value:
1da177e4
LT		 2270 * SUCCESS on success and -1 on failure.
2271 */
2272
2273static int start_nic(struct s2io_nic *nic)
2274{
1ee6dd77 2275 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2276 struct net_device *dev = nic->dev;
2277 register u64 val64 = 0;
20346722 2278 u16 subid, i;
1ee6dd77 2279 struct mac_info *mac_control;
1da177e4
LT		 2280 struct config_param *config;
2281
2282 mac_control = &nic->mac_control;
2283 config = &nic->config;
2284
2285 /* PRC Initialization and configuration */
2286 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2287 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2288 &bar0->prc_rxd0_n[i]);
2289
2290 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2291 if (nic->rxd_mode == RXD_MODE_1)
2292 val64 |= PRC_CTRL_RC_ENABLED;
2293 else
2294 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2295 if (nic->device_type == XFRAME_II_DEVICE)
2296 val64 |= PRC_CTRL_GROUP_READS;
2297 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2298 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2299 writeq(val64, &bar0->prc_ctrl_n[i]);
2300 }
2301
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_3B) {
2303 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2304 val64 = readq(&bar0->rx_pa_cfg);
2305 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2306 writeq(val64, &bar0->rx_pa_cfg);
2307 }
1da177e4 2308
926930b2
SS		 2309 if (vlan_tag_strip == 0) {
2310 val64 = readq(&bar0->rx_pa_cfg);
2311 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2312 writeq(val64, &bar0->rx_pa_cfg);
2313 vlan_strip_flag = 0;
2314 }
2315
20346722 2316 /*
1da177e4
LT		 2317 * Enabling MC-RLDRAM. After enabling the device, we timeout
2318 * for around 100ms, which is approximately the time required
2319 * for the device to be ready for operation.
2320 */
2321 val64 = readq(&bar0->mc_rldram_mrs);
2322 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2323 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325
20346722 2326 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2327
2328 /* Enabling ECC Protection. */
2329 val64 = readq(&bar0->adapter_control);
2330 val64 &= ~ADAPTER_ECC_EN;
2331 writeq(val64, &bar0->adapter_control);
2332
20346722 2333 /*
2334 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2335 * it.
2336 */
2337 val64 = readq(&bar0->adapter_status);
19a60522 2338 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2339 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2340 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2341 (unsigned long long) val64);
2342 return FAILURE;
2343 }
2344
20346722 2345 /*
1da177e4 2346 * With some switches, link might be already up at this point.
20346722 2347 * Because of this weird behavior, when we enable laser,
2348 * we may not get link. We need to handle this. We cannot
2349 * figure out which switch is misbehaving. So we are forced to
2350 * make a global change.
1da177e4
LT		 2351 */
2352
2353 /* Enabling Laser. */
2354 val64 = readq(&bar0->adapter_control);
2355 val64 |= ADAPTER_EOI_TX_ON;
2356 writeq(val64, &bar0->adapter_control);
2357
c92ca04b
AR		 2358 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2359 /*
2360 * Dont see link state interrupts initally on some switches,
2361 * so directly scheduling the link state task here.
2362 */
2363 schedule_work(&nic->set_link_task);
2364 }
1da177e4
LT		 2365 /* SXE-002: Initialize link and activity LED */
2366 subid = nic->pdev->subsystem_device;
541ae68f 2367 if (((subid & 0xFF) >= 0x07) &&
2368 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2369 val64 = readq(&bar0->gpio_control);
2370 val64 |= 0x0000800000000000ULL;
2371 writeq(val64, &bar0->gpio_control);
2372 val64 = 0x0411040400000000ULL;
509a2671 2373 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2374 }
2375
1da177e4
LT		 2376 return SUCCESS;
2377}
fed5eccd
AR		 2378/**
2379 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2380 */
1ee6dd77
RB		 2381static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2382 TxD *txdlp, int get_off)
fed5eccd 2383{
1ee6dd77 2384 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2385 struct sk_buff *skb;
1ee6dd77 2386 struct TxD *txds;
fed5eccd
AR		 2387 u16 j, frg_cnt;
2388
2389 txds = txdlp;
2fda096d 2390 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2391 pci_unmap_single(nic->pdev, (dma_addr_t)
2392 txds->Buffer_Pointer, sizeof(u64),
2393 PCI_DMA_TODEVICE);
2394 txds++;
2395 }
2396
2397 skb = (struct sk_buff *) ((unsigned long)
2398 txds->Host_Control);
2399 if (!skb) {
1ee6dd77 2400 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2401 return NULL;
2402 }
2403 pci_unmap_single(nic->pdev, (dma_addr_t)
2404 txds->Buffer_Pointer,
2405 skb->len - skb->data_len,
2406 PCI_DMA_TODEVICE);
2407 frg_cnt = skb_shinfo(skb)->nr_frags;
2408 if (frg_cnt) {
2409 txds++;
2410 for (j = 0; j < frg_cnt; j++, txds++) {
2411 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2412 if (!txds->Buffer_Pointer)
2413 break;
6aa20a22 2414 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2415 txds->Buffer_Pointer,
2416 frag->size, PCI_DMA_TODEVICE);
2417 }
2418 }
1ee6dd77 2419 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2420 return(skb);
2421}
1da177e4 2422
20346722 2423/**
2424 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2425 * @nic : device private variable.
20346722 2426 * Description:
1da177e4 2427 * Free all queued Tx buffers.
20346722 2428 * Return Value: void
1da177e4
LT		 2429*/
2430
2431static void free_tx_buffers(struct s2io_nic *nic)
2432{
2433 struct net_device *dev = nic->dev;
2434 struct sk_buff *skb;
1ee6dd77 2435 struct TxD *txdp;
1da177e4 2436 int i, j;
1ee6dd77 2437 struct mac_info *mac_control;
1da177e4 2438 struct config_param *config;
fed5eccd 2439 int cnt = 0;
1da177e4
LT		 2440
2441 mac_control = &nic->mac_control;
2442 config = &nic->config;
2443
2444 for (i = 0; i < config->tx_fifo_num; i++) {
2fda096d
SR		 2445 unsigned long flags;
2446 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
b35b3b49 2447 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
491976b2
SH		 2448 txdp = (struct TxD *) \
2449 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2450 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2451 if (skb) {
8a4bdbaa 2452 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2453 += skb->truesize;
fed5eccd
AR		 2454 dev_kfree_skb(skb);
2455 cnt++;
1da177e4 2456 }
1da177e4
LT		 2457 }
2458 DBG_PRINT(INTR_DBG,
2459 "%s:forcibly freeing %d skbs on FIFO%d\n",
2460 dev->name, cnt, i);
20346722 2461 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2462 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2fda096d 2463 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
1da177e4
LT		 2464 }
2465}
2466
20346722 2467/**
2468 * stop_nic - To stop the nic
1da177e4 2469 * @nic ; device private variable.
20346722 2470 * Description:
2471 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2472 * function does. This function is called to stop the device.
2473 * Return Value:
2474 * void.
2475 */
2476
2477static void stop_nic(struct s2io_nic *nic)
2478{
1ee6dd77 2479 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2480 register u64 val64 = 0;
5d3213cc 2481 u16 interruptible;
1ee6dd77 2482 struct mac_info *mac_control;
1da177e4
LT		 2483 struct config_param *config;
2484
2485 mac_control = &nic->mac_control;
2486 config = &nic->config;
2487
2488 /* Disable all interrupts */
9caab458 2489 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2490 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2491 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2492 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2493
5d3213cc
AR		 2494 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2495 val64 = readq(&bar0->adapter_control);
2496 val64 &= ~(ADAPTER_CNTL_EN);
2497 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2498}
2499
20346722 2500/**
2501 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2502 * @nic: device private variable
20346722 2503 * @ring_no: ring number
2504 * Description:
1da177e4
LT		 2505 * The function allocates Rx side skbs and puts the physical
2506 * address of these buffers into the RxD buffer pointers, so that the NIC
2507 * can DMA the received frame into these locations.
2508 * The NIC supports 3 receive modes, viz
2509 * 1. single buffer,
2510 * 2. three buffer and
2511 * 3. Five buffer modes.
20346722 2512 * Each mode defines how many fragments the received frame will be split
2513 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2514 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2515 * is split into 3 fragments. As of now only single buffer mode is
2516 * supported.
2517 * Return Value:
2518 * SUCCESS on success or an appropriate -ve value on failure.
2519 */
2520
ac1f60db 2521static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2522{
2523 struct net_device *dev = nic->dev;
2524 struct sk_buff *skb;
1ee6dd77 2525 struct RxD_t *rxdp;
1da177e4 2526 int off, off1, size, block_no, block_no1;
1da177e4 2527 u32 alloc_tab = 0;
20346722 2528 u32 alloc_cnt;
1ee6dd77 2529 struct mac_info *mac_control;
1da177e4 2530 struct config_param *config;
20346722 2531 u64 tmp;
1ee6dd77 2532 struct buffAdd *ba;
1ee6dd77 2533 struct RxD_t *first_rxdp = NULL;
363dc367 2534 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
6d517a27
VP		 2535 struct RxD1 *rxdp1;
2536 struct RxD3 *rxdp3;
491abf25 2537 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
1da177e4
LT		 2538
2539 mac_control = &nic->mac_control;
2540 config = &nic->config;
20346722 2541 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2542 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2543
5d3213cc 2544 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2545 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2546 while (alloc_tab < alloc_cnt) {
20346722 2547 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2548 block_index;
20346722 2549 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2550
da6971d8
AR		 2551 rxdp = mac_control->rings[ring_no].
2552 rx_blocks[block_no].rxds[off].virt_addr;
2553
2554 if ((block_no == block_no1) && (off == off1) &&
2555 (rxdp->Host_Control)) {
2556 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2557 dev->name);
1da177e4
LT		 2558 DBG_PRINT(INTR_DBG, " info equated\n");
2559 goto end;
2560 }
da6971d8 2561 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2562 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2563 block_index++;
da6971d8
AR		 2564 if (mac_control->rings[ring_no].rx_curr_put_info.
2565 block_index == mac_control->rings[ring_no].
2566 block_count)
2567 mac_control->rings[ring_no].rx_curr_put_info.
2568 block_index = 0;
2569 block_no = mac_control->rings[ring_no].
2570 rx_curr_put_info.block_index;
2571 if (off == rxd_count[nic->rxd_mode])
2572 off = 0;
20346722 2573 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2574 offset = off;
2575 rxdp = mac_control->rings[ring_no].
2576 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2577 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2578 dev->name, rxdp);
2579 }
c9fcbf47 2580
da6971d8 2581 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
6d517a27 2582 ((nic->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2583 (rxdp->Control_2 & s2BIT(0)))) {
20346722 2584 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2585 offset = off;
1da177e4
LT		 2586 goto end;
2587 }
da6971d8
AR		 2588 /* calculate size of skb based on ring mode */
2589 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2590 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2591 if (nic->rxd_mode == RXD_MODE_1)
2592 size += NET_IP_ALIGN;
da6971d8 2593 else
6d517a27 2594 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2595
da6971d8
AR		 2596 /* allocate skb */
2597 skb = dev_alloc_skb(size);
2598 if(!skb) {
0c61ed5f
RV		 2599 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2600 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b 2601 if (first_rxdp) {
2602 wmb();
2603 first_rxdp->Control_1 |= RXD_OWN_XENA;
2604 }
c53d4945
SH		 2605 nic->mac_control.stats_info->sw_stat. \
2606 mem_alloc_fail_cnt++;
da6971d8
AR		 2607 return -ENOMEM ;
2608 }
8a4bdbaa 2609 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 2610 += skb->truesize;
da6971d8
AR		 2611 if (nic->rxd_mode == RXD_MODE_1) {
2612 /* 1 buffer mode - normal operation mode */
6d517a27 2613 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2614 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2615 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2616 rxdp1->Buffer0_ptr = pci_map_single
863c11a9
AR		 2617 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2618 PCI_DMA_FROMDEVICE);
491abf25
VP		 2619 if( (rxdp1->Buffer0_ptr == 0) ||
2620 (rxdp1->Buffer0_ptr ==
2621 DMA_ERROR_CODE))
2622 goto pci_map_failed;
2623
8a4bdbaa 2624 rxdp->Control_2 =
491976b2 2625 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8 2626
6d517a27 2627 } else if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8 2628 /*
6d517a27
VP		 2629 * 2 buffer mode -
2630 * 2 buffer mode provides 128
da6971d8 2631 * byte aligned receive buffers.
da6971d8
AR		 2632 */
2633
6d517a27 2634 rxdp3 = (struct RxD3*)rxdp;
491976b2 2635 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2636 Buffer0_ptr = rxdp3->Buffer0_ptr;
2637 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2638 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2639 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2640 rxdp3->Buffer0_ptr = Buffer0_ptr;
2641 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2642
da6971d8
AR		 2643 ba = &mac_control->rings[ring_no].ba[block_no][off];
2644 skb_reserve(skb, BUF0_LEN);
2645 tmp = (u64)(unsigned long) skb->data;
2646 tmp += ALIGN_SIZE;
2647 tmp &= ~ALIGN_SIZE;
2648 skb->data = (void *) (unsigned long)tmp;
27a884dc 2649 skb_reset_tail_pointer(skb);
da6971d8 2650
6d517a27
VP		 2651 if (!(rxdp3->Buffer0_ptr))
2652 rxdp3->Buffer0_ptr =
75c30b13 2653 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2654 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2655 else
2656 pci_dma_sync_single_for_device(nic->pdev,
6d517a27 2657 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2658 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25
VP		 2659 if( (rxdp3->Buffer0_ptr == 0) ||
2660 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2661 goto pci_map_failed;
2662
da6971d8
AR		 2663 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2664 if (nic->rxd_mode == RXD_MODE_3B) {
2665 /* Two buffer mode */
2666
2667 /*
6aa20a22 2668 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2669 * L4 payload
2670 */
6d517a27 2671 rxdp3->Buffer2_ptr = pci_map_single
da6971d8
AR		 2672 (nic->pdev, skb->data, dev->mtu + 4,
2673 PCI_DMA_FROMDEVICE);
2674
491abf25
VP		 2675 if( (rxdp3->Buffer2_ptr == 0) ||
2676 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2677 goto pci_map_failed;
2678
2679 rxdp3->Buffer1_ptr =
6aa20a22 2680 pci_map_single(nic->pdev,
75c30b13
AR		 2681 ba->ba_1, BUF1_LEN,
2682 PCI_DMA_FROMDEVICE);
491abf25
VP		 2683 if( (rxdp3->Buffer1_ptr == 0) ||
2684 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2685 pci_unmap_single
2686 (nic->pdev,
3e847423 2687 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 2688 dev->mtu + 4,
2689 PCI_DMA_FROMDEVICE);
2690 goto pci_map_failed;
75c30b13 2691 }
da6971d8
AR		 2692 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2693 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2694 (dev->mtu + 4);
da6971d8 2695 }
b7b5a128 2696 rxdp->Control_2 |= s2BIT(0);
1da177e4 2697 }
1da177e4 2698 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b 2699 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2700 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2701 off++;
da6971d8
AR		 2702 if (off == (rxd_count[nic->rxd_mode] + 1))
2703 off = 0;
20346722 2704 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2705
da6971d8 2706 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2707 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2708 if (first_rxdp) {
2709 wmb();
2710 first_rxdp->Control_1 |= RXD_OWN_XENA;
2711 }
2712 first_rxdp = rxdp;
2713 }
1da177e4
LT		 2714 atomic_inc(&nic->rx_bufs_left[ring_no]);
2715 alloc_tab++;
2716 }
2717
2718 end:
303bcb4b 2719 /* Transfer ownership of first descriptor to adapter just before
2720 * exiting. Before that, use memory barrier so that ownership
2721 * and other fields are seen by adapter correctly.
2722 */
2723 if (first_rxdp) {
2724 wmb();
2725 first_rxdp->Control_1 |= RXD_OWN_XENA;
2726 }
2727
1da177e4 2728 return SUCCESS;
491abf25
VP		 2729pci_map_failed:
2730 stats->pci_map_fail_cnt++;
2731 stats->mem_freed += skb->truesize;
2732 dev_kfree_skb_irq(skb);
2733 return -ENOMEM;
1da177e4
LT		 2734}
2735
da6971d8
AR		 2736static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2737{
2738 struct net_device *dev = sp->dev;
2739 int j;
2740 struct sk_buff *skb;
1ee6dd77
RB		 2741 struct RxD_t *rxdp;
2742 struct mac_info *mac_control;
2743 struct buffAdd *ba;
6d517a27
VP		 2744 struct RxD1 *rxdp1;
2745 struct RxD3 *rxdp3;
da6971d8
AR		 2746
2747 mac_control = &sp->mac_control;
2748 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2749 rxdp = mac_control->rings[ring_no].
2750 rx_blocks[blk].rxds[j].virt_addr;
2751 skb = (struct sk_buff *)
2752 ((unsigned long) rxdp->Host_Control);
2753 if (!skb) {
2754 continue;
2755 }
2756 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2757 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2758 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2759 rxdp1->Buffer0_ptr,
2760 dev->mtu +
2761 HEADER_ETHERNET_II_802_3_SIZE
2762 + HEADER_802_2_SIZE +
2763 HEADER_SNAP_SIZE,
2764 PCI_DMA_FROMDEVICE);
1ee6dd77 2765 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2766 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2767 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2768 ba = &mac_control->rings[ring_no].
2769 ba[blk][j];
2770 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2771 rxdp3->Buffer0_ptr,
2772 BUF0_LEN,
da6971d8
AR		 2773 PCI_DMA_FROMDEVICE);
2774 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2775 rxdp3->Buffer1_ptr,
2776 BUF1_LEN,
da6971d8
AR		 2777 PCI_DMA_FROMDEVICE);
2778 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2779 rxdp3->Buffer2_ptr,
2780 dev->mtu + 4,
da6971d8 2781 PCI_DMA_FROMDEVICE);
1ee6dd77 2782 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2783 }
491976b2 2784 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2785 dev_kfree_skb(skb);
2786 atomic_dec(&sp->rx_bufs_left[ring_no]);
2787 }
2788}
2789
1da177e4 2790/**
20346722 2791 * free_rx_buffers - Frees all Rx buffers
1da177e4 2792 * @sp: device private variable.
20346722 2793 * Description:
1da177e4
LT		 2794 * This function will free all Rx buffers allocated by host.
2795 * Return Value:
2796 * NONE.
2797 */
2798
2799static void free_rx_buffers(struct s2io_nic *sp)
2800{
2801 struct net_device *dev = sp->dev;
da6971d8 2802 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2803 struct mac_info *mac_control;
1da177e4 2804 struct config_param *config;
1da177e4
LT		 2805
2806 mac_control = &sp->mac_control;
2807 config = &sp->config;
2808
2809 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2810 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2811 free_rxd_blk(sp,i,blk);
1da177e4 2812
20346722 2813 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2814 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2815 mac_control->rings[i].rx_curr_put_info.offset = 0;
2816 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2817 atomic_set(&sp->rx_bufs_left[i], 0);
2818 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2819 dev->name, buf_cnt, i);
2820 }
2821}
2822
2823/**
2824 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2825 * @napi : pointer to the napi structure.
20346722 2826 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2827 * during one pass through the 'Poll" function.
2828 * Description:
2829 * Comes into picture only if NAPI support has been incorporated. It does
2830 * the same thing that rx_intr_handler does, but not in a interrupt context
2831 * also It will process only a given number of packets.
2832 * Return value:
2833 * 0 on success and 1 if there are No Rx packets to be processed.
2834 */
2835
bea3348e 2836static int s2io_poll(struct napi_struct *napi, int budget)
1da177e4 2837{
bea3348e
SH		 2838 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2839 struct net_device *dev = nic->dev;
20346722 2840 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2841 struct mac_info *mac_control;
1da177e4 2842 struct config_param *config;
1ee6dd77 2843 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2844 int i;
1da177e4
LT		 2845
2846 mac_control = &nic->mac_control;
2847 config = &nic->config;
2848
bea3348e 2849 nic->pkts_to_process = budget;
20346722 2850 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2851
19a60522
SS		 2852 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2853 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2854
2855 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2856 rx_intr_handler(&mac_control->rings[i]);
2857 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2858 if (!nic->pkts_to_process) {
2859 /* Quota for the current iteration has been met */
2860 goto no_rx;
1da177e4 2861 }
1da177e4 2862 }
1da177e4 2863
bea3348e 2864 netif_rx_complete(dev, napi);
1da177e4
LT		 2865
2866 for (i = 0; i < config->rx_ring_num; i++) {
2867 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2868 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2869 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2870 break;
2871 }
2872 }
2873 /* Re enable the Rx interrupts. */
c92ca04b 2874 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2875 readl(&bar0->rx_traffic_mask);
bea3348e 2876 return pkt_cnt;
1da177e4 2877
20346722 2878no_rx:
1da177e4
LT		 2879 for (i = 0; i < config->rx_ring_num; i++) {
2880 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2881 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2882 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2883 break;
2884 }
2885 }
bea3348e 2886 return pkt_cnt;
1da177e4 2887}
20346722 2888
b41477f3 2889#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2890/**
b41477f3 2891 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2892 * @dev : pointer to the device structure.
2893 * Description:
b41477f3
AR		 2894 * This function will be called by upper layer to check for events on the
2895 * interface in situations where interrupts are disabled. It is used for
2896 * specific in-kernel networking tasks, such as remote consoles and kernel
2897 * debugging over the network (example netdump in RedHat).
612eff0e 2898 */
612eff0e
BH		 2899static void s2io_netpoll(struct net_device *dev)
2900{
1ee6dd77
RB		 2901 struct s2io_nic *nic = dev->priv;
2902 struct mac_info *mac_control;
612eff0e 2903 struct config_param *config;
1ee6dd77 2904 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2905 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2906 int i;
2907
d796fdb7
LV		 2908 if (pci_channel_offline(nic->pdev))
2909 return;
2910
612eff0e
BH		 2911 disable_irq(dev->irq);
2912
612eff0e
BH		 2913 mac_control = &nic->mac_control;
2914 config = &nic->config;
2915
612eff0e 2916 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2917 writeq(val64, &bar0->tx_traffic_int);
2918
6aa20a22 2919 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2920 * run out of skbs and will fail and eventually netpoll application such
2921 * as netdump will fail.
2922 */
2923 for (i = 0; i < config->tx_fifo_num; i++)
2924 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2925
b41477f3 2926 /* check for received packet and indicate up to network */
612eff0e
BH		 2927 for (i = 0; i < config->rx_ring_num; i++)
2928 rx_intr_handler(&mac_control->rings[i]);
2929
2930 for (i = 0; i < config->rx_ring_num; i++) {
2931 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2932 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2933 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2934 break;
2935 }
2936 }
612eff0e
BH		 2937 enable_irq(dev->irq);
2938 return;
2939}
2940#endif
2941
20346722 2942/**
1da177e4
LT		 2943 * rx_intr_handler - Rx interrupt handler
2944 * @nic: device private variable.
20346722 2945 * Description:
2946 * If the interrupt is because of a received frame or if the
1da177e4 2947 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2948 * called. It picks out the RxD at which place the last Rx processing had
2949 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2950 * the offset.
2951 * Return Value:
2952 * NONE.
2953 */
1ee6dd77 2954static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2955{
1ee6dd77 2956 struct s2io_nic *nic = ring_data->nic;
1da177e4 2957 struct net_device *dev = (struct net_device *) nic->dev;
c9fcbf47 2958 int get_block, put_block;
1ee6dd77
RB		 2959 struct rx_curr_get_info get_info, put_info;
2960 struct RxD_t *rxdp;
1da177e4 2961 struct sk_buff *skb;
20346722 2962 int pkt_cnt = 0;
7d3d0439 2963 int i;
6d517a27
VP		 2964 struct RxD1* rxdp1;
2965 struct RxD3* rxdp3;
7d3d0439 2966
20346722 2967 get_info = ring_data->rx_curr_get_info;
2968 get_block = get_info.block_index;
1ee6dd77 2969 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2970 put_block = put_info.block_index;
da6971d8 2971 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2972
da6971d8 2973 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2974 /*
2975 * If your are next to put index then it's
2976 * FIFO full condition
2977 */
da6971d8
AR		 2978 if ((get_block == put_block) &&
2979 (get_info.offset + 1) == put_info.offset) {
75c30b13 2980 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2981 break;
2982 }
20346722 2983 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2984 if (skb == NULL) {
2985 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2986 dev->name);
2987 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2988 return;
1da177e4 2989 }
da6971d8 2990 if (nic->rxd_mode == RXD_MODE_1) {
6d517a27 2991 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2992 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2993 rxdp1->Buffer0_ptr,
2994 dev->mtu +
2995 HEADER_ETHERNET_II_802_3_SIZE +
2996 HEADER_802_2_SIZE +
2997 HEADER_SNAP_SIZE,
2998 PCI_DMA_FROMDEVICE);
da6971d8 2999 } else if (nic->rxd_mode == RXD_MODE_3B) {
6d517a27 3000 rxdp3 = (struct RxD3*)rxdp;
75c30b13 3001 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
6d517a27
VP		 3002 rxdp3->Buffer0_ptr,
3003 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 3004 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 3005 rxdp3->Buffer2_ptr,
3006 dev->mtu + 4,
3007 PCI_DMA_FROMDEVICE);
da6971d8 3008 }
863c11a9 3009 prefetch(skb->data);
20346722 3010 rx_osm_handler(ring_data, rxdp);
3011 get_info.offset++;
da6971d8
AR		 3012 ring_data->rx_curr_get_info.offset = get_info.offset;
3013 rxdp = ring_data->rx_blocks[get_block].
3014 rxds[get_info.offset].virt_addr;
3015 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 3016 get_info.offset = 0;
da6971d8 3017 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3018 get_block++;
da6971d8
AR		 3019 if (get_block == ring_data->block_count)
3020 get_block = 0;
3021 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3022 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3023 }
1da177e4 3024
20346722 3025 nic->pkts_to_process -= 1;
db874e65 3026 if ((napi) && (!nic->pkts_to_process))
20346722 3027 break;
20346722 3028 pkt_cnt++;
1da177e4
LT		 3029 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3030 break;
3031 }
7d3d0439
RA		 3032 if (nic->lro) {
3033 /* Clear all LRO sessions before exiting */
3034 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 3035 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 3036 if (lro->in_use) {
3037 update_L3L4_header(nic, lro);
cdb5bf02 3038 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3039 clear_lro_session(lro);
3040 }
3041 }
3042 }
1da177e4 3043}
20346722 3044
3045/**
1da177e4
LT		 3046 * tx_intr_handler - Transmit interrupt handler
3047 * @nic : device private variable
20346722 3048 * Description:
3049 * If an interrupt was raised to indicate DMA complete of the
3050 * Tx packet, this function is called. It identifies the last TxD
3051 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3052 * DMA'ed into the NICs internal memory.
3053 * Return Value:
3054 * NONE
3055 */
3056
1ee6dd77 3057static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3058{
1ee6dd77 3059 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3060 struct tx_curr_get_info get_info, put_info;
3a3d5756 3061 struct sk_buff *skb = NULL;
1ee6dd77 3062 struct TxD *txdlp;
3a3d5756 3063 int pkt_cnt = 0;
2fda096d 3064 unsigned long flags = 0;
f9046eb3 3065 u8 err_mask;
1da177e4 3066
2fda096d
SR		 3067 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3068 return;
3069
20346722 3070 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3071 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3072 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722 3073 list_virt_addr;
3074 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3075 (get_info.offset != put_info.offset) &&
3076 (txdlp->Host_Control)) {
3077 /* Check for TxD errors */
3078 if (txdlp->Control_1 & TXD_T_CODE) {
3079 unsigned long long err;
3080 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3081 if (err & 0x1) {
3082 nic->mac_control.stats_info->sw_stat.
3083 parity_err_cnt++;
3084 }
491976b2
SH		 3085
3086 /* update t_code statistics */
f9046eb3
OH		 3087 err_mask = err >> 48;
3088 switch(err_mask) {
491976b2
SH		 3089 case 2:
3090 nic->mac_control.stats_info->sw_stat.
3091 tx_buf_abort_cnt++;
3092 break;
3093
3094 case 3:
3095 nic->mac_control.stats_info->sw_stat.
3096 tx_desc_abort_cnt++;
3097 break;
3098
3099 case 7:
3100 nic->mac_control.stats_info->sw_stat.
3101 tx_parity_err_cnt++;
3102 break;
3103
3104 case 10:
3105 nic->mac_control.stats_info->sw_stat.
3106 tx_link_loss_cnt++;
3107 break;
3108
3109 case 15:
3110 nic->mac_control.stats_info->sw_stat.
3111 tx_list_proc_err_cnt++;
3112 break;
3113 }
20346722 3114 }
1da177e4 3115
fed5eccd 3116 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3117 if (skb == NULL) {
2fda096d 3118 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722 3119 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3120 __FUNCTION__);
3121 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3122 return;
3123 }
3a3d5756 3124 pkt_cnt++;
20346722 3125
20346722 3126 /* Updating the statistics block */
20346722 3127 nic->stats.tx_bytes += skb->len;
491976b2 3128 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722 3129 dev_kfree_skb_irq(skb);
3130
3131 get_info.offset++;
863c11a9
AR		 3132 if (get_info.offset == get_info.fifo_len + 1)
3133 get_info.offset = 0;
1ee6dd77 3134 txdlp = (struct TxD *) fifo_data->list_info
20346722 3135 [get_info.offset].list_virt_addr;
3136 fifo_data->tx_curr_get_info.offset =
3137 get_info.offset;
1da177e4
LT		 3138 }
3139
3a3d5756 3140 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3141
3142 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3143}
3144
bd1034f0
AR		 3145/**
3146 * s2io_mdio_write - Function to write in to MDIO registers
3147 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3148 * @addr : address value
3149 * @value : data value
3150 * @dev : pointer to net_device structure
3151 * Description:
3152 * This function is used to write values to the MDIO registers
3153 * NONE
3154 */
3155static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3156{
3157 u64 val64 = 0x0;
1ee6dd77
RB		 3158 struct s2io_nic *sp = dev->priv;
3159 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3160
3161 //address transaction
3162 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3163 | MDIO_MMD_DEV_ADDR(mmd_type)
3164 | MDIO_MMS_PRT_ADDR(0x0);
3165 writeq(val64, &bar0->mdio_control);
3166 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3167 writeq(val64, &bar0->mdio_control);
3168 udelay(100);
3169
3170 //Data transaction
3171 val64 = 0x0;
3172 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3173 | MDIO_MMD_DEV_ADDR(mmd_type)
3174 | MDIO_MMS_PRT_ADDR(0x0)
3175 | MDIO_MDIO_DATA(value)
3176 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3177 writeq(val64, &bar0->mdio_control);
3178 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3179 writeq(val64, &bar0->mdio_control);
3180 udelay(100);
3181
3182 val64 = 0x0;
3183 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3184 | MDIO_MMD_DEV_ADDR(mmd_type)
3185 | MDIO_MMS_PRT_ADDR(0x0)
3186 | MDIO_OP(MDIO_OP_READ_TRANS);
3187 writeq(val64, &bar0->mdio_control);
3188 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3189 writeq(val64, &bar0->mdio_control);
3190 udelay(100);
3191
3192}
3193
3194/**
3195 * s2io_mdio_read - Function to write in to MDIO registers
3196 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3197 * @addr : address value
3198 * @dev : pointer to net_device structure
3199 * Description:
3200 * This function is used to read values to the MDIO registers
3201 * NONE
3202 */
3203static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3204{
3205 u64 val64 = 0x0;
3206 u64 rval64 = 0x0;
1ee6dd77
RB		 3207 struct s2io_nic *sp = dev->priv;
3208 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3209
3210 /* address transaction */
3211 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3212 | MDIO_MMD_DEV_ADDR(mmd_type)
3213 | MDIO_MMS_PRT_ADDR(0x0);
3214 writeq(val64, &bar0->mdio_control);
3215 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3216 writeq(val64, &bar0->mdio_control);
3217 udelay(100);
3218
3219 /* Data transaction */
3220 val64 = 0x0;
3221 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3222 | MDIO_MMD_DEV_ADDR(mmd_type)
3223 | MDIO_MMS_PRT_ADDR(0x0)
3224 | MDIO_OP(MDIO_OP_READ_TRANS);
3225 writeq(val64, &bar0->mdio_control);
3226 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3227 writeq(val64, &bar0->mdio_control);
3228 udelay(100);
3229
3230 /* Read the value from regs */
3231 rval64 = readq(&bar0->mdio_control);
3232 rval64 = rval64 & 0xFFFF0000;
3233 rval64 = rval64 >> 16;
3234 return rval64;
3235}
3236/**
3237 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3238 * @counter : couter value to be updated
3239 * @flag : flag to indicate the status
3240 * @type : counter type
3241 * Description:
3242 * This function is to check the status of the xpak counters value
3243 * NONE
3244 */
3245
3246static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3247{
3248 u64 mask = 0x3;
3249 u64 val64;
3250 int i;
3251 for(i = 0; i <index; i++)
3252 mask = mask << 0x2;
3253
3254 if(flag > 0)
3255 {
3256 *counter = *counter + 1;
3257 val64 = *regs_stat & mask;
3258 val64 = val64 >> (index * 0x2);
3259 val64 = val64 + 1;
3260 if(val64 == 3)
3261 {
3262 switch(type)
3263 {
3264 case 1:
3265 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3266 "service. Excessive temperatures may "
3267 "result in premature transceiver "
3268 "failure \n");
3269 break;
3270 case 2:
3271 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3272 "service Excessive bias currents may "
3273 "indicate imminent laser diode "
3274 "failure \n");
3275 break;
3276 case 3:
3277 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3278 "service Excessive laser output "
3279 "power may saturate far-end "
3280 "receiver\n");
3281 break;
3282 default:
3283 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3284 "type \n");
3285 }
3286 val64 = 0x0;
3287 }
3288 val64 = val64 << (index * 0x2);
3289 *regs_stat = (*regs_stat & (~mask)) | (val64);
3290
3291 } else {
3292 *regs_stat = *regs_stat & (~mask);
3293 }
3294}
3295
3296/**
3297 * s2io_updt_xpak_counter - Function to update the xpak counters
3298 * @dev : pointer to net_device struct
3299 * Description:
3300 * This function is to upate the status of the xpak counters value
3301 * NONE
3302 */
3303static void s2io_updt_xpak_counter(struct net_device *dev)
3304{
3305 u16 flag = 0x0;
3306 u16 type = 0x0;
3307 u16 val16 = 0x0;
3308 u64 val64 = 0x0;
3309 u64 addr = 0x0;
3310
1ee6dd77
RB		 3311 struct s2io_nic *sp = dev->priv;
3312 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3313
3314 /* Check the communication with the MDIO slave */
3315 addr = 0x0000;
3316 val64 = 0x0;
3317 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3318 if((val64 == 0xFFFF) || (val64 == 0x0000))
3319 {
3320 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3321 "Returned %llx\n", (unsigned long long)val64);
3322 return;
3323 }
3324
3325 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3326 if(val64 != 0x2040)
3327 {
3328 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3329 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3330 (unsigned long long)val64);
3331 return;
3332 }
3333
3334 /* Loading the DOM register to MDIO register */
3335 addr = 0xA100;
3336 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3337 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3338
3339 /* Reading the Alarm flags */
3340 addr = 0xA070;
3341 val64 = 0x0;
3342 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3343
3344 flag = CHECKBIT(val64, 0x7);
3345 type = 1;
3346 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3347 &stat_info->xpak_stat.xpak_regs_stat,
3348 0x0, flag, type);
3349
3350 if(CHECKBIT(val64, 0x6))
3351 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3352
3353 flag = CHECKBIT(val64, 0x3);
3354 type = 2;
3355 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3356 &stat_info->xpak_stat.xpak_regs_stat,
3357 0x2, flag, type);
3358
3359 if(CHECKBIT(val64, 0x2))
3360 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3361
3362 flag = CHECKBIT(val64, 0x1);
3363 type = 3;
3364 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3365 &stat_info->xpak_stat.xpak_regs_stat,
3366 0x4, flag, type);
3367
3368 if(CHECKBIT(val64, 0x0))
3369 stat_info->xpak_stat.alarm_laser_output_power_low++;
3370
3371 /* Reading the Warning flags */
3372 addr = 0xA074;
3373 val64 = 0x0;
3374 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3375
3376 if(CHECKBIT(val64, 0x7))
3377 stat_info->xpak_stat.warn_transceiver_temp_high++;
3378
3379 if(CHECKBIT(val64, 0x6))
3380 stat_info->xpak_stat.warn_transceiver_temp_low++;
3381
3382 if(CHECKBIT(val64, 0x3))
3383 stat_info->xpak_stat.warn_laser_bias_current_high++;
3384
3385 if(CHECKBIT(val64, 0x2))
3386 stat_info->xpak_stat.warn_laser_bias_current_low++;
3387
3388 if(CHECKBIT(val64, 0x1))
3389 stat_info->xpak_stat.warn_laser_output_power_high++;
3390
3391 if(CHECKBIT(val64, 0x0))
3392 stat_info->xpak_stat.warn_laser_output_power_low++;
3393}
3394
20346722 3395/**
1da177e4 3396 * wait_for_cmd_complete - waits for a command to complete.
20346722 3397 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3398 * s2io_nic structure.
20346722 3399 * Description: Function that waits for a command to Write into RMAC
3400 * ADDR DATA registers to be completed and returns either success or
3401 * error depending on whether the command was complete or not.
1da177e4
LT		 3402 * Return value:
3403 * SUCCESS on success and FAILURE on failure.
3404 */
3405
9fc93a41
SS		 3406static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3407 int bit_state)
1da177e4 3408{
9fc93a41 3409 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3410 u64 val64;
3411
9fc93a41
SS		 3412 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3413 return FAILURE;
3414
3415 do {
c92ca04b 3416 val64 = readq(addr);
9fc93a41
SS		 3417 if (bit_state == S2IO_BIT_RESET) {
3418 if (!(val64 & busy_bit)) {
3419 ret = SUCCESS;
3420 break;
3421 }
3422 } else {
3423 if (!(val64 & busy_bit)) {
3424 ret = SUCCESS;
3425 break;
3426 }
1da177e4 3427 }
c92ca04b
AR		 3428
3429 if(in_interrupt())
9fc93a41 3430 mdelay(delay);
c92ca04b 3431 else
9fc93a41 3432 msleep(delay);
c92ca04b 3433
9fc93a41
SS		 3434 if (++cnt >= 10)
3435 delay = 50;
3436 } while (cnt < 20);
1da177e4
LT		 3437 return ret;
3438}
19a60522
SS		 3439/*
3440 * check_pci_device_id - Checks if the device id is supported
3441 * @id : device id
3442 * Description: Function to check if the pci device id is supported by driver.
3443 * Return value: Actual device id if supported else PCI_ANY_ID
3444 */
3445static u16 check_pci_device_id(u16 id)
3446{
3447 switch (id) {
3448 case PCI_DEVICE_ID_HERC_WIN:
3449 case PCI_DEVICE_ID_HERC_UNI:
3450 return XFRAME_II_DEVICE;
3451 case PCI_DEVICE_ID_S2IO_UNI:
3452 case PCI_DEVICE_ID_S2IO_WIN:
3453 return XFRAME_I_DEVICE;
3454 default:
3455 return PCI_ANY_ID;
3456 }
3457}
1da177e4 3458
20346722 3459/**
3460 * s2io_reset - Resets the card.
1da177e4
LT		 3461 * @sp : private member of the device structure.
3462 * Description: Function to Reset the card. This function then also
20346722 3463 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3464 * the card reset also resets the configuration space.
3465 * Return value:
3466 * void.
3467 */
3468
1ee6dd77 3469static void s2io_reset(struct s2io_nic * sp)
1da177e4 3470{
1ee6dd77 3471 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3472 u64 val64;
5e25b9dd 3473 u16 subid, pci_cmd;
19a60522
SS		 3474 int i;
3475 u16 val16;
491976b2
SH		 3476 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3477 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3478
19a60522
SS		 3479 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3480 __FUNCTION__, sp->dev->name);
1da177e4 3481
0b1f7ebe 3482 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3483 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3484
1da177e4
LT		 3485 val64 = SW_RESET_ALL;
3486 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3487 if (strstr(sp->product_name, "CX4")) {
3488 msleep(750);
3489 }
19a60522
SS		 3490 msleep(250);
3491 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3492
19a60522
SS		 3493 /* Restore the PCI state saved during initialization. */
3494 pci_restore_state(sp->pdev);
3495 pci_read_config_word(sp->pdev, 0x2, &val16);
3496 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3497 break;
3498 msleep(200);
3499 }
1da177e4 3500
19a60522
SS		 3501 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3502 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3503 }
3504
3505 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3506
3507 s2io_init_pci(sp);
1da177e4 3508
20346722 3509 /* Set swapper to enable I/O register access */
3510 s2io_set_swapper(sp);
3511
faa4f796
SH		 3512 /* restore mac_addr entries */
3513 do_s2io_restore_unicast_mc(sp);
3514
cc6e7c44
RA		 3515 /* Restore the MSIX table entries from local variables */
3516 restore_xmsi_data(sp);
3517
5e25b9dd 3518 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3519 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3520 /* Clear "detected parity error" bit */
303bcb4b 3521 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3522
303bcb4b 3523 /* Clearing PCIX Ecc status register */
3524 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3525
303bcb4b 3526 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3527 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3528 }
5e25b9dd 3529
20346722 3530 /* Reset device statistics maintained by OS */
3531 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3532
491976b2
SH		 3533 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3534 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3535 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3536 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3537 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3538 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3539 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3540 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3541 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3542 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3543 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3544 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3545 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3546 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3547 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3548 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3549 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3550 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3551 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3552
1da177e4
LT		 3553 /* SXE-002: Configure link and activity LED to turn it off */
3554 subid = sp->pdev->subsystem_device;
541ae68f 3555 if (((subid & 0xFF) >= 0x07) &&
3556 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3557 val64 = readq(&bar0->gpio_control);
3558 val64 |= 0x0000800000000000ULL;
3559 writeq(val64, &bar0->gpio_control);
3560 val64 = 0x0411040400000000ULL;
509a2671 3561 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3562 }
3563
541ae68f 3564 /*
3565 * Clear spurious ECC interrupts that would have occured on
3566 * XFRAME II cards after reset.
3567 */
3568 if (sp->device_type == XFRAME_II_DEVICE) {
3569 val64 = readq(&bar0->pcc_err_reg);
3570 writeq(val64, &bar0->pcc_err_reg);
3571 }
3572
1da177e4
LT		 3573 sp->device_enabled_once = FALSE;
3574}
3575
3576/**
20346722 3577 * s2io_set_swapper - to set the swapper controle on the card
3578 * @sp : private member of the device structure,
1da177e4 3579 * pointer to the s2io_nic structure.
20346722 3580 * Description: Function to set the swapper control on the card
1da177e4
LT		 3581 * correctly depending on the 'endianness' of the system.
3582 * Return value:
3583 * SUCCESS on success and FAILURE on failure.
3584 */
3585
1ee6dd77 3586static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3587{
3588 struct net_device *dev = sp->dev;
1ee6dd77 3589 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3590 u64 val64, valt, valr;
3591
20346722 3592 /*
1da177e4
LT		 3593 * Set proper endian settings and verify the same by reading
3594 * the PIF Feed-back register.
3595 */
3596
3597 val64 = readq(&bar0->pif_rd_swapper_fb);
3598 if (val64 != 0x0123456789ABCDEFULL) {
3599 int i = 0;
3600 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3601 0x8100008181000081ULL, /* FE=1, SE=0 */
3602 0x4200004242000042ULL, /* FE=0, SE=1 */
3603 0}; /* FE=0, SE=0 */
3604
3605 while(i<4) {
3606 writeq(value[i], &bar0->swapper_ctrl);
3607 val64 = readq(&bar0->pif_rd_swapper_fb);
3608 if (val64 == 0x0123456789ABCDEFULL)
3609 break;
3610 i++;
3611 }
3612 if (i == 4) {
3613 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3614 dev->name);
3615 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3616 (unsigned long long) val64);
3617 return FAILURE;
3618 }
3619 valr = value[i];
3620 } else {
3621 valr = readq(&bar0->swapper_ctrl);
3622 }
3623
3624 valt = 0x0123456789ABCDEFULL;
3625 writeq(valt, &bar0->xmsi_address);
3626 val64 = readq(&bar0->xmsi_address);
3627
3628 if(val64 != valt) {
3629 int i = 0;
3630 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3631 0x0081810000818100ULL, /* FE=1, SE=0 */
3632 0x0042420000424200ULL, /* FE=0, SE=1 */
3633 0}; /* FE=0, SE=0 */
3634
3635 while(i<4) {
3636 writeq((value[i] | valr), &bar0->swapper_ctrl);
3637 writeq(valt, &bar0->xmsi_address);
3638 val64 = readq(&bar0->xmsi_address);
3639 if(val64 == valt)
3640 break;
3641 i++;
3642 }
3643 if(i == 4) {
20346722 3644 unsigned long long x = val64;
1da177e4 3645 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3646 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3647 return FAILURE;
3648 }
3649 }
3650 val64 = readq(&bar0->swapper_ctrl);
3651 val64 &= 0xFFFF000000000000ULL;
3652
3653#ifdef __BIG_ENDIAN
20346722 3654 /*
3655 * The device by default set to a big endian format, so a
1da177e4
LT		 3656 * big endian driver need not set anything.
3657 */
3658 val64 |= (SWAPPER_CTRL_TXP_FE |
3659 SWAPPER_CTRL_TXP_SE |
3660 SWAPPER_CTRL_TXD_R_FE |
3661 SWAPPER_CTRL_TXD_W_FE |
3662 SWAPPER_CTRL_TXF_R_FE |
3663 SWAPPER_CTRL_RXD_R_FE |
3664 SWAPPER_CTRL_RXD_W_FE |
3665 SWAPPER_CTRL_RXF_W_FE |
3666 SWAPPER_CTRL_XMSI_FE |
1da177e4 3667 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3668 if (sp->config.intr_type == INTA)
cc6e7c44 3669 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3670 writeq(val64, &bar0->swapper_ctrl);
3671#else
20346722 3672 /*
1da177e4 3673 * Initially we enable all bits to make it accessible by the
20346722 3674 * driver, then we selectively enable only those bits that
1da177e4
LT		 3675 * we want to set.
3676 */
3677 val64 |= (SWAPPER_CTRL_TXP_FE |
3678 SWAPPER_CTRL_TXP_SE |
3679 SWAPPER_CTRL_TXD_R_FE |
3680 SWAPPER_CTRL_TXD_R_SE |
3681 SWAPPER_CTRL_TXD_W_FE |
3682 SWAPPER_CTRL_TXD_W_SE |
3683 SWAPPER_CTRL_TXF_R_FE |
3684 SWAPPER_CTRL_RXD_R_FE |
3685 SWAPPER_CTRL_RXD_R_SE |
3686 SWAPPER_CTRL_RXD_W_FE |
3687 SWAPPER_CTRL_RXD_W_SE |
3688 SWAPPER_CTRL_RXF_W_FE |
3689 SWAPPER_CTRL_XMSI_FE |
1da177e4 3690 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3691 if (sp->config.intr_type == INTA)
cc6e7c44 3692 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3693 writeq(val64, &bar0->swapper_ctrl);
3694#endif
3695 val64 = readq(&bar0->swapper_ctrl);
3696
20346722 3697 /*
3698 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3699 * feedback register.
3700 */
3701 val64 = readq(&bar0->pif_rd_swapper_fb);
3702 if (val64 != 0x0123456789ABCDEFULL) {
3703 /* Endian settings are incorrect, calls for another dekko. */
3704 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3705 dev->name);
3706 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3707 (unsigned long long) val64);
3708 return FAILURE;
3709 }
3710
3711 return SUCCESS;
3712}
3713
1ee6dd77 3714static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3715{
1ee6dd77 3716 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3717 u64 val64;
3718 int ret = 0, cnt = 0;
3719
3720 do {
3721 val64 = readq(&bar0->xmsi_access);
b7b5a128 3722 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3723 break;
3724 mdelay(1);
3725 cnt++;
3726 } while(cnt < 5);
3727 if (cnt == 5) {
3728 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3729 ret = 1;
3730 }
3731
3732 return ret;
3733}
3734
1ee6dd77 3735static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3736{
1ee6dd77 3737 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3738 u64 val64;
3739 int i;
3740
75c30b13 3741 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3742 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3743 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
b7b5a128 3744 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3745 writeq(val64, &bar0->xmsi_access);
3746 if (wait_for_msix_trans(nic, i)) {
3747 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3748 continue;
3749 }
3750 }
3751}
3752
1ee6dd77 3753static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3754{
1ee6dd77 3755 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3756 u64 val64, addr, data;
3757 int i;
3758
3759 /* Store and display */
75c30b13 3760 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
b7b5a128 3761 val64 = (s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3762 writeq(val64, &bar0->xmsi_access);
3763 if (wait_for_msix_trans(nic, i)) {
3764 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3765 continue;
3766 }
3767 addr = readq(&bar0->xmsi_address);
3768 data = readq(&bar0->xmsi_data);
3769 if (addr && data) {
3770 nic->msix_info[i].addr = addr;
3771 nic->msix_info[i].data = data;
3772 }
3773 }
3774}
3775
1ee6dd77 3776static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3777{
1ee6dd77 3778 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3779 u64 tx_mat, rx_mat;
3780 u16 msi_control; /* Temp variable */
3781 int ret, i, j, msix_indx = 1;
3782
bd684e43 3783 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
cc6e7c44 3784 GFP_KERNEL);
bd684e43 3785 if (!nic->entries) {
491976b2
SH		 3786 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3787 __FUNCTION__);
c53d4945 3788 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3789 return -ENOMEM;
3790 }
8a4bdbaa 3791 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3792 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3793
3794 nic->s2io_entries =
bd684e43 3795 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
cc6e7c44 3796 GFP_KERNEL);
bd684e43 3797 if (!nic->s2io_entries) {
8a4bdbaa 3798 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
491976b2 3799 __FUNCTION__);
c53d4945 3800 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3801 kfree(nic->entries);
8a4bdbaa 3802 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3803 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3804 return -ENOMEM;
3805 }
8a4bdbaa 3806 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3807 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3808
3809 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3810 nic->entries[i].entry = i;
3811 nic->s2io_entries[i].entry = i;
3812 nic->s2io_entries[i].arg = NULL;
3813 nic->s2io_entries[i].in_use = 0;
3814 }
3815
3816 tx_mat = readq(&bar0->tx_mat0_n[0]);
3817 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3818 tx_mat |= TX_MAT_SET(i, msix_indx);
3819 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3820 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3821 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3822 }
3823 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3824
8a4bdbaa
SS		 3825 rx_mat = readq(&bar0->rx_mat);
3826 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3827 rx_mat |= RX_MAT_SET(j, msix_indx);
3828 nic->s2io_entries[msix_indx].arg
3829 = &nic->mac_control.rings[j];
3830 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3831 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
cc6e7c44 3832 }
8a4bdbaa 3833 writeq(rx_mat, &bar0->rx_mat);
cc6e7c44 3834
c92ca04b 3835 nic->avail_msix_vectors = 0;
cc6e7c44 3836 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3837 /* We fail init if error or we get less vectors than min required */
3838 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3839 nic->avail_msix_vectors = ret;
3840 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3841 }
cc6e7c44
RA		 3842 if (ret) {
3843 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3844 kfree(nic->entries);
8a4bdbaa 3845 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3846 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3847 kfree(nic->s2io_entries);
8a4bdbaa 3848 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3849 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3850 nic->entries = NULL;
3851 nic->s2io_entries = NULL;
c92ca04b 3852 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3853 return -ENOMEM;
3854 }
c92ca04b
AR		 3855 if (!nic->avail_msix_vectors)
3856 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3857
3858 /*
3859 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3860 * in the herc NIC. (Temp change, needs to be removed later)
3861 */
3862 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3863 msi_control |= 0x1; /* Enable MSI */
3864 pci_write_config_word(nic->pdev, 0x42, msi_control);
3865
3866 return 0;
3867}
3868
8abc4d5b 3869/* Handle software interrupt used during MSI(X) test */
33390a70 3870static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3871{
3872 struct s2io_nic *sp = dev_id;
3873
3874 sp->msi_detected = 1;
3875 wake_up(&sp->msi_wait);
3876
3877 return IRQ_HANDLED;
3878}
3879
3880/* Test interrupt path by forcing a a software IRQ */
33390a70 3881static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3882{
3883 struct pci_dev *pdev = sp->pdev;
3884 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3885 int err;
3886 u64 val64, saved64;
3887
3888 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3889 sp->name, sp);
3890 if (err) {
3891 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3892 sp->dev->name, pci_name(pdev), pdev->irq);
3893 return err;
3894 }
3895
3896 init_waitqueue_head (&sp->msi_wait);
3897 sp->msi_detected = 0;
3898
3899 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3900 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3901 val64 |= SCHED_INT_CTRL_TIMER_EN;
3902 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3903 writeq(val64, &bar0->scheduled_int_ctrl);
3904
3905 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3906
3907 if (!sp->msi_detected) {
3908 /* MSI(X) test failed, go back to INTx mode */
2450022a 3909 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3910 "using MSI(X) during test\n", sp->dev->name,
3911 pci_name(pdev));
3912
3913 err = -EOPNOTSUPP;
3914 }
3915
3916 free_irq(sp->entries[1].vector, sp);
3917
3918 writeq(saved64, &bar0->scheduled_int_ctrl);
3919
3920 return err;
3921}
18b2b7bd
SH		 3922
3923static void remove_msix_isr(struct s2io_nic *sp)
3924{
3925 int i;
3926 u16 msi_control;
3927
3928 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3929 if (sp->s2io_entries[i].in_use ==
3930 MSIX_REGISTERED_SUCCESS) {
3931 int vector = sp->entries[i].vector;
3932 void *arg = sp->s2io_entries[i].arg;
3933 free_irq(vector, arg);
3934 }
3935 }
3936
3937 kfree(sp->entries);
3938 kfree(sp->s2io_entries);
3939 sp->entries = NULL;
3940 sp->s2io_entries = NULL;
3941
3942 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3943 msi_control &= 0xFFFE; /* Disable MSI */
3944 pci_write_config_word(sp->pdev, 0x42, msi_control);
3945
3946 pci_disable_msix(sp->pdev);
3947}
3948
3949static void remove_inta_isr(struct s2io_nic *sp)
3950{
3951 struct net_device *dev = sp->dev;
3952
3953 free_irq(sp->pdev->irq, dev);
3954}
3955
1da177e4
LT		 3956/* ********************************************************* *
3957 * Functions defined below concern the OS part of the driver *
3958 * ********************************************************* */
3959
20346722 3960/**
1da177e4
LT		 3961 * s2io_open - open entry point of the driver
3962 * @dev : pointer to the device structure.
3963 * Description:
3964 * This function is the open entry point of the driver. It mainly calls a
3965 * function to allocate Rx buffers and inserts them into the buffer
20346722 3966 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3967 * Return value:
3968 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3969 * file on failure.
3970 */
3971
ac1f60db 3972static int s2io_open(struct net_device *dev)
1da177e4 3973{
1ee6dd77 3974 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3975 int err = 0;
3976
20346722 3977 /*
3978 * Make sure you have link off by default every time
1da177e4
LT		 3979 * Nic is initialized
3980 */
3981 netif_carrier_off(dev);
0b1f7ebe 3982 sp->last_link_state = 0;
1da177e4 3983
eaae7f72 3984 if (sp->config.intr_type == MSI_X) {
8abc4d5b
SS		 3985 int ret = s2io_enable_msi_x(sp);
3986
3987 if (!ret) {
8abc4d5b 3988 ret = s2io_test_msi(sp);
8abc4d5b 3989 /* rollback MSI-X, will re-enable during add_isr() */
18b2b7bd 3990 remove_msix_isr(sp);
8abc4d5b
SS		 3991 }
3992 if (ret) {
3993
3994 DBG_PRINT(ERR_DBG,
3995 "%s: MSI-X requested but failed to enable\n",
3996 dev->name);
eaae7f72 3997 sp->config.intr_type = INTA;
8abc4d5b
SS		 3998 }
3999 }
4000
c77dd43e 4001 /* NAPI doesn't work well with MSI(X) */
eaae7f72 4002 if (sp->config.intr_type != INTA) {
c77dd43e
SS		 4003 if(sp->config.napi)
4004 sp->config.napi = 0;
4005 }
4006
1da177e4 4007 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4008 err = s2io_card_up(sp);
4009 if (err) {
1da177e4
LT		 4010 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4011 dev->name);
e6a8fee2 4012 goto hw_init_failed;
1da177e4
LT		 4013 }
4014
2fd37688 4015 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4016 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4017 s2io_card_down(sp);
20346722 4018 err = -ENODEV;
e6a8fee2 4019 goto hw_init_failed;
1da177e4 4020 }
3a3d5756 4021 s2io_start_all_tx_queue(sp);
1da177e4 4022 return 0;
20346722 4023
20346722 4024hw_init_failed:
eaae7f72 4025 if (sp->config.intr_type == MSI_X) {
491976b2 4026 if (sp->entries) {
cc6e7c44 4027 kfree(sp->entries);
8a4bdbaa 4028 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 4029 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
4030 }
4031 if (sp->s2io_entries) {
cc6e7c44 4032 kfree(sp->s2io_entries);
8a4bdbaa 4033 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 4034 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
4035 }
cc6e7c44 4036 }
20346722 4037 return err;
1da177e4
LT		 4038}
4039
4040/**
4041 * s2io_close -close entry point of the driver
4042 * @dev : device pointer.
4043 * Description:
4044 * This is the stop entry point of the driver. It needs to undo exactly
4045 * whatever was done by the open entry point,thus it's usually referred to
4046 * as the close function.Among other things this function mainly stops the
4047 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4048 * Return value:
4049 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4050 * file on failure.
4051 */
4052
ac1f60db 4053static int s2io_close(struct net_device *dev)
1da177e4 4054{
1ee6dd77 4055 struct s2io_nic *sp = dev->priv;
faa4f796
SH		 4056 struct config_param *config = &sp->config;
4057 u64 tmp64;
4058 int offset;
cc6e7c44 4059
9f74ffde
SH		 4060 /* Return if the device is already closed *
4061 * Can happen when s2io_card_up failed in change_mtu *
4062 */
4063 if (!is_s2io_card_up(sp))
4064 return 0;
4065
3a3d5756 4066 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4067 /* delete all populated mac entries */
4068 for (offset = 1; offset < config->max_mc_addr; offset++) {
4069 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4070 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4071 do_s2io_delete_unicast_mc(sp, tmp64);
4072 }
4073
e6a8fee2 4074 s2io_card_down(sp);
cc6e7c44 4075
1da177e4
LT		 4076 return 0;
4077}
4078
4079/**
4080 * s2io_xmit - Tx entry point of te driver
4081 * @skb : the socket buffer containing the Tx data.
4082 * @dev : device pointer.
4083 * Description :
4084 * This function is the Tx entry point of the driver. S2IO NIC supports
4085 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4086 * NOTE: when device cant queue the pkt,just the trans_start variable will
4087 * not be upadted.
4088 * Return value:
4089 * 0 on success & 1 on failure.
4090 */
4091
ac1f60db 4092static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4093{
1ee6dd77 4094 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4095 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4096 register u64 val64;
1ee6dd77
RB		 4097 struct TxD *txdp;
4098 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4099 unsigned long flags = 0;
be3a6b02 4100 u16 vlan_tag = 0;
2fda096d 4101 struct fifo_info *fifo = NULL;
1ee6dd77 4102 struct mac_info *mac_control;
1da177e4 4103 struct config_param *config;
6cfc482b 4104 int do_spin_lock = 1;
75c30b13 4105 int offload_type;
6cfc482b 4106 int enable_per_list_interrupt = 0;
491abf25 4107 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4108
4109 mac_control = &sp->mac_control;
4110 config = &sp->config;
4111
20346722 4112 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4113
4114 if (unlikely(skb->len <= 0)) {
4115 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4116 dev_kfree_skb_any(skb);
4117 return 0;
2fda096d 4118 }
491976b2 4119
92b84437 4120 if (!is_s2io_card_up(sp)) {
20346722 4121 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4122 dev->name);
20346722 4123 dev_kfree_skb(skb);
4124 return 0;
1da177e4
LT		 4125 }
4126
4127 queue = 0;
3a3d5756 4128 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4129 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4130 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4131 if (skb->protocol == htons(ETH_P_IP)) {
4132 struct iphdr *ip;
4133 struct tcphdr *th;
4134 ip = ip_hdr(skb);
4135
4136 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4137 th = (struct tcphdr *)(((unsigned char *)ip) +
4138 ip->ihl*4);
4139
4140 if (ip->protocol == IPPROTO_TCP) {
4141 queue_len = sp->total_tcp_fifos;
4142 queue = (ntohs(th->source) +
4143 ntohs(th->dest)) &
4144 sp->fifo_selector[queue_len - 1];
4145 if (queue >= queue_len)
4146 queue = queue_len - 1;
4147 } else if (ip->protocol == IPPROTO_UDP) {
4148 queue_len = sp->total_udp_fifos;
4149 queue = (ntohs(th->source) +
4150 ntohs(th->dest)) &
4151 sp->fifo_selector[queue_len - 1];
4152 if (queue >= queue_len)
4153 queue = queue_len - 1;
4154 queue += sp->udp_fifo_idx;
4155 if (skb->len > 1024)
4156 enable_per_list_interrupt = 1;
4157 do_spin_lock = 0;
4158 }
4159 }
4160 }
4161 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4162 /* get fifo number based on skb->priority value */
4163 queue = config->fifo_mapping
4164 [skb->priority & (MAX_TX_FIFOS - 1)];
4165 fifo = &mac_control->fifos[queue];
3a3d5756 4166
6cfc482b
SH		 4167 if (do_spin_lock)
4168 spin_lock_irqsave(&fifo->tx_lock, flags);
4169 else {
4170 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4171 return NETDEV_TX_LOCKED;
4172 }
be3a6b02 4173
3a3d5756
SH		 4174#ifdef CONFIG_NETDEVICES_MULTIQUEUE
4175 if (sp->config.multiq) {
4176 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4177 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4178 return NETDEV_TX_BUSY;
4179 }
4180 } else
4181#endif
4182 if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4183 if (netif_queue_stopped(dev)) {
4184 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4185 return NETDEV_TX_BUSY;
4186 }
4187 }
4188
2fda096d
SR		 4189 put_off = (u16) fifo->tx_curr_put_info.offset;
4190 get_off = (u16) fifo->tx_curr_get_info.offset;
4191 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4192
2fda096d 4193 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4194 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4195 if (txdp->Host_Control ||
4196 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4197 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4198 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4199 dev_kfree_skb(skb);
2fda096d 4200 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4201 return 0;
4202 }
0b1f7ebe 4203
75c30b13 4204 offload_type = s2io_offload_type(skb);
75c30b13 4205 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4206 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4207 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4208 }
84fa7933 4209 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4210 txdp->Control_2 |=
4211 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4212 TXD_TX_CKO_UDP_EN);
4213 }
fed5eccd
AR		 4214 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4215 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4216 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4217 if (enable_per_list_interrupt)
4218 if (put_off & (queue_len >> 5))
4219 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4220 if (vlan_tag) {
be3a6b02 4221 txdp->Control_2 |= TXD_VLAN_ENABLE;
4222 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4223 }
4224
fed5eccd 4225 frg_len = skb->len - skb->data_len;
75c30b13 4226 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4227 int ufo_size;
4228
75c30b13 4229 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4230 ufo_size &= ~7;
4231 txdp->Control_1 |= TXD_UFO_EN;
4232 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4233 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4234#ifdef __BIG_ENDIAN
3459feb8 4235 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4236 fifo->ufo_in_band_v[put_off] =
3459feb8 4237 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4238#else
2fda096d 4239 fifo->ufo_in_band_v[put_off] =
3459feb8 4240 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4241#endif
2fda096d 4242 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4243 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4244 fifo->ufo_in_band_v,
fed5eccd 4245 sizeof(u64), PCI_DMA_TODEVICE);
491abf25
VP		 4246 if((txdp->Buffer_Pointer == 0) ||
4247 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4248 goto pci_map_failed;
fed5eccd 4249 txdp++;
fed5eccd 4250 }
1da177e4 4251
fed5eccd
AR		 4252 txdp->Buffer_Pointer = pci_map_single
4253 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
491abf25
VP		 4254 if((txdp->Buffer_Pointer == 0) ||
4255 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4256 goto pci_map_failed;
4257
fed5eccd
AR		 4258 txdp->Host_Control = (unsigned long) skb;
4259 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4260 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4261 txdp->Control_1 |= TXD_UFO_EN;
4262
4263 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4264 /* For fragmented SKB. */
4265 for (i = 0; i < frg_cnt; i++) {
4266 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4267 /* A '0' length fragment will be ignored */
4268 if (!frag->size)
4269 continue;
1da177e4
LT		 4270 txdp++;
4271 txdp->Buffer_Pointer = (u64) pci_map_page
4272 (sp->pdev, frag->page, frag->page_offset,
4273 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4274 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4275 if (offload_type == SKB_GSO_UDP)
fed5eccd 4276 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4277 }
4278 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4279
75c30b13 4280 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4281 frg_cnt++; /* as Txd0 was used for inband header */
4282
1da177e4 4283 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4284 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4285 writeq(val64, &tx_fifo->TxDL_Pointer);
4286
4287 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4288 TX_FIFO_LAST_LIST);
75c30b13 4289 if (offload_type)
fed5eccd 4290 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4291
1da177e4
LT		 4292 writeq(val64, &tx_fifo->List_Control);
4293
303bcb4b 4294 mmiowb();
4295
1da177e4 4296 put_off++;
2fda096d 4297 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4298 put_off = 0;
2fda096d 4299 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4300
4301 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4302 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4303 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4304 DBG_PRINT(TX_DBG,
4305 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4306 put_off, get_off);
3a3d5756 4307 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4308 }
491976b2 4309 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4 4310 dev->trans_start = jiffies;
2fda096d 4311 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4312
f6f4bfa3
SH		 4313 if (sp->config.intr_type == MSI_X)
4314 tx_intr_handler(fifo);
4315
491abf25
VP		 4316 return 0;
4317pci_map_failed:
4318 stats->pci_map_fail_cnt++;
3a3d5756 4319 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4320 stats->mem_freed += skb->truesize;
4321 dev_kfree_skb(skb);
2fda096d 4322 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4323 return 0;
4324}
4325
25fff88e 4326static void
4327s2io_alarm_handle(unsigned long data)
4328{
1ee6dd77 4329 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4330 struct net_device *dev = sp->dev;
25fff88e 4331
8116f3cf 4332 s2io_handle_errors(dev);
25fff88e 4333 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4334}
4335
1ee6dd77 4336static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13 4337{
99993af6
SH		 4338 if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4339 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4340 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4341 }
4342 return 0;
4343}
4344
7d12e780 4345static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4346{
1ee6dd77
RB		 4347 struct ring_info *ring = (struct ring_info *)dev_id;
4348 struct s2io_nic *sp = ring->nic;
cc6e7c44 4349
596c5c97 4350 if (!is_s2io_card_up(sp))
92b84437 4351 return IRQ_HANDLED;
92b84437 4352
75c30b13
AR		 4353 rx_intr_handler(ring);
4354 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4355
cc6e7c44
RA		 4356 return IRQ_HANDLED;
4357}
4358
7d12e780 4359static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4360{
1ee6dd77
RB		 4361 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4362 struct s2io_nic *sp = fifo->nic;
cc6e7c44 4363
596c5c97 4364 if (!is_s2io_card_up(sp))
92b84437 4365 return IRQ_HANDLED;
92b84437 4366
cc6e7c44 4367 tx_intr_handler(fifo);
cc6e7c44
RA		 4368 return IRQ_HANDLED;
4369}
1ee6dd77 4370static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4371{
1ee6dd77 4372 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4373 u64 val64;
4374
4375 val64 = readq(&bar0->pic_int_status);
4376 if (val64 & PIC_INT_GPIO) {
4377 val64 = readq(&bar0->gpio_int_reg);
4378 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4379 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4380 /*
4381 * This is unstable state so clear both up/down
4382 * interrupt and adapter to re-evaluate the link state.
4383 */
a371a07d 4384 val64 |= GPIO_INT_REG_LINK_DOWN;
4385 val64 |= GPIO_INT_REG_LINK_UP;
4386 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4387 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4388 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4389 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4390 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4391 }
c92ca04b
AR		 4392 else if (val64 & GPIO_INT_REG_LINK_UP) {
4393 val64 = readq(&bar0->adapter_status);
c92ca04b 4394 /* Enable Adapter */
19a60522
SS		 4395 val64 = readq(&bar0->adapter_control);
4396 val64 |= ADAPTER_CNTL_EN;
4397 writeq(val64, &bar0->adapter_control);
4398 val64 |= ADAPTER_LED_ON;
4399 writeq(val64, &bar0->adapter_control);
4400 if (!sp->device_enabled_once)
4401 sp->device_enabled_once = 1;
c92ca04b 4402
19a60522
SS		 4403 s2io_link(sp, LINK_UP);
4404 /*
4405 * unmask link down interrupt and mask link-up
4406 * intr
4407 */
4408 val64 = readq(&bar0->gpio_int_mask);
4409 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4410 val64 |= GPIO_INT_MASK_LINK_UP;
4411 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4412
c92ca04b
AR		 4413 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4414 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4415 s2io_link(sp, LINK_DOWN);
4416 /* Link is down so unmaks link up interrupt */
4417 val64 = readq(&bar0->gpio_int_mask);
4418 val64 &= ~GPIO_INT_MASK_LINK_UP;
4419 val64 |= GPIO_INT_MASK_LINK_DOWN;
4420 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4421
4422 /* turn off LED */
4423 val64 = readq(&bar0->adapter_control);
4424 val64 = val64 &(~ADAPTER_LED_ON);
4425 writeq(val64, &bar0->adapter_control);
a371a07d 4426 }
4427 }
c92ca04b 4428 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4429}
4430
8116f3cf
SS		 4431/**
4432 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4433 * @value: alarm bits
4434 * @addr: address value
4435 * @cnt: counter variable
4436 * Description: Check for alarm and increment the counter
4437 * Return Value:
4438 * 1 - if alarm bit set
4439 * 0 - if alarm bit is not set
4440 */
43b7c451 4441static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4442 unsigned long long *cnt)
4443{
4444 u64 val64;
4445 val64 = readq(addr);
4446 if ( val64 & value ) {
4447 writeq(val64, addr);
4448 (*cnt)++;
4449 return 1;
4450 }
4451 return 0;
4452
4453}
4454
4455/**
4456 * s2io_handle_errors - Xframe error indication handler
4457 * @nic: device private variable
4458 * Description: Handle alarms such as loss of link, single or
4459 * double ECC errors, critical and serious errors.
4460 * Return Value:
4461 * NONE
4462 */
4463static void s2io_handle_errors(void * dev_id)
4464{
4465 struct net_device *dev = (struct net_device *) dev_id;
4466 struct s2io_nic *sp = dev->priv;
4467 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4468 u64 temp64 = 0,val64=0;
4469 int i = 0;
4470
4471 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4472 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4473
92b84437 4474 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4475 return;
4476
4477 if (pci_channel_offline(sp->pdev))
4478 return;
4479
4480 memset(&sw_stat->ring_full_cnt, 0,
4481 sizeof(sw_stat->ring_full_cnt));
4482
4483 /* Handling the XPAK counters update */
4484 if(stats->xpak_timer_count < 72000) {
4485 /* waiting for an hour */
4486 stats->xpak_timer_count++;
4487 } else {
4488 s2io_updt_xpak_counter(dev);
4489 /* reset the count to zero */
4490 stats->xpak_timer_count = 0;
4491 }
4492
4493 /* Handling link status change error Intr */
4494 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4495 val64 = readq(&bar0->mac_rmac_err_reg);
4496 writeq(val64, &bar0->mac_rmac_err_reg);
4497 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4498 schedule_work(&sp->set_link_task);
4499 }
4500
4501 /* In case of a serious error, the device will be Reset. */
4502 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4503 &sw_stat->serious_err_cnt))
4504 goto reset;
4505
4506 /* Check for data parity error */
4507 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4508 &sw_stat->parity_err_cnt))
4509 goto reset;
4510
4511 /* Check for ring full counter */
4512 if (sp->device_type == XFRAME_II_DEVICE) {
4513 val64 = readq(&bar0->ring_bump_counter1);
4514 for (i=0; i<4; i++) {
4515 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4516 temp64 >>= 64 - ((i+1)*16);
4517 sw_stat->ring_full_cnt[i] += temp64;
4518 }
4519
4520 val64 = readq(&bar0->ring_bump_counter2);
4521 for (i=0; i<4; i++) {
4522 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4523 temp64 >>= 64 - ((i+1)*16);
4524 sw_stat->ring_full_cnt[i+4] += temp64;
4525 }
4526 }
4527
4528 val64 = readq(&bar0->txdma_int_status);
4529 /*check for pfc_err*/
4530 if (val64 & TXDMA_PFC_INT) {
4531 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4532 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4533 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4534 &sw_stat->pfc_err_cnt))
4535 goto reset;
4536 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4537 &sw_stat->pfc_err_cnt);
4538 }
4539
4540 /*check for tda_err*/
4541 if (val64 & TXDMA_TDA_INT) {
4542 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4543 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4544 &sw_stat->tda_err_cnt))
4545 goto reset;
4546 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4547 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4548 }
4549 /*check for pcc_err*/
4550 if (val64 & TXDMA_PCC_INT) {
4551 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4552 | PCC_N_SERR | PCC_6_COF_OV_ERR
4553 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4554 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4555 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4556 &sw_stat->pcc_err_cnt))
4557 goto reset;
4558 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4559 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4560 }
4561
4562 /*check for tti_err*/
4563 if (val64 & TXDMA_TTI_INT) {
4564 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4565 &sw_stat->tti_err_cnt))
4566 goto reset;
4567 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4568 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4569 }
4570
4571 /*check for lso_err*/
4572 if (val64 & TXDMA_LSO_INT) {
4573 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4574 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4575 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4576 goto reset;
4577 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4578 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4579 }
4580
4581 /*check for tpa_err*/
4582 if (val64 & TXDMA_TPA_INT) {
4583 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4584 &sw_stat->tpa_err_cnt))
4585 goto reset;
4586 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4587 &sw_stat->tpa_err_cnt);
4588 }
4589
4590 /*check for sm_err*/
4591 if (val64 & TXDMA_SM_INT) {
4592 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4593 &sw_stat->sm_err_cnt))
4594 goto reset;
4595 }
4596
4597 val64 = readq(&bar0->mac_int_status);
4598 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4599 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4600 &bar0->mac_tmac_err_reg,
4601 &sw_stat->mac_tmac_err_cnt))
4602 goto reset;
4603 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4604 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4605 &bar0->mac_tmac_err_reg,
4606 &sw_stat->mac_tmac_err_cnt);
4607 }
4608
4609 val64 = readq(&bar0->xgxs_int_status);
4610 if (val64 & XGXS_INT_STATUS_TXGXS) {
4611 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4612 &bar0->xgxs_txgxs_err_reg,
4613 &sw_stat->xgxs_txgxs_err_cnt))
4614 goto reset;
4615 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4616 &bar0->xgxs_txgxs_err_reg,
4617 &sw_stat->xgxs_txgxs_err_cnt);
4618 }
4619
4620 val64 = readq(&bar0->rxdma_int_status);
4621 if (val64 & RXDMA_INT_RC_INT_M) {
4622 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4623 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4624 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4625 goto reset;
4626 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4627 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4628 &sw_stat->rc_err_cnt);
4629 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4630 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4631 &sw_stat->prc_pcix_err_cnt))
4632 goto reset;
4633 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4634 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4635 &sw_stat->prc_pcix_err_cnt);
4636 }
4637
4638 if (val64 & RXDMA_INT_RPA_INT_M) {
4639 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4640 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4641 goto reset;
4642 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4643 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4644 }
4645
4646 if (val64 & RXDMA_INT_RDA_INT_M) {
4647 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4648 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4649 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4650 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4651 goto reset;
4652 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4653 | RDA_MISC_ERR | RDA_PCIX_ERR,
4654 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4655 }
4656
4657 if (val64 & RXDMA_INT_RTI_INT_M) {
4658 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4659 &sw_stat->rti_err_cnt))
4660 goto reset;
4661 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4662 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4663 }
4664
4665 val64 = readq(&bar0->mac_int_status);
4666 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4667 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4668 &bar0->mac_rmac_err_reg,
4669 &sw_stat->mac_rmac_err_cnt))
4670 goto reset;
4671 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4672 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4673 &sw_stat->mac_rmac_err_cnt);
4674 }
4675
4676 val64 = readq(&bar0->xgxs_int_status);
4677 if (val64 & XGXS_INT_STATUS_RXGXS) {
4678 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4679 &bar0->xgxs_rxgxs_err_reg,
4680 &sw_stat->xgxs_rxgxs_err_cnt))
4681 goto reset;
4682 }
4683
4684 val64 = readq(&bar0->mc_int_status);
4685 if(val64 & MC_INT_STATUS_MC_INT) {
4686 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4687 &sw_stat->mc_err_cnt))
4688 goto reset;
4689
4690 /* Handling Ecc errors */
4691 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4692 writeq(val64, &bar0->mc_err_reg);
4693 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4694 sw_stat->double_ecc_errs++;
4695 if (sp->device_type != XFRAME_II_DEVICE) {
4696 /*
4697 * Reset XframeI only if critical error
4698 */
4699 if (val64 &
4700 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4701 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4702 goto reset;
4703 }
4704 } else
4705 sw_stat->single_ecc_errs++;
4706 }
4707 }
4708 return;
4709
4710reset:
3a3d5756 4711 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4712 schedule_work(&sp->rst_timer_task);
4713 sw_stat->soft_reset_cnt++;
4714 return;
4715}
4716
1da177e4
LT		 4717/**
4718 * s2io_isr - ISR handler of the device .
4719 * @irq: the irq of the device.
4720 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4721 * Description: This function is the ISR handler of the device. It
4722 * identifies the reason for the interrupt and calls the relevant
4723 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4724 * recv buffers, if their numbers are below the panic value which is
4725 * presently set to 25% of the original number of rcv buffers allocated.
4726 * Return value:
20346722 4727 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4728 * IRQ_NONE: will be returned if interrupt is not from our device
4729 */
7d12e780 4730static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4731{
4732 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4733 struct s2io_nic *sp = dev->priv;
4734 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4735 int i;
19a60522 4736 u64 reason = 0;
1ee6dd77 4737 struct mac_info *mac_control;
1da177e4
LT		 4738 struct config_param *config;
4739
d796fdb7
LV		 4740 /* Pretend we handled any irq's from a disconnected card */
4741 if (pci_channel_offline(sp->pdev))
4742 return IRQ_NONE;
4743
596c5c97 4744 if (!is_s2io_card_up(sp))
92b84437 4745 return IRQ_NONE;
92b84437 4746
1da177e4
LT		 4747 mac_control = &sp->mac_control;
4748 config = &sp->config;
4749
20346722 4750 /*
1da177e4
LT		 4751 * Identify the cause for interrupt and call the appropriate
4752 * interrupt handler. Causes for the interrupt could be;
4753 * 1. Rx of packet.
4754 * 2. Tx complete.
4755 * 3. Link down.
1da177e4
LT		 4756 */
4757 reason = readq(&bar0->general_int_status);
4758
596c5c97
SS		 4759 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4760 /* Nothing much can be done. Get out */
4761 return IRQ_HANDLED;
1da177e4 4762 }
5d3213cc 4763
596c5c97
SS		 4764 if (reason & (GEN_INTR_RXTRAFFIC |
4765 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4766 {
4767 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4768
4769 if (config->napi) {
4770 if (reason & GEN_INTR_RXTRAFFIC) {
4771 if (likely(netif_rx_schedule_prep(dev,
4772 &sp->napi))) {
4773 __netif_rx_schedule(dev, &sp->napi);
4774 writeq(S2IO_MINUS_ONE,
4775 &bar0->rx_traffic_mask);
4776 } else
4777 writeq(S2IO_MINUS_ONE,
4778 &bar0->rx_traffic_int);
db874e65 4779 }
596c5c97
SS		 4780 } else {
4781 /*
4782 * rx_traffic_int reg is an R1 register, writing all 1's
4783 * will ensure that the actual interrupt causing bit
4784 * get's cleared and hence a read can be avoided.
4785 */
4786 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4787 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4788
4789 for (i = 0; i < config->rx_ring_num; i++)
4790 rx_intr_handler(&mac_control->rings[i]);
db874e65 4791 }
596c5c97 4792
db874e65 4793 /*
596c5c97 4794 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4795 * will ensure that the actual interrupt causing bit get's
4796 * cleared and hence a read can be avoided.
4797 */
596c5c97
SS		 4798 if (reason & GEN_INTR_TXTRAFFIC)
4799 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4800
596c5c97
SS		 4801 for (i = 0; i < config->tx_fifo_num; i++)
4802 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4803
596c5c97
SS		 4804 if (reason & GEN_INTR_TXPIC)
4805 s2io_txpic_intr_handle(sp);
fe113638 4806
596c5c97
SS		 4807 /*
4808 * Reallocate the buffers from the interrupt handler itself.
4809 */
4810 if (!config->napi) {
4811 for (i = 0; i < config->rx_ring_num; i++)
4812 s2io_chk_rx_buffers(sp, i);
4813 }
4814 writeq(sp->general_int_mask, &bar0->general_int_mask);
4815 readl(&bar0->general_int_status);
20346722 4816
596c5c97 4817 return IRQ_HANDLED;
db874e65 4818
596c5c97
SS		 4819 }
4820 else if (!reason) {
4821 /* The interrupt was not raised by us */
4822 return IRQ_NONE;
4823 }
db874e65 4824
1da177e4
LT		 4825 return IRQ_HANDLED;
4826}
4827
7ba013ac 4828/**
4829 * s2io_updt_stats -
4830 */
1ee6dd77 4831static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4832{
1ee6dd77 4833 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4834 u64 val64;
4835 int cnt = 0;
4836
92b84437 4837 if (is_s2io_card_up(sp)) {
7ba013ac 4838 /* Apprx 30us on a 133 MHz bus */
4839 val64 = SET_UPDT_CLICKS(10) |
4840 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4841 writeq(val64, &bar0->stat_cfg);
4842 do {
4843 udelay(100);
4844 val64 = readq(&bar0->stat_cfg);
b7b5a128 4845 if (!(val64 & s2BIT(0)))
7ba013ac 4846 break;
4847 cnt++;
4848 if (cnt == 5)
4849 break; /* Updt failed */
4850 } while(1);
8a4bdbaa 4851 }
7ba013ac 4852}
4853
1da177e4 4854/**
20346722 4855 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4856 * @dev : pointer to the device structure.
4857 * Description:
20346722 4858 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4859 * structure and returns a pointer to the same.
4860 * Return value:
4861 * pointer to the updated net_device_stats structure.
4862 */
4863
ac1f60db 4864static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4865{
1ee6dd77
RB		 4866 struct s2io_nic *sp = dev->priv;
4867 struct mac_info *mac_control;
1da177e4
LT		 4868 struct config_param *config;
4869
20346722 4870
1da177e4
LT		 4871 mac_control = &sp->mac_control;
4872 config = &sp->config;
4873
7ba013ac 4874 /* Configure Stats for immediate updt */
4875 s2io_updt_stats(sp);
4876
4877 sp->stats.tx_packets =
4878 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722 4879 sp->stats.tx_errors =
4880 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4881 sp->stats.rx_errors =
ee705dba 4882 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722 4883 sp->stats.multicast =
4884 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4885 sp->stats.rx_length_errors =
ee705dba 4886 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4887
4888 return (&sp->stats);
4889}
4890
4891/**
4892 * s2io_set_multicast - entry point for multicast address enable/disable.
4893 * @dev : pointer to the device structure
4894 * Description:
20346722 4895 * This function is a driver entry point which gets called by the kernel
4896 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4897 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4898 * determine, if multicast address must be enabled or if promiscuous mode
4899 * is to be disabled etc.
4900 * Return value:
4901 * void.
4902 */
4903
4904static void s2io_set_multicast(struct net_device *dev)
4905{
4906 int i, j, prev_cnt;
4907 struct dev_mc_list *mclist;
1ee6dd77
RB		 4908 struct s2io_nic *sp = dev->priv;
4909 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4910 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4911 0xfeffffffffffULL;
faa4f796 4912 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4913 void __iomem *add;
faa4f796 4914 struct config_param *config = &sp->config;
1da177e4
LT		 4915
4916 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4917 /* Enable all Multicast addresses */
4918 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4919 &bar0->rmac_addr_data0_mem);
4920 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4921 &bar0->rmac_addr_data1_mem);
4922 val64 = RMAC_ADDR_CMD_MEM_WE |
4923 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4924 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4925 writeq(val64, &bar0->rmac_addr_cmd_mem);
4926 /* Wait till command completes */
c92ca04b 4927 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4928 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4929 S2IO_BIT_RESET);
1da177e4
LT		 4930
4931 sp->m_cast_flg = 1;
faa4f796 4932 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4933 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4934 /* Disable all Multicast addresses */
4935 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4936 &bar0->rmac_addr_data0_mem);
5e25b9dd 4937 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4938 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4939 val64 = RMAC_ADDR_CMD_MEM_WE |
4940 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4941 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4942 writeq(val64, &bar0->rmac_addr_cmd_mem);
4943 /* Wait till command completes */
c92ca04b 4944 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4945 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4946 S2IO_BIT_RESET);
1da177e4
LT		 4947
4948 sp->m_cast_flg = 0;
4949 sp->all_multi_pos = 0;
4950 }
4951
4952 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4953 /* Put the NIC into promiscuous mode */
4954 add = &bar0->mac_cfg;
4955 val64 = readq(&bar0->mac_cfg);
4956 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4957
4958 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4959 writel((u32) val64, add);
4960 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4961 writel((u32) (val64 >> 32), (add + 4));
4962
926930b2
SS		 4963 if (vlan_tag_strip != 1) {
4964 val64 = readq(&bar0->rx_pa_cfg);
4965 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4966 writeq(val64, &bar0->rx_pa_cfg);
4967 vlan_strip_flag = 0;
4968 }
4969
1da177e4
LT		 4970 val64 = readq(&bar0->mac_cfg);
4971 sp->promisc_flg = 1;
776bd20f 4972 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4973 dev->name);
4974 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4975 /* Remove the NIC from promiscuous mode */
4976 add = &bar0->mac_cfg;
4977 val64 = readq(&bar0->mac_cfg);
4978 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4979
4980 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4981 writel((u32) val64, add);
4982 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4983 writel((u32) (val64 >> 32), (add + 4));
4984
926930b2
SS		 4985 if (vlan_tag_strip != 0) {
4986 val64 = readq(&bar0->rx_pa_cfg);
4987 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4988 writeq(val64, &bar0->rx_pa_cfg);
4989 vlan_strip_flag = 1;
4990 }
4991
1da177e4
LT		 4992 val64 = readq(&bar0->mac_cfg);
4993 sp->promisc_flg = 0;
776bd20f 4994 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4995 dev->name);
4996 }
4997
4998 /* Update individual M_CAST address list */
4999 if ((!sp->m_cast_flg) && dev->mc_count) {
5000 if (dev->mc_count >
faa4f796 5001 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5002 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5003 dev->name);
5004 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5005 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5006 return;
5007 }
5008
5009 prev_cnt = sp->mc_addr_count;
5010 sp->mc_addr_count = dev->mc_count;
5011
5012 /* Clear out the previous list of Mc in the H/W. */
5013 for (i = 0; i < prev_cnt; i++) {
5014 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5015 &bar0->rmac_addr_data0_mem);
5016 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5017 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5018 val64 = RMAC_ADDR_CMD_MEM_WE |
5019 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5020 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5021 (config->mc_start_offset + i);
1da177e4
LT		 5022 writeq(val64, &bar0->rmac_addr_cmd_mem);
5023
5024 /* Wait for command completes */
c92ca04b 5025 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5026 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5027 S2IO_BIT_RESET)) {
1da177e4
LT		 5028 DBG_PRINT(ERR_DBG, "%s: Adding ",
5029 dev->name);
5030 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5031 return;
5032 }
5033 }
5034
5035 /* Create the new Rx filter list and update the same in H/W. */
5036 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5037 i++, mclist = mclist->next) {
5038 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5039 ETH_ALEN);
a7a80d5a 5040 mac_addr = 0;
1da177e4
LT		 5041 for (j = 0; j < ETH_ALEN; j++) {
5042 mac_addr |= mclist->dmi_addr[j];
5043 mac_addr <<= 8;
5044 }
5045 mac_addr >>= 8;
5046 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5047 &bar0->rmac_addr_data0_mem);
5048 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5049 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5050 val64 = RMAC_ADDR_CMD_MEM_WE |
5051 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5052 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5053 (i + config->mc_start_offset);
1da177e4
LT		 5054 writeq(val64, &bar0->rmac_addr_cmd_mem);
5055
5056 /* Wait for command completes */
c92ca04b 5057 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5058 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5059 S2IO_BIT_RESET)) {
1da177e4
LT		 5060 DBG_PRINT(ERR_DBG, "%s: Adding ",
5061 dev->name);
5062 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5063 return;
5064 }
5065 }
5066 }
5067}
5068
faa4f796
SH		 5069/* read from CAM unicast & multicast addresses and store it in
5070 * def_mac_addr structure
5071 */
5072void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5073{
5074 int offset;
5075 u64 mac_addr = 0x0;
5076 struct config_param *config = &sp->config;
5077
5078 /* store unicast & multicast mac addresses */
5079 for (offset = 0; offset < config->max_mc_addr; offset++) {
5080 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5081 /* if read fails disable the entry */
5082 if (mac_addr == FAILURE)
5083 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5084 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5085 }
5086}
5087
5088/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5089static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5090{
5091 int offset;
5092 struct config_param *config = &sp->config;
5093 /* restore unicast mac address */
5094 for (offset = 0; offset < config->max_mac_addr; offset++)
5095 do_s2io_prog_unicast(sp->dev,
5096 sp->def_mac_addr[offset].mac_addr);
5097
5098 /* restore multicast mac address */
5099 for (offset = config->mc_start_offset;
5100 offset < config->max_mc_addr; offset++)
5101 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5102}
5103
5104/* add a multicast MAC address to CAM */
5105static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5106{
5107 int i;
5108 u64 mac_addr = 0;
5109 struct config_param *config = &sp->config;
5110
5111 for (i = 0; i < ETH_ALEN; i++) {
5112 mac_addr <<= 8;
5113 mac_addr |= addr[i];
5114 }
5115 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5116 return SUCCESS;
5117
5118 /* check if the multicast mac already preset in CAM */
5119 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5120 u64 tmp64;
5121 tmp64 = do_s2io_read_unicast_mc(sp, i);
5122 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5123 break;
5124
5125 if (tmp64 == mac_addr)
5126 return SUCCESS;
5127 }
5128 if (i == config->max_mc_addr) {
5129 DBG_PRINT(ERR_DBG,
5130 "CAM full no space left for multicast MAC\n");
5131 return FAILURE;
5132 }
5133 /* Update the internal structure with this new mac address */
5134 do_s2io_copy_mac_addr(sp, i, mac_addr);
5135
5136 return (do_s2io_add_mac(sp, mac_addr, i));
5137}
5138
5139/* add MAC address to CAM */
5140static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5141{
5142 u64 val64;
5143 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5144
5145 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5146 &bar0->rmac_addr_data0_mem);
5147
5148 val64 =
5149 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5150 RMAC_ADDR_CMD_MEM_OFFSET(off);
5151 writeq(val64, &bar0->rmac_addr_cmd_mem);
5152
5153 /* Wait till command completes */
5154 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5155 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5156 S2IO_BIT_RESET)) {
faa4f796 5157 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5158 return FAILURE;
5159 }
5160 return SUCCESS;
5161}
faa4f796
SH		 5162/* deletes a specified unicast/multicast mac entry from CAM */
5163static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5164{
5165 int offset;
5166 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5167 struct config_param *config = &sp->config;
5168
5169 for (offset = 1;
5170 offset < config->max_mc_addr; offset++) {
5171 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5172 if (tmp64 == addr) {
5173 /* disable the entry by writing 0xffffffffffffULL */
5174 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5175 return FAILURE;
5176 /* store the new mac list from CAM */
5177 do_s2io_store_unicast_mc(sp);
5178 return SUCCESS;
5179 }
5180 }
5181 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5182 (unsigned long long)addr);
5183 return FAILURE;
5184}
5185
5186/* read mac entries from CAM */
5187static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5188{
5189 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5190 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5191
5192 /* read mac addr */
5193 val64 =
5194 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5195 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5196 writeq(val64, &bar0->rmac_addr_cmd_mem);
5197
5198 /* Wait till command completes */
5199 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5200 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5201 S2IO_BIT_RESET)) {
5202 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5203 return FAILURE;
5204 }
5205 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5206 return (tmp64 >> 16);
5207}
2fd37688
SS		 5208
5209/**
5210 * s2io_set_mac_addr driver entry point
5211 */
faa4f796 5212
2fd37688
SS		 5213static int s2io_set_mac_addr(struct net_device *dev, void *p)
5214{
5215 struct sockaddr *addr = p;
5216
5217 if (!is_valid_ether_addr(addr->sa_data))
5218 return -EINVAL;
5219
5220 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5221
5222 /* store the MAC address in CAM */
5223 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5224}
1da177e4 5225/**
2fd37688 5226 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5227 * @dev : pointer to the device structure.
5228 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5229 * Description : This procedure will program the Xframe to receive
1da177e4 5230 * frames with new Mac Address
20346722 5231 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5232 * as defined in errno.h file on failure.
5233 */
faa4f796 5234
2fd37688 5235static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5236{
1ee6dd77 5237 struct s2io_nic *sp = dev->priv;
2fd37688 5238 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5239 int i;
faa4f796
SH		 5240 u64 tmp64;
5241 struct config_param *config = &sp->config;
1da177e4 5242
20346722 5243 /*
2fd37688
SS		 5244 * Set the new MAC address as the new unicast filter and reflect this
5245 * change on the device address registered with the OS. It will be
5246 * at offset 0.
5247 */
1da177e4
LT		 5248 for (i = 0; i < ETH_ALEN; i++) {
5249 mac_addr <<= 8;
5250 mac_addr |= addr[i];
2fd37688
SS		 5251 perm_addr <<= 8;
5252 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5253 }
5254
2fd37688
SS		 5255 /* check if the dev_addr is different than perm_addr */
5256 if (mac_addr == perm_addr)
d8d70caf
SS		 5257 return SUCCESS;
5258
faa4f796
SH		 5259 /* check if the mac already preset in CAM */
5260 for (i = 1; i < config->max_mac_addr; i++) {
5261 tmp64 = do_s2io_read_unicast_mc(sp, i);
5262 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5263 break;
5264
5265 if (tmp64 == mac_addr) {
5266 DBG_PRINT(INFO_DBG,
5267 "MAC addr:0x%llx already present in CAM\n",
5268 (unsigned long long)mac_addr);
5269 return SUCCESS;
5270 }
5271 }
5272 if (i == config->max_mac_addr) {
5273 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5274 return FAILURE;
5275 }
d8d70caf 5276 /* Update the internal structure with this new mac address */
faa4f796
SH		 5277 do_s2io_copy_mac_addr(sp, i, mac_addr);
5278 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5279}
5280
5281/**
20346722 5282 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5283 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5284 * @info: pointer to the structure with parameters given by ethtool to set
5285 * link information.
5286 * Description:
20346722 5287 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5288 * the NIC.
5289 * Return value:
5290 * 0 on success.
5291*/
5292
5293static int s2io_ethtool_sset(struct net_device *dev,
5294 struct ethtool_cmd *info)
5295{
1ee6dd77 5296 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5297 if ((info->autoneg == AUTONEG_ENABLE) ||
5298 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5299 return -EINVAL;
5300 else {
5301 s2io_close(sp->dev);
5302 s2io_open(sp->dev);
5303 }
5304
5305 return 0;
5306}
5307
5308/**
20346722 5309 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5310 * @sp : private member of the device structure, pointer to the
5311 * s2io_nic structure.
5312 * @info : pointer to the structure with parameters given by ethtool
5313 * to return link information.
5314 * Description:
5315 * Returns link specific information like speed, duplex etc.. to ethtool.
5316 * Return value :
5317 * return 0 on success.
5318 */
5319
5320static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5321{
1ee6dd77 5322 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5323 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5324 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5325 info->port = PORT_FIBRE;
1a7eb72b
SS		 5326
5327 /* info->transceiver */
5328 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5329
5330 if (netif_carrier_ok(sp->dev)) {
5331 info->speed = 10000;
5332 info->duplex = DUPLEX_FULL;
5333 } else {
5334 info->speed = -1;
5335 info->duplex = -1;
5336 }
5337
5338 info->autoneg = AUTONEG_DISABLE;
5339 return 0;
5340}
5341
5342/**
20346722 5343 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5344 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5345 * s2io_nic structure.
5346 * @info : pointer to the structure with parameters given by ethtool to
5347 * return driver information.
5348 * Description:
5349 * Returns driver specefic information like name, version etc.. to ethtool.
5350 * Return value:
5351 * void
5352 */
5353
5354static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5355 struct ethtool_drvinfo *info)
5356{
1ee6dd77 5357 struct s2io_nic *sp = dev->priv;
1da177e4 5358
dbc2309d
JL		 5359 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5360 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5361 strncpy(info->fw_version, "", sizeof(info->fw_version));
5362 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5363 info->regdump_len = XENA_REG_SPACE;
5364 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5365}
5366
5367/**
5368 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5369 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5370 * s2io_nic structure.
20346722 5371 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5372 * dumping the registers.
5373 * @reg_space: The input argumnet into which all the registers are dumped.
5374 * Description:
5375 * Dumps the entire register space of xFrame NIC into the user given
5376 * buffer area.
5377 * Return value :
5378 * void .
5379*/
5380
5381static void s2io_ethtool_gregs(struct net_device *dev,
5382 struct ethtool_regs *regs, void *space)
5383{
5384 int i;
5385 u64 reg;
5386 u8 *reg_space = (u8 *) space;
1ee6dd77 5387 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5388
5389 regs->len = XENA_REG_SPACE;
5390 regs->version = sp->pdev->subsystem_device;
5391
5392 for (i = 0; i < regs->len; i += 8) {
5393 reg = readq(sp->bar0 + i);
5394 memcpy((reg_space + i), &reg, 8);
5395 }
5396}
5397
5398/**
5399 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5400 * @data : address of the private member of the device structure, which
1da177e4 5401 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 5402 * Description: This is actually the timer function that alternates the
5403 * adapter LED bit of the adapter control bit to set/reset every time on
5404 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5405 * once every second.
5406*/
5407static void s2io_phy_id(unsigned long data)
5408{
1ee6dd77
RB		 5409 struct s2io_nic *sp = (struct s2io_nic *) data;
5410 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5411 u64 val64 = 0;
5412 u16 subid;
5413
5414 subid = sp->pdev->subsystem_device;
541ae68f 5415 if ((sp->device_type == XFRAME_II_DEVICE) ||
5416 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5417 val64 = readq(&bar0->gpio_control);
5418 val64 ^= GPIO_CTRL_GPIO_0;
5419 writeq(val64, &bar0->gpio_control);
5420 } else {
5421 val64 = readq(&bar0->adapter_control);
5422 val64 ^= ADAPTER_LED_ON;
5423 writeq(val64, &bar0->adapter_control);
5424 }
5425
5426 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5427}
5428
5429/**
5430 * s2io_ethtool_idnic - To physically identify the nic on the system.
5431 * @sp : private member of the device structure, which is a pointer to the
5432 * s2io_nic structure.
20346722 5433 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5434 * ethtool.
5435 * Description: Used to physically identify the NIC on the system.
20346722 5436 * The Link LED will blink for a time specified by the user for
1da177e4 5437 * identification.
20346722 5438 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5439 * identification is possible only if it's link is up.
5440 * Return value:
5441 * int , returns 0 on success
5442 */
5443
5444static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5445{
5446 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 5447 struct s2io_nic *sp = dev->priv;
5448 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5449 u16 subid;
5450
5451 subid = sp->pdev->subsystem_device;
5452 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f 5453 if ((sp->device_type == XFRAME_I_DEVICE) &&
5454 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5455 val64 = readq(&bar0->adapter_control);
5456 if (!(val64 & ADAPTER_CNTL_EN)) {
5457 printk(KERN_ERR
5458 "Adapter Link down, cannot blink LED\n");
5459 return -EFAULT;
5460 }
5461 }
5462 if (sp->id_timer.function == NULL) {
5463 init_timer(&sp->id_timer);
5464 sp->id_timer.function = s2io_phy_id;
5465 sp->id_timer.data = (unsigned long) sp;
5466 }
5467 mod_timer(&sp->id_timer, jiffies);
5468 if (data)
20346722 5469 msleep_interruptible(data * HZ);
1da177e4 5470 else
20346722 5471 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5472 del_timer_sync(&sp->id_timer);
5473
541ae68f 5474 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5475 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5476 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5477 }
5478
5479 return 0;
5480}
5481
0cec35eb
SH		 5482static void s2io_ethtool_gringparam(struct net_device *dev,
5483 struct ethtool_ringparam *ering)
5484{
5485 struct s2io_nic *sp = dev->priv;
5486 int i,tx_desc_count=0,rx_desc_count=0;
5487
5488 if (sp->rxd_mode == RXD_MODE_1)
5489 ering->rx_max_pending = MAX_RX_DESC_1;
5490 else if (sp->rxd_mode == RXD_MODE_3B)
5491 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5492
5493 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5494 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5495 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5496
0cec35eb
SH		 5497 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5498 ering->tx_pending = tx_desc_count;
5499 rx_desc_count = 0;
8a4bdbaa 5500 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5501 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5502
0cec35eb
SH		 5503 ering->rx_pending = rx_desc_count;
5504
5505 ering->rx_mini_max_pending = 0;
5506 ering->rx_mini_pending = 0;
5507 if(sp->rxd_mode == RXD_MODE_1)
5508 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5509 else if (sp->rxd_mode == RXD_MODE_3B)
5510 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5511 ering->rx_jumbo_pending = rx_desc_count;
5512}
5513
1da177e4
LT		 5514/**
5515 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5516 * @sp : private member of the device structure, which is a pointer to the
5517 * s2io_nic structure.
1da177e4
LT		 5518 * @ep : pointer to the structure with pause parameters given by ethtool.
5519 * Description:
5520 * Returns the Pause frame generation and reception capability of the NIC.
5521 * Return value:
5522 * void
5523 */
5524static void s2io_ethtool_getpause_data(struct net_device *dev,
5525 struct ethtool_pauseparam *ep)
5526{
5527 u64 val64;
1ee6dd77
RB		 5528 struct s2io_nic *sp = dev->priv;
5529 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5530
5531 val64 = readq(&bar0->rmac_pause_cfg);
5532 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5533 ep->tx_pause = TRUE;
5534 if (val64 & RMAC_PAUSE_RX_ENABLE)
5535 ep->rx_pause = TRUE;
5536 ep->autoneg = FALSE;
5537}
5538
5539/**
5540 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5541 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5542 * s2io_nic structure.
5543 * @ep : pointer to the structure with pause parameters given by ethtool.
5544 * Description:
5545 * It can be used to set or reset Pause frame generation or reception
5546 * support of the NIC.
5547 * Return value:
5548 * int, returns 0 on Success
5549 */
5550
5551static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5552 struct ethtool_pauseparam *ep)
1da177e4
LT		 5553{
5554 u64 val64;
1ee6dd77
RB		 5555 struct s2io_nic *sp = dev->priv;
5556 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5557
5558 val64 = readq(&bar0->rmac_pause_cfg);
5559 if (ep->tx_pause)
5560 val64 |= RMAC_PAUSE_GEN_ENABLE;
5561 else
5562 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5563 if (ep->rx_pause)
5564 val64 |= RMAC_PAUSE_RX_ENABLE;
5565 else
5566 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5567 writeq(val64, &bar0->rmac_pause_cfg);
5568 return 0;
5569}
5570
5571/**
5572 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5573 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5574 * s2io_nic structure.
5575 * @off : offset at which the data must be written
5576 * @data : Its an output parameter where the data read at the given
20346722 5577 * offset is stored.
1da177e4 5578 * Description:
20346722 5579 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5580 * read data.
5581 * NOTE: Will allow to read only part of the EEPROM visible through the
5582 * I2C bus.
5583 * Return value:
5584 * -1 on failure and 0 on success.
5585 */
5586
5587#define S2IO_DEV_ID 5
1ee6dd77 5588static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5589{
5590 int ret = -1;
5591 u32 exit_cnt = 0;
5592 u64 val64;
1ee6dd77 5593 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5594
ad4ebed0 5595 if (sp->device_type == XFRAME_I_DEVICE) {
5596 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5597 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5598 I2C_CONTROL_CNTL_START;
5599 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5600
ad4ebed0 5601 while (exit_cnt < 5) {
5602 val64 = readq(&bar0->i2c_control);
5603 if (I2C_CONTROL_CNTL_END(val64)) {
5604 *data = I2C_CONTROL_GET_DATA(val64);
5605 ret = 0;
5606 break;
5607 }
5608 msleep(50);
5609 exit_cnt++;
1da177e4 5610 }
1da177e4
LT		 5611 }
5612
ad4ebed0 5613 if (sp->device_type == XFRAME_II_DEVICE) {
5614 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5615 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5616 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5617 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5618 val64 |= SPI_CONTROL_REQ;
5619 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5620 while (exit_cnt < 5) {
5621 val64 = readq(&bar0->spi_control);
5622 if (val64 & SPI_CONTROL_NACK) {
5623 ret = 1;
5624 break;
5625 } else if (val64 & SPI_CONTROL_DONE) {
5626 *data = readq(&bar0->spi_data);
5627 *data &= 0xffffff;
5628 ret = 0;
5629 break;
5630 }
5631 msleep(50);
5632 exit_cnt++;
5633 }
5634 }
1da177e4
LT		 5635 return ret;
5636}
5637
5638/**
5639 * write_eeprom - actually writes the relevant part of the data value.
5640 * @sp : private member of the device structure, which is a pointer to the
5641 * s2io_nic structure.
5642 * @off : offset at which the data must be written
5643 * @data : The data that is to be written
20346722 5644 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5645 * the Eeprom. (max of 3)
5646 * Description:
5647 * Actually writes the relevant part of the data value into the Eeprom
5648 * through the I2C bus.
5649 * Return value:
5650 * 0 on success, -1 on failure.
5651 */
5652
1ee6dd77 5653static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5654{
5655 int exit_cnt = 0, ret = -1;
5656 u64 val64;
1ee6dd77 5657 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5658
ad4ebed0 5659 if (sp->device_type == XFRAME_I_DEVICE) {
5660 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5661 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5662 I2C_CONTROL_CNTL_START;
5663 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5664
5665 while (exit_cnt < 5) {
5666 val64 = readq(&bar0->i2c_control);
5667 if (I2C_CONTROL_CNTL_END(val64)) {
5668 if (!(val64 & I2C_CONTROL_NACK))
5669 ret = 0;
5670 break;
5671 }
5672 msleep(50);
5673 exit_cnt++;
5674 }
5675 }
1da177e4 5676
ad4ebed0 5677 if (sp->device_type == XFRAME_II_DEVICE) {
5678 int write_cnt = (cnt == 8) ? 0 : cnt;
5679 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5680
5681 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5682 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5683 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5684 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5685 val64 |= SPI_CONTROL_REQ;
5686 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5687 while (exit_cnt < 5) {
5688 val64 = readq(&bar0->spi_control);
5689 if (val64 & SPI_CONTROL_NACK) {
5690 ret = 1;
5691 break;
5692 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5693 ret = 0;
ad4ebed0 5694 break;
5695 }
5696 msleep(50);
5697 exit_cnt++;
1da177e4 5698 }
1da177e4 5699 }
1da177e4
LT		 5700 return ret;
5701}
1ee6dd77 5702static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5703{
b41477f3
AR		 5704 u8 *vpd_data;
5705 u8 data;
9dc737a7
AR		 5706 int i=0, cnt, fail = 0;
5707 int vpd_addr = 0x80;
5708
5709 if (nic->device_type == XFRAME_II_DEVICE) {
5710 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5711 vpd_addr = 0x80;
5712 }
5713 else {
5714 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5715 vpd_addr = 0x50;
5716 }
19a60522 5717 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5718
b41477f3 5719 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5720 if (!vpd_data) {
5721 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5722 return;
c53d4945 5723 }
491976b2 5724 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5725
9dc737a7
AR		 5726 for (i = 0; i < 256; i +=4 ) {
5727 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5728 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5729 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5730 for (cnt = 0; cnt <5; cnt++) {
5731 msleep(2);
5732 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5733 if (data == 0x80)
5734 break;
5735 }
5736 if (cnt >= 5) {
5737 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5738 fail = 1;
5739 break;
5740 }
5741 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5742 (u32 *)&vpd_data[i]);
5743 }
19a60522
SS		 5744
5745 if(!fail) {
5746 /* read serial number of adapter */
5747 for (cnt = 0; cnt < 256; cnt++) {
5748 if ((vpd_data[cnt] == 'S') &&
5749 (vpd_data[cnt+1] == 'N') &&
5750 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5751 memset(nic->serial_num, 0, VPD_STRING_LEN);
5752 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5753 vpd_data[cnt+2]);
5754 break;
5755 }
5756 }
5757 }
5758
5759 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5760 memset(nic->product_name, 0, vpd_data[1]);
5761 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5762 }
b41477f3 5763 kfree(vpd_data);
491976b2 5764 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5765}
5766
1da177e4
LT		 5767/**
5768 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5769 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5770 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5771 * containing all relevant information.
5772 * @data_buf : user defined value to be written into Eeprom.
5773 * Description: Reads the values stored in the Eeprom at given offset
5774 * for a given length. Stores these values int the input argument data
5775 * buffer 'data_buf' and returns these to the caller (ethtool.)
5776 * Return value:
5777 * int 0 on success
5778 */
5779
5780static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5781 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5782{
ad4ebed0 5783 u32 i, valid;
5784 u64 data;
1ee6dd77 5785 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5786
5787 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5788
5789 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5790 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5791
5792 for (i = 0; i < eeprom->len; i += 4) {
5793 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5794 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5795 return -EFAULT;
5796 }
5797 valid = INV(data);
5798 memcpy((data_buf + i), &valid, 4);
5799 }
5800 return 0;
5801}
5802
5803/**
5804 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5805 * @sp : private member of the device structure, which is a pointer to the
5806 * s2io_nic structure.
20346722 5807 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5808 * containing all relevant information.
5809 * @data_buf ; user defined value to be written into Eeprom.
5810 * Description:
5811 * Tries to write the user provided value in the Eeprom, at the offset
5812 * given by the user.
5813 * Return value:
5814 * 0 on success, -EFAULT on failure.
5815 */
5816
5817static int s2io_ethtool_seeprom(struct net_device *dev,
5818 struct ethtool_eeprom *eeprom,
5819 u8 * data_buf)
5820{
5821 int len = eeprom->len, cnt = 0;
ad4ebed0 5822 u64 valid = 0, data;
1ee6dd77 5823 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5824
5825 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5826 DBG_PRINT(ERR_DBG,
5827 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5828 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5829 eeprom->magic);
5830 return -EFAULT;
5831 }
5832
5833 while (len) {
5834 data = (u32) data_buf[cnt] & 0x000000FF;
5835 if (data) {
5836 valid = (u32) (data << 24);
5837 } else
5838 valid = data;
5839
5840 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5841 DBG_PRINT(ERR_DBG,
5842 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5843 DBG_PRINT(ERR_DBG,
5844 "write into the specified offset\n");
5845 return -EFAULT;
5846 }
5847 cnt++;
5848 len--;
5849 }
5850
5851 return 0;
5852}
5853
5854/**
20346722 5855 * s2io_register_test - reads and writes into all clock domains.
5856 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5857 * s2io_nic structure.
5858 * @data : variable that returns the result of each of the test conducted b
5859 * by the driver.
5860 * Description:
5861 * Read and write into all clock domains. The NIC has 3 clock domains,
5862 * see that registers in all the three regions are accessible.
5863 * Return value:
5864 * 0 on success.
5865 */
5866
1ee6dd77 5867static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5868{
1ee6dd77 5869 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5870 u64 val64 = 0, exp_val;
1da177e4
LT		 5871 int fail = 0;
5872
20346722 5873 val64 = readq(&bar0->pif_rd_swapper_fb);
5874 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5875 fail = 1;
5876 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5877 }
5878
5879 val64 = readq(&bar0->rmac_pause_cfg);
5880 if (val64 != 0xc000ffff00000000ULL) {
5881 fail = 1;
5882 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5883 }
5884
5885 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5886 if (sp->device_type == XFRAME_II_DEVICE)
5887 exp_val = 0x0404040404040404ULL;
5888 else
5889 exp_val = 0x0808080808080808ULL;
5890 if (val64 != exp_val) {
1da177e4
LT		 5891 fail = 1;
5892 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5893 }
5894
5895 val64 = readq(&bar0->xgxs_efifo_cfg);
5896 if (val64 != 0x000000001923141EULL) {
5897 fail = 1;
5898 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5899 }
5900
5901 val64 = 0x5A5A5A5A5A5A5A5AULL;
5902 writeq(val64, &bar0->xmsi_data);
5903 val64 = readq(&bar0->xmsi_data);
5904 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5905 fail = 1;
5906 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5907 }
5908
5909 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5910 writeq(val64, &bar0->xmsi_data);
5911 val64 = readq(&bar0->xmsi_data);
5912 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5913 fail = 1;
5914 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5915 }
5916
5917 *data = fail;
ad4ebed0 5918 return fail;
1da177e4
LT		 5919}
5920
5921/**
20346722 5922 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5923 * @sp : private member of the device structure, which is a pointer to the
5924 * s2io_nic structure.
5925 * @data:variable that returns the result of each of the test conducted by
5926 * the driver.
5927 * Description:
20346722 5928 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5929 * register.
5930 * Return value:
5931 * 0 on success.
5932 */
5933
1ee6dd77 5934static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5935{
5936 int fail = 0;
ad4ebed0 5937 u64 ret_data, org_4F0, org_7F0;
5938 u8 saved_4F0 = 0, saved_7F0 = 0;
5939 struct net_device *dev = sp->dev;
1da177e4
LT		 5940
5941 /* Test Write Error at offset 0 */
ad4ebed0 5942 /* Note that SPI interface allows write access to all areas
5943 * of EEPROM. Hence doing all negative testing only for Xframe I.
5944 */
5945 if (sp->device_type == XFRAME_I_DEVICE)
5946 if (!write_eeprom(sp, 0, 0, 3))
5947 fail = 1;
5948
5949 /* Save current values at offsets 0x4F0 and 0x7F0 */
5950 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5951 saved_4F0 = 1;
5952 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5953 saved_7F0 = 1;
1da177e4
LT		 5954
5955 /* Test Write at offset 4f0 */
ad4ebed0 5956 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5957 fail = 1;
5958 if (read_eeprom(sp, 0x4F0, &ret_data))
5959 fail = 1;
5960
ad4ebed0 5961 if (ret_data != 0x012345) {
26b7625c
AM		 5962 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5963 "Data written %llx Data read %llx\n",
5964 dev->name, (unsigned long long)0x12345,
5965 (unsigned long long)ret_data);
1da177e4 5966 fail = 1;
ad4ebed0 5967 }
1da177e4
LT		 5968
5969 /* Reset the EEPROM data go FFFF */
ad4ebed0 5970 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5971
5972 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5973 if (sp->device_type == XFRAME_I_DEVICE)
5974 if (!write_eeprom(sp, 0x07C, 0, 3))
5975 fail = 1;
1da177e4 5976
ad4ebed0 5977 /* Test Write Request at offset 0x7f0 */
5978 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5979 fail = 1;
ad4ebed0 5980 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5981 fail = 1;
5982
ad4ebed0 5983 if (ret_data != 0x012345) {
26b7625c
AM		 5984 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5985 "Data written %llx Data read %llx\n",
5986 dev->name, (unsigned long long)0x12345,
5987 (unsigned long long)ret_data);
1da177e4 5988 fail = 1;
ad4ebed0 5989 }
1da177e4
LT		 5990
5991 /* Reset the EEPROM data go FFFF */
ad4ebed0 5992 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5993
ad4ebed0 5994 if (sp->device_type == XFRAME_I_DEVICE) {
5995 /* Test Write Error at offset 0x80 */
5996 if (!write_eeprom(sp, 0x080, 0, 3))
5997 fail = 1;
1da177e4 5998
ad4ebed0 5999 /* Test Write Error at offset 0xfc */
6000 if (!write_eeprom(sp, 0x0FC, 0, 3))
6001 fail = 1;
1da177e4 6002
ad4ebed0 6003 /* Test Write Error at offset 0x100 */
6004 if (!write_eeprom(sp, 0x100, 0, 3))
6005 fail = 1;
1da177e4 6006
ad4ebed0 6007 /* Test Write Error at offset 4ec */
6008 if (!write_eeprom(sp, 0x4EC, 0, 3))
6009 fail = 1;
6010 }
6011
6012 /* Restore values at offsets 0x4F0 and 0x7F0 */
6013 if (saved_4F0)
6014 write_eeprom(sp, 0x4F0, org_4F0, 3);
6015 if (saved_7F0)
6016 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6017
6018 *data = fail;
ad4ebed0 6019 return fail;
1da177e4
LT		 6020}
6021
6022/**
6023 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6024 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6025 * s2io_nic structure.
20346722 6026 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6027 * the driver.
6028 * Description:
6029 * This invokes the MemBist test of the card. We give around
6030 * 2 secs time for the Test to complete. If it's still not complete
20346722 6031 * within this peiod, we consider that the test failed.
1da177e4
LT		 6032 * Return value:
6033 * 0 on success and -1 on failure.
6034 */
6035
1ee6dd77 6036static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6037{
6038 u8 bist = 0;
6039 int cnt = 0, ret = -1;
6040
6041 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6042 bist |= PCI_BIST_START;
6043 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6044
6045 while (cnt < 20) {
6046 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6047 if (!(bist & PCI_BIST_START)) {
6048 *data = (bist & PCI_BIST_CODE_MASK);
6049 ret = 0;
6050 break;
6051 }
6052 msleep(100);
6053 cnt++;
6054 }
6055
6056 return ret;
6057}
6058
6059/**
20346722 6060 * s2io-link_test - verifies the link state of the nic
6061 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6062 * s2io_nic structure.
6063 * @data: variable that returns the result of each of the test conducted by
6064 * the driver.
6065 * Description:
20346722 6066 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6067 * argument 'data' appropriately.
6068 * Return value:
6069 * 0 on success.
6070 */
6071
1ee6dd77 6072static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6073{
1ee6dd77 6074 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6075 u64 val64;
6076
6077 val64 = readq(&bar0->adapter_status);
c92ca04b 6078 if(!(LINK_IS_UP(val64)))
1da177e4 6079 *data = 1;
c92ca04b
AR		 6080 else
6081 *data = 0;
1da177e4 6082
b41477f3 6083 return *data;
1da177e4
LT		 6084}
6085
6086/**
20346722 6087 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6088 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6089 * s2io_nic structure.
20346722 6090 * @data - variable that returns the result of each of the test
1da177e4
LT		 6091 * conducted by the driver.
6092 * Description:
20346722 6093 * This is one of the offline test that tests the read and write
1da177e4
LT		 6094 * access to the RldRam chip on the NIC.
6095 * Return value:
6096 * 0 on success.
6097 */
6098
1ee6dd77 6099static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6100{
1ee6dd77 6101 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6102 u64 val64;
ad4ebed0 6103 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6104
6105 val64 = readq(&bar0->adapter_control);
6106 val64 &= ~ADAPTER_ECC_EN;
6107 writeq(val64, &bar0->adapter_control);
6108
6109 val64 = readq(&bar0->mc_rldram_test_ctrl);
6110 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6111 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6112
6113 val64 = readq(&bar0->mc_rldram_mrs);
6114 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6115 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6116
6117 val64 |= MC_RLDRAM_MRS_ENABLE;
6118 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6119
6120 while (iteration < 2) {
6121 val64 = 0x55555555aaaa0000ULL;
6122 if (iteration == 1) {
6123 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6124 }
6125 writeq(val64, &bar0->mc_rldram_test_d0);
6126
6127 val64 = 0xaaaa5a5555550000ULL;
6128 if (iteration == 1) {
6129 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6130 }
6131 writeq(val64, &bar0->mc_rldram_test_d1);
6132
6133 val64 = 0x55aaaaaaaa5a0000ULL;
6134 if (iteration == 1) {
6135 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6136 }
6137 writeq(val64, &bar0->mc_rldram_test_d2);
6138
ad4ebed0 6139 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6140 writeq(val64, &bar0->mc_rldram_test_add);
6141
ad4ebed0 6142 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6143 MC_RLDRAM_TEST_GO;
6144 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6145
6146 for (cnt = 0; cnt < 5; cnt++) {
6147 val64 = readq(&bar0->mc_rldram_test_ctrl);
6148 if (val64 & MC_RLDRAM_TEST_DONE)
6149 break;
6150 msleep(200);
6151 }
6152
6153 if (cnt == 5)
6154 break;
6155
ad4ebed0 6156 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6157 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6158
6159 for (cnt = 0; cnt < 5; cnt++) {
6160 val64 = readq(&bar0->mc_rldram_test_ctrl);
6161 if (val64 & MC_RLDRAM_TEST_DONE)
6162 break;
6163 msleep(500);
6164 }
6165
6166 if (cnt == 5)
6167 break;
6168
6169 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6170 if (!(val64 & MC_RLDRAM_TEST_PASS))
6171 test_fail = 1;
1da177e4
LT		 6172
6173 iteration++;
6174 }
6175
ad4ebed0 6176 *data = test_fail;
1da177e4 6177
ad4ebed0 6178 /* Bring the adapter out of test mode */
6179 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6180
6181 return test_fail;
1da177e4
LT		 6182}
6183
6184/**
6185 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6186 * @sp : private member of the device structure, which is a pointer to the
6187 * s2io_nic structure.
6188 * @ethtest : pointer to a ethtool command specific structure that will be
6189 * returned to the user.
20346722 6190 * @data : variable that returns the result of each of the test
1da177e4
LT		 6191 * conducted by the driver.
6192 * Description:
6193 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6194 * the health of the card.
6195 * Return value:
6196 * void
6197 */
6198
6199static void s2io_ethtool_test(struct net_device *dev,
6200 struct ethtool_test *ethtest,
6201 uint64_t * data)
6202{
1ee6dd77 6203 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6204 int orig_state = netif_running(sp->dev);
6205
6206 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6207 /* Offline Tests. */
20346722 6208 if (orig_state)
1da177e4 6209 s2io_close(sp->dev);
1da177e4
LT		 6210
6211 if (s2io_register_test(sp, &data[0]))
6212 ethtest->flags |= ETH_TEST_FL_FAILED;
6213
6214 s2io_reset(sp);
1da177e4
LT		 6215
6216 if (s2io_rldram_test(sp, &data[3]))
6217 ethtest->flags |= ETH_TEST_FL_FAILED;
6218
6219 s2io_reset(sp);
1da177e4
LT		 6220
6221 if (s2io_eeprom_test(sp, &data[1]))
6222 ethtest->flags |= ETH_TEST_FL_FAILED;
6223
6224 if (s2io_bist_test(sp, &data[4]))
6225 ethtest->flags |= ETH_TEST_FL_FAILED;
6226
6227 if (orig_state)
6228 s2io_open(sp->dev);
6229
6230 data[2] = 0;
6231 } else {
6232 /* Online Tests. */
6233 if (!orig_state) {
6234 DBG_PRINT(ERR_DBG,
6235 "%s: is not up, cannot run test\n",
6236 dev->name);
6237 data[0] = -1;
6238 data[1] = -1;
6239 data[2] = -1;
6240 data[3] = -1;
6241 data[4] = -1;
6242 }
6243
6244 if (s2io_link_test(sp, &data[2]))
6245 ethtest->flags |= ETH_TEST_FL_FAILED;
6246
6247 data[0] = 0;
6248 data[1] = 0;
6249 data[3] = 0;
6250 data[4] = 0;
6251 }
6252}
6253
6254static void s2io_get_ethtool_stats(struct net_device *dev,
6255 struct ethtool_stats *estats,
6256 u64 * tmp_stats)
6257{
8116f3cf 6258 int i = 0, k;
1ee6dd77
RB		 6259 struct s2io_nic *sp = dev->priv;
6260 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6261
7ba013ac 6262 s2io_updt_stats(sp);
541ae68f 6263 tmp_stats[i++] =
6264 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6265 le32_to_cpu(stat_info->tmac_frms);
6266 tmp_stats[i++] =
6267 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6268 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6269 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f 6270 tmp_stats[i++] =
6271 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6272 le32_to_cpu(stat_info->tmac_mcst_frms);
6273 tmp_stats[i++] =
6274 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6275 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6276 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6277 tmp_stats[i++] =
6278 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6279 le32_to_cpu(stat_info->tmac_ttl_octets);
6280 tmp_stats[i++] =
6281 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6282 le32_to_cpu(stat_info->tmac_ucst_frms);
6283 tmp_stats[i++] =
6284 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6285 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f 6286 tmp_stats[i++] =
6287 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6288 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6289 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6290 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f 6291 tmp_stats[i++] =
6292 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6293 le32_to_cpu(stat_info->tmac_vld_ip);
6294 tmp_stats[i++] =
6295 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6296 le32_to_cpu(stat_info->tmac_drop_ip);
6297 tmp_stats[i++] =
6298 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6299 le32_to_cpu(stat_info->tmac_icmp);
6300 tmp_stats[i++] =
6301 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6302 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6303 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f 6304 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6305 le32_to_cpu(stat_info->tmac_udp);
6306 tmp_stats[i++] =
6307 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6308 le32_to_cpu(stat_info->rmac_vld_frms);
6309 tmp_stats[i++] =
6310 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6311 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6312 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6313 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f 6314 tmp_stats[i++] =
6315 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6316 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6317 tmp_stats[i++] =
6318 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6319 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6320 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6321 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6322 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6323 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6324 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6325 tmp_stats[i++] =
6326 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6327 le32_to_cpu(stat_info->rmac_ttl_octets);
6328 tmp_stats[i++] =
6329 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6330 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6331 tmp_stats[i++] =
6332 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6333 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f 6334 tmp_stats[i++] =
6335 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6336 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6337 tmp_stats[i++] =
6338 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6339 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6340 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6341 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f 6342 tmp_stats[i++] =
6343 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6344 le32_to_cpu(stat_info->rmac_usized_frms);
6345 tmp_stats[i++] =
6346 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6347 le32_to_cpu(stat_info->rmac_osized_frms);
6348 tmp_stats[i++] =
6349 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6350 le32_to_cpu(stat_info->rmac_frag_frms);
6351 tmp_stats[i++] =
6352 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6353 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6354 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6355 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6356 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6357 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6358 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6359 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6360 tmp_stats[i++] =
6361 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6362 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6363 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6364 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6365 tmp_stats[i++] =
6366 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6367 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6368 tmp_stats[i++] =
6369 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6370 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6371 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6372 tmp_stats[i++] =
6373 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f 6374 le32_to_cpu(stat_info->rmac_udp);
6375 tmp_stats[i++] =
6376 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6377 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6378 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6379 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6380 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6381 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6382 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6383 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6384 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6385 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6386 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6387 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6388 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6389 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6390 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6391 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6392 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6393 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6394 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f 6395 tmp_stats[i++] =
6396 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6397 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6398 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6399 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f 6400 tmp_stats[i++] =
6401 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6402 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6403 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6404 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6405 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6406 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6407 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6408 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6409 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6410 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6411 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6412 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6413 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6414 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6415 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6416 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6417 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6418 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6419 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6420 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6421 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6422
6423 /* Enhanced statistics exist only for Hercules */
6424 if(sp->device_type == XFRAME_II_DEVICE) {
6425 tmp_stats[i++] =
6426 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6427 tmp_stats[i++] =
6428 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6429 tmp_stats[i++] =
6430 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6431 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6432 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6433 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6434 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6435 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6436 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6437 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6438 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6439 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6440 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6441 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6442 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6443 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6444 }
6445
7ba013ac 6446 tmp_stats[i++] = 0;
6447 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6448 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6449 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6450 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6451 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6452 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6453 for (k = 0; k < MAX_RX_RINGS; k++)
6454 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6455 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6456 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6457 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6458 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6459 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6460 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6461 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6462 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6463 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6464 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6465 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6466 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6467 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6468 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6469 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6470 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6471 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6472 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6473 int count = 0;
6aa20a22 6474 /*
bd1034f0
AR		 6475 * Since 64-bit divide does not work on all platforms,
6476 * do repeated subtraction.
6477 */
6478 while (tmp >= stat_info->sw_stat.num_aggregations) {
6479 tmp -= stat_info->sw_stat.num_aggregations;
6480 count++;
6481 }
6482 tmp_stats[i++] = count;
fe931395 6483 }
bd1034f0
AR		 6484 else
6485 tmp_stats[i++] = 0;
c53d4945 6486 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6487 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6488 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6489 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6490 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6491 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6492 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6493 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6494 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6495
6496 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6497 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6498 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6499 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6500 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6501
6502 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6503 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6504 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6505 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6506 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6507 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6508 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6509 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6510 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6511 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6512 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6513 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6514 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6515 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6516 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6517 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6518 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6519 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6520 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6521 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6522 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6523 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6524 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6525 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6526 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6527 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6528}
6529
ac1f60db 6530static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6531{
6532 return (XENA_REG_SPACE);
6533}
6534
6535
ac1f60db 6536static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6537{
1ee6dd77 6538 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6539
6540 return (sp->rx_csum);
6541}
ac1f60db
AB		 6542
6543static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6544{
1ee6dd77 6545 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6546
6547 if (data)
6548 sp->rx_csum = 1;
6549 else
6550 sp->rx_csum = 0;
6551
6552 return 0;
6553}
ac1f60db
AB		 6554
6555static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6556{
6557 return (XENA_EEPROM_SPACE);
6558}
6559
b9f2c044 6560static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6561{
b9f2c044
JG		 6562 struct s2io_nic *sp = dev->priv;
6563
6564 switch (sset) {
6565 case ETH_SS_TEST:
6566 return S2IO_TEST_LEN;
6567 case ETH_SS_STATS:
6568 switch(sp->device_type) {
6569 case XFRAME_I_DEVICE:
6570 return XFRAME_I_STAT_LEN;
6571 case XFRAME_II_DEVICE:
6572 return XFRAME_II_STAT_LEN;
6573 default:
6574 return 0;
6575 }
6576 default:
6577 return -EOPNOTSUPP;
6578 }
1da177e4 6579}
ac1f60db
AB		 6580
6581static void s2io_ethtool_get_strings(struct net_device *dev,
6582 u32 stringset, u8 * data)
1da177e4 6583{
fa1f0cb3
SS		 6584 int stat_size = 0;
6585 struct s2io_nic *sp = dev->priv;
6586
1da177e4
LT		 6587 switch (stringset) {
6588 case ETH_SS_TEST:
6589 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6590 break;
6591 case ETH_SS_STATS:
fa1f0cb3
SS		 6592 stat_size = sizeof(ethtool_xena_stats_keys);
6593 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6594 if(sp->device_type == XFRAME_II_DEVICE) {
6595 memcpy(data + stat_size,
6596 &ethtool_enhanced_stats_keys,
6597 sizeof(ethtool_enhanced_stats_keys));
6598 stat_size += sizeof(ethtool_enhanced_stats_keys);
6599 }
6600
6601 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6602 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6603 }
6604}
1da177e4 6605
ac1f60db 6606static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6607{
6608 if (data)
6609 dev->features |= NETIF_F_IP_CSUM;
6610 else
6611 dev->features &= ~NETIF_F_IP_CSUM;
6612
6613 return 0;
6614}
6615
75c30b13
AR		 6616static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6617{
6618 return (dev->features & NETIF_F_TSO) != 0;
6619}
6620static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6621{
6622 if (data)
6623 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6624 else
6625 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6626
6627 return 0;
6628}
1da177e4 6629
7282d491 6630static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6631 .get_settings = s2io_ethtool_gset,
6632 .set_settings = s2io_ethtool_sset,
6633 .get_drvinfo = s2io_ethtool_gdrvinfo,
6634 .get_regs_len = s2io_ethtool_get_regs_len,
6635 .get_regs = s2io_ethtool_gregs,
6636 .get_link = ethtool_op_get_link,
6637 .get_eeprom_len = s2io_get_eeprom_len,
6638 .get_eeprom = s2io_ethtool_geeprom,
6639 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6640 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6641 .get_pauseparam = s2io_ethtool_getpause_data,
6642 .set_pauseparam = s2io_ethtool_setpause_data,
6643 .get_rx_csum = s2io_ethtool_get_rx_csum,
6644 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6645 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6646 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6647 .get_tso = s2io_ethtool_op_get_tso,
6648 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6649 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6650 .self_test = s2io_ethtool_test,
6651 .get_strings = s2io_ethtool_get_strings,
6652 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6653 .get_ethtool_stats = s2io_get_ethtool_stats,
6654 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6655};
6656
6657/**
20346722 6658 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6659 * @dev : Device pointer.
6660 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6661 * a proprietary structure used to pass information to the driver.
6662 * @cmd : This is used to distinguish between the different commands that
6663 * can be passed to the IOCTL functions.
6664 * Description:
20346722 6665 * Currently there are no special functionality supported in IOCTL, hence
6666 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6667 */
6668
ac1f60db 6669static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6670{
6671 return -EOPNOTSUPP;
6672}
6673
6674/**
6675 * s2io_change_mtu - entry point to change MTU size for the device.
6676 * @dev : device pointer.
6677 * @new_mtu : the new MTU size for the device.
6678 * Description: A driver entry point to change MTU size for the device.
6679 * Before changing the MTU the device must be stopped.
6680 * Return value:
6681 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6682 * file on failure.
6683 */
6684
ac1f60db 6685static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6686{
1ee6dd77 6687 struct s2io_nic *sp = dev->priv;
9f74ffde 6688 int ret = 0;
1da177e4
LT		 6689
6690 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6691 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6692 dev->name);
6693 return -EPERM;
6694 }
6695
1da177e4 6696 dev->mtu = new_mtu;
d8892c6e 6697 if (netif_running(dev)) {
3a3d5756 6698 s2io_stop_all_tx_queue(sp);
e6a8fee2 6699 s2io_card_down(sp);
9f74ffde
SH		 6700 ret = s2io_card_up(sp);
6701 if (ret) {
d8892c6e 6702 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6703 __FUNCTION__);
9f74ffde 6704 return ret;
d8892c6e 6705 }
3a3d5756 6706 s2io_wake_all_tx_queue(sp);
d8892c6e 6707 } else { /* Device is down */
1ee6dd77 6708 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6709 u64 val64 = new_mtu;
6710
6711 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6712 }
1da177e4 6713
9f74ffde 6714 return ret;
1da177e4
LT		 6715}
6716
1da177e4
LT		 6717/**
6718 * s2io_set_link - Set the LInk status
6719 * @data: long pointer to device private structue
6720 * Description: Sets the link status for the adapter
6721 */
6722
c4028958 6723static void s2io_set_link(struct work_struct *work)
1da177e4 6724{
1ee6dd77 6725 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6726 struct net_device *dev = nic->dev;
1ee6dd77 6727 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6728 register u64 val64;
6729 u16 subid;
6730
22747d6b
FR		 6731 rtnl_lock();
6732
6733 if (!netif_running(dev))
6734 goto out_unlock;
6735
92b84437 6736 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6737 /* The card is being reset, no point doing anything */
22747d6b 6738 goto out_unlock;
1da177e4
LT		 6739 }
6740
6741 subid = nic->pdev->subsystem_device;
a371a07d 6742 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6743 /*
6744 * Allow a small delay for the NICs self initiated
6745 * cleanup to complete.
6746 */
6747 msleep(100);
6748 }
1da177e4
LT		 6749
6750 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6751 if (LINK_IS_UP(val64)) {
6752 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6753 if (verify_xena_quiescence(nic)) {
6754 val64 = readq(&bar0->adapter_control);
6755 val64 |= ADAPTER_CNTL_EN;
1da177e4 6756 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6757 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6758 nic->device_type, subid)) {
6759 val64 = readq(&bar0->gpio_control);
6760 val64 |= GPIO_CTRL_GPIO_0;
6761 writeq(val64, &bar0->gpio_control);
6762 val64 = readq(&bar0->gpio_control);
6763 } else {
6764 val64 |= ADAPTER_LED_ON;
6765 writeq(val64, &bar0->adapter_control);
a371a07d 6766 }
1da177e4 6767 nic->device_enabled_once = TRUE;
19a60522
SS		 6768 } else {
6769 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6770 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6771 s2io_stop_all_tx_queue(nic);
1da177e4 6772 }
19a60522 6773 }
92c48799
SS		 6774 val64 = readq(&bar0->adapter_control);
6775 val64 |= ADAPTER_LED_ON;
6776 writeq(val64, &bar0->adapter_control);
6777 s2io_link(nic, LINK_UP);
19a60522
SS		 6778 } else {
6779 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6780 subid)) {
6781 val64 = readq(&bar0->gpio_control);
6782 val64 &= ~GPIO_CTRL_GPIO_0;
6783 writeq(val64, &bar0->gpio_control);
6784 val64 = readq(&bar0->gpio_control);
1da177e4 6785 }
92c48799
SS		 6786 /* turn off LED */
6787 val64 = readq(&bar0->adapter_control);
6788 val64 = val64 &(~ADAPTER_LED_ON);
6789 writeq(val64, &bar0->adapter_control);
19a60522 6790 s2io_link(nic, LINK_DOWN);
1da177e4 6791 }
92b84437 6792 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6793
6794out_unlock:
d8d70caf 6795 rtnl_unlock();
1da177e4
LT		 6796}
6797
1ee6dd77
RB		 6798static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6799 struct buffAdd *ba,
6800 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6801 u64 *temp2, int size)
5d3213cc
AR		 6802{
6803 struct net_device *dev = sp->dev;
491abf25 6804 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6805
6806 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6807 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6808 /* allocate skb */
6809 if (*skb) {
6810 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6811 /*
6812 * As Rx frame are not going to be processed,
6813 * using same mapped address for the Rxd
6814 * buffer pointer
6815 */
6d517a27 6816 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6817 } else {
6818 *skb = dev_alloc_skb(size);
6819 if (!(*skb)) {
0c61ed5f 6820 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6821 DBG_PRINT(INFO_DBG, "memory to allocate ");
6822 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6823 sp->mac_control.stats_info->sw_stat. \
6824 mem_alloc_fail_cnt++;
5d3213cc
AR		 6825 return -ENOMEM ;
6826 }
8a4bdbaa 6827 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6828 += (*skb)->truesize;
5d3213cc
AR		 6829 /* storing the mapped addr in a temp variable
6830 * such it will be used for next rxd whose
6831 * Host Control is NULL
6832 */
6d517a27 6833 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6834 pci_map_single( sp->pdev, (*skb)->data,
6835 size - NET_IP_ALIGN,
6836 PCI_DMA_FROMDEVICE);
491abf25
VP		 6837 if( (rxdp1->Buffer0_ptr == 0) ||
6838 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6839 goto memalloc_failed;
6840 }
5d3213cc
AR		 6841 rxdp->Host_Control = (unsigned long) (*skb);
6842 }
6843 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6844 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6845 /* Two buffer Mode */
6846 if (*skb) {
6d517a27
VP		 6847 rxdp3->Buffer2_ptr = *temp2;
6848 rxdp3->Buffer0_ptr = *temp0;
6849 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6850 } else {
6851 *skb = dev_alloc_skb(size);
2ceaac75 6852 if (!(*skb)) {
c53d4945
SH		 6853 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6854 DBG_PRINT(INFO_DBG, "memory to allocate ");
6855 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6856 sp->mac_control.stats_info->sw_stat. \
6857 mem_alloc_fail_cnt++;
2ceaac75
DR		 6858 return -ENOMEM;
6859 }
8a4bdbaa 6860 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6861 += (*skb)->truesize;
6d517a27 6862 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6863 pci_map_single(sp->pdev, (*skb)->data,
6864 dev->mtu + 4,
6865 PCI_DMA_FROMDEVICE);
491abf25
VP		 6866 if( (rxdp3->Buffer2_ptr == 0) ||
6867 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6868 goto memalloc_failed;
6869 }
6d517a27 6870 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6871 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6872 PCI_DMA_FROMDEVICE);
491abf25
VP		 6873 if( (rxdp3->Buffer0_ptr == 0) ||
6874 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6875 pci_unmap_single (sp->pdev,
3e847423 6876 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6877 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6878 goto memalloc_failed;
6879 }
5d3213cc
AR		 6880 rxdp->Host_Control = (unsigned long) (*skb);
6881
6882 /* Buffer-1 will be dummy buffer not used */
6d517a27 6883 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6884 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6885 PCI_DMA_FROMDEVICE);
491abf25
VP		 6886 if( (rxdp3->Buffer1_ptr == 0) ||
6887 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6888 pci_unmap_single (sp->pdev,
3e847423
AV		 6889 (dma_addr_t)rxdp3->Buffer0_ptr,
6890 BUF0_LEN, PCI_DMA_FROMDEVICE);
6891 pci_unmap_single (sp->pdev,
6892 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6893 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6894 goto memalloc_failed;
6895 }
5d3213cc
AR		 6896 }
6897 }
6898 return 0;
491abf25
VP		 6899 memalloc_failed:
6900 stats->pci_map_fail_cnt++;
6901 stats->mem_freed += (*skb)->truesize;
6902 dev_kfree_skb(*skb);
6903 return -ENOMEM;
5d3213cc 6904}
491abf25 6905
1ee6dd77
RB		 6906static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6907 int size)
5d3213cc
AR		 6908{
6909 struct net_device *dev = sp->dev;
6910 if (sp->rxd_mode == RXD_MODE_1) {
6911 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6912 } else if (sp->rxd_mode == RXD_MODE_3B) {
6913 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6914 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6915 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6916 }
6917}
6918
1ee6dd77 6919static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6920{
6921 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6922 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6923 struct config_param *config = &sp->config;
6924 struct net_device *dev = sp->dev;
1ee6dd77 6925 struct RxD_t *rxdp = NULL;
5d3213cc 6926 struct sk_buff *skb = NULL;
1ee6dd77 6927 struct buffAdd *ba = NULL;
5d3213cc
AR		 6928 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6929
6930 /* Calculate the size based on ring mode */
6931 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6932 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6933 if (sp->rxd_mode == RXD_MODE_1)
6934 size += NET_IP_ALIGN;
6935 else if (sp->rxd_mode == RXD_MODE_3B)
6936 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6937
6938 for (i = 0; i < config->rx_ring_num; i++) {
6939 blk_cnt = config->rx_cfg[i].num_rxd /
6940 (rxd_count[sp->rxd_mode] +1);
6941
6942 for (j = 0; j < blk_cnt; j++) {
6943 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6944 rxdp = mac_control->rings[i].
6945 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6946 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6947 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6948 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6949 &skb,(u64 *)&temp0_64,
6950 (u64 *)&temp1_64,
ac1f90d6
SS		 6951 (u64 *)&temp2_64,
6952 size) == ENOMEM) {
6953 return 0;
6954 }
5d3213cc
AR		 6955
6956 set_rxd_buffer_size(sp, rxdp, size);
6957 wmb();
6958 /* flip the Ownership bit to Hardware */
6959 rxdp->Control_1 |= RXD_OWN_XENA;
6960 }
6961 }
6962 }
6963 return 0;
6964
6965}
6966
1ee6dd77 6967static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6968{
e6a8fee2 6969 int ret = 0;
c92ca04b 6970 struct net_device *dev = sp->dev;
e6a8fee2 6971 int err = 0;
1da177e4 6972
eaae7f72 6973 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 6974 ret = s2io_enable_msi_x(sp);
6975 if (ret) {
6976 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 6977 sp->config.intr_type = INTA;
20346722 6978 }
1da177e4 6979
1ee6dd77 6980 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6981 store_xmsi_data(sp);
c92ca04b 6982
e6a8fee2 6983 /* After proper initialization of H/W, register ISR */
eaae7f72 6984 if (sp->config.intr_type == MSI_X) {
fb6a825b 6985 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6986
e6a8fee2
AR		 6987 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6988 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6989 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6990 dev->name, i);
6991 err = request_irq(sp->entries[i].vector,
6992 s2io_msix_fifo_handle, 0, sp->desc[i],
6993 sp->s2io_entries[i].arg);
fb6a825b
SS		 6994 /* If either data or addr is zero print it */
6995 if(!(sp->msix_info[i].addr &&
6996 sp->msix_info[i].data)) {
2450022a 6997 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
3459feb8 6998 "Data:0x%llx\n",sp->desc[i],
fb6a825b
SS		 6999 (unsigned long long)
7000 sp->msix_info[i].addr,
3459feb8
AV		 7001 (unsigned long long)
7002 sp->msix_info[i].data);
fb6a825b
SS		 7003 } else {
7004 msix_tx_cnt++;
7005 }
e6a8fee2
AR		 7006 } else {
7007 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7008 dev->name, i);
7009 err = request_irq(sp->entries[i].vector,
7010 s2io_msix_ring_handle, 0, sp->desc[i],
7011 sp->s2io_entries[i].arg);
fb6a825b
SS		 7012 /* If either data or addr is zero print it */
7013 if(!(sp->msix_info[i].addr &&
7014 sp->msix_info[i].data)) {
2450022a 7015 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
3459feb8 7016 "Data:0x%llx\n",sp->desc[i],
fb6a825b
SS		 7017 (unsigned long long)
7018 sp->msix_info[i].addr,
3459feb8
AV		 7019 (unsigned long long)
7020 sp->msix_info[i].data);
fb6a825b
SS		 7021 } else {
7022 msix_rx_cnt++;
7023 }
c92ca04b 7024 }
e6a8fee2 7025 if (err) {
18b2b7bd 7026 remove_msix_isr(sp);
e6a8fee2
AR		 7027 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
7028 "failed\n", dev->name, i);
18b2b7bd
SH		 7029 DBG_PRINT(ERR_DBG, "%s: defaulting to INTA\n",
7030 dev->name);
7031 sp->config.intr_type = INTA;
7032 break;
e6a8fee2
AR		 7033 }
7034 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
7035 }
18b2b7bd
SH		 7036 if (!err) {
7037 printk(KERN_INFO "MSI-X-TX %d entries enabled\n",
7038 msix_tx_cnt);
7039 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7040 msix_rx_cnt);
7041 }
e6a8fee2 7042 }
eaae7f72 7043 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7044 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7045 sp->name, dev);
7046 if (err) {
7047 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7048 dev->name);
7049 return -1;
7050 }
7051 }
7052 return 0;
7053}
1ee6dd77 7054static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7055{
18b2b7bd
SH		 7056 if (sp->config.intr_type == MSI_X)
7057 remove_msix_isr(sp);
7058 else
7059 remove_inta_isr(sp);
e6a8fee2
AR		 7060}
7061
d796fdb7 7062static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7063{
7064 int cnt = 0;
1ee6dd77 7065 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7066 register u64 val64 = 0;
5f490c96
SH		 7067 struct config_param *config;
7068 config = &sp->config;
e6a8fee2 7069
9f74ffde
SH		 7070 if (!is_s2io_card_up(sp))
7071 return;
7072
e6a8fee2
AR		 7073 del_timer_sync(&sp->alarm_timer);
7074 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7075 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7076 msleep(50);
7077 }
92b84437 7078 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7079
5f490c96
SH		 7080 /* Disable napi */
7081 if (config->napi)
7082 napi_disable(&sp->napi);
7083
e6a8fee2 7084 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7085 if (do_io)
7086 stop_nic(sp);
e6a8fee2
AR		 7087
7088 s2io_rem_isr(sp);
1da177e4 7089
1da177e4 7090 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7091 while(do_io) {
5d3213cc
AR		 7092 /* As per the HW requirement we need to replenish the
7093 * receive buffer to avoid the ring bump. Since there is
7094 * no intention of processing the Rx frame at this pointwe are
7095 * just settting the ownership bit of rxd in Each Rx
7096 * ring to HW and set the appropriate buffer size
7097 * based on the ring mode
7098 */
7099 rxd_owner_bit_reset(sp);
7100
1da177e4 7101 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7102 if (verify_xena_quiescence(sp)) {
7103 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7104 break;
7105 }
7106
7107 msleep(50);
7108 cnt++;
7109 if (cnt == 10) {
7110 DBG_PRINT(ERR_DBG,
7111 "s2io_close:Device not Quiescent ");
7112 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7113 (unsigned long long) val64);
7114 break;
7115 }
d796fdb7
LV		 7116 }
7117 if (do_io)
7118 s2io_reset(sp);
1da177e4 7119
7ba013ac 7120 /* Free all Tx buffers */
1da177e4 7121 free_tx_buffers(sp);
7ba013ac 7122
7123 /* Free all Rx buffers */
1da177e4
LT		 7124 free_rx_buffers(sp);
7125
92b84437 7126 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7127}
7128
d796fdb7
LV		 7129static void s2io_card_down(struct s2io_nic * sp)
7130{
7131 do_s2io_card_down(sp, 1);
7132}
7133
1ee6dd77 7134static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7135{
cc6e7c44 7136 int i, ret = 0;
1ee6dd77 7137 struct mac_info *mac_control;
1da177e4
LT		 7138 struct config_param *config;
7139 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7140 u16 interruptible;
1da177e4
LT		 7141
7142 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7143 ret = init_nic(sp);
7144 if (ret != 0) {
1da177e4
LT		 7145 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7146 dev->name);
9f74ffde
SH		 7147 if (ret != -EIO)
7148 s2io_reset(sp);
7149 return ret;
1da177e4
LT		 7150 }
7151
20346722 7152 /*
7153 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7154 * Rx ring and initializing buffers into 30 Rx blocks
7155 */
7156 mac_control = &sp->mac_control;
7157 config = &sp->config;
7158
7159 for (i = 0; i < config->rx_ring_num; i++) {
7160 if ((ret = fill_rx_buffers(sp, i))) {
7161 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7162 dev->name);
7163 s2io_reset(sp);
7164 free_rx_buffers(sp);
7165 return -ENOMEM;
7166 }
7167 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7168 atomic_read(&sp->rx_bufs_left[i]));
7169 }
5f490c96
SH		 7170
7171 /* Initialise napi */
7172 if (config->napi)
7173 napi_enable(&sp->napi);
7174
19a60522
SS		 7175 /* Maintain the state prior to the open */
7176 if (sp->promisc_flg)
7177 sp->promisc_flg = 0;
7178 if (sp->m_cast_flg) {
7179 sp->m_cast_flg = 0;
7180 sp->all_multi_pos= 0;
7181 }
1da177e4
LT		 7182
7183 /* Setting its receive mode */
7184 s2io_set_multicast(dev);
7185
7d3d0439 7186 if (sp->lro) {
b41477f3 7187 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7188 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7189 /* Check if we can use(if specified) user provided value */
7190 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7191 sp->lro_max_aggr_per_sess = lro_max_pkts;
7192 }
7193
1da177e4
LT		 7194 /* Enable Rx Traffic and interrupts on the NIC */
7195 if (start_nic(sp)) {
7196 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7197 s2io_reset(sp);
e6a8fee2
AR		 7198 free_rx_buffers(sp);
7199 return -ENODEV;
7200 }
7201
7202 /* Add interrupt service routine */
7203 if (s2io_add_isr(sp) != 0) {
eaae7f72 7204 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7205 s2io_rem_isr(sp);
7206 s2io_reset(sp);
1da177e4
LT		 7207 free_rx_buffers(sp);
7208 return -ENODEV;
7209 }
7210
25fff88e 7211 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7212
e6a8fee2 7213 /* Enable select interrupts */
9caab458 7214 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
eaae7f72 7215 if (sp->config.intr_type != INTA)
e6a8fee2
AR		 7216 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
7217 else {
7218 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7219 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7220 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7221 }
7222
92b84437 7223 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
1da177e4
LT		 7224 return 0;
7225}
7226
20346722 7227/**
1da177e4
LT		 7228 * s2io_restart_nic - Resets the NIC.
7229 * @data : long pointer to the device private structure
7230 * Description:
7231 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7232 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7233 * the run time of the watch dog routine which is run holding a
7234 * spin lock.
7235 */
7236
c4028958 7237static void s2io_restart_nic(struct work_struct *work)
1da177e4 7238{
1ee6dd77 7239 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7240 struct net_device *dev = sp->dev;
1da177e4 7241
22747d6b
FR		 7242 rtnl_lock();
7243
7244 if (!netif_running(dev))
7245 goto out_unlock;
7246
e6a8fee2 7247 s2io_card_down(sp);
1da177e4
LT		 7248 if (s2io_card_up(sp)) {
7249 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7250 dev->name);
7251 }
3a3d5756 7252 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7253 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7254 dev->name);
22747d6b
FR		 7255out_unlock:
7256 rtnl_unlock();
1da177e4
LT		 7257}
7258
20346722 7259/**
7260 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7261 * @dev : Pointer to net device structure
7262 * Description:
7263 * This function is triggered if the Tx Queue is stopped
7264 * for a pre-defined amount of time when the Interface is still up.
7265 * If the Interface is jammed in such a situation, the hardware is
7266 * reset (by s2io_close) and restarted again (by s2io_open) to
7267 * overcome any problem that might have been caused in the hardware.
7268 * Return value:
7269 * void
7270 */
7271
7272static void s2io_tx_watchdog(struct net_device *dev)
7273{
1ee6dd77 7274 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 7275
7276 if (netif_carrier_ok(dev)) {
c53d4945 7277 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7278 schedule_work(&sp->rst_timer_task);
bd1034f0 7279 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7280 }
7281}
7282
7283/**
7284 * rx_osm_handler - To perform some OS related operations on SKB.
7285 * @sp: private member of the device structure,pointer to s2io_nic structure.
7286 * @skb : the socket buffer pointer.
7287 * @len : length of the packet
7288 * @cksum : FCS checksum of the frame.
7289 * @ring_no : the ring from which this RxD was extracted.
20346722 7290 * Description:
b41477f3 7291 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7292 * some OS related operations on the SKB before passing it to the upper
7293 * layers. It mainly checks if the checksum is OK, if so adds it to the
7294 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7295 * to the upper layer. If the checksum is wrong, it increments the Rx
7296 * packet error count, frees the SKB and returns error.
7297 * Return value:
7298 * SUCCESS on success and -1 on failure.
7299 */
1ee6dd77 7300static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7301{
1ee6dd77 7302 struct s2io_nic *sp = ring_data->nic;
1da177e4 7303 struct net_device *dev = (struct net_device *) sp->dev;
20346722 7304 struct sk_buff *skb = (struct sk_buff *)
7305 ((unsigned long) rxdp->Host_Control);
7306 int ring_no = ring_data->ring_no;
1da177e4 7307 u16 l3_csum, l4_csum;
863c11a9 7308 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 7309 struct lro *lro;
f9046eb3 7310 u8 err_mask;
da6971d8 7311
20346722 7312 skb->dev = dev;
c92ca04b 7313
863c11a9 7314 if (err) {
bd1034f0
AR		 7315 /* Check for parity error */
7316 if (err & 0x1) {
7317 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7318 }
f9046eb3
OH		 7319 err_mask = err >> 48;
7320 switch(err_mask) {
491976b2
SH		 7321 case 1:
7322 sp->mac_control.stats_info->sw_stat.
7323 rx_parity_err_cnt++;
7324 break;
7325
7326 case 2:
7327 sp->mac_control.stats_info->sw_stat.
7328 rx_abort_cnt++;
7329 break;
7330
7331 case 3:
7332 sp->mac_control.stats_info->sw_stat.
7333 rx_parity_abort_cnt++;
7334 break;
7335
7336 case 4:
7337 sp->mac_control.stats_info->sw_stat.
7338 rx_rda_fail_cnt++;
7339 break;
7340
7341 case 5:
7342 sp->mac_control.stats_info->sw_stat.
7343 rx_unkn_prot_cnt++;
7344 break;
7345
7346 case 6:
7347 sp->mac_control.stats_info->sw_stat.
7348 rx_fcs_err_cnt++;
7349 break;
bd1034f0 7350
491976b2
SH		 7351 case 7:
7352 sp->mac_control.stats_info->sw_stat.
7353 rx_buf_size_err_cnt++;
7354 break;
7355
7356 case 8:
7357 sp->mac_control.stats_info->sw_stat.
7358 rx_rxd_corrupt_cnt++;
7359 break;
7360
7361 case 15:
7362 sp->mac_control.stats_info->sw_stat.
7363 rx_unkn_err_cnt++;
7364 break;
7365 }
863c11a9
AR		 7366 /*
7367 * Drop the packet if bad transfer code. Exception being
7368 * 0x5, which could be due to unsupported IPv6 extension header.
7369 * In this case, we let stack handle the packet.
7370 * Note that in this case, since checksum will be incorrect,
7371 * stack will validate the same.
7372 */
f9046eb3
OH		 7373 if (err_mask != 0x5) {
7374 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7375 dev->name, err_mask);
863c11a9 7376 sp->stats.rx_crc_errors++;
8a4bdbaa 7377 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7378 += skb->truesize;
863c11a9
AR		 7379 dev_kfree_skb(skb);
7380 atomic_dec(&sp->rx_bufs_left[ring_no]);
7381 rxdp->Host_Control = 0;
7382 return 0;
7383 }
20346722 7384 }
1da177e4 7385
20346722 7386 /* Updating statistics */
573608e4 7387 sp->stats.rx_packets++;
20346722 7388 rxdp->Host_Control = 0;
da6971d8
AR		 7389 if (sp->rxd_mode == RXD_MODE_1) {
7390 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7391
da6971d8
AR		 7392 sp->stats.rx_bytes += len;
7393 skb_put(skb, len);
7394
6d517a27 7395 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7396 int get_block = ring_data->rx_curr_get_info.block_index;
7397 int get_off = ring_data->rx_curr_get_info.offset;
7398 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7399 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7400 unsigned char *buff = skb_push(skb, buf0_len);
7401
1ee6dd77 7402 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 7403 sp->stats.rx_bytes += buf0_len + buf2_len;
7404 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7405 skb_put(skb, buf2_len);
da6971d8 7406 }
20346722 7407
7d3d0439
RA		 7408 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7409 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 7410 (sp->rx_csum)) {
7411 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7412 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7413 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7414 /*
1da177e4
LT		 7415 * NIC verifies if the Checksum of the received
7416 * frame is Ok or not and accordingly returns
7417 * a flag in the RxD.
7418 */
7419 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 7420 if (sp->lro) {
7421 u32 tcp_len;
7422 u8 *tcp;
7423 int ret = 0;
7424
7425 ret = s2io_club_tcp_session(skb->data, &tcp,
43b7c451
SH		 7426 &tcp_len, &lro,
7427 rxdp, sp);
7d3d0439
RA		 7428 switch (ret) {
7429 case 3: /* Begin anew */
7430 lro->parent = skb;
7431 goto aggregate;
7432 case 1: /* Aggregate */
7433 {
7434 lro_append_pkt(sp, lro,
7435 skb, tcp_len);
7436 goto aggregate;
7437 }
7438 case 4: /* Flush session */
7439 {
7440 lro_append_pkt(sp, lro,
7441 skb, tcp_len);
cdb5bf02
SH		 7442 queue_rx_frame(lro->parent,
7443 lro->vlan_tag);
7d3d0439
RA		 7444 clear_lro_session(lro);
7445 sp->mac_control.stats_info->
7446 sw_stat.flush_max_pkts++;
7447 goto aggregate;
7448 }
7449 case 2: /* Flush both */
7450 lro->parent->data_len =
7451 lro->frags_len;
7452 sp->mac_control.stats_info->
7453 sw_stat.sending_both++;
cdb5bf02
SH		 7454 queue_rx_frame(lro->parent,
7455 lro->vlan_tag);
7d3d0439
RA		 7456 clear_lro_session(lro);
7457 goto send_up;
7458 case 0: /* sessions exceeded */
c92ca04b
AR		 7459 case -1: /* non-TCP or not
7460 * L2 aggregatable
7461 */
7d3d0439
RA		 7462 case 5: /*
7463 * First pkt in session not
7464 * L3/L4 aggregatable
7465 */
7466 break;
7467 default:
7468 DBG_PRINT(ERR_DBG,
7469 "%s: Samadhana!!\n",
7470 __FUNCTION__);
7471 BUG();
7472 }
7473 }
1da177e4 7474 } else {
20346722 7475 /*
7476 * Packet with erroneous checksum, let the
1da177e4
LT		 7477 * upper layers deal with it.
7478 */
7479 skb->ip_summed = CHECKSUM_NONE;
7480 }
cdb5bf02 7481 } else
1da177e4 7482 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7483
491976b2 7484 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7485send_up:
cdb5bf02 7486 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
1da177e4 7487 dev->last_rx = jiffies;
7d3d0439 7488aggregate:
1da177e4 7489 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 7490 return SUCCESS;
7491}
7492
7493/**
7494 * s2io_link - stops/starts the Tx queue.
7495 * @sp : private member of the device structure, which is a pointer to the
7496 * s2io_nic structure.
7497 * @link : inidicates whether link is UP/DOWN.
7498 * Description:
7499 * This function stops/starts the Tx queue depending on whether the link
20346722 7500 * status of the NIC is is down or up. This is called by the Alarm
7501 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7502 * Return value:
7503 * void.
7504 */
7505
1ee6dd77 7506static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7507{
7508 struct net_device *dev = (struct net_device *) sp->dev;
7509
7510 if (link != sp->last_link_state) {
b7c5678f 7511 init_tti(sp, link);
1da177e4
LT		 7512 if (link == LINK_DOWN) {
7513 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7514 s2io_stop_all_tx_queue(sp);
1da177e4 7515 netif_carrier_off(dev);
491976b2 7516 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7517 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7518 jiffies - sp->start_time;
7519 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7520 } else {
7521 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7522 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7523 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7524 jiffies - sp->start_time;
7525 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7526 netif_carrier_on(dev);
3a3d5756 7527 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7528 }
7529 }
7530 sp->last_link_state = link;
491976b2 7531 sp->start_time = jiffies;
1da177e4
LT		 7532}
7533
20346722 7534/**
7535 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7536 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7537 * s2io_nic structure.
7538 * Description:
7539 * This function initializes a few of the PCI and PCI-X configuration registers
7540 * with recommended values.
7541 * Return value:
7542 * void
7543 */
7544
1ee6dd77 7545static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7546{
20346722 7547 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7548
7549 /* Enable Data Parity Error Recovery in PCI-X command register. */
7550 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7551 &(pcix_cmd));
1da177e4 7552 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7553 (pcix_cmd | 1));
1da177e4 7554 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7555 &(pcix_cmd));
1da177e4
LT		 7556
7557 /* Set the PErr Response bit in PCI command register. */
7558 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7559 pci_write_config_word(sp->pdev, PCI_COMMAND,
7560 (pci_cmd | PCI_COMMAND_PARITY));
7561 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7562}
7563
3a3d5756
SH		 7564static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7565 u8 *dev_multiq)
9dc737a7 7566{
2fda096d 7567 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7568 (tx_fifo_num < 1)) {
2fda096d
SR		 7569 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7570 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7571
7572 if (tx_fifo_num < 1)
7573 tx_fifo_num = 1;
7574 else
7575 tx_fifo_num = MAX_TX_FIFOS;
7576
2fda096d
SR		 7577 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7578 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7579 }
2fda096d 7580
3a3d5756
SH		 7581#ifndef CONFIG_NETDEVICES_MULTIQUEUE
7582 if (multiq) {
7583 DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
7584 multiq = 0;
7585 }
7586#endif
6cfc482b 7587 if (multiq)
3a3d5756 7588 *dev_multiq = multiq;
6cfc482b
SH		 7589
7590 if (tx_steering_type && (1 == tx_fifo_num)) {
7591 if (tx_steering_type != TX_DEFAULT_STEERING)
7592 DBG_PRINT(ERR_DBG,
7593 "s2io: Tx steering is not supported with "
7594 "one fifo. Disabling Tx steering.\n");
7595 tx_steering_type = NO_STEERING;
7596 }
7597
7598 if ((tx_steering_type < NO_STEERING) ||
7599 (tx_steering_type > TX_DEFAULT_STEERING)) {
7600 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7601 "supported\n");
7602 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7603 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7604 }
7605
9dc737a7
AR		 7606 if ( rx_ring_num > 8) {
7607 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7608 "supported\n");
7609 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7610 rx_ring_num = 8;
7611 }
db874e65
SS		 7612 if (*dev_intr_type != INTA)
7613 napi = 0;
7614
eccb8628 7615 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7616 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7617 "Defaulting to INTA\n");
7618 *dev_intr_type = INTA;
7619 }
596c5c97 7620
9dc737a7
AR		 7621 if ((*dev_intr_type == MSI_X) &&
7622 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7623 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7624 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7625 "Defaulting to INTA\n");
7626 *dev_intr_type = INTA;
7627 }
fb6a825b 7628
6d517a27 7629 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7630 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7631 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7632 rx_ring_mode = 1;
9dc737a7
AR		 7633 }
7634 return SUCCESS;
7635}
7636
9fc93a41
SS		 7637/**
7638 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7639 * or Traffic class respectively.
b7c5678f 7640 * @nic: device private variable
9fc93a41
SS		 7641 * Description: The function configures the receive steering to
7642 * desired receive ring.
7643 * Return Value: SUCCESS on success and
7644 * '-1' on failure (endian settings incorrect).
7645 */
7646static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7647{
7648 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7649 register u64 val64 = 0;
7650
7651 if (ds_codepoint > 63)
7652 return FAILURE;
7653
7654 val64 = RTS_DS_MEM_DATA(ring);
7655 writeq(val64, &bar0->rts_ds_mem_data);
7656
7657 val64 = RTS_DS_MEM_CTRL_WE |
7658 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7659 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7660
7661 writeq(val64, &bar0->rts_ds_mem_ctrl);
7662
7663 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7664 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7665 S2IO_BIT_RESET);
7666}
7667
1da177e4 7668/**
20346722 7669 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7670 * @pdev : structure containing the PCI related information of the device.
7671 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7672 * Description:
7673 * The function initializes an adapter identified by the pci_dec structure.
20346722 7674 * All OS related initialization including memory and device structure and
7675 * initlaization of the device private variable is done. Also the swapper
7676 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7677 * registers of the device.
7678 * Return value:
7679 * returns 0 on success and negative on failure.
7680 */
7681
7682static int __devinit
7683s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7684{
1ee6dd77 7685 struct s2io_nic *sp;
1da177e4 7686 struct net_device *dev;
1da177e4
LT		 7687 int i, j, ret;
7688 int dma_flag = FALSE;
7689 u32 mac_up, mac_down;
7690 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7691 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7692 u16 subid;
1ee6dd77 7693 struct mac_info *mac_control;
1da177e4 7694 struct config_param *config;
541ae68f 7695 int mode;
cc6e7c44 7696 u8 dev_intr_type = intr_type;
3a3d5756 7697 u8 dev_multiq = 0;
0795af57 7698 DECLARE_MAC_BUF(mac);
1da177e4 7699
3a3d5756
SH		 7700 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7701 if (ret)
9dc737a7 7702 return ret;
1da177e4
LT		 7703
7704 if ((ret = pci_enable_device(pdev))) {
7705 DBG_PRINT(ERR_DBG,
7706 "s2io_init_nic: pci_enable_device failed\n");
7707 return ret;
7708 }
7709
1e7f0bd8 7710 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7711 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7712 dma_flag = TRUE;
1da177e4 7713 if (pci_set_consistent_dma_mask
1e7f0bd8 7714 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7715 DBG_PRINT(ERR_DBG,
7716 "Unable to obtain 64bit DMA for \
7717 consistent allocations\n");
7718 pci_disable_device(pdev);
7719 return -ENOMEM;
7720 }
1e7f0bd8 7721 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7722 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7723 } else {
7724 pci_disable_device(pdev);
7725 return -ENOMEM;
7726 }
eccb8628
VP		 7727 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7728 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7729 pci_disable_device(pdev);
7730 return -ENODEV;
1da177e4 7731 }
3a3d5756
SH		 7732#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7733 if (dev_multiq)
6cfc482b 7734 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756
SH		 7735 else
7736#endif
1ee6dd77 7737 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7738 if (dev == NULL) {
7739 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7740 pci_disable_device(pdev);
7741 pci_release_regions(pdev);
7742 return -ENODEV;
7743 }
7744
7745 pci_set_master(pdev);
7746 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7747 SET_NETDEV_DEV(dev, &pdev->dev);
7748
7749 /* Private member variable initialized to s2io NIC structure */
7750 sp = dev->priv;
1ee6dd77 7751 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7752 sp->dev = dev;
7753 sp->pdev = pdev;
1da177e4 7754 sp->high_dma_flag = dma_flag;
1da177e4 7755 sp->device_enabled_once = FALSE;
da6971d8
AR		 7756 if (rx_ring_mode == 1)
7757 sp->rxd_mode = RXD_MODE_1;
7758 if (rx_ring_mode == 2)
7759 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7760
eaae7f72 7761 sp->config.intr_type = dev_intr_type;
1da177e4 7762
541ae68f 7763 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7764 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7765 sp->device_type = XFRAME_II_DEVICE;
7766 else
7767 sp->device_type = XFRAME_I_DEVICE;
7768
43b7c451 7769 sp->lro = lro_enable;
6aa20a22 7770
1da177e4
LT		 7771 /* Initialize some PCI/PCI-X fields of the NIC. */
7772 s2io_init_pci(sp);
7773
20346722 7774 /*
1da177e4 7775 * Setting the device configuration parameters.
20346722 7776 * Most of these parameters can be specified by the user during
7777 * module insertion as they are module loadable parameters. If
7778 * these parameters are not not specified during load time, they
1da177e4
LT		 7779 * are initialized with default values.
7780 */
7781 mac_control = &sp->mac_control;
7782 config = &sp->config;
7783
596c5c97 7784 config->napi = napi;
6cfc482b 7785 config->tx_steering_type = tx_steering_type;
596c5c97 7786
1da177e4 7787 /* Tx side parameters. */
6cfc482b
SH		 7788 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7789 config->tx_fifo_num = MAX_TX_FIFOS;
7790 else
7791 config->tx_fifo_num = tx_fifo_num;
7792
7793 /* Initialize the fifos used for tx steering */
7794 if (config->tx_fifo_num < 5) {
7795 if (config->tx_fifo_num == 1)
7796 sp->total_tcp_fifos = 1;
7797 else
7798 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7799 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7800 sp->total_udp_fifos = 1;
7801 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7802 } else {
7803 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7804 FIFO_OTHER_MAX_NUM);
7805 sp->udp_fifo_idx = sp->total_tcp_fifos;
7806 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7807 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7808 }
7809
3a3d5756 7810 config->multiq = dev_multiq;
6cfc482b 7811 for (i = 0; i < config->tx_fifo_num; i++) {
1da177e4
LT		 7812 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7813 config->tx_cfg[i].fifo_priority = i;
7814 }
7815
20346722 7816 /* mapping the QoS priority to the configured fifos */
7817 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7818 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7819
6cfc482b
SH		 7820 /* map the hashing selector table to the configured fifos */
7821 for (i = 0; i < config->tx_fifo_num; i++)
7822 sp->fifo_selector[i] = fifo_selector[i];
7823
7824
1da177e4
LT		 7825 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7826 for (i = 0; i < config->tx_fifo_num; i++) {
7827 config->tx_cfg[i].f_no_snoop =
7828 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7829 if (config->tx_cfg[i].fifo_len < 65) {
7830 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7831 break;
7832 }
7833 }
fed5eccd
AR		 7834 /* + 2 because one Txd for skb->data and one Txd for UFO */
7835 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7836
7837 /* Rx side parameters. */
1da177e4
LT		 7838 config->rx_ring_num = rx_ring_num;
7839 for (i = 0; i < MAX_RX_RINGS; i++) {
7840 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7841 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7842 config->rx_cfg[i].ring_priority = i;
7843 }
7844
7845 for (i = 0; i < rx_ring_num; i++) {
7846 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7847 config->rx_cfg[i].f_no_snoop =
7848 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7849 }
7850
7851 /* Setting Mac Control parameters */
7852 mac_control->rmac_pause_time = rmac_pause_time;
7853 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7854 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7855
7856
7857 /* Initialize Ring buffer parameters. */
7858 for (i = 0; i < config->rx_ring_num; i++)
7859 atomic_set(&sp->rx_bufs_left[i], 0);
7860
7861 /* initialize the shared memory used by the NIC and the host */
7862 if (init_shared_mem(sp)) {
7863 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7864 dev->name);
1da177e4
LT		 7865 ret = -ENOMEM;
7866 goto mem_alloc_failed;
7867 }
7868
7869 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7870 pci_resource_len(pdev, 0));
7871 if (!sp->bar0) {
19a60522 7872 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7873 dev->name);
7874 ret = -ENOMEM;
7875 goto bar0_remap_failed;
7876 }
7877
7878 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7879 pci_resource_len(pdev, 2));
7880 if (!sp->bar1) {
19a60522 7881 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7882 dev->name);
7883 ret = -ENOMEM;
7884 goto bar1_remap_failed;
7885 }
7886
7887 dev->irq = pdev->irq;
7888 dev->base_addr = (unsigned long) sp->bar0;
7889
7890 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7891 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7892 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7893 (sp->bar1 + (j * 0x00020000));
7894 }
7895
7896 /* Driver entry points */
7897 dev->open = &s2io_open;
7898 dev->stop = &s2io_close;
7899 dev->hard_start_xmit = &s2io_xmit;
7900 dev->get_stats = &s2io_get_stats;
7901 dev->set_multicast_list = &s2io_set_multicast;
7902 dev->do_ioctl = &s2io_ioctl;
2fd37688 7903 dev->set_mac_address = &s2io_set_mac_addr;
1da177e4
LT		 7904 dev->change_mtu = &s2io_change_mtu;
7905 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7906 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7907 dev->vlan_rx_register = s2io_vlan_rx_register;
cdb5bf02 7908 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 7909
1da177e4
LT		 7910 /*
7911 * will use eth_mac_addr() for dev->set_mac_address
7912 * mac address will be set every time dev->open() is called
7913 */
bea3348e 7914 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
1da177e4 7915
612eff0e
BH		 7916#ifdef CONFIG_NET_POLL_CONTROLLER
7917 dev->poll_controller = s2io_netpoll;
7918#endif
7919
1da177e4
LT		 7920 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7921 if (sp->high_dma_flag == TRUE)
7922 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7923 dev->features |= NETIF_F_TSO;
f83ef8c0 7924 dev->features |= NETIF_F_TSO6;
db874e65 7925 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7926 dev->features |= NETIF_F_UFO;
7927 dev->features |= NETIF_F_HW_CSUM;
7928 }
3a3d5756
SH		 7929#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7930 if (config->multiq)
7931 dev->features |= NETIF_F_MULTI_QUEUE;
7932#endif
1da177e4
LT		 7933 dev->tx_timeout = &s2io_tx_watchdog;
7934 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7935 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7936 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7937
e960fc5c 7938 pci_save_state(sp->pdev);
1da177e4
LT		 7939
7940 /* Setting swapper control on the NIC, for proper reset operation */
7941 if (s2io_set_swapper(sp)) {
7942 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7943 dev->name);
7944 ret = -EAGAIN;
7945 goto set_swap_failed;
7946 }
7947
541ae68f 7948 /* Verify if the Herc works on the slot its placed into */
7949 if (sp->device_type & XFRAME_II_DEVICE) {
7950 mode = s2io_verify_pci_mode(sp);
7951 if (mode < 0) {
7952 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7953 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7954 ret = -EBADSLT;
7955 goto set_swap_failed;
7956 }
7957 }
7958
7959 /* Not needed for Herc */
7960 if (sp->device_type & XFRAME_I_DEVICE) {
7961 /*
7962 * Fix for all "FFs" MAC address problems observed on
7963 * Alpha platforms
7964 */
7965 fix_mac_address(sp);
7966 s2io_reset(sp);
7967 }
1da177e4
LT		 7968
7969 /*
1da177e4
LT		 7970 * MAC address initialization.
7971 * For now only one mac address will be read and used.
7972 */
7973 bar0 = sp->bar0;
7974 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 7975 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 7976 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7977 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7978 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7979 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7980 mac_down = (u32) tmp64;
7981 mac_up = (u32) (tmp64 >> 32);
7982
1da177e4
LT		 7983 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7984 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7985 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7986 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7987 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7988 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7989
1da177e4
LT		 7990 /* Set the factory defined MAC address initially */
7991 dev->addr_len = ETH_ALEN;
7992 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 7993 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 7994
faa4f796
SH		 7995 /* initialize number of multicast & unicast MAC entries variables */
7996 if (sp->device_type == XFRAME_I_DEVICE) {
7997 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7998 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7999 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8000 } else if (sp->device_type == XFRAME_II_DEVICE) {
8001 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8002 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8003 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8004 }
8005
8006 /* store mac addresses from CAM to s2io_nic structure */
8007 do_s2io_store_unicast_mc(sp);
8008
c77dd43e
SS		 8009 /* Store the values of the MSIX table in the s2io_nic structure */
8010 store_xmsi_data(sp);
b41477f3
AR		 8011 /* reset Nic and bring it to known state */
8012 s2io_reset(sp);
8013
1da177e4 8014 /*
99993af6 8015 * Initialize link state flags
541ae68f 8016 * and the card state parameter
1da177e4 8017 */
92b84437 8018 sp->state = 0;
1da177e4 8019
1da177e4 8020 /* Initialize spinlocks */
2fda096d
SR		 8021 for (i = 0; i < sp->config.tx_fifo_num; i++)
8022 spin_lock_init(&mac_control->fifos[i].tx_lock);
db874e65 8023
20346722 8024 /*
8025 * SXE-002: Configure link and activity LED to init state
8026 * on driver load.
1da177e4
LT		 8027 */
8028 subid = sp->pdev->subsystem_device;
8029 if ((subid & 0xFF) >= 0x07) {
8030 val64 = readq(&bar0->gpio_control);
8031 val64 |= 0x0000800000000000ULL;
8032 writeq(val64, &bar0->gpio_control);
8033 val64 = 0x0411040400000000ULL;
8034 writeq(val64, (void __iomem *) bar0 + 0x2700);
8035 val64 = readq(&bar0->gpio_control);
8036 }
8037
8038 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8039
8040 if (register_netdev(dev)) {
8041 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8042 ret = -ENODEV;
8043 goto register_failed;
8044 }
9dc737a7 8045 s2io_vpd_read(sp);
0c61ed5f 8046 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8047 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8048 sp->product_name, pdev->revision);
b41477f3
AR		 8049 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8050 s2io_driver_version);
0795af57
JP		 8051 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
8052 dev->name, print_mac(mac, dev->dev_addr));
19a60522 8053 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8054 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8055 mode = s2io_print_pci_mode(sp);
541ae68f 8056 if (mode < 0) {
9dc737a7 8057 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8058 ret = -EBADSLT;
9dc737a7 8059 unregister_netdev(dev);
541ae68f 8060 goto set_swap_failed;
8061 }
541ae68f 8062 }
9dc737a7
AR		 8063 switch(sp->rxd_mode) {
8064 case RXD_MODE_1:
8065 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8066 dev->name);
8067 break;
8068 case RXD_MODE_3B:
8069 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8070 dev->name);
8071 break;
9dc737a7 8072 }
db874e65
SS		 8073
8074 if (napi)
8075 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
3a3d5756
SH		 8076
8077 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8078 sp->config.tx_fifo_num);
8079
eaae7f72 8080 switch(sp->config.intr_type) {
9dc737a7
AR		 8081 case INTA:
8082 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8083 break;
9dc737a7
AR		 8084 case MSI_X:
8085 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8086 break;
8087 }
3a3d5756
SH		 8088 if (sp->config.multiq) {
8089 for (i = 0; i < sp->config.tx_fifo_num; i++)
8090 mac_control->fifos[i].multiq = config->multiq;
8091 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8092 dev->name);
8093 } else
8094 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8095 dev->name);
8096
6cfc482b
SH		 8097 switch (sp->config.tx_steering_type) {
8098 case NO_STEERING:
8099 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8100 " transmit\n", dev->name);
8101 break;
8102 case TX_PRIORITY_STEERING:
8103 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8104 " transmit\n", dev->name);
8105 break;
8106 case TX_DEFAULT_STEERING:
8107 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8108 " transmit\n", dev->name);
8109 }
8110
7d3d0439
RA		 8111 if (sp->lro)
8112 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8113 dev->name);
db874e65
SS		 8114 if (ufo)
8115 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8116 " enabled\n", dev->name);
7ba013ac 8117 /* Initialize device name */
9dc737a7 8118 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8119
20346722 8120 /*
8121 * Make Link state as off at this point, when the Link change
8122 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8123 * the right state.
8124 */
8125 netif_carrier_off(dev);
1da177e4
LT		 8126
8127 return 0;
8128
8129 register_failed:
8130 set_swap_failed:
8131 iounmap(sp->bar1);
8132 bar1_remap_failed:
8133 iounmap(sp->bar0);
8134 bar0_remap_failed:
8135 mem_alloc_failed:
8136 free_shared_mem(sp);
8137 pci_disable_device(pdev);
eccb8628 8138 pci_release_regions(pdev);
1da177e4
LT		 8139 pci_set_drvdata(pdev, NULL);
8140 free_netdev(dev);
8141
8142 return ret;
8143}
8144
8145/**
20346722 8146 * s2io_rem_nic - Free the PCI device
1da177e4 8147 * @pdev: structure containing the PCI related information of the device.
20346722 8148 * Description: This function is called by the Pci subsystem to release a
1da177e4 8149 * PCI device and free up all resource held up by the device. This could
20346722 8150 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8151 * from memory.
8152 */
8153
8154static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8155{
8156 struct net_device *dev =
8157 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8158 struct s2io_nic *sp;
1da177e4
LT		 8159
8160 if (dev == NULL) {
8161 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8162 return;
8163 }
8164
22747d6b
FR		 8165 flush_scheduled_work();
8166
1da177e4
LT		 8167 sp = dev->priv;
8168 unregister_netdev(dev);
8169
8170 free_shared_mem(sp);
8171 iounmap(sp->bar0);
8172 iounmap(sp->bar1);
eccb8628 8173 pci_release_regions(pdev);
1da177e4 8174 pci_set_drvdata(pdev, NULL);
1da177e4 8175 free_netdev(dev);
19a60522 8176 pci_disable_device(pdev);
1da177e4
LT		 8177}
8178
8179/**
8180 * s2io_starter - Entry point for the driver
8181 * Description: This function is the entry point for the driver. It verifies
8182 * the module loadable parameters and initializes PCI configuration space.
8183 */
8184
43b7c451 8185static int __init s2io_starter(void)
1da177e4 8186{
29917620 8187 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8188}
8189
8190/**
20346722 8191 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8192 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8193 */
8194
372cc597 8195static __exit void s2io_closer(void)
1da177e4
LT		 8196{
8197 pci_unregister_driver(&s2io_driver);
8198 DBG_PRINT(INIT_DBG, "cleanup done\n");
8199}
8200
8201module_init(s2io_starter);
8202module_exit(s2io_closer);
7d3d0439 8203
6aa20a22 8204static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8205 struct tcphdr **tcp, struct RxD_t *rxdp,
8206 struct s2io_nic *sp)
7d3d0439
RA		 8207{
8208 int ip_off;
8209 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8210
8211 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8212 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8213 __FUNCTION__);
8214 return -1;
8215 }
8216
cdb5bf02
SH		 8217 /* Checking for DIX type or DIX type with VLAN */
8218 if ((l2_type == 0)
8219 || (l2_type == 4)) {
8220 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8221 /*
8222 * If vlan stripping is disabled and the frame is VLAN tagged,
8223 * shift the offset by the VLAN header size bytes.
8224 */
8225 if ((!vlan_strip_flag) &&
8226 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8227 ip_off += HEADER_VLAN_SIZE;
8228 } else {
7d3d0439 8229 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8230 return -1;
7d3d0439
RA		 8231 }
8232
8233 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8234 ip_len = (u8)((*ip)->ihl);
8235 ip_len <<= 2;
8236 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8237
8238 return 0;
8239}
8240
1ee6dd77 8241static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8242 struct tcphdr *tcp)
8243{
8244 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8245 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8246 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8247 return -1;
8248 return 0;
8249}
8250
8251static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8252{
8253 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8254}
8255
1ee6dd77 8256static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8257 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439
RA		 8258{
8259 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8260 lro->l2h = l2h;
8261 lro->iph = ip;
8262 lro->tcph = tcp;
8263 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8264 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8265 lro->sg_num = 1;
8266 lro->total_len = ntohs(ip->tot_len);
8267 lro->frags_len = 0;
cdb5bf02 8268 lro->vlan_tag = vlan_tag;
6aa20a22 8269 /*
7d3d0439
RA		 8270 * check if we saw TCP timestamp. Other consistency checks have
8271 * already been done.
8272 */
8273 if (tcp->doff == 8) {
c8855953
SR		 8274 __be32 *ptr;
8275 ptr = (__be32 *)(tcp+1);
7d3d0439 8276 lro->saw_ts = 1;
c8855953 8277 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8278 lro->cur_tsecr = *(ptr+2);
8279 }
8280 lro->in_use = 1;
8281}
8282
1ee6dd77 8283static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8284{
8285 struct iphdr *ip = lro->iph;
8286 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8287 __sum16 nchk;
1ee6dd77 8288 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 8289 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8290
8291 /* Update L3 header */
8292 ip->tot_len = htons(lro->total_len);
8293 ip->check = 0;
8294 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8295 ip->check = nchk;
8296
8297 /* Update L4 header */
8298 tcp->ack_seq = lro->tcp_ack;
8299 tcp->window = lro->window;
8300
8301 /* Update tsecr field if this session has timestamps enabled */
8302 if (lro->saw_ts) {
c8855953 8303 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8304 *(ptr+2) = lro->cur_tsecr;
8305 }
8306
8307 /* Update counters required for calculation of
8308 * average no. of packets aggregated.
8309 */
8310 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8311 statinfo->sw_stat.num_aggregations++;
8312}
8313
1ee6dd77 8314static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8315 struct tcphdr *tcp, u32 l4_pyld)
8316{
8317 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8318 lro->total_len += l4_pyld;
8319 lro->frags_len += l4_pyld;
8320 lro->tcp_next_seq += l4_pyld;
8321 lro->sg_num++;
8322
8323 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8324 lro->tcp_ack = tcp->ack_seq;
8325 lro->window = tcp->window;
6aa20a22 8326
7d3d0439 8327 if (lro->saw_ts) {
c8855953 8328 __be32 *ptr;
7d3d0439 8329 /* Update tsecr and tsval from this packet */
c8855953
SR		 8330 ptr = (__be32 *)(tcp+1);
8331 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8332 lro->cur_tsecr = *(ptr + 2);
8333 }
8334}
8335
1ee6dd77 8336static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8337 struct tcphdr *tcp, u32 tcp_pyld_len)
8338{
7d3d0439
RA		 8339 u8 *ptr;
8340
79dc1901
AM		 8341 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8342
7d3d0439
RA		 8343 if (!tcp_pyld_len) {
8344 /* Runt frame or a pure ack */
8345 return -1;
8346 }
8347
8348 if (ip->ihl != 5) /* IP has options */
8349 return -1;
8350
75c30b13
AR		 8351 /* If we see CE codepoint in IP header, packet is not mergeable */
8352 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8353 return -1;
8354
8355 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8356 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8357 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8358 /*
8359 * Currently recognize only the ack control word and
8360 * any other control field being set would result in
8361 * flushing the LRO session
8362 */
8363 return -1;
8364 }
8365
6aa20a22 8366 /*
7d3d0439
RA		 8367 * Allow only one TCP timestamp option. Don't aggregate if
8368 * any other options are detected.
8369 */
8370 if (tcp->doff != 5 && tcp->doff != 8)
8371 return -1;
8372
8373 if (tcp->doff == 8) {
6aa20a22 8374 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8375 while (*ptr == TCPOPT_NOP)
8376 ptr++;
8377 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8378 return -1;
8379
8380 /* Ensure timestamp value increases monotonically */
8381 if (l_lro)
c8855953 8382 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8383 return -1;
8384
8385 /* timestamp echo reply should be non-zero */
c8855953 8386 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8387 return -1;
8388 }
8389
8390 return 0;
8391}
8392
8393static int
1ee6dd77
RB		 8394s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8395 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8396{
8397 struct iphdr *ip;
8398 struct tcphdr *tcph;
8399 int ret = 0, i;
cdb5bf02 8400 u16 vlan_tag = 0;
7d3d0439
RA		 8401
8402 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8403 rxdp, sp))) {
7d3d0439
RA		 8404 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8405 ip->saddr, ip->daddr);
cdb5bf02 8406 } else
7d3d0439 8407 return ret;
7d3d0439 8408
cdb5bf02 8409 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8410 tcph = (struct tcphdr *)*tcp;
8411 *tcp_len = get_l4_pyld_length(ip, tcph);
8412 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8413 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8414 if (l_lro->in_use) {
8415 if (check_for_socket_match(l_lro, ip, tcph))
8416 continue;
8417 /* Sock pair matched */
8418 *lro = l_lro;
8419
8420 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8421 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8422 "0x%x, actual 0x%x\n", __FUNCTION__,
8423 (*lro)->tcp_next_seq,
8424 ntohl(tcph->seq));
8425
8426 sp->mac_control.stats_info->
8427 sw_stat.outof_sequence_pkts++;
8428 ret = 2;
8429 break;
8430 }
8431
8432 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8433 ret = 1; /* Aggregate */
8434 else
8435 ret = 2; /* Flush both */
8436 break;
8437 }
8438 }
8439
8440 if (ret == 0) {
8441 /* Before searching for available LRO objects,
8442 * check if the pkt is L3/L4 aggregatable. If not
8443 * don't create new LRO session. Just send this
8444 * packet up.
8445 */
8446 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8447 return 5;
8448 }
8449
8450 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8451 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8452 if (!(l_lro->in_use)) {
8453 *lro = l_lro;
8454 ret = 3; /* Begin anew */
8455 break;
8456 }
8457 }
8458 }
8459
8460 if (ret == 0) { /* sessions exceeded */
8461 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8462 __FUNCTION__);
8463 *lro = NULL;
8464 return ret;
8465 }
8466
8467 switch (ret) {
8468 case 3:
cdb5bf02
SH		 8469 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8470 vlan_tag);
7d3d0439
RA		 8471 break;
8472 case 2:
8473 update_L3L4_header(sp, *lro);
8474 break;
8475 case 1:
8476 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8477 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8478 update_L3L4_header(sp, *lro);
8479 ret = 4; /* Flush the LRO */
8480 }
8481 break;
8482 default:
8483 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8484 __FUNCTION__);
8485 break;
8486 }
8487
8488 return ret;
8489}
8490
1ee6dd77 8491static void clear_lro_session(struct lro *lro)
7d3d0439 8492{
1ee6dd77 8493 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8494
8495 memset(lro, 0, lro_struct_size);
8496}
8497
cdb5bf02 8498static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8499{
8500 struct net_device *dev = skb->dev;
cdb5bf02 8501 struct s2io_nic *sp = dev->priv;
7d3d0439
RA		 8502
8503 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02
SH		 8504 if (sp->vlgrp && vlan_tag
8505 && (vlan_strip_flag)) {
8506 /* Queueing the vlan frame to the upper layer */
8507 if (sp->config.napi)
8508 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8509 else
8510 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8511 } else {
8512 if (sp->config.napi)
8513 netif_receive_skb(skb);
8514 else
8515 netif_rx(skb);
8516 }
7d3d0439
RA		 8517}
8518
1ee6dd77
RB		 8519static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8520 struct sk_buff *skb,
7d3d0439
RA		 8521 u32 tcp_len)
8522{
75c30b13 8523 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8524
8525 first->len += tcp_len;
8526 first->data_len = lro->frags_len;
8527 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8528 if (skb_shinfo(first)->frag_list)
8529 lro->last_frag->next = skb;
7d3d0439
RA		 8530 else
8531 skb_shinfo(first)->frag_list = skb;
372cc597 8532 first->truesize += skb->truesize;
75c30b13 8533 lro->last_frag = skb;
7d3d0439
RA		 8534 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8535 return;
8536}
d796fdb7
LV		 8537
8538/**
8539 * s2io_io_error_detected - called when PCI error is detected
8540 * @pdev: Pointer to PCI device
8453d43f 8541 * @state: The current pci connection state
d796fdb7
LV		 8542 *
8543 * This function is called after a PCI bus error affecting
8544 * this device has been detected.
8545 */
8546static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8547 pci_channel_state_t state)
8548{
8549 struct net_device *netdev = pci_get_drvdata(pdev);
8550 struct s2io_nic *sp = netdev->priv;
8551
8552 netif_device_detach(netdev);
8553
8554 if (netif_running(netdev)) {
8555 /* Bring down the card, while avoiding PCI I/O */
8556 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8557 }
8558 pci_disable_device(pdev);
8559
8560 return PCI_ERS_RESULT_NEED_RESET;
8561}
8562
8563/**
8564 * s2io_io_slot_reset - called after the pci bus has been reset.
8565 * @pdev: Pointer to PCI device
8566 *
8567 * Restart the card from scratch, as if from a cold-boot.
8568 * At this point, the card has exprienced a hard reset,
8569 * followed by fixups by BIOS, and has its config space
8570 * set up identically to what it was at cold boot.
8571 */
8572static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8573{
8574 struct net_device *netdev = pci_get_drvdata(pdev);
8575 struct s2io_nic *sp = netdev->priv;
8576
8577 if (pci_enable_device(pdev)) {
8578 printk(KERN_ERR "s2io: "
8579 "Cannot re-enable PCI device after reset.\n");
8580 return PCI_ERS_RESULT_DISCONNECT;
8581 }
8582
8583 pci_set_master(pdev);
8584 s2io_reset(sp);
8585
8586 return PCI_ERS_RESULT_RECOVERED;
8587}
8588
8589/**
8590 * s2io_io_resume - called when traffic can start flowing again.
8591 * @pdev: Pointer to PCI device
8592 *
8593 * This callback is called when the error recovery driver tells
8594 * us that its OK to resume normal operation.
8595 */
8596static void s2io_io_resume(struct pci_dev *pdev)
8597{
8598 struct net_device *netdev = pci_get_drvdata(pdev);
8599 struct s2io_nic *sp = netdev->priv;
8600
8601 if (netif_running(netdev)) {
8602 if (s2io_card_up(sp)) {
8603 printk(KERN_ERR "s2io: "
8604 "Can't bring device back up after reset.\n");
8605 return;
8606 }
8607
8608 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8609 s2io_card_down(sp);
8610 printk(KERN_ERR "s2io: "
8611 "Can't resetore mac addr after reset.\n");
8612 return;
8613 }
8614 }
8615
8616 netif_device_attach(netdev);
8617 netif_wake_queue(netdev);
8618}
Linux kernel - Deliverables
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