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S2io: Version update for memory leak fix during free_tx_buffers
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
66#include <linux/skbuff.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/stddef.h>
70#include <linux/ioctl.h>
71#include <linux/timex.h>
1da177e4 72#include <linux/ethtool.h>
1da177e4 73#include <linux/workqueue.h>
be3a6b02 74#include <linux/if_vlan.h>
7d3d0439
RA		 75#include <linux/ip.h>
76#include <linux/tcp.h>
77#include <net/tcp.h>
1da177e4 78
1da177e4
LT		 79#include <asm/system.h>
80#include <asm/uaccess.h>
20346722 81#include <asm/io.h>
fe931395 82#include <asm/div64.h>
330ce0de 83#include <asm/irq.h>
1da177e4
LT		 84
85/* local include */
86#include "s2io.h"
87#include "s2io-regs.h"
88
10371b5e 89#define DRV_VERSION "2.0.26.22"
6c1792f4 90
1da177e4 91/* S2io Driver name & version. */
20346722 92static char s2io_driver_name[] = "Neterion";
6c1792f4 93static char s2io_driver_version[] = DRV_VERSION;
1da177e4 94
6d517a27
VP		 95static int rxd_size[2] = {32,48};
96static int rxd_count[2] = {127,85};
da6971d8 97
1ee6dd77 98static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 99{
100 int ret;
101
102 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
103 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
104
105 return ret;
106}
107
20346722 108/*
1da177e4
LT		 109 * Cards with following subsystem_id have a link state indication
110 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
111 * macro below identifies these cards given the subsystem_id.
112 */
541ae68f 113#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
114 (dev_type == XFRAME_I_DEVICE) ? \
115 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
116 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 117
118#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
119 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
120#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
121#define PANIC 1
122#define LOW 2
1ee6dd77 123static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 124{
1ee6dd77 125 struct mac_info *mac_control;
20346722 126
127 mac_control = &sp->mac_control;
863c11a9
AR		 128 if (rxb_size <= rxd_count[sp->rxd_mode])
129 return PANIC;
130 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
131 return LOW;
132 return 0;
1da177e4
LT		 133}
134
92b84437
SS		 135static inline int is_s2io_card_up(const struct s2io_nic * sp)
136{
137 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
138}
139
1da177e4
LT		 140/* Ethtool related variables and Macros. */
141static char s2io_gstrings[][ETH_GSTRING_LEN] = {
142 "Register test\t(offline)",
143 "Eeprom test\t(offline)",
144 "Link test\t(online)",
145 "RLDRAM test\t(offline)",
146 "BIST Test\t(offline)"
147};
148
fa1f0cb3 149static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 150 {"tmac_frms"},
151 {"tmac_data_octets"},
152 {"tmac_drop_frms"},
153 {"tmac_mcst_frms"},
154 {"tmac_bcst_frms"},
155 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 156 {"tmac_ttl_octets"},
157 {"tmac_ucst_frms"},
158 {"tmac_nucst_frms"},
1da177e4 159 {"tmac_any_err_frms"},
bd1034f0 160 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 161 {"tmac_vld_ip_octets"},
162 {"tmac_vld_ip"},
163 {"tmac_drop_ip"},
164 {"tmac_icmp"},
165 {"tmac_rst_tcp"},
166 {"tmac_tcp"},
167 {"tmac_udp"},
168 {"rmac_vld_frms"},
169 {"rmac_data_octets"},
170 {"rmac_fcs_err_frms"},
171 {"rmac_drop_frms"},
172 {"rmac_vld_mcst_frms"},
173 {"rmac_vld_bcst_frms"},
174 {"rmac_in_rng_len_err_frms"},
bd1034f0 175 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 176 {"rmac_long_frms"},
177 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 178 {"rmac_unsup_ctrl_frms"},
179 {"rmac_ttl_octets"},
180 {"rmac_accepted_ucst_frms"},
181 {"rmac_accepted_nucst_frms"},
1da177e4 182 {"rmac_discarded_frms"},
bd1034f0
AR		 183 {"rmac_drop_events"},
184 {"rmac_ttl_less_fb_octets"},
185 {"rmac_ttl_frms"},
1da177e4
LT		 186 {"rmac_usized_frms"},
187 {"rmac_osized_frms"},
188 {"rmac_frag_frms"},
189 {"rmac_jabber_frms"},
bd1034f0
AR		 190 {"rmac_ttl_64_frms"},
191 {"rmac_ttl_65_127_frms"},
192 {"rmac_ttl_128_255_frms"},
193 {"rmac_ttl_256_511_frms"},
194 {"rmac_ttl_512_1023_frms"},
195 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 196 {"rmac_ip"},
197 {"rmac_ip_octets"},
198 {"rmac_hdr_err_ip"},
199 {"rmac_drop_ip"},
200 {"rmac_icmp"},
201 {"rmac_tcp"},
202 {"rmac_udp"},
203 {"rmac_err_drp_udp"},
bd1034f0
AR		 204 {"rmac_xgmii_err_sym"},
205 {"rmac_frms_q0"},
206 {"rmac_frms_q1"},
207 {"rmac_frms_q2"},
208 {"rmac_frms_q3"},
209 {"rmac_frms_q4"},
210 {"rmac_frms_q5"},
211 {"rmac_frms_q6"},
212 {"rmac_frms_q7"},
213 {"rmac_full_q0"},
214 {"rmac_full_q1"},
215 {"rmac_full_q2"},
216 {"rmac_full_q3"},
217 {"rmac_full_q4"},
218 {"rmac_full_q5"},
219 {"rmac_full_q6"},
220 {"rmac_full_q7"},
1da177e4 221 {"rmac_pause_cnt"},
bd1034f0
AR		 222 {"rmac_xgmii_data_err_cnt"},
223 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 224 {"rmac_accepted_ip"},
225 {"rmac_err_tcp"},
bd1034f0
AR		 226 {"rd_req_cnt"},
227 {"new_rd_req_cnt"},
228 {"new_rd_req_rtry_cnt"},
229 {"rd_rtry_cnt"},
230 {"wr_rtry_rd_ack_cnt"},
231 {"wr_req_cnt"},
232 {"new_wr_req_cnt"},
233 {"new_wr_req_rtry_cnt"},
234 {"wr_rtry_cnt"},
235 {"wr_disc_cnt"},
236 {"rd_rtry_wr_ack_cnt"},
237 {"txp_wr_cnt"},
238 {"txd_rd_cnt"},
239 {"txd_wr_cnt"},
240 {"rxd_rd_cnt"},
241 {"rxd_wr_cnt"},
242 {"txf_rd_cnt"},
fa1f0cb3
SS		 243 {"rxf_wr_cnt"}
244};
245
246static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 247 {"rmac_ttl_1519_4095_frms"},
248 {"rmac_ttl_4096_8191_frms"},
249 {"rmac_ttl_8192_max_frms"},
250 {"rmac_ttl_gt_max_frms"},
251 {"rmac_osized_alt_frms"},
252 {"rmac_jabber_alt_frms"},
253 {"rmac_gt_max_alt_frms"},
254 {"rmac_vlan_frms"},
255 {"rmac_len_discard"},
256 {"rmac_fcs_discard"},
257 {"rmac_pf_discard"},
258 {"rmac_da_discard"},
259 {"rmac_red_discard"},
260 {"rmac_rts_discard"},
261 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 262 {"link_fault_cnt"}
263};
264
265static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 266 {"\n DRIVER STATISTICS"},
267 {"single_bit_ecc_errs"},
268 {"double_bit_ecc_errs"},
bd1034f0
AR		 269 {"parity_err_cnt"},
270 {"serious_err_cnt"},
271 {"soft_reset_cnt"},
272 {"fifo_full_cnt"},
8116f3cf
SS		 273 {"ring_0_full_cnt"},
274 {"ring_1_full_cnt"},
275 {"ring_2_full_cnt"},
276 {"ring_3_full_cnt"},
277 {"ring_4_full_cnt"},
278 {"ring_5_full_cnt"},
279 {"ring_6_full_cnt"},
280 {"ring_7_full_cnt"},
43b7c451
SH		 281 {"alarm_transceiver_temp_high"},
282 {"alarm_transceiver_temp_low"},
283 {"alarm_laser_bias_current_high"},
284 {"alarm_laser_bias_current_low"},
285 {"alarm_laser_output_power_high"},
286 {"alarm_laser_output_power_low"},
287 {"warn_transceiver_temp_high"},
288 {"warn_transceiver_temp_low"},
289 {"warn_laser_bias_current_high"},
290 {"warn_laser_bias_current_low"},
291 {"warn_laser_output_power_high"},
292 {"warn_laser_output_power_low"},
293 {"lro_aggregated_pkts"},
294 {"lro_flush_both_count"},
295 {"lro_out_of_sequence_pkts"},
296 {"lro_flush_due_to_max_pkts"},
297 {"lro_avg_aggr_pkts"},
298 {"mem_alloc_fail_cnt"},
299 {"pci_map_fail_cnt"},
300 {"watchdog_timer_cnt"},
301 {"mem_allocated"},
302 {"mem_freed"},
303 {"link_up_cnt"},
304 {"link_down_cnt"},
305 {"link_up_time"},
306 {"link_down_time"},
307 {"tx_tcode_buf_abort_cnt"},
308 {"tx_tcode_desc_abort_cnt"},
309 {"tx_tcode_parity_err_cnt"},
310 {"tx_tcode_link_loss_cnt"},
311 {"tx_tcode_list_proc_err_cnt"},
312 {"rx_tcode_parity_err_cnt"},
313 {"rx_tcode_abort_cnt"},
314 {"rx_tcode_parity_abort_cnt"},
315 {"rx_tcode_rda_fail_cnt"},
316 {"rx_tcode_unkn_prot_cnt"},
317 {"rx_tcode_fcs_err_cnt"},
318 {"rx_tcode_buf_size_err_cnt"},
319 {"rx_tcode_rxd_corrupt_cnt"},
320 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 321 {"tda_err_cnt"},
322 {"pfc_err_cnt"},
323 {"pcc_err_cnt"},
324 {"tti_err_cnt"},
325 {"tpa_err_cnt"},
326 {"sm_err_cnt"},
327 {"lso_err_cnt"},
328 {"mac_tmac_err_cnt"},
329 {"mac_rmac_err_cnt"},
330 {"xgxs_txgxs_err_cnt"},
331 {"xgxs_rxgxs_err_cnt"},
332 {"rc_err_cnt"},
333 {"prc_pcix_err_cnt"},
334 {"rpa_err_cnt"},
335 {"rda_err_cnt"},
336 {"rti_err_cnt"},
337 {"mc_err_cnt"}
1da177e4
LT		 338};
339
4c3616cd
AMR		 340#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
341#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
342#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 343
344#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
345#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
346
347#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
348#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 349
4c3616cd 350#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 351#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
352
25fff88e 353#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
354 init_timer(&timer); \
355 timer.function = handle; \
356 timer.data = (unsigned long) arg; \
357 mod_timer(&timer, (jiffies + exp)) \
358
2fd37688
SS		 359/* copy mac addr to def_mac_addr array */
360static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
361{
362 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
363 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
364 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
365 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
366 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
367 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
368}
be3a6b02 369/* Add the vlan */
370static void s2io_vlan_rx_register(struct net_device *dev,
371 struct vlan_group *grp)
372{
2fda096d 373 int i;
1ee6dd77 374 struct s2io_nic *nic = dev->priv;
2fda096d
SR		 375 unsigned long flags[MAX_TX_FIFOS];
376 struct mac_info *mac_control = &nic->mac_control;
377 struct config_param *config = &nic->config;
378
379 for (i = 0; i < config->tx_fifo_num; i++)
380 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
be3a6b02 381
be3a6b02 382 nic->vlgrp = grp;
2fda096d
SR		 383 for (i = config->tx_fifo_num - 1; i >= 0; i--)
384 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
385 flags[i]);
be3a6b02 386}
387
926930b2 388/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 389static int vlan_strip_flag;
926930b2 390
cdb5bf02
SH		 391/* Unregister the vlan */
392static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
393{
394 int i;
395 struct s2io_nic *nic = dev->priv;
396 unsigned long flags[MAX_TX_FIFOS];
397 struct mac_info *mac_control = &nic->mac_control;
398 struct config_param *config = &nic->config;
399
400 for (i = 0; i < config->tx_fifo_num; i++)
401 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
402
403 if (nic->vlgrp)
404 vlan_group_set_device(nic->vlgrp, vid, NULL);
405
406 for (i = config->tx_fifo_num - 1; i >= 0; i--)
407 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
408 flags[i]);
409}
410
20346722 411/*
1da177e4
LT		 412 * Constants to be programmed into the Xena's registers, to configure
413 * the XAUI.
414 */
415
1da177e4 416#define END_SIGN 0x0
f71e1309 417static const u64 herc_act_dtx_cfg[] = {
541ae68f 418 /* Set address */
e960fc5c 419 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 420 /* Write data */
e960fc5c 421 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 422 /* Set address */
423 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
424 /* Write data */
425 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
426 /* Set address */
e960fc5c 427 0x801205150D440000ULL, 0x801205150D4400E0ULL,
428 /* Write data */
429 0x801205150D440004ULL, 0x801205150D4400E4ULL,
430 /* Set address */
541ae68f 431 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
432 /* Write data */
433 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
434 /* Done */
435 END_SIGN
436};
437
f71e1309 438static const u64 xena_dtx_cfg[] = {
c92ca04b 439 /* Set address */
1da177e4 440 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 441 /* Write data */
442 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
443 /* Set address */
444 0x8001051500000000ULL, 0x80010515000000E0ULL,
445 /* Write data */
446 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
447 /* Set address */
1da177e4 448 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 449 /* Write data */
450 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 451 END_SIGN
452};
453
20346722 454/*
1da177e4
LT		 455 * Constants for Fixing the MacAddress problem seen mostly on
456 * Alpha machines.
457 */
f71e1309 458static const u64 fix_mac[] = {
1da177e4
LT		 459 0x0060000000000000ULL, 0x0060600000000000ULL,
460 0x0040600000000000ULL, 0x0000600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0060600000000000ULL,
471 0x0020600000000000ULL, 0x0000600000000000ULL,
472 0x0040600000000000ULL, 0x0060600000000000ULL,
473 END_SIGN
474};
475
b41477f3
AR		 476MODULE_LICENSE("GPL");
477MODULE_VERSION(DRV_VERSION);
478
479
1da177e4 480/* Module Loadable parameters. */
6cfc482b 481S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 482S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 483S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 484S2IO_PARM_INT(rx_ring_mode, 1);
485S2IO_PARM_INT(use_continuous_tx_intrs, 1);
486S2IO_PARM_INT(rmac_pause_time, 0x100);
487S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
488S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
489S2IO_PARM_INT(shared_splits, 0);
490S2IO_PARM_INT(tmac_util_period, 5);
491S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 492S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 493/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
494S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 495/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 496S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 497/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 498S2IO_PARM_INT(intr_type, 2);
7d3d0439 499/* Large receive offload feature */
43b7c451
SH		 500static unsigned int lro_enable;
501module_param_named(lro, lro_enable, uint, 0);
502
7d3d0439
RA		 503/* Max pkts to be aggregated by LRO at one time. If not specified,
504 * aggregation happens until we hit max IP pkt size(64K)
505 */
b41477f3 506S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 507S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 508
509S2IO_PARM_INT(napi, 1);
510S2IO_PARM_INT(ufo, 0);
926930b2 511S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 512
513static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
514 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
515static unsigned int rx_ring_sz[MAX_RX_RINGS] =
516 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
517static unsigned int rts_frm_len[MAX_RX_RINGS] =
518 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
519
520module_param_array(tx_fifo_len, uint, NULL, 0);
521module_param_array(rx_ring_sz, uint, NULL, 0);
522module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 523
20346722 524/*
1da177e4 525 * S2IO device table.
20346722 526 * This table lists all the devices that this driver supports.
1da177e4
LT		 527 */
528static struct pci_device_id s2io_tbl[] __devinitdata = {
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
533 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722 534 PCI_ANY_ID, PCI_ANY_ID},
535 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
536 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 537 {0,}
538};
539
540MODULE_DEVICE_TABLE(pci, s2io_tbl);
541
d796fdb7
LV		 542static struct pci_error_handlers s2io_err_handler = {
543 .error_detected = s2io_io_error_detected,
544 .slot_reset = s2io_io_slot_reset,
545 .resume = s2io_io_resume,
546};
547
1da177e4
LT		 548static struct pci_driver s2io_driver = {
549 .name = "S2IO",
550 .id_table = s2io_tbl,
551 .probe = s2io_init_nic,
552 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 553 .err_handler = &s2io_err_handler,
1da177e4
LT		 554};
555
556/* A simplifier macro used both by init and free shared_mem Fns(). */
557#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
558
3a3d5756
SH		 559/* netqueue manipulation helper functions */
560static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
561{
562 int i;
563#ifdef CONFIG_NETDEVICES_MULTIQUEUE
564 if (sp->config.multiq) {
565 for (i = 0; i < sp->config.tx_fifo_num; i++)
566 netif_stop_subqueue(sp->dev, i);
567 } else
568#endif
569 {
570 for (i = 0; i < sp->config.tx_fifo_num; i++)
571 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
572 netif_stop_queue(sp->dev);
573 }
574}
575
576static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
577{
578#ifdef CONFIG_NETDEVICES_MULTIQUEUE
579 if (sp->config.multiq)
580 netif_stop_subqueue(sp->dev, fifo_no);
581 else
582#endif
583 {
584 sp->mac_control.fifos[fifo_no].queue_state =
585 FIFO_QUEUE_STOP;
586 netif_stop_queue(sp->dev);
587 }
588}
589
590static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
591{
592 int i;
593#ifdef CONFIG_NETDEVICES_MULTIQUEUE
594 if (sp->config.multiq) {
595 for (i = 0; i < sp->config.tx_fifo_num; i++)
596 netif_start_subqueue(sp->dev, i);
597 } else
598#endif
599 {
600 for (i = 0; i < sp->config.tx_fifo_num; i++)
601 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
602 netif_start_queue(sp->dev);
603 }
604}
605
606static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
607{
608#ifdef CONFIG_NETDEVICES_MULTIQUEUE
609 if (sp->config.multiq)
610 netif_start_subqueue(sp->dev, fifo_no);
611 else
612#endif
613 {
614 sp->mac_control.fifos[fifo_no].queue_state =
615 FIFO_QUEUE_START;
616 netif_start_queue(sp->dev);
617 }
618}
619
620static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
621{
622 int i;
623#ifdef CONFIG_NETDEVICES_MULTIQUEUE
624 if (sp->config.multiq) {
625 for (i = 0; i < sp->config.tx_fifo_num; i++)
626 netif_wake_subqueue(sp->dev, i);
627 } else
628#endif
629 {
630 for (i = 0; i < sp->config.tx_fifo_num; i++)
631 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
632 netif_wake_queue(sp->dev);
633 }
634}
635
636static inline void s2io_wake_tx_queue(
637 struct fifo_info *fifo, int cnt, u8 multiq)
638{
639
640#ifdef CONFIG_NETDEVICES_MULTIQUEUE
641 if (multiq) {
642 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
643 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
644 } else
645#endif
646 if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
647 if (netif_queue_stopped(fifo->dev)) {
648 fifo->queue_state = FIFO_QUEUE_START;
649 netif_wake_queue(fifo->dev);
650 }
651 }
652}
653
1da177e4
LT		 654/**
655 * init_shared_mem - Allocation and Initialization of Memory
656 * @nic: Device private variable.
20346722 657 * Description: The function allocates all the memory areas shared
658 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 659 * Rx descriptors and the statistics block.
660 */
661
662static int init_shared_mem(struct s2io_nic *nic)
663{
664 u32 size;
665 void *tmp_v_addr, *tmp_v_addr_next;
666 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 667 struct RxD_block *pre_rxd_blk = NULL;
372cc597 668 int i, j, blk_cnt;
1da177e4
LT		 669 int lst_size, lst_per_page;
670 struct net_device *dev = nic->dev;
8ae418cf 671 unsigned long tmp;
1ee6dd77 672 struct buffAdd *ba;
1da177e4 673
1ee6dd77 674 struct mac_info *mac_control;
1da177e4 675 struct config_param *config;
491976b2 676 unsigned long long mem_allocated = 0;
1da177e4
LT		 677
678 mac_control = &nic->mac_control;
679 config = &nic->config;
680
681
682 /* Allocation and initialization of TXDLs in FIOFs */
683 size = 0;
684 for (i = 0; i < config->tx_fifo_num; i++) {
685 size += config->tx_cfg[i].fifo_len;
686 }
687 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 688 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 689 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 690 return -EINVAL;
1da177e4
LT		 691 }
692
2fda096d
SR		 693 size = 0;
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 size = config->tx_cfg[i].fifo_len;
696 /*
697 * Legal values are from 2 to 8192
698 */
699 if (size < 2) {
700 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
701 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
702 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
703 "are 2 to 8192\n");
704 return -EINVAL;
705 }
706 }
707
1ee6dd77 708 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 709 lst_per_page = PAGE_SIZE / lst_size;
710
711 for (i = 0; i < config->tx_fifo_num; i++) {
712 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 713 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 714 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722 715 GFP_KERNEL);
716 if (!mac_control->fifos[i].list_info) {
0c61ed5f 717 DBG_PRINT(INFO_DBG,
1da177e4
LT		 718 "Malloc failed for list_info\n");
719 return -ENOMEM;
720 }
491976b2 721 mem_allocated += list_holder_size;
1da177e4
LT		 722 }
723 for (i = 0; i < config->tx_fifo_num; i++) {
724 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
725 lst_per_page);
20346722 726 mac_control->fifos[i].tx_curr_put_info.offset = 0;
727 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 728 config->tx_cfg[i].fifo_len - 1;
20346722 729 mac_control->fifos[i].tx_curr_get_info.offset = 0;
730 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 731 config->tx_cfg[i].fifo_len - 1;
20346722 732 mac_control->fifos[i].fifo_no = i;
733 mac_control->fifos[i].nic = nic;
fed5eccd 734 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
3a3d5756 735 mac_control->fifos[i].dev = dev;
20346722 736
1da177e4
LT		 737 for (j = 0; j < page_num; j++) {
738 int k = 0;
739 dma_addr_t tmp_p;
740 void *tmp_v;
741 tmp_v = pci_alloc_consistent(nic->pdev,
742 PAGE_SIZE, &tmp_p);
743 if (!tmp_v) {
0c61ed5f 744 DBG_PRINT(INFO_DBG,
1da177e4 745 "pci_alloc_consistent ");
0c61ed5f 746 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 747 return -ENOMEM;
748 }
776bd20f 749 /* If we got a zero DMA address(can happen on
750 * certain platforms like PPC), reallocate.
751 * Store virtual address of page we don't want,
752 * to be freed later.
753 */
754 if (!tmp_p) {
755 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 756 DBG_PRINT(INIT_DBG,
776bd20f 757 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 758 DBG_PRINT(INIT_DBG,
6b4d617d 759 "Virtual address %p\n", tmp_v);
776bd20f 760 tmp_v = pci_alloc_consistent(nic->pdev,
761 PAGE_SIZE, &tmp_p);
762 if (!tmp_v) {
0c61ed5f 763 DBG_PRINT(INFO_DBG,
776bd20f 764 "pci_alloc_consistent ");
0c61ed5f 765 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 766 return -ENOMEM;
767 }
491976b2 768 mem_allocated += PAGE_SIZE;
776bd20f 769 }
1da177e4
LT		 770 while (k < lst_per_page) {
771 int l = (j * lst_per_page) + k;
772 if (l == config->tx_cfg[i].fifo_len)
20346722 773 break;
774 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 775 tmp_v + (k * lst_size);
20346722 776 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 777 tmp_p + (k * lst_size);
778 k++;
779 }
780 }
781 }
1da177e4 782
2fda096d
SR		 783 for (i = 0; i < config->tx_fifo_num; i++) {
784 size = config->tx_cfg[i].fifo_len;
785 mac_control->fifos[i].ufo_in_band_v
786 = kcalloc(size, sizeof(u64), GFP_KERNEL);
787 if (!mac_control->fifos[i].ufo_in_band_v)
788 return -ENOMEM;
789 mem_allocated += (size * sizeof(u64));
790 }
fed5eccd 791
1da177e4
LT		 792 /* Allocation and initialization of RXDs in Rings */
793 size = 0;
794 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 795 if (config->rx_cfg[i].num_rxd %
796 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 797 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
798 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
799 i);
800 DBG_PRINT(ERR_DBG, "RxDs per Block");
801 return FAILURE;
802 }
803 size += config->rx_cfg[i].num_rxd;
20346722 804 mac_control->rings[i].block_count =
da6971d8
AR		 805 config->rx_cfg[i].num_rxd /
806 (rxd_count[nic->rxd_mode] + 1 );
807 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
808 mac_control->rings[i].block_count;
1da177e4 809 }
da6971d8 810 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 811 size = (size * (sizeof(struct RxD1)));
da6971d8 812 else
1ee6dd77 813 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 814
815 for (i = 0; i < config->rx_ring_num; i++) {
20346722 816 mac_control->rings[i].rx_curr_get_info.block_index = 0;
817 mac_control->rings[i].rx_curr_get_info.offset = 0;
818 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 819 config->rx_cfg[i].num_rxd - 1;
20346722 820 mac_control->rings[i].rx_curr_put_info.block_index = 0;
821 mac_control->rings[i].rx_curr_put_info.offset = 0;
822 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 823 config->rx_cfg[i].num_rxd - 1;
20346722 824 mac_control->rings[i].nic = nic;
825 mac_control->rings[i].ring_no = i;
826
da6971d8
AR		 827 blk_cnt = config->rx_cfg[i].num_rxd /
828 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 829 /* Allocating all the Rx blocks */
830 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 831 struct rx_block_info *rx_blocks;
da6971d8
AR		 832 int l;
833
834 rx_blocks = &mac_control->rings[i].rx_blocks[j];
835 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 836 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
837 &tmp_p_addr);
838 if (tmp_v_addr == NULL) {
839 /*
20346722 840 * In case of failure, free_shared_mem()
841 * is called, which should free any
842 * memory that was alloced till the
1da177e4
LT		 843 * failure happened.
844 */
da6971d8 845 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 846 return -ENOMEM;
847 }
491976b2 848 mem_allocated += size;
1da177e4 849 memset(tmp_v_addr, 0, size);
da6971d8
AR		 850 rx_blocks->block_virt_addr = tmp_v_addr;
851 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 852 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 853 rxd_count[nic->rxd_mode],
854 GFP_KERNEL);
372cc597
SS		 855 if (!rx_blocks->rxds)
856 return -ENOMEM;
8a4bdbaa 857 mem_allocated +=
491976b2 858 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 859 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
860 rx_blocks->rxds[l].virt_addr =
861 rx_blocks->block_virt_addr +
862 (rxd_size[nic->rxd_mode] * l);
863 rx_blocks->rxds[l].dma_addr =
864 rx_blocks->block_dma_addr +
865 (rxd_size[nic->rxd_mode] * l);
866 }
1da177e4
LT		 867 }
868 /* Interlinking all Rx Blocks */
869 for (j = 0; j < blk_cnt; j++) {
20346722 870 tmp_v_addr =
871 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 872 tmp_v_addr_next =
20346722 873 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 874 blk_cnt].block_virt_addr;
20346722 875 tmp_p_addr =
876 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 877 tmp_p_addr_next =
20346722 878 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 879 blk_cnt].block_dma_addr;
880
1ee6dd77 881 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 882 pre_rxd_blk->reserved_2_pNext_RxD_block =
883 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 884 pre_rxd_blk->pNext_RxD_Blk_physical =
885 (u64) tmp_p_addr_next;
886 }
887 }
6d517a27 888 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 889 /*
890 * Allocation of Storages for buffer addresses in 2BUFF mode
891 * and the buffers as well.
892 */
893 for (i = 0; i < config->rx_ring_num; i++) {
894 blk_cnt = config->rx_cfg[i].num_rxd /
895 (rxd_count[nic->rxd_mode]+ 1);
896 mac_control->rings[i].ba =
1ee6dd77 897 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 898 GFP_KERNEL);
da6971d8 899 if (!mac_control->rings[i].ba)
1da177e4 900 return -ENOMEM;
491976b2 901 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 902 for (j = 0; j < blk_cnt; j++) {
903 int k = 0;
904 mac_control->rings[i].ba[j] =
1ee6dd77 905 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 906 (rxd_count[nic->rxd_mode] + 1)),
907 GFP_KERNEL);
908 if (!mac_control->rings[i].ba[j])
1da177e4 909 return -ENOMEM;
491976b2
SH		 910 mem_allocated += (sizeof(struct buffAdd) * \
911 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 912 while (k != rxd_count[nic->rxd_mode]) {
913 ba = &mac_control->rings[i].ba[j][k];
914
915 ba->ba_0_org = (void *) kmalloc
916 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
917 if (!ba->ba_0_org)
918 return -ENOMEM;
8a4bdbaa 919 mem_allocated +=
491976b2 920 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 921 tmp = (unsigned long)ba->ba_0_org;
922 tmp += ALIGN_SIZE;
923 tmp &= ~((unsigned long) ALIGN_SIZE);
924 ba->ba_0 = (void *) tmp;
925
926 ba->ba_1_org = (void *) kmalloc
927 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
928 if (!ba->ba_1_org)
929 return -ENOMEM;
8a4bdbaa 930 mem_allocated
491976b2 931 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 932 tmp = (unsigned long) ba->ba_1_org;
933 tmp += ALIGN_SIZE;
934 tmp &= ~((unsigned long) ALIGN_SIZE);
935 ba->ba_1 = (void *) tmp;
936 k++;
937 }
1da177e4
LT		 938 }
939 }
940 }
1da177e4
LT		 941
942 /* Allocation and initialization of Statistics block */
1ee6dd77 943 size = sizeof(struct stat_block);
1da177e4
LT		 944 mac_control->stats_mem = pci_alloc_consistent
945 (nic->pdev, size, &mac_control->stats_mem_phy);
946
947 if (!mac_control->stats_mem) {
20346722 948 /*
949 * In case of failure, free_shared_mem() is called, which
950 * should free any memory that was alloced till the
1da177e4
LT		 951 * failure happened.
952 */
953 return -ENOMEM;
954 }
491976b2 955 mem_allocated += size;
1da177e4
LT		 956 mac_control->stats_mem_sz = size;
957
958 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 959 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 960 memset(tmp_v_addr, 0, size);
1da177e4
LT		 961 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
962 (unsigned long long) tmp_p_addr);
491976b2 963 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 964 return SUCCESS;
965}
966
20346722 967/**
968 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 969 * @nic: Device private variable.
970 * Description: This function is to free all memory locations allocated by
971 * the init_shared_mem() function and return it to the kernel.
972 */
973
974static void free_shared_mem(struct s2io_nic *nic)
975{
976 int i, j, blk_cnt, size;
977 void *tmp_v_addr;
978 dma_addr_t tmp_p_addr;
1ee6dd77 979 struct mac_info *mac_control;
1da177e4
LT		 980 struct config_param *config;
981 int lst_size, lst_per_page;
8910b49f 982 struct net_device *dev;
491976b2 983 int page_num = 0;
1da177e4
LT		 984
985 if (!nic)
986 return;
987
8910b49f
MG		 988 dev = nic->dev;
989
1da177e4
LT		 990 mac_control = &nic->mac_control;
991 config = &nic->config;
992
1ee6dd77 993 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 994 lst_per_page = PAGE_SIZE / lst_size;
995
996 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 997 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
998 lst_per_page);
1da177e4
LT		 999 for (j = 0; j < page_num; j++) {
1000 int mem_blks = (j * lst_per_page);
776bd20f 1001 if (!mac_control->fifos[i].list_info)
6aa20a22 1002 return;
776bd20f 1003 if (!mac_control->fifos[i].list_info[mem_blks].
1004 list_virt_addr)
1da177e4
LT		 1005 break;
1006 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722 1007 mac_control->fifos[i].
1008 list_info[mem_blks].
1da177e4 1009 list_virt_addr,
20346722 1010 mac_control->fifos[i].
1011 list_info[mem_blks].
1da177e4 1012 list_phy_addr);
8a4bdbaa 1013 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 1014 += PAGE_SIZE;
1da177e4 1015 }
776bd20f 1016 /* If we got a zero DMA address during allocation,
1017 * free the page now
1018 */
1019 if (mac_control->zerodma_virt_addr) {
1020 pci_free_consistent(nic->pdev, PAGE_SIZE,
1021 mac_control->zerodma_virt_addr,
1022 (dma_addr_t)0);
6aa20a22 1023 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 1024 "%s: Freeing TxDL with zero DMA addr. ",
1025 dev->name);
1026 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
1027 mac_control->zerodma_virt_addr);
8a4bdbaa 1028 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 1029 += PAGE_SIZE;
776bd20f 1030 }
20346722 1031 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 1032 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1033 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 1034 }
1035
1da177e4 1036 size = SIZE_OF_BLOCK;
1da177e4 1037 for (i = 0; i < config->rx_ring_num; i++) {
20346722 1038 blk_cnt = mac_control->rings[i].block_count;
1da177e4 1039 for (j = 0; j < blk_cnt; j++) {
20346722 1040 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
1041 block_virt_addr;
1042 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
1043 block_dma_addr;
1da177e4
LT		 1044 if (tmp_v_addr == NULL)
1045 break;
1046 pci_free_consistent(nic->pdev, size,
1047 tmp_v_addr, tmp_p_addr);
491976b2 1048 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 1049 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 1050 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1051 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1052 }
1053 }
1054
6d517a27 1055 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1056 /* Freeing buffer storage addresses in 2BUFF mode. */
1057 for (i = 0; i < config->rx_ring_num; i++) {
1058 blk_cnt = config->rx_cfg[i].num_rxd /
1059 (rxd_count[nic->rxd_mode] + 1);
1060 for (j = 0; j < blk_cnt; j++) {
1061 int k = 0;
1062 if (!mac_control->rings[i].ba[j])
1063 continue;
1064 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 1065 struct buffAdd *ba =
da6971d8
AR		 1066 &mac_control->rings[i].ba[j][k];
1067 kfree(ba->ba_0_org);
491976b2
SH		 1068 nic->mac_control.stats_info->sw_stat.\
1069 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1070 kfree(ba->ba_1_org);
491976b2
SH		 1071 nic->mac_control.stats_info->sw_stat.\
1072 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1073 k++;
1074 }
1075 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 1076 nic->mac_control.stats_info->sw_stat.mem_freed +=
1077 (sizeof(struct buffAdd) *
1078 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1079 }
da6971d8 1080 kfree(mac_control->rings[i].ba);
8a4bdbaa 1081 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1082 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1083 }
1da177e4 1084 }
1da177e4 1085
2fda096d
SR		 1086 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1087 if (mac_control->fifos[i].ufo_in_band_v) {
1088 nic->mac_control.stats_info->sw_stat.mem_freed
1089 += (config->tx_cfg[i].fifo_len * sizeof(u64));
1090 kfree(mac_control->fifos[i].ufo_in_band_v);
1091 }
1092 }
1093
1da177e4 1094 if (mac_control->stats_mem) {
2fda096d
SR		 1095 nic->mac_control.stats_info->sw_stat.mem_freed +=
1096 mac_control->stats_mem_sz;
1da177e4
LT		 1097 pci_free_consistent(nic->pdev,
1098 mac_control->stats_mem_sz,
1099 mac_control->stats_mem,
1100 mac_control->stats_mem_phy);
491976b2 1101 }
1da177e4
LT		 1102}
1103
541ae68f 1104/**
1105 * s2io_verify_pci_mode -
1106 */
1107
1ee6dd77 1108static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1109{
1ee6dd77 1110 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1111 register u64 val64 = 0;
1112 int mode;
1113
1114 val64 = readq(&bar0->pci_mode);
1115 mode = (u8)GET_PCI_MODE(val64);
1116
1117 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1118 return -1; /* Unknown PCI mode */
1119 return mode;
1120}
1121
c92ca04b
AR		 1122#define NEC_VENID 0x1033
1123#define NEC_DEVID 0x0125
1124static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1125{
1126 struct pci_dev *tdev = NULL;
26d36b64
AC		 1127 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1128 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 1129 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 1130 pci_dev_put(tdev);
c92ca04b
AR		 1131 return 1;
1132 }
1133 }
1134 return 0;
1135}
541ae68f 1136
7b32a312 1137static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1138/**
1139 * s2io_print_pci_mode -
1140 */
1ee6dd77 1141static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1142{
1ee6dd77 1143 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1144 register u64 val64 = 0;
1145 int mode;
1146 struct config_param *config = &nic->config;
1147
1148 val64 = readq(&bar0->pci_mode);
1149 mode = (u8)GET_PCI_MODE(val64);
1150
1151 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1152 return -1; /* Unknown PCI mode */
1153
c92ca04b
AR		 1154 config->bus_speed = bus_speed[mode];
1155
1156 if (s2io_on_nec_bridge(nic->pdev)) {
1157 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1158 nic->dev->name);
1159 return mode;
1160 }
1161
541ae68f 1162 if (val64 & PCI_MODE_32_BITS) {
1163 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1164 } else {
1165 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1166 }
1167
1168 switch(mode) {
1169 case PCI_MODE_PCI_33:
1170 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f 1171 break;
1172 case PCI_MODE_PCI_66:
1173 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f 1174 break;
1175 case PCI_MODE_PCIX_M1_66:
1176 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f 1177 break;
1178 case PCI_MODE_PCIX_M1_100:
1179 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f 1180 break;
1181 case PCI_MODE_PCIX_M1_133:
1182 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f 1183 break;
1184 case PCI_MODE_PCIX_M2_66:
1185 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f 1186 break;
1187 case PCI_MODE_PCIX_M2_100:
1188 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f 1189 break;
1190 case PCI_MODE_PCIX_M2_133:
1191 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f 1192 break;
1193 default:
1194 return -1; /* Unsupported bus speed */
1195 }
1196
1197 return mode;
1198}
1199
b7c5678f
RV		 1200/**
1201 * init_tti - Initialization transmit traffic interrupt scheme
1202 * @nic: device private variable
1203 * @link: link status (UP/DOWN) used to enable/disable continuous
1204 * transmit interrupts
1205 * Description: The function configures transmit traffic interrupts
1206 * Return Value: SUCCESS on success and
1207 * '-1' on failure
1208 */
1209
0d66afe7 1210static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1211{
1212 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1213 register u64 val64 = 0;
1214 int i;
1215 struct config_param *config;
1216
1217 config = &nic->config;
1218
1219 for (i = 0; i < config->tx_fifo_num; i++) {
1220 /*
1221 * TTI Initialization. Default Tx timer gets us about
1222 * 250 interrupts per sec. Continuous interrupts are enabled
1223 * by default.
1224 */
1225 if (nic->device_type == XFRAME_II_DEVICE) {
1226 int count = (nic->config.bus_speed * 125)/2;
1227 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1228 } else
1229 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1230
1231 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1232 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1233 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1234 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1235
1236 if (use_continuous_tx_intrs && (link == LINK_UP))
1237 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1238 writeq(val64, &bar0->tti_data1_mem);
1239
1240 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1241 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1242 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1243 TTI_DATA2_MEM_TX_UFC_D(0x80);
1244
1245 writeq(val64, &bar0->tti_data2_mem);
1246
1247 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1248 TTI_CMD_MEM_OFFSET(i);
1249 writeq(val64, &bar0->tti_command_mem);
1250
1251 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1252 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1253 return FAILURE;
1254 }
1255
1256 return SUCCESS;
1257}
1258
20346722 1259/**
1260 * init_nic - Initialization of hardware
b7c5678f 1261 * @nic: device private variable
20346722 1262 * Description: The function sequentially configures every block
1263 * of the H/W from their reset values.
1264 * Return Value: SUCCESS on success and
1da177e4
LT		 1265 * '-1' on failure (endian settings incorrect).
1266 */
1267
1268static int init_nic(struct s2io_nic *nic)
1269{
1ee6dd77 1270 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1271 struct net_device *dev = nic->dev;
1272 register u64 val64 = 0;
1273 void __iomem *add;
1274 u32 time;
1275 int i, j;
1ee6dd77 1276 struct mac_info *mac_control;
1da177e4 1277 struct config_param *config;
c92ca04b 1278 int dtx_cnt = 0;
1da177e4 1279 unsigned long long mem_share;
20346722 1280 int mem_size;
1da177e4
LT		 1281
1282 mac_control = &nic->mac_control;
1283 config = &nic->config;
1284
5e25b9dd 1285 /* to set the swapper controle on the card */
20346722 1286 if(s2io_set_swapper(nic)) {
1da177e4 1287 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1288 return -EIO;
1da177e4
LT		 1289 }
1290
541ae68f 1291 /*
1292 * Herc requires EOI to be removed from reset before XGXS, so..
1293 */
1294 if (nic->device_type & XFRAME_II_DEVICE) {
1295 val64 = 0xA500000000ULL;
1296 writeq(val64, &bar0->sw_reset);
1297 msleep(500);
1298 val64 = readq(&bar0->sw_reset);
1299 }
1300
1da177e4
LT		 1301 /* Remove XGXS from reset state */
1302 val64 = 0;
1303 writeq(val64, &bar0->sw_reset);
1da177e4 1304 msleep(500);
20346722 1305 val64 = readq(&bar0->sw_reset);
1da177e4 1306
7962024e
SH		 1307 /* Ensure that it's safe to access registers by checking
1308 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1309 */
1310 if (nic->device_type == XFRAME_II_DEVICE) {
1311 for (i = 0; i < 50; i++) {
1312 val64 = readq(&bar0->adapter_status);
1313 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1314 break;
1315 msleep(10);
1316 }
1317 if (i == 50)
1318 return -ENODEV;
1319 }
1320
1da177e4
LT		 1321 /* Enable Receiving broadcasts */
1322 add = &bar0->mac_cfg;
1323 val64 = readq(&bar0->mac_cfg);
1324 val64 |= MAC_RMAC_BCAST_ENABLE;
1325 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1326 writel((u32) val64, add);
1327 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1328 writel((u32) (val64 >> 32), (add + 4));
1329
1330 /* Read registers in all blocks */
1331 val64 = readq(&bar0->mac_int_mask);
1332 val64 = readq(&bar0->mc_int_mask);
1333 val64 = readq(&bar0->xgxs_int_mask);
1334
1335 /* Set MTU */
1336 val64 = dev->mtu;
1337 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1338
541ae68f 1339 if (nic->device_type & XFRAME_II_DEVICE) {
1340 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1341 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1342 &bar0->dtx_control, UF);
541ae68f 1343 if (dtx_cnt & 0x1)
1344 msleep(1); /* Necessary!! */
1da177e4
LT		 1345 dtx_cnt++;
1346 }
541ae68f 1347 } else {
c92ca04b
AR		 1348 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1349 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1350 &bar0->dtx_control, UF);
1351 val64 = readq(&bar0->dtx_control);
1352 dtx_cnt++;
1da177e4
LT		 1353 }
1354 }
1355
1356 /* Tx DMA Initialization */
1357 val64 = 0;
1358 writeq(val64, &bar0->tx_fifo_partition_0);
1359 writeq(val64, &bar0->tx_fifo_partition_1);
1360 writeq(val64, &bar0->tx_fifo_partition_2);
1361 writeq(val64, &bar0->tx_fifo_partition_3);
1362
1363
1364 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1365 val64 |=
b7c5678f 1366 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1da177e4 1367 13) | vBIT(config->tx_cfg[i].fifo_priority,
b7c5678f 1368 ((j * 32) + 5), 3);
1da177e4
LT		 1369
1370 if (i == (config->tx_fifo_num - 1)) {
1371 if (i % 2 == 0)
1372 i++;
1373 }
1374
1375 switch (i) {
1376 case 1:
1377 writeq(val64, &bar0->tx_fifo_partition_0);
1378 val64 = 0;
b7c5678f 1379 j = 0;
1da177e4
LT		 1380 break;
1381 case 3:
1382 writeq(val64, &bar0->tx_fifo_partition_1);
1383 val64 = 0;
b7c5678f 1384 j = 0;
1da177e4
LT		 1385 break;
1386 case 5:
1387 writeq(val64, &bar0->tx_fifo_partition_2);
1388 val64 = 0;
b7c5678f 1389 j = 0;
1da177e4
LT		 1390 break;
1391 case 7:
1392 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1393 val64 = 0;
1394 j = 0;
1395 break;
1396 default:
1397 j++;
1da177e4
LT		 1398 break;
1399 }
1400 }
1401
5e25b9dd 1402 /*
1403 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1404 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1405 */
541ae68f 1406 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1407 (nic->pdev->revision < 4))
5e25b9dd 1408 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1409
1da177e4
LT		 1410 val64 = readq(&bar0->tx_fifo_partition_0);
1411 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1412 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1413
20346722 1414 /*
1415 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1416 * integrity checking.
1417 */
1418 val64 = readq(&bar0->tx_pa_cfg);
1419 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1420 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1421 writeq(val64, &bar0->tx_pa_cfg);
1422
1423 /* Rx DMA intialization. */
1424 val64 = 0;
1425 for (i = 0; i < config->rx_ring_num; i++) {
1426 val64 |=
1427 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1428 3);
1429 }
1430 writeq(val64, &bar0->rx_queue_priority);
1431
20346722 1432 /*
1433 * Allocating equal share of memory to all the
1da177e4
LT		 1434 * configured Rings.
1435 */
1436 val64 = 0;
541ae68f 1437 if (nic->device_type & XFRAME_II_DEVICE)
1438 mem_size = 32;
1439 else
1440 mem_size = 64;
1441
1da177e4
LT		 1442 for (i = 0; i < config->rx_ring_num; i++) {
1443 switch (i) {
1444 case 0:
20346722 1445 mem_share = (mem_size / config->rx_ring_num +
1446 mem_size % config->rx_ring_num);
1da177e4
LT		 1447 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1448 continue;
1449 case 1:
20346722 1450 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1451 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1452 continue;
1453 case 2:
20346722 1454 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1455 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1456 continue;
1457 case 3:
20346722 1458 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1459 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1460 continue;
1461 case 4:
20346722 1462 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1463 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1464 continue;
1465 case 5:
20346722 1466 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1467 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1468 continue;
1469 case 6:
20346722 1470 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1471 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1472 continue;
1473 case 7:
20346722 1474 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1475 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1476 continue;
1477 }
1478 }
1479 writeq(val64, &bar0->rx_queue_cfg);
1480
20346722 1481 /*
5e25b9dd 1482 * Filling Tx round robin registers
b7c5678f 1483 * as per the number of FIFOs for equal scheduling priority
1da177e4 1484 */
5e25b9dd 1485 switch (config->tx_fifo_num) {
1486 case 1:
b7c5678f 1487 val64 = 0x0;
5e25b9dd 1488 writeq(val64, &bar0->tx_w_round_robin_0);
1489 writeq(val64, &bar0->tx_w_round_robin_1);
1490 writeq(val64, &bar0->tx_w_round_robin_2);
1491 writeq(val64, &bar0->tx_w_round_robin_3);
1492 writeq(val64, &bar0->tx_w_round_robin_4);
1493 break;
1494 case 2:
b7c5678f 1495 val64 = 0x0001000100010001ULL;
5e25b9dd 1496 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1498 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1500 val64 = 0x0001000100000000ULL;
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_4);
1502 break;
1503 case 3:
b7c5678f 1504 val64 = 0x0001020001020001ULL;
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1506 val64 = 0x0200010200010200ULL;
5e25b9dd 1507 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1508 val64 = 0x0102000102000102ULL;
5e25b9dd 1509 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1510 val64 = 0x0001020001020001ULL;
5e25b9dd 1511 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1512 val64 = 0x0200010200000000ULL;
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_4);
1514 break;
1515 case 4:
b7c5678f 1516 val64 = 0x0001020300010203ULL;
5e25b9dd 1517 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1518 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1519 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1521 val64 = 0x0001020300000000ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_4);
1523 break;
1524 case 5:
b7c5678f 1525 val64 = 0x0001020304000102ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1527 val64 = 0x0304000102030400ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1529 val64 = 0x0102030400010203ULL;
5e25b9dd 1530 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1531 val64 = 0x0400010203040001ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1533 val64 = 0x0203040000000000ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_4);
1535 break;
1536 case 6:
b7c5678f 1537 val64 = 0x0001020304050001ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1539 val64 = 0x0203040500010203ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1541 val64 = 0x0405000102030405ULL;
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1543 val64 = 0x0001020304050001ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1545 val64 = 0x0203040500000000ULL;
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_4);
1547 break;
1548 case 7:
b7c5678f 1549 val64 = 0x0001020304050600ULL;
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1551 val64 = 0x0102030405060001ULL;
5e25b9dd 1552 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1553 val64 = 0x0203040506000102ULL;
5e25b9dd 1554 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1555 val64 = 0x0304050600010203ULL;
5e25b9dd 1556 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1557 val64 = 0x0405060000000000ULL;
5e25b9dd 1558 writeq(val64, &bar0->tx_w_round_robin_4);
1559 break;
1560 case 8:
b7c5678f 1561 val64 = 0x0001020304050607ULL;
5e25b9dd 1562 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1563 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1564 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1565 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1566 val64 = 0x0001020300000000ULL;
5e25b9dd 1567 writeq(val64, &bar0->tx_w_round_robin_4);
1568 break;
1569 }
1570
b41477f3 1571 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1572 val64 = readq(&bar0->tx_fifo_partition_0);
1573 val64 |= (TX_FIFO_PARTITION_EN);
1574 writeq(val64, &bar0->tx_fifo_partition_0);
1575
5e25b9dd 1576 /* Filling the Rx round robin registers as per the
1577 * number of Rings and steering based on QoS.
1578 */
1579 switch (config->rx_ring_num) {
1580 case 1:
1581 val64 = 0x8080808080808080ULL;
1582 writeq(val64, &bar0->rts_qos_steering);
1583 break;
1584 case 2:
1585 val64 = 0x0000010000010000ULL;
1586 writeq(val64, &bar0->rx_w_round_robin_0);
1587 val64 = 0x0100000100000100ULL;
1588 writeq(val64, &bar0->rx_w_round_robin_1);
1589 val64 = 0x0001000001000001ULL;
1590 writeq(val64, &bar0->rx_w_round_robin_2);
1591 val64 = 0x0000010000010000ULL;
1592 writeq(val64, &bar0->rx_w_round_robin_3);
1593 val64 = 0x0100000000000000ULL;
1594 writeq(val64, &bar0->rx_w_round_robin_4);
1595
1596 val64 = 0x8080808040404040ULL;
1597 writeq(val64, &bar0->rts_qos_steering);
1598 break;
1599 case 3:
1600 val64 = 0x0001000102000001ULL;
1601 writeq(val64, &bar0->rx_w_round_robin_0);
1602 val64 = 0x0001020000010001ULL;
1603 writeq(val64, &bar0->rx_w_round_robin_1);
1604 val64 = 0x0200000100010200ULL;
1605 writeq(val64, &bar0->rx_w_round_robin_2);
1606 val64 = 0x0001000102000001ULL;
1607 writeq(val64, &bar0->rx_w_round_robin_3);
1608 val64 = 0x0001020000000000ULL;
1609 writeq(val64, &bar0->rx_w_round_robin_4);
1610
1611 val64 = 0x8080804040402020ULL;
1612 writeq(val64, &bar0->rts_qos_steering);
1613 break;
1614 case 4:
1615 val64 = 0x0001020300010200ULL;
1616 writeq(val64, &bar0->rx_w_round_robin_0);
1617 val64 = 0x0100000102030001ULL;
1618 writeq(val64, &bar0->rx_w_round_robin_1);
1619 val64 = 0x0200010000010203ULL;
1620 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1621 val64 = 0x0001020001000001ULL;
5e25b9dd 1622 writeq(val64, &bar0->rx_w_round_robin_3);
1623 val64 = 0x0203000100000000ULL;
1624 writeq(val64, &bar0->rx_w_round_robin_4);
1625
1626 val64 = 0x8080404020201010ULL;
1627 writeq(val64, &bar0->rts_qos_steering);
1628 break;
1629 case 5:
1630 val64 = 0x0001000203000102ULL;
1631 writeq(val64, &bar0->rx_w_round_robin_0);
1632 val64 = 0x0001020001030004ULL;
1633 writeq(val64, &bar0->rx_w_round_robin_1);
1634 val64 = 0x0001000203000102ULL;
1635 writeq(val64, &bar0->rx_w_round_robin_2);
1636 val64 = 0x0001020001030004ULL;
1637 writeq(val64, &bar0->rx_w_round_robin_3);
1638 val64 = 0x0001000000000000ULL;
1639 writeq(val64, &bar0->rx_w_round_robin_4);
1640
1641 val64 = 0x8080404020201008ULL;
1642 writeq(val64, &bar0->rts_qos_steering);
1643 break;
1644 case 6:
1645 val64 = 0x0001020304000102ULL;
1646 writeq(val64, &bar0->rx_w_round_robin_0);
1647 val64 = 0x0304050001020001ULL;
1648 writeq(val64, &bar0->rx_w_round_robin_1);
1649 val64 = 0x0203000100000102ULL;
1650 writeq(val64, &bar0->rx_w_round_robin_2);
1651 val64 = 0x0304000102030405ULL;
1652 writeq(val64, &bar0->rx_w_round_robin_3);
1653 val64 = 0x0001000200000000ULL;
1654 writeq(val64, &bar0->rx_w_round_robin_4);
1655
1656 val64 = 0x8080404020100804ULL;
1657 writeq(val64, &bar0->rts_qos_steering);
1658 break;
1659 case 7:
1660 val64 = 0x0001020001020300ULL;
1661 writeq(val64, &bar0->rx_w_round_robin_0);
1662 val64 = 0x0102030400010203ULL;
1663 writeq(val64, &bar0->rx_w_round_robin_1);
1664 val64 = 0x0405060001020001ULL;
1665 writeq(val64, &bar0->rx_w_round_robin_2);
1666 val64 = 0x0304050000010200ULL;
1667 writeq(val64, &bar0->rx_w_round_robin_3);
1668 val64 = 0x0102030000000000ULL;
1669 writeq(val64, &bar0->rx_w_round_robin_4);
1670
1671 val64 = 0x8080402010080402ULL;
1672 writeq(val64, &bar0->rts_qos_steering);
1673 break;
1674 case 8:
1675 val64 = 0x0001020300040105ULL;
1676 writeq(val64, &bar0->rx_w_round_robin_0);
1677 val64 = 0x0200030106000204ULL;
1678 writeq(val64, &bar0->rx_w_round_robin_1);
1679 val64 = 0x0103000502010007ULL;
1680 writeq(val64, &bar0->rx_w_round_robin_2);
1681 val64 = 0x0304010002060500ULL;
1682 writeq(val64, &bar0->rx_w_round_robin_3);
1683 val64 = 0x0103020400000000ULL;
1684 writeq(val64, &bar0->rx_w_round_robin_4);
1685
1686 val64 = 0x8040201008040201ULL;
1687 writeq(val64, &bar0->rts_qos_steering);
1688 break;
1689 }
1da177e4
LT		 1690
1691 /* UDP Fix */
1692 val64 = 0;
20346722 1693 for (i = 0; i < 8; i++)
1da177e4
LT		 1694 writeq(val64, &bar0->rts_frm_len_n[i]);
1695
5e25b9dd 1696 /* Set the default rts frame length for the rings configured */
1697 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1698 for (i = 0 ; i < config->rx_ring_num ; i++)
1699 writeq(val64, &bar0->rts_frm_len_n[i]);
1700
1701 /* Set the frame length for the configured rings
1702 * desired by the user
1703 */
1704 for (i = 0; i < config->rx_ring_num; i++) {
1705 /* If rts_frm_len[i] == 0 then it is assumed that user not
1706 * specified frame length steering.
1707 * If the user provides the frame length then program
1708 * the rts_frm_len register for those values or else
1709 * leave it as it is.
1710 */
1711 if (rts_frm_len[i] != 0) {
1712 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1713 &bar0->rts_frm_len_n[i]);
1714 }
1715 }
8a4bdbaa 1716
9fc93a41
SS		 1717 /* Disable differentiated services steering logic */
1718 for (i = 0; i < 64; i++) {
1719 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1720 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1721 dev->name);
1722 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1723 return -ENODEV;
9fc93a41
SS		 1724 }
1725 }
1726
20346722 1727 /* Program statistics memory */
1da177e4 1728 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1729
541ae68f 1730 if (nic->device_type == XFRAME_II_DEVICE) {
1731 val64 = STAT_BC(0x320);
1732 writeq(val64, &bar0->stat_byte_cnt);
1733 }
1734
20346722 1735 /*
1da177e4
LT		 1736 * Initializing the sampling rate for the device to calculate the
1737 * bandwidth utilization.
1738 */
1739 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1740 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1741 writeq(val64, &bar0->mac_link_util);
1742
20346722 1743 /*
1744 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1745 * Scheme.
1746 */
1da177e4 1747
b7c5678f
RV		 1748 /* Initialize TTI */
1749 if (SUCCESS != init_tti(nic, nic->last_link_state))
1750 return -ENODEV;
1da177e4 1751
8a4bdbaa
SS		 1752 /* RTI Initialization */
1753 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1754 /*
8a4bdbaa
SS		 1755 * Programmed to generate Apprx 500 Intrs per
1756 * second
1757 */
1758 int count = (nic->config.bus_speed * 125)/4;
1759 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1760 } else
1761 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1762 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1763 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1764 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1765
1766 writeq(val64, &bar0->rti_data1_mem);
1767
1768 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1769 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1770 if (nic->config.intr_type == MSI_X)
1771 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1772 RTI_DATA2_MEM_RX_UFC_D(0x40));
1773 else
1774 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1775 RTI_DATA2_MEM_RX_UFC_D(0x80));
1776 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1777
8a4bdbaa
SS		 1778 for (i = 0; i < config->rx_ring_num; i++) {
1779 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1780 | RTI_CMD_MEM_OFFSET(i);
1781 writeq(val64, &bar0->rti_command_mem);
1da177e4 1782
8a4bdbaa
SS		 1783 /*
1784 * Once the operation completes, the Strobe bit of the
1785 * command register will be reset. We poll for this
1786 * particular condition. We wait for a maximum of 500ms
1787 * for the operation to complete, if it's not complete
1788 * by then we return error.
1789 */
1790 time = 0;
1791 while (TRUE) {
1792 val64 = readq(&bar0->rti_command_mem);
1793 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1794 break;
b6e3f982 1795
8a4bdbaa
SS		 1796 if (time > 10) {
1797 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1798 dev->name);
9f74ffde 1799 return -ENODEV;
b6e3f982 1800 }
8a4bdbaa
SS		 1801 time++;
1802 msleep(50);
1da177e4 1803 }
1da177e4
LT		 1804 }
1805
20346722 1806 /*
1807 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1808 * the 8 Queues on Rx side.
1809 */
1810 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1811 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1812
1813 /* Disable RMAC PAD STRIPPING */
509a2671 1814 add = &bar0->mac_cfg;
1da177e4
LT		 1815 val64 = readq(&bar0->mac_cfg);
1816 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1817 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818 writel((u32) (val64), add);
1819 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820 writel((u32) (val64 >> 32), (add + 4));
1821 val64 = readq(&bar0->mac_cfg);
1822
7d3d0439
RA		 1823 /* Enable FCS stripping by adapter */
1824 add = &bar0->mac_cfg;
1825 val64 = readq(&bar0->mac_cfg);
1826 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1827 if (nic->device_type == XFRAME_II_DEVICE)
1828 writeq(val64, &bar0->mac_cfg);
1829 else {
1830 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1831 writel((u32) (val64), add);
1832 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1833 writel((u32) (val64 >> 32), (add + 4));
1834 }
1835
20346722 1836 /*
1837 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1838 * generated by xena.
1839 */
1840 val64 = readq(&bar0->rmac_pause_cfg);
1841 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1842 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1843 writeq(val64, &bar0->rmac_pause_cfg);
1844
20346722 1845 /*
1da177e4
LT		 1846 * Set the Threshold Limit for Generating the pause frame
1847 * If the amount of data in any Queue exceeds ratio of
1848 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1849 * pause frame is generated
1850 */
1851 val64 = 0;
1852 for (i = 0; i < 4; i++) {
1853 val64 |=
1854 (((u64) 0xFF00 | nic->mac_control.
1855 mc_pause_threshold_q0q3)
1856 << (i * 2 * 8));
1857 }
1858 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1859
1860 val64 = 0;
1861 for (i = 0; i < 4; i++) {
1862 val64 |=
1863 (((u64) 0xFF00 | nic->mac_control.
1864 mc_pause_threshold_q4q7)
1865 << (i * 2 * 8));
1866 }
1867 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1868
20346722 1869 /*
1870 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1871 * exceeded the limit pointed by shared_splits
1872 */
1873 val64 = readq(&bar0->pic_control);
1874 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1875 writeq(val64, &bar0->pic_control);
1876
863c11a9
AR		 1877 if (nic->config.bus_speed == 266) {
1878 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1879 writeq(0x0, &bar0->read_retry_delay);
1880 writeq(0x0, &bar0->write_retry_delay);
1881 }
1882
541ae68f 1883 /*
1884 * Programming the Herc to split every write transaction
1885 * that does not start on an ADB to reduce disconnects.
1886 */
1887 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1888 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1889 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1890 writeq(val64, &bar0->misc_control);
1891 val64 = readq(&bar0->pic_control2);
b7b5a128 1892 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1893 writeq(val64, &bar0->pic_control2);
541ae68f 1894 }
c92ca04b
AR		 1895 if (strstr(nic->product_name, "CX4")) {
1896 val64 = TMAC_AVG_IPG(0x17);
1897 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1898 }
1899
1da177e4
LT		 1900 return SUCCESS;
1901}
a371a07d 1902#define LINK_UP_DOWN_INTERRUPT 1
1903#define MAC_RMAC_ERR_TIMER 2
1904
1ee6dd77 1905static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1906{
eaae7f72 1907 if (nic->config.intr_type != INTA)
cc6e7c44 1908 return MAC_RMAC_ERR_TIMER;
a371a07d 1909 if (nic->device_type == XFRAME_II_DEVICE)
1910 return LINK_UP_DOWN_INTERRUPT;
1911 else
1912 return MAC_RMAC_ERR_TIMER;
1913}
8116f3cf 1914
9caab458
SS		 1915/**
1916 * do_s2io_write_bits - update alarm bits in alarm register
1917 * @value: alarm bits
1918 * @flag: interrupt status
1919 * @addr: address value
1920 * Description: update alarm bits in alarm register
1921 * Return Value:
1922 * NONE.
1923 */
1924static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1925{
1926 u64 temp64;
1927
1928 temp64 = readq(addr);
1929
1930 if(flag == ENABLE_INTRS)
1931 temp64 &= ~((u64) value);
1932 else
1933 temp64 |= ((u64) value);
1934 writeq(temp64, addr);
1935}
1da177e4 1936
43b7c451 1937static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1938{
1939 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1940 register u64 gen_int_mask = 0;
1941
1942 if (mask & TX_DMA_INTR) {
1943
1944 gen_int_mask |= TXDMA_INT_M;
1945
1946 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1947 TXDMA_PCC_INT | TXDMA_TTI_INT |
1948 TXDMA_LSO_INT | TXDMA_TPA_INT |
1949 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1950
1951 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1952 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1953 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1954 &bar0->pfc_err_mask);
1955
1956 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1957 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1958 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1959
1960 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1961 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1962 PCC_N_SERR | PCC_6_COF_OV_ERR |
1963 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1964 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1965 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1966
1967 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1968 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1969
1970 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1971 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1972 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1973 flag, &bar0->lso_err_mask);
1974
1975 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1976 flag, &bar0->tpa_err_mask);
1977
1978 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1979
1980 }
1981
1982 if (mask & TX_MAC_INTR) {
1983 gen_int_mask |= TXMAC_INT_M;
1984 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1985 &bar0->mac_int_mask);
1986 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1987 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1988 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1989 flag, &bar0->mac_tmac_err_mask);
1990 }
1991
1992 if (mask & TX_XGXS_INTR) {
1993 gen_int_mask |= TXXGXS_INT_M;
1994 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1995 &bar0->xgxs_int_mask);
1996 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1997 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1998 flag, &bar0->xgxs_txgxs_err_mask);
1999 }
2000
2001 if (mask & RX_DMA_INTR) {
2002 gen_int_mask |= RXDMA_INT_M;
2003 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
2004 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
2005 flag, &bar0->rxdma_int_mask);
2006 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2007 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2008 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2009 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2010 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2011 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2012 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2013 &bar0->prc_pcix_err_mask);
2014 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2015 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2016 &bar0->rpa_err_mask);
2017 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2018 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2019 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2020 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2021 flag, &bar0->rda_err_mask);
2022 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2023 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2024 flag, &bar0->rti_err_mask);
2025 }
2026
2027 if (mask & RX_MAC_INTR) {
2028 gen_int_mask |= RXMAC_INT_M;
2029 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2030 &bar0->mac_int_mask);
2031 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2032 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2033 RMAC_DOUBLE_ECC_ERR |
2034 RMAC_LINK_STATE_CHANGE_INT,
2035 flag, &bar0->mac_rmac_err_mask);
2036 }
2037
2038 if (mask & RX_XGXS_INTR)
2039 {
2040 gen_int_mask |= RXXGXS_INT_M;
2041 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2042 &bar0->xgxs_int_mask);
2043 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2044 &bar0->xgxs_rxgxs_err_mask);
2045 }
2046
2047 if (mask & MC_INTR) {
2048 gen_int_mask |= MC_INT_M;
2049 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2050 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2051 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2052 &bar0->mc_err_mask);
2053 }
2054 nic->general_int_mask = gen_int_mask;
2055
2056 /* Remove this line when alarm interrupts are enabled */
2057 nic->general_int_mask = 0;
2058}
20346722 2059/**
2060 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2061 * @nic: device private variable,
2062 * @mask: A mask indicating which Intr block must be modified and,
2063 * @flag: A flag indicating whether to enable or disable the Intrs.
2064 * Description: This function will either disable or enable the interrupts
20346722 2065 * depending on the flag argument. The mask argument can be used to
2066 * enable/disable any Intr block.
1da177e4
LT		 2067 * Return Value: NONE.
2068 */
2069
2070static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2071{
1ee6dd77 2072 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2073 register u64 temp64 = 0, intr_mask = 0;
2074
2075 intr_mask = nic->general_int_mask;
1da177e4
LT		 2076
2077 /* Top level interrupt classification */
2078 /* PIC Interrupts */
9caab458 2079 if (mask & TX_PIC_INTR) {
1da177e4 2080 /* Enable PIC Intrs in the general intr mask register */
9caab458 2081 intr_mask |= TXPIC_INT_M;
1da177e4 2082 if (flag == ENABLE_INTRS) {
20346722 2083 /*
a371a07d 2084 * If Hercules adapter enable GPIO otherwise
b41477f3 2085 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2086 * interrupts for now.
2087 * TODO
1da177e4 2088 */
a371a07d 2089 if (s2io_link_fault_indication(nic) ==
2090 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2091 do_s2io_write_bits(PIC_INT_GPIO, flag,
2092 &bar0->pic_int_mask);
2093 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2094 &bar0->gpio_int_mask);
2095 } else
a371a07d 2096 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2097 } else if (flag == DISABLE_INTRS) {
20346722 2098 /*
2099 * Disable PIC Intrs in the general
2100 * intr mask register
1da177e4
LT		 2101 */
2102 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2103 }
2104 }
2105
1da177e4
LT		 2106 /* Tx traffic interrupts */
2107 if (mask & TX_TRAFFIC_INTR) {
9caab458 2108 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2109 if (flag == ENABLE_INTRS) {
20346722 2110 /*
1da177e4 2111 * Enable all the Tx side interrupts
20346722 2112 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2113 */
2114 writeq(0x0, &bar0->tx_traffic_mask);
2115 } else if (flag == DISABLE_INTRS) {
20346722 2116 /*
2117 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2118 * register.
2119 */
2120 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2121 }
2122 }
2123
2124 /* Rx traffic interrupts */
2125 if (mask & RX_TRAFFIC_INTR) {
9caab458 2126 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2127 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2128 /* writing 0 Enables all 8 RX interrupt levels */
2129 writeq(0x0, &bar0->rx_traffic_mask);
2130 } else if (flag == DISABLE_INTRS) {
20346722 2131 /*
2132 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2133 * register.
2134 */
2135 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2136 }
2137 }
9caab458
SS		 2138
2139 temp64 = readq(&bar0->general_int_mask);
2140 if (flag == ENABLE_INTRS)
2141 temp64 &= ~((u64) intr_mask);
2142 else
2143 temp64 = DISABLE_ALL_INTRS;
2144 writeq(temp64, &bar0->general_int_mask);
2145
2146 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2147}
2148
19a60522
SS		 2149/**
2150 * verify_pcc_quiescent- Checks for PCC quiescent state
2151 * Return: 1 If PCC is quiescence
2152 * 0 If PCC is not quiescence
2153 */
1ee6dd77 2154static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2155{
19a60522 2156 int ret = 0, herc;
1ee6dd77 2157 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2158 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2159
19a60522 2160 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2161
2162 if (flag == FALSE) {
44c10138 2163 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2164 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2165 ret = 1;
19a60522
SS		 2166 } else {
2167 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2168 ret = 1;
20346722 2169 }
2170 } else {
44c10138 2171 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2172 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2173 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2174 ret = 1;
5e25b9dd 2175 } else {
2176 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2177 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2178 ret = 1;
20346722 2179 }
2180 }
2181
2182 return ret;
2183}
2184/**
2185 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2186 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2187 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2188 * differs and the calling function passes the input argument flag to
2189 * indicate this.
20346722 2190 * Return: 1 If xena is quiescence
1da177e4
LT		 2191 * 0 If Xena is not quiescence
2192 */
2193
1ee6dd77 2194static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2195{
19a60522 2196 int mode;
1ee6dd77 2197 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2198 u64 val64 = readq(&bar0->adapter_status);
2199 mode = s2io_verify_pci_mode(sp);
1da177e4 2200
19a60522
SS		 2201 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2202 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2203 return 0;
2204 }
2205 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2206 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2207 return 0;
2208 }
2209 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2210 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2211 return 0;
2212 }
2213 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2214 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2215 return 0;
2216 }
2217 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2218 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2219 return 0;
2220 }
2221 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2222 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2223 return 0;
2224 }
2225 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2226 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2227 return 0;
2228 }
2229 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2230 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2231 return 0;
1da177e4
LT		 2232 }
2233
19a60522
SS		 2234 /*
2235 * In PCI 33 mode, the P_PLL is not used, and therefore,
2236 * the the P_PLL_LOCK bit in the adapter_status register will
2237 * not be asserted.
2238 */
2239 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2240 sp->device_type == XFRAME_II_DEVICE && mode !=
2241 PCI_MODE_PCI_33) {
2242 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2243 return 0;
2244 }
2245 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2246 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2247 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2248 return 0;
2249 }
2250 return 1;
1da177e4
LT		 2251}
2252
2253/**
2254 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2255 * @sp: Pointer to device specifc structure
20346722 2256 * Description :
1da177e4
LT		 2257 * New procedure to clear mac address reading problems on Alpha platforms
2258 *
2259 */
2260
1ee6dd77 2261static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2262{
1ee6dd77 2263 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2264 u64 val64;
2265 int i = 0;
2266
2267 while (fix_mac[i] != END_SIGN) {
2268 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2269 udelay(10);
1da177e4
LT		 2270 val64 = readq(&bar0->gpio_control);
2271 }
2272}
2273
2274/**
20346722 2275 * start_nic - Turns the device on
1da177e4 2276 * @nic : device private variable.
20346722 2277 * Description:
2278 * This function actually turns the device on. Before this function is
2279 * called,all Registers are configured from their reset states
2280 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2281 * calling this function, the device interrupts are cleared and the NIC is
2282 * literally switched on by writing into the adapter control register.
20346722 2283 * Return Value:
1da177e4
LT		 2284 * SUCCESS on success and -1 on failure.
2285 */
2286
2287static int start_nic(struct s2io_nic *nic)
2288{
1ee6dd77 2289 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2290 struct net_device *dev = nic->dev;
2291 register u64 val64 = 0;
20346722 2292 u16 subid, i;
1ee6dd77 2293 struct mac_info *mac_control;
1da177e4
LT		 2294 struct config_param *config;
2295
2296 mac_control = &nic->mac_control;
2297 config = &nic->config;
2298
2299 /* PRC Initialization and configuration */
2300 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2301 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2302 &bar0->prc_rxd0_n[i]);
2303
2304 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2305 if (nic->rxd_mode == RXD_MODE_1)
2306 val64 |= PRC_CTRL_RC_ENABLED;
2307 else
2308 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2309 if (nic->device_type == XFRAME_II_DEVICE)
2310 val64 |= PRC_CTRL_GROUP_READS;
2311 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2312 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2313 writeq(val64, &bar0->prc_ctrl_n[i]);
2314 }
2315
da6971d8
AR		 2316 if (nic->rxd_mode == RXD_MODE_3B) {
2317 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2318 val64 = readq(&bar0->rx_pa_cfg);
2319 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2320 writeq(val64, &bar0->rx_pa_cfg);
2321 }
1da177e4 2322
926930b2
SS		 2323 if (vlan_tag_strip == 0) {
2324 val64 = readq(&bar0->rx_pa_cfg);
2325 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2326 writeq(val64, &bar0->rx_pa_cfg);
2327 vlan_strip_flag = 0;
2328 }
2329
20346722 2330 /*
1da177e4
LT		 2331 * Enabling MC-RLDRAM. After enabling the device, we timeout
2332 * for around 100ms, which is approximately the time required
2333 * for the device to be ready for operation.
2334 */
2335 val64 = readq(&bar0->mc_rldram_mrs);
2336 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2337 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2338 val64 = readq(&bar0->mc_rldram_mrs);
2339
20346722 2340 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2341
2342 /* Enabling ECC Protection. */
2343 val64 = readq(&bar0->adapter_control);
2344 val64 &= ~ADAPTER_ECC_EN;
2345 writeq(val64, &bar0->adapter_control);
2346
20346722 2347 /*
2348 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2349 * it.
2350 */
2351 val64 = readq(&bar0->adapter_status);
19a60522 2352 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2353 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2354 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2355 (unsigned long long) val64);
2356 return FAILURE;
2357 }
2358
20346722 2359 /*
1da177e4 2360 * With some switches, link might be already up at this point.
20346722 2361 * Because of this weird behavior, when we enable laser,
2362 * we may not get link. We need to handle this. We cannot
2363 * figure out which switch is misbehaving. So we are forced to
2364 * make a global change.
1da177e4
LT		 2365 */
2366
2367 /* Enabling Laser. */
2368 val64 = readq(&bar0->adapter_control);
2369 val64 |= ADAPTER_EOI_TX_ON;
2370 writeq(val64, &bar0->adapter_control);
2371
c92ca04b
AR		 2372 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2373 /*
2374 * Dont see link state interrupts initally on some switches,
2375 * so directly scheduling the link state task here.
2376 */
2377 schedule_work(&nic->set_link_task);
2378 }
1da177e4
LT		 2379 /* SXE-002: Initialize link and activity LED */
2380 subid = nic->pdev->subsystem_device;
541ae68f 2381 if (((subid & 0xFF) >= 0x07) &&
2382 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2383 val64 = readq(&bar0->gpio_control);
2384 val64 |= 0x0000800000000000ULL;
2385 writeq(val64, &bar0->gpio_control);
2386 val64 = 0x0411040400000000ULL;
509a2671 2387 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2388 }
2389
1da177e4
LT		 2390 return SUCCESS;
2391}
fed5eccd
AR		 2392/**
2393 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2394 */
1ee6dd77
RB		 2395static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2396 TxD *txdlp, int get_off)
fed5eccd 2397{
1ee6dd77 2398 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2399 struct sk_buff *skb;
1ee6dd77 2400 struct TxD *txds;
fed5eccd
AR		 2401 u16 j, frg_cnt;
2402
2403 txds = txdlp;
2fda096d 2404 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2405 pci_unmap_single(nic->pdev, (dma_addr_t)
2406 txds->Buffer_Pointer, sizeof(u64),
2407 PCI_DMA_TODEVICE);
2408 txds++;
2409 }
2410
2411 skb = (struct sk_buff *) ((unsigned long)
2412 txds->Host_Control);
2413 if (!skb) {
1ee6dd77 2414 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2415 return NULL;
2416 }
2417 pci_unmap_single(nic->pdev, (dma_addr_t)
2418 txds->Buffer_Pointer,
2419 skb->len - skb->data_len,
2420 PCI_DMA_TODEVICE);
2421 frg_cnt = skb_shinfo(skb)->nr_frags;
2422 if (frg_cnt) {
2423 txds++;
2424 for (j = 0; j < frg_cnt; j++, txds++) {
2425 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2426 if (!txds->Buffer_Pointer)
2427 break;
6aa20a22 2428 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2429 txds->Buffer_Pointer,
2430 frag->size, PCI_DMA_TODEVICE);
2431 }
2432 }
1ee6dd77 2433 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2434 return(skb);
2435}
1da177e4 2436
20346722 2437/**
2438 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2439 * @nic : device private variable.
20346722 2440 * Description:
1da177e4 2441 * Free all queued Tx buffers.
20346722 2442 * Return Value: void
1da177e4
LT		 2443*/
2444
2445static void free_tx_buffers(struct s2io_nic *nic)
2446{
2447 struct net_device *dev = nic->dev;
2448 struct sk_buff *skb;
1ee6dd77 2449 struct TxD *txdp;
1da177e4 2450 int i, j;
1ee6dd77 2451 struct mac_info *mac_control;
1da177e4 2452 struct config_param *config;
fed5eccd 2453 int cnt = 0;
1da177e4
LT		 2454
2455 mac_control = &nic->mac_control;
2456 config = &nic->config;
2457
2458 for (i = 0; i < config->tx_fifo_num; i++) {
2fda096d
SR		 2459 unsigned long flags;
2460 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
b35b3b49 2461 for (j = 0; j < config->tx_cfg[i].fifo_len; j++) {
491976b2
SH		 2462 txdp = (struct TxD *) \
2463 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2464 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2465 if (skb) {
8a4bdbaa 2466 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2467 += skb->truesize;
fed5eccd
AR		 2468 dev_kfree_skb(skb);
2469 cnt++;
1da177e4 2470 }
1da177e4
LT		 2471 }
2472 DBG_PRINT(INTR_DBG,
2473 "%s:forcibly freeing %d skbs on FIFO%d\n",
2474 dev->name, cnt, i);
20346722 2475 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2476 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2fda096d 2477 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
1da177e4
LT		 2478 }
2479}
2480
20346722 2481/**
2482 * stop_nic - To stop the nic
1da177e4 2483 * @nic ; device private variable.
20346722 2484 * Description:
2485 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2486 * function does. This function is called to stop the device.
2487 * Return Value:
2488 * void.
2489 */
2490
2491static void stop_nic(struct s2io_nic *nic)
2492{
1ee6dd77 2493 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2494 register u64 val64 = 0;
5d3213cc 2495 u16 interruptible;
1ee6dd77 2496 struct mac_info *mac_control;
1da177e4
LT		 2497 struct config_param *config;
2498
2499 mac_control = &nic->mac_control;
2500 config = &nic->config;
2501
2502 /* Disable all interrupts */
9caab458 2503 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2504 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2505 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2506 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2507
5d3213cc
AR		 2508 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2509 val64 = readq(&bar0->adapter_control);
2510 val64 &= ~(ADAPTER_CNTL_EN);
2511 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2512}
2513
20346722 2514/**
2515 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2516 * @nic: device private variable
20346722 2517 * @ring_no: ring number
2518 * Description:
1da177e4
LT		 2519 * The function allocates Rx side skbs and puts the physical
2520 * address of these buffers into the RxD buffer pointers, so that the NIC
2521 * can DMA the received frame into these locations.
2522 * The NIC supports 3 receive modes, viz
2523 * 1. single buffer,
2524 * 2. three buffer and
2525 * 3. Five buffer modes.
20346722 2526 * Each mode defines how many fragments the received frame will be split
2527 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2528 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2529 * is split into 3 fragments. As of now only single buffer mode is
2530 * supported.
2531 * Return Value:
2532 * SUCCESS on success or an appropriate -ve value on failure.
2533 */
2534
ac1f60db 2535static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2536{
2537 struct net_device *dev = nic->dev;
2538 struct sk_buff *skb;
1ee6dd77 2539 struct RxD_t *rxdp;
1da177e4 2540 int off, off1, size, block_no, block_no1;
1da177e4 2541 u32 alloc_tab = 0;
20346722 2542 u32 alloc_cnt;
1ee6dd77 2543 struct mac_info *mac_control;
1da177e4 2544 struct config_param *config;
20346722 2545 u64 tmp;
1ee6dd77 2546 struct buffAdd *ba;
1da177e4 2547 unsigned long flags;
1ee6dd77 2548 struct RxD_t *first_rxdp = NULL;
363dc367 2549 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
6d517a27
VP		 2550 struct RxD1 *rxdp1;
2551 struct RxD3 *rxdp3;
491abf25 2552 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
1da177e4
LT		 2553
2554 mac_control = &nic->mac_control;
2555 config = &nic->config;
20346722 2556 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2557 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2558
5d3213cc 2559 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2560 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2561 while (alloc_tab < alloc_cnt) {
20346722 2562 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2563 block_index;
20346722 2564 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2565
da6971d8
AR		 2566 rxdp = mac_control->rings[ring_no].
2567 rx_blocks[block_no].rxds[off].virt_addr;
2568
2569 if ((block_no == block_no1) && (off == off1) &&
2570 (rxdp->Host_Control)) {
2571 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2572 dev->name);
1da177e4
LT		 2573 DBG_PRINT(INTR_DBG, " info equated\n");
2574 goto end;
2575 }
da6971d8 2576 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2577 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2578 block_index++;
da6971d8
AR		 2579 if (mac_control->rings[ring_no].rx_curr_put_info.
2580 block_index == mac_control->rings[ring_no].
2581 block_count)
2582 mac_control->rings[ring_no].rx_curr_put_info.
2583 block_index = 0;
2584 block_no = mac_control->rings[ring_no].
2585 rx_curr_put_info.block_index;
2586 if (off == rxd_count[nic->rxd_mode])
2587 off = 0;
20346722 2588 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2589 offset = off;
2590 rxdp = mac_control->rings[ring_no].
2591 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2592 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2593 dev->name, rxdp);
2594 }
db874e65
SS		 2595 if(!napi) {
2596 spin_lock_irqsave(&nic->put_lock, flags);
2597 mac_control->rings[ring_no].put_pos =
2598 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2599 spin_unlock_irqrestore(&nic->put_lock, flags);
2600 } else {
2601 mac_control->rings[ring_no].put_pos =
2602 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2603 }
da6971d8 2604 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
6d517a27 2605 ((nic->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2606 (rxdp->Control_2 & s2BIT(0)))) {
20346722 2607 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2608 offset = off;
1da177e4
LT		 2609 goto end;
2610 }
da6971d8
AR		 2611 /* calculate size of skb based on ring mode */
2612 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2613 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2614 if (nic->rxd_mode == RXD_MODE_1)
2615 size += NET_IP_ALIGN;
da6971d8 2616 else
6d517a27 2617 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2618
da6971d8
AR		 2619 /* allocate skb */
2620 skb = dev_alloc_skb(size);
2621 if(!skb) {
0c61ed5f
RV		 2622 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2623 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b 2624 if (first_rxdp) {
2625 wmb();
2626 first_rxdp->Control_1 |= RXD_OWN_XENA;
2627 }
c53d4945
SH		 2628 nic->mac_control.stats_info->sw_stat. \
2629 mem_alloc_fail_cnt++;
da6971d8
AR		 2630 return -ENOMEM ;
2631 }
8a4bdbaa 2632 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 2633 += skb->truesize;
da6971d8
AR		 2634 if (nic->rxd_mode == RXD_MODE_1) {
2635 /* 1 buffer mode - normal operation mode */
6d517a27 2636 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2637 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2638 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2639 rxdp1->Buffer0_ptr = pci_map_single
863c11a9
AR		 2640 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2641 PCI_DMA_FROMDEVICE);
491abf25
VP		 2642 if( (rxdp1->Buffer0_ptr == 0) ||
2643 (rxdp1->Buffer0_ptr ==
2644 DMA_ERROR_CODE))
2645 goto pci_map_failed;
2646
8a4bdbaa 2647 rxdp->Control_2 =
491976b2 2648 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8 2649
6d517a27 2650 } else if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8 2651 /*
6d517a27
VP		 2652 * 2 buffer mode -
2653 * 2 buffer mode provides 128
da6971d8 2654 * byte aligned receive buffers.
da6971d8
AR		 2655 */
2656
6d517a27 2657 rxdp3 = (struct RxD3*)rxdp;
491976b2 2658 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2659 Buffer0_ptr = rxdp3->Buffer0_ptr;
2660 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2661 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2662 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2663 rxdp3->Buffer0_ptr = Buffer0_ptr;
2664 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2665
da6971d8
AR		 2666 ba = &mac_control->rings[ring_no].ba[block_no][off];
2667 skb_reserve(skb, BUF0_LEN);
2668 tmp = (u64)(unsigned long) skb->data;
2669 tmp += ALIGN_SIZE;
2670 tmp &= ~ALIGN_SIZE;
2671 skb->data = (void *) (unsigned long)tmp;
27a884dc 2672 skb_reset_tail_pointer(skb);
da6971d8 2673
6d517a27
VP		 2674 if (!(rxdp3->Buffer0_ptr))
2675 rxdp3->Buffer0_ptr =
75c30b13 2676 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2677 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2678 else
2679 pci_dma_sync_single_for_device(nic->pdev,
6d517a27 2680 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2681 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25
VP		 2682 if( (rxdp3->Buffer0_ptr == 0) ||
2683 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2684 goto pci_map_failed;
2685
da6971d8
AR		 2686 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2687 if (nic->rxd_mode == RXD_MODE_3B) {
2688 /* Two buffer mode */
2689
2690 /*
6aa20a22 2691 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2692 * L4 payload
2693 */
6d517a27 2694 rxdp3->Buffer2_ptr = pci_map_single
da6971d8
AR		 2695 (nic->pdev, skb->data, dev->mtu + 4,
2696 PCI_DMA_FROMDEVICE);
2697
491abf25
VP		 2698 if( (rxdp3->Buffer2_ptr == 0) ||
2699 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2700 goto pci_map_failed;
2701
2702 rxdp3->Buffer1_ptr =
6aa20a22 2703 pci_map_single(nic->pdev,
75c30b13
AR		 2704 ba->ba_1, BUF1_LEN,
2705 PCI_DMA_FROMDEVICE);
491abf25
VP		 2706 if( (rxdp3->Buffer1_ptr == 0) ||
2707 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2708 pci_unmap_single
2709 (nic->pdev,
3e847423 2710 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 2711 dev->mtu + 4,
2712 PCI_DMA_FROMDEVICE);
2713 goto pci_map_failed;
75c30b13 2714 }
da6971d8
AR		 2715 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2716 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2717 (dev->mtu + 4);
da6971d8 2718 }
b7b5a128 2719 rxdp->Control_2 |= s2BIT(0);
1da177e4 2720 }
1da177e4 2721 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b 2722 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2723 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2724 off++;
da6971d8
AR		 2725 if (off == (rxd_count[nic->rxd_mode] + 1))
2726 off = 0;
20346722 2727 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2728
da6971d8 2729 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2730 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2731 if (first_rxdp) {
2732 wmb();
2733 first_rxdp->Control_1 |= RXD_OWN_XENA;
2734 }
2735 first_rxdp = rxdp;
2736 }
1da177e4
LT		 2737 atomic_inc(&nic->rx_bufs_left[ring_no]);
2738 alloc_tab++;
2739 }
2740
2741 end:
303bcb4b 2742 /* Transfer ownership of first descriptor to adapter just before
2743 * exiting. Before that, use memory barrier so that ownership
2744 * and other fields are seen by adapter correctly.
2745 */
2746 if (first_rxdp) {
2747 wmb();
2748 first_rxdp->Control_1 |= RXD_OWN_XENA;
2749 }
2750
1da177e4 2751 return SUCCESS;
491abf25
VP		 2752pci_map_failed:
2753 stats->pci_map_fail_cnt++;
2754 stats->mem_freed += skb->truesize;
2755 dev_kfree_skb_irq(skb);
2756 return -ENOMEM;
1da177e4
LT		 2757}
2758
da6971d8
AR		 2759static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2760{
2761 struct net_device *dev = sp->dev;
2762 int j;
2763 struct sk_buff *skb;
1ee6dd77
RB		 2764 struct RxD_t *rxdp;
2765 struct mac_info *mac_control;
2766 struct buffAdd *ba;
6d517a27
VP		 2767 struct RxD1 *rxdp1;
2768 struct RxD3 *rxdp3;
da6971d8
AR		 2769
2770 mac_control = &sp->mac_control;
2771 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2772 rxdp = mac_control->rings[ring_no].
2773 rx_blocks[blk].rxds[j].virt_addr;
2774 skb = (struct sk_buff *)
2775 ((unsigned long) rxdp->Host_Control);
2776 if (!skb) {
2777 continue;
2778 }
2779 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2780 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2781 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2782 rxdp1->Buffer0_ptr,
2783 dev->mtu +
2784 HEADER_ETHERNET_II_802_3_SIZE
2785 + HEADER_802_2_SIZE +
2786 HEADER_SNAP_SIZE,
2787 PCI_DMA_FROMDEVICE);
1ee6dd77 2788 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2789 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2790 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2791 ba = &mac_control->rings[ring_no].
2792 ba[blk][j];
2793 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2794 rxdp3->Buffer0_ptr,
2795 BUF0_LEN,
da6971d8
AR		 2796 PCI_DMA_FROMDEVICE);
2797 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2798 rxdp3->Buffer1_ptr,
2799 BUF1_LEN,
da6971d8
AR		 2800 PCI_DMA_FROMDEVICE);
2801 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2802 rxdp3->Buffer2_ptr,
2803 dev->mtu + 4,
da6971d8 2804 PCI_DMA_FROMDEVICE);
1ee6dd77 2805 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2806 }
491976b2 2807 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2808 dev_kfree_skb(skb);
2809 atomic_dec(&sp->rx_bufs_left[ring_no]);
2810 }
2811}
2812
1da177e4 2813/**
20346722 2814 * free_rx_buffers - Frees all Rx buffers
1da177e4 2815 * @sp: device private variable.
20346722 2816 * Description:
1da177e4
LT		 2817 * This function will free all Rx buffers allocated by host.
2818 * Return Value:
2819 * NONE.
2820 */
2821
2822static void free_rx_buffers(struct s2io_nic *sp)
2823{
2824 struct net_device *dev = sp->dev;
da6971d8 2825 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2826 struct mac_info *mac_control;
1da177e4 2827 struct config_param *config;
1da177e4
LT		 2828
2829 mac_control = &sp->mac_control;
2830 config = &sp->config;
2831
2832 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2833 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2834 free_rxd_blk(sp,i,blk);
1da177e4 2835
20346722 2836 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2837 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2838 mac_control->rings[i].rx_curr_put_info.offset = 0;
2839 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2840 atomic_set(&sp->rx_bufs_left[i], 0);
2841 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2842 dev->name, buf_cnt, i);
2843 }
2844}
2845
2846/**
2847 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2848 * @napi : pointer to the napi structure.
20346722 2849 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2850 * during one pass through the 'Poll" function.
2851 * Description:
2852 * Comes into picture only if NAPI support has been incorporated. It does
2853 * the same thing that rx_intr_handler does, but not in a interrupt context
2854 * also It will process only a given number of packets.
2855 * Return value:
2856 * 0 on success and 1 if there are No Rx packets to be processed.
2857 */
2858
bea3348e 2859static int s2io_poll(struct napi_struct *napi, int budget)
1da177e4 2860{
bea3348e
SH		 2861 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2862 struct net_device *dev = nic->dev;
20346722 2863 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2864 struct mac_info *mac_control;
1da177e4 2865 struct config_param *config;
1ee6dd77 2866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2867 int i;
1da177e4
LT		 2868
2869 mac_control = &nic->mac_control;
2870 config = &nic->config;
2871
bea3348e 2872 nic->pkts_to_process = budget;
20346722 2873 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2874
19a60522
SS		 2875 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2876 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2877
2878 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2879 rx_intr_handler(&mac_control->rings[i]);
2880 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2881 if (!nic->pkts_to_process) {
2882 /* Quota for the current iteration has been met */
2883 goto no_rx;
1da177e4 2884 }
1da177e4 2885 }
1da177e4 2886
bea3348e 2887 netif_rx_complete(dev, napi);
1da177e4
LT		 2888
2889 for (i = 0; i < config->rx_ring_num; i++) {
2890 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2891 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2892 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2893 break;
2894 }
2895 }
2896 /* Re enable the Rx interrupts. */
c92ca04b 2897 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2898 readl(&bar0->rx_traffic_mask);
bea3348e 2899 return pkt_cnt;
1da177e4 2900
20346722 2901no_rx:
1da177e4
LT		 2902 for (i = 0; i < config->rx_ring_num; i++) {
2903 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2904 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2905 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2906 break;
2907 }
2908 }
bea3348e 2909 return pkt_cnt;
1da177e4 2910}
20346722 2911
b41477f3 2912#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2913/**
b41477f3 2914 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2915 * @dev : pointer to the device structure.
2916 * Description:
b41477f3
AR		 2917 * This function will be called by upper layer to check for events on the
2918 * interface in situations where interrupts are disabled. It is used for
2919 * specific in-kernel networking tasks, such as remote consoles and kernel
2920 * debugging over the network (example netdump in RedHat).
612eff0e 2921 */
612eff0e
BH		 2922static void s2io_netpoll(struct net_device *dev)
2923{
1ee6dd77
RB		 2924 struct s2io_nic *nic = dev->priv;
2925 struct mac_info *mac_control;
612eff0e 2926 struct config_param *config;
1ee6dd77 2927 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2928 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2929 int i;
2930
d796fdb7
LV		 2931 if (pci_channel_offline(nic->pdev))
2932 return;
2933
612eff0e
BH		 2934 disable_irq(dev->irq);
2935
612eff0e
BH		 2936 mac_control = &nic->mac_control;
2937 config = &nic->config;
2938
612eff0e 2939 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2940 writeq(val64, &bar0->tx_traffic_int);
2941
6aa20a22 2942 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2943 * run out of skbs and will fail and eventually netpoll application such
2944 * as netdump will fail.
2945 */
2946 for (i = 0; i < config->tx_fifo_num; i++)
2947 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2948
b41477f3 2949 /* check for received packet and indicate up to network */
612eff0e
BH		 2950 for (i = 0; i < config->rx_ring_num; i++)
2951 rx_intr_handler(&mac_control->rings[i]);
2952
2953 for (i = 0; i < config->rx_ring_num; i++) {
2954 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2955 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2956 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2957 break;
2958 }
2959 }
612eff0e
BH		 2960 enable_irq(dev->irq);
2961 return;
2962}
2963#endif
2964
20346722 2965/**
1da177e4
LT		 2966 * rx_intr_handler - Rx interrupt handler
2967 * @nic: device private variable.
20346722 2968 * Description:
2969 * If the interrupt is because of a received frame or if the
1da177e4 2970 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2971 * called. It picks out the RxD at which place the last Rx processing had
2972 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2973 * the offset.
2974 * Return Value:
2975 * NONE.
2976 */
1ee6dd77 2977static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2978{
1ee6dd77 2979 struct s2io_nic *nic = ring_data->nic;
1da177e4 2980 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2981 int get_block, put_block, put_offset;
1ee6dd77
RB		 2982 struct rx_curr_get_info get_info, put_info;
2983 struct RxD_t *rxdp;
1da177e4 2984 struct sk_buff *skb;
20346722 2985 int pkt_cnt = 0;
7d3d0439 2986 int i;
6d517a27
VP		 2987 struct RxD1* rxdp1;
2988 struct RxD3* rxdp3;
7d3d0439 2989
7ba013ac 2990 spin_lock(&nic->rx_lock);
7ba013ac 2991
20346722 2992 get_info = ring_data->rx_curr_get_info;
2993 get_block = get_info.block_index;
1ee6dd77 2994 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2995 put_block = put_info.block_index;
da6971d8 2996 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2997 if (!napi) {
2998 spin_lock(&nic->put_lock);
2999 put_offset = ring_data->put_pos;
3000 spin_unlock(&nic->put_lock);
3001 } else
3002 put_offset = ring_data->put_pos;
3003
da6971d8 3004 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 3005 /*
3006 * If your are next to put index then it's
3007 * FIFO full condition
3008 */
da6971d8
AR		 3009 if ((get_block == put_block) &&
3010 (get_info.offset + 1) == put_info.offset) {
75c30b13 3011 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 3012 break;
3013 }
20346722 3014 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
3015 if (skb == NULL) {
3016 DBG_PRINT(ERR_DBG, "%s: The skb is ",
3017 dev->name);
3018 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 3019 spin_unlock(&nic->rx_lock);
20346722 3020 return;
1da177e4 3021 }
da6971d8 3022 if (nic->rxd_mode == RXD_MODE_1) {
6d517a27 3023 rxdp1 = (struct RxD1*)rxdp;
da6971d8 3024 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 3025 rxdp1->Buffer0_ptr,
3026 dev->mtu +
3027 HEADER_ETHERNET_II_802_3_SIZE +
3028 HEADER_802_2_SIZE +
3029 HEADER_SNAP_SIZE,
3030 PCI_DMA_FROMDEVICE);
da6971d8 3031 } else if (nic->rxd_mode == RXD_MODE_3B) {
6d517a27 3032 rxdp3 = (struct RxD3*)rxdp;
75c30b13 3033 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
6d517a27
VP		 3034 rxdp3->Buffer0_ptr,
3035 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 3036 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 3037 rxdp3->Buffer2_ptr,
3038 dev->mtu + 4,
3039 PCI_DMA_FROMDEVICE);
da6971d8 3040 }
863c11a9 3041 prefetch(skb->data);
20346722 3042 rx_osm_handler(ring_data, rxdp);
3043 get_info.offset++;
da6971d8
AR		 3044 ring_data->rx_curr_get_info.offset = get_info.offset;
3045 rxdp = ring_data->rx_blocks[get_block].
3046 rxds[get_info.offset].virt_addr;
3047 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 3048 get_info.offset = 0;
da6971d8 3049 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3050 get_block++;
da6971d8
AR		 3051 if (get_block == ring_data->block_count)
3052 get_block = 0;
3053 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3054 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3055 }
1da177e4 3056
20346722 3057 nic->pkts_to_process -= 1;
db874e65 3058 if ((napi) && (!nic->pkts_to_process))
20346722 3059 break;
20346722 3060 pkt_cnt++;
1da177e4
LT		 3061 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3062 break;
3063 }
7d3d0439
RA		 3064 if (nic->lro) {
3065 /* Clear all LRO sessions before exiting */
3066 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 3067 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 3068 if (lro->in_use) {
3069 update_L3L4_header(nic, lro);
cdb5bf02 3070 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3071 clear_lro_session(lro);
3072 }
3073 }
3074 }
3075
7ba013ac 3076 spin_unlock(&nic->rx_lock);
1da177e4 3077}
20346722 3078
3079/**
1da177e4
LT		 3080 * tx_intr_handler - Transmit interrupt handler
3081 * @nic : device private variable
20346722 3082 * Description:
3083 * If an interrupt was raised to indicate DMA complete of the
3084 * Tx packet, this function is called. It identifies the last TxD
3085 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3086 * DMA'ed into the NICs internal memory.
3087 * Return Value:
3088 * NONE
3089 */
3090
1ee6dd77 3091static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3092{
1ee6dd77 3093 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3094 struct tx_curr_get_info get_info, put_info;
3a3d5756 3095 struct sk_buff *skb = NULL;
1ee6dd77 3096 struct TxD *txdlp;
3a3d5756 3097 int pkt_cnt = 0;
2fda096d 3098 unsigned long flags = 0;
f9046eb3 3099 u8 err_mask;
1da177e4 3100
2fda096d
SR		 3101 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3102 return;
3103
20346722 3104 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3105 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3106 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722 3107 list_virt_addr;
3108 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3109 (get_info.offset != put_info.offset) &&
3110 (txdlp->Host_Control)) {
3111 /* Check for TxD errors */
3112 if (txdlp->Control_1 & TXD_T_CODE) {
3113 unsigned long long err;
3114 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3115 if (err & 0x1) {
3116 nic->mac_control.stats_info->sw_stat.
3117 parity_err_cnt++;
3118 }
491976b2
SH		 3119
3120 /* update t_code statistics */
f9046eb3
OH		 3121 err_mask = err >> 48;
3122 switch(err_mask) {
491976b2
SH		 3123 case 2:
3124 nic->mac_control.stats_info->sw_stat.
3125 tx_buf_abort_cnt++;
3126 break;
3127
3128 case 3:
3129 nic->mac_control.stats_info->sw_stat.
3130 tx_desc_abort_cnt++;
3131 break;
3132
3133 case 7:
3134 nic->mac_control.stats_info->sw_stat.
3135 tx_parity_err_cnt++;
3136 break;
3137
3138 case 10:
3139 nic->mac_control.stats_info->sw_stat.
3140 tx_link_loss_cnt++;
3141 break;
3142
3143 case 15:
3144 nic->mac_control.stats_info->sw_stat.
3145 tx_list_proc_err_cnt++;
3146 break;
3147 }
20346722 3148 }
1da177e4 3149
fed5eccd 3150 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3151 if (skb == NULL) {
2fda096d 3152 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722 3153 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3154 __FUNCTION__);
3155 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3156 return;
3157 }
3a3d5756 3158 pkt_cnt++;
20346722 3159
20346722 3160 /* Updating the statistics block */
20346722 3161 nic->stats.tx_bytes += skb->len;
491976b2 3162 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722 3163 dev_kfree_skb_irq(skb);
3164
3165 get_info.offset++;
863c11a9
AR		 3166 if (get_info.offset == get_info.fifo_len + 1)
3167 get_info.offset = 0;
1ee6dd77 3168 txdlp = (struct TxD *) fifo_data->list_info
20346722 3169 [get_info.offset].list_virt_addr;
3170 fifo_data->tx_curr_get_info.offset =
3171 get_info.offset;
1da177e4
LT		 3172 }
3173
3a3d5756 3174 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3175
3176 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3177}
3178
bd1034f0
AR		 3179/**
3180 * s2io_mdio_write - Function to write in to MDIO registers
3181 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3182 * @addr : address value
3183 * @value : data value
3184 * @dev : pointer to net_device structure
3185 * Description:
3186 * This function is used to write values to the MDIO registers
3187 * NONE
3188 */
3189static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3190{
3191 u64 val64 = 0x0;
1ee6dd77
RB		 3192 struct s2io_nic *sp = dev->priv;
3193 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3194
3195 //address transaction
3196 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3197 | MDIO_MMD_DEV_ADDR(mmd_type)
3198 | MDIO_MMS_PRT_ADDR(0x0);
3199 writeq(val64, &bar0->mdio_control);
3200 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3201 writeq(val64, &bar0->mdio_control);
3202 udelay(100);
3203
3204 //Data transaction
3205 val64 = 0x0;
3206 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3207 | MDIO_MMD_DEV_ADDR(mmd_type)
3208 | MDIO_MMS_PRT_ADDR(0x0)
3209 | MDIO_MDIO_DATA(value)
3210 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3211 writeq(val64, &bar0->mdio_control);
3212 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3213 writeq(val64, &bar0->mdio_control);
3214 udelay(100);
3215
3216 val64 = 0x0;
3217 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3218 | MDIO_MMD_DEV_ADDR(mmd_type)
3219 | MDIO_MMS_PRT_ADDR(0x0)
3220 | MDIO_OP(MDIO_OP_READ_TRANS);
3221 writeq(val64, &bar0->mdio_control);
3222 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3223 writeq(val64, &bar0->mdio_control);
3224 udelay(100);
3225
3226}
3227
3228/**
3229 * s2io_mdio_read - Function to write in to MDIO registers
3230 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3231 * @addr : address value
3232 * @dev : pointer to net_device structure
3233 * Description:
3234 * This function is used to read values to the MDIO registers
3235 * NONE
3236 */
3237static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3238{
3239 u64 val64 = 0x0;
3240 u64 rval64 = 0x0;
1ee6dd77
RB		 3241 struct s2io_nic *sp = dev->priv;
3242 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3243
3244 /* address transaction */
3245 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3246 | MDIO_MMD_DEV_ADDR(mmd_type)
3247 | MDIO_MMS_PRT_ADDR(0x0);
3248 writeq(val64, &bar0->mdio_control);
3249 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3250 writeq(val64, &bar0->mdio_control);
3251 udelay(100);
3252
3253 /* Data transaction */
3254 val64 = 0x0;
3255 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3256 | MDIO_MMD_DEV_ADDR(mmd_type)
3257 | MDIO_MMS_PRT_ADDR(0x0)
3258 | MDIO_OP(MDIO_OP_READ_TRANS);
3259 writeq(val64, &bar0->mdio_control);
3260 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3261 writeq(val64, &bar0->mdio_control);
3262 udelay(100);
3263
3264 /* Read the value from regs */
3265 rval64 = readq(&bar0->mdio_control);
3266 rval64 = rval64 & 0xFFFF0000;
3267 rval64 = rval64 >> 16;
3268 return rval64;
3269}
3270/**
3271 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3272 * @counter : couter value to be updated
3273 * @flag : flag to indicate the status
3274 * @type : counter type
3275 * Description:
3276 * This function is to check the status of the xpak counters value
3277 * NONE
3278 */
3279
3280static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3281{
3282 u64 mask = 0x3;
3283 u64 val64;
3284 int i;
3285 for(i = 0; i <index; i++)
3286 mask = mask << 0x2;
3287
3288 if(flag > 0)
3289 {
3290 *counter = *counter + 1;
3291 val64 = *regs_stat & mask;
3292 val64 = val64 >> (index * 0x2);
3293 val64 = val64 + 1;
3294 if(val64 == 3)
3295 {
3296 switch(type)
3297 {
3298 case 1:
3299 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3300 "service. Excessive temperatures may "
3301 "result in premature transceiver "
3302 "failure \n");
3303 break;
3304 case 2:
3305 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3306 "service Excessive bias currents may "
3307 "indicate imminent laser diode "
3308 "failure \n");
3309 break;
3310 case 3:
3311 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3312 "service Excessive laser output "
3313 "power may saturate far-end "
3314 "receiver\n");
3315 break;
3316 default:
3317 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3318 "type \n");
3319 }
3320 val64 = 0x0;
3321 }
3322 val64 = val64 << (index * 0x2);
3323 *regs_stat = (*regs_stat & (~mask)) | (val64);
3324
3325 } else {
3326 *regs_stat = *regs_stat & (~mask);
3327 }
3328}
3329
3330/**
3331 * s2io_updt_xpak_counter - Function to update the xpak counters
3332 * @dev : pointer to net_device struct
3333 * Description:
3334 * This function is to upate the status of the xpak counters value
3335 * NONE
3336 */
3337static void s2io_updt_xpak_counter(struct net_device *dev)
3338{
3339 u16 flag = 0x0;
3340 u16 type = 0x0;
3341 u16 val16 = 0x0;
3342 u64 val64 = 0x0;
3343 u64 addr = 0x0;
3344
1ee6dd77
RB		 3345 struct s2io_nic *sp = dev->priv;
3346 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3347
3348 /* Check the communication with the MDIO slave */
3349 addr = 0x0000;
3350 val64 = 0x0;
3351 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3352 if((val64 == 0xFFFF) || (val64 == 0x0000))
3353 {
3354 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3355 "Returned %llx\n", (unsigned long long)val64);
3356 return;
3357 }
3358
3359 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3360 if(val64 != 0x2040)
3361 {
3362 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3363 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3364 (unsigned long long)val64);
3365 return;
3366 }
3367
3368 /* Loading the DOM register to MDIO register */
3369 addr = 0xA100;
3370 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3371 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3372
3373 /* Reading the Alarm flags */
3374 addr = 0xA070;
3375 val64 = 0x0;
3376 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3377
3378 flag = CHECKBIT(val64, 0x7);
3379 type = 1;
3380 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3381 &stat_info->xpak_stat.xpak_regs_stat,
3382 0x0, flag, type);
3383
3384 if(CHECKBIT(val64, 0x6))
3385 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3386
3387 flag = CHECKBIT(val64, 0x3);
3388 type = 2;
3389 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3390 &stat_info->xpak_stat.xpak_regs_stat,
3391 0x2, flag, type);
3392
3393 if(CHECKBIT(val64, 0x2))
3394 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3395
3396 flag = CHECKBIT(val64, 0x1);
3397 type = 3;
3398 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3399 &stat_info->xpak_stat.xpak_regs_stat,
3400 0x4, flag, type);
3401
3402 if(CHECKBIT(val64, 0x0))
3403 stat_info->xpak_stat.alarm_laser_output_power_low++;
3404
3405 /* Reading the Warning flags */
3406 addr = 0xA074;
3407 val64 = 0x0;
3408 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3409
3410 if(CHECKBIT(val64, 0x7))
3411 stat_info->xpak_stat.warn_transceiver_temp_high++;
3412
3413 if(CHECKBIT(val64, 0x6))
3414 stat_info->xpak_stat.warn_transceiver_temp_low++;
3415
3416 if(CHECKBIT(val64, 0x3))
3417 stat_info->xpak_stat.warn_laser_bias_current_high++;
3418
3419 if(CHECKBIT(val64, 0x2))
3420 stat_info->xpak_stat.warn_laser_bias_current_low++;
3421
3422 if(CHECKBIT(val64, 0x1))
3423 stat_info->xpak_stat.warn_laser_output_power_high++;
3424
3425 if(CHECKBIT(val64, 0x0))
3426 stat_info->xpak_stat.warn_laser_output_power_low++;
3427}
3428
20346722 3429/**
1da177e4 3430 * wait_for_cmd_complete - waits for a command to complete.
20346722 3431 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3432 * s2io_nic structure.
20346722 3433 * Description: Function that waits for a command to Write into RMAC
3434 * ADDR DATA registers to be completed and returns either success or
3435 * error depending on whether the command was complete or not.
1da177e4
LT		 3436 * Return value:
3437 * SUCCESS on success and FAILURE on failure.
3438 */
3439
9fc93a41
SS		 3440static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3441 int bit_state)
1da177e4 3442{
9fc93a41 3443 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3444 u64 val64;
3445
9fc93a41
SS		 3446 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3447 return FAILURE;
3448
3449 do {
c92ca04b 3450 val64 = readq(addr);
9fc93a41
SS		 3451 if (bit_state == S2IO_BIT_RESET) {
3452 if (!(val64 & busy_bit)) {
3453 ret = SUCCESS;
3454 break;
3455 }
3456 } else {
3457 if (!(val64 & busy_bit)) {
3458 ret = SUCCESS;
3459 break;
3460 }
1da177e4 3461 }
c92ca04b
AR		 3462
3463 if(in_interrupt())
9fc93a41 3464 mdelay(delay);
c92ca04b 3465 else
9fc93a41 3466 msleep(delay);
c92ca04b 3467
9fc93a41
SS		 3468 if (++cnt >= 10)
3469 delay = 50;
3470 } while (cnt < 20);
1da177e4
LT		 3471 return ret;
3472}
19a60522
SS		 3473/*
3474 * check_pci_device_id - Checks if the device id is supported
3475 * @id : device id
3476 * Description: Function to check if the pci device id is supported by driver.
3477 * Return value: Actual device id if supported else PCI_ANY_ID
3478 */
3479static u16 check_pci_device_id(u16 id)
3480{
3481 switch (id) {
3482 case PCI_DEVICE_ID_HERC_WIN:
3483 case PCI_DEVICE_ID_HERC_UNI:
3484 return XFRAME_II_DEVICE;
3485 case PCI_DEVICE_ID_S2IO_UNI:
3486 case PCI_DEVICE_ID_S2IO_WIN:
3487 return XFRAME_I_DEVICE;
3488 default:
3489 return PCI_ANY_ID;
3490 }
3491}
1da177e4 3492
20346722 3493/**
3494 * s2io_reset - Resets the card.
1da177e4
LT		 3495 * @sp : private member of the device structure.
3496 * Description: Function to Reset the card. This function then also
20346722 3497 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3498 * the card reset also resets the configuration space.
3499 * Return value:
3500 * void.
3501 */
3502
1ee6dd77 3503static void s2io_reset(struct s2io_nic * sp)
1da177e4 3504{
1ee6dd77 3505 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3506 u64 val64;
5e25b9dd 3507 u16 subid, pci_cmd;
19a60522
SS		 3508 int i;
3509 u16 val16;
491976b2
SH		 3510 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3511 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3512
19a60522
SS		 3513 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3514 __FUNCTION__, sp->dev->name);
1da177e4 3515
0b1f7ebe 3516 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3517 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3518
1da177e4
LT		 3519 val64 = SW_RESET_ALL;
3520 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3521 if (strstr(sp->product_name, "CX4")) {
3522 msleep(750);
3523 }
19a60522
SS		 3524 msleep(250);
3525 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3526
19a60522
SS		 3527 /* Restore the PCI state saved during initialization. */
3528 pci_restore_state(sp->pdev);
3529 pci_read_config_word(sp->pdev, 0x2, &val16);
3530 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3531 break;
3532 msleep(200);
3533 }
1da177e4 3534
19a60522
SS		 3535 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3536 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3537 }
3538
3539 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3540
3541 s2io_init_pci(sp);
1da177e4 3542
20346722 3543 /* Set swapper to enable I/O register access */
3544 s2io_set_swapper(sp);
3545
faa4f796
SH		 3546 /* restore mac_addr entries */
3547 do_s2io_restore_unicast_mc(sp);
3548
cc6e7c44
RA		 3549 /* Restore the MSIX table entries from local variables */
3550 restore_xmsi_data(sp);
3551
5e25b9dd 3552 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3553 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3554 /* Clear "detected parity error" bit */
303bcb4b 3555 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3556
303bcb4b 3557 /* Clearing PCIX Ecc status register */
3558 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3559
303bcb4b 3560 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3561 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3562 }
5e25b9dd 3563
20346722 3564 /* Reset device statistics maintained by OS */
3565 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3566
491976b2
SH		 3567 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3568 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3569 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3570 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3571 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3572 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3573 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3574 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3575 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3576 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3577 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3578 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3579 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3580 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3581 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3582 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3583 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3584 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3585 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3586
1da177e4
LT		 3587 /* SXE-002: Configure link and activity LED to turn it off */
3588 subid = sp->pdev->subsystem_device;
541ae68f 3589 if (((subid & 0xFF) >= 0x07) &&
3590 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3591 val64 = readq(&bar0->gpio_control);
3592 val64 |= 0x0000800000000000ULL;
3593 writeq(val64, &bar0->gpio_control);
3594 val64 = 0x0411040400000000ULL;
509a2671 3595 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3596 }
3597
541ae68f 3598 /*
3599 * Clear spurious ECC interrupts that would have occured on
3600 * XFRAME II cards after reset.
3601 */
3602 if (sp->device_type == XFRAME_II_DEVICE) {
3603 val64 = readq(&bar0->pcc_err_reg);
3604 writeq(val64, &bar0->pcc_err_reg);
3605 }
3606
1da177e4
LT		 3607 sp->device_enabled_once = FALSE;
3608}
3609
3610/**
20346722 3611 * s2io_set_swapper - to set the swapper controle on the card
3612 * @sp : private member of the device structure,
1da177e4 3613 * pointer to the s2io_nic structure.
20346722 3614 * Description: Function to set the swapper control on the card
1da177e4
LT		 3615 * correctly depending on the 'endianness' of the system.
3616 * Return value:
3617 * SUCCESS on success and FAILURE on failure.
3618 */
3619
1ee6dd77 3620static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3621{
3622 struct net_device *dev = sp->dev;
1ee6dd77 3623 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3624 u64 val64, valt, valr;
3625
20346722 3626 /*
1da177e4
LT		 3627 * Set proper endian settings and verify the same by reading
3628 * the PIF Feed-back register.
3629 */
3630
3631 val64 = readq(&bar0->pif_rd_swapper_fb);
3632 if (val64 != 0x0123456789ABCDEFULL) {
3633 int i = 0;
3634 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3635 0x8100008181000081ULL, /* FE=1, SE=0 */
3636 0x4200004242000042ULL, /* FE=0, SE=1 */
3637 0}; /* FE=0, SE=0 */
3638
3639 while(i<4) {
3640 writeq(value[i], &bar0->swapper_ctrl);
3641 val64 = readq(&bar0->pif_rd_swapper_fb);
3642 if (val64 == 0x0123456789ABCDEFULL)
3643 break;
3644 i++;
3645 }
3646 if (i == 4) {
3647 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3648 dev->name);
3649 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3650 (unsigned long long) val64);
3651 return FAILURE;
3652 }
3653 valr = value[i];
3654 } else {
3655 valr = readq(&bar0->swapper_ctrl);
3656 }
3657
3658 valt = 0x0123456789ABCDEFULL;
3659 writeq(valt, &bar0->xmsi_address);
3660 val64 = readq(&bar0->xmsi_address);
3661
3662 if(val64 != valt) {
3663 int i = 0;
3664 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3665 0x0081810000818100ULL, /* FE=1, SE=0 */
3666 0x0042420000424200ULL, /* FE=0, SE=1 */
3667 0}; /* FE=0, SE=0 */
3668
3669 while(i<4) {
3670 writeq((value[i] | valr), &bar0->swapper_ctrl);
3671 writeq(valt, &bar0->xmsi_address);
3672 val64 = readq(&bar0->xmsi_address);
3673 if(val64 == valt)
3674 break;
3675 i++;
3676 }
3677 if(i == 4) {
20346722 3678 unsigned long long x = val64;
1da177e4 3679 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3680 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3681 return FAILURE;
3682 }
3683 }
3684 val64 = readq(&bar0->swapper_ctrl);
3685 val64 &= 0xFFFF000000000000ULL;
3686
3687#ifdef __BIG_ENDIAN
20346722 3688 /*
3689 * The device by default set to a big endian format, so a
1da177e4
LT		 3690 * big endian driver need not set anything.
3691 */
3692 val64 |= (SWAPPER_CTRL_TXP_FE |
3693 SWAPPER_CTRL_TXP_SE |
3694 SWAPPER_CTRL_TXD_R_FE |
3695 SWAPPER_CTRL_TXD_W_FE |
3696 SWAPPER_CTRL_TXF_R_FE |
3697 SWAPPER_CTRL_RXD_R_FE |
3698 SWAPPER_CTRL_RXD_W_FE |
3699 SWAPPER_CTRL_RXF_W_FE |
3700 SWAPPER_CTRL_XMSI_FE |
1da177e4 3701 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3702 if (sp->config.intr_type == INTA)
cc6e7c44 3703 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3704 writeq(val64, &bar0->swapper_ctrl);
3705#else
20346722 3706 /*
1da177e4 3707 * Initially we enable all bits to make it accessible by the
20346722 3708 * driver, then we selectively enable only those bits that
1da177e4
LT		 3709 * we want to set.
3710 */
3711 val64 |= (SWAPPER_CTRL_TXP_FE |
3712 SWAPPER_CTRL_TXP_SE |
3713 SWAPPER_CTRL_TXD_R_FE |
3714 SWAPPER_CTRL_TXD_R_SE |
3715 SWAPPER_CTRL_TXD_W_FE |
3716 SWAPPER_CTRL_TXD_W_SE |
3717 SWAPPER_CTRL_TXF_R_FE |
3718 SWAPPER_CTRL_RXD_R_FE |
3719 SWAPPER_CTRL_RXD_R_SE |
3720 SWAPPER_CTRL_RXD_W_FE |
3721 SWAPPER_CTRL_RXD_W_SE |
3722 SWAPPER_CTRL_RXF_W_FE |
3723 SWAPPER_CTRL_XMSI_FE |
1da177e4 3724 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3725 if (sp->config.intr_type == INTA)
cc6e7c44 3726 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3727 writeq(val64, &bar0->swapper_ctrl);
3728#endif
3729 val64 = readq(&bar0->swapper_ctrl);
3730
20346722 3731 /*
3732 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3733 * feedback register.
3734 */
3735 val64 = readq(&bar0->pif_rd_swapper_fb);
3736 if (val64 != 0x0123456789ABCDEFULL) {
3737 /* Endian settings are incorrect, calls for another dekko. */
3738 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3739 dev->name);
3740 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3741 (unsigned long long) val64);
3742 return FAILURE;
3743 }
3744
3745 return SUCCESS;
3746}
3747
1ee6dd77 3748static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3749{
1ee6dd77 3750 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3751 u64 val64;
3752 int ret = 0, cnt = 0;
3753
3754 do {
3755 val64 = readq(&bar0->xmsi_access);
b7b5a128 3756 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3757 break;
3758 mdelay(1);
3759 cnt++;
3760 } while(cnt < 5);
3761 if (cnt == 5) {
3762 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3763 ret = 1;
3764 }
3765
3766 return ret;
3767}
3768
1ee6dd77 3769static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3770{
1ee6dd77 3771 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3772 u64 val64;
3773 int i;
3774
75c30b13 3775 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3776 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3777 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
b7b5a128 3778 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3779 writeq(val64, &bar0->xmsi_access);
3780 if (wait_for_msix_trans(nic, i)) {
3781 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3782 continue;
3783 }
3784 }
3785}
3786
1ee6dd77 3787static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3788{
1ee6dd77 3789 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3790 u64 val64, addr, data;
3791 int i;
3792
3793 /* Store and display */
75c30b13 3794 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
b7b5a128 3795 val64 = (s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3796 writeq(val64, &bar0->xmsi_access);
3797 if (wait_for_msix_trans(nic, i)) {
3798 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3799 continue;
3800 }
3801 addr = readq(&bar0->xmsi_address);
3802 data = readq(&bar0->xmsi_data);
3803 if (addr && data) {
3804 nic->msix_info[i].addr = addr;
3805 nic->msix_info[i].data = data;
3806 }
3807 }
3808}
3809
1ee6dd77 3810static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3811{
1ee6dd77 3812 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3813 u64 tx_mat, rx_mat;
3814 u16 msi_control; /* Temp variable */
3815 int ret, i, j, msix_indx = 1;
3816
bd684e43 3817 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
cc6e7c44 3818 GFP_KERNEL);
bd684e43 3819 if (!nic->entries) {
491976b2
SH		 3820 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3821 __FUNCTION__);
c53d4945 3822 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3823 return -ENOMEM;
3824 }
8a4bdbaa 3825 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3826 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3827
3828 nic->s2io_entries =
bd684e43 3829 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
cc6e7c44 3830 GFP_KERNEL);
bd684e43 3831 if (!nic->s2io_entries) {
8a4bdbaa 3832 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
491976b2 3833 __FUNCTION__);
c53d4945 3834 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3835 kfree(nic->entries);
8a4bdbaa 3836 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3837 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3838 return -ENOMEM;
3839 }
8a4bdbaa 3840 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3841 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3842
3843 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3844 nic->entries[i].entry = i;
3845 nic->s2io_entries[i].entry = i;
3846 nic->s2io_entries[i].arg = NULL;
3847 nic->s2io_entries[i].in_use = 0;
3848 }
3849
3850 tx_mat = readq(&bar0->tx_mat0_n[0]);
3851 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3852 tx_mat |= TX_MAT_SET(i, msix_indx);
3853 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3854 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3855 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3856 }
3857 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3858
8a4bdbaa
SS		 3859 rx_mat = readq(&bar0->rx_mat);
3860 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3861 rx_mat |= RX_MAT_SET(j, msix_indx);
3862 nic->s2io_entries[msix_indx].arg
3863 = &nic->mac_control.rings[j];
3864 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3865 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
cc6e7c44 3866 }
8a4bdbaa 3867 writeq(rx_mat, &bar0->rx_mat);
cc6e7c44 3868
c92ca04b 3869 nic->avail_msix_vectors = 0;
cc6e7c44 3870 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3871 /* We fail init if error or we get less vectors than min required */
3872 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3873 nic->avail_msix_vectors = ret;
3874 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3875 }
cc6e7c44
RA		 3876 if (ret) {
3877 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3878 kfree(nic->entries);
8a4bdbaa 3879 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3880 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3881 kfree(nic->s2io_entries);
8a4bdbaa 3882 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3883 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3884 nic->entries = NULL;
3885 nic->s2io_entries = NULL;
c92ca04b 3886 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3887 return -ENOMEM;
3888 }
c92ca04b
AR		 3889 if (!nic->avail_msix_vectors)
3890 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3891
3892 /*
3893 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3894 * in the herc NIC. (Temp change, needs to be removed later)
3895 */
3896 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3897 msi_control |= 0x1; /* Enable MSI */
3898 pci_write_config_word(nic->pdev, 0x42, msi_control);
3899
3900 return 0;
3901}
3902
8abc4d5b 3903/* Handle software interrupt used during MSI(X) test */
33390a70 3904static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3905{
3906 struct s2io_nic *sp = dev_id;
3907
3908 sp->msi_detected = 1;
3909 wake_up(&sp->msi_wait);
3910
3911 return IRQ_HANDLED;
3912}
3913
3914/* Test interrupt path by forcing a a software IRQ */
33390a70 3915static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3916{
3917 struct pci_dev *pdev = sp->pdev;
3918 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3919 int err;
3920 u64 val64, saved64;
3921
3922 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3923 sp->name, sp);
3924 if (err) {
3925 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3926 sp->dev->name, pci_name(pdev), pdev->irq);
3927 return err;
3928 }
3929
3930 init_waitqueue_head (&sp->msi_wait);
3931 sp->msi_detected = 0;
3932
3933 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3934 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3935 val64 |= SCHED_INT_CTRL_TIMER_EN;
3936 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3937 writeq(val64, &bar0->scheduled_int_ctrl);
3938
3939 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3940
3941 if (!sp->msi_detected) {
3942 /* MSI(X) test failed, go back to INTx mode */
2450022a 3943 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3944 "using MSI(X) during test\n", sp->dev->name,
3945 pci_name(pdev));
3946
3947 err = -EOPNOTSUPP;
3948 }
3949
3950 free_irq(sp->entries[1].vector, sp);
3951
3952 writeq(saved64, &bar0->scheduled_int_ctrl);
3953
3954 return err;
3955}
18b2b7bd
SH		 3956
3957static void remove_msix_isr(struct s2io_nic *sp)
3958{
3959 int i;
3960 u16 msi_control;
3961
3962 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3963 if (sp->s2io_entries[i].in_use ==
3964 MSIX_REGISTERED_SUCCESS) {
3965 int vector = sp->entries[i].vector;
3966 void *arg = sp->s2io_entries[i].arg;
3967 free_irq(vector, arg);
3968 }
3969 }
3970
3971 kfree(sp->entries);
3972 kfree(sp->s2io_entries);
3973 sp->entries = NULL;
3974 sp->s2io_entries = NULL;
3975
3976 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3977 msi_control &= 0xFFFE; /* Disable MSI */
3978 pci_write_config_word(sp->pdev, 0x42, msi_control);
3979
3980 pci_disable_msix(sp->pdev);
3981}
3982
3983static void remove_inta_isr(struct s2io_nic *sp)
3984{
3985 struct net_device *dev = sp->dev;
3986
3987 free_irq(sp->pdev->irq, dev);
3988}
3989
1da177e4
LT		 3990/* ********************************************************* *
3991 * Functions defined below concern the OS part of the driver *
3992 * ********************************************************* */
3993
20346722 3994/**
1da177e4
LT		 3995 * s2io_open - open entry point of the driver
3996 * @dev : pointer to the device structure.
3997 * Description:
3998 * This function is the open entry point of the driver. It mainly calls a
3999 * function to allocate Rx buffers and inserts them into the buffer
20346722 4000 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 4001 * Return value:
4002 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4003 * file on failure.
4004 */
4005
ac1f60db 4006static int s2io_open(struct net_device *dev)
1da177e4 4007{
1ee6dd77 4008 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4009 int err = 0;
4010
20346722 4011 /*
4012 * Make sure you have link off by default every time
1da177e4
LT		 4013 * Nic is initialized
4014 */
4015 netif_carrier_off(dev);
0b1f7ebe 4016 sp->last_link_state = 0;
1da177e4 4017
eaae7f72 4018 if (sp->config.intr_type == MSI_X) {
8abc4d5b
SS		 4019 int ret = s2io_enable_msi_x(sp);
4020
4021 if (!ret) {
8abc4d5b 4022 ret = s2io_test_msi(sp);
8abc4d5b 4023 /* rollback MSI-X, will re-enable during add_isr() */
18b2b7bd 4024 remove_msix_isr(sp);
8abc4d5b
SS		 4025 }
4026 if (ret) {
4027
4028 DBG_PRINT(ERR_DBG,
4029 "%s: MSI-X requested but failed to enable\n",
4030 dev->name);
eaae7f72 4031 sp->config.intr_type = INTA;
8abc4d5b
SS		 4032 }
4033 }
4034
c77dd43e 4035 /* NAPI doesn't work well with MSI(X) */
eaae7f72 4036 if (sp->config.intr_type != INTA) {
c77dd43e
SS		 4037 if(sp->config.napi)
4038 sp->config.napi = 0;
4039 }
4040
1da177e4 4041 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4042 err = s2io_card_up(sp);
4043 if (err) {
1da177e4
LT		 4044 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4045 dev->name);
e6a8fee2 4046 goto hw_init_failed;
1da177e4
LT		 4047 }
4048
2fd37688 4049 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4050 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4051 s2io_card_down(sp);
20346722 4052 err = -ENODEV;
e6a8fee2 4053 goto hw_init_failed;
1da177e4 4054 }
3a3d5756 4055 s2io_start_all_tx_queue(sp);
1da177e4 4056 return 0;
20346722 4057
20346722 4058hw_init_failed:
eaae7f72 4059 if (sp->config.intr_type == MSI_X) {
491976b2 4060 if (sp->entries) {
cc6e7c44 4061 kfree(sp->entries);
8a4bdbaa 4062 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 4063 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
4064 }
4065 if (sp->s2io_entries) {
cc6e7c44 4066 kfree(sp->s2io_entries);
8a4bdbaa 4067 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 4068 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
4069 }
cc6e7c44 4070 }
20346722 4071 return err;
1da177e4
LT		 4072}
4073
4074/**
4075 * s2io_close -close entry point of the driver
4076 * @dev : device pointer.
4077 * Description:
4078 * This is the stop entry point of the driver. It needs to undo exactly
4079 * whatever was done by the open entry point,thus it's usually referred to
4080 * as the close function.Among other things this function mainly stops the
4081 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4082 * Return value:
4083 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4084 * file on failure.
4085 */
4086
ac1f60db 4087static int s2io_close(struct net_device *dev)
1da177e4 4088{
1ee6dd77 4089 struct s2io_nic *sp = dev->priv;
faa4f796
SH		 4090 struct config_param *config = &sp->config;
4091 u64 tmp64;
4092 int offset;
cc6e7c44 4093
9f74ffde
SH		 4094 /* Return if the device is already closed *
4095 * Can happen when s2io_card_up failed in change_mtu *
4096 */
4097 if (!is_s2io_card_up(sp))
4098 return 0;
4099
3a3d5756 4100 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4101 /* delete all populated mac entries */
4102 for (offset = 1; offset < config->max_mc_addr; offset++) {
4103 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4104 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4105 do_s2io_delete_unicast_mc(sp, tmp64);
4106 }
4107
1da177e4 4108 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 4109 s2io_card_down(sp);
cc6e7c44 4110
1da177e4
LT		 4111 return 0;
4112}
4113
4114/**
4115 * s2io_xmit - Tx entry point of te driver
4116 * @skb : the socket buffer containing the Tx data.
4117 * @dev : device pointer.
4118 * Description :
4119 * This function is the Tx entry point of the driver. S2IO NIC supports
4120 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4121 * NOTE: when device cant queue the pkt,just the trans_start variable will
4122 * not be upadted.
4123 * Return value:
4124 * 0 on success & 1 on failure.
4125 */
4126
ac1f60db 4127static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4128{
1ee6dd77 4129 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4130 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4131 register u64 val64;
1ee6dd77
RB		 4132 struct TxD *txdp;
4133 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4134 unsigned long flags = 0;
be3a6b02 4135 u16 vlan_tag = 0;
2fda096d 4136 struct fifo_info *fifo = NULL;
1ee6dd77 4137 struct mac_info *mac_control;
1da177e4 4138 struct config_param *config;
6cfc482b 4139 int do_spin_lock = 1;
75c30b13 4140 int offload_type;
6cfc482b 4141 int enable_per_list_interrupt = 0;
491abf25 4142 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4143
4144 mac_control = &sp->mac_control;
4145 config = &sp->config;
4146
20346722 4147 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4148
4149 if (unlikely(skb->len <= 0)) {
4150 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4151 dev_kfree_skb_any(skb);
4152 return 0;
2fda096d 4153 }
491976b2 4154
92b84437 4155 if (!is_s2io_card_up(sp)) {
20346722 4156 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4157 dev->name);
20346722 4158 dev_kfree_skb(skb);
4159 return 0;
1da177e4
LT		 4160 }
4161
4162 queue = 0;
3a3d5756 4163 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4164 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4165 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4166 if (skb->protocol == htons(ETH_P_IP)) {
4167 struct iphdr *ip;
4168 struct tcphdr *th;
4169 ip = ip_hdr(skb);
4170
4171 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4172 th = (struct tcphdr *)(((unsigned char *)ip) +
4173 ip->ihl*4);
4174
4175 if (ip->protocol == IPPROTO_TCP) {
4176 queue_len = sp->total_tcp_fifos;
4177 queue = (ntohs(th->source) +
4178 ntohs(th->dest)) &
4179 sp->fifo_selector[queue_len - 1];
4180 if (queue >= queue_len)
4181 queue = queue_len - 1;
4182 } else if (ip->protocol == IPPROTO_UDP) {
4183 queue_len = sp->total_udp_fifos;
4184 queue = (ntohs(th->source) +
4185 ntohs(th->dest)) &
4186 sp->fifo_selector[queue_len - 1];
4187 if (queue >= queue_len)
4188 queue = queue_len - 1;
4189 queue += sp->udp_fifo_idx;
4190 if (skb->len > 1024)
4191 enable_per_list_interrupt = 1;
4192 do_spin_lock = 0;
4193 }
4194 }
4195 }
4196 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4197 /* get fifo number based on skb->priority value */
4198 queue = config->fifo_mapping
4199 [skb->priority & (MAX_TX_FIFOS - 1)];
4200 fifo = &mac_control->fifos[queue];
3a3d5756 4201
6cfc482b
SH		 4202 if (do_spin_lock)
4203 spin_lock_irqsave(&fifo->tx_lock, flags);
4204 else {
4205 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4206 return NETDEV_TX_LOCKED;
4207 }
be3a6b02 4208
3a3d5756
SH		 4209#ifdef CONFIG_NETDEVICES_MULTIQUEUE
4210 if (sp->config.multiq) {
4211 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4212 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4213 return NETDEV_TX_BUSY;
4214 }
4215 } else
4216#endif
4217 if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4218 if (netif_queue_stopped(dev)) {
4219 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4220 return NETDEV_TX_BUSY;
4221 }
4222 }
4223
2fda096d
SR		 4224 put_off = (u16) fifo->tx_curr_put_info.offset;
4225 get_off = (u16) fifo->tx_curr_get_info.offset;
4226 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4227
2fda096d 4228 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4229 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4230 if (txdp->Host_Control ||
4231 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4232 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4233 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4234 dev_kfree_skb(skb);
2fda096d 4235 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4236 return 0;
4237 }
0b1f7ebe 4238
75c30b13 4239 offload_type = s2io_offload_type(skb);
75c30b13 4240 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4241 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4242 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4243 }
84fa7933 4244 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4245 txdp->Control_2 |=
4246 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4247 TXD_TX_CKO_UDP_EN);
4248 }
fed5eccd
AR		 4249 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4250 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4251 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4252 if (enable_per_list_interrupt)
4253 if (put_off & (queue_len >> 5))
4254 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4255 if (vlan_tag) {
be3a6b02 4256 txdp->Control_2 |= TXD_VLAN_ENABLE;
4257 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4258 }
4259
fed5eccd 4260 frg_len = skb->len - skb->data_len;
75c30b13 4261 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4262 int ufo_size;
4263
75c30b13 4264 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4265 ufo_size &= ~7;
4266 txdp->Control_1 |= TXD_UFO_EN;
4267 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4268 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4269#ifdef __BIG_ENDIAN
3459feb8 4270 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4271 fifo->ufo_in_band_v[put_off] =
3459feb8 4272 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4273#else
2fda096d 4274 fifo->ufo_in_band_v[put_off] =
3459feb8 4275 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4276#endif
2fda096d 4277 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4278 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4279 fifo->ufo_in_band_v,
fed5eccd 4280 sizeof(u64), PCI_DMA_TODEVICE);
491abf25
VP		 4281 if((txdp->Buffer_Pointer == 0) ||
4282 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4283 goto pci_map_failed;
fed5eccd 4284 txdp++;
fed5eccd 4285 }
1da177e4 4286
fed5eccd
AR		 4287 txdp->Buffer_Pointer = pci_map_single
4288 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
491abf25
VP		 4289 if((txdp->Buffer_Pointer == 0) ||
4290 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4291 goto pci_map_failed;
4292
fed5eccd
AR		 4293 txdp->Host_Control = (unsigned long) skb;
4294 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4295 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4296 txdp->Control_1 |= TXD_UFO_EN;
4297
4298 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4299 /* For fragmented SKB. */
4300 for (i = 0; i < frg_cnt; i++) {
4301 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4302 /* A '0' length fragment will be ignored */
4303 if (!frag->size)
4304 continue;
1da177e4
LT		 4305 txdp++;
4306 txdp->Buffer_Pointer = (u64) pci_map_page
4307 (sp->pdev, frag->page, frag->page_offset,
4308 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4309 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4310 if (offload_type == SKB_GSO_UDP)
fed5eccd 4311 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4312 }
4313 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4314
75c30b13 4315 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4316 frg_cnt++; /* as Txd0 was used for inband header */
4317
1da177e4 4318 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4319 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4320 writeq(val64, &tx_fifo->TxDL_Pointer);
4321
4322 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4323 TX_FIFO_LAST_LIST);
75c30b13 4324 if (offload_type)
fed5eccd 4325 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4326
1da177e4
LT		 4327 writeq(val64, &tx_fifo->List_Control);
4328
303bcb4b 4329 mmiowb();
4330
1da177e4 4331 put_off++;
2fda096d 4332 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4333 put_off = 0;
2fda096d 4334 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4335
4336 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4337 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4338 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4339 DBG_PRINT(TX_DBG,
4340 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4341 put_off, get_off);
3a3d5756 4342 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4343 }
491976b2 4344 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4 4345 dev->trans_start = jiffies;
2fda096d 4346 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4347
f6f4bfa3
SH		 4348 if (sp->config.intr_type == MSI_X)
4349 tx_intr_handler(fifo);
4350
491abf25
VP		 4351 return 0;
4352pci_map_failed:
4353 stats->pci_map_fail_cnt++;
3a3d5756 4354 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4355 stats->mem_freed += skb->truesize;
4356 dev_kfree_skb(skb);
2fda096d 4357 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4358 return 0;
4359}
4360
25fff88e 4361static void
4362s2io_alarm_handle(unsigned long data)
4363{
1ee6dd77 4364 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4365 struct net_device *dev = sp->dev;
25fff88e 4366
8116f3cf 4367 s2io_handle_errors(dev);
25fff88e 4368 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4369}
4370
1ee6dd77 4371static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4372{
4373 int rxb_size, level;
4374
4375 if (!sp->lro) {
4376 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4377 level = rx_buffer_level(sp, rxb_size, rng_n);
4378
4379 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4380 int ret;
4381 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4382 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4383 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
0c61ed5f 4384 DBG_PRINT(INFO_DBG, "Out of memory in %s",
75c30b13
AR		 4385 __FUNCTION__);
4386 clear_bit(0, (&sp->tasklet_status));
4387 return -1;
4388 }
4389 clear_bit(0, (&sp->tasklet_status));
4390 } else if (level == LOW)
4391 tasklet_schedule(&sp->task);
4392
4393 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
0c61ed5f
RV		 4394 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4395 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4396 }
4397 return 0;
4398}
4399
7d12e780 4400static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4401{
1ee6dd77
RB		 4402 struct ring_info *ring = (struct ring_info *)dev_id;
4403 struct s2io_nic *sp = ring->nic;
cc6e7c44 4404
596c5c97 4405 if (!is_s2io_card_up(sp))
92b84437 4406 return IRQ_HANDLED;
92b84437 4407
75c30b13
AR		 4408 rx_intr_handler(ring);
4409 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4410
cc6e7c44
RA		 4411 return IRQ_HANDLED;
4412}
4413
7d12e780 4414static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4415{
1ee6dd77
RB		 4416 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4417 struct s2io_nic *sp = fifo->nic;
cc6e7c44 4418
596c5c97 4419 if (!is_s2io_card_up(sp))
92b84437 4420 return IRQ_HANDLED;
92b84437 4421
cc6e7c44 4422 tx_intr_handler(fifo);
cc6e7c44
RA		 4423 return IRQ_HANDLED;
4424}
1ee6dd77 4425static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4426{
1ee6dd77 4427 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4428 u64 val64;
4429
4430 val64 = readq(&bar0->pic_int_status);
4431 if (val64 & PIC_INT_GPIO) {
4432 val64 = readq(&bar0->gpio_int_reg);
4433 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4434 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4435 /*
4436 * This is unstable state so clear both up/down
4437 * interrupt and adapter to re-evaluate the link state.
4438 */
a371a07d 4439 val64 |= GPIO_INT_REG_LINK_DOWN;
4440 val64 |= GPIO_INT_REG_LINK_UP;
4441 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4442 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4443 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4444 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4445 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4446 }
c92ca04b
AR		 4447 else if (val64 & GPIO_INT_REG_LINK_UP) {
4448 val64 = readq(&bar0->adapter_status);
c92ca04b 4449 /* Enable Adapter */
19a60522
SS		 4450 val64 = readq(&bar0->adapter_control);
4451 val64 |= ADAPTER_CNTL_EN;
4452 writeq(val64, &bar0->adapter_control);
4453 val64 |= ADAPTER_LED_ON;
4454 writeq(val64, &bar0->adapter_control);
4455 if (!sp->device_enabled_once)
4456 sp->device_enabled_once = 1;
c92ca04b 4457
19a60522
SS		 4458 s2io_link(sp, LINK_UP);
4459 /*
4460 * unmask link down interrupt and mask link-up
4461 * intr
4462 */
4463 val64 = readq(&bar0->gpio_int_mask);
4464 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4465 val64 |= GPIO_INT_MASK_LINK_UP;
4466 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4467
c92ca04b
AR		 4468 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4469 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4470 s2io_link(sp, LINK_DOWN);
4471 /* Link is down so unmaks link up interrupt */
4472 val64 = readq(&bar0->gpio_int_mask);
4473 val64 &= ~GPIO_INT_MASK_LINK_UP;
4474 val64 |= GPIO_INT_MASK_LINK_DOWN;
4475 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4476
4477 /* turn off LED */
4478 val64 = readq(&bar0->adapter_control);
4479 val64 = val64 &(~ADAPTER_LED_ON);
4480 writeq(val64, &bar0->adapter_control);
a371a07d 4481 }
4482 }
c92ca04b 4483 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4484}
4485
8116f3cf
SS		 4486/**
4487 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4488 * @value: alarm bits
4489 * @addr: address value
4490 * @cnt: counter variable
4491 * Description: Check for alarm and increment the counter
4492 * Return Value:
4493 * 1 - if alarm bit set
4494 * 0 - if alarm bit is not set
4495 */
43b7c451 4496static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4497 unsigned long long *cnt)
4498{
4499 u64 val64;
4500 val64 = readq(addr);
4501 if ( val64 & value ) {
4502 writeq(val64, addr);
4503 (*cnt)++;
4504 return 1;
4505 }
4506 return 0;
4507
4508}
4509
4510/**
4511 * s2io_handle_errors - Xframe error indication handler
4512 * @nic: device private variable
4513 * Description: Handle alarms such as loss of link, single or
4514 * double ECC errors, critical and serious errors.
4515 * Return Value:
4516 * NONE
4517 */
4518static void s2io_handle_errors(void * dev_id)
4519{
4520 struct net_device *dev = (struct net_device *) dev_id;
4521 struct s2io_nic *sp = dev->priv;
4522 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4523 u64 temp64 = 0,val64=0;
4524 int i = 0;
4525
4526 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4527 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4528
92b84437 4529 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4530 return;
4531
4532 if (pci_channel_offline(sp->pdev))
4533 return;
4534
4535 memset(&sw_stat->ring_full_cnt, 0,
4536 sizeof(sw_stat->ring_full_cnt));
4537
4538 /* Handling the XPAK counters update */
4539 if(stats->xpak_timer_count < 72000) {
4540 /* waiting for an hour */
4541 stats->xpak_timer_count++;
4542 } else {
4543 s2io_updt_xpak_counter(dev);
4544 /* reset the count to zero */
4545 stats->xpak_timer_count = 0;
4546 }
4547
4548 /* Handling link status change error Intr */
4549 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4550 val64 = readq(&bar0->mac_rmac_err_reg);
4551 writeq(val64, &bar0->mac_rmac_err_reg);
4552 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4553 schedule_work(&sp->set_link_task);
4554 }
4555
4556 /* In case of a serious error, the device will be Reset. */
4557 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4558 &sw_stat->serious_err_cnt))
4559 goto reset;
4560
4561 /* Check for data parity error */
4562 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4563 &sw_stat->parity_err_cnt))
4564 goto reset;
4565
4566 /* Check for ring full counter */
4567 if (sp->device_type == XFRAME_II_DEVICE) {
4568 val64 = readq(&bar0->ring_bump_counter1);
4569 for (i=0; i<4; i++) {
4570 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4571 temp64 >>= 64 - ((i+1)*16);
4572 sw_stat->ring_full_cnt[i] += temp64;
4573 }
4574
4575 val64 = readq(&bar0->ring_bump_counter2);
4576 for (i=0; i<4; i++) {
4577 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4578 temp64 >>= 64 - ((i+1)*16);
4579 sw_stat->ring_full_cnt[i+4] += temp64;
4580 }
4581 }
4582
4583 val64 = readq(&bar0->txdma_int_status);
4584 /*check for pfc_err*/
4585 if (val64 & TXDMA_PFC_INT) {
4586 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4587 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4588 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4589 &sw_stat->pfc_err_cnt))
4590 goto reset;
4591 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4592 &sw_stat->pfc_err_cnt);
4593 }
4594
4595 /*check for tda_err*/
4596 if (val64 & TXDMA_TDA_INT) {
4597 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4598 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4599 &sw_stat->tda_err_cnt))
4600 goto reset;
4601 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4602 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4603 }
4604 /*check for pcc_err*/
4605 if (val64 & TXDMA_PCC_INT) {
4606 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4607 | PCC_N_SERR | PCC_6_COF_OV_ERR
4608 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4609 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4610 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4611 &sw_stat->pcc_err_cnt))
4612 goto reset;
4613 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4614 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4615 }
4616
4617 /*check for tti_err*/
4618 if (val64 & TXDMA_TTI_INT) {
4619 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4620 &sw_stat->tti_err_cnt))
4621 goto reset;
4622 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4623 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4624 }
4625
4626 /*check for lso_err*/
4627 if (val64 & TXDMA_LSO_INT) {
4628 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4629 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4630 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4631 goto reset;
4632 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4633 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4634 }
4635
4636 /*check for tpa_err*/
4637 if (val64 & TXDMA_TPA_INT) {
4638 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4639 &sw_stat->tpa_err_cnt))
4640 goto reset;
4641 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4642 &sw_stat->tpa_err_cnt);
4643 }
4644
4645 /*check for sm_err*/
4646 if (val64 & TXDMA_SM_INT) {
4647 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4648 &sw_stat->sm_err_cnt))
4649 goto reset;
4650 }
4651
4652 val64 = readq(&bar0->mac_int_status);
4653 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4654 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4655 &bar0->mac_tmac_err_reg,
4656 &sw_stat->mac_tmac_err_cnt))
4657 goto reset;
4658 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4659 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4660 &bar0->mac_tmac_err_reg,
4661 &sw_stat->mac_tmac_err_cnt);
4662 }
4663
4664 val64 = readq(&bar0->xgxs_int_status);
4665 if (val64 & XGXS_INT_STATUS_TXGXS) {
4666 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4667 &bar0->xgxs_txgxs_err_reg,
4668 &sw_stat->xgxs_txgxs_err_cnt))
4669 goto reset;
4670 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4671 &bar0->xgxs_txgxs_err_reg,
4672 &sw_stat->xgxs_txgxs_err_cnt);
4673 }
4674
4675 val64 = readq(&bar0->rxdma_int_status);
4676 if (val64 & RXDMA_INT_RC_INT_M) {
4677 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4678 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4679 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4680 goto reset;
4681 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4682 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4683 &sw_stat->rc_err_cnt);
4684 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4685 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4686 &sw_stat->prc_pcix_err_cnt))
4687 goto reset;
4688 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4689 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4690 &sw_stat->prc_pcix_err_cnt);
4691 }
4692
4693 if (val64 & RXDMA_INT_RPA_INT_M) {
4694 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4695 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4696 goto reset;
4697 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4698 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4699 }
4700
4701 if (val64 & RXDMA_INT_RDA_INT_M) {
4702 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4703 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4704 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4705 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4706 goto reset;
4707 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4708 | RDA_MISC_ERR | RDA_PCIX_ERR,
4709 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4710 }
4711
4712 if (val64 & RXDMA_INT_RTI_INT_M) {
4713 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4714 &sw_stat->rti_err_cnt))
4715 goto reset;
4716 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4717 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4718 }
4719
4720 val64 = readq(&bar0->mac_int_status);
4721 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4722 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4723 &bar0->mac_rmac_err_reg,
4724 &sw_stat->mac_rmac_err_cnt))
4725 goto reset;
4726 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4727 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4728 &sw_stat->mac_rmac_err_cnt);
4729 }
4730
4731 val64 = readq(&bar0->xgxs_int_status);
4732 if (val64 & XGXS_INT_STATUS_RXGXS) {
4733 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4734 &bar0->xgxs_rxgxs_err_reg,
4735 &sw_stat->xgxs_rxgxs_err_cnt))
4736 goto reset;
4737 }
4738
4739 val64 = readq(&bar0->mc_int_status);
4740 if(val64 & MC_INT_STATUS_MC_INT) {
4741 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4742 &sw_stat->mc_err_cnt))
4743 goto reset;
4744
4745 /* Handling Ecc errors */
4746 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4747 writeq(val64, &bar0->mc_err_reg);
4748 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4749 sw_stat->double_ecc_errs++;
4750 if (sp->device_type != XFRAME_II_DEVICE) {
4751 /*
4752 * Reset XframeI only if critical error
4753 */
4754 if (val64 &
4755 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4756 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4757 goto reset;
4758 }
4759 } else
4760 sw_stat->single_ecc_errs++;
4761 }
4762 }
4763 return;
4764
4765reset:
3a3d5756 4766 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4767 schedule_work(&sp->rst_timer_task);
4768 sw_stat->soft_reset_cnt++;
4769 return;
4770}
4771
1da177e4
LT		 4772/**
4773 * s2io_isr - ISR handler of the device .
4774 * @irq: the irq of the device.
4775 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4776 * Description: This function is the ISR handler of the device. It
4777 * identifies the reason for the interrupt and calls the relevant
4778 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4779 * recv buffers, if their numbers are below the panic value which is
4780 * presently set to 25% of the original number of rcv buffers allocated.
4781 * Return value:
20346722 4782 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4783 * IRQ_NONE: will be returned if interrupt is not from our device
4784 */
7d12e780 4785static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4786{
4787 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4788 struct s2io_nic *sp = dev->priv;
4789 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4790 int i;
19a60522 4791 u64 reason = 0;
1ee6dd77 4792 struct mac_info *mac_control;
1da177e4
LT		 4793 struct config_param *config;
4794
d796fdb7
LV		 4795 /* Pretend we handled any irq's from a disconnected card */
4796 if (pci_channel_offline(sp->pdev))
4797 return IRQ_NONE;
4798
596c5c97 4799 if (!is_s2io_card_up(sp))
92b84437 4800 return IRQ_NONE;
92b84437 4801
1da177e4
LT		 4802 mac_control = &sp->mac_control;
4803 config = &sp->config;
4804
20346722 4805 /*
1da177e4
LT		 4806 * Identify the cause for interrupt and call the appropriate
4807 * interrupt handler. Causes for the interrupt could be;
4808 * 1. Rx of packet.
4809 * 2. Tx complete.
4810 * 3. Link down.
1da177e4
LT		 4811 */
4812 reason = readq(&bar0->general_int_status);
4813
596c5c97
SS		 4814 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4815 /* Nothing much can be done. Get out */
4816 return IRQ_HANDLED;
1da177e4 4817 }
5d3213cc 4818
596c5c97
SS		 4819 if (reason & (GEN_INTR_RXTRAFFIC |
4820 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4821 {
4822 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4823
4824 if (config->napi) {
4825 if (reason & GEN_INTR_RXTRAFFIC) {
4826 if (likely(netif_rx_schedule_prep(dev,
4827 &sp->napi))) {
4828 __netif_rx_schedule(dev, &sp->napi);
4829 writeq(S2IO_MINUS_ONE,
4830 &bar0->rx_traffic_mask);
4831 } else
4832 writeq(S2IO_MINUS_ONE,
4833 &bar0->rx_traffic_int);
db874e65 4834 }
596c5c97
SS		 4835 } else {
4836 /*
4837 * rx_traffic_int reg is an R1 register, writing all 1's
4838 * will ensure that the actual interrupt causing bit
4839 * get's cleared and hence a read can be avoided.
4840 */
4841 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4842 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4843
4844 for (i = 0; i < config->rx_ring_num; i++)
4845 rx_intr_handler(&mac_control->rings[i]);
db874e65 4846 }
596c5c97 4847
db874e65 4848 /*
596c5c97 4849 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4850 * will ensure that the actual interrupt causing bit get's
4851 * cleared and hence a read can be avoided.
4852 */
596c5c97
SS		 4853 if (reason & GEN_INTR_TXTRAFFIC)
4854 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4855
596c5c97
SS		 4856 for (i = 0; i < config->tx_fifo_num; i++)
4857 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4858
596c5c97
SS		 4859 if (reason & GEN_INTR_TXPIC)
4860 s2io_txpic_intr_handle(sp);
fe113638 4861
596c5c97
SS		 4862 /*
4863 * Reallocate the buffers from the interrupt handler itself.
4864 */
4865 if (!config->napi) {
4866 for (i = 0; i < config->rx_ring_num; i++)
4867 s2io_chk_rx_buffers(sp, i);
4868 }
4869 writeq(sp->general_int_mask, &bar0->general_int_mask);
4870 readl(&bar0->general_int_status);
20346722 4871
596c5c97 4872 return IRQ_HANDLED;
db874e65 4873
596c5c97
SS		 4874 }
4875 else if (!reason) {
4876 /* The interrupt was not raised by us */
4877 return IRQ_NONE;
4878 }
db874e65 4879
1da177e4
LT		 4880 return IRQ_HANDLED;
4881}
4882
7ba013ac 4883/**
4884 * s2io_updt_stats -
4885 */
1ee6dd77 4886static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4887{
1ee6dd77 4888 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4889 u64 val64;
4890 int cnt = 0;
4891
92b84437 4892 if (is_s2io_card_up(sp)) {
7ba013ac 4893 /* Apprx 30us on a 133 MHz bus */
4894 val64 = SET_UPDT_CLICKS(10) |
4895 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4896 writeq(val64, &bar0->stat_cfg);
4897 do {
4898 udelay(100);
4899 val64 = readq(&bar0->stat_cfg);
b7b5a128 4900 if (!(val64 & s2BIT(0)))
7ba013ac 4901 break;
4902 cnt++;
4903 if (cnt == 5)
4904 break; /* Updt failed */
4905 } while(1);
8a4bdbaa 4906 }
7ba013ac 4907}
4908
1da177e4 4909/**
20346722 4910 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4911 * @dev : pointer to the device structure.
4912 * Description:
20346722 4913 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4914 * structure and returns a pointer to the same.
4915 * Return value:
4916 * pointer to the updated net_device_stats structure.
4917 */
4918
ac1f60db 4919static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4920{
1ee6dd77
RB		 4921 struct s2io_nic *sp = dev->priv;
4922 struct mac_info *mac_control;
1da177e4
LT		 4923 struct config_param *config;
4924
20346722 4925
1da177e4
LT		 4926 mac_control = &sp->mac_control;
4927 config = &sp->config;
4928
7ba013ac 4929 /* Configure Stats for immediate updt */
4930 s2io_updt_stats(sp);
4931
4932 sp->stats.tx_packets =
4933 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722 4934 sp->stats.tx_errors =
4935 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4936 sp->stats.rx_errors =
ee705dba 4937 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722 4938 sp->stats.multicast =
4939 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4940 sp->stats.rx_length_errors =
ee705dba 4941 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4942
4943 return (&sp->stats);
4944}
4945
4946/**
4947 * s2io_set_multicast - entry point for multicast address enable/disable.
4948 * @dev : pointer to the device structure
4949 * Description:
20346722 4950 * This function is a driver entry point which gets called by the kernel
4951 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4952 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4953 * determine, if multicast address must be enabled or if promiscuous mode
4954 * is to be disabled etc.
4955 * Return value:
4956 * void.
4957 */
4958
4959static void s2io_set_multicast(struct net_device *dev)
4960{
4961 int i, j, prev_cnt;
4962 struct dev_mc_list *mclist;
1ee6dd77
RB		 4963 struct s2io_nic *sp = dev->priv;
4964 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4965 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4966 0xfeffffffffffULL;
faa4f796 4967 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4968 void __iomem *add;
faa4f796 4969 struct config_param *config = &sp->config;
1da177e4
LT		 4970
4971 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4972 /* Enable all Multicast addresses */
4973 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4974 &bar0->rmac_addr_data0_mem);
4975 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4976 &bar0->rmac_addr_data1_mem);
4977 val64 = RMAC_ADDR_CMD_MEM_WE |
4978 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4979 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4980 writeq(val64, &bar0->rmac_addr_cmd_mem);
4981 /* Wait till command completes */
c92ca04b 4982 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4983 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4984 S2IO_BIT_RESET);
1da177e4
LT		 4985
4986 sp->m_cast_flg = 1;
faa4f796 4987 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4988 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4989 /* Disable all Multicast addresses */
4990 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4991 &bar0->rmac_addr_data0_mem);
5e25b9dd 4992 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4993 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4994 val64 = RMAC_ADDR_CMD_MEM_WE |
4995 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4996 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4997 writeq(val64, &bar0->rmac_addr_cmd_mem);
4998 /* Wait till command completes */
c92ca04b 4999 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5000 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5001 S2IO_BIT_RESET);
1da177e4
LT		 5002
5003 sp->m_cast_flg = 0;
5004 sp->all_multi_pos = 0;
5005 }
5006
5007 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5008 /* Put the NIC into promiscuous mode */
5009 add = &bar0->mac_cfg;
5010 val64 = readq(&bar0->mac_cfg);
5011 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5012
5013 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5014 writel((u32) val64, add);
5015 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5016 writel((u32) (val64 >> 32), (add + 4));
5017
926930b2
SS		 5018 if (vlan_tag_strip != 1) {
5019 val64 = readq(&bar0->rx_pa_cfg);
5020 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5021 writeq(val64, &bar0->rx_pa_cfg);
5022 vlan_strip_flag = 0;
5023 }
5024
1da177e4
LT		 5025 val64 = readq(&bar0->mac_cfg);
5026 sp->promisc_flg = 1;
776bd20f 5027 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5028 dev->name);
5029 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5030 /* Remove the NIC from promiscuous mode */
5031 add = &bar0->mac_cfg;
5032 val64 = readq(&bar0->mac_cfg);
5033 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5034
5035 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5036 writel((u32) val64, add);
5037 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5038 writel((u32) (val64 >> 32), (add + 4));
5039
926930b2
SS		 5040 if (vlan_tag_strip != 0) {
5041 val64 = readq(&bar0->rx_pa_cfg);
5042 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5043 writeq(val64, &bar0->rx_pa_cfg);
5044 vlan_strip_flag = 1;
5045 }
5046
1da177e4
LT		 5047 val64 = readq(&bar0->mac_cfg);
5048 sp->promisc_flg = 0;
776bd20f 5049 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5050 dev->name);
5051 }
5052
5053 /* Update individual M_CAST address list */
5054 if ((!sp->m_cast_flg) && dev->mc_count) {
5055 if (dev->mc_count >
faa4f796 5056 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5057 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5058 dev->name);
5059 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5060 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5061 return;
5062 }
5063
5064 prev_cnt = sp->mc_addr_count;
5065 sp->mc_addr_count = dev->mc_count;
5066
5067 /* Clear out the previous list of Mc in the H/W. */
5068 for (i = 0; i < prev_cnt; i++) {
5069 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5070 &bar0->rmac_addr_data0_mem);
5071 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5072 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5073 val64 = RMAC_ADDR_CMD_MEM_WE |
5074 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5075 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5076 (config->mc_start_offset + i);
1da177e4
LT		 5077 writeq(val64, &bar0->rmac_addr_cmd_mem);
5078
5079 /* Wait for command completes */
c92ca04b 5080 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5081 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5082 S2IO_BIT_RESET)) {
1da177e4
LT		 5083 DBG_PRINT(ERR_DBG, "%s: Adding ",
5084 dev->name);
5085 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5086 return;
5087 }
5088 }
5089
5090 /* Create the new Rx filter list and update the same in H/W. */
5091 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5092 i++, mclist = mclist->next) {
5093 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5094 ETH_ALEN);
a7a80d5a 5095 mac_addr = 0;
1da177e4
LT		 5096 for (j = 0; j < ETH_ALEN; j++) {
5097 mac_addr |= mclist->dmi_addr[j];
5098 mac_addr <<= 8;
5099 }
5100 mac_addr >>= 8;
5101 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5102 &bar0->rmac_addr_data0_mem);
5103 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5104 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5105 val64 = RMAC_ADDR_CMD_MEM_WE |
5106 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5107 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5108 (i + config->mc_start_offset);
1da177e4
LT		 5109 writeq(val64, &bar0->rmac_addr_cmd_mem);
5110
5111 /* Wait for command completes */
c92ca04b 5112 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5113 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5114 S2IO_BIT_RESET)) {
1da177e4
LT		 5115 DBG_PRINT(ERR_DBG, "%s: Adding ",
5116 dev->name);
5117 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5118 return;
5119 }
5120 }
5121 }
5122}
5123
faa4f796
SH		 5124/* read from CAM unicast & multicast addresses and store it in
5125 * def_mac_addr structure
5126 */
5127void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5128{
5129 int offset;
5130 u64 mac_addr = 0x0;
5131 struct config_param *config = &sp->config;
5132
5133 /* store unicast & multicast mac addresses */
5134 for (offset = 0; offset < config->max_mc_addr; offset++) {
5135 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5136 /* if read fails disable the entry */
5137 if (mac_addr == FAILURE)
5138 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5139 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5140 }
5141}
5142
5143/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5144static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5145{
5146 int offset;
5147 struct config_param *config = &sp->config;
5148 /* restore unicast mac address */
5149 for (offset = 0; offset < config->max_mac_addr; offset++)
5150 do_s2io_prog_unicast(sp->dev,
5151 sp->def_mac_addr[offset].mac_addr);
5152
5153 /* restore multicast mac address */
5154 for (offset = config->mc_start_offset;
5155 offset < config->max_mc_addr; offset++)
5156 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5157}
5158
5159/* add a multicast MAC address to CAM */
5160static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5161{
5162 int i;
5163 u64 mac_addr = 0;
5164 struct config_param *config = &sp->config;
5165
5166 for (i = 0; i < ETH_ALEN; i++) {
5167 mac_addr <<= 8;
5168 mac_addr |= addr[i];
5169 }
5170 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5171 return SUCCESS;
5172
5173 /* check if the multicast mac already preset in CAM */
5174 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5175 u64 tmp64;
5176 tmp64 = do_s2io_read_unicast_mc(sp, i);
5177 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5178 break;
5179
5180 if (tmp64 == mac_addr)
5181 return SUCCESS;
5182 }
5183 if (i == config->max_mc_addr) {
5184 DBG_PRINT(ERR_DBG,
5185 "CAM full no space left for multicast MAC\n");
5186 return FAILURE;
5187 }
5188 /* Update the internal structure with this new mac address */
5189 do_s2io_copy_mac_addr(sp, i, mac_addr);
5190
5191 return (do_s2io_add_mac(sp, mac_addr, i));
5192}
5193
5194/* add MAC address to CAM */
5195static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5196{
5197 u64 val64;
5198 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5199
5200 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5201 &bar0->rmac_addr_data0_mem);
5202
5203 val64 =
5204 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5205 RMAC_ADDR_CMD_MEM_OFFSET(off);
5206 writeq(val64, &bar0->rmac_addr_cmd_mem);
5207
5208 /* Wait till command completes */
5209 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5210 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5211 S2IO_BIT_RESET)) {
faa4f796 5212 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5213 return FAILURE;
5214 }
5215 return SUCCESS;
5216}
faa4f796
SH		 5217/* deletes a specified unicast/multicast mac entry from CAM */
5218static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5219{
5220 int offset;
5221 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5222 struct config_param *config = &sp->config;
5223
5224 for (offset = 1;
5225 offset < config->max_mc_addr; offset++) {
5226 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5227 if (tmp64 == addr) {
5228 /* disable the entry by writing 0xffffffffffffULL */
5229 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5230 return FAILURE;
5231 /* store the new mac list from CAM */
5232 do_s2io_store_unicast_mc(sp);
5233 return SUCCESS;
5234 }
5235 }
5236 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5237 (unsigned long long)addr);
5238 return FAILURE;
5239}
5240
5241/* read mac entries from CAM */
5242static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5243{
5244 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5245 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5246
5247 /* read mac addr */
5248 val64 =
5249 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5250 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5251 writeq(val64, &bar0->rmac_addr_cmd_mem);
5252
5253 /* Wait till command completes */
5254 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5255 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5256 S2IO_BIT_RESET)) {
5257 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5258 return FAILURE;
5259 }
5260 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5261 return (tmp64 >> 16);
5262}
2fd37688
SS		 5263
5264/**
5265 * s2io_set_mac_addr driver entry point
5266 */
faa4f796 5267
2fd37688
SS		 5268static int s2io_set_mac_addr(struct net_device *dev, void *p)
5269{
5270 struct sockaddr *addr = p;
5271
5272 if (!is_valid_ether_addr(addr->sa_data))
5273 return -EINVAL;
5274
5275 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5276
5277 /* store the MAC address in CAM */
5278 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5279}
1da177e4 5280/**
2fd37688 5281 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5282 * @dev : pointer to the device structure.
5283 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5284 * Description : This procedure will program the Xframe to receive
1da177e4 5285 * frames with new Mac Address
20346722 5286 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5287 * as defined in errno.h file on failure.
5288 */
faa4f796 5289
2fd37688 5290static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5291{
1ee6dd77 5292 struct s2io_nic *sp = dev->priv;
2fd37688 5293 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5294 int i;
faa4f796
SH		 5295 u64 tmp64;
5296 struct config_param *config = &sp->config;
1da177e4 5297
20346722 5298 /*
2fd37688
SS		 5299 * Set the new MAC address as the new unicast filter and reflect this
5300 * change on the device address registered with the OS. It will be
5301 * at offset 0.
5302 */
1da177e4
LT		 5303 for (i = 0; i < ETH_ALEN; i++) {
5304 mac_addr <<= 8;
5305 mac_addr |= addr[i];
2fd37688
SS		 5306 perm_addr <<= 8;
5307 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5308 }
5309
2fd37688
SS		 5310 /* check if the dev_addr is different than perm_addr */
5311 if (mac_addr == perm_addr)
d8d70caf
SS		 5312 return SUCCESS;
5313
faa4f796
SH		 5314 /* check if the mac already preset in CAM */
5315 for (i = 1; i < config->max_mac_addr; i++) {
5316 tmp64 = do_s2io_read_unicast_mc(sp, i);
5317 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5318 break;
5319
5320 if (tmp64 == mac_addr) {
5321 DBG_PRINT(INFO_DBG,
5322 "MAC addr:0x%llx already present in CAM\n",
5323 (unsigned long long)mac_addr);
5324 return SUCCESS;
5325 }
5326 }
5327 if (i == config->max_mac_addr) {
5328 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5329 return FAILURE;
5330 }
d8d70caf 5331 /* Update the internal structure with this new mac address */
faa4f796
SH		 5332 do_s2io_copy_mac_addr(sp, i, mac_addr);
5333 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5334}
5335
5336/**
20346722 5337 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5338 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5339 * @info: pointer to the structure with parameters given by ethtool to set
5340 * link information.
5341 * Description:
20346722 5342 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5343 * the NIC.
5344 * Return value:
5345 * 0 on success.
5346*/
5347
5348static int s2io_ethtool_sset(struct net_device *dev,
5349 struct ethtool_cmd *info)
5350{
1ee6dd77 5351 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5352 if ((info->autoneg == AUTONEG_ENABLE) ||
5353 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5354 return -EINVAL;
5355 else {
5356 s2io_close(sp->dev);
5357 s2io_open(sp->dev);
5358 }
5359
5360 return 0;
5361}
5362
5363/**
20346722 5364 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5365 * @sp : private member of the device structure, pointer to the
5366 * s2io_nic structure.
5367 * @info : pointer to the structure with parameters given by ethtool
5368 * to return link information.
5369 * Description:
5370 * Returns link specific information like speed, duplex etc.. to ethtool.
5371 * Return value :
5372 * return 0 on success.
5373 */
5374
5375static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5376{
1ee6dd77 5377 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5378 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5379 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5380 info->port = PORT_FIBRE;
1a7eb72b
SS		 5381
5382 /* info->transceiver */
5383 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5384
5385 if (netif_carrier_ok(sp->dev)) {
5386 info->speed = 10000;
5387 info->duplex = DUPLEX_FULL;
5388 } else {
5389 info->speed = -1;
5390 info->duplex = -1;
5391 }
5392
5393 info->autoneg = AUTONEG_DISABLE;
5394 return 0;
5395}
5396
5397/**
20346722 5398 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5399 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5400 * s2io_nic structure.
5401 * @info : pointer to the structure with parameters given by ethtool to
5402 * return driver information.
5403 * Description:
5404 * Returns driver specefic information like name, version etc.. to ethtool.
5405 * Return value:
5406 * void
5407 */
5408
5409static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5410 struct ethtool_drvinfo *info)
5411{
1ee6dd77 5412 struct s2io_nic *sp = dev->priv;
1da177e4 5413
dbc2309d
JL		 5414 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5415 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5416 strncpy(info->fw_version, "", sizeof(info->fw_version));
5417 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5418 info->regdump_len = XENA_REG_SPACE;
5419 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5420}
5421
5422/**
5423 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5424 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5425 * s2io_nic structure.
20346722 5426 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5427 * dumping the registers.
5428 * @reg_space: The input argumnet into which all the registers are dumped.
5429 * Description:
5430 * Dumps the entire register space of xFrame NIC into the user given
5431 * buffer area.
5432 * Return value :
5433 * void .
5434*/
5435
5436static void s2io_ethtool_gregs(struct net_device *dev,
5437 struct ethtool_regs *regs, void *space)
5438{
5439 int i;
5440 u64 reg;
5441 u8 *reg_space = (u8 *) space;
1ee6dd77 5442 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5443
5444 regs->len = XENA_REG_SPACE;
5445 regs->version = sp->pdev->subsystem_device;
5446
5447 for (i = 0; i < regs->len; i += 8) {
5448 reg = readq(sp->bar0 + i);
5449 memcpy((reg_space + i), &reg, 8);
5450 }
5451}
5452
5453/**
5454 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5455 * @data : address of the private member of the device structure, which
1da177e4 5456 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 5457 * Description: This is actually the timer function that alternates the
5458 * adapter LED bit of the adapter control bit to set/reset every time on
5459 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5460 * once every second.
5461*/
5462static void s2io_phy_id(unsigned long data)
5463{
1ee6dd77
RB		 5464 struct s2io_nic *sp = (struct s2io_nic *) data;
5465 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5466 u64 val64 = 0;
5467 u16 subid;
5468
5469 subid = sp->pdev->subsystem_device;
541ae68f 5470 if ((sp->device_type == XFRAME_II_DEVICE) ||
5471 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5472 val64 = readq(&bar0->gpio_control);
5473 val64 ^= GPIO_CTRL_GPIO_0;
5474 writeq(val64, &bar0->gpio_control);
5475 } else {
5476 val64 = readq(&bar0->adapter_control);
5477 val64 ^= ADAPTER_LED_ON;
5478 writeq(val64, &bar0->adapter_control);
5479 }
5480
5481 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5482}
5483
5484/**
5485 * s2io_ethtool_idnic - To physically identify the nic on the system.
5486 * @sp : private member of the device structure, which is a pointer to the
5487 * s2io_nic structure.
20346722 5488 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5489 * ethtool.
5490 * Description: Used to physically identify the NIC on the system.
20346722 5491 * The Link LED will blink for a time specified by the user for
1da177e4 5492 * identification.
20346722 5493 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5494 * identification is possible only if it's link is up.
5495 * Return value:
5496 * int , returns 0 on success
5497 */
5498
5499static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5500{
5501 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 5502 struct s2io_nic *sp = dev->priv;
5503 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5504 u16 subid;
5505
5506 subid = sp->pdev->subsystem_device;
5507 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f 5508 if ((sp->device_type == XFRAME_I_DEVICE) &&
5509 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5510 val64 = readq(&bar0->adapter_control);
5511 if (!(val64 & ADAPTER_CNTL_EN)) {
5512 printk(KERN_ERR
5513 "Adapter Link down, cannot blink LED\n");
5514 return -EFAULT;
5515 }
5516 }
5517 if (sp->id_timer.function == NULL) {
5518 init_timer(&sp->id_timer);
5519 sp->id_timer.function = s2io_phy_id;
5520 sp->id_timer.data = (unsigned long) sp;
5521 }
5522 mod_timer(&sp->id_timer, jiffies);
5523 if (data)
20346722 5524 msleep_interruptible(data * HZ);
1da177e4 5525 else
20346722 5526 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5527 del_timer_sync(&sp->id_timer);
5528
541ae68f 5529 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5530 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5531 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5532 }
5533
5534 return 0;
5535}
5536
0cec35eb
SH		 5537static void s2io_ethtool_gringparam(struct net_device *dev,
5538 struct ethtool_ringparam *ering)
5539{
5540 struct s2io_nic *sp = dev->priv;
5541 int i,tx_desc_count=0,rx_desc_count=0;
5542
5543 if (sp->rxd_mode == RXD_MODE_1)
5544 ering->rx_max_pending = MAX_RX_DESC_1;
5545 else if (sp->rxd_mode == RXD_MODE_3B)
5546 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5547
5548 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5549 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5550 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5551
0cec35eb
SH		 5552 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5553 ering->tx_pending = tx_desc_count;
5554 rx_desc_count = 0;
8a4bdbaa 5555 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5556 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5557
0cec35eb
SH		 5558 ering->rx_pending = rx_desc_count;
5559
5560 ering->rx_mini_max_pending = 0;
5561 ering->rx_mini_pending = 0;
5562 if(sp->rxd_mode == RXD_MODE_1)
5563 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5564 else if (sp->rxd_mode == RXD_MODE_3B)
5565 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5566 ering->rx_jumbo_pending = rx_desc_count;
5567}
5568
1da177e4
LT		 5569/**
5570 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5571 * @sp : private member of the device structure, which is a pointer to the
5572 * s2io_nic structure.
1da177e4
LT		 5573 * @ep : pointer to the structure with pause parameters given by ethtool.
5574 * Description:
5575 * Returns the Pause frame generation and reception capability of the NIC.
5576 * Return value:
5577 * void
5578 */
5579static void s2io_ethtool_getpause_data(struct net_device *dev,
5580 struct ethtool_pauseparam *ep)
5581{
5582 u64 val64;
1ee6dd77
RB		 5583 struct s2io_nic *sp = dev->priv;
5584 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5585
5586 val64 = readq(&bar0->rmac_pause_cfg);
5587 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5588 ep->tx_pause = TRUE;
5589 if (val64 & RMAC_PAUSE_RX_ENABLE)
5590 ep->rx_pause = TRUE;
5591 ep->autoneg = FALSE;
5592}
5593
5594/**
5595 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5596 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5597 * s2io_nic structure.
5598 * @ep : pointer to the structure with pause parameters given by ethtool.
5599 * Description:
5600 * It can be used to set or reset Pause frame generation or reception
5601 * support of the NIC.
5602 * Return value:
5603 * int, returns 0 on Success
5604 */
5605
5606static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5607 struct ethtool_pauseparam *ep)
1da177e4
LT		 5608{
5609 u64 val64;
1ee6dd77
RB		 5610 struct s2io_nic *sp = dev->priv;
5611 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5612
5613 val64 = readq(&bar0->rmac_pause_cfg);
5614 if (ep->tx_pause)
5615 val64 |= RMAC_PAUSE_GEN_ENABLE;
5616 else
5617 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5618 if (ep->rx_pause)
5619 val64 |= RMAC_PAUSE_RX_ENABLE;
5620 else
5621 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5622 writeq(val64, &bar0->rmac_pause_cfg);
5623 return 0;
5624}
5625
5626/**
5627 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5628 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5629 * s2io_nic structure.
5630 * @off : offset at which the data must be written
5631 * @data : Its an output parameter where the data read at the given
20346722 5632 * offset is stored.
1da177e4 5633 * Description:
20346722 5634 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5635 * read data.
5636 * NOTE: Will allow to read only part of the EEPROM visible through the
5637 * I2C bus.
5638 * Return value:
5639 * -1 on failure and 0 on success.
5640 */
5641
5642#define S2IO_DEV_ID 5
1ee6dd77 5643static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5644{
5645 int ret = -1;
5646 u32 exit_cnt = 0;
5647 u64 val64;
1ee6dd77 5648 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5649
ad4ebed0 5650 if (sp->device_type == XFRAME_I_DEVICE) {
5651 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5652 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5653 I2C_CONTROL_CNTL_START;
5654 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5655
ad4ebed0 5656 while (exit_cnt < 5) {
5657 val64 = readq(&bar0->i2c_control);
5658 if (I2C_CONTROL_CNTL_END(val64)) {
5659 *data = I2C_CONTROL_GET_DATA(val64);
5660 ret = 0;
5661 break;
5662 }
5663 msleep(50);
5664 exit_cnt++;
1da177e4 5665 }
1da177e4
LT		 5666 }
5667
ad4ebed0 5668 if (sp->device_type == XFRAME_II_DEVICE) {
5669 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5670 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5671 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5672 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5673 val64 |= SPI_CONTROL_REQ;
5674 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5675 while (exit_cnt < 5) {
5676 val64 = readq(&bar0->spi_control);
5677 if (val64 & SPI_CONTROL_NACK) {
5678 ret = 1;
5679 break;
5680 } else if (val64 & SPI_CONTROL_DONE) {
5681 *data = readq(&bar0->spi_data);
5682 *data &= 0xffffff;
5683 ret = 0;
5684 break;
5685 }
5686 msleep(50);
5687 exit_cnt++;
5688 }
5689 }
1da177e4
LT		 5690 return ret;
5691}
5692
5693/**
5694 * write_eeprom - actually writes the relevant part of the data value.
5695 * @sp : private member of the device structure, which is a pointer to the
5696 * s2io_nic structure.
5697 * @off : offset at which the data must be written
5698 * @data : The data that is to be written
20346722 5699 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5700 * the Eeprom. (max of 3)
5701 * Description:
5702 * Actually writes the relevant part of the data value into the Eeprom
5703 * through the I2C bus.
5704 * Return value:
5705 * 0 on success, -1 on failure.
5706 */
5707
1ee6dd77 5708static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5709{
5710 int exit_cnt = 0, ret = -1;
5711 u64 val64;
1ee6dd77 5712 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5713
ad4ebed0 5714 if (sp->device_type == XFRAME_I_DEVICE) {
5715 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5716 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5717 I2C_CONTROL_CNTL_START;
5718 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5719
5720 while (exit_cnt < 5) {
5721 val64 = readq(&bar0->i2c_control);
5722 if (I2C_CONTROL_CNTL_END(val64)) {
5723 if (!(val64 & I2C_CONTROL_NACK))
5724 ret = 0;
5725 break;
5726 }
5727 msleep(50);
5728 exit_cnt++;
5729 }
5730 }
1da177e4 5731
ad4ebed0 5732 if (sp->device_type == XFRAME_II_DEVICE) {
5733 int write_cnt = (cnt == 8) ? 0 : cnt;
5734 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5735
5736 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5737 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5738 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5739 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5740 val64 |= SPI_CONTROL_REQ;
5741 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5742 while (exit_cnt < 5) {
5743 val64 = readq(&bar0->spi_control);
5744 if (val64 & SPI_CONTROL_NACK) {
5745 ret = 1;
5746 break;
5747 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5748 ret = 0;
ad4ebed0 5749 break;
5750 }
5751 msleep(50);
5752 exit_cnt++;
1da177e4 5753 }
1da177e4 5754 }
1da177e4
LT		 5755 return ret;
5756}
1ee6dd77 5757static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5758{
b41477f3
AR		 5759 u8 *vpd_data;
5760 u8 data;
9dc737a7
AR		 5761 int i=0, cnt, fail = 0;
5762 int vpd_addr = 0x80;
5763
5764 if (nic->device_type == XFRAME_II_DEVICE) {
5765 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5766 vpd_addr = 0x80;
5767 }
5768 else {
5769 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5770 vpd_addr = 0x50;
5771 }
19a60522 5772 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5773
b41477f3 5774 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5775 if (!vpd_data) {
5776 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5777 return;
c53d4945 5778 }
491976b2 5779 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5780
9dc737a7
AR		 5781 for (i = 0; i < 256; i +=4 ) {
5782 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5783 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5784 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5785 for (cnt = 0; cnt <5; cnt++) {
5786 msleep(2);
5787 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5788 if (data == 0x80)
5789 break;
5790 }
5791 if (cnt >= 5) {
5792 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5793 fail = 1;
5794 break;
5795 }
5796 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5797 (u32 *)&vpd_data[i]);
5798 }
19a60522
SS		 5799
5800 if(!fail) {
5801 /* read serial number of adapter */
5802 for (cnt = 0; cnt < 256; cnt++) {
5803 if ((vpd_data[cnt] == 'S') &&
5804 (vpd_data[cnt+1] == 'N') &&
5805 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5806 memset(nic->serial_num, 0, VPD_STRING_LEN);
5807 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5808 vpd_data[cnt+2]);
5809 break;
5810 }
5811 }
5812 }
5813
5814 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5815 memset(nic->product_name, 0, vpd_data[1]);
5816 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5817 }
b41477f3 5818 kfree(vpd_data);
491976b2 5819 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5820}
5821
1da177e4
LT		 5822/**
5823 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5824 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5825 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5826 * containing all relevant information.
5827 * @data_buf : user defined value to be written into Eeprom.
5828 * Description: Reads the values stored in the Eeprom at given offset
5829 * for a given length. Stores these values int the input argument data
5830 * buffer 'data_buf' and returns these to the caller (ethtool.)
5831 * Return value:
5832 * int 0 on success
5833 */
5834
5835static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5836 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5837{
ad4ebed0 5838 u32 i, valid;
5839 u64 data;
1ee6dd77 5840 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5841
5842 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5843
5844 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5845 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5846
5847 for (i = 0; i < eeprom->len; i += 4) {
5848 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5849 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5850 return -EFAULT;
5851 }
5852 valid = INV(data);
5853 memcpy((data_buf + i), &valid, 4);
5854 }
5855 return 0;
5856}
5857
5858/**
5859 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5860 * @sp : private member of the device structure, which is a pointer to the
5861 * s2io_nic structure.
20346722 5862 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5863 * containing all relevant information.
5864 * @data_buf ; user defined value to be written into Eeprom.
5865 * Description:
5866 * Tries to write the user provided value in the Eeprom, at the offset
5867 * given by the user.
5868 * Return value:
5869 * 0 on success, -EFAULT on failure.
5870 */
5871
5872static int s2io_ethtool_seeprom(struct net_device *dev,
5873 struct ethtool_eeprom *eeprom,
5874 u8 * data_buf)
5875{
5876 int len = eeprom->len, cnt = 0;
ad4ebed0 5877 u64 valid = 0, data;
1ee6dd77 5878 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5879
5880 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5881 DBG_PRINT(ERR_DBG,
5882 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5883 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5884 eeprom->magic);
5885 return -EFAULT;
5886 }
5887
5888 while (len) {
5889 data = (u32) data_buf[cnt] & 0x000000FF;
5890 if (data) {
5891 valid = (u32) (data << 24);
5892 } else
5893 valid = data;
5894
5895 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5896 DBG_PRINT(ERR_DBG,
5897 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5898 DBG_PRINT(ERR_DBG,
5899 "write into the specified offset\n");
5900 return -EFAULT;
5901 }
5902 cnt++;
5903 len--;
5904 }
5905
5906 return 0;
5907}
5908
5909/**
20346722 5910 * s2io_register_test - reads and writes into all clock domains.
5911 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5912 * s2io_nic structure.
5913 * @data : variable that returns the result of each of the test conducted b
5914 * by the driver.
5915 * Description:
5916 * Read and write into all clock domains. The NIC has 3 clock domains,
5917 * see that registers in all the three regions are accessible.
5918 * Return value:
5919 * 0 on success.
5920 */
5921
1ee6dd77 5922static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5923{
1ee6dd77 5924 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5925 u64 val64 = 0, exp_val;
1da177e4
LT		 5926 int fail = 0;
5927
20346722 5928 val64 = readq(&bar0->pif_rd_swapper_fb);
5929 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5930 fail = 1;
5931 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5932 }
5933
5934 val64 = readq(&bar0->rmac_pause_cfg);
5935 if (val64 != 0xc000ffff00000000ULL) {
5936 fail = 1;
5937 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5938 }
5939
5940 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5941 if (sp->device_type == XFRAME_II_DEVICE)
5942 exp_val = 0x0404040404040404ULL;
5943 else
5944 exp_val = 0x0808080808080808ULL;
5945 if (val64 != exp_val) {
1da177e4
LT		 5946 fail = 1;
5947 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5948 }
5949
5950 val64 = readq(&bar0->xgxs_efifo_cfg);
5951 if (val64 != 0x000000001923141EULL) {
5952 fail = 1;
5953 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5954 }
5955
5956 val64 = 0x5A5A5A5A5A5A5A5AULL;
5957 writeq(val64, &bar0->xmsi_data);
5958 val64 = readq(&bar0->xmsi_data);
5959 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5960 fail = 1;
5961 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5962 }
5963
5964 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5965 writeq(val64, &bar0->xmsi_data);
5966 val64 = readq(&bar0->xmsi_data);
5967 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5968 fail = 1;
5969 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5970 }
5971
5972 *data = fail;
ad4ebed0 5973 return fail;
1da177e4
LT		 5974}
5975
5976/**
20346722 5977 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5978 * @sp : private member of the device structure, which is a pointer to the
5979 * s2io_nic structure.
5980 * @data:variable that returns the result of each of the test conducted by
5981 * the driver.
5982 * Description:
20346722 5983 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5984 * register.
5985 * Return value:
5986 * 0 on success.
5987 */
5988
1ee6dd77 5989static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5990{
5991 int fail = 0;
ad4ebed0 5992 u64 ret_data, org_4F0, org_7F0;
5993 u8 saved_4F0 = 0, saved_7F0 = 0;
5994 struct net_device *dev = sp->dev;
1da177e4
LT		 5995
5996 /* Test Write Error at offset 0 */
ad4ebed0 5997 /* Note that SPI interface allows write access to all areas
5998 * of EEPROM. Hence doing all negative testing only for Xframe I.
5999 */
6000 if (sp->device_type == XFRAME_I_DEVICE)
6001 if (!write_eeprom(sp, 0, 0, 3))
6002 fail = 1;
6003
6004 /* Save current values at offsets 0x4F0 and 0x7F0 */
6005 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6006 saved_4F0 = 1;
6007 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6008 saved_7F0 = 1;
1da177e4
LT		 6009
6010 /* Test Write at offset 4f0 */
ad4ebed0 6011 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6012 fail = 1;
6013 if (read_eeprom(sp, 0x4F0, &ret_data))
6014 fail = 1;
6015
ad4ebed0 6016 if (ret_data != 0x012345) {
26b7625c
AM		 6017 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6018 "Data written %llx Data read %llx\n",
6019 dev->name, (unsigned long long)0x12345,
6020 (unsigned long long)ret_data);
1da177e4 6021 fail = 1;
ad4ebed0 6022 }
1da177e4
LT		 6023
6024 /* Reset the EEPROM data go FFFF */
ad4ebed0 6025 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6026
6027 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6028 if (sp->device_type == XFRAME_I_DEVICE)
6029 if (!write_eeprom(sp, 0x07C, 0, 3))
6030 fail = 1;
1da177e4 6031
ad4ebed0 6032 /* Test Write Request at offset 0x7f0 */
6033 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6034 fail = 1;
ad4ebed0 6035 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6036 fail = 1;
6037
ad4ebed0 6038 if (ret_data != 0x012345) {
26b7625c
AM		 6039 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6040 "Data written %llx Data read %llx\n",
6041 dev->name, (unsigned long long)0x12345,
6042 (unsigned long long)ret_data);
1da177e4 6043 fail = 1;
ad4ebed0 6044 }
1da177e4
LT		 6045
6046 /* Reset the EEPROM data go FFFF */
ad4ebed0 6047 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6048
ad4ebed0 6049 if (sp->device_type == XFRAME_I_DEVICE) {
6050 /* Test Write Error at offset 0x80 */
6051 if (!write_eeprom(sp, 0x080, 0, 3))
6052 fail = 1;
1da177e4 6053
ad4ebed0 6054 /* Test Write Error at offset 0xfc */
6055 if (!write_eeprom(sp, 0x0FC, 0, 3))
6056 fail = 1;
1da177e4 6057
ad4ebed0 6058 /* Test Write Error at offset 0x100 */
6059 if (!write_eeprom(sp, 0x100, 0, 3))
6060 fail = 1;
1da177e4 6061
ad4ebed0 6062 /* Test Write Error at offset 4ec */
6063 if (!write_eeprom(sp, 0x4EC, 0, 3))
6064 fail = 1;
6065 }
6066
6067 /* Restore values at offsets 0x4F0 and 0x7F0 */
6068 if (saved_4F0)
6069 write_eeprom(sp, 0x4F0, org_4F0, 3);
6070 if (saved_7F0)
6071 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6072
6073 *data = fail;
ad4ebed0 6074 return fail;
1da177e4
LT		 6075}
6076
6077/**
6078 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6079 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6080 * s2io_nic structure.
20346722 6081 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6082 * the driver.
6083 * Description:
6084 * This invokes the MemBist test of the card. We give around
6085 * 2 secs time for the Test to complete. If it's still not complete
20346722 6086 * within this peiod, we consider that the test failed.
1da177e4
LT		 6087 * Return value:
6088 * 0 on success and -1 on failure.
6089 */
6090
1ee6dd77 6091static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6092{
6093 u8 bist = 0;
6094 int cnt = 0, ret = -1;
6095
6096 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6097 bist |= PCI_BIST_START;
6098 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6099
6100 while (cnt < 20) {
6101 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6102 if (!(bist & PCI_BIST_START)) {
6103 *data = (bist & PCI_BIST_CODE_MASK);
6104 ret = 0;
6105 break;
6106 }
6107 msleep(100);
6108 cnt++;
6109 }
6110
6111 return ret;
6112}
6113
6114/**
20346722 6115 * s2io-link_test - verifies the link state of the nic
6116 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6117 * s2io_nic structure.
6118 * @data: variable that returns the result of each of the test conducted by
6119 * the driver.
6120 * Description:
20346722 6121 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6122 * argument 'data' appropriately.
6123 * Return value:
6124 * 0 on success.
6125 */
6126
1ee6dd77 6127static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6128{
1ee6dd77 6129 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6130 u64 val64;
6131
6132 val64 = readq(&bar0->adapter_status);
c92ca04b 6133 if(!(LINK_IS_UP(val64)))
1da177e4 6134 *data = 1;
c92ca04b
AR		 6135 else
6136 *data = 0;
1da177e4 6137
b41477f3 6138 return *data;
1da177e4
LT		 6139}
6140
6141/**
20346722 6142 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6143 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6144 * s2io_nic structure.
20346722 6145 * @data - variable that returns the result of each of the test
1da177e4
LT		 6146 * conducted by the driver.
6147 * Description:
20346722 6148 * This is one of the offline test that tests the read and write
1da177e4
LT		 6149 * access to the RldRam chip on the NIC.
6150 * Return value:
6151 * 0 on success.
6152 */
6153
1ee6dd77 6154static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6155{
1ee6dd77 6156 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6157 u64 val64;
ad4ebed0 6158 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6159
6160 val64 = readq(&bar0->adapter_control);
6161 val64 &= ~ADAPTER_ECC_EN;
6162 writeq(val64, &bar0->adapter_control);
6163
6164 val64 = readq(&bar0->mc_rldram_test_ctrl);
6165 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6166 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6167
6168 val64 = readq(&bar0->mc_rldram_mrs);
6169 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6170 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6171
6172 val64 |= MC_RLDRAM_MRS_ENABLE;
6173 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6174
6175 while (iteration < 2) {
6176 val64 = 0x55555555aaaa0000ULL;
6177 if (iteration == 1) {
6178 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6179 }
6180 writeq(val64, &bar0->mc_rldram_test_d0);
6181
6182 val64 = 0xaaaa5a5555550000ULL;
6183 if (iteration == 1) {
6184 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6185 }
6186 writeq(val64, &bar0->mc_rldram_test_d1);
6187
6188 val64 = 0x55aaaaaaaa5a0000ULL;
6189 if (iteration == 1) {
6190 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6191 }
6192 writeq(val64, &bar0->mc_rldram_test_d2);
6193
ad4ebed0 6194 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6195 writeq(val64, &bar0->mc_rldram_test_add);
6196
ad4ebed0 6197 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6198 MC_RLDRAM_TEST_GO;
6199 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6200
6201 for (cnt = 0; cnt < 5; cnt++) {
6202 val64 = readq(&bar0->mc_rldram_test_ctrl);
6203 if (val64 & MC_RLDRAM_TEST_DONE)
6204 break;
6205 msleep(200);
6206 }
6207
6208 if (cnt == 5)
6209 break;
6210
ad4ebed0 6211 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6212 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6213
6214 for (cnt = 0; cnt < 5; cnt++) {
6215 val64 = readq(&bar0->mc_rldram_test_ctrl);
6216 if (val64 & MC_RLDRAM_TEST_DONE)
6217 break;
6218 msleep(500);
6219 }
6220
6221 if (cnt == 5)
6222 break;
6223
6224 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6225 if (!(val64 & MC_RLDRAM_TEST_PASS))
6226 test_fail = 1;
1da177e4
LT		 6227
6228 iteration++;
6229 }
6230
ad4ebed0 6231 *data = test_fail;
1da177e4 6232
ad4ebed0 6233 /* Bring the adapter out of test mode */
6234 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6235
6236 return test_fail;
1da177e4
LT		 6237}
6238
6239/**
6240 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6241 * @sp : private member of the device structure, which is a pointer to the
6242 * s2io_nic structure.
6243 * @ethtest : pointer to a ethtool command specific structure that will be
6244 * returned to the user.
20346722 6245 * @data : variable that returns the result of each of the test
1da177e4
LT		 6246 * conducted by the driver.
6247 * Description:
6248 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6249 * the health of the card.
6250 * Return value:
6251 * void
6252 */
6253
6254static void s2io_ethtool_test(struct net_device *dev,
6255 struct ethtool_test *ethtest,
6256 uint64_t * data)
6257{
1ee6dd77 6258 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6259 int orig_state = netif_running(sp->dev);
6260
6261 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6262 /* Offline Tests. */
20346722 6263 if (orig_state)
1da177e4 6264 s2io_close(sp->dev);
1da177e4
LT		 6265
6266 if (s2io_register_test(sp, &data[0]))
6267 ethtest->flags |= ETH_TEST_FL_FAILED;
6268
6269 s2io_reset(sp);
1da177e4
LT		 6270
6271 if (s2io_rldram_test(sp, &data[3]))
6272 ethtest->flags |= ETH_TEST_FL_FAILED;
6273
6274 s2io_reset(sp);
1da177e4
LT		 6275
6276 if (s2io_eeprom_test(sp, &data[1]))
6277 ethtest->flags |= ETH_TEST_FL_FAILED;
6278
6279 if (s2io_bist_test(sp, &data[4]))
6280 ethtest->flags |= ETH_TEST_FL_FAILED;
6281
6282 if (orig_state)
6283 s2io_open(sp->dev);
6284
6285 data[2] = 0;
6286 } else {
6287 /* Online Tests. */
6288 if (!orig_state) {
6289 DBG_PRINT(ERR_DBG,
6290 "%s: is not up, cannot run test\n",
6291 dev->name);
6292 data[0] = -1;
6293 data[1] = -1;
6294 data[2] = -1;
6295 data[3] = -1;
6296 data[4] = -1;
6297 }
6298
6299 if (s2io_link_test(sp, &data[2]))
6300 ethtest->flags |= ETH_TEST_FL_FAILED;
6301
6302 data[0] = 0;
6303 data[1] = 0;
6304 data[3] = 0;
6305 data[4] = 0;
6306 }
6307}
6308
6309static void s2io_get_ethtool_stats(struct net_device *dev,
6310 struct ethtool_stats *estats,
6311 u64 * tmp_stats)
6312{
8116f3cf 6313 int i = 0, k;
1ee6dd77
RB		 6314 struct s2io_nic *sp = dev->priv;
6315 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6316
7ba013ac 6317 s2io_updt_stats(sp);
541ae68f 6318 tmp_stats[i++] =
6319 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6320 le32_to_cpu(stat_info->tmac_frms);
6321 tmp_stats[i++] =
6322 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6323 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6324 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f 6325 tmp_stats[i++] =
6326 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6327 le32_to_cpu(stat_info->tmac_mcst_frms);
6328 tmp_stats[i++] =
6329 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6330 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6331 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6332 tmp_stats[i++] =
6333 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6334 le32_to_cpu(stat_info->tmac_ttl_octets);
6335 tmp_stats[i++] =
6336 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6337 le32_to_cpu(stat_info->tmac_ucst_frms);
6338 tmp_stats[i++] =
6339 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6340 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f 6341 tmp_stats[i++] =
6342 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6343 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6344 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6345 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f 6346 tmp_stats[i++] =
6347 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6348 le32_to_cpu(stat_info->tmac_vld_ip);
6349 tmp_stats[i++] =
6350 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6351 le32_to_cpu(stat_info->tmac_drop_ip);
6352 tmp_stats[i++] =
6353 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6354 le32_to_cpu(stat_info->tmac_icmp);
6355 tmp_stats[i++] =
6356 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6357 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6358 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f 6359 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6360 le32_to_cpu(stat_info->tmac_udp);
6361 tmp_stats[i++] =
6362 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6363 le32_to_cpu(stat_info->rmac_vld_frms);
6364 tmp_stats[i++] =
6365 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6366 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6367 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6368 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f 6369 tmp_stats[i++] =
6370 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6371 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6372 tmp_stats[i++] =
6373 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6374 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6375 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6376 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6377 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6378 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6379 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6380 tmp_stats[i++] =
6381 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6382 le32_to_cpu(stat_info->rmac_ttl_octets);
6383 tmp_stats[i++] =
6384 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6385 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6386 tmp_stats[i++] =
6387 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6388 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f 6389 tmp_stats[i++] =
6390 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6391 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6392 tmp_stats[i++] =
6393 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6394 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6395 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6396 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f 6397 tmp_stats[i++] =
6398 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6399 le32_to_cpu(stat_info->rmac_usized_frms);
6400 tmp_stats[i++] =
6401 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6402 le32_to_cpu(stat_info->rmac_osized_frms);
6403 tmp_stats[i++] =
6404 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6405 le32_to_cpu(stat_info->rmac_frag_frms);
6406 tmp_stats[i++] =
6407 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6408 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6409 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6410 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6411 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6412 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6413 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6414 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6415 tmp_stats[i++] =
6416 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6417 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6418 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6419 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6420 tmp_stats[i++] =
6421 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6422 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6423 tmp_stats[i++] =
6424 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6425 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6426 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6427 tmp_stats[i++] =
6428 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f 6429 le32_to_cpu(stat_info->rmac_udp);
6430 tmp_stats[i++] =
6431 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6432 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6433 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6434 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6435 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6436 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6437 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6438 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6439 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6440 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6441 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6442 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6443 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6444 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6445 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6446 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6447 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6448 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6449 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f 6450 tmp_stats[i++] =
6451 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6452 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6453 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6454 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f 6455 tmp_stats[i++] =
6456 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6457 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6458 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6459 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6460 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6461 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6462 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6463 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6464 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6477
6478 /* Enhanced statistics exist only for Hercules */
6479 if(sp->device_type == XFRAME_II_DEVICE) {
6480 tmp_stats[i++] =
6481 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6482 tmp_stats[i++] =
6483 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6484 tmp_stats[i++] =
6485 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6486 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6487 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6488 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6489 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6490 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6491 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6492 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6493 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6494 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6495 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6496 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6497 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6498 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6499 }
6500
7ba013ac 6501 tmp_stats[i++] = 0;
6502 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6503 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6504 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6505 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6506 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6507 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6508 for (k = 0; k < MAX_RX_RINGS; k++)
6509 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6510 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6511 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6512 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6513 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6514 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6515 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6516 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6517 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6518 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6519 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6520 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6521 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6522 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6523 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6524 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6525 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6526 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6527 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6528 int count = 0;
6aa20a22 6529 /*
bd1034f0
AR		 6530 * Since 64-bit divide does not work on all platforms,
6531 * do repeated subtraction.
6532 */
6533 while (tmp >= stat_info->sw_stat.num_aggregations) {
6534 tmp -= stat_info->sw_stat.num_aggregations;
6535 count++;
6536 }
6537 tmp_stats[i++] = count;
fe931395 6538 }
bd1034f0
AR		 6539 else
6540 tmp_stats[i++] = 0;
c53d4945 6541 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6542 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6543 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6544 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6545 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6546 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6547 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6548 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6549 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6550
6551 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6552 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6553 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6554 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6555 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6556
6557 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6558 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6559 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6560 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6561 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6562 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6563 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6564 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6565 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6566 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6567 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6568 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6569 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6570 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6571 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6572 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6573 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6574 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6575 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6576 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6577 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6578 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6579 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6580 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6581 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6582 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6583}
6584
ac1f60db 6585static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6586{
6587 return (XENA_REG_SPACE);
6588}
6589
6590
ac1f60db 6591static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6592{
1ee6dd77 6593 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6594
6595 return (sp->rx_csum);
6596}
ac1f60db
AB		 6597
6598static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6599{
1ee6dd77 6600 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6601
6602 if (data)
6603 sp->rx_csum = 1;
6604 else
6605 sp->rx_csum = 0;
6606
6607 return 0;
6608}
ac1f60db
AB		 6609
6610static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6611{
6612 return (XENA_EEPROM_SPACE);
6613}
6614
b9f2c044 6615static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6616{
b9f2c044
JG		 6617 struct s2io_nic *sp = dev->priv;
6618
6619 switch (sset) {
6620 case ETH_SS_TEST:
6621 return S2IO_TEST_LEN;
6622 case ETH_SS_STATS:
6623 switch(sp->device_type) {
6624 case XFRAME_I_DEVICE:
6625 return XFRAME_I_STAT_LEN;
6626 case XFRAME_II_DEVICE:
6627 return XFRAME_II_STAT_LEN;
6628 default:
6629 return 0;
6630 }
6631 default:
6632 return -EOPNOTSUPP;
6633 }
1da177e4 6634}
ac1f60db
AB		 6635
6636static void s2io_ethtool_get_strings(struct net_device *dev,
6637 u32 stringset, u8 * data)
1da177e4 6638{
fa1f0cb3
SS		 6639 int stat_size = 0;
6640 struct s2io_nic *sp = dev->priv;
6641
1da177e4
LT		 6642 switch (stringset) {
6643 case ETH_SS_TEST:
6644 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6645 break;
6646 case ETH_SS_STATS:
fa1f0cb3
SS		 6647 stat_size = sizeof(ethtool_xena_stats_keys);
6648 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6649 if(sp->device_type == XFRAME_II_DEVICE) {
6650 memcpy(data + stat_size,
6651 &ethtool_enhanced_stats_keys,
6652 sizeof(ethtool_enhanced_stats_keys));
6653 stat_size += sizeof(ethtool_enhanced_stats_keys);
6654 }
6655
6656 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6657 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6658 }
6659}
1da177e4 6660
ac1f60db 6661static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6662{
6663 if (data)
6664 dev->features |= NETIF_F_IP_CSUM;
6665 else
6666 dev->features &= ~NETIF_F_IP_CSUM;
6667
6668 return 0;
6669}
6670
75c30b13
AR		 6671static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6672{
6673 return (dev->features & NETIF_F_TSO) != 0;
6674}
6675static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6676{
6677 if (data)
6678 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6679 else
6680 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6681
6682 return 0;
6683}
1da177e4 6684
7282d491 6685static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6686 .get_settings = s2io_ethtool_gset,
6687 .set_settings = s2io_ethtool_sset,
6688 .get_drvinfo = s2io_ethtool_gdrvinfo,
6689 .get_regs_len = s2io_ethtool_get_regs_len,
6690 .get_regs = s2io_ethtool_gregs,
6691 .get_link = ethtool_op_get_link,
6692 .get_eeprom_len = s2io_get_eeprom_len,
6693 .get_eeprom = s2io_ethtool_geeprom,
6694 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6695 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6696 .get_pauseparam = s2io_ethtool_getpause_data,
6697 .set_pauseparam = s2io_ethtool_setpause_data,
6698 .get_rx_csum = s2io_ethtool_get_rx_csum,
6699 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6700 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6701 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6702 .get_tso = s2io_ethtool_op_get_tso,
6703 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6704 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6705 .self_test = s2io_ethtool_test,
6706 .get_strings = s2io_ethtool_get_strings,
6707 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6708 .get_ethtool_stats = s2io_get_ethtool_stats,
6709 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6710};
6711
6712/**
20346722 6713 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6714 * @dev : Device pointer.
6715 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6716 * a proprietary structure used to pass information to the driver.
6717 * @cmd : This is used to distinguish between the different commands that
6718 * can be passed to the IOCTL functions.
6719 * Description:
20346722 6720 * Currently there are no special functionality supported in IOCTL, hence
6721 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6722 */
6723
ac1f60db 6724static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6725{
6726 return -EOPNOTSUPP;
6727}
6728
6729/**
6730 * s2io_change_mtu - entry point to change MTU size for the device.
6731 * @dev : device pointer.
6732 * @new_mtu : the new MTU size for the device.
6733 * Description: A driver entry point to change MTU size for the device.
6734 * Before changing the MTU the device must be stopped.
6735 * Return value:
6736 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6737 * file on failure.
6738 */
6739
ac1f60db 6740static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6741{
1ee6dd77 6742 struct s2io_nic *sp = dev->priv;
9f74ffde 6743 int ret = 0;
1da177e4
LT		 6744
6745 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6746 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6747 dev->name);
6748 return -EPERM;
6749 }
6750
1da177e4 6751 dev->mtu = new_mtu;
d8892c6e 6752 if (netif_running(dev)) {
3a3d5756 6753 s2io_stop_all_tx_queue(sp);
e6a8fee2 6754 s2io_card_down(sp);
9f74ffde
SH		 6755 ret = s2io_card_up(sp);
6756 if (ret) {
d8892c6e 6757 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6758 __FUNCTION__);
9f74ffde 6759 return ret;
d8892c6e 6760 }
3a3d5756 6761 s2io_wake_all_tx_queue(sp);
d8892c6e 6762 } else { /* Device is down */
1ee6dd77 6763 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6764 u64 val64 = new_mtu;
6765
6766 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6767 }
1da177e4 6768
9f74ffde 6769 return ret;
1da177e4
LT		 6770}
6771
6772/**
6773 * s2io_tasklet - Bottom half of the ISR.
6774 * @dev_adr : address of the device structure in dma_addr_t format.
6775 * Description:
6776 * This is the tasklet or the bottom half of the ISR. This is
20346722 6777 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 6778 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 6779 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 6780 * replenish the Rx buffers in the Rx buffer descriptors.
6781 * Return value:
6782 * void.
6783 */
6784
6785static void s2io_tasklet(unsigned long dev_addr)
6786{
6787 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 6788 struct s2io_nic *sp = dev->priv;
1da177e4 6789 int i, ret;
1ee6dd77 6790 struct mac_info *mac_control;
1da177e4
LT		 6791 struct config_param *config;
6792
6793 mac_control = &sp->mac_control;
6794 config = &sp->config;
6795
6796 if (!TASKLET_IN_USE) {
6797 for (i = 0; i < config->rx_ring_num; i++) {
6798 ret = fill_rx_buffers(sp, i);
6799 if (ret == -ENOMEM) {
0c61ed5f 6800 DBG_PRINT(INFO_DBG, "%s: Out of ",
1da177e4 6801 dev->name);
491976b2 6802 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
1da177e4
LT		 6803 break;
6804 } else if (ret == -EFILL) {
0c61ed5f 6805 DBG_PRINT(INFO_DBG,
1da177e4
LT		 6806 "%s: Rx Ring %d is full\n",
6807 dev->name, i);
6808 break;
6809 }
6810 }
6811 clear_bit(0, (&sp->tasklet_status));
6812 }
6813}
6814
6815/**
6816 * s2io_set_link - Set the LInk status
6817 * @data: long pointer to device private structue
6818 * Description: Sets the link status for the adapter
6819 */
6820
c4028958 6821static void s2io_set_link(struct work_struct *work)
1da177e4 6822{
1ee6dd77 6823 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6824 struct net_device *dev = nic->dev;
1ee6dd77 6825 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6826 register u64 val64;
6827 u16 subid;
6828
22747d6b
FR		 6829 rtnl_lock();
6830
6831 if (!netif_running(dev))
6832 goto out_unlock;
6833
92b84437 6834 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6835 /* The card is being reset, no point doing anything */
22747d6b 6836 goto out_unlock;
1da177e4
LT		 6837 }
6838
6839 subid = nic->pdev->subsystem_device;
a371a07d 6840 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6841 /*
6842 * Allow a small delay for the NICs self initiated
6843 * cleanup to complete.
6844 */
6845 msleep(100);
6846 }
1da177e4
LT		 6847
6848 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6849 if (LINK_IS_UP(val64)) {
6850 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6851 if (verify_xena_quiescence(nic)) {
6852 val64 = readq(&bar0->adapter_control);
6853 val64 |= ADAPTER_CNTL_EN;
1da177e4 6854 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6855 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6856 nic->device_type, subid)) {
6857 val64 = readq(&bar0->gpio_control);
6858 val64 |= GPIO_CTRL_GPIO_0;
6859 writeq(val64, &bar0->gpio_control);
6860 val64 = readq(&bar0->gpio_control);
6861 } else {
6862 val64 |= ADAPTER_LED_ON;
6863 writeq(val64, &bar0->adapter_control);
a371a07d 6864 }
1da177e4 6865 nic->device_enabled_once = TRUE;
19a60522
SS		 6866 } else {
6867 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6868 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6869 s2io_stop_all_tx_queue(nic);
1da177e4 6870 }
19a60522 6871 }
92c48799
SS		 6872 val64 = readq(&bar0->adapter_control);
6873 val64 |= ADAPTER_LED_ON;
6874 writeq(val64, &bar0->adapter_control);
6875 s2io_link(nic, LINK_UP);
19a60522
SS		 6876 } else {
6877 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6878 subid)) {
6879 val64 = readq(&bar0->gpio_control);
6880 val64 &= ~GPIO_CTRL_GPIO_0;
6881 writeq(val64, &bar0->gpio_control);
6882 val64 = readq(&bar0->gpio_control);
1da177e4 6883 }
92c48799
SS		 6884 /* turn off LED */
6885 val64 = readq(&bar0->adapter_control);
6886 val64 = val64 &(~ADAPTER_LED_ON);
6887 writeq(val64, &bar0->adapter_control);
19a60522 6888 s2io_link(nic, LINK_DOWN);
1da177e4 6889 }
92b84437 6890 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6891
6892out_unlock:
d8d70caf 6893 rtnl_unlock();
1da177e4
LT		 6894}
6895
1ee6dd77
RB		 6896static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6897 struct buffAdd *ba,
6898 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6899 u64 *temp2, int size)
5d3213cc
AR		 6900{
6901 struct net_device *dev = sp->dev;
491abf25 6902 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6903
6904 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6905 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6906 /* allocate skb */
6907 if (*skb) {
6908 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6909 /*
6910 * As Rx frame are not going to be processed,
6911 * using same mapped address for the Rxd
6912 * buffer pointer
6913 */
6d517a27 6914 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6915 } else {
6916 *skb = dev_alloc_skb(size);
6917 if (!(*skb)) {
0c61ed5f 6918 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6919 DBG_PRINT(INFO_DBG, "memory to allocate ");
6920 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6921 sp->mac_control.stats_info->sw_stat. \
6922 mem_alloc_fail_cnt++;
5d3213cc
AR		 6923 return -ENOMEM ;
6924 }
8a4bdbaa 6925 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6926 += (*skb)->truesize;
5d3213cc
AR		 6927 /* storing the mapped addr in a temp variable
6928 * such it will be used for next rxd whose
6929 * Host Control is NULL
6930 */
6d517a27 6931 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6932 pci_map_single( sp->pdev, (*skb)->data,
6933 size - NET_IP_ALIGN,
6934 PCI_DMA_FROMDEVICE);
491abf25
VP		 6935 if( (rxdp1->Buffer0_ptr == 0) ||
6936 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6937 goto memalloc_failed;
6938 }
5d3213cc
AR		 6939 rxdp->Host_Control = (unsigned long) (*skb);
6940 }
6941 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6942 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6943 /* Two buffer Mode */
6944 if (*skb) {
6d517a27
VP		 6945 rxdp3->Buffer2_ptr = *temp2;
6946 rxdp3->Buffer0_ptr = *temp0;
6947 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6948 } else {
6949 *skb = dev_alloc_skb(size);
2ceaac75 6950 if (!(*skb)) {
c53d4945
SH		 6951 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6952 DBG_PRINT(INFO_DBG, "memory to allocate ");
6953 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6954 sp->mac_control.stats_info->sw_stat. \
6955 mem_alloc_fail_cnt++;
2ceaac75
DR		 6956 return -ENOMEM;
6957 }
8a4bdbaa 6958 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6959 += (*skb)->truesize;
6d517a27 6960 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6961 pci_map_single(sp->pdev, (*skb)->data,
6962 dev->mtu + 4,
6963 PCI_DMA_FROMDEVICE);
491abf25
VP		 6964 if( (rxdp3->Buffer2_ptr == 0) ||
6965 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6966 goto memalloc_failed;
6967 }
6d517a27 6968 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6969 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6970 PCI_DMA_FROMDEVICE);
491abf25
VP		 6971 if( (rxdp3->Buffer0_ptr == 0) ||
6972 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6973 pci_unmap_single (sp->pdev,
3e847423 6974 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6975 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6976 goto memalloc_failed;
6977 }
5d3213cc
AR		 6978 rxdp->Host_Control = (unsigned long) (*skb);
6979
6980 /* Buffer-1 will be dummy buffer not used */
6d517a27 6981 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6982 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6983 PCI_DMA_FROMDEVICE);
491abf25
VP		 6984 if( (rxdp3->Buffer1_ptr == 0) ||
6985 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6986 pci_unmap_single (sp->pdev,
3e847423
AV		 6987 (dma_addr_t)rxdp3->Buffer0_ptr,
6988 BUF0_LEN, PCI_DMA_FROMDEVICE);
6989 pci_unmap_single (sp->pdev,
6990 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6991 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6992 goto memalloc_failed;
6993 }
5d3213cc
AR		 6994 }
6995 }
6996 return 0;
491abf25
VP		 6997 memalloc_failed:
6998 stats->pci_map_fail_cnt++;
6999 stats->mem_freed += (*skb)->truesize;
7000 dev_kfree_skb(*skb);
7001 return -ENOMEM;
5d3213cc 7002}
491abf25 7003
1ee6dd77
RB		 7004static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
7005 int size)
5d3213cc
AR		 7006{
7007 struct net_device *dev = sp->dev;
7008 if (sp->rxd_mode == RXD_MODE_1) {
7009 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
7010 } else if (sp->rxd_mode == RXD_MODE_3B) {
7011 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7012 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
7013 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 7014 }
7015}
7016
1ee6dd77 7017static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 7018{
7019 int i, j, k, blk_cnt = 0, size;
1ee6dd77 7020 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 7021 struct config_param *config = &sp->config;
7022 struct net_device *dev = sp->dev;
1ee6dd77 7023 struct RxD_t *rxdp = NULL;
5d3213cc 7024 struct sk_buff *skb = NULL;
1ee6dd77 7025 struct buffAdd *ba = NULL;
5d3213cc
AR		 7026 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7027
7028 /* Calculate the size based on ring mode */
7029 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7030 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7031 if (sp->rxd_mode == RXD_MODE_1)
7032 size += NET_IP_ALIGN;
7033 else if (sp->rxd_mode == RXD_MODE_3B)
7034 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7035
7036 for (i = 0; i < config->rx_ring_num; i++) {
7037 blk_cnt = config->rx_cfg[i].num_rxd /
7038 (rxd_count[sp->rxd_mode] +1);
7039
7040 for (j = 0; j < blk_cnt; j++) {
7041 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7042 rxdp = mac_control->rings[i].
7043 rx_blocks[j].rxds[k].virt_addr;
6d517a27 7044 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 7045 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 7046 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 7047 &skb,(u64 *)&temp0_64,
7048 (u64 *)&temp1_64,
ac1f90d6
SS		 7049 (u64 *)&temp2_64,
7050 size) == ENOMEM) {
7051 return 0;
7052 }
5d3213cc
AR		 7053
7054 set_rxd_buffer_size(sp, rxdp, size);
7055 wmb();
7056 /* flip the Ownership bit to Hardware */
7057 rxdp->Control_1 |= RXD_OWN_XENA;
7058 }
7059 }
7060 }
7061 return 0;
7062
7063}
7064
1ee6dd77 7065static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 7066{
e6a8fee2 7067 int ret = 0;
c92ca04b 7068 struct net_device *dev = sp->dev;
e6a8fee2 7069 int err = 0;
1da177e4 7070
eaae7f72 7071 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7072 ret = s2io_enable_msi_x(sp);
7073 if (ret) {
7074 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7075 sp->config.intr_type = INTA;
20346722 7076 }
1da177e4 7077
1ee6dd77 7078 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 7079 store_xmsi_data(sp);
c92ca04b 7080
e6a8fee2 7081 /* After proper initialization of H/W, register ISR */
eaae7f72 7082 if (sp->config.intr_type == MSI_X) {
fb6a825b 7083 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 7084
e6a8fee2
AR		 7085 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
7086 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
7087 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7088 dev->name, i);
7089 err = request_irq(sp->entries[i].vector,
7090 s2io_msix_fifo_handle, 0, sp->desc[i],
7091 sp->s2io_entries[i].arg);
fb6a825b
SS		 7092 /* If either data or addr is zero print it */
7093 if(!(sp->msix_info[i].addr &&
7094 sp->msix_info[i].data)) {
2450022a 7095 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
3459feb8 7096 "Data:0x%llx\n",sp->desc[i],
fb6a825b
SS		 7097 (unsigned long long)
7098 sp->msix_info[i].addr,
3459feb8
AV		 7099 (unsigned long long)
7100 sp->msix_info[i].data);
fb6a825b
SS		 7101 } else {
7102 msix_tx_cnt++;
7103 }
e6a8fee2
AR		 7104 } else {
7105 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7106 dev->name, i);
7107 err = request_irq(sp->entries[i].vector,
7108 s2io_msix_ring_handle, 0, sp->desc[i],
7109 sp->s2io_entries[i].arg);
fb6a825b
SS		 7110 /* If either data or addr is zero print it */
7111 if(!(sp->msix_info[i].addr &&
7112 sp->msix_info[i].data)) {
2450022a 7113 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
3459feb8 7114 "Data:0x%llx\n",sp->desc[i],
fb6a825b
SS		 7115 (unsigned long long)
7116 sp->msix_info[i].addr,
3459feb8
AV		 7117 (unsigned long long)
7118 sp->msix_info[i].data);
fb6a825b
SS		 7119 } else {
7120 msix_rx_cnt++;
7121 }
c92ca04b 7122 }
e6a8fee2 7123 if (err) {
18b2b7bd 7124 remove_msix_isr(sp);
e6a8fee2
AR		 7125 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
7126 "failed\n", dev->name, i);
18b2b7bd
SH		 7127 DBG_PRINT(ERR_DBG, "%s: defaulting to INTA\n",
7128 dev->name);
7129 sp->config.intr_type = INTA;
7130 break;
e6a8fee2
AR		 7131 }
7132 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
7133 }
18b2b7bd
SH		 7134 if (!err) {
7135 printk(KERN_INFO "MSI-X-TX %d entries enabled\n",
7136 msix_tx_cnt);
7137 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
7138 msix_rx_cnt);
7139 }
e6a8fee2 7140 }
eaae7f72 7141 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7142 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7143 sp->name, dev);
7144 if (err) {
7145 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7146 dev->name);
7147 return -1;
7148 }
7149 }
7150 return 0;
7151}
1ee6dd77 7152static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7153{
18b2b7bd
SH		 7154 if (sp->config.intr_type == MSI_X)
7155 remove_msix_isr(sp);
7156 else
7157 remove_inta_isr(sp);
e6a8fee2
AR		 7158}
7159
d796fdb7 7160static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7161{
7162 int cnt = 0;
1ee6dd77 7163 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 7164 unsigned long flags;
7165 register u64 val64 = 0;
5f490c96
SH		 7166 struct config_param *config;
7167 config = &sp->config;
e6a8fee2 7168
9f74ffde
SH		 7169 if (!is_s2io_card_up(sp))
7170 return;
7171
e6a8fee2
AR		 7172 del_timer_sync(&sp->alarm_timer);
7173 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7174 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7175 msleep(50);
7176 }
92b84437 7177 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7178
5f490c96
SH		 7179 /* Disable napi */
7180 if (config->napi)
7181 napi_disable(&sp->napi);
7182
e6a8fee2 7183 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7184 if (do_io)
7185 stop_nic(sp);
e6a8fee2
AR		 7186
7187 s2io_rem_isr(sp);
1da177e4
LT		 7188
7189 /* Kill tasklet. */
7190 tasklet_kill(&sp->task);
7191
7192 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7193 while(do_io) {
5d3213cc
AR		 7194 /* As per the HW requirement we need to replenish the
7195 * receive buffer to avoid the ring bump. Since there is
7196 * no intention of processing the Rx frame at this pointwe are
7197 * just settting the ownership bit of rxd in Each Rx
7198 * ring to HW and set the appropriate buffer size
7199 * based on the ring mode
7200 */
7201 rxd_owner_bit_reset(sp);
7202
1da177e4 7203 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7204 if (verify_xena_quiescence(sp)) {
7205 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7206 break;
7207 }
7208
7209 msleep(50);
7210 cnt++;
7211 if (cnt == 10) {
7212 DBG_PRINT(ERR_DBG,
7213 "s2io_close:Device not Quiescent ");
7214 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7215 (unsigned long long) val64);
7216 break;
7217 }
d796fdb7
LV		 7218 }
7219 if (do_io)
7220 s2io_reset(sp);
1da177e4 7221
7ba013ac 7222 /* Free all Tx buffers */
1da177e4 7223 free_tx_buffers(sp);
7ba013ac 7224
7225 /* Free all Rx buffers */
7226 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 7227 free_rx_buffers(sp);
7ba013ac 7228 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 7229
92b84437 7230 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7231}
7232
d796fdb7
LV		 7233static void s2io_card_down(struct s2io_nic * sp)
7234{
7235 do_s2io_card_down(sp, 1);
7236}
7237
1ee6dd77 7238static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7239{
cc6e7c44 7240 int i, ret = 0;
1ee6dd77 7241 struct mac_info *mac_control;
1da177e4
LT		 7242 struct config_param *config;
7243 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7244 u16 interruptible;
1da177e4
LT		 7245
7246 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7247 ret = init_nic(sp);
7248 if (ret != 0) {
1da177e4
LT		 7249 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7250 dev->name);
9f74ffde
SH		 7251 if (ret != -EIO)
7252 s2io_reset(sp);
7253 return ret;
1da177e4
LT		 7254 }
7255
20346722 7256 /*
7257 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7258 * Rx ring and initializing buffers into 30 Rx blocks
7259 */
7260 mac_control = &sp->mac_control;
7261 config = &sp->config;
7262
7263 for (i = 0; i < config->rx_ring_num; i++) {
7264 if ((ret = fill_rx_buffers(sp, i))) {
7265 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7266 dev->name);
7267 s2io_reset(sp);
7268 free_rx_buffers(sp);
7269 return -ENOMEM;
7270 }
7271 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7272 atomic_read(&sp->rx_bufs_left[i]));
7273 }
5f490c96
SH		 7274
7275 /* Initialise napi */
7276 if (config->napi)
7277 napi_enable(&sp->napi);
7278
19a60522
SS		 7279 /* Maintain the state prior to the open */
7280 if (sp->promisc_flg)
7281 sp->promisc_flg = 0;
7282 if (sp->m_cast_flg) {
7283 sp->m_cast_flg = 0;
7284 sp->all_multi_pos= 0;
7285 }
1da177e4
LT		 7286
7287 /* Setting its receive mode */
7288 s2io_set_multicast(dev);
7289
7d3d0439 7290 if (sp->lro) {
b41477f3 7291 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7292 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7293 /* Check if we can use(if specified) user provided value */
7294 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7295 sp->lro_max_aggr_per_sess = lro_max_pkts;
7296 }
7297
1da177e4
LT		 7298 /* Enable Rx Traffic and interrupts on the NIC */
7299 if (start_nic(sp)) {
7300 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7301 s2io_reset(sp);
e6a8fee2
AR		 7302 free_rx_buffers(sp);
7303 return -ENODEV;
7304 }
7305
7306 /* Add interrupt service routine */
7307 if (s2io_add_isr(sp) != 0) {
eaae7f72 7308 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7309 s2io_rem_isr(sp);
7310 s2io_reset(sp);
1da177e4
LT		 7311 free_rx_buffers(sp);
7312 return -ENODEV;
7313 }
7314
25fff88e 7315 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7316
e6a8fee2
AR		 7317 /* Enable tasklet for the device */
7318 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
7319
7320 /* Enable select interrupts */
9caab458 7321 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
eaae7f72 7322 if (sp->config.intr_type != INTA)
e6a8fee2
AR		 7323 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
7324 else {
7325 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7326 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7327 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7328 }
7329
92b84437 7330 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
1da177e4
LT		 7331 return 0;
7332}
7333
20346722 7334/**
1da177e4
LT		 7335 * s2io_restart_nic - Resets the NIC.
7336 * @data : long pointer to the device private structure
7337 * Description:
7338 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7339 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7340 * the run time of the watch dog routine which is run holding a
7341 * spin lock.
7342 */
7343
c4028958 7344static void s2io_restart_nic(struct work_struct *work)
1da177e4 7345{
1ee6dd77 7346 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7347 struct net_device *dev = sp->dev;
1da177e4 7348
22747d6b
FR		 7349 rtnl_lock();
7350
7351 if (!netif_running(dev))
7352 goto out_unlock;
7353
e6a8fee2 7354 s2io_card_down(sp);
1da177e4
LT		 7355 if (s2io_card_up(sp)) {
7356 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7357 dev->name);
7358 }
3a3d5756 7359 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7360 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7361 dev->name);
22747d6b
FR		 7362out_unlock:
7363 rtnl_unlock();
1da177e4
LT		 7364}
7365
20346722 7366/**
7367 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7368 * @dev : Pointer to net device structure
7369 * Description:
7370 * This function is triggered if the Tx Queue is stopped
7371 * for a pre-defined amount of time when the Interface is still up.
7372 * If the Interface is jammed in such a situation, the hardware is
7373 * reset (by s2io_close) and restarted again (by s2io_open) to
7374 * overcome any problem that might have been caused in the hardware.
7375 * Return value:
7376 * void
7377 */
7378
7379static void s2io_tx_watchdog(struct net_device *dev)
7380{
1ee6dd77 7381 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 7382
7383 if (netif_carrier_ok(dev)) {
c53d4945 7384 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7385 schedule_work(&sp->rst_timer_task);
bd1034f0 7386 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7387 }
7388}
7389
7390/**
7391 * rx_osm_handler - To perform some OS related operations on SKB.
7392 * @sp: private member of the device structure,pointer to s2io_nic structure.
7393 * @skb : the socket buffer pointer.
7394 * @len : length of the packet
7395 * @cksum : FCS checksum of the frame.
7396 * @ring_no : the ring from which this RxD was extracted.
20346722 7397 * Description:
b41477f3 7398 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7399 * some OS related operations on the SKB before passing it to the upper
7400 * layers. It mainly checks if the checksum is OK, if so adds it to the
7401 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7402 * to the upper layer. If the checksum is wrong, it increments the Rx
7403 * packet error count, frees the SKB and returns error.
7404 * Return value:
7405 * SUCCESS on success and -1 on failure.
7406 */
1ee6dd77 7407static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7408{
1ee6dd77 7409 struct s2io_nic *sp = ring_data->nic;
1da177e4 7410 struct net_device *dev = (struct net_device *) sp->dev;
20346722 7411 struct sk_buff *skb = (struct sk_buff *)
7412 ((unsigned long) rxdp->Host_Control);
7413 int ring_no = ring_data->ring_no;
1da177e4 7414 u16 l3_csum, l4_csum;
863c11a9 7415 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 7416 struct lro *lro;
f9046eb3 7417 u8 err_mask;
da6971d8 7418
20346722 7419 skb->dev = dev;
c92ca04b 7420
863c11a9 7421 if (err) {
bd1034f0
AR		 7422 /* Check for parity error */
7423 if (err & 0x1) {
7424 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7425 }
f9046eb3
OH		 7426 err_mask = err >> 48;
7427 switch(err_mask) {
491976b2
SH		 7428 case 1:
7429 sp->mac_control.stats_info->sw_stat.
7430 rx_parity_err_cnt++;
7431 break;
7432
7433 case 2:
7434 sp->mac_control.stats_info->sw_stat.
7435 rx_abort_cnt++;
7436 break;
7437
7438 case 3:
7439 sp->mac_control.stats_info->sw_stat.
7440 rx_parity_abort_cnt++;
7441 break;
7442
7443 case 4:
7444 sp->mac_control.stats_info->sw_stat.
7445 rx_rda_fail_cnt++;
7446 break;
7447
7448 case 5:
7449 sp->mac_control.stats_info->sw_stat.
7450 rx_unkn_prot_cnt++;
7451 break;
7452
7453 case 6:
7454 sp->mac_control.stats_info->sw_stat.
7455 rx_fcs_err_cnt++;
7456 break;
bd1034f0 7457
491976b2
SH		 7458 case 7:
7459 sp->mac_control.stats_info->sw_stat.
7460 rx_buf_size_err_cnt++;
7461 break;
7462
7463 case 8:
7464 sp->mac_control.stats_info->sw_stat.
7465 rx_rxd_corrupt_cnt++;
7466 break;
7467
7468 case 15:
7469 sp->mac_control.stats_info->sw_stat.
7470 rx_unkn_err_cnt++;
7471 break;
7472 }
863c11a9
AR		 7473 /*
7474 * Drop the packet if bad transfer code. Exception being
7475 * 0x5, which could be due to unsupported IPv6 extension header.
7476 * In this case, we let stack handle the packet.
7477 * Note that in this case, since checksum will be incorrect,
7478 * stack will validate the same.
7479 */
f9046eb3
OH		 7480 if (err_mask != 0x5) {
7481 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7482 dev->name, err_mask);
863c11a9 7483 sp->stats.rx_crc_errors++;
8a4bdbaa 7484 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7485 += skb->truesize;
863c11a9
AR		 7486 dev_kfree_skb(skb);
7487 atomic_dec(&sp->rx_bufs_left[ring_no]);
7488 rxdp->Host_Control = 0;
7489 return 0;
7490 }
20346722 7491 }
1da177e4 7492
20346722 7493 /* Updating statistics */
573608e4 7494 sp->stats.rx_packets++;
20346722 7495 rxdp->Host_Control = 0;
da6971d8
AR		 7496 if (sp->rxd_mode == RXD_MODE_1) {
7497 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7498
da6971d8
AR		 7499 sp->stats.rx_bytes += len;
7500 skb_put(skb, len);
7501
6d517a27 7502 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7503 int get_block = ring_data->rx_curr_get_info.block_index;
7504 int get_off = ring_data->rx_curr_get_info.offset;
7505 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7506 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7507 unsigned char *buff = skb_push(skb, buf0_len);
7508
1ee6dd77 7509 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 7510 sp->stats.rx_bytes += buf0_len + buf2_len;
7511 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7512 skb_put(skb, buf2_len);
da6971d8 7513 }
20346722 7514
7d3d0439
RA		 7515 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7516 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 7517 (sp->rx_csum)) {
7518 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7519 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7520 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7521 /*
1da177e4
LT		 7522 * NIC verifies if the Checksum of the received
7523 * frame is Ok or not and accordingly returns
7524 * a flag in the RxD.
7525 */
7526 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 7527 if (sp->lro) {
7528 u32 tcp_len;
7529 u8 *tcp;
7530 int ret = 0;
7531
7532 ret = s2io_club_tcp_session(skb->data, &tcp,
43b7c451
SH		 7533 &tcp_len, &lro,
7534 rxdp, sp);
7d3d0439
RA		 7535 switch (ret) {
7536 case 3: /* Begin anew */
7537 lro->parent = skb;
7538 goto aggregate;
7539 case 1: /* Aggregate */
7540 {
7541 lro_append_pkt(sp, lro,
7542 skb, tcp_len);
7543 goto aggregate;
7544 }
7545 case 4: /* Flush session */
7546 {
7547 lro_append_pkt(sp, lro,
7548 skb, tcp_len);
cdb5bf02
SH		 7549 queue_rx_frame(lro->parent,
7550 lro->vlan_tag);
7d3d0439
RA		 7551 clear_lro_session(lro);
7552 sp->mac_control.stats_info->
7553 sw_stat.flush_max_pkts++;
7554 goto aggregate;
7555 }
7556 case 2: /* Flush both */
7557 lro->parent->data_len =
7558 lro->frags_len;
7559 sp->mac_control.stats_info->
7560 sw_stat.sending_both++;
cdb5bf02
SH		 7561 queue_rx_frame(lro->parent,
7562 lro->vlan_tag);
7d3d0439
RA		 7563 clear_lro_session(lro);
7564 goto send_up;
7565 case 0: /* sessions exceeded */
c92ca04b
AR		 7566 case -1: /* non-TCP or not
7567 * L2 aggregatable
7568 */
7d3d0439
RA		 7569 case 5: /*
7570 * First pkt in session not
7571 * L3/L4 aggregatable
7572 */
7573 break;
7574 default:
7575 DBG_PRINT(ERR_DBG,
7576 "%s: Samadhana!!\n",
7577 __FUNCTION__);
7578 BUG();
7579 }
7580 }
1da177e4 7581 } else {
20346722 7582 /*
7583 * Packet with erroneous checksum, let the
1da177e4
LT		 7584 * upper layers deal with it.
7585 */
7586 skb->ip_summed = CHECKSUM_NONE;
7587 }
cdb5bf02 7588 } else
1da177e4 7589 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7590
491976b2 7591 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7592send_up:
cdb5bf02 7593 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
1da177e4 7594 dev->last_rx = jiffies;
7d3d0439 7595aggregate:
1da177e4 7596 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 7597 return SUCCESS;
7598}
7599
7600/**
7601 * s2io_link - stops/starts the Tx queue.
7602 * @sp : private member of the device structure, which is a pointer to the
7603 * s2io_nic structure.
7604 * @link : inidicates whether link is UP/DOWN.
7605 * Description:
7606 * This function stops/starts the Tx queue depending on whether the link
20346722 7607 * status of the NIC is is down or up. This is called by the Alarm
7608 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7609 * Return value:
7610 * void.
7611 */
7612
1ee6dd77 7613static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7614{
7615 struct net_device *dev = (struct net_device *) sp->dev;
7616
7617 if (link != sp->last_link_state) {
b7c5678f 7618 init_tti(sp, link);
1da177e4
LT		 7619 if (link == LINK_DOWN) {
7620 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7621 s2io_stop_all_tx_queue(sp);
1da177e4 7622 netif_carrier_off(dev);
491976b2 7623 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7624 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7625 jiffies - sp->start_time;
7626 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7627 } else {
7628 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7629 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7630 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7631 jiffies - sp->start_time;
7632 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7633 netif_carrier_on(dev);
3a3d5756 7634 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7635 }
7636 }
7637 sp->last_link_state = link;
491976b2 7638 sp->start_time = jiffies;
1da177e4
LT		 7639}
7640
20346722 7641/**
7642 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7643 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7644 * s2io_nic structure.
7645 * Description:
7646 * This function initializes a few of the PCI and PCI-X configuration registers
7647 * with recommended values.
7648 * Return value:
7649 * void
7650 */
7651
1ee6dd77 7652static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7653{
20346722 7654 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7655
7656 /* Enable Data Parity Error Recovery in PCI-X command register. */
7657 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7658 &(pcix_cmd));
1da177e4 7659 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7660 (pcix_cmd | 1));
1da177e4 7661 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7662 &(pcix_cmd));
1da177e4
LT		 7663
7664 /* Set the PErr Response bit in PCI command register. */
7665 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7666 pci_write_config_word(sp->pdev, PCI_COMMAND,
7667 (pci_cmd | PCI_COMMAND_PARITY));
7668 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7669}
7670
3a3d5756
SH		 7671static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7672 u8 *dev_multiq)
9dc737a7 7673{
2fda096d 7674 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7675 (tx_fifo_num < 1)) {
2fda096d
SR		 7676 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7677 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7678
7679 if (tx_fifo_num < 1)
7680 tx_fifo_num = 1;
7681 else
7682 tx_fifo_num = MAX_TX_FIFOS;
7683
2fda096d
SR		 7684 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7685 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7686 }
2fda096d 7687
3a3d5756
SH		 7688#ifndef CONFIG_NETDEVICES_MULTIQUEUE
7689 if (multiq) {
7690 DBG_PRINT(ERR_DBG, "s2io: Multiqueue support not enabled\n");
7691 multiq = 0;
7692 }
7693#endif
6cfc482b 7694 if (multiq)
3a3d5756 7695 *dev_multiq = multiq;
6cfc482b
SH		 7696
7697 if (tx_steering_type && (1 == tx_fifo_num)) {
7698 if (tx_steering_type != TX_DEFAULT_STEERING)
7699 DBG_PRINT(ERR_DBG,
7700 "s2io: Tx steering is not supported with "
7701 "one fifo. Disabling Tx steering.\n");
7702 tx_steering_type = NO_STEERING;
7703 }
7704
7705 if ((tx_steering_type < NO_STEERING) ||
7706 (tx_steering_type > TX_DEFAULT_STEERING)) {
7707 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7708 "supported\n");
7709 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7710 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7711 }
7712
9dc737a7
AR		 7713 if ( rx_ring_num > 8) {
7714 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7715 "supported\n");
7716 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7717 rx_ring_num = 8;
7718 }
db874e65
SS		 7719 if (*dev_intr_type != INTA)
7720 napi = 0;
7721
eccb8628 7722 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7723 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7724 "Defaulting to INTA\n");
7725 *dev_intr_type = INTA;
7726 }
596c5c97 7727
9dc737a7
AR		 7728 if ((*dev_intr_type == MSI_X) &&
7729 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7730 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7731 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7732 "Defaulting to INTA\n");
7733 *dev_intr_type = INTA;
7734 }
fb6a825b 7735
6d517a27 7736 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7737 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7738 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7739 rx_ring_mode = 1;
9dc737a7
AR		 7740 }
7741 return SUCCESS;
7742}
7743
9fc93a41
SS		 7744/**
7745 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7746 * or Traffic class respectively.
b7c5678f 7747 * @nic: device private variable
9fc93a41
SS		 7748 * Description: The function configures the receive steering to
7749 * desired receive ring.
7750 * Return Value: SUCCESS on success and
7751 * '-1' on failure (endian settings incorrect).
7752 */
7753static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7754{
7755 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7756 register u64 val64 = 0;
7757
7758 if (ds_codepoint > 63)
7759 return FAILURE;
7760
7761 val64 = RTS_DS_MEM_DATA(ring);
7762 writeq(val64, &bar0->rts_ds_mem_data);
7763
7764 val64 = RTS_DS_MEM_CTRL_WE |
7765 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7766 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7767
7768 writeq(val64, &bar0->rts_ds_mem_ctrl);
7769
7770 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7771 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7772 S2IO_BIT_RESET);
7773}
7774
1da177e4 7775/**
20346722 7776 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7777 * @pdev : structure containing the PCI related information of the device.
7778 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7779 * Description:
7780 * The function initializes an adapter identified by the pci_dec structure.
20346722 7781 * All OS related initialization including memory and device structure and
7782 * initlaization of the device private variable is done. Also the swapper
7783 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7784 * registers of the device.
7785 * Return value:
7786 * returns 0 on success and negative on failure.
7787 */
7788
7789static int __devinit
7790s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7791{
1ee6dd77 7792 struct s2io_nic *sp;
1da177e4 7793 struct net_device *dev;
1da177e4
LT		 7794 int i, j, ret;
7795 int dma_flag = FALSE;
7796 u32 mac_up, mac_down;
7797 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7798 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7799 u16 subid;
1ee6dd77 7800 struct mac_info *mac_control;
1da177e4 7801 struct config_param *config;
541ae68f 7802 int mode;
cc6e7c44 7803 u8 dev_intr_type = intr_type;
3a3d5756 7804 u8 dev_multiq = 0;
0795af57 7805 DECLARE_MAC_BUF(mac);
1da177e4 7806
3a3d5756
SH		 7807 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7808 if (ret)
9dc737a7 7809 return ret;
1da177e4
LT		 7810
7811 if ((ret = pci_enable_device(pdev))) {
7812 DBG_PRINT(ERR_DBG,
7813 "s2io_init_nic: pci_enable_device failed\n");
7814 return ret;
7815 }
7816
1e7f0bd8 7817 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7818 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7819 dma_flag = TRUE;
1da177e4 7820 if (pci_set_consistent_dma_mask
1e7f0bd8 7821 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7822 DBG_PRINT(ERR_DBG,
7823 "Unable to obtain 64bit DMA for \
7824 consistent allocations\n");
7825 pci_disable_device(pdev);
7826 return -ENOMEM;
7827 }
1e7f0bd8 7828 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7829 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7830 } else {
7831 pci_disable_device(pdev);
7832 return -ENOMEM;
7833 }
eccb8628
VP		 7834 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7835 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7836 pci_disable_device(pdev);
7837 return -ENODEV;
1da177e4 7838 }
3a3d5756
SH		 7839#ifdef CONFIG_NETDEVICES_MULTIQUEUE
7840 if (dev_multiq)
6cfc482b 7841 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756
SH		 7842 else
7843#endif
1ee6dd77 7844 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7845 if (dev == NULL) {
7846 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7847 pci_disable_device(pdev);
7848 pci_release_regions(pdev);
7849 return -ENODEV;
7850 }
7851
7852 pci_set_master(pdev);
7853 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7854 SET_NETDEV_DEV(dev, &pdev->dev);
7855
7856 /* Private member variable initialized to s2io NIC structure */
7857 sp = dev->priv;
1ee6dd77 7858 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7859 sp->dev = dev;
7860 sp->pdev = pdev;
1da177e4 7861 sp->high_dma_flag = dma_flag;
1da177e4 7862 sp->device_enabled_once = FALSE;
da6971d8
AR		 7863 if (rx_ring_mode == 1)
7864 sp->rxd_mode = RXD_MODE_1;
7865 if (rx_ring_mode == 2)
7866 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7867
eaae7f72 7868 sp->config.intr_type = dev_intr_type;
1da177e4 7869
541ae68f 7870 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7871 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7872 sp->device_type = XFRAME_II_DEVICE;
7873 else
7874 sp->device_type = XFRAME_I_DEVICE;
7875
43b7c451 7876 sp->lro = lro_enable;
6aa20a22 7877
1da177e4
LT		 7878 /* Initialize some PCI/PCI-X fields of the NIC. */
7879 s2io_init_pci(sp);
7880
20346722 7881 /*
1da177e4 7882 * Setting the device configuration parameters.
20346722 7883 * Most of these parameters can be specified by the user during
7884 * module insertion as they are module loadable parameters. If
7885 * these parameters are not not specified during load time, they
1da177e4
LT		 7886 * are initialized with default values.
7887 */
7888 mac_control = &sp->mac_control;
7889 config = &sp->config;
7890
596c5c97 7891 config->napi = napi;
6cfc482b 7892 config->tx_steering_type = tx_steering_type;
596c5c97 7893
1da177e4 7894 /* Tx side parameters. */
6cfc482b
SH		 7895 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7896 config->tx_fifo_num = MAX_TX_FIFOS;
7897 else
7898 config->tx_fifo_num = tx_fifo_num;
7899
7900 /* Initialize the fifos used for tx steering */
7901 if (config->tx_fifo_num < 5) {
7902 if (config->tx_fifo_num == 1)
7903 sp->total_tcp_fifos = 1;
7904 else
7905 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7906 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7907 sp->total_udp_fifos = 1;
7908 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7909 } else {
7910 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7911 FIFO_OTHER_MAX_NUM);
7912 sp->udp_fifo_idx = sp->total_tcp_fifos;
7913 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7914 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7915 }
7916
3a3d5756 7917 config->multiq = dev_multiq;
6cfc482b 7918 for (i = 0; i < config->tx_fifo_num; i++) {
1da177e4
LT		 7919 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7920 config->tx_cfg[i].fifo_priority = i;
7921 }
7922
20346722 7923 /* mapping the QoS priority to the configured fifos */
7924 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7925 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7926
6cfc482b
SH		 7927 /* map the hashing selector table to the configured fifos */
7928 for (i = 0; i < config->tx_fifo_num; i++)
7929 sp->fifo_selector[i] = fifo_selector[i];
7930
7931
1da177e4
LT		 7932 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7933 for (i = 0; i < config->tx_fifo_num; i++) {
7934 config->tx_cfg[i].f_no_snoop =
7935 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7936 if (config->tx_cfg[i].fifo_len < 65) {
7937 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7938 break;
7939 }
7940 }
fed5eccd
AR		 7941 /* + 2 because one Txd for skb->data and one Txd for UFO */
7942 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7943
7944 /* Rx side parameters. */
1da177e4
LT		 7945 config->rx_ring_num = rx_ring_num;
7946 for (i = 0; i < MAX_RX_RINGS; i++) {
7947 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7948 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7949 config->rx_cfg[i].ring_priority = i;
7950 }
7951
7952 for (i = 0; i < rx_ring_num; i++) {
7953 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7954 config->rx_cfg[i].f_no_snoop =
7955 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7956 }
7957
7958 /* Setting Mac Control parameters */
7959 mac_control->rmac_pause_time = rmac_pause_time;
7960 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7961 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7962
7963
7964 /* Initialize Ring buffer parameters. */
7965 for (i = 0; i < config->rx_ring_num; i++)
7966 atomic_set(&sp->rx_bufs_left[i], 0);
7967
7968 /* initialize the shared memory used by the NIC and the host */
7969 if (init_shared_mem(sp)) {
7970 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7971 dev->name);
1da177e4
LT		 7972 ret = -ENOMEM;
7973 goto mem_alloc_failed;
7974 }
7975
7976 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7977 pci_resource_len(pdev, 0));
7978 if (!sp->bar0) {
19a60522 7979 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7980 dev->name);
7981 ret = -ENOMEM;
7982 goto bar0_remap_failed;
7983 }
7984
7985 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7986 pci_resource_len(pdev, 2));
7987 if (!sp->bar1) {
19a60522 7988 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7989 dev->name);
7990 ret = -ENOMEM;
7991 goto bar1_remap_failed;
7992 }
7993
7994 dev->irq = pdev->irq;
7995 dev->base_addr = (unsigned long) sp->bar0;
7996
7997 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7998 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7999 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 8000 (sp->bar1 + (j * 0x00020000));
8001 }
8002
8003 /* Driver entry points */
8004 dev->open = &s2io_open;
8005 dev->stop = &s2io_close;
8006 dev->hard_start_xmit = &s2io_xmit;
8007 dev->get_stats = &s2io_get_stats;
8008 dev->set_multicast_list = &s2io_set_multicast;
8009 dev->do_ioctl = &s2io_ioctl;
2fd37688 8010 dev->set_mac_address = &s2io_set_mac_addr;
1da177e4
LT		 8011 dev->change_mtu = &s2io_change_mtu;
8012 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8013 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8014 dev->vlan_rx_register = s2io_vlan_rx_register;
cdb5bf02 8015 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 8016
1da177e4
LT		 8017 /*
8018 * will use eth_mac_addr() for dev->set_mac_address
8019 * mac address will be set every time dev->open() is called
8020 */
bea3348e 8021 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
1da177e4 8022
612eff0e
BH		 8023#ifdef CONFIG_NET_POLL_CONTROLLER
8024 dev->poll_controller = s2io_netpoll;
8025#endif
8026
1da177e4
LT		 8027 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
8028 if (sp->high_dma_flag == TRUE)
8029 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8030 dev->features |= NETIF_F_TSO;
f83ef8c0 8031 dev->features |= NETIF_F_TSO6;
db874e65 8032 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8033 dev->features |= NETIF_F_UFO;
8034 dev->features |= NETIF_F_HW_CSUM;
8035 }
3a3d5756
SH		 8036#ifdef CONFIG_NETDEVICES_MULTIQUEUE
8037 if (config->multiq)
8038 dev->features |= NETIF_F_MULTI_QUEUE;
8039#endif
1da177e4
LT		 8040 dev->tx_timeout = &s2io_tx_watchdog;
8041 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8042 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8043 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8044
e960fc5c 8045 pci_save_state(sp->pdev);
1da177e4
LT		 8046
8047 /* Setting swapper control on the NIC, for proper reset operation */
8048 if (s2io_set_swapper(sp)) {
8049 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
8050 dev->name);
8051 ret = -EAGAIN;
8052 goto set_swap_failed;
8053 }
8054
541ae68f 8055 /* Verify if the Herc works on the slot its placed into */
8056 if (sp->device_type & XFRAME_II_DEVICE) {
8057 mode = s2io_verify_pci_mode(sp);
8058 if (mode < 0) {
8059 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
8060 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8061 ret = -EBADSLT;
8062 goto set_swap_failed;
8063 }
8064 }
8065
8066 /* Not needed for Herc */
8067 if (sp->device_type & XFRAME_I_DEVICE) {
8068 /*
8069 * Fix for all "FFs" MAC address problems observed on
8070 * Alpha platforms
8071 */
8072 fix_mac_address(sp);
8073 s2io_reset(sp);
8074 }
1da177e4
LT		 8075
8076 /*
1da177e4
LT		 8077 * MAC address initialization.
8078 * For now only one mac address will be read and used.
8079 */
8080 bar0 = sp->bar0;
8081 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 8082 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8083 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8084 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 8085 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 8086 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8087 mac_down = (u32) tmp64;
8088 mac_up = (u32) (tmp64 >> 32);
8089
1da177e4
LT		 8090 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8091 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8092 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8093 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8094 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8095 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8096
1da177e4
LT		 8097 /* Set the factory defined MAC address initially */
8098 dev->addr_len = ETH_ALEN;
8099 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8100 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8101
faa4f796
SH		 8102 /* initialize number of multicast & unicast MAC entries variables */
8103 if (sp->device_type == XFRAME_I_DEVICE) {
8104 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8105 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8106 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8107 } else if (sp->device_type == XFRAME_II_DEVICE) {
8108 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8109 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8110 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8111 }
8112
8113 /* store mac addresses from CAM to s2io_nic structure */
8114 do_s2io_store_unicast_mc(sp);
8115
c77dd43e
SS		 8116 /* Store the values of the MSIX table in the s2io_nic structure */
8117 store_xmsi_data(sp);
b41477f3
AR		 8118 /* reset Nic and bring it to known state */
8119 s2io_reset(sp);
8120
1da177e4 8121 /*
20346722 8122 * Initialize the tasklet status and link state flags
541ae68f 8123 * and the card state parameter
1da177e4 8124 */
1da177e4 8125 sp->tasklet_status = 0;
92b84437 8126 sp->state = 0;
1da177e4 8127
1da177e4 8128 /* Initialize spinlocks */
2fda096d
SR		 8129 for (i = 0; i < sp->config.tx_fifo_num; i++)
8130 spin_lock_init(&mac_control->fifos[i].tx_lock);
db874e65
SS		 8131
8132 if (!napi)
8133 spin_lock_init(&sp->put_lock);
7ba013ac 8134 spin_lock_init(&sp->rx_lock);
1da177e4 8135
20346722 8136 /*
8137 * SXE-002: Configure link and activity LED to init state
8138 * on driver load.
1da177e4
LT		 8139 */
8140 subid = sp->pdev->subsystem_device;
8141 if ((subid & 0xFF) >= 0x07) {
8142 val64 = readq(&bar0->gpio_control);
8143 val64 |= 0x0000800000000000ULL;
8144 writeq(val64, &bar0->gpio_control);
8145 val64 = 0x0411040400000000ULL;
8146 writeq(val64, (void __iomem *) bar0 + 0x2700);
8147 val64 = readq(&bar0->gpio_control);
8148 }
8149
8150 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8151
8152 if (register_netdev(dev)) {
8153 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8154 ret = -ENODEV;
8155 goto register_failed;
8156 }
9dc737a7 8157 s2io_vpd_read(sp);
0c61ed5f 8158 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8159 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8160 sp->product_name, pdev->revision);
b41477f3
AR		 8161 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8162 s2io_driver_version);
0795af57
JP		 8163 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
8164 dev->name, print_mac(mac, dev->dev_addr));
19a60522 8165 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8166 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8167 mode = s2io_print_pci_mode(sp);
541ae68f 8168 if (mode < 0) {
9dc737a7 8169 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8170 ret = -EBADSLT;
9dc737a7 8171 unregister_netdev(dev);
541ae68f 8172 goto set_swap_failed;
8173 }
541ae68f 8174 }
9dc737a7
AR		 8175 switch(sp->rxd_mode) {
8176 case RXD_MODE_1:
8177 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8178 dev->name);
8179 break;
8180 case RXD_MODE_3B:
8181 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8182 dev->name);
8183 break;
9dc737a7 8184 }
db874e65
SS		 8185
8186 if (napi)
8187 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
3a3d5756
SH		 8188
8189 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8190 sp->config.tx_fifo_num);
8191
eaae7f72 8192 switch(sp->config.intr_type) {
9dc737a7
AR		 8193 case INTA:
8194 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8195 break;
9dc737a7
AR		 8196 case MSI_X:
8197 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8198 break;
8199 }
3a3d5756
SH		 8200 if (sp->config.multiq) {
8201 for (i = 0; i < sp->config.tx_fifo_num; i++)
8202 mac_control->fifos[i].multiq = config->multiq;
8203 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8204 dev->name);
8205 } else
8206 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8207 dev->name);
8208
6cfc482b
SH		 8209 switch (sp->config.tx_steering_type) {
8210 case NO_STEERING:
8211 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8212 " transmit\n", dev->name);
8213 break;
8214 case TX_PRIORITY_STEERING:
8215 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8216 " transmit\n", dev->name);
8217 break;
8218 case TX_DEFAULT_STEERING:
8219 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8220 " transmit\n", dev->name);
8221 }
8222
7d3d0439
RA		 8223 if (sp->lro)
8224 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8225 dev->name);
db874e65
SS		 8226 if (ufo)
8227 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8228 " enabled\n", dev->name);
7ba013ac 8229 /* Initialize device name */
9dc737a7 8230 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8231
20346722 8232 /*
8233 * Make Link state as off at this point, when the Link change
8234 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8235 * the right state.
8236 */
8237 netif_carrier_off(dev);
1da177e4
LT		 8238
8239 return 0;
8240
8241 register_failed:
8242 set_swap_failed:
8243 iounmap(sp->bar1);
8244 bar1_remap_failed:
8245 iounmap(sp->bar0);
8246 bar0_remap_failed:
8247 mem_alloc_failed:
8248 free_shared_mem(sp);
8249 pci_disable_device(pdev);
eccb8628 8250 pci_release_regions(pdev);
1da177e4
LT		 8251 pci_set_drvdata(pdev, NULL);
8252 free_netdev(dev);
8253
8254 return ret;
8255}
8256
8257/**
20346722 8258 * s2io_rem_nic - Free the PCI device
1da177e4 8259 * @pdev: structure containing the PCI related information of the device.
20346722 8260 * Description: This function is called by the Pci subsystem to release a
1da177e4 8261 * PCI device and free up all resource held up by the device. This could
20346722 8262 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8263 * from memory.
8264 */
8265
8266static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8267{
8268 struct net_device *dev =
8269 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8270 struct s2io_nic *sp;
1da177e4
LT		 8271
8272 if (dev == NULL) {
8273 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8274 return;
8275 }
8276
22747d6b
FR		 8277 flush_scheduled_work();
8278
1da177e4
LT		 8279 sp = dev->priv;
8280 unregister_netdev(dev);
8281
8282 free_shared_mem(sp);
8283 iounmap(sp->bar0);
8284 iounmap(sp->bar1);
eccb8628 8285 pci_release_regions(pdev);
1da177e4 8286 pci_set_drvdata(pdev, NULL);
1da177e4 8287 free_netdev(dev);
19a60522 8288 pci_disable_device(pdev);
1da177e4
LT		 8289}
8290
8291/**
8292 * s2io_starter - Entry point for the driver
8293 * Description: This function is the entry point for the driver. It verifies
8294 * the module loadable parameters and initializes PCI configuration space.
8295 */
8296
43b7c451 8297static int __init s2io_starter(void)
1da177e4 8298{
29917620 8299 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8300}
8301
8302/**
20346722 8303 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8304 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8305 */
8306
372cc597 8307static __exit void s2io_closer(void)
1da177e4
LT		 8308{
8309 pci_unregister_driver(&s2io_driver);
8310 DBG_PRINT(INIT_DBG, "cleanup done\n");
8311}
8312
8313module_init(s2io_starter);
8314module_exit(s2io_closer);
7d3d0439 8315
6aa20a22 8316static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8317 struct tcphdr **tcp, struct RxD_t *rxdp,
8318 struct s2io_nic *sp)
7d3d0439
RA		 8319{
8320 int ip_off;
8321 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8322
8323 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8324 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8325 __FUNCTION__);
8326 return -1;
8327 }
8328
cdb5bf02
SH		 8329 /* Checking for DIX type or DIX type with VLAN */
8330 if ((l2_type == 0)
8331 || (l2_type == 4)) {
8332 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8333 /*
8334 * If vlan stripping is disabled and the frame is VLAN tagged,
8335 * shift the offset by the VLAN header size bytes.
8336 */
8337 if ((!vlan_strip_flag) &&
8338 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8339 ip_off += HEADER_VLAN_SIZE;
8340 } else {
7d3d0439 8341 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8342 return -1;
7d3d0439
RA		 8343 }
8344
8345 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8346 ip_len = (u8)((*ip)->ihl);
8347 ip_len <<= 2;
8348 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8349
8350 return 0;
8351}
8352
1ee6dd77 8353static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8354 struct tcphdr *tcp)
8355{
8356 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8357 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8358 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8359 return -1;
8360 return 0;
8361}
8362
8363static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8364{
8365 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8366}
8367
1ee6dd77 8368static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8369 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439
RA		 8370{
8371 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8372 lro->l2h = l2h;
8373 lro->iph = ip;
8374 lro->tcph = tcp;
8375 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8376 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8377 lro->sg_num = 1;
8378 lro->total_len = ntohs(ip->tot_len);
8379 lro->frags_len = 0;
cdb5bf02 8380 lro->vlan_tag = vlan_tag;
6aa20a22 8381 /*
7d3d0439
RA		 8382 * check if we saw TCP timestamp. Other consistency checks have
8383 * already been done.
8384 */
8385 if (tcp->doff == 8) {
c8855953
SR		 8386 __be32 *ptr;
8387 ptr = (__be32 *)(tcp+1);
7d3d0439 8388 lro->saw_ts = 1;
c8855953 8389 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8390 lro->cur_tsecr = *(ptr+2);
8391 }
8392 lro->in_use = 1;
8393}
8394
1ee6dd77 8395static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8396{
8397 struct iphdr *ip = lro->iph;
8398 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8399 __sum16 nchk;
1ee6dd77 8400 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 8401 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8402
8403 /* Update L3 header */
8404 ip->tot_len = htons(lro->total_len);
8405 ip->check = 0;
8406 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8407 ip->check = nchk;
8408
8409 /* Update L4 header */
8410 tcp->ack_seq = lro->tcp_ack;
8411 tcp->window = lro->window;
8412
8413 /* Update tsecr field if this session has timestamps enabled */
8414 if (lro->saw_ts) {
c8855953 8415 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8416 *(ptr+2) = lro->cur_tsecr;
8417 }
8418
8419 /* Update counters required for calculation of
8420 * average no. of packets aggregated.
8421 */
8422 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8423 statinfo->sw_stat.num_aggregations++;
8424}
8425
1ee6dd77 8426static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8427 struct tcphdr *tcp, u32 l4_pyld)
8428{
8429 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8430 lro->total_len += l4_pyld;
8431 lro->frags_len += l4_pyld;
8432 lro->tcp_next_seq += l4_pyld;
8433 lro->sg_num++;
8434
8435 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8436 lro->tcp_ack = tcp->ack_seq;
8437 lro->window = tcp->window;
6aa20a22 8438
7d3d0439 8439 if (lro->saw_ts) {
c8855953 8440 __be32 *ptr;
7d3d0439 8441 /* Update tsecr and tsval from this packet */
c8855953
SR		 8442 ptr = (__be32 *)(tcp+1);
8443 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8444 lro->cur_tsecr = *(ptr + 2);
8445 }
8446}
8447
1ee6dd77 8448static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8449 struct tcphdr *tcp, u32 tcp_pyld_len)
8450{
7d3d0439
RA		 8451 u8 *ptr;
8452
79dc1901
AM		 8453 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8454
7d3d0439
RA		 8455 if (!tcp_pyld_len) {
8456 /* Runt frame or a pure ack */
8457 return -1;
8458 }
8459
8460 if (ip->ihl != 5) /* IP has options */
8461 return -1;
8462
75c30b13
AR		 8463 /* If we see CE codepoint in IP header, packet is not mergeable */
8464 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8465 return -1;
8466
8467 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8468 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8469 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8470 /*
8471 * Currently recognize only the ack control word and
8472 * any other control field being set would result in
8473 * flushing the LRO session
8474 */
8475 return -1;
8476 }
8477
6aa20a22 8478 /*
7d3d0439
RA		 8479 * Allow only one TCP timestamp option. Don't aggregate if
8480 * any other options are detected.
8481 */
8482 if (tcp->doff != 5 && tcp->doff != 8)
8483 return -1;
8484
8485 if (tcp->doff == 8) {
6aa20a22 8486 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8487 while (*ptr == TCPOPT_NOP)
8488 ptr++;
8489 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8490 return -1;
8491
8492 /* Ensure timestamp value increases monotonically */
8493 if (l_lro)
c8855953 8494 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8495 return -1;
8496
8497 /* timestamp echo reply should be non-zero */
c8855953 8498 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8499 return -1;
8500 }
8501
8502 return 0;
8503}
8504
8505static int
1ee6dd77
RB		 8506s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8507 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8508{
8509 struct iphdr *ip;
8510 struct tcphdr *tcph;
8511 int ret = 0, i;
cdb5bf02 8512 u16 vlan_tag = 0;
7d3d0439
RA		 8513
8514 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8515 rxdp, sp))) {
7d3d0439
RA		 8516 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8517 ip->saddr, ip->daddr);
cdb5bf02 8518 } else
7d3d0439 8519 return ret;
7d3d0439 8520
cdb5bf02 8521 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8522 tcph = (struct tcphdr *)*tcp;
8523 *tcp_len = get_l4_pyld_length(ip, tcph);
8524 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8525 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8526 if (l_lro->in_use) {
8527 if (check_for_socket_match(l_lro, ip, tcph))
8528 continue;
8529 /* Sock pair matched */
8530 *lro = l_lro;
8531
8532 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8533 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8534 "0x%x, actual 0x%x\n", __FUNCTION__,
8535 (*lro)->tcp_next_seq,
8536 ntohl(tcph->seq));
8537
8538 sp->mac_control.stats_info->
8539 sw_stat.outof_sequence_pkts++;
8540 ret = 2;
8541 break;
8542 }
8543
8544 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8545 ret = 1; /* Aggregate */
8546 else
8547 ret = 2; /* Flush both */
8548 break;
8549 }
8550 }
8551
8552 if (ret == 0) {
8553 /* Before searching for available LRO objects,
8554 * check if the pkt is L3/L4 aggregatable. If not
8555 * don't create new LRO session. Just send this
8556 * packet up.
8557 */
8558 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8559 return 5;
8560 }
8561
8562 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8563 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8564 if (!(l_lro->in_use)) {
8565 *lro = l_lro;
8566 ret = 3; /* Begin anew */
8567 break;
8568 }
8569 }
8570 }
8571
8572 if (ret == 0) { /* sessions exceeded */
8573 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8574 __FUNCTION__);
8575 *lro = NULL;
8576 return ret;
8577 }
8578
8579 switch (ret) {
8580 case 3:
cdb5bf02
SH		 8581 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8582 vlan_tag);
7d3d0439
RA		 8583 break;
8584 case 2:
8585 update_L3L4_header(sp, *lro);
8586 break;
8587 case 1:
8588 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8589 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8590 update_L3L4_header(sp, *lro);
8591 ret = 4; /* Flush the LRO */
8592 }
8593 break;
8594 default:
8595 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8596 __FUNCTION__);
8597 break;
8598 }
8599
8600 return ret;
8601}
8602
1ee6dd77 8603static void clear_lro_session(struct lro *lro)
7d3d0439 8604{
1ee6dd77 8605 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8606
8607 memset(lro, 0, lro_struct_size);
8608}
8609
cdb5bf02 8610static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8611{
8612 struct net_device *dev = skb->dev;
cdb5bf02 8613 struct s2io_nic *sp = dev->priv;
7d3d0439
RA		 8614
8615 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02
SH		 8616 if (sp->vlgrp && vlan_tag
8617 && (vlan_strip_flag)) {
8618 /* Queueing the vlan frame to the upper layer */
8619 if (sp->config.napi)
8620 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8621 else
8622 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8623 } else {
8624 if (sp->config.napi)
8625 netif_receive_skb(skb);
8626 else
8627 netif_rx(skb);
8628 }
7d3d0439
RA		 8629}
8630
1ee6dd77
RB		 8631static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8632 struct sk_buff *skb,
7d3d0439
RA		 8633 u32 tcp_len)
8634{
75c30b13 8635 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8636
8637 first->len += tcp_len;
8638 first->data_len = lro->frags_len;
8639 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8640 if (skb_shinfo(first)->frag_list)
8641 lro->last_frag->next = skb;
7d3d0439
RA		 8642 else
8643 skb_shinfo(first)->frag_list = skb;
372cc597 8644 first->truesize += skb->truesize;
75c30b13 8645 lro->last_frag = skb;
7d3d0439
RA		 8646 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8647 return;
8648}
d796fdb7
LV		 8649
8650/**
8651 * s2io_io_error_detected - called when PCI error is detected
8652 * @pdev: Pointer to PCI device
8453d43f 8653 * @state: The current pci connection state
d796fdb7
LV		 8654 *
8655 * This function is called after a PCI bus error affecting
8656 * this device has been detected.
8657 */
8658static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8659 pci_channel_state_t state)
8660{
8661 struct net_device *netdev = pci_get_drvdata(pdev);
8662 struct s2io_nic *sp = netdev->priv;
8663
8664 netif_device_detach(netdev);
8665
8666 if (netif_running(netdev)) {
8667 /* Bring down the card, while avoiding PCI I/O */
8668 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8669 }
8670 pci_disable_device(pdev);
8671
8672 return PCI_ERS_RESULT_NEED_RESET;
8673}
8674
8675/**
8676 * s2io_io_slot_reset - called after the pci bus has been reset.
8677 * @pdev: Pointer to PCI device
8678 *
8679 * Restart the card from scratch, as if from a cold-boot.
8680 * At this point, the card has exprienced a hard reset,
8681 * followed by fixups by BIOS, and has its config space
8682 * set up identically to what it was at cold boot.
8683 */
8684static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8685{
8686 struct net_device *netdev = pci_get_drvdata(pdev);
8687 struct s2io_nic *sp = netdev->priv;
8688
8689 if (pci_enable_device(pdev)) {
8690 printk(KERN_ERR "s2io: "
8691 "Cannot re-enable PCI device after reset.\n");
8692 return PCI_ERS_RESULT_DISCONNECT;
8693 }
8694
8695 pci_set_master(pdev);
8696 s2io_reset(sp);
8697
8698 return PCI_ERS_RESULT_RECOVERED;
8699}
8700
8701/**
8702 * s2io_io_resume - called when traffic can start flowing again.
8703 * @pdev: Pointer to PCI device
8704 *
8705 * This callback is called when the error recovery driver tells
8706 * us that its OK to resume normal operation.
8707 */
8708static void s2io_io_resume(struct pci_dev *pdev)
8709{
8710 struct net_device *netdev = pci_get_drvdata(pdev);
8711 struct s2io_nic *sp = netdev->priv;
8712
8713 if (netif_running(netdev)) {
8714 if (s2io_card_up(sp)) {
8715 printk(KERN_ERR "s2io: "
8716 "Can't bring device back up after reset.\n");
8717 return;
8718 }
8719
8720 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8721 s2io_card_down(sp);
8722 printk(KERN_ERR "s2io: "
8723 "Can't resetore mac addr after reset.\n");
8724 return;
8725 }
8726 }
8727
8728 netif_device_attach(netdev);
8729 netif_wake_queue(netdev);
8730}
Linux kernel - Deliverables
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