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s2io bogus memset
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
1da177e4
LT		 3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8
AR		 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7
AR		 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
1da177e4
LT		 45 ************************************************************************/
46
1da177e4
LT		 47#include <linux/module.h>
48#include <linux/types.h>
49#include <linux/errno.h>
50#include <linux/ioport.h>
51#include <linux/pci.h>
1e7f0bd8 52#include <linux/dma-mapping.h>
1da177e4
LT		 53#include <linux/kernel.h>
54#include <linux/netdevice.h>
55#include <linux/etherdevice.h>
56#include <linux/skbuff.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/stddef.h>
60#include <linux/ioctl.h>
61#include <linux/timex.h>
62#include <linux/sched.h>
63#include <linux/ethtool.h>
1da177e4 64#include <linux/workqueue.h>
be3a6b02 65#include <linux/if_vlan.h>
7d3d0439
RA		 66#include <linux/ip.h>
67#include <linux/tcp.h>
68#include <net/tcp.h>
1da177e4 69
1da177e4
LT		 70#include <asm/system.h>
71#include <asm/uaccess.h>
20346722 72#include <asm/io.h>
fe931395 73#include <asm/div64.h>
330ce0de 74#include <asm/irq.h>
1da177e4
LT		 75
76/* local include */
77#include "s2io.h"
78#include "s2io-regs.h"
79
75c30b13 80#define DRV_VERSION "2.0.15.2"
6c1792f4 81
1da177e4 82/* S2io Driver name & version. */
20346722 83static char s2io_driver_name[] = "Neterion";
6c1792f4 84static char s2io_driver_version[] = DRV_VERSION;
1da177e4 85
26df54bf
AB		 86static int rxd_size[4] = {32,48,48,64};
87static int rxd_count[4] = {127,85,85,63};
da6971d8 88
5e25b9dd 89static inline int RXD_IS_UP2DT(RxD_t *rxdp)
90{
91 int ret;
92
93 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
94 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
95
96 return ret;
97}
98
20346722 99/*
1da177e4
LT		 100 * Cards with following subsystem_id have a link state indication
101 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
102 * macro below identifies these cards given the subsystem_id.
103 */
541ae68f 104#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
105 (dev_type == XFRAME_I_DEVICE) ? \
106 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
107 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 108
109#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
110 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
111#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
112#define PANIC 1
113#define LOW 2
114static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
115{
20346722 116 mac_info_t *mac_control;
117
118 mac_control = &sp->mac_control;
863c11a9
AR		 119 if (rxb_size <= rxd_count[sp->rxd_mode])
120 return PANIC;
121 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
122 return LOW;
123 return 0;
1da177e4
LT		 124}
125
126/* Ethtool related variables and Macros. */
127static char s2io_gstrings[][ETH_GSTRING_LEN] = {
128 "Register test\t(offline)",
129 "Eeprom test\t(offline)",
130 "Link test\t(online)",
131 "RLDRAM test\t(offline)",
132 "BIST Test\t(offline)"
133};
134
135static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
136 {"tmac_frms"},
137 {"tmac_data_octets"},
138 {"tmac_drop_frms"},
139 {"tmac_mcst_frms"},
140 {"tmac_bcst_frms"},
141 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 142 {"tmac_ttl_octets"},
143 {"tmac_ucst_frms"},
144 {"tmac_nucst_frms"},
1da177e4 145 {"tmac_any_err_frms"},
bd1034f0 146 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 147 {"tmac_vld_ip_octets"},
148 {"tmac_vld_ip"},
149 {"tmac_drop_ip"},
150 {"tmac_icmp"},
151 {"tmac_rst_tcp"},
152 {"tmac_tcp"},
153 {"tmac_udp"},
154 {"rmac_vld_frms"},
155 {"rmac_data_octets"},
156 {"rmac_fcs_err_frms"},
157 {"rmac_drop_frms"},
158 {"rmac_vld_mcst_frms"},
159 {"rmac_vld_bcst_frms"},
160 {"rmac_in_rng_len_err_frms"},
bd1034f0 161 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 162 {"rmac_long_frms"},
163 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 164 {"rmac_unsup_ctrl_frms"},
165 {"rmac_ttl_octets"},
166 {"rmac_accepted_ucst_frms"},
167 {"rmac_accepted_nucst_frms"},
1da177e4 168 {"rmac_discarded_frms"},
bd1034f0
AR		 169 {"rmac_drop_events"},
170 {"rmac_ttl_less_fb_octets"},
171 {"rmac_ttl_frms"},
1da177e4
LT		 172 {"rmac_usized_frms"},
173 {"rmac_osized_frms"},
174 {"rmac_frag_frms"},
175 {"rmac_jabber_frms"},
bd1034f0
AR		 176 {"rmac_ttl_64_frms"},
177 {"rmac_ttl_65_127_frms"},
178 {"rmac_ttl_128_255_frms"},
179 {"rmac_ttl_256_511_frms"},
180 {"rmac_ttl_512_1023_frms"},
181 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 182 {"rmac_ip"},
183 {"rmac_ip_octets"},
184 {"rmac_hdr_err_ip"},
185 {"rmac_drop_ip"},
186 {"rmac_icmp"},
187 {"rmac_tcp"},
188 {"rmac_udp"},
189 {"rmac_err_drp_udp"},
bd1034f0
AR		 190 {"rmac_xgmii_err_sym"},
191 {"rmac_frms_q0"},
192 {"rmac_frms_q1"},
193 {"rmac_frms_q2"},
194 {"rmac_frms_q3"},
195 {"rmac_frms_q4"},
196 {"rmac_frms_q5"},
197 {"rmac_frms_q6"},
198 {"rmac_frms_q7"},
199 {"rmac_full_q0"},
200 {"rmac_full_q1"},
201 {"rmac_full_q2"},
202 {"rmac_full_q3"},
203 {"rmac_full_q4"},
204 {"rmac_full_q5"},
205 {"rmac_full_q6"},
206 {"rmac_full_q7"},
1da177e4 207 {"rmac_pause_cnt"},
bd1034f0
AR		 208 {"rmac_xgmii_data_err_cnt"},
209 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 210 {"rmac_accepted_ip"},
211 {"rmac_err_tcp"},
bd1034f0
AR		 212 {"rd_req_cnt"},
213 {"new_rd_req_cnt"},
214 {"new_rd_req_rtry_cnt"},
215 {"rd_rtry_cnt"},
216 {"wr_rtry_rd_ack_cnt"},
217 {"wr_req_cnt"},
218 {"new_wr_req_cnt"},
219 {"new_wr_req_rtry_cnt"},
220 {"wr_rtry_cnt"},
221 {"wr_disc_cnt"},
222 {"rd_rtry_wr_ack_cnt"},
223 {"txp_wr_cnt"},
224 {"txd_rd_cnt"},
225 {"txd_wr_cnt"},
226 {"rxd_rd_cnt"},
227 {"rxd_wr_cnt"},
228 {"txf_rd_cnt"},
229 {"rxf_wr_cnt"},
230 {"rmac_ttl_1519_4095_frms"},
231 {"rmac_ttl_4096_8191_frms"},
232 {"rmac_ttl_8192_max_frms"},
233 {"rmac_ttl_gt_max_frms"},
234 {"rmac_osized_alt_frms"},
235 {"rmac_jabber_alt_frms"},
236 {"rmac_gt_max_alt_frms"},
237 {"rmac_vlan_frms"},
238 {"rmac_len_discard"},
239 {"rmac_fcs_discard"},
240 {"rmac_pf_discard"},
241 {"rmac_da_discard"},
242 {"rmac_red_discard"},
243 {"rmac_rts_discard"},
244 {"rmac_ingm_full_discard"},
245 {"link_fault_cnt"},
7ba013ac 246 {"\n DRIVER STATISTICS"},
247 {"single_bit_ecc_errs"},
248 {"double_bit_ecc_errs"},
bd1034f0
AR		 249 {"parity_err_cnt"},
250 {"serious_err_cnt"},
251 {"soft_reset_cnt"},
252 {"fifo_full_cnt"},
253 {"ring_full_cnt"},
254 ("alarm_transceiver_temp_high"),
255 ("alarm_transceiver_temp_low"),
256 ("alarm_laser_bias_current_high"),
257 ("alarm_laser_bias_current_low"),
258 ("alarm_laser_output_power_high"),
259 ("alarm_laser_output_power_low"),
260 ("warn_transceiver_temp_high"),
261 ("warn_transceiver_temp_low"),
262 ("warn_laser_bias_current_high"),
263 ("warn_laser_bias_current_low"),
264 ("warn_laser_output_power_high"),
265 ("warn_laser_output_power_low"),
7d3d0439
RA		 266 ("lro_aggregated_pkts"),
267 ("lro_flush_both_count"),
268 ("lro_out_of_sequence_pkts"),
269 ("lro_flush_due_to_max_pkts"),
270 ("lro_avg_aggr_pkts"),
1da177e4
LT		 271};
272
273#define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
274#define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
275
276#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
277#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
278
25fff88e 279#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
280 init_timer(&timer); \
281 timer.function = handle; \
282 timer.data = (unsigned long) arg; \
283 mod_timer(&timer, (jiffies + exp)) \
284
be3a6b02 285/* Add the vlan */
286static void s2io_vlan_rx_register(struct net_device *dev,
287 struct vlan_group *grp)
288{
289 nic_t *nic = dev->priv;
290 unsigned long flags;
291
292 spin_lock_irqsave(&nic->tx_lock, flags);
293 nic->vlgrp = grp;
294 spin_unlock_irqrestore(&nic->tx_lock, flags);
295}
296
297/* Unregister the vlan */
298static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
299{
300 nic_t *nic = dev->priv;
301 unsigned long flags;
302
303 spin_lock_irqsave(&nic->tx_lock, flags);
304 if (nic->vlgrp)
305 nic->vlgrp->vlan_devices[vid] = NULL;
306 spin_unlock_irqrestore(&nic->tx_lock, flags);
307}
308
20346722 309/*
1da177e4
LT		 310 * Constants to be programmed into the Xena's registers, to configure
311 * the XAUI.
312 */
313
1da177e4 314#define END_SIGN 0x0
f71e1309 315static const u64 herc_act_dtx_cfg[] = {
541ae68f 316 /* Set address */
e960fc5c 317 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 318 /* Write data */
e960fc5c 319 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 320 /* Set address */
321 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
322 /* Write data */
323 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
324 /* Set address */
e960fc5c 325 0x801205150D440000ULL, 0x801205150D4400E0ULL,
326 /* Write data */
327 0x801205150D440004ULL, 0x801205150D4400E4ULL,
328 /* Set address */
541ae68f 329 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
330 /* Write data */
331 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
332 /* Done */
333 END_SIGN
334};
335
f71e1309 336static const u64 xena_dtx_cfg[] = {
c92ca04b 337 /* Set address */
1da177e4 338 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 339 /* Write data */
340 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
341 /* Set address */
342 0x8001051500000000ULL, 0x80010515000000E0ULL,
343 /* Write data */
344 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
345 /* Set address */
1da177e4 346 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 347 /* Write data */
348 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 349 END_SIGN
350};
351
20346722 352/*
1da177e4
LT		 353 * Constants for Fixing the MacAddress problem seen mostly on
354 * Alpha machines.
355 */
f71e1309 356static const u64 fix_mac[] = {
1da177e4
LT		 357 0x0060000000000000ULL, 0x0060600000000000ULL,
358 0x0040600000000000ULL, 0x0000600000000000ULL,
359 0x0020600000000000ULL, 0x0060600000000000ULL,
360 0x0020600000000000ULL, 0x0060600000000000ULL,
361 0x0020600000000000ULL, 0x0060600000000000ULL,
362 0x0020600000000000ULL, 0x0060600000000000ULL,
363 0x0020600000000000ULL, 0x0060600000000000ULL,
364 0x0020600000000000ULL, 0x0060600000000000ULL,
365 0x0020600000000000ULL, 0x0060600000000000ULL,
366 0x0020600000000000ULL, 0x0060600000000000ULL,
367 0x0020600000000000ULL, 0x0060600000000000ULL,
368 0x0020600000000000ULL, 0x0060600000000000ULL,
369 0x0020600000000000ULL, 0x0000600000000000ULL,
370 0x0040600000000000ULL, 0x0060600000000000ULL,
371 END_SIGN
372};
373
b41477f3
AR		 374MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
375MODULE_LICENSE("GPL");
376MODULE_VERSION(DRV_VERSION);
377
378
1da177e4 379/* Module Loadable parameters. */
b41477f3
AR		 380S2IO_PARM_INT(tx_fifo_num, 1);
381S2IO_PARM_INT(rx_ring_num, 1);
382
383
384S2IO_PARM_INT(rx_ring_mode, 1);
385S2IO_PARM_INT(use_continuous_tx_intrs, 1);
386S2IO_PARM_INT(rmac_pause_time, 0x100);
387S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
388S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
389S2IO_PARM_INT(shared_splits, 0);
390S2IO_PARM_INT(tmac_util_period, 5);
391S2IO_PARM_INT(rmac_util_period, 5);
392S2IO_PARM_INT(bimodal, 0);
393S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 394/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 395S2IO_PARM_INT(rxsync_frequency, 3);
cc6e7c44 396/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
b41477f3 397S2IO_PARM_INT(intr_type, 0);
7d3d0439 398/* Large receive offload feature */
b41477f3 399S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 400/* Max pkts to be aggregated by LRO at one time. If not specified,
401 * aggregation happens until we hit max IP pkt size(64K)
402 */
b41477f3
AR		 403S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
404#ifndef CONFIG_S2IO_NAPI
405S2IO_PARM_INT(indicate_max_pkts, 0);
406#endif
407
408static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
409 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
410static unsigned int rx_ring_sz[MAX_RX_RINGS] =
411 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
412static unsigned int rts_frm_len[MAX_RX_RINGS] =
413 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
414
415module_param_array(tx_fifo_len, uint, NULL, 0);
416module_param_array(rx_ring_sz, uint, NULL, 0);
417module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 418
20346722 419/*
1da177e4 420 * S2IO device table.
20346722 421 * This table lists all the devices that this driver supports.
1da177e4
LT		 422 */
423static struct pci_device_id s2io_tbl[] __devinitdata = {
424 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
425 PCI_ANY_ID, PCI_ANY_ID},
426 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
427 PCI_ANY_ID, PCI_ANY_ID},
428 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722 429 PCI_ANY_ID, PCI_ANY_ID},
430 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
431 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 432 {0,}
433};
434
435MODULE_DEVICE_TABLE(pci, s2io_tbl);
436
437static struct pci_driver s2io_driver = {
438 .name = "S2IO",
439 .id_table = s2io_tbl,
440 .probe = s2io_init_nic,
441 .remove = __devexit_p(s2io_rem_nic),
442};
443
444/* A simplifier macro used both by init and free shared_mem Fns(). */
445#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
446
447/**
448 * init_shared_mem - Allocation and Initialization of Memory
449 * @nic: Device private variable.
20346722 450 * Description: The function allocates all the memory areas shared
451 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 452 * Rx descriptors and the statistics block.
453 */
454
455static int init_shared_mem(struct s2io_nic *nic)
456{
457 u32 size;
458 void *tmp_v_addr, *tmp_v_addr_next;
459 dma_addr_t tmp_p_addr, tmp_p_addr_next;
460 RxD_block_t *pre_rxd_blk = NULL;
20346722 461 int i, j, blk_cnt, rx_sz, tx_sz;
1da177e4
LT		 462 int lst_size, lst_per_page;
463 struct net_device *dev = nic->dev;
8ae418cf 464 unsigned long tmp;
1da177e4 465 buffAdd_t *ba;
1da177e4
LT		 466
467 mac_info_t *mac_control;
468 struct config_param *config;
469
470 mac_control = &nic->mac_control;
471 config = &nic->config;
472
473
474 /* Allocation and initialization of TXDLs in FIOFs */
475 size = 0;
476 for (i = 0; i < config->tx_fifo_num; i++) {
477 size += config->tx_cfg[i].fifo_len;
478 }
479 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 480 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 481 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 482 return -EINVAL;
1da177e4
LT		 483 }
484
485 lst_size = (sizeof(TxD_t) * config->max_txds);
20346722 486 tx_sz = lst_size * size;
1da177e4
LT		 487 lst_per_page = PAGE_SIZE / lst_size;
488
489 for (i = 0; i < config->tx_fifo_num; i++) {
490 int fifo_len = config->tx_cfg[i].fifo_len;
491 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
20346722 492 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
493 GFP_KERNEL);
494 if (!mac_control->fifos[i].list_info) {
1da177e4
LT		 495 DBG_PRINT(ERR_DBG,
496 "Malloc failed for list_info\n");
497 return -ENOMEM;
498 }
20346722 499 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 500 }
501 for (i = 0; i < config->tx_fifo_num; i++) {
502 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
503 lst_per_page);
20346722 504 mac_control->fifos[i].tx_curr_put_info.offset = 0;
505 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 506 config->tx_cfg[i].fifo_len - 1;
20346722 507 mac_control->fifos[i].tx_curr_get_info.offset = 0;
508 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 509 config->tx_cfg[i].fifo_len - 1;
20346722 510 mac_control->fifos[i].fifo_no = i;
511 mac_control->fifos[i].nic = nic;
fed5eccd 512 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 513
1da177e4
LT		 514 for (j = 0; j < page_num; j++) {
515 int k = 0;
516 dma_addr_t tmp_p;
517 void *tmp_v;
518 tmp_v = pci_alloc_consistent(nic->pdev,
519 PAGE_SIZE, &tmp_p);
520 if (!tmp_v) {
521 DBG_PRINT(ERR_DBG,
522 "pci_alloc_consistent ");
523 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
524 return -ENOMEM;
525 }
776bd20f 526 /* If we got a zero DMA address(can happen on
527 * certain platforms like PPC), reallocate.
528 * Store virtual address of page we don't want,
529 * to be freed later.
530 */
531 if (!tmp_p) {
532 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 533 DBG_PRINT(INIT_DBG,
776bd20f 534 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 535 DBG_PRINT(INIT_DBG,
6b4d617d 536 "Virtual address %p\n", tmp_v);
776bd20f 537 tmp_v = pci_alloc_consistent(nic->pdev,
538 PAGE_SIZE, &tmp_p);
539 if (!tmp_v) {
540 DBG_PRINT(ERR_DBG,
541 "pci_alloc_consistent ");
542 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
543 return -ENOMEM;
544 }
545 }
1da177e4
LT		 546 while (k < lst_per_page) {
547 int l = (j * lst_per_page) + k;
548 if (l == config->tx_cfg[i].fifo_len)
20346722 549 break;
550 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 551 tmp_v + (k * lst_size);
20346722 552 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 553 tmp_p + (k * lst_size);
554 k++;
555 }
556 }
557 }
1da177e4 558
3196265e 559 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 560 if (!nic->ufo_in_band_v)
561 return -ENOMEM;
562
1da177e4
LT		 563 /* Allocation and initialization of RXDs in Rings */
564 size = 0;
565 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 566 if (config->rx_cfg[i].num_rxd %
567 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 568 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
569 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
570 i);
571 DBG_PRINT(ERR_DBG, "RxDs per Block");
572 return FAILURE;
573 }
574 size += config->rx_cfg[i].num_rxd;
20346722 575 mac_control->rings[i].block_count =
da6971d8
AR		 576 config->rx_cfg[i].num_rxd /
577 (rxd_count[nic->rxd_mode] + 1 );
578 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
579 mac_control->rings[i].block_count;
1da177e4 580 }
da6971d8
AR		 581 if (nic->rxd_mode == RXD_MODE_1)
582 size = (size * (sizeof(RxD1_t)));
583 else
584 size = (size * (sizeof(RxD3_t)));
20346722 585 rx_sz = size;
1da177e4
LT		 586
587 for (i = 0; i < config->rx_ring_num; i++) {
20346722 588 mac_control->rings[i].rx_curr_get_info.block_index = 0;
589 mac_control->rings[i].rx_curr_get_info.offset = 0;
590 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 591 config->rx_cfg[i].num_rxd - 1;
20346722 592 mac_control->rings[i].rx_curr_put_info.block_index = 0;
593 mac_control->rings[i].rx_curr_put_info.offset = 0;
594 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 595 config->rx_cfg[i].num_rxd - 1;
20346722 596 mac_control->rings[i].nic = nic;
597 mac_control->rings[i].ring_no = i;
598
da6971d8
AR		 599 blk_cnt = config->rx_cfg[i].num_rxd /
600 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 601 /* Allocating all the Rx blocks */
602 for (j = 0; j < blk_cnt; j++) {
da6971d8
AR		 603 rx_block_info_t *rx_blocks;
604 int l;
605
606 rx_blocks = &mac_control->rings[i].rx_blocks[j];
607 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 608 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
609 &tmp_p_addr);
610 if (tmp_v_addr == NULL) {
611 /*
20346722 612 * In case of failure, free_shared_mem()
613 * is called, which should free any
614 * memory that was alloced till the
1da177e4
LT		 615 * failure happened.
616 */
da6971d8 617 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 618 return -ENOMEM;
619 }
620 memset(tmp_v_addr, 0, size);
da6971d8
AR		 621 rx_blocks->block_virt_addr = tmp_v_addr;
622 rx_blocks->block_dma_addr = tmp_p_addr;
623 rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
624 rxd_count[nic->rxd_mode],
625 GFP_KERNEL);
626 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
627 rx_blocks->rxds[l].virt_addr =
628 rx_blocks->block_virt_addr +
629 (rxd_size[nic->rxd_mode] * l);
630 rx_blocks->rxds[l].dma_addr =
631 rx_blocks->block_dma_addr +
632 (rxd_size[nic->rxd_mode] * l);
633 }
1da177e4
LT		 634 }
635 /* Interlinking all Rx Blocks */
636 for (j = 0; j < blk_cnt; j++) {
20346722 637 tmp_v_addr =
638 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 639 tmp_v_addr_next =
20346722 640 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 641 blk_cnt].block_virt_addr;
20346722 642 tmp_p_addr =
643 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 644 tmp_p_addr_next =
20346722 645 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 646 blk_cnt].block_dma_addr;
647
648 pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
1da177e4
LT		 649 pre_rxd_blk->reserved_2_pNext_RxD_block =
650 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 651 pre_rxd_blk->pNext_RxD_Blk_physical =
652 (u64) tmp_p_addr_next;
653 }
654 }
da6971d8
AR		 655 if (nic->rxd_mode >= RXD_MODE_3A) {
656 /*
657 * Allocation of Storages for buffer addresses in 2BUFF mode
658 * and the buffers as well.
659 */
660 for (i = 0; i < config->rx_ring_num; i++) {
661 blk_cnt = config->rx_cfg[i].num_rxd /
662 (rxd_count[nic->rxd_mode]+ 1);
663 mac_control->rings[i].ba =
664 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
1da177e4 665 GFP_KERNEL);
da6971d8 666 if (!mac_control->rings[i].ba)
1da177e4 667 return -ENOMEM;
da6971d8
AR		 668 for (j = 0; j < blk_cnt; j++) {
669 int k = 0;
670 mac_control->rings[i].ba[j] =
671 kmalloc((sizeof(buffAdd_t) *
672 (rxd_count[nic->rxd_mode] + 1)),
673 GFP_KERNEL);
674 if (!mac_control->rings[i].ba[j])
1da177e4 675 return -ENOMEM;
da6971d8
AR		 676 while (k != rxd_count[nic->rxd_mode]) {
677 ba = &mac_control->rings[i].ba[j][k];
678
679 ba->ba_0_org = (void *) kmalloc
680 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
681 if (!ba->ba_0_org)
682 return -ENOMEM;
683 tmp = (unsigned long)ba->ba_0_org;
684 tmp += ALIGN_SIZE;
685 tmp &= ~((unsigned long) ALIGN_SIZE);
686 ba->ba_0 = (void *) tmp;
687
688 ba->ba_1_org = (void *) kmalloc
689 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
690 if (!ba->ba_1_org)
691 return -ENOMEM;
692 tmp = (unsigned long) ba->ba_1_org;
693 tmp += ALIGN_SIZE;
694 tmp &= ~((unsigned long) ALIGN_SIZE);
695 ba->ba_1 = (void *) tmp;
696 k++;
697 }
1da177e4
LT		 698 }
699 }
700 }
1da177e4
LT		 701
702 /* Allocation and initialization of Statistics block */
703 size = sizeof(StatInfo_t);
704 mac_control->stats_mem = pci_alloc_consistent
705 (nic->pdev, size, &mac_control->stats_mem_phy);
706
707 if (!mac_control->stats_mem) {
20346722 708 /*
709 * In case of failure, free_shared_mem() is called, which
710 * should free any memory that was alloced till the
1da177e4
LT		 711 * failure happened.
712 */
713 return -ENOMEM;
714 }
715 mac_control->stats_mem_sz = size;
716
717 tmp_v_addr = mac_control->stats_mem;
718 mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
719 memset(tmp_v_addr, 0, size);
1da177e4
LT		 720 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
721 (unsigned long long) tmp_p_addr);
722
723 return SUCCESS;
724}
725
20346722 726/**
727 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 728 * @nic: Device private variable.
729 * Description: This function is to free all memory locations allocated by
730 * the init_shared_mem() function and return it to the kernel.
731 */
732
733static void free_shared_mem(struct s2io_nic *nic)
734{
735 int i, j, blk_cnt, size;
736 void *tmp_v_addr;
737 dma_addr_t tmp_p_addr;
738 mac_info_t *mac_control;
739 struct config_param *config;
740 int lst_size, lst_per_page;
776bd20f 741 struct net_device *dev = nic->dev;
1da177e4
LT		 742
743 if (!nic)
744 return;
745
746 mac_control = &nic->mac_control;
747 config = &nic->config;
748
749 lst_size = (sizeof(TxD_t) * config->max_txds);
750 lst_per_page = PAGE_SIZE / lst_size;
751
752 for (i = 0; i < config->tx_fifo_num; i++) {
753 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
754 lst_per_page);
755 for (j = 0; j < page_num; j++) {
756 int mem_blks = (j * lst_per_page);
776bd20f 757 if (!mac_control->fifos[i].list_info)
6aa20a22 758 return;
776bd20f 759 if (!mac_control->fifos[i].list_info[mem_blks].
760 list_virt_addr)
1da177e4
LT		 761 break;
762 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722 763 mac_control->fifos[i].
764 list_info[mem_blks].
1da177e4 765 list_virt_addr,
20346722 766 mac_control->fifos[i].
767 list_info[mem_blks].
1da177e4
LT		 768 list_phy_addr);
769 }
776bd20f 770 /* If we got a zero DMA address during allocation,
771 * free the page now
772 */
773 if (mac_control->zerodma_virt_addr) {
774 pci_free_consistent(nic->pdev, PAGE_SIZE,
775 mac_control->zerodma_virt_addr,
776 (dma_addr_t)0);
6aa20a22 777 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 778 "%s: Freeing TxDL with zero DMA addr. ",
779 dev->name);
780 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
781 mac_control->zerodma_virt_addr);
776bd20f 782 }
20346722 783 kfree(mac_control->fifos[i].list_info);
1da177e4
LT		 784 }
785
1da177e4 786 size = SIZE_OF_BLOCK;
1da177e4 787 for (i = 0; i < config->rx_ring_num; i++) {
20346722 788 blk_cnt = mac_control->rings[i].block_count;
1da177e4 789 for (j = 0; j < blk_cnt; j++) {
20346722 790 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
791 block_virt_addr;
792 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
793 block_dma_addr;
1da177e4
LT		 794 if (tmp_v_addr == NULL)
795 break;
796 pci_free_consistent(nic->pdev, size,
797 tmp_v_addr, tmp_p_addr);
da6971d8 798 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1da177e4
LT		 799 }
800 }
801
da6971d8
AR		 802 if (nic->rxd_mode >= RXD_MODE_3A) {
803 /* Freeing buffer storage addresses in 2BUFF mode. */
804 for (i = 0; i < config->rx_ring_num; i++) {
805 blk_cnt = config->rx_cfg[i].num_rxd /
806 (rxd_count[nic->rxd_mode] + 1);
807 for (j = 0; j < blk_cnt; j++) {
808 int k = 0;
809 if (!mac_control->rings[i].ba[j])
810 continue;
811 while (k != rxd_count[nic->rxd_mode]) {
812 buffAdd_t *ba =
813 &mac_control->rings[i].ba[j][k];
814 kfree(ba->ba_0_org);
815 kfree(ba->ba_1_org);
816 k++;
817 }
818 kfree(mac_control->rings[i].ba[j]);
1da177e4 819 }
da6971d8 820 kfree(mac_control->rings[i].ba);
1da177e4 821 }
1da177e4 822 }
1da177e4
LT		 823
824 if (mac_control->stats_mem) {
825 pci_free_consistent(nic->pdev,
826 mac_control->stats_mem_sz,
827 mac_control->stats_mem,
828 mac_control->stats_mem_phy);
829 }
fed5eccd
AR		 830 if (nic->ufo_in_band_v)
831 kfree(nic->ufo_in_band_v);
1da177e4
LT		 832}
833
541ae68f 834/**
835 * s2io_verify_pci_mode -
836 */
837
838static int s2io_verify_pci_mode(nic_t *nic)
839{
509a2671 840 XENA_dev_config_t __iomem *bar0 = nic->bar0;
541ae68f 841 register u64 val64 = 0;
842 int mode;
843
844 val64 = readq(&bar0->pci_mode);
845 mode = (u8)GET_PCI_MODE(val64);
846
847 if ( val64 & PCI_MODE_UNKNOWN_MODE)
848 return -1; /* Unknown PCI mode */
849 return mode;
850}
851
c92ca04b
AR		 852#define NEC_VENID 0x1033
853#define NEC_DEVID 0x0125
854static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
855{
856 struct pci_dev *tdev = NULL;
26d36b64
AC		 857 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
858 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 859 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 860 pci_dev_put(tdev);
c92ca04b
AR		 861 return 1;
862 }
863 }
864 return 0;
865}
541ae68f 866
7b32a312 867static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 868/**
869 * s2io_print_pci_mode -
870 */
871static int s2io_print_pci_mode(nic_t *nic)
872{
509a2671 873 XENA_dev_config_t __iomem *bar0 = nic->bar0;
541ae68f 874 register u64 val64 = 0;
875 int mode;
876 struct config_param *config = &nic->config;
877
878 val64 = readq(&bar0->pci_mode);
879 mode = (u8)GET_PCI_MODE(val64);
880
881 if ( val64 & PCI_MODE_UNKNOWN_MODE)
882 return -1; /* Unknown PCI mode */
883
c92ca04b
AR		 884 config->bus_speed = bus_speed[mode];
885
886 if (s2io_on_nec_bridge(nic->pdev)) {
887 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
888 nic->dev->name);
889 return mode;
890 }
891
541ae68f 892 if (val64 & PCI_MODE_32_BITS) {
893 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
894 } else {
895 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
896 }
897
898 switch(mode) {
899 case PCI_MODE_PCI_33:
900 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f 901 break;
902 case PCI_MODE_PCI_66:
903 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f 904 break;
905 case PCI_MODE_PCIX_M1_66:
906 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f 907 break;
908 case PCI_MODE_PCIX_M1_100:
909 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f 910 break;
911 case PCI_MODE_PCIX_M1_133:
912 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f 913 break;
914 case PCI_MODE_PCIX_M2_66:
915 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f 916 break;
917 case PCI_MODE_PCIX_M2_100:
918 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f 919 break;
920 case PCI_MODE_PCIX_M2_133:
921 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f 922 break;
923 default:
924 return -1; /* Unsupported bus speed */
925 }
926
927 return mode;
928}
929
20346722 930/**
931 * init_nic - Initialization of hardware
1da177e4 932 * @nic: device peivate variable
20346722 933 * Description: The function sequentially configures every block
934 * of the H/W from their reset values.
935 * Return Value: SUCCESS on success and
1da177e4
LT		 936 * '-1' on failure (endian settings incorrect).
937 */
938
939static int init_nic(struct s2io_nic *nic)
940{
941 XENA_dev_config_t __iomem *bar0 = nic->bar0;
942 struct net_device *dev = nic->dev;
943 register u64 val64 = 0;
944 void __iomem *add;
945 u32 time;
946 int i, j;
947 mac_info_t *mac_control;
948 struct config_param *config;
c92ca04b 949 int dtx_cnt = 0;
1da177e4 950 unsigned long long mem_share;
20346722 951 int mem_size;
1da177e4
LT		 952
953 mac_control = &nic->mac_control;
954 config = &nic->config;
955
5e25b9dd 956 /* to set the swapper controle on the card */
20346722 957 if(s2io_set_swapper(nic)) {
1da177e4
LT		 958 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
959 return -1;
960 }
961
541ae68f 962 /*
963 * Herc requires EOI to be removed from reset before XGXS, so..
964 */
965 if (nic->device_type & XFRAME_II_DEVICE) {
966 val64 = 0xA500000000ULL;
967 writeq(val64, &bar0->sw_reset);
968 msleep(500);
969 val64 = readq(&bar0->sw_reset);
970 }
971
1da177e4
LT		 972 /* Remove XGXS from reset state */
973 val64 = 0;
974 writeq(val64, &bar0->sw_reset);
1da177e4 975 msleep(500);
20346722 976 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 977
978 /* Enable Receiving broadcasts */
979 add = &bar0->mac_cfg;
980 val64 = readq(&bar0->mac_cfg);
981 val64 |= MAC_RMAC_BCAST_ENABLE;
982 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
983 writel((u32) val64, add);
984 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
985 writel((u32) (val64 >> 32), (add + 4));
986
987 /* Read registers in all blocks */
988 val64 = readq(&bar0->mac_int_mask);
989 val64 = readq(&bar0->mc_int_mask);
990 val64 = readq(&bar0->xgxs_int_mask);
991
992 /* Set MTU */
993 val64 = dev->mtu;
994 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
995
541ae68f 996 if (nic->device_type & XFRAME_II_DEVICE) {
997 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 998 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 999 &bar0->dtx_control, UF);
541ae68f 1000 if (dtx_cnt & 0x1)
1001 msleep(1); /* Necessary!! */
1da177e4
LT		 1002 dtx_cnt++;
1003 }
541ae68f 1004 } else {
c92ca04b
AR		 1005 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1006 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1007 &bar0->dtx_control, UF);
1008 val64 = readq(&bar0->dtx_control);
1009 dtx_cnt++;
1da177e4
LT		 1010 }
1011 }
1012
1013 /* Tx DMA Initialization */
1014 val64 = 0;
1015 writeq(val64, &bar0->tx_fifo_partition_0);
1016 writeq(val64, &bar0->tx_fifo_partition_1);
1017 writeq(val64, &bar0->tx_fifo_partition_2);
1018 writeq(val64, &bar0->tx_fifo_partition_3);
1019
1020
1021 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1022 val64 |=
1023 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1024 13) | vBIT(config->tx_cfg[i].fifo_priority,
1025 ((i * 32) + 5), 3);
1026
1027 if (i == (config->tx_fifo_num - 1)) {
1028 if (i % 2 == 0)
1029 i++;
1030 }
1031
1032 switch (i) {
1033 case 1:
1034 writeq(val64, &bar0->tx_fifo_partition_0);
1035 val64 = 0;
1036 break;
1037 case 3:
1038 writeq(val64, &bar0->tx_fifo_partition_1);
1039 val64 = 0;
1040 break;
1041 case 5:
1042 writeq(val64, &bar0->tx_fifo_partition_2);
1043 val64 = 0;
1044 break;
1045 case 7:
1046 writeq(val64, &bar0->tx_fifo_partition_3);
1047 break;
1048 }
1049 }
1050
5e25b9dd 1051 /*
1052 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1053 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1054 */
541ae68f 1055 if ((nic->device_type == XFRAME_I_DEVICE) &&
1056 (get_xena_rev_id(nic->pdev) < 4))
5e25b9dd 1057 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1058
1da177e4
LT		 1059 val64 = readq(&bar0->tx_fifo_partition_0);
1060 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1061 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1062
20346722 1063 /*
1064 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1065 * integrity checking.
1066 */
1067 val64 = readq(&bar0->tx_pa_cfg);
1068 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1069 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1070 writeq(val64, &bar0->tx_pa_cfg);
1071
1072 /* Rx DMA intialization. */
1073 val64 = 0;
1074 for (i = 0; i < config->rx_ring_num; i++) {
1075 val64 |=
1076 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1077 3);
1078 }
1079 writeq(val64, &bar0->rx_queue_priority);
1080
20346722 1081 /*
1082 * Allocating equal share of memory to all the
1da177e4
LT		 1083 * configured Rings.
1084 */
1085 val64 = 0;
541ae68f 1086 if (nic->device_type & XFRAME_II_DEVICE)
1087 mem_size = 32;
1088 else
1089 mem_size = 64;
1090
1da177e4
LT		 1091 for (i = 0; i < config->rx_ring_num; i++) {
1092 switch (i) {
1093 case 0:
20346722 1094 mem_share = (mem_size / config->rx_ring_num +
1095 mem_size % config->rx_ring_num);
1da177e4
LT		 1096 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1097 continue;
1098 case 1:
20346722 1099 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1100 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1101 continue;
1102 case 2:
20346722 1103 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1104 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1105 continue;
1106 case 3:
20346722 1107 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1108 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1109 continue;
1110 case 4:
20346722 1111 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1112 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1113 continue;
1114 case 5:
20346722 1115 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1116 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1117 continue;
1118 case 6:
20346722 1119 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1120 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1121 continue;
1122 case 7:
20346722 1123 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1124 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1125 continue;
1126 }
1127 }
1128 writeq(val64, &bar0->rx_queue_cfg);
1129
20346722 1130 /*
5e25b9dd 1131 * Filling Tx round robin registers
1132 * as per the number of FIFOs
1da177e4 1133 */
5e25b9dd 1134 switch (config->tx_fifo_num) {
1135 case 1:
1136 val64 = 0x0000000000000000ULL;
1137 writeq(val64, &bar0->tx_w_round_robin_0);
1138 writeq(val64, &bar0->tx_w_round_robin_1);
1139 writeq(val64, &bar0->tx_w_round_robin_2);
1140 writeq(val64, &bar0->tx_w_round_robin_3);
1141 writeq(val64, &bar0->tx_w_round_robin_4);
1142 break;
1143 case 2:
1144 val64 = 0x0000010000010000ULL;
1145 writeq(val64, &bar0->tx_w_round_robin_0);
1146 val64 = 0x0100000100000100ULL;
1147 writeq(val64, &bar0->tx_w_round_robin_1);
1148 val64 = 0x0001000001000001ULL;
1149 writeq(val64, &bar0->tx_w_round_robin_2);
1150 val64 = 0x0000010000010000ULL;
1151 writeq(val64, &bar0->tx_w_round_robin_3);
1152 val64 = 0x0100000000000000ULL;
1153 writeq(val64, &bar0->tx_w_round_robin_4);
1154 break;
1155 case 3:
1156 val64 = 0x0001000102000001ULL;
1157 writeq(val64, &bar0->tx_w_round_robin_0);
1158 val64 = 0x0001020000010001ULL;
1159 writeq(val64, &bar0->tx_w_round_robin_1);
1160 val64 = 0x0200000100010200ULL;
1161 writeq(val64, &bar0->tx_w_round_robin_2);
1162 val64 = 0x0001000102000001ULL;
1163 writeq(val64, &bar0->tx_w_round_robin_3);
1164 val64 = 0x0001020000000000ULL;
1165 writeq(val64, &bar0->tx_w_round_robin_4);
1166 break;
1167 case 4:
1168 val64 = 0x0001020300010200ULL;
1169 writeq(val64, &bar0->tx_w_round_robin_0);
1170 val64 = 0x0100000102030001ULL;
1171 writeq(val64, &bar0->tx_w_round_robin_1);
1172 val64 = 0x0200010000010203ULL;
1173 writeq(val64, &bar0->tx_w_round_robin_2);
1174 val64 = 0x0001020001000001ULL;
1175 writeq(val64, &bar0->tx_w_round_robin_3);
1176 val64 = 0x0203000100000000ULL;
1177 writeq(val64, &bar0->tx_w_round_robin_4);
1178 break;
1179 case 5:
1180 val64 = 0x0001000203000102ULL;
1181 writeq(val64, &bar0->tx_w_round_robin_0);
1182 val64 = 0x0001020001030004ULL;
1183 writeq(val64, &bar0->tx_w_round_robin_1);
1184 val64 = 0x0001000203000102ULL;
1185 writeq(val64, &bar0->tx_w_round_robin_2);
1186 val64 = 0x0001020001030004ULL;
1187 writeq(val64, &bar0->tx_w_round_robin_3);
1188 val64 = 0x0001000000000000ULL;
1189 writeq(val64, &bar0->tx_w_round_robin_4);
1190 break;
1191 case 6:
1192 val64 = 0x0001020304000102ULL;
1193 writeq(val64, &bar0->tx_w_round_robin_0);
1194 val64 = 0x0304050001020001ULL;
1195 writeq(val64, &bar0->tx_w_round_robin_1);
1196 val64 = 0x0203000100000102ULL;
1197 writeq(val64, &bar0->tx_w_round_robin_2);
1198 val64 = 0x0304000102030405ULL;
1199 writeq(val64, &bar0->tx_w_round_robin_3);
1200 val64 = 0x0001000200000000ULL;
1201 writeq(val64, &bar0->tx_w_round_robin_4);
1202 break;
1203 case 7:
1204 val64 = 0x0001020001020300ULL;
1205 writeq(val64, &bar0->tx_w_round_robin_0);
1206 val64 = 0x0102030400010203ULL;
1207 writeq(val64, &bar0->tx_w_round_robin_1);
1208 val64 = 0x0405060001020001ULL;
1209 writeq(val64, &bar0->tx_w_round_robin_2);
1210 val64 = 0x0304050000010200ULL;
1211 writeq(val64, &bar0->tx_w_round_robin_3);
1212 val64 = 0x0102030000000000ULL;
1213 writeq(val64, &bar0->tx_w_round_robin_4);
1214 break;
1215 case 8:
1216 val64 = 0x0001020300040105ULL;
1217 writeq(val64, &bar0->tx_w_round_robin_0);
1218 val64 = 0x0200030106000204ULL;
1219 writeq(val64, &bar0->tx_w_round_robin_1);
1220 val64 = 0x0103000502010007ULL;
1221 writeq(val64, &bar0->tx_w_round_robin_2);
1222 val64 = 0x0304010002060500ULL;
1223 writeq(val64, &bar0->tx_w_round_robin_3);
1224 val64 = 0x0103020400000000ULL;
1225 writeq(val64, &bar0->tx_w_round_robin_4);
1226 break;
1227 }
1228
b41477f3 1229 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1230 val64 = readq(&bar0->tx_fifo_partition_0);
1231 val64 |= (TX_FIFO_PARTITION_EN);
1232 writeq(val64, &bar0->tx_fifo_partition_0);
1233
5e25b9dd 1234 /* Filling the Rx round robin registers as per the
1235 * number of Rings and steering based on QoS.
1236 */
1237 switch (config->rx_ring_num) {
1238 case 1:
1239 val64 = 0x8080808080808080ULL;
1240 writeq(val64, &bar0->rts_qos_steering);
1241 break;
1242 case 2:
1243 val64 = 0x0000010000010000ULL;
1244 writeq(val64, &bar0->rx_w_round_robin_0);
1245 val64 = 0x0100000100000100ULL;
1246 writeq(val64, &bar0->rx_w_round_robin_1);
1247 val64 = 0x0001000001000001ULL;
1248 writeq(val64, &bar0->rx_w_round_robin_2);
1249 val64 = 0x0000010000010000ULL;
1250 writeq(val64, &bar0->rx_w_round_robin_3);
1251 val64 = 0x0100000000000000ULL;
1252 writeq(val64, &bar0->rx_w_round_robin_4);
1253
1254 val64 = 0x8080808040404040ULL;
1255 writeq(val64, &bar0->rts_qos_steering);
1256 break;
1257 case 3:
1258 val64 = 0x0001000102000001ULL;
1259 writeq(val64, &bar0->rx_w_round_robin_0);
1260 val64 = 0x0001020000010001ULL;
1261 writeq(val64, &bar0->rx_w_round_robin_1);
1262 val64 = 0x0200000100010200ULL;
1263 writeq(val64, &bar0->rx_w_round_robin_2);
1264 val64 = 0x0001000102000001ULL;
1265 writeq(val64, &bar0->rx_w_round_robin_3);
1266 val64 = 0x0001020000000000ULL;
1267 writeq(val64, &bar0->rx_w_round_robin_4);
1268
1269 val64 = 0x8080804040402020ULL;
1270 writeq(val64, &bar0->rts_qos_steering);
1271 break;
1272 case 4:
1273 val64 = 0x0001020300010200ULL;
1274 writeq(val64, &bar0->rx_w_round_robin_0);
1275 val64 = 0x0100000102030001ULL;
1276 writeq(val64, &bar0->rx_w_round_robin_1);
1277 val64 = 0x0200010000010203ULL;
1278 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1279 val64 = 0x0001020001000001ULL;
5e25b9dd 1280 writeq(val64, &bar0->rx_w_round_robin_3);
1281 val64 = 0x0203000100000000ULL;
1282 writeq(val64, &bar0->rx_w_round_robin_4);
1283
1284 val64 = 0x8080404020201010ULL;
1285 writeq(val64, &bar0->rts_qos_steering);
1286 break;
1287 case 5:
1288 val64 = 0x0001000203000102ULL;
1289 writeq(val64, &bar0->rx_w_round_robin_0);
1290 val64 = 0x0001020001030004ULL;
1291 writeq(val64, &bar0->rx_w_round_robin_1);
1292 val64 = 0x0001000203000102ULL;
1293 writeq(val64, &bar0->rx_w_round_robin_2);
1294 val64 = 0x0001020001030004ULL;
1295 writeq(val64, &bar0->rx_w_round_robin_3);
1296 val64 = 0x0001000000000000ULL;
1297 writeq(val64, &bar0->rx_w_round_robin_4);
1298
1299 val64 = 0x8080404020201008ULL;
1300 writeq(val64, &bar0->rts_qos_steering);
1301 break;
1302 case 6:
1303 val64 = 0x0001020304000102ULL;
1304 writeq(val64, &bar0->rx_w_round_robin_0);
1305 val64 = 0x0304050001020001ULL;
1306 writeq(val64, &bar0->rx_w_round_robin_1);
1307 val64 = 0x0203000100000102ULL;
1308 writeq(val64, &bar0->rx_w_round_robin_2);
1309 val64 = 0x0304000102030405ULL;
1310 writeq(val64, &bar0->rx_w_round_robin_3);
1311 val64 = 0x0001000200000000ULL;
1312 writeq(val64, &bar0->rx_w_round_robin_4);
1313
1314 val64 = 0x8080404020100804ULL;
1315 writeq(val64, &bar0->rts_qos_steering);
1316 break;
1317 case 7:
1318 val64 = 0x0001020001020300ULL;
1319 writeq(val64, &bar0->rx_w_round_robin_0);
1320 val64 = 0x0102030400010203ULL;
1321 writeq(val64, &bar0->rx_w_round_robin_1);
1322 val64 = 0x0405060001020001ULL;
1323 writeq(val64, &bar0->rx_w_round_robin_2);
1324 val64 = 0x0304050000010200ULL;
1325 writeq(val64, &bar0->rx_w_round_robin_3);
1326 val64 = 0x0102030000000000ULL;
1327 writeq(val64, &bar0->rx_w_round_robin_4);
1328
1329 val64 = 0x8080402010080402ULL;
1330 writeq(val64, &bar0->rts_qos_steering);
1331 break;
1332 case 8:
1333 val64 = 0x0001020300040105ULL;
1334 writeq(val64, &bar0->rx_w_round_robin_0);
1335 val64 = 0x0200030106000204ULL;
1336 writeq(val64, &bar0->rx_w_round_robin_1);
1337 val64 = 0x0103000502010007ULL;
1338 writeq(val64, &bar0->rx_w_round_robin_2);
1339 val64 = 0x0304010002060500ULL;
1340 writeq(val64, &bar0->rx_w_round_robin_3);
1341 val64 = 0x0103020400000000ULL;
1342 writeq(val64, &bar0->rx_w_round_robin_4);
1343
1344 val64 = 0x8040201008040201ULL;
1345 writeq(val64, &bar0->rts_qos_steering);
1346 break;
1347 }
1da177e4
LT		 1348
1349 /* UDP Fix */
1350 val64 = 0;
20346722 1351 for (i = 0; i < 8; i++)
1da177e4
LT		 1352 writeq(val64, &bar0->rts_frm_len_n[i]);
1353
5e25b9dd 1354 /* Set the default rts frame length for the rings configured */
1355 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1356 for (i = 0 ; i < config->rx_ring_num ; i++)
1357 writeq(val64, &bar0->rts_frm_len_n[i]);
1358
1359 /* Set the frame length for the configured rings
1360 * desired by the user
1361 */
1362 for (i = 0; i < config->rx_ring_num; i++) {
1363 /* If rts_frm_len[i] == 0 then it is assumed that user not
1364 * specified frame length steering.
1365 * If the user provides the frame length then program
1366 * the rts_frm_len register for those values or else
1367 * leave it as it is.
1368 */
1369 if (rts_frm_len[i] != 0) {
1370 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1371 &bar0->rts_frm_len_n[i]);
1372 }
1373 }
1da177e4 1374
20346722 1375 /* Program statistics memory */
1da177e4 1376 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1377
541ae68f 1378 if (nic->device_type == XFRAME_II_DEVICE) {
1379 val64 = STAT_BC(0x320);
1380 writeq(val64, &bar0->stat_byte_cnt);
1381 }
1382
20346722 1383 /*
1da177e4
LT		 1384 * Initializing the sampling rate for the device to calculate the
1385 * bandwidth utilization.
1386 */
1387 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1388 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1389 writeq(val64, &bar0->mac_link_util);
1390
1391
20346722 1392 /*
1393 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1394 * Scheme.
1395 */
20346722 1396 /*
1397 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1398 * 250 interrupts per sec. Continuous interrupts are enabled
1399 * by default.
1400 */
541ae68f 1401 if (nic->device_type == XFRAME_II_DEVICE) {
1402 int count = (nic->config.bus_speed * 125)/2;
1403 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1404 } else {
1405
1406 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1407 }
1408 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1409 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1410 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f 1411 if (use_continuous_tx_intrs)
1412 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1413 writeq(val64, &bar0->tti_data1_mem);
1414
1415 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416 TTI_DATA2_MEM_TX_UFC_B(0x20) |
5e25b9dd 1417 TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1418 writeq(val64, &bar0->tti_data2_mem);
1419
1420 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1421 writeq(val64, &bar0->tti_command_mem);
1422
20346722 1423 /*
1da177e4
LT		 1424 * Once the operation completes, the Strobe bit of the command
1425 * register will be reset. We poll for this particular condition
1426 * We wait for a maximum of 500ms for the operation to complete,
1427 * if it's not complete by then we return error.
1428 */
1429 time = 0;
1430 while (TRUE) {
1431 val64 = readq(&bar0->tti_command_mem);
1432 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1433 break;
1434 }
1435 if (time > 10) {
1436 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1437 dev->name);
1438 return -1;
1439 }
1440 msleep(50);
1441 time++;
1442 }
1443
b6e3f982 1444 if (nic->config.bimodal) {
1445 int k = 0;
1446 for (k = 0; k < config->rx_ring_num; k++) {
1447 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1448 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1449 writeq(val64, &bar0->tti_command_mem);
541ae68f 1450
541ae68f 1451 /*
b6e3f982 1452 * Once the operation completes, the Strobe bit of the command
1453 * register will be reset. We poll for this particular condition
1454 * We wait for a maximum of 500ms for the operation to complete,
1455 * if it's not complete by then we return error.
1456 */
1457 time = 0;
1458 while (TRUE) {
1459 val64 = readq(&bar0->tti_command_mem);
1460 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1461 break;
1462 }
1463 if (time > 10) {
1464 DBG_PRINT(ERR_DBG,
1465 "%s: TTI init Failed\n",
1466 dev->name);
1467 return -1;
1468 }
1469 time++;
1470 msleep(50);
1471 }
1472 }
541ae68f 1473 } else {
1da177e4 1474
b6e3f982 1475 /* RTI Initialization */
1476 if (nic->device_type == XFRAME_II_DEVICE) {
1477 /*
1478 * Programmed to generate Apprx 500 Intrs per
1479 * second
1480 */
1481 int count = (nic->config.bus_speed * 125)/4;
1482 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1483 } else {
1484 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1485 }
1486 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1487 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1488 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1489
b6e3f982 1490 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1491
b6e3f982 1492 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1493 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1494 if (nic->intr_type == MSI_X)
1495 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1496 RTI_DATA2_MEM_RX_UFC_D(0x40));
1497 else
1498 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1499 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1500 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1501
b6e3f982 1502 for (i = 0; i < config->rx_ring_num; i++) {
1503 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1504 | RTI_CMD_MEM_OFFSET(i);
1505 writeq(val64, &bar0->rti_command_mem);
1506
1507 /*
1508 * Once the operation completes, the Strobe bit of the
1509 * command register will be reset. We poll for this
1510 * particular condition. We wait for a maximum of 500ms
1511 * for the operation to complete, if it's not complete
1512 * by then we return error.
1513 */
1514 time = 0;
1515 while (TRUE) {
1516 val64 = readq(&bar0->rti_command_mem);
1517 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1518 break;
1519 }
1520 if (time > 10) {
1521 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1522 dev->name);
1523 return -1;
1524 }
1525 time++;
1526 msleep(50);
1527 }
1da177e4 1528 }
1da177e4
LT		 1529 }
1530
20346722 1531 /*
1532 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1533 * the 8 Queues on Rx side.
1534 */
1535 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1536 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1537
1538 /* Disable RMAC PAD STRIPPING */
509a2671 1539 add = &bar0->mac_cfg;
1da177e4
LT		 1540 val64 = readq(&bar0->mac_cfg);
1541 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1542 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1543 writel((u32) (val64), add);
1544 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1545 writel((u32) (val64 >> 32), (add + 4));
1546 val64 = readq(&bar0->mac_cfg);
1547
7d3d0439
RA		 1548 /* Enable FCS stripping by adapter */
1549 add = &bar0->mac_cfg;
1550 val64 = readq(&bar0->mac_cfg);
1551 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1552 if (nic->device_type == XFRAME_II_DEVICE)
1553 writeq(val64, &bar0->mac_cfg);
1554 else {
1555 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1556 writel((u32) (val64), add);
1557 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1558 writel((u32) (val64 >> 32), (add + 4));
1559 }
1560
20346722 1561 /*
1562 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1563 * generated by xena.
1564 */
1565 val64 = readq(&bar0->rmac_pause_cfg);
1566 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1567 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1568 writeq(val64, &bar0->rmac_pause_cfg);
1569
20346722 1570 /*
1da177e4
LT		 1571 * Set the Threshold Limit for Generating the pause frame
1572 * If the amount of data in any Queue exceeds ratio of
1573 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1574 * pause frame is generated
1575 */
1576 val64 = 0;
1577 for (i = 0; i < 4; i++) {
1578 val64 |=
1579 (((u64) 0xFF00 | nic->mac_control.
1580 mc_pause_threshold_q0q3)
1581 << (i * 2 * 8));
1582 }
1583 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1584
1585 val64 = 0;
1586 for (i = 0; i < 4; i++) {
1587 val64 |=
1588 (((u64) 0xFF00 | nic->mac_control.
1589 mc_pause_threshold_q4q7)
1590 << (i * 2 * 8));
1591 }
1592 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1593
20346722 1594 /*
1595 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1596 * exceeded the limit pointed by shared_splits
1597 */
1598 val64 = readq(&bar0->pic_control);
1599 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1600 writeq(val64, &bar0->pic_control);
1601
863c11a9
AR		 1602 if (nic->config.bus_speed == 266) {
1603 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1604 writeq(0x0, &bar0->read_retry_delay);
1605 writeq(0x0, &bar0->write_retry_delay);
1606 }
1607
541ae68f 1608 /*
1609 * Programming the Herc to split every write transaction
1610 * that does not start on an ADB to reduce disconnects.
1611 */
1612 if (nic->device_type == XFRAME_II_DEVICE) {
863c11a9
AR		 1613 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1614 writeq(val64, &bar0->misc_control);
1615 val64 = readq(&bar0->pic_control2);
1616 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1617 writeq(val64, &bar0->pic_control2);
541ae68f 1618 }
c92ca04b
AR		 1619 if (strstr(nic->product_name, "CX4")) {
1620 val64 = TMAC_AVG_IPG(0x17);
1621 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1622 }
1623
1da177e4
LT		 1624 return SUCCESS;
1625}
a371a07d 1626#define LINK_UP_DOWN_INTERRUPT 1
1627#define MAC_RMAC_ERR_TIMER 2
1628
ac1f60db 1629static int s2io_link_fault_indication(nic_t *nic)
a371a07d 1630{
cc6e7c44
RA		 1631 if (nic->intr_type != INTA)
1632 return MAC_RMAC_ERR_TIMER;
a371a07d 1633 if (nic->device_type == XFRAME_II_DEVICE)
1634 return LINK_UP_DOWN_INTERRUPT;
1635 else
1636 return MAC_RMAC_ERR_TIMER;
1637}
1da177e4 1638
20346722 1639/**
1640 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1641 * @nic: device private variable,
1642 * @mask: A mask indicating which Intr block must be modified and,
1643 * @flag: A flag indicating whether to enable or disable the Intrs.
1644 * Description: This function will either disable or enable the interrupts
20346722 1645 * depending on the flag argument. The mask argument can be used to
1646 * enable/disable any Intr block.
1da177e4
LT		 1647 * Return Value: NONE.
1648 */
1649
1650static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1651{
1652 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1653 register u64 val64 = 0, temp64 = 0;
1654
1655 /* Top level interrupt classification */
1656 /* PIC Interrupts */
1657 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1658 /* Enable PIC Intrs in the general intr mask register */
1659 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1660 if (flag == ENABLE_INTRS) {
1661 temp64 = readq(&bar0->general_int_mask);
1662 temp64 &= ~((u64) val64);
1663 writeq(temp64, &bar0->general_int_mask);
20346722 1664 /*
a371a07d 1665 * If Hercules adapter enable GPIO otherwise
b41477f3 1666 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 1667 * interrupts for now.
1668 * TODO
1da177e4 1669 */
a371a07d 1670 if (s2io_link_fault_indication(nic) ==
1671 LINK_UP_DOWN_INTERRUPT ) {
1672 temp64 = readq(&bar0->pic_int_mask);
1673 temp64 &= ~((u64) PIC_INT_GPIO);
1674 writeq(temp64, &bar0->pic_int_mask);
1675 temp64 = readq(&bar0->gpio_int_mask);
1676 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1677 writeq(temp64, &bar0->gpio_int_mask);
1678 } else {
1679 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1680 }
20346722 1681 /*
1da177e4
LT		 1682 * No MSI Support is available presently, so TTI and
1683 * RTI interrupts are also disabled.
1684 */
1685 } else if (flag == DISABLE_INTRS) {
20346722 1686 /*
1687 * Disable PIC Intrs in the general
1688 * intr mask register
1da177e4
LT		 1689 */
1690 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1691 temp64 = readq(&bar0->general_int_mask);
1692 val64 |= temp64;
1693 writeq(val64, &bar0->general_int_mask);
1694 }
1695 }
1696
1697 /* DMA Interrupts */
1698 /* Enabling/Disabling Tx DMA interrupts */
1699 if (mask & TX_DMA_INTR) {
1700 /* Enable TxDMA Intrs in the general intr mask register */
1701 val64 = TXDMA_INT_M;
1702 if (flag == ENABLE_INTRS) {
1703 temp64 = readq(&bar0->general_int_mask);
1704 temp64 &= ~((u64) val64);
1705 writeq(temp64, &bar0->general_int_mask);
20346722 1706 /*
1707 * Keep all interrupts other than PFC interrupt
1da177e4
LT		 1708 * and PCC interrupt disabled in DMA level.
1709 */
1710 val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1711 TXDMA_PCC_INT_M);
1712 writeq(val64, &bar0->txdma_int_mask);
20346722 1713 /*
1714 * Enable only the MISC error 1 interrupt in PFC block
1da177e4
LT		 1715 */
1716 val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1717 writeq(val64, &bar0->pfc_err_mask);
20346722 1718 /*
1719 * Enable only the FB_ECC error interrupt in PCC block
1da177e4
LT		 1720 */
1721 val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1722 writeq(val64, &bar0->pcc_err_mask);
1723 } else if (flag == DISABLE_INTRS) {
20346722 1724 /*
1725 * Disable TxDMA Intrs in the general intr mask
1726 * register
1da177e4
LT		 1727 */
1728 writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1729 writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1730 temp64 = readq(&bar0->general_int_mask);
1731 val64 |= temp64;
1732 writeq(val64, &bar0->general_int_mask);
1733 }
1734 }
1735
1736 /* Enabling/Disabling Rx DMA interrupts */
1737 if (mask & RX_DMA_INTR) {
1738 /* Enable RxDMA Intrs in the general intr mask register */
1739 val64 = RXDMA_INT_M;
1740 if (flag == ENABLE_INTRS) {
1741 temp64 = readq(&bar0->general_int_mask);
1742 temp64 &= ~((u64) val64);
1743 writeq(temp64, &bar0->general_int_mask);
20346722 1744 /*
1745 * All RxDMA block interrupts are disabled for now
1746 * TODO
1da177e4
LT		 1747 */
1748 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1749 } else if (flag == DISABLE_INTRS) {
20346722 1750 /*
1751 * Disable RxDMA Intrs in the general intr mask
1752 * register
1da177e4
LT		 1753 */
1754 writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1755 temp64 = readq(&bar0->general_int_mask);
1756 val64 |= temp64;
1757 writeq(val64, &bar0->general_int_mask);
1758 }
1759 }
1760
1761 /* MAC Interrupts */
1762 /* Enabling/Disabling MAC interrupts */
1763 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1764 val64 = TXMAC_INT_M | RXMAC_INT_M;
1765 if (flag == ENABLE_INTRS) {
1766 temp64 = readq(&bar0->general_int_mask);
1767 temp64 &= ~((u64) val64);
1768 writeq(temp64, &bar0->general_int_mask);
20346722 1769 /*
1770 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1771 * TODO
1772 */
1da177e4 1773 } else if (flag == DISABLE_INTRS) {
20346722 1774 /*
1775 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1776 */
1777 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1778 writeq(DISABLE_ALL_INTRS,
1779 &bar0->mac_rmac_err_mask);
1780
1781 temp64 = readq(&bar0->general_int_mask);
1782 val64 |= temp64;
1783 writeq(val64, &bar0->general_int_mask);
1784 }
1785 }
1786
1787 /* XGXS Interrupts */
1788 if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1789 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1790 if (flag == ENABLE_INTRS) {
1791 temp64 = readq(&bar0->general_int_mask);
1792 temp64 &= ~((u64) val64);
1793 writeq(temp64, &bar0->general_int_mask);
20346722 1794 /*
1da177e4 1795 * All XGXS block error interrupts are disabled for now
20346722 1796 * TODO
1da177e4
LT		 1797 */
1798 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1799 } else if (flag == DISABLE_INTRS) {
20346722 1800 /*
1801 * Disable MC Intrs in the general intr mask register
1da177e4
LT		 1802 */
1803 writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1804 temp64 = readq(&bar0->general_int_mask);
1805 val64 |= temp64;
1806 writeq(val64, &bar0->general_int_mask);
1807 }
1808 }
1809
1810 /* Memory Controller(MC) interrupts */
1811 if (mask & MC_INTR) {
1812 val64 = MC_INT_M;
1813 if (flag == ENABLE_INTRS) {
1814 temp64 = readq(&bar0->general_int_mask);
1815 temp64 &= ~((u64) val64);
1816 writeq(temp64, &bar0->general_int_mask);
20346722 1817 /*
5e25b9dd 1818 * Enable all MC Intrs.
1da177e4 1819 */
5e25b9dd 1820 writeq(0x0, &bar0->mc_int_mask);
1821 writeq(0x0, &bar0->mc_err_mask);
1da177e4
LT		 1822 } else if (flag == DISABLE_INTRS) {
1823 /*
1824 * Disable MC Intrs in the general intr mask register
1825 */
1826 writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1827 temp64 = readq(&bar0->general_int_mask);
1828 val64 |= temp64;
1829 writeq(val64, &bar0->general_int_mask);
1830 }
1831 }
1832
1833
1834 /* Tx traffic interrupts */
1835 if (mask & TX_TRAFFIC_INTR) {
1836 val64 = TXTRAFFIC_INT_M;
1837 if (flag == ENABLE_INTRS) {
1838 temp64 = readq(&bar0->general_int_mask);
1839 temp64 &= ~((u64) val64);
1840 writeq(temp64, &bar0->general_int_mask);
20346722 1841 /*
1da177e4 1842 * Enable all the Tx side interrupts
20346722 1843 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1844 */
1845 writeq(0x0, &bar0->tx_traffic_mask);
1846 } else if (flag == DISABLE_INTRS) {
20346722 1847 /*
1848 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1849 * register.
1850 */
1851 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1852 temp64 = readq(&bar0->general_int_mask);
1853 val64 |= temp64;
1854 writeq(val64, &bar0->general_int_mask);
1855 }
1856 }
1857
1858 /* Rx traffic interrupts */
1859 if (mask & RX_TRAFFIC_INTR) {
1860 val64 = RXTRAFFIC_INT_M;
1861 if (flag == ENABLE_INTRS) {
1862 temp64 = readq(&bar0->general_int_mask);
1863 temp64 &= ~((u64) val64);
1864 writeq(temp64, &bar0->general_int_mask);
1865 /* writing 0 Enables all 8 RX interrupt levels */
1866 writeq(0x0, &bar0->rx_traffic_mask);
1867 } else if (flag == DISABLE_INTRS) {
20346722 1868 /*
1869 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1870 * register.
1871 */
1872 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1873 temp64 = readq(&bar0->general_int_mask);
1874 val64 |= temp64;
1875 writeq(val64, &bar0->general_int_mask);
1876 }
1877 }
1878}
1879
541ae68f 1880static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
20346722 1881{
1882 int ret = 0;
1883
1884 if (flag == FALSE) {
541ae68f 1885 if ((!herc && (rev_id >= 4)) || herc) {
5e25b9dd 1886 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1887 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1888 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1889 ret = 1;
1890 }
541ae68f 1891 }else {
5e25b9dd 1892 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1893 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1894 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1895 ret = 1;
1896 }
20346722 1897 }
1898 } else {
541ae68f 1899 if ((!herc && (rev_id >= 4)) || herc) {
5e25b9dd 1900 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1901 ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1902 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1903 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1904 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1905 ret = 1;
1906 }
1907 } else {
1908 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1909 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1910 (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1911 ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1912 ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1913 ret = 1;
1914 }
20346722 1915 }
1916 }
1917
1918 return ret;
1919}
1920/**
1921 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4
LT		 1922 * @val64 : Value read from adapter status register.
1923 * @flag : indicates if the adapter enable bit was ever written once
1924 * before.
1925 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1926 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1927 * differs and the calling function passes the input argument flag to
1928 * indicate this.
20346722 1929 * Return: 1 If xena is quiescence
1da177e4
LT		 1930 * 0 If Xena is not quiescence
1931 */
1932
20346722 1933static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1da177e4 1934{
541ae68f 1935 int ret = 0, herc;
1da177e4 1936 u64 tmp64 = ~((u64) val64);
5e25b9dd 1937 int rev_id = get_xena_rev_id(sp->pdev);
1da177e4 1938
541ae68f 1939 herc = (sp->device_type == XFRAME_II_DEVICE);
1da177e4
LT		 1940 if (!
1941 (tmp64 &
1942 (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1943 ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1944 ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1945 ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1946 ADAPTER_STATUS_P_PLL_LOCK))) {
541ae68f 1947 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1da177e4
LT		 1948 }
1949
1950 return ret;
1951}
1952
1953/**
1954 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1955 * @sp: Pointer to device specifc structure
20346722 1956 * Description :
1da177e4
LT		 1957 * New procedure to clear mac address reading problems on Alpha platforms
1958 *
1959 */
1960
ac1f60db 1961static void fix_mac_address(nic_t * sp)
1da177e4
LT		 1962{
1963 XENA_dev_config_t __iomem *bar0 = sp->bar0;
1964 u64 val64;
1965 int i = 0;
1966
1967 while (fix_mac[i] != END_SIGN) {
1968 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1969 udelay(10);
1da177e4
LT		 1970 val64 = readq(&bar0->gpio_control);
1971 }
1972}
1973
1974/**
20346722 1975 * start_nic - Turns the device on
1da177e4 1976 * @nic : device private variable.
20346722 1977 * Description:
1978 * This function actually turns the device on. Before this function is
1979 * called,all Registers are configured from their reset states
1980 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1981 * calling this function, the device interrupts are cleared and the NIC is
1982 * literally switched on by writing into the adapter control register.
20346722 1983 * Return Value:
1da177e4
LT		 1984 * SUCCESS on success and -1 on failure.
1985 */
1986
1987static int start_nic(struct s2io_nic *nic)
1988{
1989 XENA_dev_config_t __iomem *bar0 = nic->bar0;
1990 struct net_device *dev = nic->dev;
1991 register u64 val64 = 0;
20346722 1992 u16 subid, i;
1da177e4
LT		 1993 mac_info_t *mac_control;
1994 struct config_param *config;
1995
1996 mac_control = &nic->mac_control;
1997 config = &nic->config;
1998
1999 /* PRC Initialization and configuration */
2000 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2001 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2002 &bar0->prc_rxd0_n[i]);
2003
2004 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982 2005 if (nic->config.bimodal)
2006 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 2007 if (nic->rxd_mode == RXD_MODE_1)
2008 val64 |= PRC_CTRL_RC_ENABLED;
2009 else
2010 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2011 if (nic->device_type == XFRAME_II_DEVICE)
2012 val64 |= PRC_CTRL_GROUP_READS;
2013 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2014 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2015 writeq(val64, &bar0->prc_ctrl_n[i]);
2016 }
2017
da6971d8
AR		 2018 if (nic->rxd_mode == RXD_MODE_3B) {
2019 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2020 val64 = readq(&bar0->rx_pa_cfg);
2021 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2022 writeq(val64, &bar0->rx_pa_cfg);
2023 }
1da177e4 2024
20346722 2025 /*
1da177e4
LT		 2026 * Enabling MC-RLDRAM. After enabling the device, we timeout
2027 * for around 100ms, which is approximately the time required
2028 * for the device to be ready for operation.
2029 */
2030 val64 = readq(&bar0->mc_rldram_mrs);
2031 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2032 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2033 val64 = readq(&bar0->mc_rldram_mrs);
2034
20346722 2035 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2036
2037 /* Enabling ECC Protection. */
2038 val64 = readq(&bar0->adapter_control);
2039 val64 &= ~ADAPTER_ECC_EN;
2040 writeq(val64, &bar0->adapter_control);
2041
20346722 2042 /*
2043 * Clearing any possible Link state change interrupts that
1da177e4
LT		 2044 * could have popped up just before Enabling the card.
2045 */
2046 val64 = readq(&bar0->mac_rmac_err_reg);
2047 if (val64)
2048 writeq(val64, &bar0->mac_rmac_err_reg);
2049
20346722 2050 /*
2051 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2052 * it.
2053 */
2054 val64 = readq(&bar0->adapter_status);
20346722 2055 if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1da177e4
LT		 2056 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2057 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2058 (unsigned long long) val64);
2059 return FAILURE;
2060 }
2061
20346722 2062 /*
1da177e4 2063 * With some switches, link might be already up at this point.
20346722 2064 * Because of this weird behavior, when we enable laser,
2065 * we may not get link. We need to handle this. We cannot
2066 * figure out which switch is misbehaving. So we are forced to
2067 * make a global change.
1da177e4
LT		 2068 */
2069
2070 /* Enabling Laser. */
2071 val64 = readq(&bar0->adapter_control);
2072 val64 |= ADAPTER_EOI_TX_ON;
2073 writeq(val64, &bar0->adapter_control);
2074
c92ca04b
AR		 2075 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2076 /*
2077 * Dont see link state interrupts initally on some switches,
2078 * so directly scheduling the link state task here.
2079 */
2080 schedule_work(&nic->set_link_task);
2081 }
1da177e4
LT		 2082 /* SXE-002: Initialize link and activity LED */
2083 subid = nic->pdev->subsystem_device;
541ae68f 2084 if (((subid & 0xFF) >= 0x07) &&
2085 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2086 val64 = readq(&bar0->gpio_control);
2087 val64 |= 0x0000800000000000ULL;
2088 writeq(val64, &bar0->gpio_control);
2089 val64 = 0x0411040400000000ULL;
509a2671 2090 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2091 }
2092
1da177e4
LT		 2093 return SUCCESS;
2094}
fed5eccd
AR		 2095/**
2096 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2097 */
2098static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2099{
2100 nic_t *nic = fifo_data->nic;
2101 struct sk_buff *skb;
2102 TxD_t *txds;
2103 u16 j, frg_cnt;
2104
2105 txds = txdlp;
26b7625c 2106 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2107 pci_unmap_single(nic->pdev, (dma_addr_t)
2108 txds->Buffer_Pointer, sizeof(u64),
2109 PCI_DMA_TODEVICE);
2110 txds++;
2111 }
2112
2113 skb = (struct sk_buff *) ((unsigned long)
2114 txds->Host_Control);
2115 if (!skb) {
2116 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2117 return NULL;
2118 }
2119 pci_unmap_single(nic->pdev, (dma_addr_t)
2120 txds->Buffer_Pointer,
2121 skb->len - skb->data_len,
2122 PCI_DMA_TODEVICE);
2123 frg_cnt = skb_shinfo(skb)->nr_frags;
2124 if (frg_cnt) {
2125 txds++;
2126 for (j = 0; j < frg_cnt; j++, txds++) {
2127 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2128 if (!txds->Buffer_Pointer)
2129 break;
6aa20a22 2130 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2131 txds->Buffer_Pointer,
2132 frag->size, PCI_DMA_TODEVICE);
2133 }
2134 }
b41477f3 2135 memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
fed5eccd
AR		 2136 return(skb);
2137}
1da177e4 2138
20346722 2139/**
2140 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2141 * @nic : device private variable.
20346722 2142 * Description:
1da177e4 2143 * Free all queued Tx buffers.
20346722 2144 * Return Value: void
1da177e4
LT		 2145*/
2146
2147static void free_tx_buffers(struct s2io_nic *nic)
2148{
2149 struct net_device *dev = nic->dev;
2150 struct sk_buff *skb;
2151 TxD_t *txdp;
2152 int i, j;
2153 mac_info_t *mac_control;
2154 struct config_param *config;
fed5eccd 2155 int cnt = 0;
1da177e4
LT		 2156
2157 mac_control = &nic->mac_control;
2158 config = &nic->config;
2159
2160 for (i = 0; i < config->tx_fifo_num; i++) {
2161 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
20346722 2162 txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
1da177e4 2163 list_virt_addr;
fed5eccd
AR		 2164 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2165 if (skb) {
2166 dev_kfree_skb(skb);
2167 cnt++;
1da177e4 2168 }
1da177e4
LT		 2169 }
2170 DBG_PRINT(INTR_DBG,
2171 "%s:forcibly freeing %d skbs on FIFO%d\n",
2172 dev->name, cnt, i);
20346722 2173 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2174 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2175 }
2176}
2177
20346722 2178/**
2179 * stop_nic - To stop the nic
1da177e4 2180 * @nic ; device private variable.
20346722 2181 * Description:
2182 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2183 * function does. This function is called to stop the device.
2184 * Return Value:
2185 * void.
2186 */
2187
2188static void stop_nic(struct s2io_nic *nic)
2189{
2190 XENA_dev_config_t __iomem *bar0 = nic->bar0;
2191 register u64 val64 = 0;
5d3213cc 2192 u16 interruptible;
1da177e4
LT		 2193 mac_info_t *mac_control;
2194 struct config_param *config;
2195
2196 mac_control = &nic->mac_control;
2197 config = &nic->config;
2198
2199 /* Disable all interrupts */
e960fc5c 2200 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d 2201 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2202 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2203 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2204
5d3213cc
AR		 2205 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2206 val64 = readq(&bar0->adapter_control);
2207 val64 &= ~(ADAPTER_CNTL_EN);
2208 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2209}
2210
26df54bf 2211static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
da6971d8
AR		 2212{
2213 struct net_device *dev = nic->dev;
2214 struct sk_buff *frag_list;
50eb8006 2215 void *tmp;
da6971d8
AR		 2216
2217 /* Buffer-1 receives L3/L4 headers */
2218 ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2219 (nic->pdev, skb->data, l3l4hdr_size + 4,
2220 PCI_DMA_FROMDEVICE);
2221
2222 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2223 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2224 if (skb_shinfo(skb)->frag_list == NULL) {
2225 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2226 return -ENOMEM ;
2227 }
2228 frag_list = skb_shinfo(skb)->frag_list;
2229 frag_list->next = NULL;
50eb8006
JG		 2230 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2231 frag_list->data = tmp;
2232 frag_list->tail = tmp;
da6971d8
AR		 2233
2234 /* Buffer-2 receives L4 data payload */
2235 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2236 frag_list->data, dev->mtu,
2237 PCI_DMA_FROMDEVICE);
2238 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2239 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2240
2241 return SUCCESS;
2242}
2243
20346722 2244/**
2245 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2246 * @nic: device private variable
20346722 2247 * @ring_no: ring number
2248 * Description:
1da177e4
LT		 2249 * The function allocates Rx side skbs and puts the physical
2250 * address of these buffers into the RxD buffer pointers, so that the NIC
2251 * can DMA the received frame into these locations.
2252 * The NIC supports 3 receive modes, viz
2253 * 1. single buffer,
2254 * 2. three buffer and
2255 * 3. Five buffer modes.
20346722 2256 * Each mode defines how many fragments the received frame will be split
2257 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2258 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2259 * is split into 3 fragments. As of now only single buffer mode is
2260 * supported.
2261 * Return Value:
2262 * SUCCESS on success or an appropriate -ve value on failure.
2263 */
2264
ac1f60db 2265static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2266{
2267 struct net_device *dev = nic->dev;
2268 struct sk_buff *skb;
2269 RxD_t *rxdp;
2270 int off, off1, size, block_no, block_no1;
1da177e4 2271 u32 alloc_tab = 0;
20346722 2272 u32 alloc_cnt;
1da177e4
LT		 2273 mac_info_t *mac_control;
2274 struct config_param *config;
20346722 2275 u64 tmp;
1da177e4 2276 buffAdd_t *ba;
1da177e4
LT		 2277#ifndef CONFIG_S2IO_NAPI
2278 unsigned long flags;
2279#endif
303bcb4b 2280 RxD_t *first_rxdp = NULL;
1da177e4
LT		 2281
2282 mac_control = &nic->mac_control;
2283 config = &nic->config;
20346722 2284 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2285 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2286
5d3213cc 2287 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2288 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2289 while (alloc_tab < alloc_cnt) {
20346722 2290 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2291 block_index;
20346722 2292 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2293
da6971d8
AR		 2294 rxdp = mac_control->rings[ring_no].
2295 rx_blocks[block_no].rxds[off].virt_addr;
2296
2297 if ((block_no == block_no1) && (off == off1) &&
2298 (rxdp->Host_Control)) {
2299 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2300 dev->name);
1da177e4
LT		 2301 DBG_PRINT(INTR_DBG, " info equated\n");
2302 goto end;
2303 }
da6971d8 2304 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2305 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2306 block_index++;
da6971d8
AR		 2307 if (mac_control->rings[ring_no].rx_curr_put_info.
2308 block_index == mac_control->rings[ring_no].
2309 block_count)
2310 mac_control->rings[ring_no].rx_curr_put_info.
2311 block_index = 0;
2312 block_no = mac_control->rings[ring_no].
2313 rx_curr_put_info.block_index;
2314 if (off == rxd_count[nic->rxd_mode])
2315 off = 0;
20346722 2316 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2317 offset = off;
2318 rxdp = mac_control->rings[ring_no].
2319 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2320 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2321 dev->name, rxdp);
2322 }
2323#ifndef CONFIG_S2IO_NAPI
2324 spin_lock_irqsave(&nic->put_lock, flags);
20346722 2325 mac_control->rings[ring_no].put_pos =
da6971d8 2326 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
1da177e4
LT		 2327 spin_unlock_irqrestore(&nic->put_lock, flags);
2328#endif
da6971d8
AR		 2329 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2330 ((nic->rxd_mode >= RXD_MODE_3A) &&
2331 (rxdp->Control_2 & BIT(0)))) {
20346722 2332 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2333 offset = off;
1da177e4
LT		 2334 goto end;
2335 }
da6971d8
AR		 2336 /* calculate size of skb based on ring mode */
2337 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2338 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2339 if (nic->rxd_mode == RXD_MODE_1)
2340 size += NET_IP_ALIGN;
2341 else if (nic->rxd_mode == RXD_MODE_3B)
2342 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2343 else
2344 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2345
da6971d8
AR		 2346 /* allocate skb */
2347 skb = dev_alloc_skb(size);
2348 if(!skb) {
1da177e4
LT		 2349 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2350 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
303bcb4b 2351 if (first_rxdp) {
2352 wmb();
2353 first_rxdp->Control_1 |= RXD_OWN_XENA;
2354 }
da6971d8
AR		 2355 return -ENOMEM ;
2356 }
2357 if (nic->rxd_mode == RXD_MODE_1) {
2358 /* 1 buffer mode - normal operation mode */
2359 memset(rxdp, 0, sizeof(RxD1_t));
2360 skb_reserve(skb, NET_IP_ALIGN);
2361 ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
863c11a9
AR		 2362 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2363 PCI_DMA_FROMDEVICE);
2364 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8
AR		 2365
2366 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2367 /*
2368 * 2 or 3 buffer mode -
2369 * Both 2 buffer mode and 3 buffer mode provides 128
2370 * byte aligned receive buffers.
2371 *
2372 * 3 buffer mode provides header separation where in
2373 * skb->data will have L3/L4 headers where as
2374 * skb_shinfo(skb)->frag_list will have the L4 data
2375 * payload
2376 */
2377
2378 memset(rxdp, 0, sizeof(RxD3_t));
2379 ba = &mac_control->rings[ring_no].ba[block_no][off];
2380 skb_reserve(skb, BUF0_LEN);
2381 tmp = (u64)(unsigned long) skb->data;
2382 tmp += ALIGN_SIZE;
2383 tmp &= ~ALIGN_SIZE;
2384 skb->data = (void *) (unsigned long)tmp;
2385 skb->tail = (void *) (unsigned long)tmp;
2386
75c30b13
AR		 2387 if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2388 ((RxD3_t*)rxdp)->Buffer0_ptr =
2389 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2390 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2391 else
2392 pci_dma_sync_single_for_device(nic->pdev,
2393 (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2394 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2395 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2396 if (nic->rxd_mode == RXD_MODE_3B) {
2397 /* Two buffer mode */
2398
2399 /*
6aa20a22 2400 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2401 * L4 payload
2402 */
2403 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2404 (nic->pdev, skb->data, dev->mtu + 4,
2405 PCI_DMA_FROMDEVICE);
2406
75c30b13
AR		 2407 /* Buffer-1 will be dummy buffer. Not used */
2408 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2409 ((RxD3_t*)rxdp)->Buffer1_ptr =
6aa20a22 2410 pci_map_single(nic->pdev,
75c30b13
AR		 2411 ba->ba_1, BUF1_LEN,
2412 PCI_DMA_FROMDEVICE);
2413 }
da6971d8
AR		 2414 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2415 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2416 (dev->mtu + 4);
2417 } else {
2418 /* 3 buffer mode */
2419 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2420 dev_kfree_skb_irq(skb);
2421 if (first_rxdp) {
2422 wmb();
2423 first_rxdp->Control_1 |=
2424 RXD_OWN_XENA;
2425 }
2426 return -ENOMEM ;
2427 }
2428 }
2429 rxdp->Control_2 |= BIT(0);
1da177e4 2430 }
1da177e4 2431 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b 2432 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2433 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2434 off++;
da6971d8
AR		 2435 if (off == (rxd_count[nic->rxd_mode] + 1))
2436 off = 0;
20346722 2437 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2438
da6971d8 2439 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2440 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2441 if (first_rxdp) {
2442 wmb();
2443 first_rxdp->Control_1 |= RXD_OWN_XENA;
2444 }
2445 first_rxdp = rxdp;
2446 }
1da177e4
LT		 2447 atomic_inc(&nic->rx_bufs_left[ring_no]);
2448 alloc_tab++;
2449 }
2450
2451 end:
303bcb4b 2452 /* Transfer ownership of first descriptor to adapter just before
2453 * exiting. Before that, use memory barrier so that ownership
2454 * and other fields are seen by adapter correctly.
2455 */
2456 if (first_rxdp) {
2457 wmb();
2458 first_rxdp->Control_1 |= RXD_OWN_XENA;
2459 }
2460
1da177e4
LT		 2461 return SUCCESS;
2462}
2463
da6971d8
AR		 2464static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2465{
2466 struct net_device *dev = sp->dev;
2467 int j;
2468 struct sk_buff *skb;
2469 RxD_t *rxdp;
2470 mac_info_t *mac_control;
2471 buffAdd_t *ba;
2472
2473 mac_control = &sp->mac_control;
2474 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2475 rxdp = mac_control->rings[ring_no].
2476 rx_blocks[blk].rxds[j].virt_addr;
2477 skb = (struct sk_buff *)
2478 ((unsigned long) rxdp->Host_Control);
2479 if (!skb) {
2480 continue;
2481 }
2482 if (sp->rxd_mode == RXD_MODE_1) {
2483 pci_unmap_single(sp->pdev, (dma_addr_t)
2484 ((RxD1_t*)rxdp)->Buffer0_ptr,
2485 dev->mtu +
2486 HEADER_ETHERNET_II_802_3_SIZE
2487 + HEADER_802_2_SIZE +
2488 HEADER_SNAP_SIZE,
2489 PCI_DMA_FROMDEVICE);
2490 memset(rxdp, 0, sizeof(RxD1_t));
2491 } else if(sp->rxd_mode == RXD_MODE_3B) {
2492 ba = &mac_control->rings[ring_no].
2493 ba[blk][j];
2494 pci_unmap_single(sp->pdev, (dma_addr_t)
2495 ((RxD3_t*)rxdp)->Buffer0_ptr,
2496 BUF0_LEN,
2497 PCI_DMA_FROMDEVICE);
2498 pci_unmap_single(sp->pdev, (dma_addr_t)
2499 ((RxD3_t*)rxdp)->Buffer1_ptr,
2500 BUF1_LEN,
2501 PCI_DMA_FROMDEVICE);
2502 pci_unmap_single(sp->pdev, (dma_addr_t)
2503 ((RxD3_t*)rxdp)->Buffer2_ptr,
2504 dev->mtu + 4,
2505 PCI_DMA_FROMDEVICE);
2506 memset(rxdp, 0, sizeof(RxD3_t));
2507 } else {
2508 pci_unmap_single(sp->pdev, (dma_addr_t)
2509 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2510 PCI_DMA_FROMDEVICE);
2511 pci_unmap_single(sp->pdev, (dma_addr_t)
6aa20a22 2512 ((RxD3_t*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2513 l3l4hdr_size + 4,
2514 PCI_DMA_FROMDEVICE);
2515 pci_unmap_single(sp->pdev, (dma_addr_t)
2516 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2517 PCI_DMA_FROMDEVICE);
2518 memset(rxdp, 0, sizeof(RxD3_t));
2519 }
2520 dev_kfree_skb(skb);
2521 atomic_dec(&sp->rx_bufs_left[ring_no]);
2522 }
2523}
2524
1da177e4 2525/**
20346722 2526 * free_rx_buffers - Frees all Rx buffers
1da177e4 2527 * @sp: device private variable.
20346722 2528 * Description:
1da177e4
LT		 2529 * This function will free all Rx buffers allocated by host.
2530 * Return Value:
2531 * NONE.
2532 */
2533
2534static void free_rx_buffers(struct s2io_nic *sp)
2535{
2536 struct net_device *dev = sp->dev;
da6971d8 2537 int i, blk = 0, buf_cnt = 0;
1da177e4
LT		 2538 mac_info_t *mac_control;
2539 struct config_param *config;
1da177e4
LT		 2540
2541 mac_control = &sp->mac_control;
2542 config = &sp->config;
2543
2544 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2545 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2546 free_rxd_blk(sp,i,blk);
1da177e4 2547
20346722 2548 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2549 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2550 mac_control->rings[i].rx_curr_put_info.offset = 0;
2551 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2552 atomic_set(&sp->rx_bufs_left[i], 0);
2553 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2554 dev->name, buf_cnt, i);
2555 }
2556}
2557
2558/**
2559 * s2io_poll - Rx interrupt handler for NAPI support
2560 * @dev : pointer to the device structure.
20346722 2561 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2562 * during one pass through the 'Poll" function.
2563 * Description:
2564 * Comes into picture only if NAPI support has been incorporated. It does
2565 * the same thing that rx_intr_handler does, but not in a interrupt context
2566 * also It will process only a given number of packets.
2567 * Return value:
2568 * 0 on success and 1 if there are No Rx packets to be processed.
2569 */
2570
20346722 2571#if defined(CONFIG_S2IO_NAPI)
1da177e4
LT		 2572static int s2io_poll(struct net_device *dev, int *budget)
2573{
2574 nic_t *nic = dev->priv;
20346722 2575 int pkt_cnt = 0, org_pkts_to_process;
1da177e4
LT		 2576 mac_info_t *mac_control;
2577 struct config_param *config;
509a2671 2578 XENA_dev_config_t __iomem *bar0 = nic->bar0;
863c11a9 2579 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
20346722 2580 int i;
1da177e4 2581
7ba013ac 2582 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2583 mac_control = &nic->mac_control;
2584 config = &nic->config;
2585
20346722 2586 nic->pkts_to_process = *budget;
2587 if (nic->pkts_to_process > dev->quota)
2588 nic->pkts_to_process = dev->quota;
2589 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2590
1da177e4 2591 writeq(val64, &bar0->rx_traffic_int);
863c11a9 2592 val64 = readl(&bar0->rx_traffic_int);
1da177e4
LT		 2593
2594 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2595 rx_intr_handler(&mac_control->rings[i]);
2596 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2597 if (!nic->pkts_to_process) {
2598 /* Quota for the current iteration has been met */
2599 goto no_rx;
1da177e4 2600 }
1da177e4
LT		 2601 }
2602 if (!pkt_cnt)
2603 pkt_cnt = 1;
2604
2605 dev->quota -= pkt_cnt;
2606 *budget -= pkt_cnt;
2607 netif_rx_complete(dev);
2608
2609 for (i = 0; i < config->rx_ring_num; i++) {
2610 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2611 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2612 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2613 break;
2614 }
2615 }
2616 /* Re enable the Rx interrupts. */
c92ca04b
AR		 2617 writeq(0x0, &bar0->rx_traffic_mask);
2618 val64 = readl(&bar0->rx_traffic_mask);
7ba013ac 2619 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2620 return 0;
2621
20346722 2622no_rx:
1da177e4
LT		 2623 dev->quota -= pkt_cnt;
2624 *budget -= pkt_cnt;
2625
2626 for (i = 0; i < config->rx_ring_num; i++) {
2627 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2628 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2629 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2630 break;
2631 }
2632 }
7ba013ac 2633 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2634 return 1;
2635}
20346722 2636#endif
2637
b41477f3 2638#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2639/**
b41477f3 2640 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2641 * @dev : pointer to the device structure.
2642 * Description:
b41477f3
AR		 2643 * This function will be called by upper layer to check for events on the
2644 * interface in situations where interrupts are disabled. It is used for
2645 * specific in-kernel networking tasks, such as remote consoles and kernel
2646 * debugging over the network (example netdump in RedHat).
612eff0e 2647 */
612eff0e
BH		 2648static void s2io_netpoll(struct net_device *dev)
2649{
2650 nic_t *nic = dev->priv;
2651 mac_info_t *mac_control;
2652 struct config_param *config;
2653 XENA_dev_config_t __iomem *bar0 = nic->bar0;
b41477f3 2654 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2655 int i;
2656
2657 disable_irq(dev->irq);
2658
2659 atomic_inc(&nic->isr_cnt);
2660 mac_control = &nic->mac_control;
2661 config = &nic->config;
2662
612eff0e 2663 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2664 writeq(val64, &bar0->tx_traffic_int);
2665
6aa20a22 2666 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2667 * run out of skbs and will fail and eventually netpoll application such
2668 * as netdump will fail.
2669 */
2670 for (i = 0; i < config->tx_fifo_num; i++)
2671 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2672
b41477f3 2673 /* check for received packet and indicate up to network */
612eff0e
BH		 2674 for (i = 0; i < config->rx_ring_num; i++)
2675 rx_intr_handler(&mac_control->rings[i]);
2676
2677 for (i = 0; i < config->rx_ring_num; i++) {
2678 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2679 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2680 DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2681 break;
2682 }
2683 }
2684 atomic_dec(&nic->isr_cnt);
2685 enable_irq(dev->irq);
2686 return;
2687}
2688#endif
2689
20346722 2690/**
1da177e4
LT		 2691 * rx_intr_handler - Rx interrupt handler
2692 * @nic: device private variable.
20346722 2693 * Description:
2694 * If the interrupt is because of a received frame or if the
1da177e4 2695 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2696 * called. It picks out the RxD at which place the last Rx processing had
2697 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2698 * the offset.
2699 * Return Value:
2700 * NONE.
2701 */
20346722 2702static void rx_intr_handler(ring_info_t *ring_data)
1da177e4 2703{
20346722 2704 nic_t *nic = ring_data->nic;
1da177e4 2705 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2706 int get_block, put_block, put_offset;
1da177e4
LT		 2707 rx_curr_get_info_t get_info, put_info;
2708 RxD_t *rxdp;
2709 struct sk_buff *skb;
20346722 2710#ifndef CONFIG_S2IO_NAPI
2711 int pkt_cnt = 0;
1da177e4 2712#endif
7d3d0439
RA		 2713 int i;
2714
7ba013ac 2715 spin_lock(&nic->rx_lock);
2716 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2717 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac 2718 __FUNCTION__, dev->name);
2719 spin_unlock(&nic->rx_lock);
776bd20f 2720 return;
7ba013ac 2721 }
2722
20346722 2723 get_info = ring_data->rx_curr_get_info;
2724 get_block = get_info.block_index;
2725 put_info = ring_data->rx_curr_put_info;
2726 put_block = put_info.block_index;
da6971d8 2727 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
20346722 2728#ifndef CONFIG_S2IO_NAPI
2729 spin_lock(&nic->put_lock);
2730 put_offset = ring_data->put_pos;
2731 spin_unlock(&nic->put_lock);
2732#else
da6971d8 2733 put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
20346722 2734 put_info.offset;
2735#endif
da6971d8
AR		 2736 while (RXD_IS_UP2DT(rxdp)) {
2737 /* If your are next to put index then it's FIFO full condition */
2738 if ((get_block == put_block) &&
2739 (get_info.offset + 1) == put_info.offset) {
75c30b13 2740 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2741 break;
2742 }
20346722 2743 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2744 if (skb == NULL) {
2745 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2746 dev->name);
2747 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2748 spin_unlock(&nic->rx_lock);
20346722 2749 return;
1da177e4 2750 }
da6971d8
AR		 2751 if (nic->rxd_mode == RXD_MODE_1) {
2752 pci_unmap_single(nic->pdev, (dma_addr_t)
2753 ((RxD1_t*)rxdp)->Buffer0_ptr,
20346722 2754 dev->mtu +
2755 HEADER_ETHERNET_II_802_3_SIZE +
2756 HEADER_802_2_SIZE +
2757 HEADER_SNAP_SIZE,
2758 PCI_DMA_FROMDEVICE);
da6971d8 2759 } else if (nic->rxd_mode == RXD_MODE_3B) {
75c30b13 2760 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
da6971d8 2761 ((RxD3_t*)rxdp)->Buffer0_ptr,
20346722 2762 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2763 pci_unmap_single(nic->pdev, (dma_addr_t)
2764 ((RxD3_t*)rxdp)->Buffer2_ptr,
2765 dev->mtu + 4,
20346722 2766 PCI_DMA_FROMDEVICE);
da6971d8 2767 } else {
75c30b13 2768 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
da6971d8
AR		 2769 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2770 PCI_DMA_FROMDEVICE);
2771 pci_unmap_single(nic->pdev, (dma_addr_t)
2772 ((RxD3_t*)rxdp)->Buffer1_ptr,
2773 l3l4hdr_size + 4,
2774 PCI_DMA_FROMDEVICE);
2775 pci_unmap_single(nic->pdev, (dma_addr_t)
2776 ((RxD3_t*)rxdp)->Buffer2_ptr,
2777 dev->mtu, PCI_DMA_FROMDEVICE);
2778 }
863c11a9 2779 prefetch(skb->data);
20346722 2780 rx_osm_handler(ring_data, rxdp);
2781 get_info.offset++;
da6971d8
AR		 2782 ring_data->rx_curr_get_info.offset = get_info.offset;
2783 rxdp = ring_data->rx_blocks[get_block].
2784 rxds[get_info.offset].virt_addr;
2785 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2786 get_info.offset = 0;
da6971d8 2787 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2788 get_block++;
da6971d8
AR		 2789 if (get_block == ring_data->block_count)
2790 get_block = 0;
2791 ring_data->rx_curr_get_info.block_index = get_block;
20346722 2792 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2793 }
1da177e4 2794
20346722 2795#ifdef CONFIG_S2IO_NAPI
2796 nic->pkts_to_process -= 1;
2797 if (!nic->pkts_to_process)
2798 break;
2799#else
2800 pkt_cnt++;
1da177e4
LT		 2801 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2802 break;
20346722 2803#endif
1da177e4 2804 }
7d3d0439
RA		 2805 if (nic->lro) {
2806 /* Clear all LRO sessions before exiting */
2807 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2808 lro_t *lro = &nic->lro0_n[i];
2809 if (lro->in_use) {
2810 update_L3L4_header(nic, lro);
2811 queue_rx_frame(lro->parent);
2812 clear_lro_session(lro);
2813 }
2814 }
2815 }
2816
7ba013ac 2817 spin_unlock(&nic->rx_lock);
1da177e4 2818}
20346722 2819
2820/**
1da177e4
LT		 2821 * tx_intr_handler - Transmit interrupt handler
2822 * @nic : device private variable
20346722 2823 * Description:
2824 * If an interrupt was raised to indicate DMA complete of the
2825 * Tx packet, this function is called. It identifies the last TxD
2826 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2827 * DMA'ed into the NICs internal memory.
2828 * Return Value:
2829 * NONE
2830 */
2831
20346722 2832static void tx_intr_handler(fifo_info_t *fifo_data)
1da177e4 2833{
20346722 2834 nic_t *nic = fifo_data->nic;
1da177e4
LT		 2835 struct net_device *dev = (struct net_device *) nic->dev;
2836 tx_curr_get_info_t get_info, put_info;
2837 struct sk_buff *skb;
2838 TxD_t *txdlp;
1da177e4 2839
20346722 2840 get_info = fifo_data->tx_curr_get_info;
2841 put_info = fifo_data->tx_curr_put_info;
2842 txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2843 list_virt_addr;
2844 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2845 (get_info.offset != put_info.offset) &&
2846 (txdlp->Host_Control)) {
2847 /* Check for TxD errors */
2848 if (txdlp->Control_1 & TXD_T_CODE) {
2849 unsigned long long err;
2850 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2851 if (err & 0x1) {
2852 nic->mac_control.stats_info->sw_stat.
2853 parity_err_cnt++;
2854 }
776bd20f 2855 if ((err >> 48) == 0xA) {
2856 DBG_PRINT(TX_DBG, "TxD returned due \
cc6e7c44 2857to loss of link\n");
776bd20f 2858 }
2859 else {
2860 DBG_PRINT(ERR_DBG, "***TxD error \
cc6e7c44 2861%llx\n", err);
776bd20f 2862 }
20346722 2863 }
1da177e4 2864
fed5eccd 2865 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 2866 if (skb == NULL) {
2867 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2868 __FUNCTION__);
2869 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2870 return;
2871 }
2872
20346722 2873 /* Updating the statistics block */
20346722 2874 nic->stats.tx_bytes += skb->len;
2875 dev_kfree_skb_irq(skb);
2876
2877 get_info.offset++;
863c11a9
AR		 2878 if (get_info.offset == get_info.fifo_len + 1)
2879 get_info.offset = 0;
20346722 2880 txdlp = (TxD_t *) fifo_data->list_info
2881 [get_info.offset].list_virt_addr;
2882 fifo_data->tx_curr_get_info.offset =
2883 get_info.offset;
1da177e4
LT		 2884 }
2885
2886 spin_lock(&nic->tx_lock);
2887 if (netif_queue_stopped(dev))
2888 netif_wake_queue(dev);
2889 spin_unlock(&nic->tx_lock);
2890}
2891
bd1034f0
AR		 2892/**
2893 * s2io_mdio_write - Function to write in to MDIO registers
2894 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2895 * @addr : address value
2896 * @value : data value
2897 * @dev : pointer to net_device structure
2898 * Description:
2899 * This function is used to write values to the MDIO registers
2900 * NONE
2901 */
2902static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2903{
2904 u64 val64 = 0x0;
2905 nic_t *sp = dev->priv;
cc3afe6f 2906 XENA_dev_config_t __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2907
2908 //address transaction
2909 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2910 | MDIO_MMD_DEV_ADDR(mmd_type)
2911 | MDIO_MMS_PRT_ADDR(0x0);
2912 writeq(val64, &bar0->mdio_control);
2913 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2914 writeq(val64, &bar0->mdio_control);
2915 udelay(100);
2916
2917 //Data transaction
2918 val64 = 0x0;
2919 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2920 | MDIO_MMD_DEV_ADDR(mmd_type)
2921 | MDIO_MMS_PRT_ADDR(0x0)
2922 | MDIO_MDIO_DATA(value)
2923 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2924 writeq(val64, &bar0->mdio_control);
2925 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2926 writeq(val64, &bar0->mdio_control);
2927 udelay(100);
2928
2929 val64 = 0x0;
2930 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2931 | MDIO_MMD_DEV_ADDR(mmd_type)
2932 | MDIO_MMS_PRT_ADDR(0x0)
2933 | MDIO_OP(MDIO_OP_READ_TRANS);
2934 writeq(val64, &bar0->mdio_control);
2935 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2936 writeq(val64, &bar0->mdio_control);
2937 udelay(100);
2938
2939}
2940
2941/**
2942 * s2io_mdio_read - Function to write in to MDIO registers
2943 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2944 * @addr : address value
2945 * @dev : pointer to net_device structure
2946 * Description:
2947 * This function is used to read values to the MDIO registers
2948 * NONE
2949 */
2950static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2951{
2952 u64 val64 = 0x0;
2953 u64 rval64 = 0x0;
2954 nic_t *sp = dev->priv;
cc3afe6f 2955 XENA_dev_config_t __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2956
2957 /* address transaction */
2958 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2959 | MDIO_MMD_DEV_ADDR(mmd_type)
2960 | MDIO_MMS_PRT_ADDR(0x0);
2961 writeq(val64, &bar0->mdio_control);
2962 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2963 writeq(val64, &bar0->mdio_control);
2964 udelay(100);
2965
2966 /* Data transaction */
2967 val64 = 0x0;
2968 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2969 | MDIO_MMD_DEV_ADDR(mmd_type)
2970 | MDIO_MMS_PRT_ADDR(0x0)
2971 | MDIO_OP(MDIO_OP_READ_TRANS);
2972 writeq(val64, &bar0->mdio_control);
2973 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2974 writeq(val64, &bar0->mdio_control);
2975 udelay(100);
2976
2977 /* Read the value from regs */
2978 rval64 = readq(&bar0->mdio_control);
2979 rval64 = rval64 & 0xFFFF0000;
2980 rval64 = rval64 >> 16;
2981 return rval64;
2982}
2983/**
2984 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2985 * @counter : couter value to be updated
2986 * @flag : flag to indicate the status
2987 * @type : counter type
2988 * Description:
2989 * This function is to check the status of the xpak counters value
2990 * NONE
2991 */
2992
2993static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2994{
2995 u64 mask = 0x3;
2996 u64 val64;
2997 int i;
2998 for(i = 0; i <index; i++)
2999 mask = mask << 0x2;
3000
3001 if(flag > 0)
3002 {
3003 *counter = *counter + 1;
3004 val64 = *regs_stat & mask;
3005 val64 = val64 >> (index * 0x2);
3006 val64 = val64 + 1;
3007 if(val64 == 3)
3008 {
3009 switch(type)
3010 {
3011 case 1:
3012 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3013 "service. Excessive temperatures may "
3014 "result in premature transceiver "
3015 "failure \n");
3016 break;
3017 case 2:
3018 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3019 "service Excessive bias currents may "
3020 "indicate imminent laser diode "
3021 "failure \n");
3022 break;
3023 case 3:
3024 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3025 "service Excessive laser output "
3026 "power may saturate far-end "
3027 "receiver\n");
3028 break;
3029 default:
3030 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3031 "type \n");
3032 }
3033 val64 = 0x0;
3034 }
3035 val64 = val64 << (index * 0x2);
3036 *regs_stat = (*regs_stat & (~mask)) | (val64);
3037
3038 } else {
3039 *regs_stat = *regs_stat & (~mask);
3040 }
3041}
3042
3043/**
3044 * s2io_updt_xpak_counter - Function to update the xpak counters
3045 * @dev : pointer to net_device struct
3046 * Description:
3047 * This function is to upate the status of the xpak counters value
3048 * NONE
3049 */
3050static void s2io_updt_xpak_counter(struct net_device *dev)
3051{
3052 u16 flag = 0x0;
3053 u16 type = 0x0;
3054 u16 val16 = 0x0;
3055 u64 val64 = 0x0;
3056 u64 addr = 0x0;
3057
3058 nic_t *sp = dev->priv;
3059 StatInfo_t *stat_info = sp->mac_control.stats_info;
3060
3061 /* Check the communication with the MDIO slave */
3062 addr = 0x0000;
3063 val64 = 0x0;
3064 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3065 if((val64 == 0xFFFF) || (val64 == 0x0000))
3066 {
3067 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3068 "Returned %llx\n", (unsigned long long)val64);
3069 return;
3070 }
3071
3072 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3073 if(val64 != 0x2040)
3074 {
3075 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3076 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3077 (unsigned long long)val64);
3078 return;
3079 }
3080
3081 /* Loading the DOM register to MDIO register */
3082 addr = 0xA100;
3083 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3084 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3085
3086 /* Reading the Alarm flags */
3087 addr = 0xA070;
3088 val64 = 0x0;
3089 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3090
3091 flag = CHECKBIT(val64, 0x7);
3092 type = 1;
3093 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3094 &stat_info->xpak_stat.xpak_regs_stat,
3095 0x0, flag, type);
3096
3097 if(CHECKBIT(val64, 0x6))
3098 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3099
3100 flag = CHECKBIT(val64, 0x3);
3101 type = 2;
3102 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3103 &stat_info->xpak_stat.xpak_regs_stat,
3104 0x2, flag, type);
3105
3106 if(CHECKBIT(val64, 0x2))
3107 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3108
3109 flag = CHECKBIT(val64, 0x1);
3110 type = 3;
3111 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3112 &stat_info->xpak_stat.xpak_regs_stat,
3113 0x4, flag, type);
3114
3115 if(CHECKBIT(val64, 0x0))
3116 stat_info->xpak_stat.alarm_laser_output_power_low++;
3117
3118 /* Reading the Warning flags */
3119 addr = 0xA074;
3120 val64 = 0x0;
3121 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3122
3123 if(CHECKBIT(val64, 0x7))
3124 stat_info->xpak_stat.warn_transceiver_temp_high++;
3125
3126 if(CHECKBIT(val64, 0x6))
3127 stat_info->xpak_stat.warn_transceiver_temp_low++;
3128
3129 if(CHECKBIT(val64, 0x3))
3130 stat_info->xpak_stat.warn_laser_bias_current_high++;
3131
3132 if(CHECKBIT(val64, 0x2))
3133 stat_info->xpak_stat.warn_laser_bias_current_low++;
3134
3135 if(CHECKBIT(val64, 0x1))
3136 stat_info->xpak_stat.warn_laser_output_power_high++;
3137
3138 if(CHECKBIT(val64, 0x0))
3139 stat_info->xpak_stat.warn_laser_output_power_low++;
3140}
3141
20346722 3142/**
1da177e4
LT		 3143 * alarm_intr_handler - Alarm Interrrupt handler
3144 * @nic: device private variable
20346722 3145 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3146 * complete, this function is called. If the interrupt was to indicate
20346722 3147 * a loss of link, the OSM link status handler is invoked for any other
3148 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3149 * and a H/W reset is issued.
3150 * Return Value:
3151 * NONE
3152*/
3153
3154static void alarm_intr_handler(struct s2io_nic *nic)
3155{
3156 struct net_device *dev = (struct net_device *) nic->dev;
3157 XENA_dev_config_t __iomem *bar0 = nic->bar0;
3158 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3159 u64 cnt;
3160 int i;
3161 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3162 /* Handling the XPAK counters update */
3163 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3164 /* waiting for an hour */
3165 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3166 } else {
3167 s2io_updt_xpak_counter(dev);
3168 /* reset the count to zero */
3169 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3170 }
1da177e4
LT		 3171
3172 /* Handling link status change error Intr */
a371a07d 3173 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3174 err_reg = readq(&bar0->mac_rmac_err_reg);
3175 writeq(err_reg, &bar0->mac_rmac_err_reg);
3176 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3177 schedule_work(&nic->set_link_task);
3178 }
1da177e4
LT		 3179 }
3180
5e25b9dd 3181 /* Handling Ecc errors */
3182 val64 = readq(&bar0->mc_err_reg);
3183 writeq(val64, &bar0->mc_err_reg);
3184 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3185 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac 3186 nic->mac_control.stats_info->sw_stat.
3187 double_ecc_errs++;
776bd20f 3188 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3189 dev->name);
776bd20f 3190 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3191 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3192 /* Reset XframeI only if critical error */
3193 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3194 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3195 netif_stop_queue(dev);
3196 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3197 nic->mac_control.stats_info->sw_stat.
3198 soft_reset_cnt++;
776bd20f 3199 }
e960fc5c 3200 }
5e25b9dd 3201 } else {
7ba013ac 3202 nic->mac_control.stats_info->sw_stat.
3203 single_ecc_errs++;
5e25b9dd 3204 }
3205 }
3206
1da177e4
LT		 3207 /* In case of a serious error, the device will be Reset. */
3208 val64 = readq(&bar0->serr_source);
3209 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3210 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3211 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3212 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3213 (unsigned long long)val64);
1da177e4
LT		 3214 netif_stop_queue(dev);
3215 schedule_work(&nic->rst_timer_task);
bd1034f0 3216 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3217 }
3218
3219 /*
3220 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3221 * Error occurs, the adapter will be recycled by disabling the
20346722 3222 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3223 * becomes Quiescent.
3224 */
3225 val64 = readq(&bar0->pcc_err_reg);
3226 writeq(val64, &bar0->pcc_err_reg);
3227 if (val64 & PCC_FB_ECC_DB_ERR) {
3228 u64 ac = readq(&bar0->adapter_control);
3229 ac &= ~(ADAPTER_CNTL_EN);
3230 writeq(ac, &bar0->adapter_control);
3231 ac = readq(&bar0->adapter_control);
3232 schedule_work(&nic->set_link_task);
3233 }
bd1034f0
AR		 3234 /* Check for data parity error */
3235 val64 = readq(&bar0->pic_int_status);
3236 if (val64 & PIC_INT_GPIO) {
3237 val64 = readq(&bar0->gpio_int_reg);
3238 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3239 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3240 schedule_work(&nic->rst_timer_task);
3241 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3242 }
3243 }
3244
3245 /* Check for ring full counter */
3246 if (nic->device_type & XFRAME_II_DEVICE) {
3247 val64 = readq(&bar0->ring_bump_counter1);
3248 for (i=0; i<4; i++) {
3249 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3250 cnt >>= 64 - ((i+1)*16);
3251 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3252 += cnt;
3253 }
3254
3255 val64 = readq(&bar0->ring_bump_counter2);
3256 for (i=0; i<4; i++) {
3257 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3258 cnt >>= 64 - ((i+1)*16);
3259 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3260 += cnt;
3261 }
3262 }
1da177e4
LT		 3263
3264 /* Other type of interrupts are not being handled now, TODO */
3265}
3266
20346722 3267/**
1da177e4 3268 * wait_for_cmd_complete - waits for a command to complete.
20346722 3269 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3270 * s2io_nic structure.
20346722 3271 * Description: Function that waits for a command to Write into RMAC
3272 * ADDR DATA registers to be completed and returns either success or
3273 * error depending on whether the command was complete or not.
1da177e4
LT		 3274 * Return value:
3275 * SUCCESS on success and FAILURE on failure.
3276 */
3277
cc3afe6f 3278static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit)
1da177e4 3279{
1da177e4
LT		 3280 int ret = FAILURE, cnt = 0;
3281 u64 val64;
3282
3283 while (TRUE) {
c92ca04b
AR		 3284 val64 = readq(addr);
3285 if (!(val64 & busy_bit)) {
1da177e4
LT		 3286 ret = SUCCESS;
3287 break;
3288 }
c92ca04b
AR		 3289
3290 if(in_interrupt())
3291 mdelay(50);
3292 else
3293 msleep(50);
3294
1da177e4
LT		 3295 if (cnt++ > 10)
3296 break;
3297 }
1da177e4
LT		 3298 return ret;
3299}
3300
20346722 3301/**
3302 * s2io_reset - Resets the card.
1da177e4
LT		 3303 * @sp : private member of the device structure.
3304 * Description: Function to Reset the card. This function then also
20346722 3305 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3306 * the card reset also resets the configuration space.
3307 * Return value:
3308 * void.
3309 */
3310
26df54bf 3311static void s2io_reset(nic_t * sp)
1da177e4
LT		 3312{
3313 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3314 u64 val64;
5e25b9dd 3315 u16 subid, pci_cmd;
1da177e4 3316
0b1f7ebe 3317 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3318 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3319
1da177e4
LT		 3320 val64 = SW_RESET_ALL;
3321 writeq(val64, &bar0->sw_reset);
3322
20346722 3323 /*
3324 * At this stage, if the PCI write is indeed completed, the
3325 * card is reset and so is the PCI Config space of the device.
3326 * So a read cannot be issued at this stage on any of the
1da177e4
LT		 3327 * registers to ensure the write into "sw_reset" register
3328 * has gone through.
3329 * Question: Is there any system call that will explicitly force
3330 * all the write commands still pending on the bus to be pushed
3331 * through?
3332 * As of now I'am just giving a 250ms delay and hoping that the
3333 * PCI write to sw_reset register is done by this time.
3334 */
3335 msleep(250);
c92ca04b
AR		 3336 if (strstr(sp->product_name, "CX4")) {
3337 msleep(750);
3338 }
1da177e4 3339
e960fc5c 3340 /* Restore the PCI state saved during initialization. */
3341 pci_restore_state(sp->pdev);
3342 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
0b1f7ebe 3343 pci_cmd);
1da177e4
LT		 3344 s2io_init_pci(sp);
3345
3346 msleep(250);
3347
20346722 3348 /* Set swapper to enable I/O register access */
3349 s2io_set_swapper(sp);
3350
cc6e7c44
RA		 3351 /* Restore the MSIX table entries from local variables */
3352 restore_xmsi_data(sp);
3353
5e25b9dd 3354 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3355 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3356 /* Clear "detected parity error" bit */
303bcb4b 3357 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3358
303bcb4b 3359 /* Clearing PCIX Ecc status register */
3360 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3361
303bcb4b 3362 /* Clearing PCI_STATUS error reflected here */
3363 writeq(BIT(62), &bar0->txpic_int_reg);
3364 }
5e25b9dd 3365
20346722 3366 /* Reset device statistics maintained by OS */
3367 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3368
1da177e4
LT		 3369 /* SXE-002: Configure link and activity LED to turn it off */
3370 subid = sp->pdev->subsystem_device;
541ae68f 3371 if (((subid & 0xFF) >= 0x07) &&
3372 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3373 val64 = readq(&bar0->gpio_control);
3374 val64 |= 0x0000800000000000ULL;
3375 writeq(val64, &bar0->gpio_control);
3376 val64 = 0x0411040400000000ULL;
509a2671 3377 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3378 }
3379
541ae68f 3380 /*
3381 * Clear spurious ECC interrupts that would have occured on
3382 * XFRAME II cards after reset.
3383 */
3384 if (sp->device_type == XFRAME_II_DEVICE) {
3385 val64 = readq(&bar0->pcc_err_reg);
3386 writeq(val64, &bar0->pcc_err_reg);
3387 }
3388
1da177e4
LT		 3389 sp->device_enabled_once = FALSE;
3390}
3391
3392/**
20346722 3393 * s2io_set_swapper - to set the swapper controle on the card
3394 * @sp : private member of the device structure,
1da177e4 3395 * pointer to the s2io_nic structure.
20346722 3396 * Description: Function to set the swapper control on the card
1da177e4
LT		 3397 * correctly depending on the 'endianness' of the system.
3398 * Return value:
3399 * SUCCESS on success and FAILURE on failure.
3400 */
3401
26df54bf 3402static int s2io_set_swapper(nic_t * sp)
1da177e4
LT		 3403{
3404 struct net_device *dev = sp->dev;
3405 XENA_dev_config_t __iomem *bar0 = sp->bar0;
3406 u64 val64, valt, valr;
3407
20346722 3408 /*
1da177e4
LT		 3409 * Set proper endian settings and verify the same by reading
3410 * the PIF Feed-back register.
3411 */
3412
3413 val64 = readq(&bar0->pif_rd_swapper_fb);
3414 if (val64 != 0x0123456789ABCDEFULL) {
3415 int i = 0;
3416 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3417 0x8100008181000081ULL, /* FE=1, SE=0 */
3418 0x4200004242000042ULL, /* FE=0, SE=1 */
3419 0}; /* FE=0, SE=0 */
3420
3421 while(i<4) {
3422 writeq(value[i], &bar0->swapper_ctrl);
3423 val64 = readq(&bar0->pif_rd_swapper_fb);
3424 if (val64 == 0x0123456789ABCDEFULL)
3425 break;
3426 i++;
3427 }
3428 if (i == 4) {
3429 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3430 dev->name);
3431 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3432 (unsigned long long) val64);
3433 return FAILURE;
3434 }
3435 valr = value[i];
3436 } else {
3437 valr = readq(&bar0->swapper_ctrl);
3438 }
3439
3440 valt = 0x0123456789ABCDEFULL;
3441 writeq(valt, &bar0->xmsi_address);
3442 val64 = readq(&bar0->xmsi_address);
3443
3444 if(val64 != valt) {
3445 int i = 0;
3446 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3447 0x0081810000818100ULL, /* FE=1, SE=0 */
3448 0x0042420000424200ULL, /* FE=0, SE=1 */
3449 0}; /* FE=0, SE=0 */
3450
3451 while(i<4) {
3452 writeq((value[i] | valr), &bar0->swapper_ctrl);
3453 writeq(valt, &bar0->xmsi_address);
3454 val64 = readq(&bar0->xmsi_address);
3455 if(val64 == valt)
3456 break;
3457 i++;
3458 }
3459 if(i == 4) {
20346722 3460 unsigned long long x = val64;
1da177e4 3461 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3462 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3463 return FAILURE;
3464 }
3465 }
3466 val64 = readq(&bar0->swapper_ctrl);
3467 val64 &= 0xFFFF000000000000ULL;
3468
3469#ifdef __BIG_ENDIAN
20346722 3470 /*
3471 * The device by default set to a big endian format, so a
1da177e4
LT		 3472 * big endian driver need not set anything.
3473 */
3474 val64 |= (SWAPPER_CTRL_TXP_FE |
3475 SWAPPER_CTRL_TXP_SE |
3476 SWAPPER_CTRL_TXD_R_FE |
3477 SWAPPER_CTRL_TXD_W_FE |
3478 SWAPPER_CTRL_TXF_R_FE |
3479 SWAPPER_CTRL_RXD_R_FE |
3480 SWAPPER_CTRL_RXD_W_FE |
3481 SWAPPER_CTRL_RXF_W_FE |
3482 SWAPPER_CTRL_XMSI_FE |
1da177e4 3483 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3484 if (sp->intr_type == INTA)
cc6e7c44 3485 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3486 writeq(val64, &bar0->swapper_ctrl);
3487#else
20346722 3488 /*
1da177e4 3489 * Initially we enable all bits to make it accessible by the
20346722 3490 * driver, then we selectively enable only those bits that
1da177e4
LT		 3491 * we want to set.
3492 */
3493 val64 |= (SWAPPER_CTRL_TXP_FE |
3494 SWAPPER_CTRL_TXP_SE |
3495 SWAPPER_CTRL_TXD_R_FE |
3496 SWAPPER_CTRL_TXD_R_SE |
3497 SWAPPER_CTRL_TXD_W_FE |
3498 SWAPPER_CTRL_TXD_W_SE |
3499 SWAPPER_CTRL_TXF_R_FE |
3500 SWAPPER_CTRL_RXD_R_FE |
3501 SWAPPER_CTRL_RXD_R_SE |
3502 SWAPPER_CTRL_RXD_W_FE |
3503 SWAPPER_CTRL_RXD_W_SE |
3504 SWAPPER_CTRL_RXF_W_FE |
3505 SWAPPER_CTRL_XMSI_FE |
1da177e4 3506 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3507 if (sp->intr_type == INTA)
3508 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3509 writeq(val64, &bar0->swapper_ctrl);
3510#endif
3511 val64 = readq(&bar0->swapper_ctrl);
3512
20346722 3513 /*
3514 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3515 * feedback register.
3516 */
3517 val64 = readq(&bar0->pif_rd_swapper_fb);
3518 if (val64 != 0x0123456789ABCDEFULL) {
3519 /* Endian settings are incorrect, calls for another dekko. */
3520 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3521 dev->name);
3522 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3523 (unsigned long long) val64);
3524 return FAILURE;
3525 }
3526
3527 return SUCCESS;
3528}
3529
ac1f60db 3530static int wait_for_msix_trans(nic_t *nic, int i)
cc6e7c44 3531{
37eb47ed 3532 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3533 u64 val64;
3534 int ret = 0, cnt = 0;
3535
3536 do {
3537 val64 = readq(&bar0->xmsi_access);
3538 if (!(val64 & BIT(15)))
3539 break;
3540 mdelay(1);
3541 cnt++;
3542 } while(cnt < 5);
3543 if (cnt == 5) {
3544 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3545 ret = 1;
3546 }
3547
3548 return ret;
3549}
3550
26df54bf 3551static void restore_xmsi_data(nic_t *nic)
cc6e7c44 3552{
37eb47ed 3553 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3554 u64 val64;
3555 int i;
3556
75c30b13 3557 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3558 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3559 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3560 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3561 writeq(val64, &bar0->xmsi_access);
3562 if (wait_for_msix_trans(nic, i)) {
3563 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3564 continue;
3565 }
3566 }
3567}
3568
ac1f60db 3569static void store_xmsi_data(nic_t *nic)
cc6e7c44 3570{
37eb47ed 3571 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3572 u64 val64, addr, data;
3573 int i;
3574
3575 /* Store and display */
75c30b13 3576 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3577 val64 = (BIT(15) | vBIT(i, 26, 6));
3578 writeq(val64, &bar0->xmsi_access);
3579 if (wait_for_msix_trans(nic, i)) {
3580 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3581 continue;
3582 }
3583 addr = readq(&bar0->xmsi_address);
3584 data = readq(&bar0->xmsi_data);
3585 if (addr && data) {
3586 nic->msix_info[i].addr = addr;
3587 nic->msix_info[i].data = data;
3588 }
3589 }
3590}
3591
3592int s2io_enable_msi(nic_t *nic)
3593{
37eb47ed 3594 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3595 u16 msi_ctrl, msg_val;
3596 struct config_param *config = &nic->config;
3597 struct net_device *dev = nic->dev;
3598 u64 val64, tx_mat, rx_mat;
3599 int i, err;
3600
3601 val64 = readq(&bar0->pic_control);
3602 val64 &= ~BIT(1);
3603 writeq(val64, &bar0->pic_control);
3604
3605 err = pci_enable_msi(nic->pdev);
3606 if (err) {
3607 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3608 nic->dev->name);
3609 return err;
3610 }
3611
3612 /*
3613 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3614 * for interrupt handling.
3615 */
3616 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3617 msg_val ^= 0x1;
3618 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3619 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3620
3621 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3622 msi_ctrl |= 0x10;
3623 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3624
3625 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3626 tx_mat = readq(&bar0->tx_mat0_n[0]);
3627 for (i=0; i<config->tx_fifo_num; i++) {
3628 tx_mat |= TX_MAT_SET(i, 1);
3629 }
3630 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3631
3632 rx_mat = readq(&bar0->rx_mat);
3633 for (i=0; i<config->rx_ring_num; i++) {
3634 rx_mat |= RX_MAT_SET(i, 1);
3635 }
3636 writeq(rx_mat, &bar0->rx_mat);
3637
3638 dev->irq = nic->pdev->irq;
3639 return 0;
3640}
3641
26df54bf 3642static int s2io_enable_msi_x(nic_t *nic)
cc6e7c44 3643{
37eb47ed 3644 XENA_dev_config_t __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3645 u64 tx_mat, rx_mat;
3646 u16 msi_control; /* Temp variable */
3647 int ret, i, j, msix_indx = 1;
3648
3649 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3650 GFP_KERNEL);
3651 if (nic->entries == NULL) {
3652 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3653 return -ENOMEM;
3654 }
3655 memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3656
3657 nic->s2io_entries =
3658 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3659 GFP_KERNEL);
3660 if (nic->s2io_entries == NULL) {
3661 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3662 kfree(nic->entries);
3663 return -ENOMEM;
3664 }
3665 memset(nic->s2io_entries, 0,
3666 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3667
3668 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3669 nic->entries[i].entry = i;
3670 nic->s2io_entries[i].entry = i;
3671 nic->s2io_entries[i].arg = NULL;
3672 nic->s2io_entries[i].in_use = 0;
3673 }
3674
3675 tx_mat = readq(&bar0->tx_mat0_n[0]);
3676 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3677 tx_mat |= TX_MAT_SET(i, msix_indx);
3678 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3679 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3680 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3681 }
3682 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3683
3684 if (!nic->config.bimodal) {
3685 rx_mat = readq(&bar0->rx_mat);
3686 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3687 rx_mat |= RX_MAT_SET(j, msix_indx);
3688 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3689 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3690 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3691 }
3692 writeq(rx_mat, &bar0->rx_mat);
3693 } else {
3694 tx_mat = readq(&bar0->tx_mat0_n[7]);
3695 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3696 tx_mat |= TX_MAT_SET(i, msix_indx);
3697 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3698 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3699 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3700 }
3701 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3702 }
3703
c92ca04b 3704 nic->avail_msix_vectors = 0;
cc6e7c44 3705 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3706 /* We fail init if error or we get less vectors than min required */
3707 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3708 nic->avail_msix_vectors = ret;
3709 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3710 }
cc6e7c44
RA		 3711 if (ret) {
3712 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3713 kfree(nic->entries);
3714 kfree(nic->s2io_entries);
3715 nic->entries = NULL;
3716 nic->s2io_entries = NULL;
c92ca04b 3717 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3718 return -ENOMEM;
3719 }
c92ca04b
AR		 3720 if (!nic->avail_msix_vectors)
3721 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3722
3723 /*
3724 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3725 * in the herc NIC. (Temp change, needs to be removed later)
3726 */
3727 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3728 msi_control |= 0x1; /* Enable MSI */
3729 pci_write_config_word(nic->pdev, 0x42, msi_control);
3730
3731 return 0;
3732}
3733
1da177e4
LT		 3734/* ********************************************************* *
3735 * Functions defined below concern the OS part of the driver *
3736 * ********************************************************* */
3737
20346722 3738/**
1da177e4
LT		 3739 * s2io_open - open entry point of the driver
3740 * @dev : pointer to the device structure.
3741 * Description:
3742 * This function is the open entry point of the driver. It mainly calls a
3743 * function to allocate Rx buffers and inserts them into the buffer
20346722 3744 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3745 * Return value:
3746 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3747 * file on failure.
3748 */
3749
ac1f60db 3750static int s2io_open(struct net_device *dev)
1da177e4
LT		 3751{
3752 nic_t *sp = dev->priv;
3753 int err = 0;
3754
20346722 3755 /*
3756 * Make sure you have link off by default every time
1da177e4
LT		 3757 * Nic is initialized
3758 */
3759 netif_carrier_off(dev);
0b1f7ebe 3760 sp->last_link_state = 0;
1da177e4
LT		 3761
3762 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3763 err = s2io_card_up(sp);
3764 if (err) {
1da177e4
LT		 3765 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3766 dev->name);
e6a8fee2 3767 goto hw_init_failed;
1da177e4
LT		 3768 }
3769
3770 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3771 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3772 s2io_card_down(sp);
20346722 3773 err = -ENODEV;
e6a8fee2 3774 goto hw_init_failed;
1da177e4
LT		 3775 }
3776
3777 netif_start_queue(dev);
3778 return 0;
20346722 3779
20346722 3780hw_init_failed:
cc6e7c44
RA		 3781 if (sp->intr_type == MSI_X) {
3782 if (sp->entries)
3783 kfree(sp->entries);
3784 if (sp->s2io_entries)
3785 kfree(sp->s2io_entries);
3786 }
20346722 3787 return err;
1da177e4
LT		 3788}
3789
3790/**
3791 * s2io_close -close entry point of the driver
3792 * @dev : device pointer.
3793 * Description:
3794 * This is the stop entry point of the driver. It needs to undo exactly
3795 * whatever was done by the open entry point,thus it's usually referred to
3796 * as the close function.Among other things this function mainly stops the
3797 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3798 * Return value:
3799 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3800 * file on failure.
3801 */
3802
ac1f60db 3803static int s2io_close(struct net_device *dev)
1da177e4
LT		 3804{
3805 nic_t *sp = dev->priv;
cc6e7c44 3806
1da177e4
LT		 3807 flush_scheduled_work();
3808 netif_stop_queue(dev);
3809 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3810 s2io_card_down(sp);
cc6e7c44 3811
1da177e4
LT		 3812 sp->device_close_flag = TRUE; /* Device is shut down. */
3813 return 0;
3814}
3815
3816/**
3817 * s2io_xmit - Tx entry point of te driver
3818 * @skb : the socket buffer containing the Tx data.
3819 * @dev : device pointer.
3820 * Description :
3821 * This function is the Tx entry point of the driver. S2IO NIC supports
3822 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3823 * NOTE: when device cant queue the pkt,just the trans_start variable will
3824 * not be upadted.
3825 * Return value:
3826 * 0 on success & 1 on failure.
3827 */
3828
ac1f60db 3829static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 3830{
3831 nic_t *sp = dev->priv;
3832 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3833 register u64 val64;
3834 TxD_t *txdp;
3835 TxFIFO_element_t __iomem *tx_fifo;
3836 unsigned long flags;
be3a6b02 3837 u16 vlan_tag = 0;
3838 int vlan_priority = 0;
1da177e4
LT		 3839 mac_info_t *mac_control;
3840 struct config_param *config;
75c30b13 3841 int offload_type;
1da177e4
LT		 3842
3843 mac_control = &sp->mac_control;
3844 config = &sp->config;
3845
20346722 3846 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
1da177e4 3847 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 3848 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 3849 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3850 dev->name);
3851 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722 3852 dev_kfree_skb(skb);
3853 return 0;
1da177e4
LT		 3854 }
3855
3856 queue = 0;
1da177e4 3857
be3a6b02 3858 /* Get Fifo number to Transmit based on vlan priority */
3859 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3860 vlan_tag = vlan_tx_tag_get(skb);
3861 vlan_priority = vlan_tag >> 13;
3862 queue = config->fifo_mapping[vlan_priority];
3863 }
3864
20346722 3865 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3866 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3867 txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3868 list_virt_addr;
3869
3870 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3871 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3872 if (txdp->Host_Control ||
3873 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3874 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3875 netif_stop_queue(dev);
3876 dev_kfree_skb(skb);
3877 spin_unlock_irqrestore(&sp->tx_lock, flags);
3878 return 0;
3879 }
0b1f7ebe 3880
3881 /* A buffer with no data will be dropped */
3882 if (!skb->len) {
3883 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3884 dev_kfree_skb(skb);
3885 spin_unlock_irqrestore(&sp->tx_lock, flags);
3886 return 0;
3887 }
3888
75c30b13 3889 offload_type = s2io_offload_type(skb);
1da177e4 3890#ifdef NETIF_F_TSO
75c30b13 3891 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3892 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 3893 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4
LT		 3894 }
3895#endif
84fa7933 3896 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 3897 txdp->Control_2 |=
3898 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3899 TXD_TX_CKO_UDP_EN);
3900 }
fed5eccd
AR		 3901 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3902 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 3903 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 3904
be3a6b02 3905 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3906 txdp->Control_2 |= TXD_VLAN_ENABLE;
3907 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3908 }
3909
fed5eccd 3910 frg_len = skb->len - skb->data_len;
75c30b13 3911 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 3912 int ufo_size;
3913
75c30b13 3914 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 3915 ufo_size &= ~7;
3916 txdp->Control_1 |= TXD_UFO_EN;
3917 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3918 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3919#ifdef __BIG_ENDIAN
3920 sp->ufo_in_band_v[put_off] =
3921 (u64)skb_shinfo(skb)->ip6_frag_id;
3922#else
3923 sp->ufo_in_band_v[put_off] =
3924 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3925#endif
3926 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3927 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3928 sp->ufo_in_band_v,
3929 sizeof(u64), PCI_DMA_TODEVICE);
3930 txdp++;
fed5eccd 3931 }
1da177e4 3932
fed5eccd
AR		 3933 txdp->Buffer_Pointer = pci_map_single
3934 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3935 txdp->Host_Control = (unsigned long) skb;
3936 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 3937 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3938 txdp->Control_1 |= TXD_UFO_EN;
3939
3940 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 3941 /* For fragmented SKB. */
3942 for (i = 0; i < frg_cnt; i++) {
3943 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 3944 /* A '0' length fragment will be ignored */
3945 if (!frag->size)
3946 continue;
1da177e4
LT		 3947 txdp++;
3948 txdp->Buffer_Pointer = (u64) pci_map_page
3949 (sp->pdev, frag->page, frag->page_offset,
3950 frag->size, PCI_DMA_TODEVICE);
efd51b5c 3951 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 3952 if (offload_type == SKB_GSO_UDP)
fed5eccd 3953 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 3954 }
3955 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3956
75c30b13 3957 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3958 frg_cnt++; /* as Txd0 was used for inband header */
3959
1da177e4 3960 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 3961 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 3962 writeq(val64, &tx_fifo->TxDL_Pointer);
3963
3964 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3965 TX_FIFO_LAST_LIST);
75c30b13 3966 if (offload_type)
fed5eccd 3967 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 3968
1da177e4
LT		 3969 writeq(val64, &tx_fifo->List_Control);
3970
303bcb4b 3971 mmiowb();
3972
1da177e4 3973 put_off++;
863c11a9
AR		 3974 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3975 put_off = 0;
20346722 3976 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 3977
3978 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 3979 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 3980 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 3981 DBG_PRINT(TX_DBG,
3982 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3983 put_off, get_off);
3984 netif_stop_queue(dev);
3985 }
3986
3987 dev->trans_start = jiffies;
3988 spin_unlock_irqrestore(&sp->tx_lock, flags);
3989
3990 return 0;
3991}
3992
25fff88e 3993static void
3994s2io_alarm_handle(unsigned long data)
3995{
3996 nic_t *sp = (nic_t *)data;
3997
3998 alarm_intr_handler(sp);
3999 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4000}
4001
75c30b13
AR		 4002static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4003{
4004 int rxb_size, level;
4005
4006 if (!sp->lro) {
4007 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4008 level = rx_buffer_level(sp, rxb_size, rng_n);
4009
4010 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4011 int ret;
4012 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4013 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4014 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4015 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4016 __FUNCTION__);
4017 clear_bit(0, (&sp->tasklet_status));
4018 return -1;
4019 }
4020 clear_bit(0, (&sp->tasklet_status));
4021 } else if (level == LOW)
4022 tasklet_schedule(&sp->task);
4023
4024 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4025 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4026 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4027 }
4028 return 0;
4029}
4030
7d12e780 4031static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
cc6e7c44
RA		 4032{
4033 struct net_device *dev = (struct net_device *) dev_id;
4034 nic_t *sp = dev->priv;
4035 int i;
cc6e7c44
RA		 4036 mac_info_t *mac_control;
4037 struct config_param *config;
4038
4039 atomic_inc(&sp->isr_cnt);
4040 mac_control = &sp->mac_control;
4041 config = &sp->config;
4042 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4043
4044 /* If Intr is because of Rx Traffic */
4045 for (i = 0; i < config->rx_ring_num; i++)
4046 rx_intr_handler(&mac_control->rings[i]);
4047
4048 /* If Intr is because of Tx Traffic */
4049 for (i = 0; i < config->tx_fifo_num; i++)
4050 tx_intr_handler(&mac_control->fifos[i]);
4051
4052 /*
4053 * If the Rx buffer count is below the panic threshold then
4054 * reallocate the buffers from the interrupt handler itself,
4055 * else schedule a tasklet to reallocate the buffers.
4056 */
75c30b13
AR		 4057 for (i = 0; i < config->rx_ring_num; i++)
4058 s2io_chk_rx_buffers(sp, i);
cc6e7c44
RA		 4059
4060 atomic_dec(&sp->isr_cnt);
4061 return IRQ_HANDLED;
4062}
4063
7d12e780 4064static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44
RA		 4065{
4066 ring_info_t *ring = (ring_info_t *)dev_id;
4067 nic_t *sp = ring->nic;
cc6e7c44
RA		 4068
4069 atomic_inc(&sp->isr_cnt);
cc6e7c44 4070
75c30b13
AR		 4071 rx_intr_handler(ring);
4072 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4073
cc6e7c44 4074 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4075 return IRQ_HANDLED;
4076}
4077
7d12e780 4078static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44
RA		 4079{
4080 fifo_info_t *fifo = (fifo_info_t *)dev_id;
4081 nic_t *sp = fifo->nic;
4082
4083 atomic_inc(&sp->isr_cnt);
4084 tx_intr_handler(fifo);
4085 atomic_dec(&sp->isr_cnt);
4086 return IRQ_HANDLED;
4087}
a371a07d 4088static void s2io_txpic_intr_handle(nic_t *sp)
4089{
509a2671 4090 XENA_dev_config_t __iomem *bar0 = sp->bar0;
a371a07d 4091 u64 val64;
4092
4093 val64 = readq(&bar0->pic_int_status);
4094 if (val64 & PIC_INT_GPIO) {
4095 val64 = readq(&bar0->gpio_int_reg);
4096 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4097 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4098 /*
4099 * This is unstable state so clear both up/down
4100 * interrupt and adapter to re-evaluate the link state.
4101 */
a371a07d 4102 val64 |= GPIO_INT_REG_LINK_DOWN;
4103 val64 |= GPIO_INT_REG_LINK_UP;
4104 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4105 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4106 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4107 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4108 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4109 }
c92ca04b
AR		 4110 else if (val64 & GPIO_INT_REG_LINK_UP) {
4111 val64 = readq(&bar0->adapter_status);
4112 if (verify_xena_quiescence(sp, val64,
4113 sp->device_enabled_once)) {
4114 /* Enable Adapter */
4115 val64 = readq(&bar0->adapter_control);
4116 val64 |= ADAPTER_CNTL_EN;
4117 writeq(val64, &bar0->adapter_control);
4118 val64 |= ADAPTER_LED_ON;
4119 writeq(val64, &bar0->adapter_control);
4120 if (!sp->device_enabled_once)
4121 sp->device_enabled_once = 1;
4122
4123 s2io_link(sp, LINK_UP);
4124 /*
4125 * unmask link down interrupt and mask link-up
4126 * intr
4127 */
4128 val64 = readq(&bar0->gpio_int_mask);
4129 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4130 val64 |= GPIO_INT_MASK_LINK_UP;
4131 writeq(val64, &bar0->gpio_int_mask);
4132
4133 }
4134 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4135 val64 = readq(&bar0->adapter_status);
4136 if (verify_xena_quiescence(sp, val64,
4137 sp->device_enabled_once)) {
4138 s2io_link(sp, LINK_DOWN);
4139 /* Link is down so unmaks link up interrupt */
4140 val64 = readq(&bar0->gpio_int_mask);
4141 val64 &= ~GPIO_INT_MASK_LINK_UP;
4142 val64 |= GPIO_INT_MASK_LINK_DOWN;
4143 writeq(val64, &bar0->gpio_int_mask);
4144 }
a371a07d 4145 }
4146 }
c92ca04b 4147 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4148}
4149
1da177e4
LT		 4150/**
4151 * s2io_isr - ISR handler of the device .
4152 * @irq: the irq of the device.
4153 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4154 * Description: This function is the ISR handler of the device. It
4155 * identifies the reason for the interrupt and calls the relevant
4156 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4157 * recv buffers, if their numbers are below the panic value which is
4158 * presently set to 25% of the original number of rcv buffers allocated.
4159 * Return value:
20346722 4160 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4161 * IRQ_NONE: will be returned if interrupt is not from our device
4162 */
7d12e780 4163static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4164{
4165 struct net_device *dev = (struct net_device *) dev_id;
4166 nic_t *sp = dev->priv;
4167 XENA_dev_config_t __iomem *bar0 = sp->bar0;
20346722 4168 int i;
5d3213cc 4169 u64 reason = 0, val64, org_mask;
1da177e4
LT		 4170 mac_info_t *mac_control;
4171 struct config_param *config;
4172
7ba013ac 4173 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4174 mac_control = &sp->mac_control;
4175 config = &sp->config;
4176
20346722 4177 /*
1da177e4
LT		 4178 * Identify the cause for interrupt and call the appropriate
4179 * interrupt handler. Causes for the interrupt could be;
4180 * 1. Rx of packet.
4181 * 2. Tx complete.
4182 * 3. Link down.
20346722 4183 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4184 */
4185 reason = readq(&bar0->general_int_status);
4186
4187 if (!reason) {
4188 /* The interrupt was not raised by Xena. */
7ba013ac 4189 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4190 return IRQ_NONE;
4191 }
4192
863c11a9 4193 val64 = 0xFFFFFFFFFFFFFFFFULL;
5d3213cc
AR		 4194 /* Store current mask before masking all interrupts */
4195 org_mask = readq(&bar0->general_int_mask);
4196 writeq(val64, &bar0->general_int_mask);
4197
1da177e4
LT		 4198#ifdef CONFIG_S2IO_NAPI
4199 if (reason & GEN_INTR_RXTRAFFIC) {
4200 if (netif_rx_schedule_prep(dev)) {
863c11a9 4201 writeq(val64, &bar0->rx_traffic_mask);
1da177e4
LT		 4202 __netif_rx_schedule(dev);
4203 }
4204 }
4205#else
863c11a9
AR		 4206 /*
4207 * Rx handler is called by default, without checking for the
4208 * cause of interrupt.
4209 * rx_traffic_int reg is an R1 register, writing all 1's
4210 * will ensure that the actual interrupt causing bit get's
4211 * cleared and hence a read can be avoided.
4212 */
4213 writeq(val64, &bar0->rx_traffic_int);
4214 for (i = 0; i < config->rx_ring_num; i++) {
4215 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4216 }
4217#endif
4218
863c11a9
AR		 4219 /*
4220 * tx_traffic_int reg is an R1 register, writing all 1's
4221 * will ensure that the actual interrupt causing bit get's
4222 * cleared and hence a read can be avoided.
4223 */
4224 writeq(val64, &bar0->tx_traffic_int);
fe113638 4225
863c11a9
AR		 4226 for (i = 0; i < config->tx_fifo_num; i++)
4227 tx_intr_handler(&mac_control->fifos[i]);
20346722 4228
a371a07d 4229 if (reason & GEN_INTR_TXPIC)
4230 s2io_txpic_intr_handle(sp);
20346722 4231 /*
4232 * If the Rx buffer count is below the panic threshold then
4233 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4234 * else schedule a tasklet to reallocate the buffers.
4235 */
4236#ifndef CONFIG_S2IO_NAPI
75c30b13
AR		 4237 for (i = 0; i < config->rx_ring_num; i++)
4238 s2io_chk_rx_buffers(sp, i);
1da177e4 4239#endif
5d3213cc 4240 writeq(org_mask, &bar0->general_int_mask);
7ba013ac 4241 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4242 return IRQ_HANDLED;
4243}
4244
7ba013ac 4245/**
4246 * s2io_updt_stats -
4247 */
4248static void s2io_updt_stats(nic_t *sp)
4249{
4250 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4251 u64 val64;
4252 int cnt = 0;
4253
4254 if (atomic_read(&sp->card_state) == CARD_UP) {
4255 /* Apprx 30us on a 133 MHz bus */
4256 val64 = SET_UPDT_CLICKS(10) |
4257 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4258 writeq(val64, &bar0->stat_cfg);
4259 do {
4260 udelay(100);
4261 val64 = readq(&bar0->stat_cfg);
4262 if (!(val64 & BIT(0)))
4263 break;
4264 cnt++;
4265 if (cnt == 5)
4266 break; /* Updt failed */
4267 } while(1);
75c30b13
AR		 4268 } else {
4269 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
7ba013ac 4270 }
4271}
4272
1da177e4 4273/**
20346722 4274 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4275 * @dev : pointer to the device structure.
4276 * Description:
20346722 4277 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4278 * structure and returns a pointer to the same.
4279 * Return value:
4280 * pointer to the updated net_device_stats structure.
4281 */
4282
ac1f60db 4283static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4
LT		 4284{
4285 nic_t *sp = dev->priv;
4286 mac_info_t *mac_control;
4287 struct config_param *config;
4288
20346722 4289
1da177e4
LT		 4290 mac_control = &sp->mac_control;
4291 config = &sp->config;
4292
7ba013ac 4293 /* Configure Stats for immediate updt */
4294 s2io_updt_stats(sp);
4295
4296 sp->stats.tx_packets =
4297 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722 4298 sp->stats.tx_errors =
4299 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4300 sp->stats.rx_errors =
ee705dba 4301 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722 4302 sp->stats.multicast =
4303 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4304 sp->stats.rx_length_errors =
ee705dba 4305 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4306
4307 return (&sp->stats);
4308}
4309
4310/**
4311 * s2io_set_multicast - entry point for multicast address enable/disable.
4312 * @dev : pointer to the device structure
4313 * Description:
20346722 4314 * This function is a driver entry point which gets called by the kernel
4315 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4316 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4317 * determine, if multicast address must be enabled or if promiscuous mode
4318 * is to be disabled etc.
4319 * Return value:
4320 * void.
4321 */
4322
4323static void s2io_set_multicast(struct net_device *dev)
4324{
4325 int i, j, prev_cnt;
4326 struct dev_mc_list *mclist;
4327 nic_t *sp = dev->priv;
4328 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4329 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4330 0xfeffffffffffULL;
4331 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4332 void __iomem *add;
4333
4334 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4335 /* Enable all Multicast addresses */
4336 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4337 &bar0->rmac_addr_data0_mem);
4338 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4339 &bar0->rmac_addr_data1_mem);
4340 val64 = RMAC_ADDR_CMD_MEM_WE |
4341 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4342 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4343 writeq(val64, &bar0->rmac_addr_cmd_mem);
4344 /* Wait till command completes */
c92ca04b
AR		 4345 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4346 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 4347
4348 sp->m_cast_flg = 1;
4349 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4350 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4351 /* Disable all Multicast addresses */
4352 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4353 &bar0->rmac_addr_data0_mem);
5e25b9dd 4354 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4355 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4356 val64 = RMAC_ADDR_CMD_MEM_WE |
4357 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4358 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4359 writeq(val64, &bar0->rmac_addr_cmd_mem);
4360 /* Wait till command completes */
c92ca04b
AR		 4361 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4362 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 4363
4364 sp->m_cast_flg = 0;
4365 sp->all_multi_pos = 0;
4366 }
4367
4368 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4369 /* Put the NIC into promiscuous mode */
4370 add = &bar0->mac_cfg;
4371 val64 = readq(&bar0->mac_cfg);
4372 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4373
4374 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4375 writel((u32) val64, add);
4376 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4377 writel((u32) (val64 >> 32), (add + 4));
4378
4379 val64 = readq(&bar0->mac_cfg);
4380 sp->promisc_flg = 1;
776bd20f 4381 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4382 dev->name);
4383 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4384 /* Remove the NIC from promiscuous mode */
4385 add = &bar0->mac_cfg;
4386 val64 = readq(&bar0->mac_cfg);
4387 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4388
4389 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4390 writel((u32) val64, add);
4391 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4392 writel((u32) (val64 >> 32), (add + 4));
4393
4394 val64 = readq(&bar0->mac_cfg);
4395 sp->promisc_flg = 0;
776bd20f 4396 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4397 dev->name);
4398 }
4399
4400 /* Update individual M_CAST address list */
4401 if ((!sp->m_cast_flg) && dev->mc_count) {
4402 if (dev->mc_count >
4403 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4404 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4405 dev->name);
4406 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4407 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4408 return;
4409 }
4410
4411 prev_cnt = sp->mc_addr_count;
4412 sp->mc_addr_count = dev->mc_count;
4413
4414 /* Clear out the previous list of Mc in the H/W. */
4415 for (i = 0; i < prev_cnt; i++) {
4416 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4417 &bar0->rmac_addr_data0_mem);
4418 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4419 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4420 val64 = RMAC_ADDR_CMD_MEM_WE |
4421 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4422 RMAC_ADDR_CMD_MEM_OFFSET
4423 (MAC_MC_ADDR_START_OFFSET + i);
4424 writeq(val64, &bar0->rmac_addr_cmd_mem);
4425
4426 /* Wait for command completes */
c92ca04b
AR		 4427 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4428 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4429 DBG_PRINT(ERR_DBG, "%s: Adding ",
4430 dev->name);
4431 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4432 return;
4433 }
4434 }
4435
4436 /* Create the new Rx filter list and update the same in H/W. */
4437 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4438 i++, mclist = mclist->next) {
4439 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4440 ETH_ALEN);
a7a80d5a 4441 mac_addr = 0;
1da177e4
LT		 4442 for (j = 0; j < ETH_ALEN; j++) {
4443 mac_addr |= mclist->dmi_addr[j];
4444 mac_addr <<= 8;
4445 }
4446 mac_addr >>= 8;
4447 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4448 &bar0->rmac_addr_data0_mem);
4449 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4450 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4451 val64 = RMAC_ADDR_CMD_MEM_WE |
4452 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4453 RMAC_ADDR_CMD_MEM_OFFSET
4454 (i + MAC_MC_ADDR_START_OFFSET);
4455 writeq(val64, &bar0->rmac_addr_cmd_mem);
4456
4457 /* Wait for command completes */
c92ca04b
AR		 4458 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4459 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4460 DBG_PRINT(ERR_DBG, "%s: Adding ",
4461 dev->name);
4462 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4463 return;
4464 }
4465 }
4466 }
4467}
4468
4469/**
20346722 4470 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4471 * @dev : pointer to the device structure.
4472 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4473 * Description : This procedure will program the Xframe to receive
1da177e4 4474 * frames with new Mac Address
20346722 4475 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4476 * as defined in errno.h file on failure.
4477 */
4478
26df54bf 4479static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4
LT		 4480{
4481 nic_t *sp = dev->priv;
4482 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4483 register u64 val64, mac_addr = 0;
4484 int i;
4485
20346722 4486 /*
1da177e4
LT		 4487 * Set the new MAC address as the new unicast filter and reflect this
4488 * change on the device address registered with the OS. It will be
20346722 4489 * at offset 0.
1da177e4
LT		 4490 */
4491 for (i = 0; i < ETH_ALEN; i++) {
4492 mac_addr <<= 8;
4493 mac_addr |= addr[i];
4494 }
4495
4496 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4497 &bar0->rmac_addr_data0_mem);
4498
4499 val64 =
4500 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4501 RMAC_ADDR_CMD_MEM_OFFSET(0);
4502 writeq(val64, &bar0->rmac_addr_cmd_mem);
4503 /* Wait till command completes */
c92ca04b
AR		 4504 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4505 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
1da177e4
LT		 4506 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4507 return FAILURE;
4508 }
4509
4510 return SUCCESS;
4511}
4512
4513/**
20346722 4514 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4515 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4516 * @info: pointer to the structure with parameters given by ethtool to set
4517 * link information.
4518 * Description:
20346722 4519 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4520 * the NIC.
4521 * Return value:
4522 * 0 on success.
4523*/
4524
4525static int s2io_ethtool_sset(struct net_device *dev,
4526 struct ethtool_cmd *info)
4527{
4528 nic_t *sp = dev->priv;
4529 if ((info->autoneg == AUTONEG_ENABLE) ||
4530 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4531 return -EINVAL;
4532 else {
4533 s2io_close(sp->dev);
4534 s2io_open(sp->dev);
4535 }
4536
4537 return 0;
4538}
4539
4540/**
20346722 4541 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4542 * @sp : private member of the device structure, pointer to the
4543 * s2io_nic structure.
4544 * @info : pointer to the structure with parameters given by ethtool
4545 * to return link information.
4546 * Description:
4547 * Returns link specific information like speed, duplex etc.. to ethtool.
4548 * Return value :
4549 * return 0 on success.
4550 */
4551
4552static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4553{
4554 nic_t *sp = dev->priv;
4555 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4556 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4557 info->port = PORT_FIBRE;
4558 /* info->transceiver?? TODO */
4559
4560 if (netif_carrier_ok(sp->dev)) {
4561 info->speed = 10000;
4562 info->duplex = DUPLEX_FULL;
4563 } else {
4564 info->speed = -1;
4565 info->duplex = -1;
4566 }
4567
4568 info->autoneg = AUTONEG_DISABLE;
4569 return 0;
4570}
4571
4572/**
20346722 4573 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4574 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4575 * s2io_nic structure.
4576 * @info : pointer to the structure with parameters given by ethtool to
4577 * return driver information.
4578 * Description:
4579 * Returns driver specefic information like name, version etc.. to ethtool.
4580 * Return value:
4581 * void
4582 */
4583
4584static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4585 struct ethtool_drvinfo *info)
4586{
4587 nic_t *sp = dev->priv;
4588
dbc2309d
JL		 4589 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4590 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4591 strncpy(info->fw_version, "", sizeof(info->fw_version));
4592 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4593 info->regdump_len = XENA_REG_SPACE;
4594 info->eedump_len = XENA_EEPROM_SPACE;
4595 info->testinfo_len = S2IO_TEST_LEN;
4596 info->n_stats = S2IO_STAT_LEN;
4597}
4598
4599/**
4600 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4601 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4602 * s2io_nic structure.
20346722 4603 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4604 * dumping the registers.
4605 * @reg_space: The input argumnet into which all the registers are dumped.
4606 * Description:
4607 * Dumps the entire register space of xFrame NIC into the user given
4608 * buffer area.
4609 * Return value :
4610 * void .
4611*/
4612
4613static void s2io_ethtool_gregs(struct net_device *dev,
4614 struct ethtool_regs *regs, void *space)
4615{
4616 int i;
4617 u64 reg;
4618 u8 *reg_space = (u8 *) space;
4619 nic_t *sp = dev->priv;
4620
4621 regs->len = XENA_REG_SPACE;
4622 regs->version = sp->pdev->subsystem_device;
4623
4624 for (i = 0; i < regs->len; i += 8) {
4625 reg = readq(sp->bar0 + i);
4626 memcpy((reg_space + i), &reg, 8);
4627 }
4628}
4629
4630/**
4631 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4632 * @data : address of the private member of the device structure, which
1da177e4 4633 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 4634 * Description: This is actually the timer function that alternates the
4635 * adapter LED bit of the adapter control bit to set/reset every time on
4636 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4637 * once every second.
4638*/
4639static void s2io_phy_id(unsigned long data)
4640{
4641 nic_t *sp = (nic_t *) data;
4642 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4643 u64 val64 = 0;
4644 u16 subid;
4645
4646 subid = sp->pdev->subsystem_device;
541ae68f 4647 if ((sp->device_type == XFRAME_II_DEVICE) ||
4648 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4649 val64 = readq(&bar0->gpio_control);
4650 val64 ^= GPIO_CTRL_GPIO_0;
4651 writeq(val64, &bar0->gpio_control);
4652 } else {
4653 val64 = readq(&bar0->adapter_control);
4654 val64 ^= ADAPTER_LED_ON;
4655 writeq(val64, &bar0->adapter_control);
4656 }
4657
4658 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4659}
4660
4661/**
4662 * s2io_ethtool_idnic - To physically identify the nic on the system.
4663 * @sp : private member of the device structure, which is a pointer to the
4664 * s2io_nic structure.
20346722 4665 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4666 * ethtool.
4667 * Description: Used to physically identify the NIC on the system.
20346722 4668 * The Link LED will blink for a time specified by the user for
1da177e4 4669 * identification.
20346722 4670 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4671 * identification is possible only if it's link is up.
4672 * Return value:
4673 * int , returns 0 on success
4674 */
4675
4676static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4677{
4678 u64 val64 = 0, last_gpio_ctrl_val;
4679 nic_t *sp = dev->priv;
4680 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4681 u16 subid;
4682
4683 subid = sp->pdev->subsystem_device;
4684 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f 4685 if ((sp->device_type == XFRAME_I_DEVICE) &&
4686 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4687 val64 = readq(&bar0->adapter_control);
4688 if (!(val64 & ADAPTER_CNTL_EN)) {
4689 printk(KERN_ERR
4690 "Adapter Link down, cannot blink LED\n");
4691 return -EFAULT;
4692 }
4693 }
4694 if (sp->id_timer.function == NULL) {
4695 init_timer(&sp->id_timer);
4696 sp->id_timer.function = s2io_phy_id;
4697 sp->id_timer.data = (unsigned long) sp;
4698 }
4699 mod_timer(&sp->id_timer, jiffies);
4700 if (data)
20346722 4701 msleep_interruptible(data * HZ);
1da177e4 4702 else
20346722 4703 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4704 del_timer_sync(&sp->id_timer);
4705
541ae68f 4706 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4707 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4708 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4709 }
4710
4711 return 0;
4712}
4713
4714/**
4715 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 4716 * @sp : private member of the device structure, which is a pointer to the
4717 * s2io_nic structure.
1da177e4
LT		 4718 * @ep : pointer to the structure with pause parameters given by ethtool.
4719 * Description:
4720 * Returns the Pause frame generation and reception capability of the NIC.
4721 * Return value:
4722 * void
4723 */
4724static void s2io_ethtool_getpause_data(struct net_device *dev,
4725 struct ethtool_pauseparam *ep)
4726{
4727 u64 val64;
4728 nic_t *sp = dev->priv;
4729 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4730
4731 val64 = readq(&bar0->rmac_pause_cfg);
4732 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4733 ep->tx_pause = TRUE;
4734 if (val64 & RMAC_PAUSE_RX_ENABLE)
4735 ep->rx_pause = TRUE;
4736 ep->autoneg = FALSE;
4737}
4738
4739/**
4740 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4741 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4742 * s2io_nic structure.
4743 * @ep : pointer to the structure with pause parameters given by ethtool.
4744 * Description:
4745 * It can be used to set or reset Pause frame generation or reception
4746 * support of the NIC.
4747 * Return value:
4748 * int, returns 0 on Success
4749 */
4750
4751static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4752 struct ethtool_pauseparam *ep)
1da177e4
LT		 4753{
4754 u64 val64;
4755 nic_t *sp = dev->priv;
4756 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4757
4758 val64 = readq(&bar0->rmac_pause_cfg);
4759 if (ep->tx_pause)
4760 val64 |= RMAC_PAUSE_GEN_ENABLE;
4761 else
4762 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4763 if (ep->rx_pause)
4764 val64 |= RMAC_PAUSE_RX_ENABLE;
4765 else
4766 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4767 writeq(val64, &bar0->rmac_pause_cfg);
4768 return 0;
4769}
4770
4771/**
4772 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 4773 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4774 * s2io_nic structure.
4775 * @off : offset at which the data must be written
4776 * @data : Its an output parameter where the data read at the given
20346722 4777 * offset is stored.
1da177e4 4778 * Description:
20346722 4779 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 4780 * read data.
4781 * NOTE: Will allow to read only part of the EEPROM visible through the
4782 * I2C bus.
4783 * Return value:
4784 * -1 on failure and 0 on success.
4785 */
4786
4787#define S2IO_DEV_ID 5
ad4ebed0 4788static int read_eeprom(nic_t * sp, int off, u64 * data)
1da177e4
LT		 4789{
4790 int ret = -1;
4791 u32 exit_cnt = 0;
4792 u64 val64;
4793 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4794
ad4ebed0 4795 if (sp->device_type == XFRAME_I_DEVICE) {
4796 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4797 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4798 I2C_CONTROL_CNTL_START;
4799 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 4800
ad4ebed0 4801 while (exit_cnt < 5) {
4802 val64 = readq(&bar0->i2c_control);
4803 if (I2C_CONTROL_CNTL_END(val64)) {
4804 *data = I2C_CONTROL_GET_DATA(val64);
4805 ret = 0;
4806 break;
4807 }
4808 msleep(50);
4809 exit_cnt++;
1da177e4 4810 }
1da177e4
LT		 4811 }
4812
ad4ebed0 4813 if (sp->device_type == XFRAME_II_DEVICE) {
4814 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4815 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 4816 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4817 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4818 val64 |= SPI_CONTROL_REQ;
4819 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4820 while (exit_cnt < 5) {
4821 val64 = readq(&bar0->spi_control);
4822 if (val64 & SPI_CONTROL_NACK) {
4823 ret = 1;
4824 break;
4825 } else if (val64 & SPI_CONTROL_DONE) {
4826 *data = readq(&bar0->spi_data);
4827 *data &= 0xffffff;
4828 ret = 0;
4829 break;
4830 }
4831 msleep(50);
4832 exit_cnt++;
4833 }
4834 }
1da177e4
LT		 4835 return ret;
4836}
4837
4838/**
4839 * write_eeprom - actually writes the relevant part of the data value.
4840 * @sp : private member of the device structure, which is a pointer to the
4841 * s2io_nic structure.
4842 * @off : offset at which the data must be written
4843 * @data : The data that is to be written
20346722 4844 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 4845 * the Eeprom. (max of 3)
4846 * Description:
4847 * Actually writes the relevant part of the data value into the Eeprom
4848 * through the I2C bus.
4849 * Return value:
4850 * 0 on success, -1 on failure.
4851 */
4852
ad4ebed0 4853static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
1da177e4
LT		 4854{
4855 int exit_cnt = 0, ret = -1;
4856 u64 val64;
4857 XENA_dev_config_t __iomem *bar0 = sp->bar0;
4858
ad4ebed0 4859 if (sp->device_type == XFRAME_I_DEVICE) {
4860 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4861 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4862 I2C_CONTROL_CNTL_START;
4863 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4864
4865 while (exit_cnt < 5) {
4866 val64 = readq(&bar0->i2c_control);
4867 if (I2C_CONTROL_CNTL_END(val64)) {
4868 if (!(val64 & I2C_CONTROL_NACK))
4869 ret = 0;
4870 break;
4871 }
4872 msleep(50);
4873 exit_cnt++;
4874 }
4875 }
1da177e4 4876
ad4ebed0 4877 if (sp->device_type == XFRAME_II_DEVICE) {
4878 int write_cnt = (cnt == 8) ? 0 : cnt;
4879 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4880
4881 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4882 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 4883 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4884 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4885 val64 |= SPI_CONTROL_REQ;
4886 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4887 while (exit_cnt < 5) {
4888 val64 = readq(&bar0->spi_control);
4889 if (val64 & SPI_CONTROL_NACK) {
4890 ret = 1;
4891 break;
4892 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 4893 ret = 0;
ad4ebed0 4894 break;
4895 }
4896 msleep(50);
4897 exit_cnt++;
1da177e4 4898 }
1da177e4 4899 }
1da177e4
LT		 4900 return ret;
4901}
9dc737a7
AR		 4902static void s2io_vpd_read(nic_t *nic)
4903{
b41477f3
AR		 4904 u8 *vpd_data;
4905 u8 data;
9dc737a7
AR		 4906 int i=0, cnt, fail = 0;
4907 int vpd_addr = 0x80;
4908
4909 if (nic->device_type == XFRAME_II_DEVICE) {
4910 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4911 vpd_addr = 0x80;
4912 }
4913 else {
4914 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4915 vpd_addr = 0x50;
4916 }
4917
b41477f3
AR		 4918 vpd_data = kmalloc(256, GFP_KERNEL);
4919 if (!vpd_data)
4920 return;
4921
9dc737a7
AR		 4922 for (i = 0; i < 256; i +=4 ) {
4923 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4924 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
4925 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4926 for (cnt = 0; cnt <5; cnt++) {
4927 msleep(2);
4928 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4929 if (data == 0x80)
4930 break;
4931 }
4932 if (cnt >= 5) {
4933 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4934 fail = 1;
4935 break;
4936 }
4937 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
4938 (u32 *)&vpd_data[i]);
4939 }
4940 if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4941 memset(nic->product_name, 0, vpd_data[1]);
4942 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4943 }
b41477f3 4944 kfree(vpd_data);
9dc737a7
AR		 4945}
4946
1da177e4
LT		 4947/**
4948 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4949 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 4950 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 4951 * containing all relevant information.
4952 * @data_buf : user defined value to be written into Eeprom.
4953 * Description: Reads the values stored in the Eeprom at given offset
4954 * for a given length. Stores these values int the input argument data
4955 * buffer 'data_buf' and returns these to the caller (ethtool.)
4956 * Return value:
4957 * int 0 on success
4958 */
4959
4960static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 4961 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 4962{
ad4ebed0 4963 u32 i, valid;
4964 u64 data;
1da177e4
LT		 4965 nic_t *sp = dev->priv;
4966
4967 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4968
4969 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4970 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4971
4972 for (i = 0; i < eeprom->len; i += 4) {
4973 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4974 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4975 return -EFAULT;
4976 }
4977 valid = INV(data);
4978 memcpy((data_buf + i), &valid, 4);
4979 }
4980 return 0;
4981}
4982
4983/**
4984 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4985 * @sp : private member of the device structure, which is a pointer to the
4986 * s2io_nic structure.
20346722 4987 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 4988 * containing all relevant information.
4989 * @data_buf ; user defined value to be written into Eeprom.
4990 * Description:
4991 * Tries to write the user provided value in the Eeprom, at the offset
4992 * given by the user.
4993 * Return value:
4994 * 0 on success, -EFAULT on failure.
4995 */
4996
4997static int s2io_ethtool_seeprom(struct net_device *dev,
4998 struct ethtool_eeprom *eeprom,
4999 u8 * data_buf)
5000{
5001 int len = eeprom->len, cnt = 0;
ad4ebed0 5002 u64 valid = 0, data;
1da177e4
LT		 5003 nic_t *sp = dev->priv;
5004
5005 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5006 DBG_PRINT(ERR_DBG,
5007 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5008 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5009 eeprom->magic);
5010 return -EFAULT;
5011 }
5012
5013 while (len) {
5014 data = (u32) data_buf[cnt] & 0x000000FF;
5015 if (data) {
5016 valid = (u32) (data << 24);
5017 } else
5018 valid = data;
5019
5020 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5021 DBG_PRINT(ERR_DBG,
5022 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5023 DBG_PRINT(ERR_DBG,
5024 "write into the specified offset\n");
5025 return -EFAULT;
5026 }
5027 cnt++;
5028 len--;
5029 }
5030
5031 return 0;
5032}
5033
5034/**
20346722 5035 * s2io_register_test - reads and writes into all clock domains.
5036 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5037 * s2io_nic structure.
5038 * @data : variable that returns the result of each of the test conducted b
5039 * by the driver.
5040 * Description:
5041 * Read and write into all clock domains. The NIC has 3 clock domains,
5042 * see that registers in all the three regions are accessible.
5043 * Return value:
5044 * 0 on success.
5045 */
5046
5047static int s2io_register_test(nic_t * sp, uint64_t * data)
5048{
5049 XENA_dev_config_t __iomem *bar0 = sp->bar0;
ad4ebed0 5050 u64 val64 = 0, exp_val;
1da177e4
LT		 5051 int fail = 0;
5052
20346722 5053 val64 = readq(&bar0->pif_rd_swapper_fb);
5054 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5055 fail = 1;
5056 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5057 }
5058
5059 val64 = readq(&bar0->rmac_pause_cfg);
5060 if (val64 != 0xc000ffff00000000ULL) {
5061 fail = 1;
5062 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5063 }
5064
5065 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5066 if (sp->device_type == XFRAME_II_DEVICE)
5067 exp_val = 0x0404040404040404ULL;
5068 else
5069 exp_val = 0x0808080808080808ULL;
5070 if (val64 != exp_val) {
1da177e4
LT		 5071 fail = 1;
5072 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5073 }
5074
5075 val64 = readq(&bar0->xgxs_efifo_cfg);
5076 if (val64 != 0x000000001923141EULL) {
5077 fail = 1;
5078 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5079 }
5080
5081 val64 = 0x5A5A5A5A5A5A5A5AULL;
5082 writeq(val64, &bar0->xmsi_data);
5083 val64 = readq(&bar0->xmsi_data);
5084 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5085 fail = 1;
5086 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5087 }
5088
5089 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5090 writeq(val64, &bar0->xmsi_data);
5091 val64 = readq(&bar0->xmsi_data);
5092 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5093 fail = 1;
5094 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5095 }
5096
5097 *data = fail;
ad4ebed0 5098 return fail;
1da177e4
LT		 5099}
5100
5101/**
20346722 5102 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5103 * @sp : private member of the device structure, which is a pointer to the
5104 * s2io_nic structure.
5105 * @data:variable that returns the result of each of the test conducted by
5106 * the driver.
5107 * Description:
20346722 5108 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5109 * register.
5110 * Return value:
5111 * 0 on success.
5112 */
5113
5114static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5115{
5116 int fail = 0;
ad4ebed0 5117 u64 ret_data, org_4F0, org_7F0;
5118 u8 saved_4F0 = 0, saved_7F0 = 0;
5119 struct net_device *dev = sp->dev;
1da177e4
LT		 5120
5121 /* Test Write Error at offset 0 */
ad4ebed0 5122 /* Note that SPI interface allows write access to all areas
5123 * of EEPROM. Hence doing all negative testing only for Xframe I.
5124 */
5125 if (sp->device_type == XFRAME_I_DEVICE)
5126 if (!write_eeprom(sp, 0, 0, 3))
5127 fail = 1;
5128
5129 /* Save current values at offsets 0x4F0 and 0x7F0 */
5130 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5131 saved_4F0 = 1;
5132 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5133 saved_7F0 = 1;
1da177e4
LT		 5134
5135 /* Test Write at offset 4f0 */
ad4ebed0 5136 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5137 fail = 1;
5138 if (read_eeprom(sp, 0x4F0, &ret_data))
5139 fail = 1;
5140
ad4ebed0 5141 if (ret_data != 0x012345) {
26b7625c
AM		 5142 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5143 "Data written %llx Data read %llx\n",
5144 dev->name, (unsigned long long)0x12345,
5145 (unsigned long long)ret_data);
1da177e4 5146 fail = 1;
ad4ebed0 5147 }
1da177e4
LT		 5148
5149 /* Reset the EEPROM data go FFFF */
ad4ebed0 5150 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5151
5152 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5153 if (sp->device_type == XFRAME_I_DEVICE)
5154 if (!write_eeprom(sp, 0x07C, 0, 3))
5155 fail = 1;
1da177e4 5156
ad4ebed0 5157 /* Test Write Request at offset 0x7f0 */
5158 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5159 fail = 1;
ad4ebed0 5160 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5161 fail = 1;
5162
ad4ebed0 5163 if (ret_data != 0x012345) {
26b7625c
AM		 5164 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5165 "Data written %llx Data read %llx\n",
5166 dev->name, (unsigned long long)0x12345,
5167 (unsigned long long)ret_data);
1da177e4 5168 fail = 1;
ad4ebed0 5169 }
1da177e4
LT		 5170
5171 /* Reset the EEPROM data go FFFF */
ad4ebed0 5172 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5173
ad4ebed0 5174 if (sp->device_type == XFRAME_I_DEVICE) {
5175 /* Test Write Error at offset 0x80 */
5176 if (!write_eeprom(sp, 0x080, 0, 3))
5177 fail = 1;
1da177e4 5178
ad4ebed0 5179 /* Test Write Error at offset 0xfc */
5180 if (!write_eeprom(sp, 0x0FC, 0, 3))
5181 fail = 1;
1da177e4 5182
ad4ebed0 5183 /* Test Write Error at offset 0x100 */
5184 if (!write_eeprom(sp, 0x100, 0, 3))
5185 fail = 1;
1da177e4 5186
ad4ebed0 5187 /* Test Write Error at offset 4ec */
5188 if (!write_eeprom(sp, 0x4EC, 0, 3))
5189 fail = 1;
5190 }
5191
5192 /* Restore values at offsets 0x4F0 and 0x7F0 */
5193 if (saved_4F0)
5194 write_eeprom(sp, 0x4F0, org_4F0, 3);
5195 if (saved_7F0)
5196 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5197
5198 *data = fail;
ad4ebed0 5199 return fail;
1da177e4
LT		 5200}
5201
5202/**
5203 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5204 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5205 * s2io_nic structure.
20346722 5206 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5207 * the driver.
5208 * Description:
5209 * This invokes the MemBist test of the card. We give around
5210 * 2 secs time for the Test to complete. If it's still not complete
20346722 5211 * within this peiod, we consider that the test failed.
1da177e4
LT		 5212 * Return value:
5213 * 0 on success and -1 on failure.
5214 */
5215
5216static int s2io_bist_test(nic_t * sp, uint64_t * data)
5217{
5218 u8 bist = 0;
5219 int cnt = 0, ret = -1;
5220
5221 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5222 bist |= PCI_BIST_START;
5223 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5224
5225 while (cnt < 20) {
5226 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5227 if (!(bist & PCI_BIST_START)) {
5228 *data = (bist & PCI_BIST_CODE_MASK);
5229 ret = 0;
5230 break;
5231 }
5232 msleep(100);
5233 cnt++;
5234 }
5235
5236 return ret;
5237}
5238
5239/**
20346722 5240 * s2io-link_test - verifies the link state of the nic
5241 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5242 * s2io_nic structure.
5243 * @data: variable that returns the result of each of the test conducted by
5244 * the driver.
5245 * Description:
20346722 5246 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5247 * argument 'data' appropriately.
5248 * Return value:
5249 * 0 on success.
5250 */
5251
5252static int s2io_link_test(nic_t * sp, uint64_t * data)
5253{
5254 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5255 u64 val64;
5256
5257 val64 = readq(&bar0->adapter_status);
c92ca04b 5258 if(!(LINK_IS_UP(val64)))
1da177e4 5259 *data = 1;
c92ca04b
AR		 5260 else
5261 *data = 0;
1da177e4 5262
b41477f3 5263 return *data;
1da177e4
LT		 5264}
5265
5266/**
20346722 5267 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5268 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5269 * s2io_nic structure.
20346722 5270 * @data - variable that returns the result of each of the test
1da177e4
LT		 5271 * conducted by the driver.
5272 * Description:
20346722 5273 * This is one of the offline test that tests the read and write
1da177e4
LT		 5274 * access to the RldRam chip on the NIC.
5275 * Return value:
5276 * 0 on success.
5277 */
5278
5279static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5280{
5281 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5282 u64 val64;
ad4ebed0 5283 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5284
5285 val64 = readq(&bar0->adapter_control);
5286 val64 &= ~ADAPTER_ECC_EN;
5287 writeq(val64, &bar0->adapter_control);
5288
5289 val64 = readq(&bar0->mc_rldram_test_ctrl);
5290 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5291 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5292
5293 val64 = readq(&bar0->mc_rldram_mrs);
5294 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5295 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5296
5297 val64 |= MC_RLDRAM_MRS_ENABLE;
5298 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5299
5300 while (iteration < 2) {
5301 val64 = 0x55555555aaaa0000ULL;
5302 if (iteration == 1) {
5303 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5304 }
5305 writeq(val64, &bar0->mc_rldram_test_d0);
5306
5307 val64 = 0xaaaa5a5555550000ULL;
5308 if (iteration == 1) {
5309 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5310 }
5311 writeq(val64, &bar0->mc_rldram_test_d1);
5312
5313 val64 = 0x55aaaaaaaa5a0000ULL;
5314 if (iteration == 1) {
5315 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5316 }
5317 writeq(val64, &bar0->mc_rldram_test_d2);
5318
ad4ebed0 5319 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5320 writeq(val64, &bar0->mc_rldram_test_add);
5321
ad4ebed0 5322 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5323 MC_RLDRAM_TEST_GO;
5324 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5325
5326 for (cnt = 0; cnt < 5; cnt++) {
5327 val64 = readq(&bar0->mc_rldram_test_ctrl);
5328 if (val64 & MC_RLDRAM_TEST_DONE)
5329 break;
5330 msleep(200);
5331 }
5332
5333 if (cnt == 5)
5334 break;
5335
ad4ebed0 5336 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5337 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5338
5339 for (cnt = 0; cnt < 5; cnt++) {
5340 val64 = readq(&bar0->mc_rldram_test_ctrl);
5341 if (val64 & MC_RLDRAM_TEST_DONE)
5342 break;
5343 msleep(500);
5344 }
5345
5346 if (cnt == 5)
5347 break;
5348
5349 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5350 if (!(val64 & MC_RLDRAM_TEST_PASS))
5351 test_fail = 1;
1da177e4
LT		 5352
5353 iteration++;
5354 }
5355
ad4ebed0 5356 *data = test_fail;
1da177e4 5357
ad4ebed0 5358 /* Bring the adapter out of test mode */
5359 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5360
5361 return test_fail;
1da177e4
LT		 5362}
5363
5364/**
5365 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5366 * @sp : private member of the device structure, which is a pointer to the
5367 * s2io_nic structure.
5368 * @ethtest : pointer to a ethtool command specific structure that will be
5369 * returned to the user.
20346722 5370 * @data : variable that returns the result of each of the test
1da177e4
LT		 5371 * conducted by the driver.
5372 * Description:
5373 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5374 * the health of the card.
5375 * Return value:
5376 * void
5377 */
5378
5379static void s2io_ethtool_test(struct net_device *dev,
5380 struct ethtool_test *ethtest,
5381 uint64_t * data)
5382{
5383 nic_t *sp = dev->priv;
5384 int orig_state = netif_running(sp->dev);
5385
5386 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5387 /* Offline Tests. */
20346722 5388 if (orig_state)
1da177e4 5389 s2io_close(sp->dev);
1da177e4
LT		 5390
5391 if (s2io_register_test(sp, &data[0]))
5392 ethtest->flags |= ETH_TEST_FL_FAILED;
5393
5394 s2io_reset(sp);
1da177e4
LT		 5395
5396 if (s2io_rldram_test(sp, &data[3]))
5397 ethtest->flags |= ETH_TEST_FL_FAILED;
5398
5399 s2io_reset(sp);
1da177e4
LT		 5400
5401 if (s2io_eeprom_test(sp, &data[1]))
5402 ethtest->flags |= ETH_TEST_FL_FAILED;
5403
5404 if (s2io_bist_test(sp, &data[4]))
5405 ethtest->flags |= ETH_TEST_FL_FAILED;
5406
5407 if (orig_state)
5408 s2io_open(sp->dev);
5409
5410 data[2] = 0;
5411 } else {
5412 /* Online Tests. */
5413 if (!orig_state) {
5414 DBG_PRINT(ERR_DBG,
5415 "%s: is not up, cannot run test\n",
5416 dev->name);
5417 data[0] = -1;
5418 data[1] = -1;
5419 data[2] = -1;
5420 data[3] = -1;
5421 data[4] = -1;
5422 }
5423
5424 if (s2io_link_test(sp, &data[2]))
5425 ethtest->flags |= ETH_TEST_FL_FAILED;
5426
5427 data[0] = 0;
5428 data[1] = 0;
5429 data[3] = 0;
5430 data[4] = 0;
5431 }
5432}
5433
5434static void s2io_get_ethtool_stats(struct net_device *dev,
5435 struct ethtool_stats *estats,
5436 u64 * tmp_stats)
5437{
5438 int i = 0;
5439 nic_t *sp = dev->priv;
5440 StatInfo_t *stat_info = sp->mac_control.stats_info;
5441
7ba013ac 5442 s2io_updt_stats(sp);
541ae68f 5443 tmp_stats[i++] =
5444 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5445 le32_to_cpu(stat_info->tmac_frms);
5446 tmp_stats[i++] =
5447 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5448 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5449 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f 5450 tmp_stats[i++] =
5451 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5452 le32_to_cpu(stat_info->tmac_mcst_frms);
5453 tmp_stats[i++] =
5454 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5455 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5456 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5457 tmp_stats[i++] =
5458 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5459 le32_to_cpu(stat_info->tmac_ttl_octets);
5460 tmp_stats[i++] =
5461 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5462 le32_to_cpu(stat_info->tmac_ucst_frms);
5463 tmp_stats[i++] =
5464 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5465 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f 5466 tmp_stats[i++] =
5467 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5468 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5469 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5470 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f 5471 tmp_stats[i++] =
5472 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5473 le32_to_cpu(stat_info->tmac_vld_ip);
5474 tmp_stats[i++] =
5475 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5476 le32_to_cpu(stat_info->tmac_drop_ip);
5477 tmp_stats[i++] =
5478 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5479 le32_to_cpu(stat_info->tmac_icmp);
5480 tmp_stats[i++] =
5481 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5482 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5483 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f 5484 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5485 le32_to_cpu(stat_info->tmac_udp);
5486 tmp_stats[i++] =
5487 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5488 le32_to_cpu(stat_info->rmac_vld_frms);
5489 tmp_stats[i++] =
5490 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5491 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5492 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5493 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f 5494 tmp_stats[i++] =
5495 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5496 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5497 tmp_stats[i++] =
5498 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5499 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5500 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5501 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5502 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5503 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5504 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5505 tmp_stats[i++] =
5506 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5507 le32_to_cpu(stat_info->rmac_ttl_octets);
5508 tmp_stats[i++] =
5509 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5510 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5511 tmp_stats[i++] =
5512 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5513 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f 5514 tmp_stats[i++] =
5515 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5516 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5517 tmp_stats[i++] =
5518 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5519 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5520 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5521 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f 5522 tmp_stats[i++] =
5523 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5524 le32_to_cpu(stat_info->rmac_usized_frms);
5525 tmp_stats[i++] =
5526 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5527 le32_to_cpu(stat_info->rmac_osized_frms);
5528 tmp_stats[i++] =
5529 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5530 le32_to_cpu(stat_info->rmac_frag_frms);
5531 tmp_stats[i++] =
5532 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5533 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5534 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5535 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5536 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5537 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5538 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5539 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5540 tmp_stats[i++] =
5541 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5542 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5543 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5544 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5545 tmp_stats[i++] =
5546 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5547 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5548 tmp_stats[i++] =
5549 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5550 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5551 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5552 tmp_stats[i++] =
5553 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f 5554 le32_to_cpu(stat_info->rmac_udp);
5555 tmp_stats[i++] =
5556 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5557 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5558 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5559 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5560 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5561 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5562 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5563 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5564 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5565 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5566 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5567 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5568 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5569 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5570 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5571 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5572 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5573 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5574 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f 5575 tmp_stats[i++] =
5576 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5577 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5578 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5579 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f 5580 tmp_stats[i++] =
5581 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5582 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5583 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5584 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5585 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5586 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5587 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5588 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5589 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5590 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5591 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5592 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5593 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5594 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5595 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5596 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5597 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5598 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5599 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5600 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5601 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5602 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5603 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5604 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5605 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5606 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5607 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5608 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5609 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5610 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5611 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5612 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5613 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5614 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5615 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5616 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5617 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
7ba013ac 5618 tmp_stats[i++] = 0;
5619 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5620 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5621 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5622 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5623 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5624 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5625 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5626 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5627 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5628 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5629 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5630 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5631 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5632 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5633 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5634 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5635 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5636 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5637 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5638 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5639 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5640 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5641 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5642 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5643 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5644 int count = 0;
6aa20a22 5645 /*
bd1034f0
AR		 5646 * Since 64-bit divide does not work on all platforms,
5647 * do repeated subtraction.
5648 */
5649 while (tmp >= stat_info->sw_stat.num_aggregations) {
5650 tmp -= stat_info->sw_stat.num_aggregations;
5651 count++;
5652 }
5653 tmp_stats[i++] = count;
fe931395 5654 }
bd1034f0
AR		 5655 else
5656 tmp_stats[i++] = 0;
1da177e4
LT		 5657}
5658
ac1f60db 5659static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5660{
5661 return (XENA_REG_SPACE);
5662}
5663
5664
ac1f60db 5665static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4
LT		 5666{
5667 nic_t *sp = dev->priv;
5668
5669 return (sp->rx_csum);
5670}
ac1f60db
AB		 5671
5672static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5673{
5674 nic_t *sp = dev->priv;
5675
5676 if (data)
5677 sp->rx_csum = 1;
5678 else
5679 sp->rx_csum = 0;
5680
5681 return 0;
5682}
ac1f60db
AB		 5683
5684static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5685{
5686 return (XENA_EEPROM_SPACE);
5687}
5688
ac1f60db 5689static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5690{
5691 return (S2IO_TEST_LEN);
5692}
ac1f60db
AB		 5693
5694static void s2io_ethtool_get_strings(struct net_device *dev,
5695 u32 stringset, u8 * data)
1da177e4
LT		 5696{
5697 switch (stringset) {
5698 case ETH_SS_TEST:
5699 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5700 break;
5701 case ETH_SS_STATS:
5702 memcpy(data, &ethtool_stats_keys,
5703 sizeof(ethtool_stats_keys));
5704 }
5705}
1da177e4
LT		 5706static int s2io_ethtool_get_stats_count(struct net_device *dev)
5707{
5708 return (S2IO_STAT_LEN);
5709}
5710
ac1f60db 5711static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5712{
5713 if (data)
5714 dev->features |= NETIF_F_IP_CSUM;
5715 else
5716 dev->features &= ~NETIF_F_IP_CSUM;
5717
5718 return 0;
5719}
5720
75c30b13
AR		 5721static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5722{
5723 return (dev->features & NETIF_F_TSO) != 0;
5724}
5725static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5726{
5727 if (data)
5728 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5729 else
5730 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5731
5732 return 0;
5733}
1da177e4 5734
7282d491 5735static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 5736 .get_settings = s2io_ethtool_gset,
5737 .set_settings = s2io_ethtool_sset,
5738 .get_drvinfo = s2io_ethtool_gdrvinfo,
5739 .get_regs_len = s2io_ethtool_get_regs_len,
5740 .get_regs = s2io_ethtool_gregs,
5741 .get_link = ethtool_op_get_link,
5742 .get_eeprom_len = s2io_get_eeprom_len,
5743 .get_eeprom = s2io_ethtool_geeprom,
5744 .set_eeprom = s2io_ethtool_seeprom,
5745 .get_pauseparam = s2io_ethtool_getpause_data,
5746 .set_pauseparam = s2io_ethtool_setpause_data,
5747 .get_rx_csum = s2io_ethtool_get_rx_csum,
5748 .set_rx_csum = s2io_ethtool_set_rx_csum,
5749 .get_tx_csum = ethtool_op_get_tx_csum,
5750 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5751 .get_sg = ethtool_op_get_sg,
5752 .set_sg = ethtool_op_set_sg,
5753#ifdef NETIF_F_TSO
75c30b13
AR		 5754 .get_tso = s2io_ethtool_op_get_tso,
5755 .set_tso = s2io_ethtool_op_set_tso,
1da177e4 5756#endif
fed5eccd
AR		 5757 .get_ufo = ethtool_op_get_ufo,
5758 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 5759 .self_test_count = s2io_ethtool_self_test_count,
5760 .self_test = s2io_ethtool_test,
5761 .get_strings = s2io_ethtool_get_strings,
5762 .phys_id = s2io_ethtool_idnic,
5763 .get_stats_count = s2io_ethtool_get_stats_count,
5764 .get_ethtool_stats = s2io_get_ethtool_stats
5765};
5766
5767/**
20346722 5768 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 5769 * @dev : Device pointer.
5770 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5771 * a proprietary structure used to pass information to the driver.
5772 * @cmd : This is used to distinguish between the different commands that
5773 * can be passed to the IOCTL functions.
5774 * Description:
20346722 5775 * Currently there are no special functionality supported in IOCTL, hence
5776 * function always return EOPNOTSUPPORTED
1da177e4
LT		 5777 */
5778
ac1f60db 5779static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 5780{
5781 return -EOPNOTSUPP;
5782}
5783
5784/**
5785 * s2io_change_mtu - entry point to change MTU size for the device.
5786 * @dev : device pointer.
5787 * @new_mtu : the new MTU size for the device.
5788 * Description: A driver entry point to change MTU size for the device.
5789 * Before changing the MTU the device must be stopped.
5790 * Return value:
5791 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5792 * file on failure.
5793 */
5794
ac1f60db 5795static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4
LT		 5796{
5797 nic_t *sp = dev->priv;
1da177e4
LT		 5798
5799 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5800 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5801 dev->name);
5802 return -EPERM;
5803 }
5804
1da177e4 5805 dev->mtu = new_mtu;
d8892c6e 5806 if (netif_running(dev)) {
e6a8fee2 5807 s2io_card_down(sp);
d8892c6e 5808 netif_stop_queue(dev);
5809 if (s2io_card_up(sp)) {
5810 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5811 __FUNCTION__);
5812 }
5813 if (netif_queue_stopped(dev))
5814 netif_wake_queue(dev);
5815 } else { /* Device is down */
5816 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5817 u64 val64 = new_mtu;
5818
5819 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5820 }
1da177e4
LT		 5821
5822 return 0;
5823}
5824
5825/**
5826 * s2io_tasklet - Bottom half of the ISR.
5827 * @dev_adr : address of the device structure in dma_addr_t format.
5828 * Description:
5829 * This is the tasklet or the bottom half of the ISR. This is
20346722 5830 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 5831 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 5832 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 5833 * replenish the Rx buffers in the Rx buffer descriptors.
5834 * Return value:
5835 * void.
5836 */
5837
5838static void s2io_tasklet(unsigned long dev_addr)
5839{
5840 struct net_device *dev = (struct net_device *) dev_addr;
5841 nic_t *sp = dev->priv;
5842 int i, ret;
5843 mac_info_t *mac_control;
5844 struct config_param *config;
5845
5846 mac_control = &sp->mac_control;
5847 config = &sp->config;
5848
5849 if (!TASKLET_IN_USE) {
5850 for (i = 0; i < config->rx_ring_num; i++) {
5851 ret = fill_rx_buffers(sp, i);
5852 if (ret == -ENOMEM) {
5853 DBG_PRINT(ERR_DBG, "%s: Out of ",
5854 dev->name);
5855 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5856 break;
5857 } else if (ret == -EFILL) {
5858 DBG_PRINT(ERR_DBG,
5859 "%s: Rx Ring %d is full\n",
5860 dev->name, i);
5861 break;
5862 }
5863 }
5864 clear_bit(0, (&sp->tasklet_status));
5865 }
5866}
5867
5868/**
5869 * s2io_set_link - Set the LInk status
5870 * @data: long pointer to device private structue
5871 * Description: Sets the link status for the adapter
5872 */
5873
c4028958 5874static void s2io_set_link(struct work_struct *work)
1da177e4 5875{
c4028958 5876 nic_t *nic = container_of(work, nic_t, set_link_task);
1da177e4
LT		 5877 struct net_device *dev = nic->dev;
5878 XENA_dev_config_t __iomem *bar0 = nic->bar0;
5879 register u64 val64;
5880 u16 subid;
5881
5882 if (test_and_set_bit(0, &(nic->link_state))) {
5883 /* The card is being reset, no point doing anything */
5884 return;
5885 }
5886
5887 subid = nic->pdev->subsystem_device;
a371a07d 5888 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5889 /*
5890 * Allow a small delay for the NICs self initiated
5891 * cleanup to complete.
5892 */
5893 msleep(100);
5894 }
1da177e4
LT		 5895
5896 val64 = readq(&bar0->adapter_status);
20346722 5897 if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
1da177e4
LT		 5898 if (LINK_IS_UP(val64)) {
5899 val64 = readq(&bar0->adapter_control);
5900 val64 |= ADAPTER_CNTL_EN;
5901 writeq(val64, &bar0->adapter_control);
541ae68f 5902 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5903 subid)) {
1da177e4
LT		 5904 val64 = readq(&bar0->gpio_control);
5905 val64 |= GPIO_CTRL_GPIO_0;
5906 writeq(val64, &bar0->gpio_control);
5907 val64 = readq(&bar0->gpio_control);
5908 } else {
5909 val64 |= ADAPTER_LED_ON;
5910 writeq(val64, &bar0->adapter_control);
5911 }
a371a07d 5912 if (s2io_link_fault_indication(nic) ==
5913 MAC_RMAC_ERR_TIMER) {
5914 val64 = readq(&bar0->adapter_status);
5915 if (!LINK_IS_UP(val64)) {
5916 DBG_PRINT(ERR_DBG, "%s:", dev->name);
5917 DBG_PRINT(ERR_DBG, " Link down");
5918 DBG_PRINT(ERR_DBG, "after ");
5919 DBG_PRINT(ERR_DBG, "enabling ");
5920 DBG_PRINT(ERR_DBG, "device \n");
5921 }
1da177e4
LT		 5922 }
5923 if (nic->device_enabled_once == FALSE) {
5924 nic->device_enabled_once = TRUE;
5925 }
5926 s2io_link(nic, LINK_UP);
5927 } else {
541ae68f 5928 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5929 subid)) {
1da177e4
LT		 5930 val64 = readq(&bar0->gpio_control);
5931 val64 &= ~GPIO_CTRL_GPIO_0;
5932 writeq(val64, &bar0->gpio_control);
5933 val64 = readq(&bar0->gpio_control);
5934 }
5935 s2io_link(nic, LINK_DOWN);
5936 }
5937 } else { /* NIC is not Quiescent. */
5938 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5939 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5940 netif_stop_queue(dev);
5941 }
5942 clear_bit(0, &(nic->link_state));
5943}
5944
5d3213cc
AR		 5945static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5946 struct sk_buff **skb, u64 *temp0, u64 *temp1,
5947 u64 *temp2, int size)
5948{
5949 struct net_device *dev = sp->dev;
5950 struct sk_buff *frag_list;
5951
5952 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
5953 /* allocate skb */
5954 if (*skb) {
5955 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
5956 /*
5957 * As Rx frame are not going to be processed,
5958 * using same mapped address for the Rxd
5959 * buffer pointer
5960 */
5961 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
5962 } else {
5963 *skb = dev_alloc_skb(size);
5964 if (!(*skb)) {
5965 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
5966 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
5967 return -ENOMEM ;
5968 }
5969 /* storing the mapped addr in a temp variable
5970 * such it will be used for next rxd whose
5971 * Host Control is NULL
5972 */
5973 ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
5974 pci_map_single( sp->pdev, (*skb)->data,
5975 size - NET_IP_ALIGN,
5976 PCI_DMA_FROMDEVICE);
5977 rxdp->Host_Control = (unsigned long) (*skb);
5978 }
5979 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
5980 /* Two buffer Mode */
5981 if (*skb) {
5982 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
5983 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
5984 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
5985 } else {
5986 *skb = dev_alloc_skb(size);
2ceaac75
DR		 5987 if (!(*skb)) {
5988 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
5989 dev->name);
5990 return -ENOMEM;
5991 }
5d3213cc
AR		 5992 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
5993 pci_map_single(sp->pdev, (*skb)->data,
5994 dev->mtu + 4,
5995 PCI_DMA_FROMDEVICE);
5996 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
5997 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
5998 PCI_DMA_FROMDEVICE);
5999 rxdp->Host_Control = (unsigned long) (*skb);
6000
6001 /* Buffer-1 will be dummy buffer not used */
6002 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6003 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6004 PCI_DMA_FROMDEVICE);
6005 }
6006 } else if ((rxdp->Host_Control == 0)) {
6007 /* Three buffer mode */
6008 if (*skb) {
6009 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6010 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6011 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6012 } else {
6013 *skb = dev_alloc_skb(size);
2ceaac75
DR		 6014 if (!(*skb)) {
6015 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
6016 dev->name);
6017 return -ENOMEM;
6018 }
5d3213cc
AR		 6019 ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6020 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6021 PCI_DMA_FROMDEVICE);
6022 /* Buffer-1 receives L3/L4 headers */
6023 ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6024 pci_map_single( sp->pdev, (*skb)->data,
6025 l3l4hdr_size + 4,
6026 PCI_DMA_FROMDEVICE);
6027 /*
6028 * skb_shinfo(skb)->frag_list will have L4
6029 * data payload
6030 */
6031 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6032 ALIGN_SIZE);
6033 if (skb_shinfo(*skb)->frag_list == NULL) {
6034 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6035 failed\n ", dev->name);
6036 return -ENOMEM ;
6037 }
6038 frag_list = skb_shinfo(*skb)->frag_list;
6039 frag_list->next = NULL;
6040 /*
6041 * Buffer-2 receives L4 data payload
6042 */
6043 ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6044 pci_map_single( sp->pdev, frag_list->data,
6045 dev->mtu, PCI_DMA_FROMDEVICE);
6046 }
6047 }
6048 return 0;
6049}
6050static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6051{
6052 struct net_device *dev = sp->dev;
6053 if (sp->rxd_mode == RXD_MODE_1) {
6054 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6055 } else if (sp->rxd_mode == RXD_MODE_3B) {
6056 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6057 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6058 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6059 } else {
6060 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6061 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6062 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6063 }
6064}
6065
6066static int rxd_owner_bit_reset(nic_t *sp)
6067{
6068 int i, j, k, blk_cnt = 0, size;
6069 mac_info_t * mac_control = &sp->mac_control;
6070 struct config_param *config = &sp->config;
6071 struct net_device *dev = sp->dev;
6072 RxD_t *rxdp = NULL;
6073 struct sk_buff *skb = NULL;
6074 buffAdd_t *ba = NULL;
6075 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6076
6077 /* Calculate the size based on ring mode */
6078 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6079 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6080 if (sp->rxd_mode == RXD_MODE_1)
6081 size += NET_IP_ALIGN;
6082 else if (sp->rxd_mode == RXD_MODE_3B)
6083 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6084 else
6085 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6086
6087 for (i = 0; i < config->rx_ring_num; i++) {
6088 blk_cnt = config->rx_cfg[i].num_rxd /
6089 (rxd_count[sp->rxd_mode] +1);
6090
6091 for (j = 0; j < blk_cnt; j++) {
6092 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6093 rxdp = mac_control->rings[i].
6094 rx_blocks[j].rxds[k].virt_addr;
6095 if(sp->rxd_mode >= RXD_MODE_3A)
6096 ba = &mac_control->rings[i].ba[j][k];
6097 set_rxd_buffer_pointer(sp, rxdp, ba,
6098 &skb,(u64 *)&temp0_64,
6099 (u64 *)&temp1_64,
6100 (u64 *)&temp2_64, size);
6101
6102 set_rxd_buffer_size(sp, rxdp, size);
6103 wmb();
6104 /* flip the Ownership bit to Hardware */
6105 rxdp->Control_1 |= RXD_OWN_XENA;
6106 }
6107 }
6108 }
6109 return 0;
6110
6111}
6112
e6a8fee2 6113static int s2io_add_isr(nic_t * sp)
1da177e4 6114{
e6a8fee2 6115 int ret = 0;
c92ca04b 6116 struct net_device *dev = sp->dev;
e6a8fee2 6117 int err = 0;
1da177e4 6118
e6a8fee2
AR		 6119 if (sp->intr_type == MSI)
6120 ret = s2io_enable_msi(sp);
6121 else if (sp->intr_type == MSI_X)
6122 ret = s2io_enable_msi_x(sp);
6123 if (ret) {
6124 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6125 sp->intr_type = INTA;
20346722 6126 }
1da177e4 6127
e6a8fee2
AR		 6128 /* Store the values of the MSIX table in the nic_t structure */
6129 store_xmsi_data(sp);
c92ca04b 6130
e6a8fee2
AR		 6131 /* After proper initialization of H/W, register ISR */
6132 if (sp->intr_type == MSI) {
6133 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6134 IRQF_SHARED, sp->name, dev);
6135 if (err) {
6136 pci_disable_msi(sp->pdev);
6137 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6138 dev->name);
6139 return -1;
6140 }
6141 }
6142 if (sp->intr_type == MSI_X) {
6143 int i;
c92ca04b 6144
e6a8fee2
AR		 6145 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6146 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6147 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6148 dev->name, i);
6149 err = request_irq(sp->entries[i].vector,
6150 s2io_msix_fifo_handle, 0, sp->desc[i],
6151 sp->s2io_entries[i].arg);
6152 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6153 (unsigned long long)sp->msix_info[i].addr);
6154 } else {
6155 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6156 dev->name, i);
6157 err = request_irq(sp->entries[i].vector,
6158 s2io_msix_ring_handle, 0, sp->desc[i],
6159 sp->s2io_entries[i].arg);
6160 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6161 (unsigned long long)sp->msix_info[i].addr);
c92ca04b 6162 }
e6a8fee2
AR		 6163 if (err) {
6164 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6165 "failed\n", dev->name, i);
6166 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6167 return -1;
6168 }
6169 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6170 }
6171 }
6172 if (sp->intr_type == INTA) {
6173 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6174 sp->name, dev);
6175 if (err) {
6176 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6177 dev->name);
6178 return -1;
6179 }
6180 }
6181 return 0;
6182}
6183static void s2io_rem_isr(nic_t * sp)
6184{
6185 int cnt = 0;
6186 struct net_device *dev = sp->dev;
6187
6188 if (sp->intr_type == MSI_X) {
6189 int i;
6190 u16 msi_control;
6191
6192 for (i=1; (sp->s2io_entries[i].in_use ==
6193 MSIX_REGISTERED_SUCCESS); i++) {
6194 int vector = sp->entries[i].vector;
6195 void *arg = sp->s2io_entries[i].arg;
6196
6197 free_irq(vector, arg);
6198 }
6199 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6200 msi_control &= 0xFFFE; /* Disable MSI */
6201 pci_write_config_word(sp->pdev, 0x42, msi_control);
6202
6203 pci_disable_msix(sp->pdev);
6204 } else {
6205 free_irq(sp->pdev->irq, dev);
6206 if (sp->intr_type == MSI) {
6207 u16 val;
6208
6209 pci_disable_msi(sp->pdev);
6210 pci_read_config_word(sp->pdev, 0x4c, &val);
6211 val ^= 0x1;
6212 pci_write_config_word(sp->pdev, 0x4c, val);
c92ca04b
AR		 6213 }
6214 }
6215 /* Waiting till all Interrupt handlers are complete */
6216 cnt = 0;
6217 do {
6218 msleep(10);
6219 if (!atomic_read(&sp->isr_cnt))
6220 break;
6221 cnt++;
6222 } while(cnt < 5);
e6a8fee2
AR		 6223}
6224
6225static void s2io_card_down(nic_t * sp)
6226{
6227 int cnt = 0;
6228 XENA_dev_config_t __iomem *bar0 = sp->bar0;
6229 unsigned long flags;
6230 register u64 val64 = 0;
6231
6232 del_timer_sync(&sp->alarm_timer);
6233 /* If s2io_set_link task is executing, wait till it completes. */
6234 while (test_and_set_bit(0, &(sp->link_state))) {
6235 msleep(50);
6236 }
6237 atomic_set(&sp->card_state, CARD_DOWN);
6238
6239 /* disable Tx and Rx traffic on the NIC */
6240 stop_nic(sp);
6241
6242 s2io_rem_isr(sp);
1da177e4
LT		 6243
6244 /* Kill tasklet. */
6245 tasklet_kill(&sp->task);
6246
6247 /* Check if the device is Quiescent and then Reset the NIC */
6248 do {
5d3213cc
AR		 6249 /* As per the HW requirement we need to replenish the
6250 * receive buffer to avoid the ring bump. Since there is
6251 * no intention of processing the Rx frame at this pointwe are
6252 * just settting the ownership bit of rxd in Each Rx
6253 * ring to HW and set the appropriate buffer size
6254 * based on the ring mode
6255 */
6256 rxd_owner_bit_reset(sp);
6257
1da177e4 6258 val64 = readq(&bar0->adapter_status);
20346722 6259 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
1da177e4
LT		 6260 break;
6261 }
6262
6263 msleep(50);
6264 cnt++;
6265 if (cnt == 10) {
6266 DBG_PRINT(ERR_DBG,
6267 "s2io_close:Device not Quiescent ");
6268 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6269 (unsigned long long) val64);
6270 break;
6271 }
6272 } while (1);
1da177e4
LT		 6273 s2io_reset(sp);
6274
7ba013ac 6275 spin_lock_irqsave(&sp->tx_lock, flags);
6276 /* Free all Tx buffers */
1da177e4 6277 free_tx_buffers(sp);
7ba013ac 6278 spin_unlock_irqrestore(&sp->tx_lock, flags);
6279
6280 /* Free all Rx buffers */
6281 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6282 free_rx_buffers(sp);
7ba013ac 6283 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6284
1da177e4
LT		 6285 clear_bit(0, &(sp->link_state));
6286}
6287
6288static int s2io_card_up(nic_t * sp)
6289{
cc6e7c44 6290 int i, ret = 0;
1da177e4
LT		 6291 mac_info_t *mac_control;
6292 struct config_param *config;
6293 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6294 u16 interruptible;
1da177e4
LT		 6295
6296 /* Initialize the H/W I/O registers */
6297 if (init_nic(sp) != 0) {
6298 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6299 dev->name);
e6a8fee2 6300 s2io_reset(sp);
1da177e4
LT		 6301 return -ENODEV;
6302 }
6303
20346722 6304 /*
6305 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6306 * Rx ring and initializing buffers into 30 Rx blocks
6307 */
6308 mac_control = &sp->mac_control;
6309 config = &sp->config;
6310
6311 for (i = 0; i < config->rx_ring_num; i++) {
6312 if ((ret = fill_rx_buffers(sp, i))) {
6313 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6314 dev->name);
6315 s2io_reset(sp);
6316 free_rx_buffers(sp);
6317 return -ENOMEM;
6318 }
6319 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6320 atomic_read(&sp->rx_bufs_left[i]));
6321 }
6322
6323 /* Setting its receive mode */
6324 s2io_set_multicast(dev);
6325
7d3d0439 6326 if (sp->lro) {
b41477f3 6327 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6328 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6329 /* Check if we can use(if specified) user provided value */
6330 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6331 sp->lro_max_aggr_per_sess = lro_max_pkts;
6332 }
6333
1da177e4
LT		 6334 /* Enable Rx Traffic and interrupts on the NIC */
6335 if (start_nic(sp)) {
6336 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6337 s2io_reset(sp);
e6a8fee2
AR		 6338 free_rx_buffers(sp);
6339 return -ENODEV;
6340 }
6341
6342 /* Add interrupt service routine */
6343 if (s2io_add_isr(sp) != 0) {
6344 if (sp->intr_type == MSI_X)
6345 s2io_rem_isr(sp);
6346 s2io_reset(sp);
1da177e4
LT		 6347 free_rx_buffers(sp);
6348 return -ENODEV;
6349 }
6350
25fff88e 6351 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6352
e6a8fee2
AR		 6353 /* Enable tasklet for the device */
6354 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6355
6356 /* Enable select interrupts */
6357 if (sp->intr_type != INTA)
6358 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6359 else {
6360 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6361 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6362 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6363 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6364 }
6365
6366
1da177e4
LT		 6367 atomic_set(&sp->card_state, CARD_UP);
6368 return 0;
6369}
6370
20346722 6371/**
1da177e4
LT		 6372 * s2io_restart_nic - Resets the NIC.
6373 * @data : long pointer to the device private structure
6374 * Description:
6375 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6376 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6377 * the run time of the watch dog routine which is run holding a
6378 * spin lock.
6379 */
6380
c4028958 6381static void s2io_restart_nic(struct work_struct *work)
1da177e4 6382{
c4028958
DH		 6383 nic_t *sp = container_of(work, nic_t, rst_timer_task);
6384 struct net_device *dev = sp->dev;
1da177e4 6385
e6a8fee2 6386 s2io_card_down(sp);
1da177e4
LT		 6387 if (s2io_card_up(sp)) {
6388 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6389 dev->name);
6390 }
6391 netif_wake_queue(dev);
6392 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6393 dev->name);
20346722 6394
1da177e4
LT		 6395}
6396
20346722 6397/**
6398 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6399 * @dev : Pointer to net device structure
6400 * Description:
6401 * This function is triggered if the Tx Queue is stopped
6402 * for a pre-defined amount of time when the Interface is still up.
6403 * If the Interface is jammed in such a situation, the hardware is
6404 * reset (by s2io_close) and restarted again (by s2io_open) to
6405 * overcome any problem that might have been caused in the hardware.
6406 * Return value:
6407 * void
6408 */
6409
6410static void s2io_tx_watchdog(struct net_device *dev)
6411{
6412 nic_t *sp = dev->priv;
6413
6414 if (netif_carrier_ok(dev)) {
6415 schedule_work(&sp->rst_timer_task);
bd1034f0 6416 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6417 }
6418}
6419
6420/**
6421 * rx_osm_handler - To perform some OS related operations on SKB.
6422 * @sp: private member of the device structure,pointer to s2io_nic structure.
6423 * @skb : the socket buffer pointer.
6424 * @len : length of the packet
6425 * @cksum : FCS checksum of the frame.
6426 * @ring_no : the ring from which this RxD was extracted.
20346722 6427 * Description:
b41477f3 6428 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6429 * some OS related operations on the SKB before passing it to the upper
6430 * layers. It mainly checks if the checksum is OK, if so adds it to the
6431 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6432 * to the upper layer. If the checksum is wrong, it increments the Rx
6433 * packet error count, frees the SKB and returns error.
6434 * Return value:
6435 * SUCCESS on success and -1 on failure.
6436 */
20346722 6437static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
1da177e4 6438{
20346722 6439 nic_t *sp = ring_data->nic;
1da177e4 6440 struct net_device *dev = (struct net_device *) sp->dev;
20346722 6441 struct sk_buff *skb = (struct sk_buff *)
6442 ((unsigned long) rxdp->Host_Control);
6443 int ring_no = ring_data->ring_no;
1da177e4 6444 u16 l3_csum, l4_csum;
863c11a9 6445 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7d3d0439 6446 lro_t *lro;
da6971d8 6447
20346722 6448 skb->dev = dev;
c92ca04b 6449
863c11a9 6450 if (err) {
bd1034f0
AR		 6451 /* Check for parity error */
6452 if (err & 0x1) {
6453 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6454 }
6455
863c11a9
AR		 6456 /*
6457 * Drop the packet if bad transfer code. Exception being
6458 * 0x5, which could be due to unsupported IPv6 extension header.
6459 * In this case, we let stack handle the packet.
6460 * Note that in this case, since checksum will be incorrect,
6461 * stack will validate the same.
6462 */
6463 if (err && ((err >> 48) != 0x5)) {
6464 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6465 dev->name, err);
6466 sp->stats.rx_crc_errors++;
6467 dev_kfree_skb(skb);
6468 atomic_dec(&sp->rx_bufs_left[ring_no]);
6469 rxdp->Host_Control = 0;
6470 return 0;
6471 }
20346722 6472 }
1da177e4 6473
20346722 6474 /* Updating statistics */
6475 rxdp->Host_Control = 0;
6476 sp->rx_pkt_count++;
6477 sp->stats.rx_packets++;
da6971d8
AR		 6478 if (sp->rxd_mode == RXD_MODE_1) {
6479 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6480
da6971d8
AR		 6481 sp->stats.rx_bytes += len;
6482 skb_put(skb, len);
6483
6484 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6485 int get_block = ring_data->rx_curr_get_info.block_index;
6486 int get_off = ring_data->rx_curr_get_info.offset;
6487 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6488 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6489 unsigned char *buff = skb_push(skb, buf0_len);
6490
6491 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
6492 sp->stats.rx_bytes += buf0_len + buf2_len;
6493 memcpy(buff, ba->ba_0, buf0_len);
6494
6495 if (sp->rxd_mode == RXD_MODE_3A) {
6496 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6497
6498 skb_put(skb, buf1_len);
6499 skb->len += buf2_len;
6500 skb->data_len += buf2_len;
6501 skb->truesize += buf2_len;
6502 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6503 sp->stats.rx_bytes += buf1_len;
6504
6505 } else
6506 skb_put(skb, buf2_len);
6507 }
20346722 6508
7d3d0439
RA		 6509 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6510 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 6511 (sp->rx_csum)) {
6512 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6513 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6514 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6515 /*
1da177e4
LT		 6516 * NIC verifies if the Checksum of the received
6517 * frame is Ok or not and accordingly returns
6518 * a flag in the RxD.
6519 */
6520 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6521 if (sp->lro) {
6522 u32 tcp_len;
6523 u8 *tcp;
6524 int ret = 0;
6525
6526 ret = s2io_club_tcp_session(skb->data, &tcp,
6527 &tcp_len, &lro, rxdp, sp);
6528 switch (ret) {
6529 case 3: /* Begin anew */
6530 lro->parent = skb;
6531 goto aggregate;
6532 case 1: /* Aggregate */
6533 {
6534 lro_append_pkt(sp, lro,
6535 skb, tcp_len);
6536 goto aggregate;
6537 }
6538 case 4: /* Flush session */
6539 {
6540 lro_append_pkt(sp, lro,
6541 skb, tcp_len);
6542 queue_rx_frame(lro->parent);
6543 clear_lro_session(lro);
6544 sp->mac_control.stats_info->
6545 sw_stat.flush_max_pkts++;
6546 goto aggregate;
6547 }
6548 case 2: /* Flush both */
6549 lro->parent->data_len =
6550 lro->frags_len;
6551 sp->mac_control.stats_info->
6552 sw_stat.sending_both++;
6553 queue_rx_frame(lro->parent);
6554 clear_lro_session(lro);
6555 goto send_up;
6556 case 0: /* sessions exceeded */
c92ca04b
AR		 6557 case -1: /* non-TCP or not
6558 * L2 aggregatable
6559 */
7d3d0439
RA		 6560 case 5: /*
6561 * First pkt in session not
6562 * L3/L4 aggregatable
6563 */
6564 break;
6565 default:
6566 DBG_PRINT(ERR_DBG,
6567 "%s: Samadhana!!\n",
6568 __FUNCTION__);
6569 BUG();
6570 }
6571 }
1da177e4 6572 } else {
20346722 6573 /*
6574 * Packet with erroneous checksum, let the
1da177e4
LT		 6575 * upper layers deal with it.
6576 */
6577 skb->ip_summed = CHECKSUM_NONE;
6578 }
6579 } else {
6580 skb->ip_summed = CHECKSUM_NONE;
6581 }
6582
7d3d0439
RA		 6583 if (!sp->lro) {
6584 skb->protocol = eth_type_trans(skb, dev);
1da177e4 6585#ifdef CONFIG_S2IO_NAPI
7d3d0439
RA		 6586 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6587 /* Queueing the vlan frame to the upper layer */
6588 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6589 RXD_GET_VLAN_TAG(rxdp->Control_2));
6590 } else {
6591 netif_receive_skb(skb);
6592 }
1da177e4 6593#else
7d3d0439
RA		 6594 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6595 /* Queueing the vlan frame to the upper layer */
6596 vlan_hwaccel_rx(skb, sp->vlgrp,
6597 RXD_GET_VLAN_TAG(rxdp->Control_2));
6598 } else {
6599 netif_rx(skb);
6600 }
1da177e4 6601#endif
7d3d0439
RA		 6602 } else {
6603send_up:
6604 queue_rx_frame(skb);
6aa20a22 6605 }
1da177e4 6606 dev->last_rx = jiffies;
7d3d0439 6607aggregate:
1da177e4 6608 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 6609 return SUCCESS;
6610}
6611
6612/**
6613 * s2io_link - stops/starts the Tx queue.
6614 * @sp : private member of the device structure, which is a pointer to the
6615 * s2io_nic structure.
6616 * @link : inidicates whether link is UP/DOWN.
6617 * Description:
6618 * This function stops/starts the Tx queue depending on whether the link
20346722 6619 * status of the NIC is is down or up. This is called by the Alarm
6620 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 6621 * Return value:
6622 * void.
6623 */
6624
26df54bf 6625static void s2io_link(nic_t * sp, int link)
1da177e4
LT		 6626{
6627 struct net_device *dev = (struct net_device *) sp->dev;
6628
6629 if (link != sp->last_link_state) {
6630 if (link == LINK_DOWN) {
6631 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6632 netif_carrier_off(dev);
6633 } else {
6634 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6635 netif_carrier_on(dev);
6636 }
6637 }
6638 sp->last_link_state = link;
6639}
6640
6641/**
20346722 6642 * get_xena_rev_id - to identify revision ID of xena.
6643 * @pdev : PCI Dev structure
6644 * Description:
6645 * Function to identify the Revision ID of xena.
6646 * Return value:
6647 * returns the revision ID of the device.
6648 */
6649
26df54bf 6650static int get_xena_rev_id(struct pci_dev *pdev)
20346722 6651{
6652 u8 id = 0;
6653 int ret;
6654 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6655 return id;
6656}
6657
6658/**
6659 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6660 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 6661 * s2io_nic structure.
6662 * Description:
6663 * This function initializes a few of the PCI and PCI-X configuration registers
6664 * with recommended values.
6665 * Return value:
6666 * void
6667 */
6668
6669static void s2io_init_pci(nic_t * sp)
6670{
20346722 6671 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 6672
6673 /* Enable Data Parity Error Recovery in PCI-X command register. */
6674 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6675 &(pcix_cmd));
1da177e4 6676 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6677 (pcix_cmd | 1));
1da177e4 6678 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6679 &(pcix_cmd));
1da177e4
LT		 6680
6681 /* Set the PErr Response bit in PCI command register. */
6682 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6683 pci_write_config_word(sp->pdev, PCI_COMMAND,
6684 (pci_cmd | PCI_COMMAND_PARITY));
6685 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 6686}
6687
9dc737a7
AR		 6688static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6689{
6690 if ( tx_fifo_num > 8) {
6691 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6692 "supported\n");
6693 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6694 tx_fifo_num = 8;
6695 }
6696 if ( rx_ring_num > 8) {
6697 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6698 "supported\n");
6699 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6700 rx_ring_num = 8;
6701 }
6702#ifdef CONFIG_S2IO_NAPI
6703 if (*dev_intr_type != INTA) {
6704 DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
6705 "MSI/MSI-X is enabled. Defaulting to INTA\n");
6706 *dev_intr_type = INTA;
6707 }
6708#endif
6709#ifndef CONFIG_PCI_MSI
6710 if (*dev_intr_type != INTA) {
6711 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6712 "MSI/MSI-X. Defaulting to INTA\n");
6713 *dev_intr_type = INTA;
6714 }
6715#else
6716 if (*dev_intr_type > MSI_X) {
6717 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6718 "Defaulting to INTA\n");
6719 *dev_intr_type = INTA;
6720 }
6721#endif
6722 if ((*dev_intr_type == MSI_X) &&
6723 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6724 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 6725 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 6726 "Defaulting to INTA\n");
6727 *dev_intr_type = INTA;
6728 }
6729 if (rx_ring_mode > 3) {
6730 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6731 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6732 rx_ring_mode = 3;
6733 }
6734 return SUCCESS;
6735}
6736
1da177e4 6737/**
20346722 6738 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 6739 * @pdev : structure containing the PCI related information of the device.
6740 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6741 * Description:
6742 * The function initializes an adapter identified by the pci_dec structure.
20346722 6743 * All OS related initialization including memory and device structure and
6744 * initlaization of the device private variable is done. Also the swapper
6745 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 6746 * registers of the device.
6747 * Return value:
6748 * returns 0 on success and negative on failure.
6749 */
6750
6751static int __devinit
6752s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6753{
6754 nic_t *sp;
6755 struct net_device *dev;
1da177e4
LT		 6756 int i, j, ret;
6757 int dma_flag = FALSE;
6758 u32 mac_up, mac_down;
6759 u64 val64 = 0, tmp64 = 0;
6760 XENA_dev_config_t __iomem *bar0 = NULL;
6761 u16 subid;
6762 mac_info_t *mac_control;
6763 struct config_param *config;
541ae68f 6764 int mode;
cc6e7c44 6765 u8 dev_intr_type = intr_type;
1da177e4 6766
9dc737a7
AR		 6767 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6768 return ret;
1da177e4
LT		 6769
6770 if ((ret = pci_enable_device(pdev))) {
6771 DBG_PRINT(ERR_DBG,
6772 "s2io_init_nic: pci_enable_device failed\n");
6773 return ret;
6774 }
6775
1e7f0bd8 6776 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6777 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6778 dma_flag = TRUE;
1da177e4 6779 if (pci_set_consistent_dma_mask
1e7f0bd8 6780 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6781 DBG_PRINT(ERR_DBG,
6782 "Unable to obtain 64bit DMA for \
6783 consistent allocations\n");
6784 pci_disable_device(pdev);
6785 return -ENOMEM;
6786 }
1e7f0bd8 6787 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 6788 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6789 } else {
6790 pci_disable_device(pdev);
6791 return -ENOMEM;
6792 }
cc6e7c44
RA		 6793 if (dev_intr_type != MSI_X) {
6794 if (pci_request_regions(pdev, s2io_driver_name)) {
b41477f3
AR		 6795 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6796 pci_disable_device(pdev);
cc6e7c44
RA		 6797 return -ENODEV;
6798 }
6799 }
6800 else {
6801 if (!(request_mem_region(pci_resource_start(pdev, 0),
6802 pci_resource_len(pdev, 0), s2io_driver_name))) {
6803 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6804 pci_disable_device(pdev);
6805 return -ENODEV;
6806 }
6807 if (!(request_mem_region(pci_resource_start(pdev, 2),
6808 pci_resource_len(pdev, 2), s2io_driver_name))) {
6809 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6810 release_mem_region(pci_resource_start(pdev, 0),
6811 pci_resource_len(pdev, 0));
6812 pci_disable_device(pdev);
6813 return -ENODEV;
6814 }
1da177e4
LT		 6815 }
6816
6817 dev = alloc_etherdev(sizeof(nic_t));
6818 if (dev == NULL) {
6819 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6820 pci_disable_device(pdev);
6821 pci_release_regions(pdev);
6822 return -ENODEV;
6823 }
6824
6825 pci_set_master(pdev);
6826 pci_set_drvdata(pdev, dev);
6827 SET_MODULE_OWNER(dev);
6828 SET_NETDEV_DEV(dev, &pdev->dev);
6829
6830 /* Private member variable initialized to s2io NIC structure */
6831 sp = dev->priv;
6832 memset(sp, 0, sizeof(nic_t));
6833 sp->dev = dev;
6834 sp->pdev = pdev;
1da177e4 6835 sp->high_dma_flag = dma_flag;
1da177e4 6836 sp->device_enabled_once = FALSE;
da6971d8
AR		 6837 if (rx_ring_mode == 1)
6838 sp->rxd_mode = RXD_MODE_1;
6839 if (rx_ring_mode == 2)
6840 sp->rxd_mode = RXD_MODE_3B;
6841 if (rx_ring_mode == 3)
6842 sp->rxd_mode = RXD_MODE_3A;
6843
cc6e7c44 6844 sp->intr_type = dev_intr_type;
1da177e4 6845
541ae68f 6846 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6847 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6848 sp->device_type = XFRAME_II_DEVICE;
6849 else
6850 sp->device_type = XFRAME_I_DEVICE;
6851
7d3d0439 6852 sp->lro = lro;
6aa20a22 6853
1da177e4
LT		 6854 /* Initialize some PCI/PCI-X fields of the NIC. */
6855 s2io_init_pci(sp);
6856
20346722 6857 /*
1da177e4 6858 * Setting the device configuration parameters.
20346722 6859 * Most of these parameters can be specified by the user during
6860 * module insertion as they are module loadable parameters. If
6861 * these parameters are not not specified during load time, they
1da177e4
LT		 6862 * are initialized with default values.
6863 */
6864 mac_control = &sp->mac_control;
6865 config = &sp->config;
6866
6867 /* Tx side parameters. */
1da177e4
LT		 6868 config->tx_fifo_num = tx_fifo_num;
6869 for (i = 0; i < MAX_TX_FIFOS; i++) {
6870 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6871 config->tx_cfg[i].fifo_priority = i;
6872 }
6873
20346722 6874 /* mapping the QoS priority to the configured fifos */
6875 for (i = 0; i < MAX_TX_FIFOS; i++)
6876 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6877
1da177e4
LT		 6878 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6879 for (i = 0; i < config->tx_fifo_num; i++) {
6880 config->tx_cfg[i].f_no_snoop =
6881 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6882 if (config->tx_cfg[i].fifo_len < 65) {
6883 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6884 break;
6885 }
6886 }
fed5eccd
AR		 6887 /* + 2 because one Txd for skb->data and one Txd for UFO */
6888 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 6889
6890 /* Rx side parameters. */
1da177e4
LT		 6891 config->rx_ring_num = rx_ring_num;
6892 for (i = 0; i < MAX_RX_RINGS; i++) {
6893 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 6894 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 6895 config->rx_cfg[i].ring_priority = i;
6896 }
6897
6898 for (i = 0; i < rx_ring_num; i++) {
6899 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6900 config->rx_cfg[i].f_no_snoop =
6901 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6902 }
6903
6904 /* Setting Mac Control parameters */
6905 mac_control->rmac_pause_time = rmac_pause_time;
6906 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6907 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6908
6909
6910 /* Initialize Ring buffer parameters. */
6911 for (i = 0; i < config->rx_ring_num; i++)
6912 atomic_set(&sp->rx_bufs_left[i], 0);
6913
7ba013ac 6914 /* Initialize the number of ISRs currently running */
6915 atomic_set(&sp->isr_cnt, 0);
6916
1da177e4
LT		 6917 /* initialize the shared memory used by the NIC and the host */
6918 if (init_shared_mem(sp)) {
6919 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 6920 dev->name);
1da177e4
LT		 6921 ret = -ENOMEM;
6922 goto mem_alloc_failed;
6923 }
6924
6925 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6926 pci_resource_len(pdev, 0));
6927 if (!sp->bar0) {
6928 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6929 dev->name);
6930 ret = -ENOMEM;
6931 goto bar0_remap_failed;
6932 }
6933
6934 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6935 pci_resource_len(pdev, 2));
6936 if (!sp->bar1) {
6937 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6938 dev->name);
6939 ret = -ENOMEM;
6940 goto bar1_remap_failed;
6941 }
6942
6943 dev->irq = pdev->irq;
6944 dev->base_addr = (unsigned long) sp->bar0;
6945
6946 /* Initializing the BAR1 address as the start of the FIFO pointer. */
6947 for (j = 0; j < MAX_TX_FIFOS; j++) {
6948 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6949 (sp->bar1 + (j * 0x00020000));
6950 }
6951
6952 /* Driver entry points */
6953 dev->open = &s2io_open;
6954 dev->stop = &s2io_close;
6955 dev->hard_start_xmit = &s2io_xmit;
6956 dev->get_stats = &s2io_get_stats;
6957 dev->set_multicast_list = &s2io_set_multicast;
6958 dev->do_ioctl = &s2io_ioctl;
6959 dev->change_mtu = &s2io_change_mtu;
6960 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 6961 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6962 dev->vlan_rx_register = s2io_vlan_rx_register;
6963 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 6964
1da177e4
LT		 6965 /*
6966 * will use eth_mac_addr() for dev->set_mac_address
6967 * mac address will be set every time dev->open() is called
6968 */
20346722 6969#if defined(CONFIG_S2IO_NAPI)
1da177e4 6970 dev->poll = s2io_poll;
20346722 6971 dev->weight = 32;
1da177e4
LT		 6972#endif
6973
612eff0e
BH		 6974#ifdef CONFIG_NET_POLL_CONTROLLER
6975 dev->poll_controller = s2io_netpoll;
6976#endif
6977
1da177e4
LT		 6978 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6979 if (sp->high_dma_flag == TRUE)
6980 dev->features |= NETIF_F_HIGHDMA;
6981#ifdef NETIF_F_TSO
6982 dev->features |= NETIF_F_TSO;
f83ef8c0
HX		 6983#endif
6984#ifdef NETIF_F_TSO6
6985 dev->features |= NETIF_F_TSO6;
1da177e4 6986#endif
fed5eccd
AR		 6987 if (sp->device_type & XFRAME_II_DEVICE) {
6988 dev->features |= NETIF_F_UFO;
6989 dev->features |= NETIF_F_HW_CSUM;
6990 }
1da177e4
LT		 6991
6992 dev->tx_timeout = &s2io_tx_watchdog;
6993 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 6994 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
6995 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 6996
e960fc5c 6997 pci_save_state(sp->pdev);
1da177e4
LT		 6998
6999 /* Setting swapper control on the NIC, for proper reset operation */
7000 if (s2io_set_swapper(sp)) {
7001 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7002 dev->name);
7003 ret = -EAGAIN;
7004 goto set_swap_failed;
7005 }
7006
541ae68f 7007 /* Verify if the Herc works on the slot its placed into */
7008 if (sp->device_type & XFRAME_II_DEVICE) {
7009 mode = s2io_verify_pci_mode(sp);
7010 if (mode < 0) {
7011 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7012 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7013 ret = -EBADSLT;
7014 goto set_swap_failed;
7015 }
7016 }
7017
7018 /* Not needed for Herc */
7019 if (sp->device_type & XFRAME_I_DEVICE) {
7020 /*
7021 * Fix for all "FFs" MAC address problems observed on
7022 * Alpha platforms
7023 */
7024 fix_mac_address(sp);
7025 s2io_reset(sp);
7026 }
1da177e4
LT		 7027
7028 /*
1da177e4
LT		 7029 * MAC address initialization.
7030 * For now only one mac address will be read and used.
7031 */
7032 bar0 = sp->bar0;
7033 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7034 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7035 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b
AR		 7036 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7037 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
1da177e4
LT		 7038 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7039 mac_down = (u32) tmp64;
7040 mac_up = (u32) (tmp64 >> 32);
7041
7042 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7043
7044 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7045 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7046 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7047 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7048 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7049 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7050
1da177e4
LT		 7051 /* Set the factory defined MAC address initially */
7052 dev->addr_len = ETH_ALEN;
7053 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7054
b41477f3
AR		 7055 /* reset Nic and bring it to known state */
7056 s2io_reset(sp);
7057
1da177e4 7058 /*
20346722 7059 * Initialize the tasklet status and link state flags
541ae68f 7060 * and the card state parameter
1da177e4
LT		 7061 */
7062 atomic_set(&(sp->card_state), 0);
7063 sp->tasklet_status = 0;
7064 sp->link_state = 0;
7065
1da177e4
LT		 7066 /* Initialize spinlocks */
7067 spin_lock_init(&sp->tx_lock);
7068#ifndef CONFIG_S2IO_NAPI
7069 spin_lock_init(&sp->put_lock);
7070#endif
7ba013ac 7071 spin_lock_init(&sp->rx_lock);
1da177e4 7072
20346722 7073 /*
7074 * SXE-002: Configure link and activity LED to init state
7075 * on driver load.
1da177e4
LT		 7076 */
7077 subid = sp->pdev->subsystem_device;
7078 if ((subid & 0xFF) >= 0x07) {
7079 val64 = readq(&bar0->gpio_control);
7080 val64 |= 0x0000800000000000ULL;
7081 writeq(val64, &bar0->gpio_control);
7082 val64 = 0x0411040400000000ULL;
7083 writeq(val64, (void __iomem *) bar0 + 0x2700);
7084 val64 = readq(&bar0->gpio_control);
7085 }
7086
7087 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7088
7089 if (register_netdev(dev)) {
7090 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7091 ret = -ENODEV;
7092 goto register_failed;
7093 }
9dc737a7 7094 s2io_vpd_read(sp);
9dc737a7 7095 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
b41477f3
AR		 7096 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7097 sp->product_name, get_xena_rev_id(sp->pdev));
7098 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7099 s2io_driver_version);
9dc737a7
AR		 7100 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7101 "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
541ae68f 7102 sp->def_mac_addr[0].mac_addr[0],
7103 sp->def_mac_addr[0].mac_addr[1],
7104 sp->def_mac_addr[0].mac_addr[2],
7105 sp->def_mac_addr[0].mac_addr[3],
7106 sp->def_mac_addr[0].mac_addr[4],
7107 sp->def_mac_addr[0].mac_addr[5]);
9dc737a7 7108 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7109 mode = s2io_print_pci_mode(sp);
541ae68f 7110 if (mode < 0) {
9dc737a7 7111 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7112 ret = -EBADSLT;
9dc737a7 7113 unregister_netdev(dev);
541ae68f 7114 goto set_swap_failed;
7115 }
541ae68f 7116 }
9dc737a7
AR		 7117 switch(sp->rxd_mode) {
7118 case RXD_MODE_1:
7119 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7120 dev->name);
7121 break;
7122 case RXD_MODE_3B:
7123 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7124 dev->name);
7125 break;
7126 case RXD_MODE_3A:
7127 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7128 dev->name);
7129 break;
7130 }
7131#ifdef CONFIG_S2IO_NAPI
7132 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7133#endif
7134 switch(sp->intr_type) {
7135 case INTA:
7136 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7137 break;
7138 case MSI:
7139 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7140 break;
7141 case MSI_X:
7142 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7143 break;
7144 }
7d3d0439
RA		 7145 if (sp->lro)
7146 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7147 dev->name);
7d3d0439 7148
7ba013ac 7149 /* Initialize device name */
9dc737a7 7150 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7151
b6e3f982 7152 /* Initialize bimodal Interrupts */
7153 sp->config.bimodal = bimodal;
7154 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7155 sp->config.bimodal = 0;
7156 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7157 dev->name);
7158 }
7159
20346722 7160 /*
7161 * Make Link state as off at this point, when the Link change
7162 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7163 * the right state.
7164 */
7165 netif_carrier_off(dev);
1da177e4
LT		 7166
7167 return 0;
7168
7169 register_failed:
7170 set_swap_failed:
7171 iounmap(sp->bar1);
7172 bar1_remap_failed:
7173 iounmap(sp->bar0);
7174 bar0_remap_failed:
7175 mem_alloc_failed:
7176 free_shared_mem(sp);
7177 pci_disable_device(pdev);
cc6e7c44
RA		 7178 if (dev_intr_type != MSI_X)
7179 pci_release_regions(pdev);
7180 else {
7181 release_mem_region(pci_resource_start(pdev, 0),
7182 pci_resource_len(pdev, 0));
7183 release_mem_region(pci_resource_start(pdev, 2),
7184 pci_resource_len(pdev, 2));
7185 }
1da177e4
LT		 7186 pci_set_drvdata(pdev, NULL);
7187 free_netdev(dev);
7188
7189 return ret;
7190}
7191
7192/**
20346722 7193 * s2io_rem_nic - Free the PCI device
1da177e4 7194 * @pdev: structure containing the PCI related information of the device.
20346722 7195 * Description: This function is called by the Pci subsystem to release a
1da177e4 7196 * PCI device and free up all resource held up by the device. This could
20346722 7197 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7198 * from memory.
7199 */
7200
7201static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7202{
7203 struct net_device *dev =
7204 (struct net_device *) pci_get_drvdata(pdev);
7205 nic_t *sp;
7206
7207 if (dev == NULL) {
7208 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7209 return;
7210 }
7211
7212 sp = dev->priv;
7213 unregister_netdev(dev);
7214
7215 free_shared_mem(sp);
7216 iounmap(sp->bar0);
7217 iounmap(sp->bar1);
7218 pci_disable_device(pdev);
cc6e7c44
RA		 7219 if (sp->intr_type != MSI_X)
7220 pci_release_regions(pdev);
7221 else {
7222 release_mem_region(pci_resource_start(pdev, 0),
7223 pci_resource_len(pdev, 0));
7224 release_mem_region(pci_resource_start(pdev, 2),
7225 pci_resource_len(pdev, 2));
7226 }
1da177e4 7227 pci_set_drvdata(pdev, NULL);
1da177e4
LT		 7228 free_netdev(dev);
7229}
7230
7231/**
7232 * s2io_starter - Entry point for the driver
7233 * Description: This function is the entry point for the driver. It verifies
7234 * the module loadable parameters and initializes PCI configuration space.
7235 */
7236
7237int __init s2io_starter(void)
7238{
29917620 7239 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7240}
7241
7242/**
20346722 7243 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7244 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7245 */
7246
26df54bf 7247static void s2io_closer(void)
1da177e4
LT		 7248{
7249 pci_unregister_driver(&s2io_driver);
7250 DBG_PRINT(INIT_DBG, "cleanup done\n");
7251}
7252
7253module_init(s2io_starter);
7254module_exit(s2io_closer);
7d3d0439 7255
6aa20a22 7256static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7d3d0439
RA		 7257 struct tcphdr **tcp, RxD_t *rxdp)
7258{
7259 int ip_off;
7260 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7261
7262 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7263 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7264 __FUNCTION__);
7265 return -1;
7266 }
7267
7268 /* TODO:
7269 * By default the VLAN field in the MAC is stripped by the card, if this
7270 * feature is turned off in rx_pa_cfg register, then the ip_off field
7271 * has to be shifted by a further 2 bytes
7272 */
7273 switch (l2_type) {
7274 case 0: /* DIX type */
7275 case 4: /* DIX type with VLAN */
7276 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7277 break;
7278 /* LLC, SNAP etc are considered non-mergeable */
7279 default:
7280 return -1;
7281 }
7282
7283 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7284 ip_len = (u8)((*ip)->ihl);
7285 ip_len <<= 2;
7286 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7287
7288 return 0;
7289}
7290
7291static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
7292 struct tcphdr *tcp)
7293{
7294 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7295 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7296 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7297 return -1;
7298 return 0;
7299}
7300
7301static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7302{
7303 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7304}
7305
7306static void initiate_new_session(lro_t *lro, u8 *l2h,
7307 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7308{
7309 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7310 lro->l2h = l2h;
7311 lro->iph = ip;
7312 lro->tcph = tcp;
7313 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7314 lro->tcp_ack = ntohl(tcp->ack_seq);
7315 lro->sg_num = 1;
7316 lro->total_len = ntohs(ip->tot_len);
7317 lro->frags_len = 0;
6aa20a22 7318 /*
7d3d0439
RA		 7319 * check if we saw TCP timestamp. Other consistency checks have
7320 * already been done.
7321 */
7322 if (tcp->doff == 8) {
7323 u32 *ptr;
7324 ptr = (u32 *)(tcp+1);
7325 lro->saw_ts = 1;
7326 lro->cur_tsval = *(ptr+1);
7327 lro->cur_tsecr = *(ptr+2);
7328 }
7329 lro->in_use = 1;
7330}
7331
7332static void update_L3L4_header(nic_t *sp, lro_t *lro)
7333{
7334 struct iphdr *ip = lro->iph;
7335 struct tcphdr *tcp = lro->tcph;
7336 u16 nchk;
7337 StatInfo_t *statinfo = sp->mac_control.stats_info;
7338 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7339
7340 /* Update L3 header */
7341 ip->tot_len = htons(lro->total_len);
7342 ip->check = 0;
7343 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7344 ip->check = nchk;
7345
7346 /* Update L4 header */
7347 tcp->ack_seq = lro->tcp_ack;
7348 tcp->window = lro->window;
7349
7350 /* Update tsecr field if this session has timestamps enabled */
7351 if (lro->saw_ts) {
7352 u32 *ptr = (u32 *)(tcp + 1);
7353 *(ptr+2) = lro->cur_tsecr;
7354 }
7355
7356 /* Update counters required for calculation of
7357 * average no. of packets aggregated.
7358 */
7359 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7360 statinfo->sw_stat.num_aggregations++;
7361}
7362
7363static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7364 struct tcphdr *tcp, u32 l4_pyld)
7365{
7366 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7367 lro->total_len += l4_pyld;
7368 lro->frags_len += l4_pyld;
7369 lro->tcp_next_seq += l4_pyld;
7370 lro->sg_num++;
7371
7372 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7373 lro->tcp_ack = tcp->ack_seq;
7374 lro->window = tcp->window;
6aa20a22 7375
7d3d0439
RA		 7376 if (lro->saw_ts) {
7377 u32 *ptr;
7378 /* Update tsecr and tsval from this packet */
7379 ptr = (u32 *) (tcp + 1);
6aa20a22 7380 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7381 lro->cur_tsecr = *(ptr + 2);
7382 }
7383}
7384
7385static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7386 struct tcphdr *tcp, u32 tcp_pyld_len)
7387{
7d3d0439
RA		 7388 u8 *ptr;
7389
79dc1901
AM		 7390 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7391
7d3d0439
RA		 7392 if (!tcp_pyld_len) {
7393 /* Runt frame or a pure ack */
7394 return -1;
7395 }
7396
7397 if (ip->ihl != 5) /* IP has options */
7398 return -1;
7399
75c30b13
AR		 7400 /* If we see CE codepoint in IP header, packet is not mergeable */
7401 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7402 return -1;
7403
7404 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7405 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7406 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7407 /*
7408 * Currently recognize only the ack control word and
7409 * any other control field being set would result in
7410 * flushing the LRO session
7411 */
7412 return -1;
7413 }
7414
6aa20a22 7415 /*
7d3d0439
RA		 7416 * Allow only one TCP timestamp option. Don't aggregate if
7417 * any other options are detected.
7418 */
7419 if (tcp->doff != 5 && tcp->doff != 8)
7420 return -1;
7421
7422 if (tcp->doff == 8) {
6aa20a22 7423 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7424 while (*ptr == TCPOPT_NOP)
7425 ptr++;
7426 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7427 return -1;
7428
7429 /* Ensure timestamp value increases monotonically */
7430 if (l_lro)
7431 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7432 return -1;
7433
7434 /* timestamp echo reply should be non-zero */
6aa20a22 7435 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7436 return -1;
7437 }
7438
7439 return 0;
7440}
7441
7442static int
7443s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7444 RxD_t *rxdp, nic_t *sp)
7445{
7446 struct iphdr *ip;
7447 struct tcphdr *tcph;
7448 int ret = 0, i;
7449
7450 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7451 rxdp))) {
7452 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7453 ip->saddr, ip->daddr);
7454 } else {
7455 return ret;
7456 }
7457
7458 tcph = (struct tcphdr *)*tcp;
7459 *tcp_len = get_l4_pyld_length(ip, tcph);
7460 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7461 lro_t *l_lro = &sp->lro0_n[i];
7462 if (l_lro->in_use) {
7463 if (check_for_socket_match(l_lro, ip, tcph))
7464 continue;
7465 /* Sock pair matched */
7466 *lro = l_lro;
7467
7468 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7469 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7470 "0x%x, actual 0x%x\n", __FUNCTION__,
7471 (*lro)->tcp_next_seq,
7472 ntohl(tcph->seq));
7473
7474 sp->mac_control.stats_info->
7475 sw_stat.outof_sequence_pkts++;
7476 ret = 2;
7477 break;
7478 }
7479
7480 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7481 ret = 1; /* Aggregate */
7482 else
7483 ret = 2; /* Flush both */
7484 break;
7485 }
7486 }
7487
7488 if (ret == 0) {
7489 /* Before searching for available LRO objects,
7490 * check if the pkt is L3/L4 aggregatable. If not
7491 * don't create new LRO session. Just send this
7492 * packet up.
7493 */
7494 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7495 return 5;
7496 }
7497
7498 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7499 lro_t *l_lro = &sp->lro0_n[i];
7500 if (!(l_lro->in_use)) {
7501 *lro = l_lro;
7502 ret = 3; /* Begin anew */
7503 break;
7504 }
7505 }
7506 }
7507
7508 if (ret == 0) { /* sessions exceeded */
7509 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7510 __FUNCTION__);
7511 *lro = NULL;
7512 return ret;
7513 }
7514
7515 switch (ret) {
7516 case 3:
7517 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7518 break;
7519 case 2:
7520 update_L3L4_header(sp, *lro);
7521 break;
7522 case 1:
7523 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7524 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7525 update_L3L4_header(sp, *lro);
7526 ret = 4; /* Flush the LRO */
7527 }
7528 break;
7529 default:
7530 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7531 __FUNCTION__);
7532 break;
7533 }
7534
7535 return ret;
7536}
7537
7538static void clear_lro_session(lro_t *lro)
7539{
7540 static u16 lro_struct_size = sizeof(lro_t);
7541
7542 memset(lro, 0, lro_struct_size);
7543}
7544
7545static void queue_rx_frame(struct sk_buff *skb)
7546{
7547 struct net_device *dev = skb->dev;
7548
7549 skb->protocol = eth_type_trans(skb, dev);
7550#ifdef CONFIG_S2IO_NAPI
7551 netif_receive_skb(skb);
7552#else
7553 netif_rx(skb);
7554#endif
7555}
7556
7557static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7558 u32 tcp_len)
7559{
75c30b13 7560 struct sk_buff *first = lro->parent;
7d3d0439
RA		 7561
7562 first->len += tcp_len;
7563 first->data_len = lro->frags_len;
7564 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 7565 if (skb_shinfo(first)->frag_list)
7566 lro->last_frag->next = skb;
7d3d0439
RA		 7567 else
7568 skb_shinfo(first)->frag_list = skb;
75c30b13 7569 lro->last_frag = skb;
7d3d0439
RA		 7570 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7571 return;
7572}
Linux kernel - Deliverables
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