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s2io.c: use kzalloc
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
1da177e4
LT		 57#include <linux/module.h>
58#include <linux/types.h>
59#include <linux/errno.h>
60#include <linux/ioport.h>
61#include <linux/pci.h>
1e7f0bd8 62#include <linux/dma-mapping.h>
1da177e4
LT		 63#include <linux/kernel.h>
64#include <linux/netdevice.h>
65#include <linux/etherdevice.h>
40239396 66#include <linux/mdio.h>
1da177e4
LT		 67#include <linux/skbuff.h>
68#include <linux/init.h>
69#include <linux/delay.h>
70#include <linux/stddef.h>
71#include <linux/ioctl.h>
72#include <linux/timex.h>
1da177e4 73#include <linux/ethtool.h>
1da177e4 74#include <linux/workqueue.h>
be3a6b02 75#include <linux/if_vlan.h>
7d3d0439
RA		 76#include <linux/ip.h>
77#include <linux/tcp.h>
78#include <net/tcp.h>
1da177e4 79
1da177e4
LT		 80#include <asm/system.h>
81#include <asm/uaccess.h>
20346722 82#include <asm/io.h>
fe931395 83#include <asm/div64.h>
330ce0de 84#include <asm/irq.h>
1da177e4
LT		 85
86/* local include */
87#include "s2io.h"
88#include "s2io-regs.h"
89
29d0a2b0 90#define DRV_VERSION "2.0.26.25"
6c1792f4 91
1da177e4 92/* S2io Driver name & version. */
20346722 93static char s2io_driver_name[] = "Neterion";
6c1792f4 94static char s2io_driver_version[] = DRV_VERSION;
1da177e4 95
6d517a27
VP		 96static int rxd_size[2] = {32,48};
97static int rxd_count[2] = {127,85};
da6971d8 98
1ee6dd77 99static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 100{
101 int ret;
102
103 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
104 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
105
106 return ret;
107}
108
20346722 109/*
1da177e4
LT		 110 * Cards with following subsystem_id have a link state indication
111 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
112 * macro below identifies these cards given the subsystem_id.
113 */
541ae68f 114#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
115 (dev_type == XFRAME_I_DEVICE) ? \
116 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
117 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 118
119#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
120 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 121
92b84437
SS		 122static inline int is_s2io_card_up(const struct s2io_nic * sp)
123{
124 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
125}
126
1da177e4 127/* Ethtool related variables and Macros. */
6fce365d 128static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 129 "Register test\t(offline)",
130 "Eeprom test\t(offline)",
131 "Link test\t(online)",
132 "RLDRAM test\t(offline)",
133 "BIST Test\t(offline)"
134};
135
6fce365d 136static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 137 {"tmac_frms"},
138 {"tmac_data_octets"},
139 {"tmac_drop_frms"},
140 {"tmac_mcst_frms"},
141 {"tmac_bcst_frms"},
142 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 143 {"tmac_ttl_octets"},
144 {"tmac_ucst_frms"},
145 {"tmac_nucst_frms"},
1da177e4 146 {"tmac_any_err_frms"},
bd1034f0 147 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 148 {"tmac_vld_ip_octets"},
149 {"tmac_vld_ip"},
150 {"tmac_drop_ip"},
151 {"tmac_icmp"},
152 {"tmac_rst_tcp"},
153 {"tmac_tcp"},
154 {"tmac_udp"},
155 {"rmac_vld_frms"},
156 {"rmac_data_octets"},
157 {"rmac_fcs_err_frms"},
158 {"rmac_drop_frms"},
159 {"rmac_vld_mcst_frms"},
160 {"rmac_vld_bcst_frms"},
161 {"rmac_in_rng_len_err_frms"},
bd1034f0 162 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 163 {"rmac_long_frms"},
164 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 165 {"rmac_unsup_ctrl_frms"},
166 {"rmac_ttl_octets"},
167 {"rmac_accepted_ucst_frms"},
168 {"rmac_accepted_nucst_frms"},
1da177e4 169 {"rmac_discarded_frms"},
bd1034f0
AR		 170 {"rmac_drop_events"},
171 {"rmac_ttl_less_fb_octets"},
172 {"rmac_ttl_frms"},
1da177e4
LT		 173 {"rmac_usized_frms"},
174 {"rmac_osized_frms"},
175 {"rmac_frag_frms"},
176 {"rmac_jabber_frms"},
bd1034f0
AR		 177 {"rmac_ttl_64_frms"},
178 {"rmac_ttl_65_127_frms"},
179 {"rmac_ttl_128_255_frms"},
180 {"rmac_ttl_256_511_frms"},
181 {"rmac_ttl_512_1023_frms"},
182 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 183 {"rmac_ip"},
184 {"rmac_ip_octets"},
185 {"rmac_hdr_err_ip"},
186 {"rmac_drop_ip"},
187 {"rmac_icmp"},
188 {"rmac_tcp"},
189 {"rmac_udp"},
190 {"rmac_err_drp_udp"},
bd1034f0
AR		 191 {"rmac_xgmii_err_sym"},
192 {"rmac_frms_q0"},
193 {"rmac_frms_q1"},
194 {"rmac_frms_q2"},
195 {"rmac_frms_q3"},
196 {"rmac_frms_q4"},
197 {"rmac_frms_q5"},
198 {"rmac_frms_q6"},
199 {"rmac_frms_q7"},
200 {"rmac_full_q0"},
201 {"rmac_full_q1"},
202 {"rmac_full_q2"},
203 {"rmac_full_q3"},
204 {"rmac_full_q4"},
205 {"rmac_full_q5"},
206 {"rmac_full_q6"},
207 {"rmac_full_q7"},
1da177e4 208 {"rmac_pause_cnt"},
bd1034f0
AR		 209 {"rmac_xgmii_data_err_cnt"},
210 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 211 {"rmac_accepted_ip"},
212 {"rmac_err_tcp"},
bd1034f0
AR		 213 {"rd_req_cnt"},
214 {"new_rd_req_cnt"},
215 {"new_rd_req_rtry_cnt"},
216 {"rd_rtry_cnt"},
217 {"wr_rtry_rd_ack_cnt"},
218 {"wr_req_cnt"},
219 {"new_wr_req_cnt"},
220 {"new_wr_req_rtry_cnt"},
221 {"wr_rtry_cnt"},
222 {"wr_disc_cnt"},
223 {"rd_rtry_wr_ack_cnt"},
224 {"txp_wr_cnt"},
225 {"txd_rd_cnt"},
226 {"txd_wr_cnt"},
227 {"rxd_rd_cnt"},
228 {"rxd_wr_cnt"},
229 {"txf_rd_cnt"},
fa1f0cb3
SS		 230 {"rxf_wr_cnt"}
231};
232
6fce365d 233static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 234 {"rmac_ttl_1519_4095_frms"},
235 {"rmac_ttl_4096_8191_frms"},
236 {"rmac_ttl_8192_max_frms"},
237 {"rmac_ttl_gt_max_frms"},
238 {"rmac_osized_alt_frms"},
239 {"rmac_jabber_alt_frms"},
240 {"rmac_gt_max_alt_frms"},
241 {"rmac_vlan_frms"},
242 {"rmac_len_discard"},
243 {"rmac_fcs_discard"},
244 {"rmac_pf_discard"},
245 {"rmac_da_discard"},
246 {"rmac_red_discard"},
247 {"rmac_rts_discard"},
248 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 249 {"link_fault_cnt"}
250};
251
6fce365d 252static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 253 {"\n DRIVER STATISTICS"},
254 {"single_bit_ecc_errs"},
255 {"double_bit_ecc_errs"},
bd1034f0
AR		 256 {"parity_err_cnt"},
257 {"serious_err_cnt"},
258 {"soft_reset_cnt"},
259 {"fifo_full_cnt"},
8116f3cf
SS		 260 {"ring_0_full_cnt"},
261 {"ring_1_full_cnt"},
262 {"ring_2_full_cnt"},
263 {"ring_3_full_cnt"},
264 {"ring_4_full_cnt"},
265 {"ring_5_full_cnt"},
266 {"ring_6_full_cnt"},
267 {"ring_7_full_cnt"},
43b7c451
SH		 268 {"alarm_transceiver_temp_high"},
269 {"alarm_transceiver_temp_low"},
270 {"alarm_laser_bias_current_high"},
271 {"alarm_laser_bias_current_low"},
272 {"alarm_laser_output_power_high"},
273 {"alarm_laser_output_power_low"},
274 {"warn_transceiver_temp_high"},
275 {"warn_transceiver_temp_low"},
276 {"warn_laser_bias_current_high"},
277 {"warn_laser_bias_current_low"},
278 {"warn_laser_output_power_high"},
279 {"warn_laser_output_power_low"},
280 {"lro_aggregated_pkts"},
281 {"lro_flush_both_count"},
282 {"lro_out_of_sequence_pkts"},
283 {"lro_flush_due_to_max_pkts"},
284 {"lro_avg_aggr_pkts"},
285 {"mem_alloc_fail_cnt"},
286 {"pci_map_fail_cnt"},
287 {"watchdog_timer_cnt"},
288 {"mem_allocated"},
289 {"mem_freed"},
290 {"link_up_cnt"},
291 {"link_down_cnt"},
292 {"link_up_time"},
293 {"link_down_time"},
294 {"tx_tcode_buf_abort_cnt"},
295 {"tx_tcode_desc_abort_cnt"},
296 {"tx_tcode_parity_err_cnt"},
297 {"tx_tcode_link_loss_cnt"},
298 {"tx_tcode_list_proc_err_cnt"},
299 {"rx_tcode_parity_err_cnt"},
300 {"rx_tcode_abort_cnt"},
301 {"rx_tcode_parity_abort_cnt"},
302 {"rx_tcode_rda_fail_cnt"},
303 {"rx_tcode_unkn_prot_cnt"},
304 {"rx_tcode_fcs_err_cnt"},
305 {"rx_tcode_buf_size_err_cnt"},
306 {"rx_tcode_rxd_corrupt_cnt"},
307 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 308 {"tda_err_cnt"},
309 {"pfc_err_cnt"},
310 {"pcc_err_cnt"},
311 {"tti_err_cnt"},
312 {"tpa_err_cnt"},
313 {"sm_err_cnt"},
314 {"lso_err_cnt"},
315 {"mac_tmac_err_cnt"},
316 {"mac_rmac_err_cnt"},
317 {"xgxs_txgxs_err_cnt"},
318 {"xgxs_rxgxs_err_cnt"},
319 {"rc_err_cnt"},
320 {"prc_pcix_err_cnt"},
321 {"rpa_err_cnt"},
322 {"rda_err_cnt"},
323 {"rti_err_cnt"},
324 {"mc_err_cnt"}
1da177e4
LT		 325};
326
4c3616cd
AMR		 327#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
328#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
329#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 330
331#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
332#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
333
334#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
335#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 336
4c3616cd 337#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 338#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
339
25fff88e 340#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
341 init_timer(&timer); \
342 timer.function = handle; \
343 timer.data = (unsigned long) arg; \
344 mod_timer(&timer, (jiffies + exp)) \
345
2fd37688
SS		 346/* copy mac addr to def_mac_addr array */
347static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
348{
349 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
350 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
351 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
352 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
353 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
354 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
355}
04025095 356
be3a6b02 357/* Add the vlan */
358static void s2io_vlan_rx_register(struct net_device *dev,
04025095 359 struct vlan_group *grp)
be3a6b02 360{
2fda096d 361 int i;
4cf1653a 362 struct s2io_nic *nic = netdev_priv(dev);
2fda096d
SR		 363 unsigned long flags[MAX_TX_FIFOS];
364 struct mac_info *mac_control = &nic->mac_control;
365 struct config_param *config = &nic->config;
366
13d866a9
JP		 367 for (i = 0; i < config->tx_fifo_num; i++) {
368 struct fifo_info *fifo = &mac_control->fifos[i];
369
370 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
371 }
be3a6b02 372
be3a6b02 373 nic->vlgrp = grp;
13d866a9
JP		 374
375 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
376 struct fifo_info *fifo = &mac_control->fifos[i];
377
378 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
379 }
be3a6b02 380}
381
cdb5bf02 382/* Unregister the vlan */
04025095 383static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 384{
385 int i;
4cf1653a 386 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02
SH		 387 unsigned long flags[MAX_TX_FIFOS];
388 struct mac_info *mac_control = &nic->mac_control;
389 struct config_param *config = &nic->config;
390
13d866a9
JP		 391 for (i = 0; i < config->tx_fifo_num; i++) {
392 struct fifo_info *fifo = &mac_control->fifos[i];
393
394 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
395 }
cdb5bf02
SH		 396
397 if (nic->vlgrp)
398 vlan_group_set_device(nic->vlgrp, vid, NULL);
399
13d866a9
JP		 400 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
401 struct fifo_info *fifo = &mac_control->fifos[i];
402
403 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
404 }
cdb5bf02
SH		 405}
406
20346722 407/*
1da177e4
LT		 408 * Constants to be programmed into the Xena's registers, to configure
409 * the XAUI.
410 */
411
1da177e4 412#define END_SIGN 0x0
f71e1309 413static const u64 herc_act_dtx_cfg[] = {
541ae68f 414 /* Set address */
e960fc5c 415 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 416 /* Write data */
e960fc5c 417 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 418 /* Set address */
419 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
420 /* Write data */
421 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
422 /* Set address */
e960fc5c 423 0x801205150D440000ULL, 0x801205150D4400E0ULL,
424 /* Write data */
425 0x801205150D440004ULL, 0x801205150D4400E4ULL,
426 /* Set address */
541ae68f 427 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
428 /* Write data */
429 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
430 /* Done */
431 END_SIGN
432};
433
f71e1309 434static const u64 xena_dtx_cfg[] = {
c92ca04b 435 /* Set address */
1da177e4 436 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 437 /* Write data */
438 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
439 /* Set address */
440 0x8001051500000000ULL, 0x80010515000000E0ULL,
441 /* Write data */
442 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
443 /* Set address */
1da177e4 444 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 445 /* Write data */
446 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 447 END_SIGN
448};
449
20346722 450/*
1da177e4
LT		 451 * Constants for Fixing the MacAddress problem seen mostly on
452 * Alpha machines.
453 */
f71e1309 454static const u64 fix_mac[] = {
1da177e4
LT		 455 0x0060000000000000ULL, 0x0060600000000000ULL,
456 0x0040600000000000ULL, 0x0000600000000000ULL,
457 0x0020600000000000ULL, 0x0060600000000000ULL,
458 0x0020600000000000ULL, 0x0060600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0000600000000000ULL,
468 0x0040600000000000ULL, 0x0060600000000000ULL,
469 END_SIGN
470};
471
b41477f3
AR		 472MODULE_LICENSE("GPL");
473MODULE_VERSION(DRV_VERSION);
474
475
1da177e4 476/* Module Loadable parameters. */
6cfc482b 477S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 478S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 479S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 480S2IO_PARM_INT(rx_ring_mode, 1);
481S2IO_PARM_INT(use_continuous_tx_intrs, 1);
482S2IO_PARM_INT(rmac_pause_time, 0x100);
483S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
484S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
485S2IO_PARM_INT(shared_splits, 0);
486S2IO_PARM_INT(tmac_util_period, 5);
487S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 488S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 489/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
490S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 491/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 492S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 493/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 494S2IO_PARM_INT(intr_type, 2);
7d3d0439 495/* Large receive offload feature */
43b7c451
SH		 496static unsigned int lro_enable;
497module_param_named(lro, lro_enable, uint, 0);
498
7d3d0439
RA		 499/* Max pkts to be aggregated by LRO at one time. If not specified,
500 * aggregation happens until we hit max IP pkt size(64K)
501 */
b41477f3 502S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 503S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 504
505S2IO_PARM_INT(napi, 1);
506S2IO_PARM_INT(ufo, 0);
926930b2 507S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 508
509static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
510 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
511static unsigned int rx_ring_sz[MAX_RX_RINGS] =
512 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
513static unsigned int rts_frm_len[MAX_RX_RINGS] =
514 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
515
516module_param_array(tx_fifo_len, uint, NULL, 0);
517module_param_array(rx_ring_sz, uint, NULL, 0);
518module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 519
20346722 520/*
1da177e4 521 * S2IO device table.
20346722 522 * This table lists all the devices that this driver supports.
1da177e4
LT		 523 */
524static struct pci_device_id s2io_tbl[] __devinitdata = {
525 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
526 PCI_ANY_ID, PCI_ANY_ID},
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722 530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
532 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 533 {0,}
534};
535
536MODULE_DEVICE_TABLE(pci, s2io_tbl);
537
d796fdb7
LV		 538static struct pci_error_handlers s2io_err_handler = {
539 .error_detected = s2io_io_error_detected,
540 .slot_reset = s2io_io_slot_reset,
541 .resume = s2io_io_resume,
542};
543
1da177e4
LT		 544static struct pci_driver s2io_driver = {
545 .name = "S2IO",
546 .id_table = s2io_tbl,
547 .probe = s2io_init_nic,
548 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 549 .err_handler = &s2io_err_handler,
1da177e4
LT		 550};
551
552/* A simplifier macro used both by init and free shared_mem Fns(). */
553#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
554
3a3d5756
SH		 555/* netqueue manipulation helper functions */
556static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
557{
fd2ea0a7
DM		 558 if (!sp->config.multiq) {
559 int i;
560
3a3d5756
SH		 561 for (i = 0; i < sp->config.tx_fifo_num; i++)
562 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 563 }
fd2ea0a7 564 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 565}
566
567static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
568{
fd2ea0a7 569 if (!sp->config.multiq)
3a3d5756
SH		 570 sp->mac_control.fifos[fifo_no].queue_state =
571 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 572
573 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 574}
575
576static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
577{
fd2ea0a7
DM		 578 if (!sp->config.multiq) {
579 int i;
580
3a3d5756
SH		 581 for (i = 0; i < sp->config.tx_fifo_num; i++)
582 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 583 }
fd2ea0a7 584 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 585}
586
587static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
588{
fd2ea0a7 589 if (!sp->config.multiq)
3a3d5756
SH		 590 sp->mac_control.fifos[fifo_no].queue_state =
591 FIFO_QUEUE_START;
fd2ea0a7
DM		 592
593 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 594}
595
596static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
597{
fd2ea0a7
DM		 598 if (!sp->config.multiq) {
599 int i;
600
3a3d5756
SH		 601 for (i = 0; i < sp->config.tx_fifo_num; i++)
602 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 603 }
fd2ea0a7 604 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 605}
606
607static inline void s2io_wake_tx_queue(
608 struct fifo_info *fifo, int cnt, u8 multiq)
609{
610
3a3d5756
SH		 611 if (multiq) {
612 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
613 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 614 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 615 if (netif_queue_stopped(fifo->dev)) {
616 fifo->queue_state = FIFO_QUEUE_START;
617 netif_wake_queue(fifo->dev);
618 }
619 }
620}
621
1da177e4
LT		 622/**
623 * init_shared_mem - Allocation and Initialization of Memory
624 * @nic: Device private variable.
20346722 625 * Description: The function allocates all the memory areas shared
626 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 627 * Rx descriptors and the statistics block.
628 */
629
630static int init_shared_mem(struct s2io_nic *nic)
631{
632 u32 size;
633 void *tmp_v_addr, *tmp_v_addr_next;
634 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 635 struct RxD_block *pre_rxd_blk = NULL;
372cc597 636 int i, j, blk_cnt;
1da177e4
LT		 637 int lst_size, lst_per_page;
638 struct net_device *dev = nic->dev;
8ae418cf 639 unsigned long tmp;
1ee6dd77 640 struct buffAdd *ba;
1da177e4 641
1ee6dd77 642 struct mac_info *mac_control;
1da177e4 643 struct config_param *config;
491976b2 644 unsigned long long mem_allocated = 0;
1da177e4
LT		 645
646 mac_control = &nic->mac_control;
647 config = &nic->config;
648
13d866a9 649 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 650 size = 0;
651 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 652 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
653
654 size += tx_cfg->fifo_len;
1da177e4
LT		 655 }
656 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 657 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 658 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 659 return -EINVAL;
1da177e4
LT		 660 }
661
2fda096d
SR		 662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
2fda096d
SR		 667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
671 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
672 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
673 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
674 "are 2 to 8192\n");
675 return -EINVAL;
676 }
677 }
678
1ee6dd77 679 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 680 lst_per_page = PAGE_SIZE / lst_size;
681
682 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 683 struct fifo_info *fifo = &mac_control->fifos[i];
684 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
685 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 686 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 687
688 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
689 if (!fifo->list_info) {
0c61ed5f 690 DBG_PRINT(INFO_DBG,
1da177e4
LT		 691 "Malloc failed for list_info\n");
692 return -ENOMEM;
693 }
491976b2 694 mem_allocated += list_holder_size;
1da177e4
LT		 695 }
696 for (i = 0; i < config->tx_fifo_num; i++) {
697 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
698 lst_per_page);
13d866a9
JP		 699 struct fifo_info *fifo = &mac_control->fifos[i];
700 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
701
702 fifo->tx_curr_put_info.offset = 0;
703 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->tx_curr_get_info.offset = 0;
705 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
706 fifo->fifo_no = i;
707 fifo->nic = nic;
708 fifo->max_txds = MAX_SKB_FRAGS + 2;
709 fifo->dev = dev;
20346722 710
1da177e4
LT		 711 for (j = 0; j < page_num; j++) {
712 int k = 0;
713 dma_addr_t tmp_p;
714 void *tmp_v;
715 tmp_v = pci_alloc_consistent(nic->pdev,
716 PAGE_SIZE, &tmp_p);
717 if (!tmp_v) {
0c61ed5f 718 DBG_PRINT(INFO_DBG,
1da177e4 719 "pci_alloc_consistent ");
0c61ed5f 720 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 721 return -ENOMEM;
722 }
776bd20f 723 /* If we got a zero DMA address(can happen on
724 * certain platforms like PPC), reallocate.
725 * Store virtual address of page we don't want,
726 * to be freed later.
727 */
728 if (!tmp_p) {
729 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 730 DBG_PRINT(INIT_DBG,
776bd20f 731 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 732 DBG_PRINT(INIT_DBG,
6b4d617d 733 "Virtual address %p\n", tmp_v);
776bd20f 734 tmp_v = pci_alloc_consistent(nic->pdev,
735 PAGE_SIZE, &tmp_p);
736 if (!tmp_v) {
0c61ed5f 737 DBG_PRINT(INFO_DBG,
776bd20f 738 "pci_alloc_consistent ");
0c61ed5f 739 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 740 return -ENOMEM;
741 }
491976b2 742 mem_allocated += PAGE_SIZE;
776bd20f 743 }
1da177e4
LT		 744 while (k < lst_per_page) {
745 int l = (j * lst_per_page) + k;
13d866a9 746 if (l == tx_cfg->fifo_len)
20346722 747 break;
13d866a9 748 fifo->list_info[l].list_virt_addr =
1da177e4 749 tmp_v + (k * lst_size);
13d866a9 750 fifo->list_info[l].list_phy_addr =
1da177e4
LT		 751 tmp_p + (k * lst_size);
752 k++;
753 }
754 }
755 }
1da177e4 756
2fda096d 757 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 758 struct fifo_info *fifo = &mac_control->fifos[i];
759 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
760
761 size = tx_cfg->fifo_len;
762 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
763 if (!fifo->ufo_in_band_v)
2fda096d
SR		 764 return -ENOMEM;
765 mem_allocated += (size * sizeof(u64));
766 }
fed5eccd 767
1da177e4
LT		 768 /* Allocation and initialization of RXDs in Rings */
769 size = 0;
770 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 771 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
772 struct ring_info *ring = &mac_control->rings[i];
773
774 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
1da177e4 775 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
13d866a9 776 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
1da177e4
LT		 777 DBG_PRINT(ERR_DBG, "RxDs per Block");
778 return FAILURE;
779 }
13d866a9
JP		 780 size += rx_cfg->num_rxd;
781 ring->block_count = rx_cfg->num_rxd /
da6971d8 782 (rxd_count[nic->rxd_mode] + 1 );
13d866a9 783 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 784 }
da6971d8 785 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 786 size = (size * (sizeof(struct RxD1)));
da6971d8 787 else
1ee6dd77 788 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 789
790 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 791 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
792 struct ring_info *ring = &mac_control->rings[i];
793
794 ring->rx_curr_get_info.block_index = 0;
795 ring->rx_curr_get_info.offset = 0;
796 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
797 ring->rx_curr_put_info.block_index = 0;
798 ring->rx_curr_put_info.offset = 0;
799 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
800 ring->nic = nic;
801 ring->ring_no = i;
802 ring->lro = lro_enable;
803
804 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 805 /* Allocating all the Rx blocks */
806 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 807 struct rx_block_info *rx_blocks;
da6971d8
AR		 808 int l;
809
13d866a9 810 rx_blocks = &ring->rx_blocks[j];
da6971d8 811 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 812 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
813 &tmp_p_addr);
814 if (tmp_v_addr == NULL) {
815 /*
20346722 816 * In case of failure, free_shared_mem()
817 * is called, which should free any
818 * memory that was alloced till the
1da177e4
LT		 819 * failure happened.
820 */
da6971d8 821 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 822 return -ENOMEM;
823 }
491976b2 824 mem_allocated += size;
1da177e4 825 memset(tmp_v_addr, 0, size);
4f870320
JP		 826
827 size = sizeof(struct rxd_info) *
828 rxd_count[nic->rxd_mode];
da6971d8
AR		 829 rx_blocks->block_virt_addr = tmp_v_addr;
830 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 831 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 832 if (!rx_blocks->rxds)
833 return -ENOMEM;
4f870320 834 mem_allocated += size;
da6971d8
AR		 835 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
836 rx_blocks->rxds[l].virt_addr =
837 rx_blocks->block_virt_addr +
838 (rxd_size[nic->rxd_mode] * l);
839 rx_blocks->rxds[l].dma_addr =
840 rx_blocks->block_dma_addr +
841 (rxd_size[nic->rxd_mode] * l);
842 }
1da177e4
LT		 843 }
844 /* Interlinking all Rx Blocks */
845 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 846 int next = (j + 1) % blk_cnt;
847 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
848 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
849 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
850 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 851
1ee6dd77 852 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 853 pre_rxd_blk->reserved_2_pNext_RxD_block =
854 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 855 pre_rxd_blk->pNext_RxD_Blk_physical =
856 (u64) tmp_p_addr_next;
857 }
858 }
6d517a27 859 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 860 /*
861 * Allocation of Storages for buffer addresses in 2BUFF mode
862 * and the buffers as well.
863 */
864 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 865 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
866 struct ring_info *ring = &mac_control->rings[i];
867
868 blk_cnt = rx_cfg->num_rxd /
869 (rxd_count[nic->rxd_mode]+ 1);
4f870320
JP		 870 size = sizeof(struct buffAdd *) * blk_cnt;
871 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 872 if (!ring->ba)
1da177e4 873 return -ENOMEM;
4f870320 874 mem_allocated += size;
da6971d8
AR		 875 for (j = 0; j < blk_cnt; j++) {
876 int k = 0;
4f870320
JP		 877
878 size = sizeof(struct buffAdd) *
879 (rxd_count[nic->rxd_mode] + 1);
880 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 881 if (!ring->ba[j])
1da177e4 882 return -ENOMEM;
4f870320 883 mem_allocated += size;
da6971d8 884 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 885 ba = &ring->ba[j][k];
4f870320
JP		 886 size = BUF0_LEN + ALIGN_SIZE;
887 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 888 if (!ba->ba_0_org)
889 return -ENOMEM;
4f870320 890 mem_allocated += size;
da6971d8
AR		 891 tmp = (unsigned long)ba->ba_0_org;
892 tmp += ALIGN_SIZE;
893 tmp &= ~((unsigned long) ALIGN_SIZE);
894 ba->ba_0 = (void *) tmp;
895
4f870320
JP		 896 size = BUF1_LEN + ALIGN_SIZE;
897 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 898 if (!ba->ba_1_org)
899 return -ENOMEM;
4f870320 900 mem_allocated += size;
da6971d8
AR		 901 tmp = (unsigned long) ba->ba_1_org;
902 tmp += ALIGN_SIZE;
903 tmp &= ~((unsigned long) ALIGN_SIZE);
904 ba->ba_1 = (void *) tmp;
905 k++;
906 }
1da177e4
LT		 907 }
908 }
909 }
1da177e4
LT		 910
911 /* Allocation and initialization of Statistics block */
1ee6dd77 912 size = sizeof(struct stat_block);
1da177e4
LT		 913 mac_control->stats_mem = pci_alloc_consistent
914 (nic->pdev, size, &mac_control->stats_mem_phy);
915
916 if (!mac_control->stats_mem) {
20346722 917 /*
918 * In case of failure, free_shared_mem() is called, which
919 * should free any memory that was alloced till the
1da177e4
LT		 920 * failure happened.
921 */
922 return -ENOMEM;
923 }
491976b2 924 mem_allocated += size;
1da177e4
LT		 925 mac_control->stats_mem_sz = size;
926
927 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 928 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 929 memset(tmp_v_addr, 0, size);
1da177e4
LT		 930 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
931 (unsigned long long) tmp_p_addr);
491976b2 932 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 933 return SUCCESS;
934}
935
20346722 936/**
937 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 938 * @nic: Device private variable.
939 * Description: This function is to free all memory locations allocated by
940 * the init_shared_mem() function and return it to the kernel.
941 */
942
943static void free_shared_mem(struct s2io_nic *nic)
944{
945 int i, j, blk_cnt, size;
946 void *tmp_v_addr;
947 dma_addr_t tmp_p_addr;
1ee6dd77 948 struct mac_info *mac_control;
1da177e4
LT		 949 struct config_param *config;
950 int lst_size, lst_per_page;
8910b49f 951 struct net_device *dev;
491976b2 952 int page_num = 0;
1da177e4
LT		 953
954 if (!nic)
955 return;
956
8910b49f
MG		 957 dev = nic->dev;
958
1da177e4
LT		 959 mac_control = &nic->mac_control;
960 config = &nic->config;
961
1ee6dd77 962 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 963 lst_per_page = PAGE_SIZE / lst_size;
964
965 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 966 struct fifo_info *fifo = &mac_control->fifos[i];
967 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
968
969 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 970 for (j = 0; j < page_num; j++) {
971 int mem_blks = (j * lst_per_page);
13d866a9
JP		 972 struct list_info_hold *fli;
973
974 if (!fifo->list_info)
6aa20a22 975 return;
13d866a9
JP		 976
977 fli = &fifo->list_info[mem_blks];
978 if (!fli->list_virt_addr)
1da177e4
LT		 979 break;
980 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 981 fli->list_virt_addr,
982 fli->list_phy_addr);
8a4bdbaa 983 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 984 += PAGE_SIZE;
1da177e4 985 }
776bd20f 986 /* If we got a zero DMA address during allocation,
987 * free the page now
988 */
989 if (mac_control->zerodma_virt_addr) {
990 pci_free_consistent(nic->pdev, PAGE_SIZE,
991 mac_control->zerodma_virt_addr,
992 (dma_addr_t)0);
6aa20a22 993 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 994 "%s: Freeing TxDL with zero DMA addr. ",
995 dev->name);
996 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
997 mac_control->zerodma_virt_addr);
8a4bdbaa 998 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 999 += PAGE_SIZE;
776bd20f 1000 }
13d866a9 1001 kfree(fifo->list_info);
8a4bdbaa 1002 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1003 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 1004 }
1005
1da177e4 1006 size = SIZE_OF_BLOCK;
1da177e4 1007 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1008 struct ring_info *ring = &mac_control->rings[i];
1009
1010 blk_cnt = ring->block_count;
1da177e4 1011 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1012 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1013 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1014 if (tmp_v_addr == NULL)
1015 break;
1016 pci_free_consistent(nic->pdev, size,
1017 tmp_v_addr, tmp_p_addr);
491976b2 1018 nic->mac_control.stats_info->sw_stat.mem_freed += size;
13d866a9 1019 kfree(ring->rx_blocks[j].rxds);
8a4bdbaa 1020 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1021 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 1022 }
1023 }
1024
6d517a27 1025 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1026 /* Freeing buffer storage addresses in 2BUFF mode. */
1027 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1028 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1029 struct ring_info *ring = &mac_control->rings[i];
1030
1031 blk_cnt = rx_cfg->num_rxd /
1032 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1033 for (j = 0; j < blk_cnt; j++) {
1034 int k = 0;
13d866a9 1035 if (!ring->ba[j])
da6971d8
AR		 1036 continue;
1037 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1038 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1039 kfree(ba->ba_0_org);
491976b2
SH		 1040 nic->mac_control.stats_info->sw_stat.\
1041 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 1042 kfree(ba->ba_1_org);
491976b2
SH		 1043 nic->mac_control.stats_info->sw_stat.\
1044 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 1045 k++;
1046 }
13d866a9 1047 kfree(ring->ba[j]);
9caab458
SS		 1048 nic->mac_control.stats_info->sw_stat.mem_freed +=
1049 (sizeof(struct buffAdd) *
1050 (rxd_count[nic->rxd_mode] + 1));
1da177e4 1051 }
13d866a9 1052 kfree(ring->ba);
8a4bdbaa 1053 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 1054 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 1055 }
1da177e4 1056 }
1da177e4 1057
2fda096d 1058 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1059 struct fifo_info *fifo = &mac_control->fifos[i];
1060 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1061
1062 if (fifo->ufo_in_band_v) {
2fda096d 1063 nic->mac_control.stats_info->sw_stat.mem_freed
13d866a9
JP		 1064 += (tx_cfg->fifo_len * sizeof(u64));
1065 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1066 }
1067 }
1068
1da177e4 1069 if (mac_control->stats_mem) {
2fda096d
SR		 1070 nic->mac_control.stats_info->sw_stat.mem_freed +=
1071 mac_control->stats_mem_sz;
1da177e4
LT		 1072 pci_free_consistent(nic->pdev,
1073 mac_control->stats_mem_sz,
1074 mac_control->stats_mem,
1075 mac_control->stats_mem_phy);
491976b2 1076 }
1da177e4
LT		 1077}
1078
541ae68f 1079/**
1080 * s2io_verify_pci_mode -
1081 */
1082
1ee6dd77 1083static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1084{
1ee6dd77 1085 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1086 register u64 val64 = 0;
1087 int mode;
1088
1089 val64 = readq(&bar0->pci_mode);
1090 mode = (u8)GET_PCI_MODE(val64);
1091
1092 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1093 return -1; /* Unknown PCI mode */
1094 return mode;
1095}
1096
c92ca04b
AR		 1097#define NEC_VENID 0x1033
1098#define NEC_DEVID 0x0125
1099static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1100{
1101 struct pci_dev *tdev = NULL;
26d36b64
AC		 1102 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1103 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1104 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1105 pci_dev_put(tdev);
c92ca04b 1106 return 1;
7ad62dbc 1107 }
c92ca04b
AR		 1108 }
1109 }
1110 return 0;
1111}
541ae68f 1112
7b32a312 1113static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1114/**
1115 * s2io_print_pci_mode -
1116 */
1ee6dd77 1117static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1118{
1ee6dd77 1119 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1120 register u64 val64 = 0;
1121 int mode;
1122 struct config_param *config = &nic->config;
1123
1124 val64 = readq(&bar0->pci_mode);
1125 mode = (u8)GET_PCI_MODE(val64);
1126
1127 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1128 return -1; /* Unknown PCI mode */
1129
c92ca04b
AR		 1130 config->bus_speed = bus_speed[mode];
1131
1132 if (s2io_on_nec_bridge(nic->pdev)) {
1133 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1134 nic->dev->name);
1135 return mode;
1136 }
1137
541ae68f 1138 if (val64 & PCI_MODE_32_BITS) {
1139 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1140 } else {
1141 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1142 }
1143
1144 switch(mode) {
1145 case PCI_MODE_PCI_33:
1146 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f 1147 break;
1148 case PCI_MODE_PCI_66:
1149 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f 1150 break;
1151 case PCI_MODE_PCIX_M1_66:
1152 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f 1153 break;
1154 case PCI_MODE_PCIX_M1_100:
1155 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f 1156 break;
1157 case PCI_MODE_PCIX_M1_133:
1158 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f 1159 break;
1160 case PCI_MODE_PCIX_M2_66:
1161 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f 1162 break;
1163 case PCI_MODE_PCIX_M2_100:
1164 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f 1165 break;
1166 case PCI_MODE_PCIX_M2_133:
1167 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f 1168 break;
1169 default:
1170 return -1; /* Unsupported bus speed */
1171 }
1172
1173 return mode;
1174}
1175
b7c5678f
RV		 1176/**
1177 * init_tti - Initialization transmit traffic interrupt scheme
1178 * @nic: device private variable
1179 * @link: link status (UP/DOWN) used to enable/disable continuous
1180 * transmit interrupts
1181 * Description: The function configures transmit traffic interrupts
1182 * Return Value: SUCCESS on success and
1183 * '-1' on failure
1184 */
1185
0d66afe7 1186static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1187{
1188 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1189 register u64 val64 = 0;
1190 int i;
1191 struct config_param *config;
1192
1193 config = &nic->config;
1194
1195 for (i = 0; i < config->tx_fifo_num; i++) {
1196 /*
1197 * TTI Initialization. Default Tx timer gets us about
1198 * 250 interrupts per sec. Continuous interrupts are enabled
1199 * by default.
1200 */
1201 if (nic->device_type == XFRAME_II_DEVICE) {
1202 int count = (nic->config.bus_speed * 125)/2;
1203 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1204 } else
1205 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1206
1207 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1208 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1209 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1210 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1211 if (i == 0)
1212 if (use_continuous_tx_intrs && (link == LINK_UP))
1213 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1214 writeq(val64, &bar0->tti_data1_mem);
1215
ac731ab6
SH		 1216 if (nic->config.intr_type == MSI_X) {
1217 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1218 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1219 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1220 TTI_DATA2_MEM_TX_UFC_D(0x300);
1221 } else {
1222 if ((nic->config.tx_steering_type ==
1223 TX_DEFAULT_STEERING) &&
1224 (config->tx_fifo_num > 1) &&
1225 (i >= nic->udp_fifo_idx) &&
1226 (i < (nic->udp_fifo_idx +
1227 nic->total_udp_fifos)))
1228 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1229 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1230 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1231 TTI_DATA2_MEM_TX_UFC_D(0x120);
1232 else
1233 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1234 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1235 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1236 TTI_DATA2_MEM_TX_UFC_D(0x80);
1237 }
b7c5678f
RV		 1238
1239 writeq(val64, &bar0->tti_data2_mem);
1240
1241 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1242 TTI_CMD_MEM_OFFSET(i);
1243 writeq(val64, &bar0->tti_command_mem);
1244
1245 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1246 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1247 return FAILURE;
1248 }
1249
1250 return SUCCESS;
1251}
1252
20346722 1253/**
1254 * init_nic - Initialization of hardware
b7c5678f 1255 * @nic: device private variable
20346722 1256 * Description: The function sequentially configures every block
1257 * of the H/W from their reset values.
1258 * Return Value: SUCCESS on success and
1da177e4
LT		 1259 * '-1' on failure (endian settings incorrect).
1260 */
1261
1262static int init_nic(struct s2io_nic *nic)
1263{
1ee6dd77 1264 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1265 struct net_device *dev = nic->dev;
1266 register u64 val64 = 0;
1267 void __iomem *add;
1268 u32 time;
1269 int i, j;
1ee6dd77 1270 struct mac_info *mac_control;
1da177e4 1271 struct config_param *config;
c92ca04b 1272 int dtx_cnt = 0;
1da177e4 1273 unsigned long long mem_share;
20346722 1274 int mem_size;
1da177e4
LT		 1275
1276 mac_control = &nic->mac_control;
1277 config = &nic->config;
1278
5e25b9dd 1279 /* to set the swapper controle on the card */
20346722 1280 if(s2io_set_swapper(nic)) {
1da177e4 1281 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1282 return -EIO;
1da177e4
LT		 1283 }
1284
541ae68f 1285 /*
1286 * Herc requires EOI to be removed from reset before XGXS, so..
1287 */
1288 if (nic->device_type & XFRAME_II_DEVICE) {
1289 val64 = 0xA500000000ULL;
1290 writeq(val64, &bar0->sw_reset);
1291 msleep(500);
1292 val64 = readq(&bar0->sw_reset);
1293 }
1294
1da177e4
LT		 1295 /* Remove XGXS from reset state */
1296 val64 = 0;
1297 writeq(val64, &bar0->sw_reset);
1da177e4 1298 msleep(500);
20346722 1299 val64 = readq(&bar0->sw_reset);
1da177e4 1300
7962024e
SH		 1301 /* Ensure that it's safe to access registers by checking
1302 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1303 */
1304 if (nic->device_type == XFRAME_II_DEVICE) {
1305 for (i = 0; i < 50; i++) {
1306 val64 = readq(&bar0->adapter_status);
1307 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1308 break;
1309 msleep(10);
1310 }
1311 if (i == 50)
1312 return -ENODEV;
1313 }
1314
1da177e4
LT		 1315 /* Enable Receiving broadcasts */
1316 add = &bar0->mac_cfg;
1317 val64 = readq(&bar0->mac_cfg);
1318 val64 |= MAC_RMAC_BCAST_ENABLE;
1319 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1320 writel((u32) val64, add);
1321 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1322 writel((u32) (val64 >> 32), (add + 4));
1323
1324 /* Read registers in all blocks */
1325 val64 = readq(&bar0->mac_int_mask);
1326 val64 = readq(&bar0->mc_int_mask);
1327 val64 = readq(&bar0->xgxs_int_mask);
1328
1329 /* Set MTU */
1330 val64 = dev->mtu;
1331 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1332
541ae68f 1333 if (nic->device_type & XFRAME_II_DEVICE) {
1334 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1335 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1336 &bar0->dtx_control, UF);
541ae68f 1337 if (dtx_cnt & 0x1)
1338 msleep(1); /* Necessary!! */
1da177e4
LT		 1339 dtx_cnt++;
1340 }
541ae68f 1341 } else {
c92ca04b
AR		 1342 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1343 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1344 &bar0->dtx_control, UF);
1345 val64 = readq(&bar0->dtx_control);
1346 dtx_cnt++;
1da177e4
LT		 1347 }
1348 }
1349
1350 /* Tx DMA Initialization */
1351 val64 = 0;
1352 writeq(val64, &bar0->tx_fifo_partition_0);
1353 writeq(val64, &bar0->tx_fifo_partition_1);
1354 writeq(val64, &bar0->tx_fifo_partition_2);
1355 writeq(val64, &bar0->tx_fifo_partition_3);
1356
1357
1358 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1359 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1360
1361 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1362 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1363
1364 if (i == (config->tx_fifo_num - 1)) {
1365 if (i % 2 == 0)
1366 i++;
1367 }
1368
1369 switch (i) {
1370 case 1:
1371 writeq(val64, &bar0->tx_fifo_partition_0);
1372 val64 = 0;
b7c5678f 1373 j = 0;
1da177e4
LT		 1374 break;
1375 case 3:
1376 writeq(val64, &bar0->tx_fifo_partition_1);
1377 val64 = 0;
b7c5678f 1378 j = 0;
1da177e4
LT		 1379 break;
1380 case 5:
1381 writeq(val64, &bar0->tx_fifo_partition_2);
1382 val64 = 0;
b7c5678f 1383 j = 0;
1da177e4
LT		 1384 break;
1385 case 7:
1386 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1387 val64 = 0;
1388 j = 0;
1389 break;
1390 default:
1391 j++;
1da177e4
LT		 1392 break;
1393 }
1394 }
1395
5e25b9dd 1396 /*
1397 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1398 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1399 */
541ae68f 1400 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1401 (nic->pdev->revision < 4))
5e25b9dd 1402 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1403
1da177e4
LT		 1404 val64 = readq(&bar0->tx_fifo_partition_0);
1405 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1406 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1407
20346722 1408 /*
1409 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1410 * integrity checking.
1411 */
1412 val64 = readq(&bar0->tx_pa_cfg);
1413 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1414 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1415 writeq(val64, &bar0->tx_pa_cfg);
1416
1417 /* Rx DMA intialization. */
1418 val64 = 0;
1419 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1420 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1421
1422 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1423 }
1424 writeq(val64, &bar0->rx_queue_priority);
1425
20346722 1426 /*
1427 * Allocating equal share of memory to all the
1da177e4
LT		 1428 * configured Rings.
1429 */
1430 val64 = 0;
541ae68f 1431 if (nic->device_type & XFRAME_II_DEVICE)
1432 mem_size = 32;
1433 else
1434 mem_size = 64;
1435
1da177e4
LT		 1436 for (i = 0; i < config->rx_ring_num; i++) {
1437 switch (i) {
1438 case 0:
20346722 1439 mem_share = (mem_size / config->rx_ring_num +
1440 mem_size % config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1442 continue;
1443 case 1:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1446 continue;
1447 case 2:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1450 continue;
1451 case 3:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1454 continue;
1455 case 4:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1458 continue;
1459 case 5:
20346722 1460 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1461 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1462 continue;
1463 case 6:
20346722 1464 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1465 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1466 continue;
1467 case 7:
20346722 1468 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1469 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1470 continue;
1471 }
1472 }
1473 writeq(val64, &bar0->rx_queue_cfg);
1474
20346722 1475 /*
5e25b9dd 1476 * Filling Tx round robin registers
b7c5678f 1477 * as per the number of FIFOs for equal scheduling priority
1da177e4 1478 */
5e25b9dd 1479 switch (config->tx_fifo_num) {
1480 case 1:
b7c5678f 1481 val64 = 0x0;
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 writeq(val64, &bar0->tx_w_round_robin_1);
1484 writeq(val64, &bar0->tx_w_round_robin_2);
1485 writeq(val64, &bar0->tx_w_round_robin_3);
1486 writeq(val64, &bar0->tx_w_round_robin_4);
1487 break;
1488 case 2:
b7c5678f 1489 val64 = 0x0001000100010001ULL;
5e25b9dd 1490 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1492 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1494 val64 = 0x0001000100000000ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_4);
1496 break;
1497 case 3:
b7c5678f 1498 val64 = 0x0001020001020001ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1500 val64 = 0x0200010200010200ULL;
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1502 val64 = 0x0102000102000102ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1504 val64 = 0x0001020001020001ULL;
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1506 val64 = 0x0200010200000000ULL;
5e25b9dd 1507 writeq(val64, &bar0->tx_w_round_robin_4);
1508 break;
1509 case 4:
b7c5678f 1510 val64 = 0x0001020300010203ULL;
5e25b9dd 1511 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1513 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1515 val64 = 0x0001020300000000ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_4);
1517 break;
1518 case 5:
b7c5678f 1519 val64 = 0x0001020304000102ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1521 val64 = 0x0304000102030400ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1523 val64 = 0x0102030400010203ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1525 val64 = 0x0400010203040001ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1527 val64 = 0x0203040000000000ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_4);
1529 break;
1530 case 6:
b7c5678f 1531 val64 = 0x0001020304050001ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1533 val64 = 0x0203040500010203ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1535 val64 = 0x0405000102030405ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1537 val64 = 0x0001020304050001ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1539 val64 = 0x0203040500000000ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_4);
1541 break;
1542 case 7:
b7c5678f 1543 val64 = 0x0001020304050600ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1545 val64 = 0x0102030405060001ULL;
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1547 val64 = 0x0203040506000102ULL;
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1549 val64 = 0x0304050600010203ULL;
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1551 val64 = 0x0405060000000000ULL;
5e25b9dd 1552 writeq(val64, &bar0->tx_w_round_robin_4);
1553 break;
1554 case 8:
b7c5678f 1555 val64 = 0x0001020304050607ULL;
5e25b9dd 1556 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1557 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1558 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1559 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1560 val64 = 0x0001020300000000ULL;
5e25b9dd 1561 writeq(val64, &bar0->tx_w_round_robin_4);
1562 break;
1563 }
1564
b41477f3 1565 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1566 val64 = readq(&bar0->tx_fifo_partition_0);
1567 val64 |= (TX_FIFO_PARTITION_EN);
1568 writeq(val64, &bar0->tx_fifo_partition_0);
1569
5e25b9dd 1570 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1571 * number of Rings and steering based on QoS with
1572 * equal priority.
1573 */
5e25b9dd 1574 switch (config->rx_ring_num) {
1575 case 1:
0425b46a
SH		 1576 val64 = 0x0;
1577 writeq(val64, &bar0->rx_w_round_robin_0);
1578 writeq(val64, &bar0->rx_w_round_robin_1);
1579 writeq(val64, &bar0->rx_w_round_robin_2);
1580 writeq(val64, &bar0->rx_w_round_robin_3);
1581 writeq(val64, &bar0->rx_w_round_robin_4);
1582
5e25b9dd 1583 val64 = 0x8080808080808080ULL;
1584 writeq(val64, &bar0->rts_qos_steering);
1585 break;
1586 case 2:
0425b46a 1587 val64 = 0x0001000100010001ULL;
5e25b9dd 1588 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1589 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1590 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1591 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1592 val64 = 0x0001000100000000ULL;
5e25b9dd 1593 writeq(val64, &bar0->rx_w_round_robin_4);
1594
1595 val64 = 0x8080808040404040ULL;
1596 writeq(val64, &bar0->rts_qos_steering);
1597 break;
1598 case 3:
0425b46a 1599 val64 = 0x0001020001020001ULL;
5e25b9dd 1600 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1601 val64 = 0x0200010200010200ULL;
5e25b9dd 1602 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1603 val64 = 0x0102000102000102ULL;
5e25b9dd 1604 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1605 val64 = 0x0001020001020001ULL;
5e25b9dd 1606 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1607 val64 = 0x0200010200000000ULL;
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_4);
1609
1610 val64 = 0x8080804040402020ULL;
1611 writeq(val64, &bar0->rts_qos_steering);
1612 break;
1613 case 4:
0425b46a 1614 val64 = 0x0001020300010203ULL;
5e25b9dd 1615 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1616 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1617 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1618 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1619 val64 = 0x0001020300000000ULL;
5e25b9dd 1620 writeq(val64, &bar0->rx_w_round_robin_4);
1621
1622 val64 = 0x8080404020201010ULL;
1623 writeq(val64, &bar0->rts_qos_steering);
1624 break;
1625 case 5:
0425b46a 1626 val64 = 0x0001020304000102ULL;
5e25b9dd 1627 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1628 val64 = 0x0304000102030400ULL;
5e25b9dd 1629 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1630 val64 = 0x0102030400010203ULL;
5e25b9dd 1631 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1632 val64 = 0x0400010203040001ULL;
5e25b9dd 1633 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1634 val64 = 0x0203040000000000ULL;
5e25b9dd 1635 writeq(val64, &bar0->rx_w_round_robin_4);
1636
1637 val64 = 0x8080404020201008ULL;
1638 writeq(val64, &bar0->rts_qos_steering);
1639 break;
1640 case 6:
0425b46a 1641 val64 = 0x0001020304050001ULL;
5e25b9dd 1642 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1643 val64 = 0x0203040500010203ULL;
5e25b9dd 1644 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1645 val64 = 0x0405000102030405ULL;
5e25b9dd 1646 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1647 val64 = 0x0001020304050001ULL;
5e25b9dd 1648 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1649 val64 = 0x0203040500000000ULL;
5e25b9dd 1650 writeq(val64, &bar0->rx_w_round_robin_4);
1651
1652 val64 = 0x8080404020100804ULL;
1653 writeq(val64, &bar0->rts_qos_steering);
1654 break;
1655 case 7:
0425b46a 1656 val64 = 0x0001020304050600ULL;
5e25b9dd 1657 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1658 val64 = 0x0102030405060001ULL;
5e25b9dd 1659 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1660 val64 = 0x0203040506000102ULL;
5e25b9dd 1661 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1662 val64 = 0x0304050600010203ULL;
5e25b9dd 1663 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1664 val64 = 0x0405060000000000ULL;
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_4);
1666
1667 val64 = 0x8080402010080402ULL;
1668 writeq(val64, &bar0->rts_qos_steering);
1669 break;
1670 case 8:
0425b46a 1671 val64 = 0x0001020304050607ULL;
5e25b9dd 1672 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1673 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1674 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1675 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1676 val64 = 0x0001020300000000ULL;
5e25b9dd 1677 writeq(val64, &bar0->rx_w_round_robin_4);
1678
1679 val64 = 0x8040201008040201ULL;
1680 writeq(val64, &bar0->rts_qos_steering);
1681 break;
1682 }
1da177e4
LT		 1683
1684 /* UDP Fix */
1685 val64 = 0;
20346722 1686 for (i = 0; i < 8; i++)
1da177e4
LT		 1687 writeq(val64, &bar0->rts_frm_len_n[i]);
1688
5e25b9dd 1689 /* Set the default rts frame length for the rings configured */
1690 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1691 for (i = 0 ; i < config->rx_ring_num ; i++)
1692 writeq(val64, &bar0->rts_frm_len_n[i]);
1693
1694 /* Set the frame length for the configured rings
1695 * desired by the user
1696 */
1697 for (i = 0; i < config->rx_ring_num; i++) {
1698 /* If rts_frm_len[i] == 0 then it is assumed that user not
1699 * specified frame length steering.
1700 * If the user provides the frame length then program
1701 * the rts_frm_len register for those values or else
1702 * leave it as it is.
1703 */
1704 if (rts_frm_len[i] != 0) {
1705 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1706 &bar0->rts_frm_len_n[i]);
1707 }
1708 }
8a4bdbaa 1709
9fc93a41
SS		 1710 /* Disable differentiated services steering logic */
1711 for (i = 0; i < 64; i++) {
1712 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1713 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1714 dev->name);
1715 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1716 return -ENODEV;
9fc93a41
SS		 1717 }
1718 }
1719
20346722 1720 /* Program statistics memory */
1da177e4 1721 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1722
541ae68f 1723 if (nic->device_type == XFRAME_II_DEVICE) {
1724 val64 = STAT_BC(0x320);
1725 writeq(val64, &bar0->stat_byte_cnt);
1726 }
1727
20346722 1728 /*
1da177e4
LT		 1729 * Initializing the sampling rate for the device to calculate the
1730 * bandwidth utilization.
1731 */
1732 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1733 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1734 writeq(val64, &bar0->mac_link_util);
1735
20346722 1736 /*
1737 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1738 * Scheme.
1739 */
1da177e4 1740
b7c5678f
RV		 1741 /* Initialize TTI */
1742 if (SUCCESS != init_tti(nic, nic->last_link_state))
1743 return -ENODEV;
1da177e4 1744
8a4bdbaa
SS		 1745 /* RTI Initialization */
1746 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1747 /*
8a4bdbaa
SS		 1748 * Programmed to generate Apprx 500 Intrs per
1749 * second
1750 */
1751 int count = (nic->config.bus_speed * 125)/4;
1752 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1753 } else
1754 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1755 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1756 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1757 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1758
1759 writeq(val64, &bar0->rti_data1_mem);
1760
1761 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1762 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1763 if (nic->config.intr_type == MSI_X)
1764 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1765 RTI_DATA2_MEM_RX_UFC_D(0x40));
1766 else
1767 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1768 RTI_DATA2_MEM_RX_UFC_D(0x80));
1769 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1770
8a4bdbaa
SS		 1771 for (i = 0; i < config->rx_ring_num; i++) {
1772 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1773 | RTI_CMD_MEM_OFFSET(i);
1774 writeq(val64, &bar0->rti_command_mem);
1da177e4 1775
8a4bdbaa
SS		 1776 /*
1777 * Once the operation completes, the Strobe bit of the
1778 * command register will be reset. We poll for this
1779 * particular condition. We wait for a maximum of 500ms
1780 * for the operation to complete, if it's not complete
1781 * by then we return error.
1782 */
1783 time = 0;
f957bcf0 1784 while (true) {
8a4bdbaa
SS		 1785 val64 = readq(&bar0->rti_command_mem);
1786 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1787 break;
b6e3f982 1788
8a4bdbaa
SS		 1789 if (time > 10) {
1790 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1791 dev->name);
9f74ffde 1792 return -ENODEV;
b6e3f982 1793 }
8a4bdbaa
SS		 1794 time++;
1795 msleep(50);
1da177e4 1796 }
1da177e4
LT		 1797 }
1798
20346722 1799 /*
1800 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1801 * the 8 Queues on Rx side.
1802 */
1803 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1804 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1805
1806 /* Disable RMAC PAD STRIPPING */
509a2671 1807 add = &bar0->mac_cfg;
1da177e4
LT		 1808 val64 = readq(&bar0->mac_cfg);
1809 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1810 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1811 writel((u32) (val64), add);
1812 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1813 writel((u32) (val64 >> 32), (add + 4));
1814 val64 = readq(&bar0->mac_cfg);
1815
7d3d0439
RA		 1816 /* Enable FCS stripping by adapter */
1817 add = &bar0->mac_cfg;
1818 val64 = readq(&bar0->mac_cfg);
1819 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1820 if (nic->device_type == XFRAME_II_DEVICE)
1821 writeq(val64, &bar0->mac_cfg);
1822 else {
1823 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1824 writel((u32) (val64), add);
1825 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1826 writel((u32) (val64 >> 32), (add + 4));
1827 }
1828
20346722 1829 /*
1830 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1831 * generated by xena.
1832 */
1833 val64 = readq(&bar0->rmac_pause_cfg);
1834 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1835 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1836 writeq(val64, &bar0->rmac_pause_cfg);
1837
20346722 1838 /*
1da177e4
LT		 1839 * Set the Threshold Limit for Generating the pause frame
1840 * If the amount of data in any Queue exceeds ratio of
1841 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1842 * pause frame is generated
1843 */
1844 val64 = 0;
1845 for (i = 0; i < 4; i++) {
1846 val64 |=
1847 (((u64) 0xFF00 | nic->mac_control.
1848 mc_pause_threshold_q0q3)
1849 << (i * 2 * 8));
1850 }
1851 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1852
1853 val64 = 0;
1854 for (i = 0; i < 4; i++) {
1855 val64 |=
1856 (((u64) 0xFF00 | nic->mac_control.
1857 mc_pause_threshold_q4q7)
1858 << (i * 2 * 8));
1859 }
1860 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1861
20346722 1862 /*
1863 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1864 * exceeded the limit pointed by shared_splits
1865 */
1866 val64 = readq(&bar0->pic_control);
1867 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1868 writeq(val64, &bar0->pic_control);
1869
863c11a9
AR		 1870 if (nic->config.bus_speed == 266) {
1871 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1872 writeq(0x0, &bar0->read_retry_delay);
1873 writeq(0x0, &bar0->write_retry_delay);
1874 }
1875
541ae68f 1876 /*
1877 * Programming the Herc to split every write transaction
1878 * that does not start on an ADB to reduce disconnects.
1879 */
1880 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1881 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1882 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1883 writeq(val64, &bar0->misc_control);
1884 val64 = readq(&bar0->pic_control2);
b7b5a128 1885 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1886 writeq(val64, &bar0->pic_control2);
541ae68f 1887 }
c92ca04b
AR		 1888 if (strstr(nic->product_name, "CX4")) {
1889 val64 = TMAC_AVG_IPG(0x17);
1890 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1891 }
1892
1da177e4
LT		 1893 return SUCCESS;
1894}
a371a07d 1895#define LINK_UP_DOWN_INTERRUPT 1
1896#define MAC_RMAC_ERR_TIMER 2
1897
1ee6dd77 1898static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1899{
1900 if (nic->device_type == XFRAME_II_DEVICE)
1901 return LINK_UP_DOWN_INTERRUPT;
1902 else
1903 return MAC_RMAC_ERR_TIMER;
1904}
8116f3cf 1905
9caab458
SS		 1906/**
1907 * do_s2io_write_bits - update alarm bits in alarm register
1908 * @value: alarm bits
1909 * @flag: interrupt status
1910 * @addr: address value
1911 * Description: update alarm bits in alarm register
1912 * Return Value:
1913 * NONE.
1914 */
1915static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1916{
1917 u64 temp64;
1918
1919 temp64 = readq(addr);
1920
1921 if(flag == ENABLE_INTRS)
1922 temp64 &= ~((u64) value);
1923 else
1924 temp64 |= ((u64) value);
1925 writeq(temp64, addr);
1926}
1da177e4 1927
43b7c451 1928static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1929{
1930 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1931 register u64 gen_int_mask = 0;
01e16faa 1932 u64 interruptible;
9caab458 1933
01e16faa 1934 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458
SS		 1935 if (mask & TX_DMA_INTR) {
1936
1937 gen_int_mask |= TXDMA_INT_M;
1938
1939 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1940 TXDMA_PCC_INT | TXDMA_TTI_INT |
1941 TXDMA_LSO_INT | TXDMA_TPA_INT |
1942 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1943
1944 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1945 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1946 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1947 &bar0->pfc_err_mask);
1948
1949 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1950 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1951 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1952
1953 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1954 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1955 PCC_N_SERR | PCC_6_COF_OV_ERR |
1956 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1957 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1958 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1959
1960 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1961 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1962
1963 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1964 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1965 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1966 flag, &bar0->lso_err_mask);
1967
1968 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1969 flag, &bar0->tpa_err_mask);
1970
1971 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1972
1973 }
1974
1975 if (mask & TX_MAC_INTR) {
1976 gen_int_mask |= TXMAC_INT_M;
1977 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1978 &bar0->mac_int_mask);
1979 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1980 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1981 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1982 flag, &bar0->mac_tmac_err_mask);
1983 }
1984
1985 if (mask & TX_XGXS_INTR) {
1986 gen_int_mask |= TXXGXS_INT_M;
1987 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1988 &bar0->xgxs_int_mask);
1989 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1990 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1991 flag, &bar0->xgxs_txgxs_err_mask);
1992 }
1993
1994 if (mask & RX_DMA_INTR) {
1995 gen_int_mask |= RXDMA_INT_M;
1996 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1997 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1998 flag, &bar0->rxdma_int_mask);
1999 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
2000 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
2001 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
2002 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
2003 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
2004 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
2005 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
2006 &bar0->prc_pcix_err_mask);
2007 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
2008 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2009 &bar0->rpa_err_mask);
2010 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2011 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2012 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2013 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
2014 flag, &bar0->rda_err_mask);
2015 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2016 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2017 flag, &bar0->rti_err_mask);
2018 }
2019
2020 if (mask & RX_MAC_INTR) {
2021 gen_int_mask |= RXMAC_INT_M;
2022 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2023 &bar0->mac_int_mask);
01e16faa 2024 interruptible = RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
9caab458 2025 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
01e16faa
SH		 2026 RMAC_DOUBLE_ECC_ERR;
2027 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2028 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2029 do_s2io_write_bits(interruptible,
9caab458
SS		 2030 flag, &bar0->mac_rmac_err_mask);
2031 }
2032
2033 if (mask & RX_XGXS_INTR)
2034 {
2035 gen_int_mask |= RXXGXS_INT_M;
2036 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2037 &bar0->xgxs_int_mask);
2038 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2039 &bar0->xgxs_rxgxs_err_mask);
2040 }
2041
2042 if (mask & MC_INTR) {
2043 gen_int_mask |= MC_INT_M;
2044 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
2045 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2046 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2047 &bar0->mc_err_mask);
2048 }
2049 nic->general_int_mask = gen_int_mask;
2050
2051 /* Remove this line when alarm interrupts are enabled */
2052 nic->general_int_mask = 0;
2053}
20346722 2054/**
2055 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2056 * @nic: device private variable,
2057 * @mask: A mask indicating which Intr block must be modified and,
2058 * @flag: A flag indicating whether to enable or disable the Intrs.
2059 * Description: This function will either disable or enable the interrupts
20346722 2060 * depending on the flag argument. The mask argument can be used to
2061 * enable/disable any Intr block.
1da177e4
LT		 2062 * Return Value: NONE.
2063 */
2064
2065static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2066{
1ee6dd77 2067 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2068 register u64 temp64 = 0, intr_mask = 0;
2069
2070 intr_mask = nic->general_int_mask;
1da177e4
LT		 2071
2072 /* Top level interrupt classification */
2073 /* PIC Interrupts */
9caab458 2074 if (mask & TX_PIC_INTR) {
1da177e4 2075 /* Enable PIC Intrs in the general intr mask register */
9caab458 2076 intr_mask |= TXPIC_INT_M;
1da177e4 2077 if (flag == ENABLE_INTRS) {
20346722 2078 /*
a371a07d 2079 * If Hercules adapter enable GPIO otherwise
b41477f3 2080 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2081 * interrupts for now.
2082 * TODO
1da177e4 2083 */
a371a07d 2084 if (s2io_link_fault_indication(nic) ==
2085 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 2086 do_s2io_write_bits(PIC_INT_GPIO, flag,
2087 &bar0->pic_int_mask);
2088 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2089 &bar0->gpio_int_mask);
2090 } else
a371a07d 2091 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2092 } else if (flag == DISABLE_INTRS) {
20346722 2093 /*
2094 * Disable PIC Intrs in the general
2095 * intr mask register
1da177e4
LT		 2096 */
2097 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2098 }
2099 }
2100
1da177e4
LT		 2101 /* Tx traffic interrupts */
2102 if (mask & TX_TRAFFIC_INTR) {
9caab458 2103 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2104 if (flag == ENABLE_INTRS) {
20346722 2105 /*
1da177e4 2106 * Enable all the Tx side interrupts
20346722 2107 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2108 */
2109 writeq(0x0, &bar0->tx_traffic_mask);
2110 } else if (flag == DISABLE_INTRS) {
20346722 2111 /*
2112 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2113 * register.
2114 */
2115 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2116 }
2117 }
2118
2119 /* Rx traffic interrupts */
2120 if (mask & RX_TRAFFIC_INTR) {
9caab458 2121 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2122 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2123 /* writing 0 Enables all 8 RX interrupt levels */
2124 writeq(0x0, &bar0->rx_traffic_mask);
2125 } else if (flag == DISABLE_INTRS) {
20346722 2126 /*
2127 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2128 * register.
2129 */
2130 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2131 }
2132 }
9caab458
SS		 2133
2134 temp64 = readq(&bar0->general_int_mask);
2135 if (flag == ENABLE_INTRS)
2136 temp64 &= ~((u64) intr_mask);
2137 else
2138 temp64 = DISABLE_ALL_INTRS;
2139 writeq(temp64, &bar0->general_int_mask);
2140
2141 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2142}
2143
19a60522
SS		 2144/**
2145 * verify_pcc_quiescent- Checks for PCC quiescent state
2146 * Return: 1 If PCC is quiescence
2147 * 0 If PCC is not quiescence
2148 */
1ee6dd77 2149static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2150{
19a60522 2151 int ret = 0, herc;
1ee6dd77 2152 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2153 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2154
19a60522 2155 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2156
f957bcf0 2157 if (flag == false) {
44c10138 2158 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2159 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2160 ret = 1;
19a60522
SS		 2161 } else {
2162 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2163 ret = 1;
20346722 2164 }
2165 } else {
44c10138 2166 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2167 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2168 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2169 ret = 1;
5e25b9dd 2170 } else {
2171 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2172 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2173 ret = 1;
20346722 2174 }
2175 }
2176
2177 return ret;
2178}
2179/**
2180 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2181 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2182 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2183 * differs and the calling function passes the input argument flag to
2184 * indicate this.
20346722 2185 * Return: 1 If xena is quiescence
1da177e4
LT		 2186 * 0 If Xena is not quiescence
2187 */
2188
1ee6dd77 2189static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2190{
19a60522 2191 int mode;
1ee6dd77 2192 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2193 u64 val64 = readq(&bar0->adapter_status);
2194 mode = s2io_verify_pci_mode(sp);
1da177e4 2195
19a60522
SS		 2196 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2197 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2198 return 0;
2199 }
2200 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2201 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2202 return 0;
2203 }
2204 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2205 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2206 return 0;
2207 }
2208 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2209 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2210 return 0;
2211 }
2212 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2213 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2214 return 0;
2215 }
2216 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2217 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2218 return 0;
2219 }
2220 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2221 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2222 return 0;
2223 }
2224 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2225 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2226 return 0;
1da177e4
LT		 2227 }
2228
19a60522
SS		 2229 /*
2230 * In PCI 33 mode, the P_PLL is not used, and therefore,
2231 * the the P_PLL_LOCK bit in the adapter_status register will
2232 * not be asserted.
2233 */
2234 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2235 sp->device_type == XFRAME_II_DEVICE && mode !=
2236 PCI_MODE_PCI_33) {
2237 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2238 return 0;
2239 }
2240 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2241 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2242 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2243 return 0;
2244 }
2245 return 1;
1da177e4
LT		 2246}
2247
2248/**
2249 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2250 * @sp: Pointer to device specifc structure
20346722 2251 * Description :
1da177e4
LT		 2252 * New procedure to clear mac address reading problems on Alpha platforms
2253 *
2254 */
2255
1ee6dd77 2256static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2257{
1ee6dd77 2258 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2259 u64 val64;
2260 int i = 0;
2261
2262 while (fix_mac[i] != END_SIGN) {
2263 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2264 udelay(10);
1da177e4
LT		 2265 val64 = readq(&bar0->gpio_control);
2266 }
2267}
2268
2269/**
20346722 2270 * start_nic - Turns the device on
1da177e4 2271 * @nic : device private variable.
20346722 2272 * Description:
2273 * This function actually turns the device on. Before this function is
2274 * called,all Registers are configured from their reset states
2275 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2276 * calling this function, the device interrupts are cleared and the NIC is
2277 * literally switched on by writing into the adapter control register.
20346722 2278 * Return Value:
1da177e4
LT		 2279 * SUCCESS on success and -1 on failure.
2280 */
2281
2282static int start_nic(struct s2io_nic *nic)
2283{
1ee6dd77 2284 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2285 struct net_device *dev = nic->dev;
2286 register u64 val64 = 0;
20346722 2287 u16 subid, i;
1ee6dd77 2288 struct mac_info *mac_control;
1da177e4
LT		 2289 struct config_param *config;
2290
2291 mac_control = &nic->mac_control;
2292 config = &nic->config;
2293
2294 /* PRC Initialization and configuration */
2295 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2296 struct ring_info *ring = &mac_control->rings[i];
2297
2298 writeq((u64) ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2299 &bar0->prc_rxd0_n[i]);
2300
2301 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2302 if (nic->rxd_mode == RXD_MODE_1)
2303 val64 |= PRC_CTRL_RC_ENABLED;
2304 else
2305 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2306 if (nic->device_type == XFRAME_II_DEVICE)
2307 val64 |= PRC_CTRL_GROUP_READS;
2308 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2309 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2310 writeq(val64, &bar0->prc_ctrl_n[i]);
2311 }
2312
da6971d8
AR		 2313 if (nic->rxd_mode == RXD_MODE_3B) {
2314 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2315 val64 = readq(&bar0->rx_pa_cfg);
2316 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2317 writeq(val64, &bar0->rx_pa_cfg);
2318 }
1da177e4 2319
926930b2
SS		 2320 if (vlan_tag_strip == 0) {
2321 val64 = readq(&bar0->rx_pa_cfg);
2322 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2323 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2324 nic->vlan_strip_flag = 0;
926930b2
SS		 2325 }
2326
20346722 2327 /*
1da177e4
LT		 2328 * Enabling MC-RLDRAM. After enabling the device, we timeout
2329 * for around 100ms, which is approximately the time required
2330 * for the device to be ready for operation.
2331 */
2332 val64 = readq(&bar0->mc_rldram_mrs);
2333 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2334 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2335 val64 = readq(&bar0->mc_rldram_mrs);
2336
20346722 2337 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2338
2339 /* Enabling ECC Protection. */
2340 val64 = readq(&bar0->adapter_control);
2341 val64 &= ~ADAPTER_ECC_EN;
2342 writeq(val64, &bar0->adapter_control);
2343
20346722 2344 /*
2345 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2346 * it.
2347 */
2348 val64 = readq(&bar0->adapter_status);
19a60522 2349 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2350 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2351 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2352 (unsigned long long) val64);
2353 return FAILURE;
2354 }
2355
20346722 2356 /*
1da177e4 2357 * With some switches, link might be already up at this point.
20346722 2358 * Because of this weird behavior, when we enable laser,
2359 * we may not get link. We need to handle this. We cannot
2360 * figure out which switch is misbehaving. So we are forced to
2361 * make a global change.
1da177e4
LT		 2362 */
2363
2364 /* Enabling Laser. */
2365 val64 = readq(&bar0->adapter_control);
2366 val64 |= ADAPTER_EOI_TX_ON;
2367 writeq(val64, &bar0->adapter_control);
2368
c92ca04b
AR		 2369 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2370 /*
2371 * Dont see link state interrupts initally on some switches,
2372 * so directly scheduling the link state task here.
2373 */
2374 schedule_work(&nic->set_link_task);
2375 }
1da177e4
LT		 2376 /* SXE-002: Initialize link and activity LED */
2377 subid = nic->pdev->subsystem_device;
541ae68f 2378 if (((subid & 0xFF) >= 0x07) &&
2379 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2380 val64 = readq(&bar0->gpio_control);
2381 val64 |= 0x0000800000000000ULL;
2382 writeq(val64, &bar0->gpio_control);
2383 val64 = 0x0411040400000000ULL;
509a2671 2384 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2385 }
2386
1da177e4
LT		 2387 return SUCCESS;
2388}
fed5eccd
AR		 2389/**
2390 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2391 */
1ee6dd77
RB		 2392static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2393 TxD *txdlp, int get_off)
fed5eccd 2394{
1ee6dd77 2395 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2396 struct sk_buff *skb;
1ee6dd77 2397 struct TxD *txds;
fed5eccd
AR		 2398 u16 j, frg_cnt;
2399
2400 txds = txdlp;
2fda096d 2401 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2402 pci_unmap_single(nic->pdev, (dma_addr_t)
2403 txds->Buffer_Pointer, sizeof(u64),
2404 PCI_DMA_TODEVICE);
2405 txds++;
2406 }
2407
2408 skb = (struct sk_buff *) ((unsigned long)
2409 txds->Host_Control);
2410 if (!skb) {
1ee6dd77 2411 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2412 return NULL;
2413 }
2414 pci_unmap_single(nic->pdev, (dma_addr_t)
2415 txds->Buffer_Pointer,
2416 skb->len - skb->data_len,
2417 PCI_DMA_TODEVICE);
2418 frg_cnt = skb_shinfo(skb)->nr_frags;
2419 if (frg_cnt) {
2420 txds++;
2421 for (j = 0; j < frg_cnt; j++, txds++) {
2422 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2423 if (!txds->Buffer_Pointer)
2424 break;
6aa20a22 2425 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2426 txds->Buffer_Pointer,
2427 frag->size, PCI_DMA_TODEVICE);
2428 }
2429 }
1ee6dd77 2430 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2431 return(skb);
2432}
1da177e4 2433
20346722 2434/**
2435 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2436 * @nic : device private variable.
20346722 2437 * Description:
1da177e4 2438 * Free all queued Tx buffers.
20346722 2439 * Return Value: void
1da177e4
LT		 2440*/
2441
2442static void free_tx_buffers(struct s2io_nic *nic)
2443{
2444 struct net_device *dev = nic->dev;
2445 struct sk_buff *skb;
1ee6dd77 2446 struct TxD *txdp;
1da177e4 2447 int i, j;
1ee6dd77 2448 struct mac_info *mac_control;
1da177e4 2449 struct config_param *config;
fed5eccd 2450 int cnt = 0;
1da177e4
LT		 2451
2452 mac_control = &nic->mac_control;
2453 config = &nic->config;
2454
2455 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2456 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2457 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2458 unsigned long flags;
13d866a9
JP		 2459
2460 spin_lock_irqsave(&fifo->tx_lock, flags);
2461 for (j = 0; j < tx_cfg->fifo_len; j++) {
2462 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2463 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2464 if (skb) {
8a4bdbaa 2465 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2466 += skb->truesize;
fed5eccd
AR		 2467 dev_kfree_skb(skb);
2468 cnt++;
1da177e4 2469 }
1da177e4
LT		 2470 }
2471 DBG_PRINT(INTR_DBG,
2472 "%s:forcibly freeing %d skbs on FIFO%d\n",
2473 dev->name, cnt, i);
13d866a9
JP		 2474 fifo->tx_curr_get_info.offset = 0;
2475 fifo->tx_curr_put_info.offset = 0;
2476 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2477 }
2478}
2479
20346722 2480/**
2481 * stop_nic - To stop the nic
1da177e4 2482 * @nic ; device private variable.
20346722 2483 * Description:
2484 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2485 * function does. This function is called to stop the device.
2486 * Return Value:
2487 * void.
2488 */
2489
2490static void stop_nic(struct s2io_nic *nic)
2491{
1ee6dd77 2492 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2493 register u64 val64 = 0;
5d3213cc 2494 u16 interruptible;
1ee6dd77 2495 struct mac_info *mac_control;
1da177e4
LT		 2496 struct config_param *config;
2497
2498 mac_control = &nic->mac_control;
2499 config = &nic->config;
2500
2501 /* Disable all interrupts */
9caab458 2502 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2503 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2504 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2505 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2506
5d3213cc
AR		 2507 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2508 val64 = readq(&bar0->adapter_control);
2509 val64 &= ~(ADAPTER_CNTL_EN);
2510 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2511}
2512
20346722 2513/**
2514 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2515 * @ring_info: per ring structure
3f78d885
SH		 2516 * @from_card_up: If this is true, we will map the buffer to get
2517 * the dma address for buf0 and buf1 to give it to the card.
2518 * Else we will sync the already mapped buffer to give it to the card.
20346722 2519 * Description:
1da177e4
LT		 2520 * The function allocates Rx side skbs and puts the physical
2521 * address of these buffers into the RxD buffer pointers, so that the NIC
2522 * can DMA the received frame into these locations.
2523 * The NIC supports 3 receive modes, viz
2524 * 1. single buffer,
2525 * 2. three buffer and
2526 * 3. Five buffer modes.
20346722 2527 * Each mode defines how many fragments the received frame will be split
2528 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2529 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2530 * is split into 3 fragments. As of now only single buffer mode is
2531 * supported.
2532 * Return Value:
2533 * SUCCESS on success or an appropriate -ve value on failure.
2534 */
8d8bb39b
FT		 2535static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2536 int from_card_up)
1da177e4 2537{
1da177e4 2538 struct sk_buff *skb;
1ee6dd77 2539 struct RxD_t *rxdp;
0425b46a 2540 int off, size, block_no, block_no1;
1da177e4 2541 u32 alloc_tab = 0;
20346722 2542 u32 alloc_cnt;
20346722 2543 u64 tmp;
1ee6dd77 2544 struct buffAdd *ba;
1ee6dd77 2545 struct RxD_t *first_rxdp = NULL;
363dc367 2546 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2547 int rxd_index = 0;
6d517a27
VP		 2548 struct RxD1 *rxdp1;
2549 struct RxD3 *rxdp3;
0425b46a 2550 struct swStat *stats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2551
0425b46a 2552 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2553
0425b46a 2554 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2555 while (alloc_tab < alloc_cnt) {
0425b46a 2556 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2557
0425b46a
SH		 2558 off = ring->rx_curr_put_info.offset;
2559
2560 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2561
2562 rxd_index = off + 1;
2563 if (block_no)
2564 rxd_index += (block_no * ring->rxd_count);
da6971d8 2565
7d2e3cb7 2566 if ((block_no == block_no1) &&
0425b46a
SH		 2567 (off == ring->rx_curr_get_info.offset) &&
2568 (rxdp->Host_Control)) {
da6971d8 2569 DBG_PRINT(INTR_DBG, "%s: Get and Put",
0425b46a 2570 ring->dev->name);
1da177e4
LT		 2571 DBG_PRINT(INTR_DBG, " info equated\n");
2572 goto end;
2573 }
0425b46a
SH		 2574 if (off && (off == ring->rxd_count)) {
2575 ring->rx_curr_put_info.block_index++;
2576 if (ring->rx_curr_put_info.block_index ==
2577 ring->block_count)
2578 ring->rx_curr_put_info.block_index = 0;
2579 block_no = ring->rx_curr_put_info.block_index;
2580 off = 0;
2581 ring->rx_curr_put_info.offset = off;
2582 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2583 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2584 ring->dev->name, rxdp);
2585
1da177e4 2586 }
c9fcbf47 2587
da6971d8 2588 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
0425b46a 2589 ((ring->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2590 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2591 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2592 goto end;
2593 }
da6971d8 2594 /* calculate size of skb based on ring mode */
0425b46a 2595 size = ring->mtu + HEADER_ETHERNET_II_802_3_SIZE +
da6971d8 2596 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2597 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2598 size += NET_IP_ALIGN;
da6971d8 2599 else
0425b46a 2600 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2601
da6971d8
AR		 2602 /* allocate skb */
2603 skb = dev_alloc_skb(size);
2604 if(!skb) {
0425b46a 2605 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2606 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b 2607 if (first_rxdp) {
2608 wmb();
2609 first_rxdp->Control_1 |= RXD_OWN_XENA;
2610 }
0425b46a 2611 stats->mem_alloc_fail_cnt++;
7d2e3cb7 2612
da6971d8
AR		 2613 return -ENOMEM ;
2614 }
0425b46a
SH		 2615 stats->mem_allocated += skb->truesize;
2616
2617 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2618 /* 1 buffer mode - normal operation mode */
6d517a27 2619 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2620 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2621 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2622 rxdp1->Buffer0_ptr = pci_map_single
0425b46a 2623 (ring->pdev, skb->data, size - NET_IP_ALIGN,
863c11a9 2624 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2625 if (pci_dma_mapping_error(nic->pdev,
2626 rxdp1->Buffer0_ptr))
491abf25
VP		 2627 goto pci_map_failed;
2628
8a4bdbaa 2629 rxdp->Control_2 =
491976b2 2630 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
0425b46a
SH		 2631 rxdp->Host_Control = (unsigned long) (skb);
2632 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2633 /*
6d517a27
VP		 2634 * 2 buffer mode -
2635 * 2 buffer mode provides 128
da6971d8 2636 * byte aligned receive buffers.
da6971d8
AR		 2637 */
2638
6d517a27 2639 rxdp3 = (struct RxD3*)rxdp;
491976b2 2640 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2641 Buffer0_ptr = rxdp3->Buffer0_ptr;
2642 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2643 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2644 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2645 rxdp3->Buffer0_ptr = Buffer0_ptr;
2646 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2647
0425b46a 2648 ba = &ring->ba[block_no][off];
da6971d8
AR		 2649 skb_reserve(skb, BUF0_LEN);
2650 tmp = (u64)(unsigned long) skb->data;
2651 tmp += ALIGN_SIZE;
2652 tmp &= ~ALIGN_SIZE;
2653 skb->data = (void *) (unsigned long)tmp;
27a884dc 2654 skb_reset_tail_pointer(skb);
da6971d8 2655
3f78d885 2656 if (from_card_up) {
6d517a27 2657 rxdp3->Buffer0_ptr =
0425b46a
SH		 2658 pci_map_single(ring->pdev, ba->ba_0,
2659 BUF0_LEN, PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 2660 if (pci_dma_mapping_error(nic->pdev,
2661 rxdp3->Buffer0_ptr))
3f78d885
SH		 2662 goto pci_map_failed;
2663 } else
0425b46a 2664 pci_dma_sync_single_for_device(ring->pdev,
6d517a27 2665 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2666 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25 2667
da6971d8 2668 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2669 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2670 /* Two buffer mode */
2671
2672 /*
6aa20a22 2673 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2674 * L4 payload
2675 */
6d517a27 2676 rxdp3->Buffer2_ptr = pci_map_single
0425b46a 2677 (ring->pdev, skb->data, ring->mtu + 4,
da6971d8
AR		 2678 PCI_DMA_FROMDEVICE);
2679
8d8bb39b
FT		 2680 if (pci_dma_mapping_error(nic->pdev,
2681 rxdp3->Buffer2_ptr))
491abf25
VP		 2682 goto pci_map_failed;
2683
3f78d885 2684 if (from_card_up) {
0425b46a
SH		 2685 rxdp3->Buffer1_ptr =
2686 pci_map_single(ring->pdev,
75c30b13
AR		 2687 ba->ba_1, BUF1_LEN,
2688 PCI_DMA_FROMDEVICE);
0425b46a 2689
8d8bb39b
FT		 2690 if (pci_dma_mapping_error(nic->pdev,
2691 rxdp3->Buffer1_ptr)) {
3f78d885
SH		 2692 pci_unmap_single
2693 (ring->pdev,
2694 (dma_addr_t)(unsigned long)
2695 skb->data,
2696 ring->mtu + 4,
2697 PCI_DMA_FROMDEVICE);
2698 goto pci_map_failed;
2699 }
75c30b13 2700 }
da6971d8
AR		 2701 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2702 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
0425b46a 2703 (ring->mtu + 4);
da6971d8 2704 }
b7b5a128 2705 rxdp->Control_2 |= s2BIT(0);
0425b46a 2706 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2707 }
303bcb4b 2708 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2709 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2710 off++;
0425b46a 2711 if (off == (ring->rxd_count + 1))
da6971d8 2712 off = 0;
0425b46a 2713 ring->rx_curr_put_info.offset = off;
20346722 2714
da6971d8 2715 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2716 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2717 if (first_rxdp) {
2718 wmb();
2719 first_rxdp->Control_1 |= RXD_OWN_XENA;
2720 }
2721 first_rxdp = rxdp;
2722 }
0425b46a 2723 ring->rx_bufs_left += 1;
1da177e4
LT		 2724 alloc_tab++;
2725 }
2726
2727 end:
303bcb4b 2728 /* Transfer ownership of first descriptor to adapter just before
2729 * exiting. Before that, use memory barrier so that ownership
2730 * and other fields are seen by adapter correctly.
2731 */
2732 if (first_rxdp) {
2733 wmb();
2734 first_rxdp->Control_1 |= RXD_OWN_XENA;
2735 }
2736
1da177e4 2737 return SUCCESS;
491abf25
VP		 2738pci_map_failed:
2739 stats->pci_map_fail_cnt++;
2740 stats->mem_freed += skb->truesize;
2741 dev_kfree_skb_irq(skb);
2742 return -ENOMEM;
1da177e4
LT		 2743}
2744
da6971d8
AR		 2745static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2746{
2747 struct net_device *dev = sp->dev;
2748 int j;
2749 struct sk_buff *skb;
1ee6dd77
RB		 2750 struct RxD_t *rxdp;
2751 struct mac_info *mac_control;
2752 struct buffAdd *ba;
6d517a27
VP		 2753 struct RxD1 *rxdp1;
2754 struct RxD3 *rxdp3;
da6971d8
AR		 2755
2756 mac_control = &sp->mac_control;
2757 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2758 rxdp = mac_control->rings[ring_no].
2759 rx_blocks[blk].rxds[j].virt_addr;
2760 skb = (struct sk_buff *)
2761 ((unsigned long) rxdp->Host_Control);
2762 if (!skb) {
2763 continue;
2764 }
2765 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2766 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2767 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2768 rxdp1->Buffer0_ptr,
2769 dev->mtu +
2770 HEADER_ETHERNET_II_802_3_SIZE
2771 + HEADER_802_2_SIZE +
2772 HEADER_SNAP_SIZE,
2773 PCI_DMA_FROMDEVICE);
1ee6dd77 2774 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2775 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2776 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2777 ba = &mac_control->rings[ring_no].
2778 ba[blk][j];
2779 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2780 rxdp3->Buffer0_ptr,
2781 BUF0_LEN,
da6971d8
AR		 2782 PCI_DMA_FROMDEVICE);
2783 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2784 rxdp3->Buffer1_ptr,
2785 BUF1_LEN,
da6971d8
AR		 2786 PCI_DMA_FROMDEVICE);
2787 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2788 rxdp3->Buffer2_ptr,
2789 dev->mtu + 4,
da6971d8 2790 PCI_DMA_FROMDEVICE);
1ee6dd77 2791 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2792 }
491976b2 2793 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8 2794 dev_kfree_skb(skb);
0425b46a 2795 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2796 }
2797}
2798
1da177e4 2799/**
20346722 2800 * free_rx_buffers - Frees all Rx buffers
1da177e4 2801 * @sp: device private variable.
20346722 2802 * Description:
1da177e4
LT		 2803 * This function will free all Rx buffers allocated by host.
2804 * Return Value:
2805 * NONE.
2806 */
2807
2808static void free_rx_buffers(struct s2io_nic *sp)
2809{
2810 struct net_device *dev = sp->dev;
da6971d8 2811 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2812 struct mac_info *mac_control;
1da177e4 2813 struct config_param *config;
1da177e4
LT		 2814
2815 mac_control = &sp->mac_control;
2816 config = &sp->config;
2817
2818 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2819 struct ring_info *ring = &mac_control->rings[i];
2820
da6971d8
AR		 2821 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2822 free_rxd_blk(sp,i,blk);
1da177e4 2823
13d866a9
JP		 2824 ring->rx_curr_put_info.block_index = 0;
2825 ring->rx_curr_get_info.block_index = 0;
2826 ring->rx_curr_put_info.offset = 0;
2827 ring->rx_curr_get_info.offset = 0;
2828 ring->rx_bufs_left = 0;
1da177e4
LT		 2829 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2830 dev->name, buf_cnt, i);
2831 }
2832}
2833
8d8bb39b 2834static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2835{
8d8bb39b 2836 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
f61e0a35
SH		 2837 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2838 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2839 }
2840 return 0;
2841}
2842
1da177e4
LT		 2843/**
2844 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2845 * @napi : pointer to the napi structure.
20346722 2846 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2847 * during one pass through the 'Poll" function.
2848 * Description:
2849 * Comes into picture only if NAPI support has been incorporated. It does
2850 * the same thing that rx_intr_handler does, but not in a interrupt context
2851 * also It will process only a given number of packets.
2852 * Return value:
2853 * 0 on success and 1 if there are No Rx packets to be processed.
2854 */
2855
f61e0a35 2856static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2857{
f61e0a35
SH		 2858 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2859 struct net_device *dev = ring->dev;
1da177e4 2860 struct config_param *config;
f61e0a35
SH		 2861 struct mac_info *mac_control;
2862 int pkts_processed = 0;
1a79d1c3
AV		 2863 u8 __iomem *addr = NULL;
2864 u8 val8 = 0;
4cf1653a 2865 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2867 int budget_org = budget;
1da177e4 2868
1da177e4 2869 config = &nic->config;
f61e0a35 2870 mac_control = &nic->mac_control;
1da177e4 2871
f61e0a35
SH		 2872 if (unlikely(!is_s2io_card_up(nic)))
2873 return 0;
1da177e4 2874
f61e0a35 2875 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2876 s2io_chk_rx_buffers(nic, ring);
1da177e4 2877
f61e0a35 2878 if (pkts_processed < budget_org) {
288379f0 2879 napi_complete(napi);
f61e0a35 2880 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2881 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2882 addr += 7 - ring->ring_no;
2883 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2884 writeb(val8, addr);
2885 val8 = readb(addr);
1da177e4 2886 }
f61e0a35
SH		 2887 return pkts_processed;
2888}
2889static int s2io_poll_inta(struct napi_struct *napi, int budget)
2890{
2891 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2892 struct config_param *config;
2893 struct mac_info *mac_control;
2894 int pkts_processed = 0;
2895 int ring_pkts_processed, i;
2896 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2897 int budget_org = budget;
1da177e4 2898
f61e0a35
SH		 2899 config = &nic->config;
2900 mac_control = &nic->mac_control;
1da177e4 2901
f61e0a35
SH		 2902 if (unlikely(!is_s2io_card_up(nic)))
2903 return 0;
1da177e4 2904
1da177e4 2905 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2906 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2907 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2908 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2909 pkts_processed += ring_pkts_processed;
2910 budget -= ring_pkts_processed;
2911 if (budget <= 0)
1da177e4 2912 break;
1da177e4 2913 }
f61e0a35 2914 if (pkts_processed < budget_org) {
288379f0 2915 napi_complete(napi);
f61e0a35
SH		 2916 /* Re enable the Rx interrupts for the ring */
2917 writeq(0, &bar0->rx_traffic_mask);
2918 readl(&bar0->rx_traffic_mask);
2919 }
2920 return pkts_processed;
1da177e4 2921}
20346722 2922
b41477f3 2923#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2924/**
b41477f3 2925 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2926 * @dev : pointer to the device structure.
2927 * Description:
b41477f3
AR		 2928 * This function will be called by upper layer to check for events on the
2929 * interface in situations where interrupts are disabled. It is used for
2930 * specific in-kernel networking tasks, such as remote consoles and kernel
2931 * debugging over the network (example netdump in RedHat).
612eff0e 2932 */
612eff0e
BH		 2933static void s2io_netpoll(struct net_device *dev)
2934{
4cf1653a 2935 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2936 struct mac_info *mac_control;
612eff0e 2937 struct config_param *config;
1ee6dd77 2938 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2939 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2940 int i;
2941
d796fdb7
LV		 2942 if (pci_channel_offline(nic->pdev))
2943 return;
2944
612eff0e
BH		 2945 disable_irq(dev->irq);
2946
612eff0e
BH		 2947 mac_control = &nic->mac_control;
2948 config = &nic->config;
2949
612eff0e 2950 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2951 writeq(val64, &bar0->tx_traffic_int);
2952
6aa20a22 2953 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2954 * run out of skbs and will fail and eventually netpoll application such
2955 * as netdump will fail.
2956 */
2957 for (i = 0; i < config->tx_fifo_num; i++)
2958 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2959
b41477f3 2960 /* check for received packet and indicate up to network */
13d866a9
JP		 2961 for (i = 0; i < config->rx_ring_num; i++) {
2962 struct ring_info *ring = &mac_control->rings[i];
2963
2964 rx_intr_handler(ring, 0);
2965 }
612eff0e
BH		 2966
2967 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2968 struct ring_info *ring = &mac_control->rings[i];
2969
2970 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
0c61ed5f
RV		 2971 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2972 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2973 break;
2974 }
2975 }
612eff0e
BH		 2976 enable_irq(dev->irq);
2977 return;
2978}
2979#endif
2980
20346722 2981/**
1da177e4 2982 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2983 * @ring_info: per ring structure.
2984 * @budget: budget for napi processing.
20346722 2985 * Description:
2986 * If the interrupt is because of a received frame or if the
1da177e4 2987 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2988 * called. It picks out the RxD at which place the last Rx processing had
2989 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2990 * the offset.
2991 * Return Value:
f61e0a35 2992 * No. of napi packets processed.
1da177e4 2993 */
f61e0a35 2994static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2995{
c9fcbf47 2996 int get_block, put_block;
1ee6dd77
RB		 2997 struct rx_curr_get_info get_info, put_info;
2998 struct RxD_t *rxdp;
1da177e4 2999 struct sk_buff *skb;
f61e0a35 3000 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 3001 int i;
6d517a27
VP		 3002 struct RxD1* rxdp1;
3003 struct RxD3* rxdp3;
7d3d0439 3004
20346722 3005 get_info = ring_data->rx_curr_get_info;
3006 get_block = get_info.block_index;
1ee6dd77 3007 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 3008 put_block = put_info.block_index;
da6971d8 3009 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 3010
da6971d8 3011 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 3012 /*
3013 * If your are next to put index then it's
3014 * FIFO full condition
3015 */
da6971d8
AR		 3016 if ((get_block == put_block) &&
3017 (get_info.offset + 1) == put_info.offset) {
0425b46a
SH		 3018 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
3019 ring_data->dev->name);
da6971d8
AR		 3020 break;
3021 }
20346722 3022 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
3023 if (skb == NULL) {
3024 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 3025 ring_data->dev->name);
20346722 3026 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
f61e0a35 3027 return 0;
1da177e4 3028 }
0425b46a 3029 if (ring_data->rxd_mode == RXD_MODE_1) {
6d517a27 3030 rxdp1 = (struct RxD1*)rxdp;
0425b46a 3031 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3032 rxdp1->Buffer0_ptr,
0425b46a 3033 ring_data->mtu +
6d517a27
VP		 3034 HEADER_ETHERNET_II_802_3_SIZE +
3035 HEADER_802_2_SIZE +
3036 HEADER_SNAP_SIZE,
3037 PCI_DMA_FROMDEVICE);
0425b46a 3038 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
6d517a27 3039 rxdp3 = (struct RxD3*)rxdp;
0425b46a 3040 pci_dma_sync_single_for_cpu(ring_data->pdev, (dma_addr_t)
6d517a27
VP		 3041 rxdp3->Buffer0_ptr,
3042 BUF0_LEN, PCI_DMA_FROMDEVICE);
0425b46a 3043 pci_unmap_single(ring_data->pdev, (dma_addr_t)
6d517a27 3044 rxdp3->Buffer2_ptr,
0425b46a 3045 ring_data->mtu + 4,
6d517a27 3046 PCI_DMA_FROMDEVICE);
da6971d8 3047 }
863c11a9 3048 prefetch(skb->data);
20346722 3049 rx_osm_handler(ring_data, rxdp);
3050 get_info.offset++;
da6971d8
AR		 3051 ring_data->rx_curr_get_info.offset = get_info.offset;
3052 rxdp = ring_data->rx_blocks[get_block].
3053 rxds[get_info.offset].virt_addr;
0425b46a 3054 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3055 get_info.offset = 0;
da6971d8 3056 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3057 get_block++;
da6971d8
AR		 3058 if (get_block == ring_data->block_count)
3059 get_block = 0;
3060 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3061 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3062 }
1da177e4 3063
f61e0a35
SH		 3064 if (ring_data->nic->config.napi) {
3065 budget--;
3066 napi_pkts++;
3067 if (!budget)
0425b46a
SH		 3068 break;
3069 }
20346722 3070 pkt_cnt++;
1da177e4
LT		 3071 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3072 break;
3073 }
0425b46a 3074 if (ring_data->lro) {
7d3d0439
RA		 3075 /* Clear all LRO sessions before exiting */
3076 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 3077 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3078 if (lro->in_use) {
0425b46a 3079 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3080 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3081 clear_lro_session(lro);
3082 }
3083 }
3084 }
f61e0a35 3085 return(napi_pkts);
1da177e4 3086}
20346722 3087
3088/**
1da177e4
LT		 3089 * tx_intr_handler - Transmit interrupt handler
3090 * @nic : device private variable
20346722 3091 * Description:
3092 * If an interrupt was raised to indicate DMA complete of the
3093 * Tx packet, this function is called. It identifies the last TxD
3094 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3095 * DMA'ed into the NICs internal memory.
3096 * Return Value:
3097 * NONE
3098 */
3099
1ee6dd77 3100static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3101{
1ee6dd77 3102 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3103 struct tx_curr_get_info get_info, put_info;
3a3d5756 3104 struct sk_buff *skb = NULL;
1ee6dd77 3105 struct TxD *txdlp;
3a3d5756 3106 int pkt_cnt = 0;
2fda096d 3107 unsigned long flags = 0;
f9046eb3 3108 u8 err_mask;
1da177e4 3109
2fda096d
SR		 3110 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3111 return;
3112
20346722 3113 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 3114 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3115 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722 3116 list_virt_addr;
3117 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3118 (get_info.offset != put_info.offset) &&
3119 (txdlp->Host_Control)) {
3120 /* Check for TxD errors */
3121 if (txdlp->Control_1 & TXD_T_CODE) {
3122 unsigned long long err;
3123 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 3124 if (err & 0x1) {
3125 nic->mac_control.stats_info->sw_stat.
3126 parity_err_cnt++;
3127 }
491976b2
SH		 3128
3129 /* update t_code statistics */
f9046eb3
OH		 3130 err_mask = err >> 48;
3131 switch(err_mask) {
491976b2
SH		 3132 case 2:
3133 nic->mac_control.stats_info->sw_stat.
3134 tx_buf_abort_cnt++;
3135 break;
3136
3137 case 3:
3138 nic->mac_control.stats_info->sw_stat.
3139 tx_desc_abort_cnt++;
3140 break;
3141
3142 case 7:
3143 nic->mac_control.stats_info->sw_stat.
3144 tx_parity_err_cnt++;
3145 break;
3146
3147 case 10:
3148 nic->mac_control.stats_info->sw_stat.
3149 tx_link_loss_cnt++;
3150 break;
3151
3152 case 15:
3153 nic->mac_control.stats_info->sw_stat.
3154 tx_list_proc_err_cnt++;
3155 break;
3156 }
20346722 3157 }
1da177e4 3158
fed5eccd 3159 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3160 if (skb == NULL) {
2fda096d 3161 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722 3162 DBG_PRINT(ERR_DBG, "%s: Null skb ",
b39d66a8 3163 __func__);
20346722 3164 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3165 return;
3166 }
3a3d5756 3167 pkt_cnt++;
20346722 3168
20346722 3169 /* Updating the statistics block */
dc56e634 3170 nic->dev->stats.tx_bytes += skb->len;
491976b2 3171 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722 3172 dev_kfree_skb_irq(skb);
3173
3174 get_info.offset++;
863c11a9
AR		 3175 if (get_info.offset == get_info.fifo_len + 1)
3176 get_info.offset = 0;
1ee6dd77 3177 txdlp = (struct TxD *) fifo_data->list_info
20346722 3178 [get_info.offset].list_virt_addr;
3179 fifo_data->tx_curr_get_info.offset =
3180 get_info.offset;
1da177e4
LT		 3181 }
3182
3a3d5756 3183 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3184
3185 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3186}
3187
bd1034f0
AR		 3188/**
3189 * s2io_mdio_write - Function to write in to MDIO registers
3190 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3191 * @addr : address value
3192 * @value : data value
3193 * @dev : pointer to net_device structure
3194 * Description:
3195 * This function is used to write values to the MDIO registers
3196 * NONE
3197 */
3198static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3199{
3200 u64 val64 = 0x0;
4cf1653a 3201 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3203
3204 //address transaction
3205 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3206 | MDIO_MMD_DEV_ADDR(mmd_type)
3207 | MDIO_MMS_PRT_ADDR(0x0);
3208 writeq(val64, &bar0->mdio_control);
3209 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3210 writeq(val64, &bar0->mdio_control);
3211 udelay(100);
3212
3213 //Data transaction
3214 val64 = 0x0;
3215 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3216 | MDIO_MMD_DEV_ADDR(mmd_type)
3217 | MDIO_MMS_PRT_ADDR(0x0)
3218 | MDIO_MDIO_DATA(value)
3219 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3220 writeq(val64, &bar0->mdio_control);
3221 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3222 writeq(val64, &bar0->mdio_control);
3223 udelay(100);
3224
3225 val64 = 0x0;
3226 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3227 | MDIO_MMD_DEV_ADDR(mmd_type)
3228 | MDIO_MMS_PRT_ADDR(0x0)
3229 | MDIO_OP(MDIO_OP_READ_TRANS);
3230 writeq(val64, &bar0->mdio_control);
3231 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3232 writeq(val64, &bar0->mdio_control);
3233 udelay(100);
3234
3235}
3236
3237/**
3238 * s2io_mdio_read - Function to write in to MDIO registers
3239 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3240 * @addr : address value
3241 * @dev : pointer to net_device structure
3242 * Description:
3243 * This function is used to read values to the MDIO registers
3244 * NONE
3245 */
3246static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3247{
3248 u64 val64 = 0x0;
3249 u64 rval64 = 0x0;
4cf1653a 3250 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3252
3253 /* address transaction */
3254 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3255 | MDIO_MMD_DEV_ADDR(mmd_type)
3256 | MDIO_MMS_PRT_ADDR(0x0);
3257 writeq(val64, &bar0->mdio_control);
3258 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3259 writeq(val64, &bar0->mdio_control);
3260 udelay(100);
3261
3262 /* Data transaction */
3263 val64 = 0x0;
3264 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3265 | MDIO_MMD_DEV_ADDR(mmd_type)
3266 | MDIO_MMS_PRT_ADDR(0x0)
3267 | MDIO_OP(MDIO_OP_READ_TRANS);
3268 writeq(val64, &bar0->mdio_control);
3269 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3270 writeq(val64, &bar0->mdio_control);
3271 udelay(100);
3272
3273 /* Read the value from regs */
3274 rval64 = readq(&bar0->mdio_control);
3275 rval64 = rval64 & 0xFFFF0000;
3276 rval64 = rval64 >> 16;
3277 return rval64;
3278}
3279/**
3280 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3281 * @counter : couter value to be updated
3282 * @flag : flag to indicate the status
3283 * @type : counter type
3284 * Description:
3285 * This function is to check the status of the xpak counters value
3286 * NONE
3287 */
3288
3289static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3290{
3291 u64 mask = 0x3;
3292 u64 val64;
3293 int i;
3294 for(i = 0; i <index; i++)
3295 mask = mask << 0x2;
3296
3297 if(flag > 0)
3298 {
3299 *counter = *counter + 1;
3300 val64 = *regs_stat & mask;
3301 val64 = val64 >> (index * 0x2);
3302 val64 = val64 + 1;
3303 if(val64 == 3)
3304 {
3305 switch(type)
3306 {
3307 case 1:
3308 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3309 "service. Excessive temperatures may "
3310 "result in premature transceiver "
3311 "failure \n");
3312 break;
3313 case 2:
3314 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3315 "service Excessive bias currents may "
3316 "indicate imminent laser diode "
3317 "failure \n");
3318 break;
3319 case 3:
3320 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3321 "service Excessive laser output "
3322 "power may saturate far-end "
3323 "receiver\n");
3324 break;
3325 default:
3326 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3327 "type \n");
3328 }
3329 val64 = 0x0;
3330 }
3331 val64 = val64 << (index * 0x2);
3332 *regs_stat = (*regs_stat & (~mask)) | (val64);
3333
3334 } else {
3335 *regs_stat = *regs_stat & (~mask);
3336 }
3337}
3338
3339/**
3340 * s2io_updt_xpak_counter - Function to update the xpak counters
3341 * @dev : pointer to net_device struct
3342 * Description:
3343 * This function is to upate the status of the xpak counters value
3344 * NONE
3345 */
3346static void s2io_updt_xpak_counter(struct net_device *dev)
3347{
3348 u16 flag = 0x0;
3349 u16 type = 0x0;
3350 u16 val16 = 0x0;
3351 u64 val64 = 0x0;
3352 u64 addr = 0x0;
3353
4cf1653a 3354 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3355 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3356
3357 /* Check the communication with the MDIO slave */
40239396 3358 addr = MDIO_CTRL1;
bd1034f0 3359 val64 = 0x0;
40239396 3360 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3361 if((val64 == 0xFFFF) || (val64 == 0x0000))
3362 {
3363 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3364 "Returned %llx\n", (unsigned long long)val64);
3365 return;
3366 }
3367
40239396
BH		 3368 /* Check for the expected value of control reg 1 */
3369 if(val64 != MDIO_CTRL1_SPEED10G)
bd1034f0
AR		 3370 {
3371 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
40239396
BH		 3372 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3373 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3374 return;
3375 }
3376
3377 /* Loading the DOM register to MDIO register */
3378 addr = 0xA100;
40239396
BH		 3379 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3380 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3381
3382 /* Reading the Alarm flags */
3383 addr = 0xA070;
3384 val64 = 0x0;
40239396 3385 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3386
3387 flag = CHECKBIT(val64, 0x7);
3388 type = 1;
3389 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3390 &stat_info->xpak_stat.xpak_regs_stat,
3391 0x0, flag, type);
3392
3393 if(CHECKBIT(val64, 0x6))
3394 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3395
3396 flag = CHECKBIT(val64, 0x3);
3397 type = 2;
3398 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3399 &stat_info->xpak_stat.xpak_regs_stat,
3400 0x2, flag, type);
3401
3402 if(CHECKBIT(val64, 0x2))
3403 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3404
3405 flag = CHECKBIT(val64, 0x1);
3406 type = 3;
3407 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3408 &stat_info->xpak_stat.xpak_regs_stat,
3409 0x4, flag, type);
3410
3411 if(CHECKBIT(val64, 0x0))
3412 stat_info->xpak_stat.alarm_laser_output_power_low++;
3413
3414 /* Reading the Warning flags */
3415 addr = 0xA074;
3416 val64 = 0x0;
40239396 3417 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3418
3419 if(CHECKBIT(val64, 0x7))
3420 stat_info->xpak_stat.warn_transceiver_temp_high++;
3421
3422 if(CHECKBIT(val64, 0x6))
3423 stat_info->xpak_stat.warn_transceiver_temp_low++;
3424
3425 if(CHECKBIT(val64, 0x3))
3426 stat_info->xpak_stat.warn_laser_bias_current_high++;
3427
3428 if(CHECKBIT(val64, 0x2))
3429 stat_info->xpak_stat.warn_laser_bias_current_low++;
3430
3431 if(CHECKBIT(val64, 0x1))
3432 stat_info->xpak_stat.warn_laser_output_power_high++;
3433
3434 if(CHECKBIT(val64, 0x0))
3435 stat_info->xpak_stat.warn_laser_output_power_low++;
3436}
3437
20346722 3438/**
1da177e4 3439 * wait_for_cmd_complete - waits for a command to complete.
20346722 3440 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3441 * s2io_nic structure.
20346722 3442 * Description: Function that waits for a command to Write into RMAC
3443 * ADDR DATA registers to be completed and returns either success or
3444 * error depending on whether the command was complete or not.
1da177e4
LT		 3445 * Return value:
3446 * SUCCESS on success and FAILURE on failure.
3447 */
3448
9fc93a41
SS		 3449static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3450 int bit_state)
1da177e4 3451{
9fc93a41 3452 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3453 u64 val64;
3454
9fc93a41
SS		 3455 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3456 return FAILURE;
3457
3458 do {
c92ca04b 3459 val64 = readq(addr);
9fc93a41
SS		 3460 if (bit_state == S2IO_BIT_RESET) {
3461 if (!(val64 & busy_bit)) {
3462 ret = SUCCESS;
3463 break;
3464 }
3465 } else {
3466 if (!(val64 & busy_bit)) {
3467 ret = SUCCESS;
3468 break;
3469 }
1da177e4 3470 }
c92ca04b
AR		 3471
3472 if(in_interrupt())
9fc93a41 3473 mdelay(delay);
c92ca04b 3474 else
9fc93a41 3475 msleep(delay);
c92ca04b 3476
9fc93a41
SS		 3477 if (++cnt >= 10)
3478 delay = 50;
3479 } while (cnt < 20);
1da177e4
LT		 3480 return ret;
3481}
19a60522
SS		 3482/*
3483 * check_pci_device_id - Checks if the device id is supported
3484 * @id : device id
3485 * Description: Function to check if the pci device id is supported by driver.
3486 * Return value: Actual device id if supported else PCI_ANY_ID
3487 */
3488static u16 check_pci_device_id(u16 id)
3489{
3490 switch (id) {
3491 case PCI_DEVICE_ID_HERC_WIN:
3492 case PCI_DEVICE_ID_HERC_UNI:
3493 return XFRAME_II_DEVICE;
3494 case PCI_DEVICE_ID_S2IO_UNI:
3495 case PCI_DEVICE_ID_S2IO_WIN:
3496 return XFRAME_I_DEVICE;
3497 default:
3498 return PCI_ANY_ID;
3499 }
3500}
1da177e4 3501
20346722 3502/**
3503 * s2io_reset - Resets the card.
1da177e4
LT		 3504 * @sp : private member of the device structure.
3505 * Description: Function to Reset the card. This function then also
20346722 3506 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3507 * the card reset also resets the configuration space.
3508 * Return value:
3509 * void.
3510 */
3511
1ee6dd77 3512static void s2io_reset(struct s2io_nic * sp)
1da177e4 3513{
1ee6dd77 3514 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3515 u64 val64;
5e25b9dd 3516 u16 subid, pci_cmd;
19a60522
SS		 3517 int i;
3518 u16 val16;
491976b2
SH		 3519 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3520 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3521
19a60522 3522 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
b39d66a8 3523 __func__, sp->dev->name);
1da177e4 3524
0b1f7ebe 3525 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3526 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3527
1da177e4
LT		 3528 val64 = SW_RESET_ALL;
3529 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3530 if (strstr(sp->product_name, "CX4")) {
3531 msleep(750);
3532 }
19a60522
SS		 3533 msleep(250);
3534 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3535
19a60522
SS		 3536 /* Restore the PCI state saved during initialization. */
3537 pci_restore_state(sp->pdev);
3538 pci_read_config_word(sp->pdev, 0x2, &val16);
3539 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3540 break;
3541 msleep(200);
3542 }
1da177e4 3543
19a60522 3544 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
b39d66a8 3545 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __func__);
19a60522
SS		 3546 }
3547
3548 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3549
3550 s2io_init_pci(sp);
1da177e4 3551
20346722 3552 /* Set swapper to enable I/O register access */
3553 s2io_set_swapper(sp);
3554
faa4f796
SH		 3555 /* restore mac_addr entries */
3556 do_s2io_restore_unicast_mc(sp);
3557
cc6e7c44
RA		 3558 /* Restore the MSIX table entries from local variables */
3559 restore_xmsi_data(sp);
3560
5e25b9dd 3561 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3562 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3563 /* Clear "detected parity error" bit */
303bcb4b 3564 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3565
303bcb4b 3566 /* Clearing PCIX Ecc status register */
3567 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3568
303bcb4b 3569 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3570 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3571 }
5e25b9dd 3572
20346722 3573 /* Reset device statistics maintained by OS */
3574 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3575
491976b2
SH		 3576 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3577 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3578 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3579 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3580 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3581 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3582 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3583 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3584 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3585 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3586 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3587 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3588 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3589 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3590 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3591 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3592 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3593 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3594 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3595
1da177e4
LT		 3596 /* SXE-002: Configure link and activity LED to turn it off */
3597 subid = sp->pdev->subsystem_device;
541ae68f 3598 if (((subid & 0xFF) >= 0x07) &&
3599 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3600 val64 = readq(&bar0->gpio_control);
3601 val64 |= 0x0000800000000000ULL;
3602 writeq(val64, &bar0->gpio_control);
3603 val64 = 0x0411040400000000ULL;
509a2671 3604 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3605 }
3606
541ae68f 3607 /*
3608 * Clear spurious ECC interrupts that would have occured on
3609 * XFRAME II cards after reset.
3610 */
3611 if (sp->device_type == XFRAME_II_DEVICE) {
3612 val64 = readq(&bar0->pcc_err_reg);
3613 writeq(val64, &bar0->pcc_err_reg);
3614 }
3615
f957bcf0 3616 sp->device_enabled_once = false;
1da177e4
LT		 3617}
3618
3619/**
20346722 3620 * s2io_set_swapper - to set the swapper controle on the card
3621 * @sp : private member of the device structure,
1da177e4 3622 * pointer to the s2io_nic structure.
20346722 3623 * Description: Function to set the swapper control on the card
1da177e4
LT		 3624 * correctly depending on the 'endianness' of the system.
3625 * Return value:
3626 * SUCCESS on success and FAILURE on failure.
3627 */
3628
1ee6dd77 3629static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3630{
3631 struct net_device *dev = sp->dev;
1ee6dd77 3632 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3633 u64 val64, valt, valr;
3634
20346722 3635 /*
1da177e4
LT		 3636 * Set proper endian settings and verify the same by reading
3637 * the PIF Feed-back register.
3638 */
3639
3640 val64 = readq(&bar0->pif_rd_swapper_fb);
3641 if (val64 != 0x0123456789ABCDEFULL) {
3642 int i = 0;
3643 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3644 0x8100008181000081ULL, /* FE=1, SE=0 */
3645 0x4200004242000042ULL, /* FE=0, SE=1 */
3646 0}; /* FE=0, SE=0 */
3647
3648 while(i<4) {
3649 writeq(value[i], &bar0->swapper_ctrl);
3650 val64 = readq(&bar0->pif_rd_swapper_fb);
3651 if (val64 == 0x0123456789ABCDEFULL)
3652 break;
3653 i++;
3654 }
3655 if (i == 4) {
3656 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3657 dev->name);
3658 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3659 (unsigned long long) val64);
3660 return FAILURE;
3661 }
3662 valr = value[i];
3663 } else {
3664 valr = readq(&bar0->swapper_ctrl);
3665 }
3666
3667 valt = 0x0123456789ABCDEFULL;
3668 writeq(valt, &bar0->xmsi_address);
3669 val64 = readq(&bar0->xmsi_address);
3670
3671 if(val64 != valt) {
3672 int i = 0;
3673 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3674 0x0081810000818100ULL, /* FE=1, SE=0 */
3675 0x0042420000424200ULL, /* FE=0, SE=1 */
3676 0}; /* FE=0, SE=0 */
3677
3678 while(i<4) {
3679 writeq((value[i] | valr), &bar0->swapper_ctrl);
3680 writeq(valt, &bar0->xmsi_address);
3681 val64 = readq(&bar0->xmsi_address);
3682 if(val64 == valt)
3683 break;
3684 i++;
3685 }
3686 if(i == 4) {
20346722 3687 unsigned long long x = val64;
1da177e4 3688 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3689 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3690 return FAILURE;
3691 }
3692 }
3693 val64 = readq(&bar0->swapper_ctrl);
3694 val64 &= 0xFFFF000000000000ULL;
3695
3696#ifdef __BIG_ENDIAN
20346722 3697 /*
3698 * The device by default set to a big endian format, so a
1da177e4
LT		 3699 * big endian driver need not set anything.
3700 */
3701 val64 |= (SWAPPER_CTRL_TXP_FE |
3702 SWAPPER_CTRL_TXP_SE |
3703 SWAPPER_CTRL_TXD_R_FE |
3704 SWAPPER_CTRL_TXD_W_FE |
3705 SWAPPER_CTRL_TXF_R_FE |
3706 SWAPPER_CTRL_RXD_R_FE |
3707 SWAPPER_CTRL_RXD_W_FE |
3708 SWAPPER_CTRL_RXF_W_FE |
3709 SWAPPER_CTRL_XMSI_FE |
1da177e4 3710 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3711 if (sp->config.intr_type == INTA)
cc6e7c44 3712 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3713 writeq(val64, &bar0->swapper_ctrl);
3714#else
20346722 3715 /*
1da177e4 3716 * Initially we enable all bits to make it accessible by the
20346722 3717 * driver, then we selectively enable only those bits that
1da177e4
LT		 3718 * we want to set.
3719 */
3720 val64 |= (SWAPPER_CTRL_TXP_FE |
3721 SWAPPER_CTRL_TXP_SE |
3722 SWAPPER_CTRL_TXD_R_FE |
3723 SWAPPER_CTRL_TXD_R_SE |
3724 SWAPPER_CTRL_TXD_W_FE |
3725 SWAPPER_CTRL_TXD_W_SE |
3726 SWAPPER_CTRL_TXF_R_FE |
3727 SWAPPER_CTRL_RXD_R_FE |
3728 SWAPPER_CTRL_RXD_R_SE |
3729 SWAPPER_CTRL_RXD_W_FE |
3730 SWAPPER_CTRL_RXD_W_SE |
3731 SWAPPER_CTRL_RXF_W_FE |
3732 SWAPPER_CTRL_XMSI_FE |
1da177e4 3733 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3734 if (sp->config.intr_type == INTA)
cc6e7c44 3735 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3736 writeq(val64, &bar0->swapper_ctrl);
3737#endif
3738 val64 = readq(&bar0->swapper_ctrl);
3739
20346722 3740 /*
3741 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3742 * feedback register.
3743 */
3744 val64 = readq(&bar0->pif_rd_swapper_fb);
3745 if (val64 != 0x0123456789ABCDEFULL) {
3746 /* Endian settings are incorrect, calls for another dekko. */
3747 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3748 dev->name);
3749 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3750 (unsigned long long) val64);
3751 return FAILURE;
3752 }
3753
3754 return SUCCESS;
3755}
3756
1ee6dd77 3757static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3758{
1ee6dd77 3759 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3760 u64 val64;
3761 int ret = 0, cnt = 0;
3762
3763 do {
3764 val64 = readq(&bar0->xmsi_access);
b7b5a128 3765 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3766 break;
3767 mdelay(1);
3768 cnt++;
3769 } while(cnt < 5);
3770 if (cnt == 5) {
3771 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3772 ret = 1;
3773 }
3774
3775 return ret;
3776}
3777
1ee6dd77 3778static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3779{
1ee6dd77 3780 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3781 u64 val64;
f61e0a35
SH		 3782 int i, msix_index;
3783
3784
3785 if (nic->device_type == XFRAME_I_DEVICE)
3786 return;
cc6e7c44 3787
75c30b13 3788 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35 3789 msix_index = (i) ? ((i-1) * 8 + 1): 0;
cc6e7c44
RA		 3790 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3791 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3792 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3793 writeq(val64, &bar0->xmsi_access);
f61e0a35 3794 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3795 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3796 continue;
3797 }
3798 }
3799}
3800
1ee6dd77 3801static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3802{
1ee6dd77 3803 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3804 u64 val64, addr, data;
f61e0a35
SH		 3805 int i, msix_index;
3806
3807 if (nic->device_type == XFRAME_I_DEVICE)
3808 return;
cc6e7c44
RA		 3809
3810 /* Store and display */
75c30b13 3811 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
f61e0a35
SH		 3812 msix_index = (i) ? ((i-1) * 8 + 1): 0;
3813 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3814 writeq(val64, &bar0->xmsi_access);
f61e0a35 3815 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3816 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3817 continue;
3818 }
3819 addr = readq(&bar0->xmsi_address);
3820 data = readq(&bar0->xmsi_data);
3821 if (addr && data) {
3822 nic->msix_info[i].addr = addr;
3823 nic->msix_info[i].data = data;
3824 }
3825 }
3826}
3827
1ee6dd77 3828static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3829{
1ee6dd77 3830 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3831 u64 rx_mat;
cc6e7c44
RA		 3832 u16 msi_control; /* Temp variable */
3833 int ret, i, j, msix_indx = 1;
4f870320 3834 int size;
cc6e7c44 3835
4f870320 3836 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3837 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3838 if (!nic->entries) {
491976b2 3839 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
b39d66a8 3840 __func__);
c53d4945 3841 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3842 return -ENOMEM;
3843 }
4f870320 3844 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
f61e0a35 3845
4f870320 3846 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3847 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3848 if (!nic->s2io_entries) {
8a4bdbaa 3849 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
b39d66a8 3850 __func__);
c53d4945 3851 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3852 kfree(nic->entries);
8a4bdbaa 3853 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3854 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3855 return -ENOMEM;
3856 }
4f870320 3857 nic->mac_control.stats_info->sw_stat.mem_allocated += size;
cc6e7c44 3858
ac731ab6
SH		 3859 nic->entries[0].entry = 0;
3860 nic->s2io_entries[0].entry = 0;
3861 nic->s2io_entries[0].in_use = MSIX_FLG;
3862 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3863 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3864
f61e0a35
SH		 3865 for (i = 1; i < nic->num_entries; i++) {
3866 nic->entries[i].entry = ((i - 1) * 8) + 1;
3867 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3868 nic->s2io_entries[i].arg = NULL;
3869 nic->s2io_entries[i].in_use = 0;
3870 }
3871
8a4bdbaa 3872 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3873 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3874 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3875 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3876 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3877 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3878 msix_indx += 8;
cc6e7c44 3879 }
8a4bdbaa 3880 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3881 readq(&bar0->rx_mat);
cc6e7c44 3882
f61e0a35 3883 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3884 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3885 if (ret) {
073a2436 3886 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
cc6e7c44 3887 kfree(nic->entries);
8a4bdbaa 3888 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3889 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44 3890 kfree(nic->s2io_entries);
8a4bdbaa 3891 nic->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 3892 += (nic->num_entries * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3893 nic->entries = NULL;
3894 nic->s2io_entries = NULL;
3895 return -ENOMEM;
3896 }
3897
3898 /*
3899 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3900 * in the herc NIC. (Temp change, needs to be removed later)
3901 */
3902 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3903 msi_control |= 0x1; /* Enable MSI */
3904 pci_write_config_word(nic->pdev, 0x42, msi_control);
3905
3906 return 0;
3907}
3908
8abc4d5b 3909/* Handle software interrupt used during MSI(X) test */
33390a70 3910static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3911{
3912 struct s2io_nic *sp = dev_id;
3913
3914 sp->msi_detected = 1;
3915 wake_up(&sp->msi_wait);
3916
3917 return IRQ_HANDLED;
3918}
3919
3920/* Test interrupt path by forcing a a software IRQ */
33390a70 3921static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3922{
3923 struct pci_dev *pdev = sp->pdev;
3924 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3925 int err;
3926 u64 val64, saved64;
3927
3928 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3929 sp->name, sp);
3930 if (err) {
3931 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3932 sp->dev->name, pci_name(pdev), pdev->irq);
3933 return err;
3934 }
3935
3936 init_waitqueue_head (&sp->msi_wait);
3937 sp->msi_detected = 0;
3938
3939 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3940 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3941 val64 |= SCHED_INT_CTRL_TIMER_EN;
3942 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3943 writeq(val64, &bar0->scheduled_int_ctrl);
3944
3945 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3946
3947 if (!sp->msi_detected) {
3948 /* MSI(X) test failed, go back to INTx mode */
2450022a 3949 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3950 "using MSI(X) during test\n", sp->dev->name,
3951 pci_name(pdev));
3952
3953 err = -EOPNOTSUPP;
3954 }
3955
3956 free_irq(sp->entries[1].vector, sp);
3957
3958 writeq(saved64, &bar0->scheduled_int_ctrl);
3959
3960 return err;
3961}
18b2b7bd
SH		 3962
3963static void remove_msix_isr(struct s2io_nic *sp)
3964{
3965 int i;
3966 u16 msi_control;
3967
f61e0a35 3968 for (i = 0; i < sp->num_entries; i++) {
18b2b7bd
SH		 3969 if (sp->s2io_entries[i].in_use ==
3970 MSIX_REGISTERED_SUCCESS) {
3971 int vector = sp->entries[i].vector;
3972 void *arg = sp->s2io_entries[i].arg;
3973 free_irq(vector, arg);
3974 }
3975 }
3976
3977 kfree(sp->entries);
3978 kfree(sp->s2io_entries);
3979 sp->entries = NULL;
3980 sp->s2io_entries = NULL;
3981
3982 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3983 msi_control &= 0xFFFE; /* Disable MSI */
3984 pci_write_config_word(sp->pdev, 0x42, msi_control);
3985
3986 pci_disable_msix(sp->pdev);
3987}
3988
3989static void remove_inta_isr(struct s2io_nic *sp)
3990{
3991 struct net_device *dev = sp->dev;
3992
3993 free_irq(sp->pdev->irq, dev);
3994}
3995
1da177e4
LT		 3996/* ********************************************************* *
3997 * Functions defined below concern the OS part of the driver *
3998 * ********************************************************* */
3999
20346722 4000/**
1da177e4
LT		 4001 * s2io_open - open entry point of the driver
4002 * @dev : pointer to the device structure.
4003 * Description:
4004 * This function is the open entry point of the driver. It mainly calls a
4005 * function to allocate Rx buffers and inserts them into the buffer
20346722 4006 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 4007 * Return value:
4008 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4009 * file on failure.
4010 */
4011
ac1f60db 4012static int s2io_open(struct net_device *dev)
1da177e4 4013{
4cf1653a 4014 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4015 int err = 0;
4016
20346722 4017 /*
4018 * Make sure you have link off by default every time
1da177e4
LT		 4019 * Nic is initialized
4020 */
4021 netif_carrier_off(dev);
0b1f7ebe 4022 sp->last_link_state = 0;
1da177e4
LT		 4023
4024 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 4025 err = s2io_card_up(sp);
4026 if (err) {
1da177e4
LT		 4027 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
4028 dev->name);
e6a8fee2 4029 goto hw_init_failed;
1da177e4
LT		 4030 }
4031
2fd37688 4032 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4033 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4034 s2io_card_down(sp);
20346722 4035 err = -ENODEV;
e6a8fee2 4036 goto hw_init_failed;
1da177e4 4037 }
3a3d5756 4038 s2io_start_all_tx_queue(sp);
1da177e4 4039 return 0;
20346722 4040
20346722 4041hw_init_failed:
eaae7f72 4042 if (sp->config.intr_type == MSI_X) {
491976b2 4043 if (sp->entries) {
cc6e7c44 4044 kfree(sp->entries);
8a4bdbaa 4045 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4046 += (sp->num_entries * sizeof(struct msix_entry));
491976b2
SH		 4047 }
4048 if (sp->s2io_entries) {
cc6e7c44 4049 kfree(sp->s2io_entries);
8a4bdbaa 4050 sp->mac_control.stats_info->sw_stat.mem_freed
f61e0a35 4051 += (sp->num_entries * sizeof(struct s2io_msix_entry));
491976b2 4052 }
cc6e7c44 4053 }
20346722 4054 return err;
1da177e4
LT		 4055}
4056
4057/**
4058 * s2io_close -close entry point of the driver
4059 * @dev : device pointer.
4060 * Description:
4061 * This is the stop entry point of the driver. It needs to undo exactly
4062 * whatever was done by the open entry point,thus it's usually referred to
4063 * as the close function.Among other things this function mainly stops the
4064 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4065 * Return value:
4066 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4067 * file on failure.
4068 */
4069
ac1f60db 4070static int s2io_close(struct net_device *dev)
1da177e4 4071{
4cf1653a 4072 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4073 struct config_param *config = &sp->config;
4074 u64 tmp64;
4075 int offset;
cc6e7c44 4076
9f74ffde
SH		 4077 /* Return if the device is already closed *
4078 * Can happen when s2io_card_up failed in change_mtu *
4079 */
4080 if (!is_s2io_card_up(sp))
4081 return 0;
4082
3a3d5756 4083 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4084 /* delete all populated mac entries */
4085 for (offset = 1; offset < config->max_mc_addr; offset++) {
4086 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4087 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4088 do_s2io_delete_unicast_mc(sp, tmp64);
4089 }
4090
e6a8fee2 4091 s2io_card_down(sp);
cc6e7c44 4092
1da177e4
LT		 4093 return 0;
4094}
4095
4096/**
4097 * s2io_xmit - Tx entry point of te driver
4098 * @skb : the socket buffer containing the Tx data.
4099 * @dev : device pointer.
4100 * Description :
4101 * This function is the Tx entry point of the driver. S2IO NIC supports
4102 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4103 * NOTE: when device cant queue the pkt,just the trans_start variable will
4104 * not be upadted.
4105 * Return value:
4106 * 0 on success & 1 on failure.
4107 */
4108
ac1f60db 4109static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4110{
4cf1653a 4111 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4112 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4113 register u64 val64;
1ee6dd77
RB		 4114 struct TxD *txdp;
4115 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4116 unsigned long flags = 0;
be3a6b02 4117 u16 vlan_tag = 0;
2fda096d 4118 struct fifo_info *fifo = NULL;
1ee6dd77 4119 struct mac_info *mac_control;
1da177e4 4120 struct config_param *config;
6cfc482b 4121 int do_spin_lock = 1;
75c30b13 4122 int offload_type;
6cfc482b 4123 int enable_per_list_interrupt = 0;
491abf25 4124 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4125
4126 mac_control = &sp->mac_control;
4127 config = &sp->config;
4128
20346722 4129 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4130
4131 if (unlikely(skb->len <= 0)) {
4132 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4133 dev_kfree_skb_any(skb);
6ed10654 4134 return NETDEV_TX_OK;
2fda096d 4135 }
491976b2 4136
92b84437 4137 if (!is_s2io_card_up(sp)) {
20346722 4138 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4139 dev->name);
20346722 4140 dev_kfree_skb(skb);
6ed10654 4141 return NETDEV_TX_OK;
1da177e4
LT		 4142 }
4143
4144 queue = 0;
3a3d5756 4145 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4146 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4147 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4148 if (skb->protocol == htons(ETH_P_IP)) {
4149 struct iphdr *ip;
4150 struct tcphdr *th;
4151 ip = ip_hdr(skb);
4152
4153 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4154 th = (struct tcphdr *)(((unsigned char *)ip) +
4155 ip->ihl*4);
4156
4157 if (ip->protocol == IPPROTO_TCP) {
4158 queue_len = sp->total_tcp_fifos;
4159 queue = (ntohs(th->source) +
4160 ntohs(th->dest)) &
4161 sp->fifo_selector[queue_len - 1];
4162 if (queue >= queue_len)
4163 queue = queue_len - 1;
4164 } else if (ip->protocol == IPPROTO_UDP) {
4165 queue_len = sp->total_udp_fifos;
4166 queue = (ntohs(th->source) +
4167 ntohs(th->dest)) &
4168 sp->fifo_selector[queue_len - 1];
4169 if (queue >= queue_len)
4170 queue = queue_len - 1;
4171 queue += sp->udp_fifo_idx;
4172 if (skb->len > 1024)
4173 enable_per_list_interrupt = 1;
4174 do_spin_lock = 0;
4175 }
4176 }
4177 }
4178 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4179 /* get fifo number based on skb->priority value */
4180 queue = config->fifo_mapping
4181 [skb->priority & (MAX_TX_FIFOS - 1)];
4182 fifo = &mac_control->fifos[queue];
3a3d5756 4183
6cfc482b
SH		 4184 if (do_spin_lock)
4185 spin_lock_irqsave(&fifo->tx_lock, flags);
4186 else {
4187 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4188 return NETDEV_TX_LOCKED;
4189 }
be3a6b02 4190
3a3d5756
SH		 4191 if (sp->config.multiq) {
4192 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4193 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4194 return NETDEV_TX_BUSY;
4195 }
b19fa1fa 4196 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4197 if (netif_queue_stopped(dev)) {
4198 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4199 return NETDEV_TX_BUSY;
4200 }
4201 }
4202
2fda096d
SR		 4203 put_off = (u16) fifo->tx_curr_put_info.offset;
4204 get_off = (u16) fifo->tx_curr_get_info.offset;
4205 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4206
2fda096d 4207 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4208 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4209 if (txdp->Host_Control ||
4210 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4211 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4212 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4213 dev_kfree_skb(skb);
2fda096d 4214 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4215 return NETDEV_TX_OK;
1da177e4 4216 }
0b1f7ebe 4217
75c30b13 4218 offload_type = s2io_offload_type(skb);
75c30b13 4219 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4220 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4221 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4222 }
84fa7933 4223 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4224 txdp->Control_2 |=
4225 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4226 TXD_TX_CKO_UDP_EN);
4227 }
fed5eccd
AR		 4228 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4229 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4230 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4231 if (enable_per_list_interrupt)
4232 if (put_off & (queue_len >> 5))
4233 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4234 if (vlan_tag) {
be3a6b02 4235 txdp->Control_2 |= TXD_VLAN_ENABLE;
4236 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4237 }
4238
fed5eccd 4239 frg_len = skb->len - skb->data_len;
75c30b13 4240 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4241 int ufo_size;
4242
75c30b13 4243 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4244 ufo_size &= ~7;
4245 txdp->Control_1 |= TXD_UFO_EN;
4246 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4247 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4248#ifdef __BIG_ENDIAN
3459feb8 4249 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4250 fifo->ufo_in_band_v[put_off] =
3459feb8 4251 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4252#else
2fda096d 4253 fifo->ufo_in_band_v[put_off] =
3459feb8 4254 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4255#endif
2fda096d 4256 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4257 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4258 fifo->ufo_in_band_v,
fed5eccd 4259 sizeof(u64), PCI_DMA_TODEVICE);
8d8bb39b 4260 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4261 goto pci_map_failed;
fed5eccd 4262 txdp++;
fed5eccd 4263 }
1da177e4 4264
fed5eccd
AR		 4265 txdp->Buffer_Pointer = pci_map_single
4266 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4267 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4268 goto pci_map_failed;
4269
fed5eccd
AR		 4270 txdp->Host_Control = (unsigned long) skb;
4271 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4272 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4273 txdp->Control_1 |= TXD_UFO_EN;
4274
4275 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4276 /* For fragmented SKB. */
4277 for (i = 0; i < frg_cnt; i++) {
4278 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4279 /* A '0' length fragment will be ignored */
4280 if (!frag->size)
4281 continue;
1da177e4
LT		 4282 txdp++;
4283 txdp->Buffer_Pointer = (u64) pci_map_page
4284 (sp->pdev, frag->page, frag->page_offset,
4285 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4286 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4287 if (offload_type == SKB_GSO_UDP)
fed5eccd 4288 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4289 }
4290 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4291
75c30b13 4292 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4293 frg_cnt++; /* as Txd0 was used for inband header */
4294
1da177e4 4295 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4296 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4297 writeq(val64, &tx_fifo->TxDL_Pointer);
4298
4299 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4300 TX_FIFO_LAST_LIST);
75c30b13 4301 if (offload_type)
fed5eccd 4302 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4303
1da177e4
LT		 4304 writeq(val64, &tx_fifo->List_Control);
4305
303bcb4b 4306 mmiowb();
4307
1da177e4 4308 put_off++;
2fda096d 4309 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4310 put_off = 0;
2fda096d 4311 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4312
4313 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4314 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4315 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4316 DBG_PRINT(TX_DBG,
4317 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4318 put_off, get_off);
3a3d5756 4319 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4320 }
491976b2 4321 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
2fda096d 4322 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4323
f6f4bfa3
SH		 4324 if (sp->config.intr_type == MSI_X)
4325 tx_intr_handler(fifo);
4326
6ed10654 4327 return NETDEV_TX_OK;
491abf25
VP		 4328pci_map_failed:
4329 stats->pci_map_fail_cnt++;
3a3d5756 4330 s2io_stop_tx_queue(sp, fifo->fifo_no);
491abf25
VP		 4331 stats->mem_freed += skb->truesize;
4332 dev_kfree_skb(skb);
2fda096d 4333 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4334 return NETDEV_TX_OK;
1da177e4
LT		 4335}
4336
25fff88e 4337static void
4338s2io_alarm_handle(unsigned long data)
4339{
1ee6dd77 4340 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4341 struct net_device *dev = sp->dev;
25fff88e 4342
8116f3cf 4343 s2io_handle_errors(dev);
25fff88e 4344 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4345}
4346
7d12e780 4347static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4348{
1ee6dd77
RB		 4349 struct ring_info *ring = (struct ring_info *)dev_id;
4350 struct s2io_nic *sp = ring->nic;
f61e0a35 4351 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4352
f61e0a35 4353 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4354 return IRQ_HANDLED;
92b84437 4355
f61e0a35 4356 if (sp->config.napi) {
1a79d1c3
AV		 4357 u8 __iomem *addr = NULL;
4358 u8 val8 = 0;
f61e0a35 4359
1a79d1c3 4360 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4361 addr += (7 - ring->ring_no);
4362 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4363 writeb(val8, addr);
4364 val8 = readb(addr);
288379f0 4365 napi_schedule(&ring->napi);
f61e0a35
SH		 4366 } else {
4367 rx_intr_handler(ring, 0);
8d8bb39b 4368 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4369 }
7d3d0439 4370
cc6e7c44
RA		 4371 return IRQ_HANDLED;
4372}
4373
7d12e780 4374static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4375{
ac731ab6
SH		 4376 int i;
4377 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4378 struct s2io_nic *sp = fifos->nic;
4379 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4380 struct config_param *config = &sp->config;
4381 u64 reason;
cc6e7c44 4382
ac731ab6
SH		 4383 if (unlikely(!is_s2io_card_up(sp)))
4384 return IRQ_NONE;
4385
4386 reason = readq(&bar0->general_int_status);
4387 if (unlikely(reason == S2IO_MINUS_ONE))
4388 /* Nothing much can be done. Get out */
92b84437 4389 return IRQ_HANDLED;
92b84437 4390
01e16faa
SH		 4391 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4392 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4393
01e16faa
SH		 4394 if (reason & GEN_INTR_TXPIC)
4395 s2io_txpic_intr_handle(sp);
ac731ab6 4396
01e16faa
SH		 4397 if (reason & GEN_INTR_TXTRAFFIC)
4398 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4399
01e16faa
SH		 4400 for (i = 0; i < config->tx_fifo_num; i++)
4401 tx_intr_handler(&fifos[i]);
ac731ab6 4402
01e16faa
SH		 4403 writeq(sp->general_int_mask, &bar0->general_int_mask);
4404 readl(&bar0->general_int_status);
4405 return IRQ_HANDLED;
4406 }
4407 /* The interrupt was not raised by us */
4408 return IRQ_NONE;
cc6e7c44 4409}
ac731ab6 4410
1ee6dd77 4411static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4412{
1ee6dd77 4413 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4414 u64 val64;
4415
4416 val64 = readq(&bar0->pic_int_status);
4417 if (val64 & PIC_INT_GPIO) {
4418 val64 = readq(&bar0->gpio_int_reg);
4419 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4420 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4421 /*
4422 * This is unstable state so clear both up/down
4423 * interrupt and adapter to re-evaluate the link state.
4424 */
a371a07d 4425 val64 |= GPIO_INT_REG_LINK_DOWN;
4426 val64 |= GPIO_INT_REG_LINK_UP;
4427 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4428 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4429 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4430 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4431 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4432 }
c92ca04b
AR		 4433 else if (val64 & GPIO_INT_REG_LINK_UP) {
4434 val64 = readq(&bar0->adapter_status);
c92ca04b 4435 /* Enable Adapter */
19a60522
SS		 4436 val64 = readq(&bar0->adapter_control);
4437 val64 |= ADAPTER_CNTL_EN;
4438 writeq(val64, &bar0->adapter_control);
4439 val64 |= ADAPTER_LED_ON;
4440 writeq(val64, &bar0->adapter_control);
4441 if (!sp->device_enabled_once)
4442 sp->device_enabled_once = 1;
c92ca04b 4443
19a60522
SS		 4444 s2io_link(sp, LINK_UP);
4445 /*
4446 * unmask link down interrupt and mask link-up
4447 * intr
4448 */
4449 val64 = readq(&bar0->gpio_int_mask);
4450 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4451 val64 |= GPIO_INT_MASK_LINK_UP;
4452 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4453
c92ca04b
AR		 4454 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4455 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4456 s2io_link(sp, LINK_DOWN);
4457 /* Link is down so unmaks link up interrupt */
4458 val64 = readq(&bar0->gpio_int_mask);
4459 val64 &= ~GPIO_INT_MASK_LINK_UP;
4460 val64 |= GPIO_INT_MASK_LINK_DOWN;
4461 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4462
4463 /* turn off LED */
4464 val64 = readq(&bar0->adapter_control);
4465 val64 = val64 &(~ADAPTER_LED_ON);
4466 writeq(val64, &bar0->adapter_control);
a371a07d 4467 }
4468 }
c92ca04b 4469 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4470}
4471
8116f3cf
SS		 4472/**
4473 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4474 * @value: alarm bits
4475 * @addr: address value
4476 * @cnt: counter variable
4477 * Description: Check for alarm and increment the counter
4478 * Return Value:
4479 * 1 - if alarm bit set
4480 * 0 - if alarm bit is not set
4481 */
43b7c451 4482static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4483 unsigned long long *cnt)
4484{
4485 u64 val64;
4486 val64 = readq(addr);
4487 if ( val64 & value ) {
4488 writeq(val64, addr);
4489 (*cnt)++;
4490 return 1;
4491 }
4492 return 0;
4493
4494}
4495
4496/**
4497 * s2io_handle_errors - Xframe error indication handler
4498 * @nic: device private variable
4499 * Description: Handle alarms such as loss of link, single or
4500 * double ECC errors, critical and serious errors.
4501 * Return Value:
4502 * NONE
4503 */
4504static void s2io_handle_errors(void * dev_id)
4505{
4506 struct net_device *dev = (struct net_device *) dev_id;
4cf1653a 4507 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf
SS		 4508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4509 u64 temp64 = 0,val64=0;
4510 int i = 0;
4511
4512 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4513 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4514
92b84437 4515 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4516 return;
4517
4518 if (pci_channel_offline(sp->pdev))
4519 return;
4520
4521 memset(&sw_stat->ring_full_cnt, 0,
4522 sizeof(sw_stat->ring_full_cnt));
4523
4524 /* Handling the XPAK counters update */
4525 if(stats->xpak_timer_count < 72000) {
4526 /* waiting for an hour */
4527 stats->xpak_timer_count++;
4528 } else {
4529 s2io_updt_xpak_counter(dev);
4530 /* reset the count to zero */
4531 stats->xpak_timer_count = 0;
4532 }
4533
4534 /* Handling link status change error Intr */
4535 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4536 val64 = readq(&bar0->mac_rmac_err_reg);
4537 writeq(val64, &bar0->mac_rmac_err_reg);
4538 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4539 schedule_work(&sp->set_link_task);
4540 }
4541
4542 /* In case of a serious error, the device will be Reset. */
4543 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4544 &sw_stat->serious_err_cnt))
4545 goto reset;
4546
4547 /* Check for data parity error */
4548 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4549 &sw_stat->parity_err_cnt))
4550 goto reset;
4551
4552 /* Check for ring full counter */
4553 if (sp->device_type == XFRAME_II_DEVICE) {
4554 val64 = readq(&bar0->ring_bump_counter1);
4555 for (i=0; i<4; i++) {
4556 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4557 temp64 >>= 64 - ((i+1)*16);
4558 sw_stat->ring_full_cnt[i] += temp64;
4559 }
4560
4561 val64 = readq(&bar0->ring_bump_counter2);
4562 for (i=0; i<4; i++) {
4563 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4564 temp64 >>= 64 - ((i+1)*16);
4565 sw_stat->ring_full_cnt[i+4] += temp64;
4566 }
4567 }
4568
4569 val64 = readq(&bar0->txdma_int_status);
4570 /*check for pfc_err*/
4571 if (val64 & TXDMA_PFC_INT) {
4572 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4573 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4574 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4575 &sw_stat->pfc_err_cnt))
4576 goto reset;
4577 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4578 &sw_stat->pfc_err_cnt);
4579 }
4580
4581 /*check for tda_err*/
4582 if (val64 & TXDMA_TDA_INT) {
4583 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4584 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4585 &sw_stat->tda_err_cnt))
4586 goto reset;
4587 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4588 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4589 }
4590 /*check for pcc_err*/
4591 if (val64 & TXDMA_PCC_INT) {
4592 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4593 | PCC_N_SERR | PCC_6_COF_OV_ERR
4594 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4595 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4596 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4597 &sw_stat->pcc_err_cnt))
4598 goto reset;
4599 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4600 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4601 }
4602
4603 /*check for tti_err*/
4604 if (val64 & TXDMA_TTI_INT) {
4605 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4606 &sw_stat->tti_err_cnt))
4607 goto reset;
4608 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4609 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4610 }
4611
4612 /*check for lso_err*/
4613 if (val64 & TXDMA_LSO_INT) {
4614 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4615 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4616 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4617 goto reset;
4618 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4619 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4620 }
4621
4622 /*check for tpa_err*/
4623 if (val64 & TXDMA_TPA_INT) {
4624 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4625 &sw_stat->tpa_err_cnt))
4626 goto reset;
4627 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4628 &sw_stat->tpa_err_cnt);
4629 }
4630
4631 /*check for sm_err*/
4632 if (val64 & TXDMA_SM_INT) {
4633 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4634 &sw_stat->sm_err_cnt))
4635 goto reset;
4636 }
4637
4638 val64 = readq(&bar0->mac_int_status);
4639 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4640 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4641 &bar0->mac_tmac_err_reg,
4642 &sw_stat->mac_tmac_err_cnt))
4643 goto reset;
4644 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4645 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4646 &bar0->mac_tmac_err_reg,
4647 &sw_stat->mac_tmac_err_cnt);
4648 }
4649
4650 val64 = readq(&bar0->xgxs_int_status);
4651 if (val64 & XGXS_INT_STATUS_TXGXS) {
4652 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4653 &bar0->xgxs_txgxs_err_reg,
4654 &sw_stat->xgxs_txgxs_err_cnt))
4655 goto reset;
4656 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4657 &bar0->xgxs_txgxs_err_reg,
4658 &sw_stat->xgxs_txgxs_err_cnt);
4659 }
4660
4661 val64 = readq(&bar0->rxdma_int_status);
4662 if (val64 & RXDMA_INT_RC_INT_M) {
4663 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4664 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4665 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4666 goto reset;
4667 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4668 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4669 &sw_stat->rc_err_cnt);
4670 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4671 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4672 &sw_stat->prc_pcix_err_cnt))
4673 goto reset;
4674 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4675 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4676 &sw_stat->prc_pcix_err_cnt);
4677 }
4678
4679 if (val64 & RXDMA_INT_RPA_INT_M) {
4680 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4681 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4682 goto reset;
4683 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4684 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4685 }
4686
4687 if (val64 & RXDMA_INT_RDA_INT_M) {
4688 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4689 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4690 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4691 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4692 goto reset;
4693 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4694 | RDA_MISC_ERR | RDA_PCIX_ERR,
4695 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4696 }
4697
4698 if (val64 & RXDMA_INT_RTI_INT_M) {
4699 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4700 &sw_stat->rti_err_cnt))
4701 goto reset;
4702 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4703 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4704 }
4705
4706 val64 = readq(&bar0->mac_int_status);
4707 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4708 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4709 &bar0->mac_rmac_err_reg,
4710 &sw_stat->mac_rmac_err_cnt))
4711 goto reset;
4712 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4713 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4714 &sw_stat->mac_rmac_err_cnt);
4715 }
4716
4717 val64 = readq(&bar0->xgxs_int_status);
4718 if (val64 & XGXS_INT_STATUS_RXGXS) {
4719 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4720 &bar0->xgxs_rxgxs_err_reg,
4721 &sw_stat->xgxs_rxgxs_err_cnt))
4722 goto reset;
4723 }
4724
4725 val64 = readq(&bar0->mc_int_status);
4726 if(val64 & MC_INT_STATUS_MC_INT) {
4727 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4728 &sw_stat->mc_err_cnt))
4729 goto reset;
4730
4731 /* Handling Ecc errors */
4732 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4733 writeq(val64, &bar0->mc_err_reg);
4734 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4735 sw_stat->double_ecc_errs++;
4736 if (sp->device_type != XFRAME_II_DEVICE) {
4737 /*
4738 * Reset XframeI only if critical error
4739 */
4740 if (val64 &
4741 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4742 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4743 goto reset;
4744 }
4745 } else
4746 sw_stat->single_ecc_errs++;
4747 }
4748 }
4749 return;
4750
4751reset:
3a3d5756 4752 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4753 schedule_work(&sp->rst_timer_task);
4754 sw_stat->soft_reset_cnt++;
4755 return;
4756}
4757
1da177e4
LT		 4758/**
4759 * s2io_isr - ISR handler of the device .
4760 * @irq: the irq of the device.
4761 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4762 * Description: This function is the ISR handler of the device. It
4763 * identifies the reason for the interrupt and calls the relevant
4764 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4765 * recv buffers, if their numbers are below the panic value which is
4766 * presently set to 25% of the original number of rcv buffers allocated.
4767 * Return value:
20346722 4768 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4769 * IRQ_NONE: will be returned if interrupt is not from our device
4770 */
7d12e780 4771static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4772{
4773 struct net_device *dev = (struct net_device *) dev_id;
4cf1653a 4774 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4775 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4776 int i;
19a60522 4777 u64 reason = 0;
1ee6dd77 4778 struct mac_info *mac_control;
1da177e4
LT		 4779 struct config_param *config;
4780
d796fdb7
LV		 4781 /* Pretend we handled any irq's from a disconnected card */
4782 if (pci_channel_offline(sp->pdev))
4783 return IRQ_NONE;
4784
596c5c97 4785 if (!is_s2io_card_up(sp))
92b84437 4786 return IRQ_NONE;
92b84437 4787
1da177e4
LT		 4788 mac_control = &sp->mac_control;
4789 config = &sp->config;
4790
20346722 4791 /*
1da177e4
LT		 4792 * Identify the cause for interrupt and call the appropriate
4793 * interrupt handler. Causes for the interrupt could be;
4794 * 1. Rx of packet.
4795 * 2. Tx complete.
4796 * 3. Link down.
1da177e4
LT		 4797 */
4798 reason = readq(&bar0->general_int_status);
4799
596c5c97
SS		 4800 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4801 /* Nothing much can be done. Get out */
4802 return IRQ_HANDLED;
1da177e4 4803 }
5d3213cc 4804
596c5c97
SS		 4805 if (reason & (GEN_INTR_RXTRAFFIC |
4806 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4807 {
4808 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4809
4810 if (config->napi) {
4811 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4812 napi_schedule(&sp->napi);
f61e0a35
SH		 4813 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4814 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4815 readl(&bar0->rx_traffic_int);
db874e65 4816 }
596c5c97
SS		 4817 } else {
4818 /*
4819 * rx_traffic_int reg is an R1 register, writing all 1's
4820 * will ensure that the actual interrupt causing bit
4821 * get's cleared and hence a read can be avoided.
4822 */
4823 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4824 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4825
13d866a9
JP		 4826 for (i = 0; i < config->rx_ring_num; i++) {
4827 struct ring_info *ring = &mac_control->rings[i];
4828
4829 rx_intr_handler(ring, 0);
4830 }
db874e65 4831 }
596c5c97 4832
db874e65 4833 /*
596c5c97 4834 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4835 * will ensure that the actual interrupt causing bit get's
4836 * cleared and hence a read can be avoided.
4837 */
596c5c97
SS		 4838 if (reason & GEN_INTR_TXTRAFFIC)
4839 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4840
596c5c97
SS		 4841 for (i = 0; i < config->tx_fifo_num; i++)
4842 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4843
596c5c97
SS		 4844 if (reason & GEN_INTR_TXPIC)
4845 s2io_txpic_intr_handle(sp);
fe113638 4846
596c5c97
SS		 4847 /*
4848 * Reallocate the buffers from the interrupt handler itself.
4849 */
4850 if (!config->napi) {
13d866a9
JP		 4851 for (i = 0; i < config->rx_ring_num; i++) {
4852 struct ring_info *ring = &mac_control->rings[i];
4853
4854 s2io_chk_rx_buffers(sp, ring);
4855 }
596c5c97
SS		 4856 }
4857 writeq(sp->general_int_mask, &bar0->general_int_mask);
4858 readl(&bar0->general_int_status);
20346722 4859
596c5c97 4860 return IRQ_HANDLED;
db874e65 4861
596c5c97
SS		 4862 }
4863 else if (!reason) {
4864 /* The interrupt was not raised by us */
4865 return IRQ_NONE;
4866 }
db874e65 4867
1da177e4
LT		 4868 return IRQ_HANDLED;
4869}
4870
7ba013ac 4871/**
4872 * s2io_updt_stats -
4873 */
1ee6dd77 4874static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4875{
1ee6dd77 4876 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4877 u64 val64;
4878 int cnt = 0;
4879
92b84437 4880 if (is_s2io_card_up(sp)) {
7ba013ac 4881 /* Apprx 30us on a 133 MHz bus */
4882 val64 = SET_UPDT_CLICKS(10) |
4883 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4884 writeq(val64, &bar0->stat_cfg);
4885 do {
4886 udelay(100);
4887 val64 = readq(&bar0->stat_cfg);
b7b5a128 4888 if (!(val64 & s2BIT(0)))
7ba013ac 4889 break;
4890 cnt++;
4891 if (cnt == 5)
4892 break; /* Updt failed */
4893 } while(1);
8a4bdbaa 4894 }
7ba013ac 4895}
4896
1da177e4 4897/**
20346722 4898 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4899 * @dev : pointer to the device structure.
4900 * Description:
20346722 4901 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4902 * structure and returns a pointer to the same.
4903 * Return value:
4904 * pointer to the updated net_device_stats structure.
4905 */
4906
ac1f60db 4907static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4908{
4cf1653a 4909 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4910 struct mac_info *mac_control;
1da177e4 4911 struct config_param *config;
0425b46a 4912 int i;
1da177e4 4913
20346722 4914
1da177e4
LT		 4915 mac_control = &sp->mac_control;
4916 config = &sp->config;
4917
7ba013ac 4918 /* Configure Stats for immediate updt */
4919 s2io_updt_stats(sp);
4920
dc56e634
BL		 4921 /* Using sp->stats as a staging area, because reset (due to mtu
4922 change, for example) will clear some hardware counters */
4923 dev->stats.tx_packets +=
4924 le32_to_cpu(mac_control->stats_info->tmac_frms) -
4925 sp->stats.tx_packets;
7ba013ac 4926 sp->stats.tx_packets =
4927 le32_to_cpu(mac_control->stats_info->tmac_frms);
dc56e634
BL		 4928 dev->stats.tx_errors +=
4929 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms) -
4930 sp->stats.tx_errors;
20346722 4931 sp->stats.tx_errors =
4932 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
dc56e634
BL		 4933 dev->stats.rx_errors +=
4934 le64_to_cpu(mac_control->stats_info->rmac_drop_frms) -
4935 sp->stats.rx_errors;
20346722 4936 sp->stats.rx_errors =
ee705dba 4937 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
dc56e634
BL		 4938 dev->stats.multicast =
4939 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms) -
4940 sp->stats.multicast;
20346722 4941 sp->stats.multicast =
4942 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
dc56e634
BL		 4943 dev->stats.rx_length_errors =
4944 le64_to_cpu(mac_control->stats_info->rmac_long_frms) -
4945 sp->stats.rx_length_errors;
1da177e4 4946 sp->stats.rx_length_errors =
ee705dba 4947 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4 4948
0425b46a 4949 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4950 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4951 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4952 struct ring_info *ring = &mac_control->rings[i];
4953
4954 dev->stats.rx_packets += ring->rx_packets;
4955 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4956 }
4957
dc56e634 4958 return (&dev->stats);
1da177e4
LT		 4959}
4960
4961/**
4962 * s2io_set_multicast - entry point for multicast address enable/disable.
4963 * @dev : pointer to the device structure
4964 * Description:
20346722 4965 * This function is a driver entry point which gets called by the kernel
4966 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4967 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4968 * determine, if multicast address must be enabled or if promiscuous mode
4969 * is to be disabled etc.
4970 * Return value:
4971 * void.
4972 */
4973
4974static void s2io_set_multicast(struct net_device *dev)
4975{
4976 int i, j, prev_cnt;
4977 struct dev_mc_list *mclist;
4cf1653a 4978 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4979 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4980 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4981 0xfeffffffffffULL;
faa4f796 4982 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4983 void __iomem *add;
faa4f796 4984 struct config_param *config = &sp->config;
1da177e4
LT		 4985
4986 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4987 /* Enable all Multicast addresses */
4988 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4989 &bar0->rmac_addr_data0_mem);
4990 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4991 &bar0->rmac_addr_data1_mem);
4992 val64 = RMAC_ADDR_CMD_MEM_WE |
4993 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4994 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4995 writeq(val64, &bar0->rmac_addr_cmd_mem);
4996 /* Wait till command completes */
c92ca04b 4997 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4998 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4999 S2IO_BIT_RESET);
1da177e4
LT		 5000
5001 sp->m_cast_flg = 1;
faa4f796 5002 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5003 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5004 /* Disable all Multicast addresses */
5005 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5006 &bar0->rmac_addr_data0_mem);
5e25b9dd 5007 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5008 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5009 val64 = RMAC_ADDR_CMD_MEM_WE |
5010 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5011 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5012 writeq(val64, &bar0->rmac_addr_cmd_mem);
5013 /* Wait till command completes */
c92ca04b 5014 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5015 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5016 S2IO_BIT_RESET);
1da177e4
LT		 5017
5018 sp->m_cast_flg = 0;
5019 sp->all_multi_pos = 0;
5020 }
5021
5022 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5023 /* Put the NIC into promiscuous mode */
5024 add = &bar0->mac_cfg;
5025 val64 = readq(&bar0->mac_cfg);
5026 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5027
5028 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5029 writel((u32) val64, add);
5030 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5031 writel((u32) (val64 >> 32), (add + 4));
5032
926930b2
SS		 5033 if (vlan_tag_strip != 1) {
5034 val64 = readq(&bar0->rx_pa_cfg);
5035 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5036 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5037 sp->vlan_strip_flag = 0;
926930b2
SS		 5038 }
5039
1da177e4
LT		 5040 val64 = readq(&bar0->mac_cfg);
5041 sp->promisc_flg = 1;
776bd20f 5042 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5043 dev->name);
5044 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5045 /* Remove the NIC from promiscuous mode */
5046 add = &bar0->mac_cfg;
5047 val64 = readq(&bar0->mac_cfg);
5048 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5049
5050 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5051 writel((u32) val64, add);
5052 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5053 writel((u32) (val64 >> 32), (add + 4));
5054
926930b2
SS		 5055 if (vlan_tag_strip != 0) {
5056 val64 = readq(&bar0->rx_pa_cfg);
5057 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5058 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5059 sp->vlan_strip_flag = 1;
926930b2
SS		 5060 }
5061
1da177e4
LT		 5062 val64 = readq(&bar0->mac_cfg);
5063 sp->promisc_flg = 0;
776bd20f 5064 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5065 dev->name);
5066 }
5067
5068 /* Update individual M_CAST address list */
5069 if ((!sp->m_cast_flg) && dev->mc_count) {
5070 if (dev->mc_count >
faa4f796 5071 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5072 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5073 dev->name);
5074 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5075 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5076 return;
5077 }
5078
5079 prev_cnt = sp->mc_addr_count;
5080 sp->mc_addr_count = dev->mc_count;
5081
5082 /* Clear out the previous list of Mc in the H/W. */
5083 for (i = 0; i < prev_cnt; i++) {
5084 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5085 &bar0->rmac_addr_data0_mem);
5086 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5087 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5088 val64 = RMAC_ADDR_CMD_MEM_WE |
5089 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5090 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5091 (config->mc_start_offset + i);
1da177e4
LT		 5092 writeq(val64, &bar0->rmac_addr_cmd_mem);
5093
5094 /* Wait for command completes */
c92ca04b 5095 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5096 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5097 S2IO_BIT_RESET)) {
1da177e4
LT		 5098 DBG_PRINT(ERR_DBG, "%s: Adding ",
5099 dev->name);
5100 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5101 return;
5102 }
5103 }
5104
5105 /* Create the new Rx filter list and update the same in H/W. */
5106 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5107 i++, mclist = mclist->next) {
5108 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5109 ETH_ALEN);
a7a80d5a 5110 mac_addr = 0;
1da177e4
LT		 5111 for (j = 0; j < ETH_ALEN; j++) {
5112 mac_addr |= mclist->dmi_addr[j];
5113 mac_addr <<= 8;
5114 }
5115 mac_addr >>= 8;
5116 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5117 &bar0->rmac_addr_data0_mem);
5118 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 5119 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 5120 val64 = RMAC_ADDR_CMD_MEM_WE |
5121 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5122 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 5123 (i + config->mc_start_offset);
1da177e4
LT		 5124 writeq(val64, &bar0->rmac_addr_cmd_mem);
5125
5126 /* Wait for command completes */
c92ca04b 5127 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 5128 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5129 S2IO_BIT_RESET)) {
1da177e4
LT		 5130 DBG_PRINT(ERR_DBG, "%s: Adding ",
5131 dev->name);
5132 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5133 return;
5134 }
5135 }
5136 }
5137}
5138
faa4f796
SH		 5139/* read from CAM unicast & multicast addresses and store it in
5140 * def_mac_addr structure
5141 */
dac499f9 5142static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5143{
5144 int offset;
5145 u64 mac_addr = 0x0;
5146 struct config_param *config = &sp->config;
5147
5148 /* store unicast & multicast mac addresses */
5149 for (offset = 0; offset < config->max_mc_addr; offset++) {
5150 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5151 /* if read fails disable the entry */
5152 if (mac_addr == FAILURE)
5153 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5154 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5155 }
5156}
5157
5158/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5159static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5160{
5161 int offset;
5162 struct config_param *config = &sp->config;
5163 /* restore unicast mac address */
5164 for (offset = 0; offset < config->max_mac_addr; offset++)
5165 do_s2io_prog_unicast(sp->dev,
5166 sp->def_mac_addr[offset].mac_addr);
5167
5168 /* restore multicast mac address */
5169 for (offset = config->mc_start_offset;
5170 offset < config->max_mc_addr; offset++)
5171 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5172}
5173
5174/* add a multicast MAC address to CAM */
5175static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5176{
5177 int i;
5178 u64 mac_addr = 0;
5179 struct config_param *config = &sp->config;
5180
5181 for (i = 0; i < ETH_ALEN; i++) {
5182 mac_addr <<= 8;
5183 mac_addr |= addr[i];
5184 }
5185 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5186 return SUCCESS;
5187
5188 /* check if the multicast mac already preset in CAM */
5189 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5190 u64 tmp64;
5191 tmp64 = do_s2io_read_unicast_mc(sp, i);
5192 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5193 break;
5194
5195 if (tmp64 == mac_addr)
5196 return SUCCESS;
5197 }
5198 if (i == config->max_mc_addr) {
5199 DBG_PRINT(ERR_DBG,
5200 "CAM full no space left for multicast MAC\n");
5201 return FAILURE;
5202 }
5203 /* Update the internal structure with this new mac address */
5204 do_s2io_copy_mac_addr(sp, i, mac_addr);
5205
5206 return (do_s2io_add_mac(sp, mac_addr, i));
5207}
5208
5209/* add MAC address to CAM */
5210static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5211{
5212 u64 val64;
5213 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5214
5215 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5216 &bar0->rmac_addr_data0_mem);
5217
5218 val64 =
5219 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5220 RMAC_ADDR_CMD_MEM_OFFSET(off);
5221 writeq(val64, &bar0->rmac_addr_cmd_mem);
5222
5223 /* Wait till command completes */
5224 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5225 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5226 S2IO_BIT_RESET)) {
faa4f796 5227 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5228 return FAILURE;
5229 }
5230 return SUCCESS;
5231}
faa4f796
SH		 5232/* deletes a specified unicast/multicast mac entry from CAM */
5233static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5234{
5235 int offset;
5236 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5237 struct config_param *config = &sp->config;
5238
5239 for (offset = 1;
5240 offset < config->max_mc_addr; offset++) {
5241 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5242 if (tmp64 == addr) {
5243 /* disable the entry by writing 0xffffffffffffULL */
5244 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5245 return FAILURE;
5246 /* store the new mac list from CAM */
5247 do_s2io_store_unicast_mc(sp);
5248 return SUCCESS;
5249 }
5250 }
5251 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5252 (unsigned long long)addr);
5253 return FAILURE;
5254}
5255
5256/* read mac entries from CAM */
5257static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5258{
5259 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5260 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5261
5262 /* read mac addr */
5263 val64 =
5264 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5265 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5266 writeq(val64, &bar0->rmac_addr_cmd_mem);
5267
5268 /* Wait till command completes */
5269 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5270 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5271 S2IO_BIT_RESET)) {
5272 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5273 return FAILURE;
5274 }
5275 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5276 return (tmp64 >> 16);
5277}
2fd37688
SS		 5278
5279/**
5280 * s2io_set_mac_addr driver entry point
5281 */
faa4f796 5282
2fd37688
SS		 5283static int s2io_set_mac_addr(struct net_device *dev, void *p)
5284{
5285 struct sockaddr *addr = p;
5286
5287 if (!is_valid_ether_addr(addr->sa_data))
5288 return -EINVAL;
5289
5290 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5291
5292 /* store the MAC address in CAM */
5293 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5294}
1da177e4 5295/**
2fd37688 5296 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5297 * @dev : pointer to the device structure.
5298 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5299 * Description : This procedure will program the Xframe to receive
1da177e4 5300 * frames with new Mac Address
20346722 5301 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5302 * as defined in errno.h file on failure.
5303 */
faa4f796 5304
2fd37688 5305static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5306{
4cf1653a 5307 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5308 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5309 int i;
faa4f796
SH		 5310 u64 tmp64;
5311 struct config_param *config = &sp->config;
1da177e4 5312
20346722 5313 /*
2fd37688
SS		 5314 * Set the new MAC address as the new unicast filter and reflect this
5315 * change on the device address registered with the OS. It will be
5316 * at offset 0.
5317 */
1da177e4
LT		 5318 for (i = 0; i < ETH_ALEN; i++) {
5319 mac_addr <<= 8;
5320 mac_addr |= addr[i];
2fd37688
SS		 5321 perm_addr <<= 8;
5322 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5323 }
5324
2fd37688
SS		 5325 /* check if the dev_addr is different than perm_addr */
5326 if (mac_addr == perm_addr)
d8d70caf
SS		 5327 return SUCCESS;
5328
faa4f796
SH		 5329 /* check if the mac already preset in CAM */
5330 for (i = 1; i < config->max_mac_addr; i++) {
5331 tmp64 = do_s2io_read_unicast_mc(sp, i);
5332 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5333 break;
5334
5335 if (tmp64 == mac_addr) {
5336 DBG_PRINT(INFO_DBG,
5337 "MAC addr:0x%llx already present in CAM\n",
5338 (unsigned long long)mac_addr);
5339 return SUCCESS;
5340 }
5341 }
5342 if (i == config->max_mac_addr) {
5343 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5344 return FAILURE;
5345 }
d8d70caf 5346 /* Update the internal structure with this new mac address */
faa4f796
SH		 5347 do_s2io_copy_mac_addr(sp, i, mac_addr);
5348 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5349}
5350
5351/**
20346722 5352 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5353 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5354 * @info: pointer to the structure with parameters given by ethtool to set
5355 * link information.
5356 * Description:
20346722 5357 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5358 * the NIC.
5359 * Return value:
5360 * 0 on success.
5361*/
5362
5363static int s2io_ethtool_sset(struct net_device *dev,
5364 struct ethtool_cmd *info)
5365{
4cf1653a 5366 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5367 if ((info->autoneg == AUTONEG_ENABLE) ||
5368 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5369 return -EINVAL;
5370 else {
5371 s2io_close(sp->dev);
5372 s2io_open(sp->dev);
5373 }
5374
5375 return 0;
5376}
5377
5378/**
20346722 5379 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5380 * @sp : private member of the device structure, pointer to the
5381 * s2io_nic structure.
5382 * @info : pointer to the structure with parameters given by ethtool
5383 * to return link information.
5384 * Description:
5385 * Returns link specific information like speed, duplex etc.. to ethtool.
5386 * Return value :
5387 * return 0 on success.
5388 */
5389
5390static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5391{
4cf1653a 5392 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5393 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5394 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5395 info->port = PORT_FIBRE;
1a7eb72b
SS		 5396
5397 /* info->transceiver */
5398 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5399
5400 if (netif_carrier_ok(sp->dev)) {
5401 info->speed = 10000;
5402 info->duplex = DUPLEX_FULL;
5403 } else {
5404 info->speed = -1;
5405 info->duplex = -1;
5406 }
5407
5408 info->autoneg = AUTONEG_DISABLE;
5409 return 0;
5410}
5411
5412/**
20346722 5413 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5414 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5415 * s2io_nic structure.
5416 * @info : pointer to the structure with parameters given by ethtool to
5417 * return driver information.
5418 * Description:
5419 * Returns driver specefic information like name, version etc.. to ethtool.
5420 * Return value:
5421 * void
5422 */
5423
5424static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5425 struct ethtool_drvinfo *info)
5426{
4cf1653a 5427 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5428
dbc2309d
JL		 5429 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5430 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5431 strncpy(info->fw_version, "", sizeof(info->fw_version));
5432 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5433 info->regdump_len = XENA_REG_SPACE;
5434 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5435}
5436
5437/**
5438 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5439 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5440 * s2io_nic structure.
20346722 5441 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5442 * dumping the registers.
5443 * @reg_space: The input argumnet into which all the registers are dumped.
5444 * Description:
5445 * Dumps the entire register space of xFrame NIC into the user given
5446 * buffer area.
5447 * Return value :
5448 * void .
5449*/
5450
5451static void s2io_ethtool_gregs(struct net_device *dev,
5452 struct ethtool_regs *regs, void *space)
5453{
5454 int i;
5455 u64 reg;
5456 u8 *reg_space = (u8 *) space;
4cf1653a 5457 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5458
5459 regs->len = XENA_REG_SPACE;
5460 regs->version = sp->pdev->subsystem_device;
5461
5462 for (i = 0; i < regs->len; i += 8) {
5463 reg = readq(sp->bar0 + i);
5464 memcpy((reg_space + i), &reg, 8);
5465 }
5466}
5467
5468/**
5469 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5470 * @data : address of the private member of the device structure, which
1da177e4 5471 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 5472 * Description: This is actually the timer function that alternates the
5473 * adapter LED bit of the adapter control bit to set/reset every time on
5474 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5475 * once every second.
5476*/
5477static void s2io_phy_id(unsigned long data)
5478{
1ee6dd77
RB		 5479 struct s2io_nic *sp = (struct s2io_nic *) data;
5480 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5481 u64 val64 = 0;
5482 u16 subid;
5483
5484 subid = sp->pdev->subsystem_device;
541ae68f 5485 if ((sp->device_type == XFRAME_II_DEVICE) ||
5486 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5487 val64 = readq(&bar0->gpio_control);
5488 val64 ^= GPIO_CTRL_GPIO_0;
5489 writeq(val64, &bar0->gpio_control);
5490 } else {
5491 val64 = readq(&bar0->adapter_control);
5492 val64 ^= ADAPTER_LED_ON;
5493 writeq(val64, &bar0->adapter_control);
5494 }
5495
5496 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5497}
5498
5499/**
5500 * s2io_ethtool_idnic - To physically identify the nic on the system.
5501 * @sp : private member of the device structure, which is a pointer to the
5502 * s2io_nic structure.
20346722 5503 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5504 * ethtool.
5505 * Description: Used to physically identify the NIC on the system.
20346722 5506 * The Link LED will blink for a time specified by the user for
1da177e4 5507 * identification.
20346722 5508 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5509 * identification is possible only if it's link is up.
5510 * Return value:
5511 * int , returns 0 on success
5512 */
5513
5514static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5515{
5516 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5517 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5518 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5519 u16 subid;
5520
5521 subid = sp->pdev->subsystem_device;
5522 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f 5523 if ((sp->device_type == XFRAME_I_DEVICE) &&
5524 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5525 val64 = readq(&bar0->adapter_control);
5526 if (!(val64 & ADAPTER_CNTL_EN)) {
5527 printk(KERN_ERR
5528 "Adapter Link down, cannot blink LED\n");
5529 return -EFAULT;
5530 }
5531 }
5532 if (sp->id_timer.function == NULL) {
5533 init_timer(&sp->id_timer);
5534 sp->id_timer.function = s2io_phy_id;
5535 sp->id_timer.data = (unsigned long) sp;
5536 }
5537 mod_timer(&sp->id_timer, jiffies);
5538 if (data)
20346722 5539 msleep_interruptible(data * HZ);
1da177e4 5540 else
20346722 5541 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5542 del_timer_sync(&sp->id_timer);
5543
541ae68f 5544 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5545 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5546 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5547 }
5548
5549 return 0;
5550}
5551
0cec35eb
SH		 5552static void s2io_ethtool_gringparam(struct net_device *dev,
5553 struct ethtool_ringparam *ering)
5554{
4cf1653a 5555 struct s2io_nic *sp = netdev_priv(dev);
0cec35eb
SH		 5556 int i,tx_desc_count=0,rx_desc_count=0;
5557
5558 if (sp->rxd_mode == RXD_MODE_1)
5559 ering->rx_max_pending = MAX_RX_DESC_1;
5560 else if (sp->rxd_mode == RXD_MODE_3B)
5561 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5562
5563 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5564 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5565 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5566
0cec35eb
SH		 5567 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5568 ering->tx_pending = tx_desc_count;
5569 rx_desc_count = 0;
8a4bdbaa 5570 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5571 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5572
0cec35eb
SH		 5573 ering->rx_pending = rx_desc_count;
5574
5575 ering->rx_mini_max_pending = 0;
5576 ering->rx_mini_pending = 0;
5577 if(sp->rxd_mode == RXD_MODE_1)
5578 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5579 else if (sp->rxd_mode == RXD_MODE_3B)
5580 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5581 ering->rx_jumbo_pending = rx_desc_count;
5582}
5583
1da177e4
LT		 5584/**
5585 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5586 * @sp : private member of the device structure, which is a pointer to the
5587 * s2io_nic structure.
1da177e4
LT		 5588 * @ep : pointer to the structure with pause parameters given by ethtool.
5589 * Description:
5590 * Returns the Pause frame generation and reception capability of the NIC.
5591 * Return value:
5592 * void
5593 */
5594static void s2io_ethtool_getpause_data(struct net_device *dev,
5595 struct ethtool_pauseparam *ep)
5596{
5597 u64 val64;
4cf1653a 5598 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5599 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5600
5601 val64 = readq(&bar0->rmac_pause_cfg);
5602 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5603 ep->tx_pause = true;
1da177e4 5604 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5605 ep->rx_pause = true;
5606 ep->autoneg = false;
1da177e4
LT		 5607}
5608
5609/**
5610 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5611 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5612 * s2io_nic structure.
5613 * @ep : pointer to the structure with pause parameters given by ethtool.
5614 * Description:
5615 * It can be used to set or reset Pause frame generation or reception
5616 * support of the NIC.
5617 * Return value:
5618 * int, returns 0 on Success
5619 */
5620
5621static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5622 struct ethtool_pauseparam *ep)
1da177e4
LT		 5623{
5624 u64 val64;
4cf1653a 5625 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5626 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5627
5628 val64 = readq(&bar0->rmac_pause_cfg);
5629 if (ep->tx_pause)
5630 val64 |= RMAC_PAUSE_GEN_ENABLE;
5631 else
5632 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5633 if (ep->rx_pause)
5634 val64 |= RMAC_PAUSE_RX_ENABLE;
5635 else
5636 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5637 writeq(val64, &bar0->rmac_pause_cfg);
5638 return 0;
5639}
5640
5641/**
5642 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5643 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5644 * s2io_nic structure.
5645 * @off : offset at which the data must be written
5646 * @data : Its an output parameter where the data read at the given
20346722 5647 * offset is stored.
1da177e4 5648 * Description:
20346722 5649 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5650 * read data.
5651 * NOTE: Will allow to read only part of the EEPROM visible through the
5652 * I2C bus.
5653 * Return value:
5654 * -1 on failure and 0 on success.
5655 */
5656
5657#define S2IO_DEV_ID 5
1ee6dd77 5658static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5659{
5660 int ret = -1;
5661 u32 exit_cnt = 0;
5662 u64 val64;
1ee6dd77 5663 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5664
ad4ebed0 5665 if (sp->device_type == XFRAME_I_DEVICE) {
5666 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5667 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5668 I2C_CONTROL_CNTL_START;
5669 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5670
ad4ebed0 5671 while (exit_cnt < 5) {
5672 val64 = readq(&bar0->i2c_control);
5673 if (I2C_CONTROL_CNTL_END(val64)) {
5674 *data = I2C_CONTROL_GET_DATA(val64);
5675 ret = 0;
5676 break;
5677 }
5678 msleep(50);
5679 exit_cnt++;
1da177e4 5680 }
1da177e4
LT		 5681 }
5682
ad4ebed0 5683 if (sp->device_type == XFRAME_II_DEVICE) {
5684 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5685 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5686 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5687 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5688 val64 |= SPI_CONTROL_REQ;
5689 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5690 while (exit_cnt < 5) {
5691 val64 = readq(&bar0->spi_control);
5692 if (val64 & SPI_CONTROL_NACK) {
5693 ret = 1;
5694 break;
5695 } else if (val64 & SPI_CONTROL_DONE) {
5696 *data = readq(&bar0->spi_data);
5697 *data &= 0xffffff;
5698 ret = 0;
5699 break;
5700 }
5701 msleep(50);
5702 exit_cnt++;
5703 }
5704 }
1da177e4
LT		 5705 return ret;
5706}
5707
5708/**
5709 * write_eeprom - actually writes the relevant part of the data value.
5710 * @sp : private member of the device structure, which is a pointer to the
5711 * s2io_nic structure.
5712 * @off : offset at which the data must be written
5713 * @data : The data that is to be written
20346722 5714 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5715 * the Eeprom. (max of 3)
5716 * Description:
5717 * Actually writes the relevant part of the data value into the Eeprom
5718 * through the I2C bus.
5719 * Return value:
5720 * 0 on success, -1 on failure.
5721 */
5722
1ee6dd77 5723static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5724{
5725 int exit_cnt = 0, ret = -1;
5726 u64 val64;
1ee6dd77 5727 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5728
ad4ebed0 5729 if (sp->device_type == XFRAME_I_DEVICE) {
5730 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5731 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5732 I2C_CONTROL_CNTL_START;
5733 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5734
5735 while (exit_cnt < 5) {
5736 val64 = readq(&bar0->i2c_control);
5737 if (I2C_CONTROL_CNTL_END(val64)) {
5738 if (!(val64 & I2C_CONTROL_NACK))
5739 ret = 0;
5740 break;
5741 }
5742 msleep(50);
5743 exit_cnt++;
5744 }
5745 }
1da177e4 5746
ad4ebed0 5747 if (sp->device_type == XFRAME_II_DEVICE) {
5748 int write_cnt = (cnt == 8) ? 0 : cnt;
5749 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5750
5751 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5752 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5753 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5754 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5755 val64 |= SPI_CONTROL_REQ;
5756 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5757 while (exit_cnt < 5) {
5758 val64 = readq(&bar0->spi_control);
5759 if (val64 & SPI_CONTROL_NACK) {
5760 ret = 1;
5761 break;
5762 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5763 ret = 0;
ad4ebed0 5764 break;
5765 }
5766 msleep(50);
5767 exit_cnt++;
1da177e4 5768 }
1da177e4 5769 }
1da177e4
LT		 5770 return ret;
5771}
1ee6dd77 5772static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5773{
b41477f3
AR		 5774 u8 *vpd_data;
5775 u8 data;
9dc737a7
AR		 5776 int i=0, cnt, fail = 0;
5777 int vpd_addr = 0x80;
5778
5779 if (nic->device_type == XFRAME_II_DEVICE) {
5780 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5781 vpd_addr = 0x80;
5782 }
5783 else {
5784 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5785 vpd_addr = 0x50;
5786 }
19a60522 5787 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5788
b41477f3 5789 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5790 if (!vpd_data) {
5791 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5792 return;
c53d4945 5793 }
491976b2 5794 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5795
9dc737a7
AR		 5796 for (i = 0; i < 256; i +=4 ) {
5797 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5798 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5799 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5800 for (cnt = 0; cnt <5; cnt++) {
5801 msleep(2);
5802 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5803 if (data == 0x80)
5804 break;
5805 }
5806 if (cnt >= 5) {
5807 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5808 fail = 1;
5809 break;
5810 }
5811 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5812 (u32 *)&vpd_data[i]);
5813 }
19a60522
SS		 5814
5815 if(!fail) {
5816 /* read serial number of adapter */
5817 for (cnt = 0; cnt < 256; cnt++) {
5818 if ((vpd_data[cnt] == 'S') &&
5819 (vpd_data[cnt+1] == 'N') &&
5820 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5821 memset(nic->serial_num, 0, VPD_STRING_LEN);
5822 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5823 vpd_data[cnt+2]);
5824 break;
5825 }
5826 }
5827 }
5828
5829 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5830 memset(nic->product_name, 0, vpd_data[1]);
5831 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5832 }
b41477f3 5833 kfree(vpd_data);
491976b2 5834 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5835}
5836
1da177e4
LT		 5837/**
5838 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5839 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5840 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5841 * containing all relevant information.
5842 * @data_buf : user defined value to be written into Eeprom.
5843 * Description: Reads the values stored in the Eeprom at given offset
5844 * for a given length. Stores these values int the input argument data
5845 * buffer 'data_buf' and returns these to the caller (ethtool.)
5846 * Return value:
5847 * int 0 on success
5848 */
5849
5850static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5851 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5852{
ad4ebed0 5853 u32 i, valid;
5854 u64 data;
4cf1653a 5855 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5856
5857 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5858
5859 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5860 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5861
5862 for (i = 0; i < eeprom->len; i += 4) {
5863 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5864 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5865 return -EFAULT;
5866 }
5867 valid = INV(data);
5868 memcpy((data_buf + i), &valid, 4);
5869 }
5870 return 0;
5871}
5872
5873/**
5874 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5875 * @sp : private member of the device structure, which is a pointer to the
5876 * s2io_nic structure.
20346722 5877 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5878 * containing all relevant information.
5879 * @data_buf ; user defined value to be written into Eeprom.
5880 * Description:
5881 * Tries to write the user provided value in the Eeprom, at the offset
5882 * given by the user.
5883 * Return value:
5884 * 0 on success, -EFAULT on failure.
5885 */
5886
5887static int s2io_ethtool_seeprom(struct net_device *dev,
5888 struct ethtool_eeprom *eeprom,
5889 u8 * data_buf)
5890{
5891 int len = eeprom->len, cnt = 0;
ad4ebed0 5892 u64 valid = 0, data;
4cf1653a 5893 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5894
5895 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5896 DBG_PRINT(ERR_DBG,
5897 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5898 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5899 eeprom->magic);
5900 return -EFAULT;
5901 }
5902
5903 while (len) {
5904 data = (u32) data_buf[cnt] & 0x000000FF;
5905 if (data) {
5906 valid = (u32) (data << 24);
5907 } else
5908 valid = data;
5909
5910 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5911 DBG_PRINT(ERR_DBG,
5912 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5913 DBG_PRINT(ERR_DBG,
5914 "write into the specified offset\n");
5915 return -EFAULT;
5916 }
5917 cnt++;
5918 len--;
5919 }
5920
5921 return 0;
5922}
5923
5924/**
20346722 5925 * s2io_register_test - reads and writes into all clock domains.
5926 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5927 * s2io_nic structure.
5928 * @data : variable that returns the result of each of the test conducted b
5929 * by the driver.
5930 * Description:
5931 * Read and write into all clock domains. The NIC has 3 clock domains,
5932 * see that registers in all the three regions are accessible.
5933 * Return value:
5934 * 0 on success.
5935 */
5936
1ee6dd77 5937static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5938{
1ee6dd77 5939 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5940 u64 val64 = 0, exp_val;
1da177e4
LT		 5941 int fail = 0;
5942
20346722 5943 val64 = readq(&bar0->pif_rd_swapper_fb);
5944 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5945 fail = 1;
5946 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5947 }
5948
5949 val64 = readq(&bar0->rmac_pause_cfg);
5950 if (val64 != 0xc000ffff00000000ULL) {
5951 fail = 1;
5952 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5953 }
5954
5955 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5956 if (sp->device_type == XFRAME_II_DEVICE)
5957 exp_val = 0x0404040404040404ULL;
5958 else
5959 exp_val = 0x0808080808080808ULL;
5960 if (val64 != exp_val) {
1da177e4
LT		 5961 fail = 1;
5962 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5963 }
5964
5965 val64 = readq(&bar0->xgxs_efifo_cfg);
5966 if (val64 != 0x000000001923141EULL) {
5967 fail = 1;
5968 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5969 }
5970
5971 val64 = 0x5A5A5A5A5A5A5A5AULL;
5972 writeq(val64, &bar0->xmsi_data);
5973 val64 = readq(&bar0->xmsi_data);
5974 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5975 fail = 1;
5976 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5977 }
5978
5979 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5980 writeq(val64, &bar0->xmsi_data);
5981 val64 = readq(&bar0->xmsi_data);
5982 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5983 fail = 1;
5984 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5985 }
5986
5987 *data = fail;
ad4ebed0 5988 return fail;
1da177e4
LT		 5989}
5990
5991/**
20346722 5992 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5993 * @sp : private member of the device structure, which is a pointer to the
5994 * s2io_nic structure.
5995 * @data:variable that returns the result of each of the test conducted by
5996 * the driver.
5997 * Description:
20346722 5998 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5999 * register.
6000 * Return value:
6001 * 0 on success.
6002 */
6003
1ee6dd77 6004static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6005{
6006 int fail = 0;
ad4ebed0 6007 u64 ret_data, org_4F0, org_7F0;
6008 u8 saved_4F0 = 0, saved_7F0 = 0;
6009 struct net_device *dev = sp->dev;
1da177e4
LT		 6010
6011 /* Test Write Error at offset 0 */
ad4ebed0 6012 /* Note that SPI interface allows write access to all areas
6013 * of EEPROM. Hence doing all negative testing only for Xframe I.
6014 */
6015 if (sp->device_type == XFRAME_I_DEVICE)
6016 if (!write_eeprom(sp, 0, 0, 3))
6017 fail = 1;
6018
6019 /* Save current values at offsets 0x4F0 and 0x7F0 */
6020 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6021 saved_4F0 = 1;
6022 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6023 saved_7F0 = 1;
1da177e4
LT		 6024
6025 /* Test Write at offset 4f0 */
ad4ebed0 6026 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6027 fail = 1;
6028 if (read_eeprom(sp, 0x4F0, &ret_data))
6029 fail = 1;
6030
ad4ebed0 6031 if (ret_data != 0x012345) {
26b7625c
AM		 6032 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6033 "Data written %llx Data read %llx\n",
6034 dev->name, (unsigned long long)0x12345,
6035 (unsigned long long)ret_data);
1da177e4 6036 fail = 1;
ad4ebed0 6037 }
1da177e4
LT		 6038
6039 /* Reset the EEPROM data go FFFF */
ad4ebed0 6040 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6041
6042 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6043 if (sp->device_type == XFRAME_I_DEVICE)
6044 if (!write_eeprom(sp, 0x07C, 0, 3))
6045 fail = 1;
1da177e4 6046
ad4ebed0 6047 /* Test Write Request at offset 0x7f0 */
6048 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6049 fail = 1;
ad4ebed0 6050 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6051 fail = 1;
6052
ad4ebed0 6053 if (ret_data != 0x012345) {
26b7625c
AM		 6054 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6055 "Data written %llx Data read %llx\n",
6056 dev->name, (unsigned long long)0x12345,
6057 (unsigned long long)ret_data);
1da177e4 6058 fail = 1;
ad4ebed0 6059 }
1da177e4
LT		 6060
6061 /* Reset the EEPROM data go FFFF */
ad4ebed0 6062 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6063
ad4ebed0 6064 if (sp->device_type == XFRAME_I_DEVICE) {
6065 /* Test Write Error at offset 0x80 */
6066 if (!write_eeprom(sp, 0x080, 0, 3))
6067 fail = 1;
1da177e4 6068
ad4ebed0 6069 /* Test Write Error at offset 0xfc */
6070 if (!write_eeprom(sp, 0x0FC, 0, 3))
6071 fail = 1;
1da177e4 6072
ad4ebed0 6073 /* Test Write Error at offset 0x100 */
6074 if (!write_eeprom(sp, 0x100, 0, 3))
6075 fail = 1;
1da177e4 6076
ad4ebed0 6077 /* Test Write Error at offset 4ec */
6078 if (!write_eeprom(sp, 0x4EC, 0, 3))
6079 fail = 1;
6080 }
6081
6082 /* Restore values at offsets 0x4F0 and 0x7F0 */
6083 if (saved_4F0)
6084 write_eeprom(sp, 0x4F0, org_4F0, 3);
6085 if (saved_7F0)
6086 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6087
6088 *data = fail;
ad4ebed0 6089 return fail;
1da177e4
LT		 6090}
6091
6092/**
6093 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6094 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6095 * s2io_nic structure.
20346722 6096 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6097 * the driver.
6098 * Description:
6099 * This invokes the MemBist test of the card. We give around
6100 * 2 secs time for the Test to complete. If it's still not complete
20346722 6101 * within this peiod, we consider that the test failed.
1da177e4
LT		 6102 * Return value:
6103 * 0 on success and -1 on failure.
6104 */
6105
1ee6dd77 6106static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 6107{
6108 u8 bist = 0;
6109 int cnt = 0, ret = -1;
6110
6111 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6112 bist |= PCI_BIST_START;
6113 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6114
6115 while (cnt < 20) {
6116 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6117 if (!(bist & PCI_BIST_START)) {
6118 *data = (bist & PCI_BIST_CODE_MASK);
6119 ret = 0;
6120 break;
6121 }
6122 msleep(100);
6123 cnt++;
6124 }
6125
6126 return ret;
6127}
6128
6129/**
20346722 6130 * s2io-link_test - verifies the link state of the nic
6131 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6132 * s2io_nic structure.
6133 * @data: variable that returns the result of each of the test conducted by
6134 * the driver.
6135 * Description:
20346722 6136 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6137 * argument 'data' appropriately.
6138 * Return value:
6139 * 0 on success.
6140 */
6141
1ee6dd77 6142static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6143{
1ee6dd77 6144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6145 u64 val64;
6146
6147 val64 = readq(&bar0->adapter_status);
c92ca04b 6148 if(!(LINK_IS_UP(val64)))
1da177e4 6149 *data = 1;
c92ca04b
AR		 6150 else
6151 *data = 0;
1da177e4 6152
b41477f3 6153 return *data;
1da177e4
LT		 6154}
6155
6156/**
20346722 6157 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6158 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6159 * s2io_nic structure.
20346722 6160 * @data - variable that returns the result of each of the test
1da177e4
LT		 6161 * conducted by the driver.
6162 * Description:
20346722 6163 * This is one of the offline test that tests the read and write
1da177e4
LT		 6164 * access to the RldRam chip on the NIC.
6165 * Return value:
6166 * 0 on success.
6167 */
6168
1ee6dd77 6169static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 6170{
1ee6dd77 6171 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6172 u64 val64;
ad4ebed0 6173 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6174
6175 val64 = readq(&bar0->adapter_control);
6176 val64 &= ~ADAPTER_ECC_EN;
6177 writeq(val64, &bar0->adapter_control);
6178
6179 val64 = readq(&bar0->mc_rldram_test_ctrl);
6180 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6181 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6182
6183 val64 = readq(&bar0->mc_rldram_mrs);
6184 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6185 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6186
6187 val64 |= MC_RLDRAM_MRS_ENABLE;
6188 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6189
6190 while (iteration < 2) {
6191 val64 = 0x55555555aaaa0000ULL;
6192 if (iteration == 1) {
6193 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6194 }
6195 writeq(val64, &bar0->mc_rldram_test_d0);
6196
6197 val64 = 0xaaaa5a5555550000ULL;
6198 if (iteration == 1) {
6199 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6200 }
6201 writeq(val64, &bar0->mc_rldram_test_d1);
6202
6203 val64 = 0x55aaaaaaaa5a0000ULL;
6204 if (iteration == 1) {
6205 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6206 }
6207 writeq(val64, &bar0->mc_rldram_test_d2);
6208
ad4ebed0 6209 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6210 writeq(val64, &bar0->mc_rldram_test_add);
6211
ad4ebed0 6212 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6213 MC_RLDRAM_TEST_GO;
6214 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6215
6216 for (cnt = 0; cnt < 5; cnt++) {
6217 val64 = readq(&bar0->mc_rldram_test_ctrl);
6218 if (val64 & MC_RLDRAM_TEST_DONE)
6219 break;
6220 msleep(200);
6221 }
6222
6223 if (cnt == 5)
6224 break;
6225
ad4ebed0 6226 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6227 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6228
6229 for (cnt = 0; cnt < 5; cnt++) {
6230 val64 = readq(&bar0->mc_rldram_test_ctrl);
6231 if (val64 & MC_RLDRAM_TEST_DONE)
6232 break;
6233 msleep(500);
6234 }
6235
6236 if (cnt == 5)
6237 break;
6238
6239 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6240 if (!(val64 & MC_RLDRAM_TEST_PASS))
6241 test_fail = 1;
1da177e4
LT		 6242
6243 iteration++;
6244 }
6245
ad4ebed0 6246 *data = test_fail;
1da177e4 6247
ad4ebed0 6248 /* Bring the adapter out of test mode */
6249 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6250
6251 return test_fail;
1da177e4
LT		 6252}
6253
6254/**
6255 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6256 * @sp : private member of the device structure, which is a pointer to the
6257 * s2io_nic structure.
6258 * @ethtest : pointer to a ethtool command specific structure that will be
6259 * returned to the user.
20346722 6260 * @data : variable that returns the result of each of the test
1da177e4
LT		 6261 * conducted by the driver.
6262 * Description:
6263 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6264 * the health of the card.
6265 * Return value:
6266 * void
6267 */
6268
6269static void s2io_ethtool_test(struct net_device *dev,
6270 struct ethtool_test *ethtest,
6271 uint64_t * data)
6272{
4cf1653a 6273 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6274 int orig_state = netif_running(sp->dev);
6275
6276 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6277 /* Offline Tests. */
20346722 6278 if (orig_state)
1da177e4 6279 s2io_close(sp->dev);
1da177e4
LT		 6280
6281 if (s2io_register_test(sp, &data[0]))
6282 ethtest->flags |= ETH_TEST_FL_FAILED;
6283
6284 s2io_reset(sp);
1da177e4
LT		 6285
6286 if (s2io_rldram_test(sp, &data[3]))
6287 ethtest->flags |= ETH_TEST_FL_FAILED;
6288
6289 s2io_reset(sp);
1da177e4
LT		 6290
6291 if (s2io_eeprom_test(sp, &data[1]))
6292 ethtest->flags |= ETH_TEST_FL_FAILED;
6293
6294 if (s2io_bist_test(sp, &data[4]))
6295 ethtest->flags |= ETH_TEST_FL_FAILED;
6296
6297 if (orig_state)
6298 s2io_open(sp->dev);
6299
6300 data[2] = 0;
6301 } else {
6302 /* Online Tests. */
6303 if (!orig_state) {
6304 DBG_PRINT(ERR_DBG,
6305 "%s: is not up, cannot run test\n",
6306 dev->name);
6307 data[0] = -1;
6308 data[1] = -1;
6309 data[2] = -1;
6310 data[3] = -1;
6311 data[4] = -1;
6312 }
6313
6314 if (s2io_link_test(sp, &data[2]))
6315 ethtest->flags |= ETH_TEST_FL_FAILED;
6316
6317 data[0] = 0;
6318 data[1] = 0;
6319 data[3] = 0;
6320 data[4] = 0;
6321 }
6322}
6323
6324static void s2io_get_ethtool_stats(struct net_device *dev,
6325 struct ethtool_stats *estats,
6326 u64 * tmp_stats)
6327{
8116f3cf 6328 int i = 0, k;
4cf1653a 6329 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 6330 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6331
7ba013ac 6332 s2io_updt_stats(sp);
541ae68f 6333 tmp_stats[i++] =
6334 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6335 le32_to_cpu(stat_info->tmac_frms);
6336 tmp_stats[i++] =
6337 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6338 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6339 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f 6340 tmp_stats[i++] =
6341 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6342 le32_to_cpu(stat_info->tmac_mcst_frms);
6343 tmp_stats[i++] =
6344 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6345 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6346 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6347 tmp_stats[i++] =
6348 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6349 le32_to_cpu(stat_info->tmac_ttl_octets);
6350 tmp_stats[i++] =
6351 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6352 le32_to_cpu(stat_info->tmac_ucst_frms);
6353 tmp_stats[i++] =
6354 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6355 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f 6356 tmp_stats[i++] =
6357 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6358 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6359 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6360 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f 6361 tmp_stats[i++] =
6362 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6363 le32_to_cpu(stat_info->tmac_vld_ip);
6364 tmp_stats[i++] =
6365 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6366 le32_to_cpu(stat_info->tmac_drop_ip);
6367 tmp_stats[i++] =
6368 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6369 le32_to_cpu(stat_info->tmac_icmp);
6370 tmp_stats[i++] =
6371 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6372 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6373 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f 6374 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6375 le32_to_cpu(stat_info->tmac_udp);
6376 tmp_stats[i++] =
6377 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6378 le32_to_cpu(stat_info->rmac_vld_frms);
6379 tmp_stats[i++] =
6380 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6381 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6382 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6383 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f 6384 tmp_stats[i++] =
6385 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6386 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6387 tmp_stats[i++] =
6388 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6389 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6390 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6391 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6392 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6393 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6394 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6395 tmp_stats[i++] =
6396 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6397 le32_to_cpu(stat_info->rmac_ttl_octets);
6398 tmp_stats[i++] =
6399 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6400 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6401 tmp_stats[i++] =
6402 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6403 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f 6404 tmp_stats[i++] =
6405 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6406 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6407 tmp_stats[i++] =
6408 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6409 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6410 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6411 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f 6412 tmp_stats[i++] =
6413 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6414 le32_to_cpu(stat_info->rmac_usized_frms);
6415 tmp_stats[i++] =
6416 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6417 le32_to_cpu(stat_info->rmac_osized_frms);
6418 tmp_stats[i++] =
6419 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6420 le32_to_cpu(stat_info->rmac_frag_frms);
6421 tmp_stats[i++] =
6422 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6423 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6424 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6425 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6426 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6427 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6428 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6429 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6430 tmp_stats[i++] =
6431 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6432 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6433 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6434 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6435 tmp_stats[i++] =
6436 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6437 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6438 tmp_stats[i++] =
6439 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6440 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6441 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6442 tmp_stats[i++] =
6443 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f 6444 le32_to_cpu(stat_info->rmac_udp);
6445 tmp_stats[i++] =
6446 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6447 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6448 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6449 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6450 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6451 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6452 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6453 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6454 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6455 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6456 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6457 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6458 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6459 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6460 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6461 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6462 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6463 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6464 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f 6465 tmp_stats[i++] =
6466 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6467 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6468 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6469 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f 6470 tmp_stats[i++] =
6471 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6472 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6473 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6474 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6481 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6482 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6483 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6484 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6485 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6486 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6487 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6488 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6489 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6490 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6491 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6492
6493 /* Enhanced statistics exist only for Hercules */
6494 if(sp->device_type == XFRAME_II_DEVICE) {
6495 tmp_stats[i++] =
6496 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6497 tmp_stats[i++] =
6498 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6499 tmp_stats[i++] =
6500 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6501 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6502 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6503 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6504 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6505 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6506 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6507 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6508 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6509 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6510 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6511 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6512 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6513 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6514 }
6515
7ba013ac 6516 tmp_stats[i++] = 0;
6517 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6518 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6519 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6520 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6521 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6522 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6523 for (k = 0; k < MAX_RX_RINGS; k++)
6524 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6525 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6526 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6527 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6528 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6529 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6530 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6531 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6532 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6533 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6534 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6535 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6536 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6537 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6538 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6539 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6540 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6541 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6542 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6543 int count = 0;
6aa20a22 6544 /*
bd1034f0
AR		 6545 * Since 64-bit divide does not work on all platforms,
6546 * do repeated subtraction.
6547 */
6548 while (tmp >= stat_info->sw_stat.num_aggregations) {
6549 tmp -= stat_info->sw_stat.num_aggregations;
6550 count++;
6551 }
6552 tmp_stats[i++] = count;
fe931395 6553 }
bd1034f0
AR		 6554 else
6555 tmp_stats[i++] = 0;
c53d4945 6556 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6557 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6558 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6559 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6560 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6561 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6562 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6563 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6564 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6565
6566 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6567 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6568 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6569 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6570 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6571
6572 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6573 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6574 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6575 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6576 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6577 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6578 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6579 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6580 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6581 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6582 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6583 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6584 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6585 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6586 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6587 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6588 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6589 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6590 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6591 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6592 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6593 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6594 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6595 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6596 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6597 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6598}
6599
ac1f60db 6600static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6601{
6602 return (XENA_REG_SPACE);
6603}
6604
6605
ac1f60db 6606static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6607{
4cf1653a 6608 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6609
6610 return (sp->rx_csum);
6611}
ac1f60db
AB		 6612
6613static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6614{
4cf1653a 6615 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6616
6617 if (data)
6618 sp->rx_csum = 1;
6619 else
6620 sp->rx_csum = 0;
6621
6622 return 0;
6623}
ac1f60db
AB		 6624
6625static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6626{
6627 return (XENA_EEPROM_SPACE);
6628}
6629
b9f2c044 6630static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6631{
4cf1653a 6632 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6633
6634 switch (sset) {
6635 case ETH_SS_TEST:
6636 return S2IO_TEST_LEN;
6637 case ETH_SS_STATS:
6638 switch(sp->device_type) {
6639 case XFRAME_I_DEVICE:
6640 return XFRAME_I_STAT_LEN;
6641 case XFRAME_II_DEVICE:
6642 return XFRAME_II_STAT_LEN;
6643 default:
6644 return 0;
6645 }
6646 default:
6647 return -EOPNOTSUPP;
6648 }
1da177e4 6649}
ac1f60db
AB		 6650
6651static void s2io_ethtool_get_strings(struct net_device *dev,
6652 u32 stringset, u8 * data)
1da177e4 6653{
fa1f0cb3 6654 int stat_size = 0;
4cf1653a 6655 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6656
1da177e4
LT		 6657 switch (stringset) {
6658 case ETH_SS_TEST:
6659 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6660 break;
6661 case ETH_SS_STATS:
fa1f0cb3
SS		 6662 stat_size = sizeof(ethtool_xena_stats_keys);
6663 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6664 if(sp->device_type == XFRAME_II_DEVICE) {
6665 memcpy(data + stat_size,
6666 &ethtool_enhanced_stats_keys,
6667 sizeof(ethtool_enhanced_stats_keys));
6668 stat_size += sizeof(ethtool_enhanced_stats_keys);
6669 }
6670
6671 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6672 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6673 }
6674}
1da177e4 6675
ac1f60db 6676static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6677{
6678 if (data)
6679 dev->features |= NETIF_F_IP_CSUM;
6680 else
6681 dev->features &= ~NETIF_F_IP_CSUM;
6682
6683 return 0;
6684}
6685
75c30b13
AR		 6686static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6687{
6688 return (dev->features & NETIF_F_TSO) != 0;
6689}
6690static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6691{
6692 if (data)
6693 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6694 else
6695 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6696
6697 return 0;
6698}
1da177e4 6699
7282d491 6700static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6701 .get_settings = s2io_ethtool_gset,
6702 .set_settings = s2io_ethtool_sset,
6703 .get_drvinfo = s2io_ethtool_gdrvinfo,
6704 .get_regs_len = s2io_ethtool_get_regs_len,
6705 .get_regs = s2io_ethtool_gregs,
6706 .get_link = ethtool_op_get_link,
6707 .get_eeprom_len = s2io_get_eeprom_len,
6708 .get_eeprom = s2io_ethtool_geeprom,
6709 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6710 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6711 .get_pauseparam = s2io_ethtool_getpause_data,
6712 .set_pauseparam = s2io_ethtool_setpause_data,
6713 .get_rx_csum = s2io_ethtool_get_rx_csum,
6714 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6715 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6716 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6717 .get_tso = s2io_ethtool_op_get_tso,
6718 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6719 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6720 .self_test = s2io_ethtool_test,
6721 .get_strings = s2io_ethtool_get_strings,
6722 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6723 .get_ethtool_stats = s2io_get_ethtool_stats,
6724 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6725};
6726
6727/**
20346722 6728 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6729 * @dev : Device pointer.
6730 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6731 * a proprietary structure used to pass information to the driver.
6732 * @cmd : This is used to distinguish between the different commands that
6733 * can be passed to the IOCTL functions.
6734 * Description:
20346722 6735 * Currently there are no special functionality supported in IOCTL, hence
6736 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6737 */
6738
ac1f60db 6739static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6740{
6741 return -EOPNOTSUPP;
6742}
6743
6744/**
6745 * s2io_change_mtu - entry point to change MTU size for the device.
6746 * @dev : device pointer.
6747 * @new_mtu : the new MTU size for the device.
6748 * Description: A driver entry point to change MTU size for the device.
6749 * Before changing the MTU the device must be stopped.
6750 * Return value:
6751 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6752 * file on failure.
6753 */
6754
ac1f60db 6755static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6756{
4cf1653a 6757 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6758 int ret = 0;
1da177e4
LT		 6759
6760 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6761 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6762 dev->name);
6763 return -EPERM;
6764 }
6765
1da177e4 6766 dev->mtu = new_mtu;
d8892c6e 6767 if (netif_running(dev)) {
3a3d5756 6768 s2io_stop_all_tx_queue(sp);
e6a8fee2 6769 s2io_card_down(sp);
9f74ffde
SH		 6770 ret = s2io_card_up(sp);
6771 if (ret) {
d8892c6e 6772 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6773 __func__);
9f74ffde 6774 return ret;
d8892c6e 6775 }
3a3d5756 6776 s2io_wake_all_tx_queue(sp);
d8892c6e 6777 } else { /* Device is down */
1ee6dd77 6778 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6779 u64 val64 = new_mtu;
6780
6781 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6782 }
1da177e4 6783
9f74ffde 6784 return ret;
1da177e4
LT		 6785}
6786
1da177e4
LT		 6787/**
6788 * s2io_set_link - Set the LInk status
6789 * @data: long pointer to device private structue
6790 * Description: Sets the link status for the adapter
6791 */
6792
c4028958 6793static void s2io_set_link(struct work_struct *work)
1da177e4 6794{
1ee6dd77 6795 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6796 struct net_device *dev = nic->dev;
1ee6dd77 6797 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6798 register u64 val64;
6799 u16 subid;
6800
22747d6b
FR		 6801 rtnl_lock();
6802
6803 if (!netif_running(dev))
6804 goto out_unlock;
6805
92b84437 6806 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6807 /* The card is being reset, no point doing anything */
22747d6b 6808 goto out_unlock;
1da177e4
LT		 6809 }
6810
6811 subid = nic->pdev->subsystem_device;
a371a07d 6812 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6813 /*
6814 * Allow a small delay for the NICs self initiated
6815 * cleanup to complete.
6816 */
6817 msleep(100);
6818 }
1da177e4
LT		 6819
6820 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6821 if (LINK_IS_UP(val64)) {
6822 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6823 if (verify_xena_quiescence(nic)) {
6824 val64 = readq(&bar0->adapter_control);
6825 val64 |= ADAPTER_CNTL_EN;
1da177e4 6826 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6827 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6828 nic->device_type, subid)) {
6829 val64 = readq(&bar0->gpio_control);
6830 val64 |= GPIO_CTRL_GPIO_0;
6831 writeq(val64, &bar0->gpio_control);
6832 val64 = readq(&bar0->gpio_control);
6833 } else {
6834 val64 |= ADAPTER_LED_ON;
6835 writeq(val64, &bar0->adapter_control);
a371a07d 6836 }
f957bcf0 6837 nic->device_enabled_once = true;
19a60522
SS		 6838 } else {
6839 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6840 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6841 s2io_stop_all_tx_queue(nic);
1da177e4 6842 }
19a60522 6843 }
92c48799
SS		 6844 val64 = readq(&bar0->adapter_control);
6845 val64 |= ADAPTER_LED_ON;
6846 writeq(val64, &bar0->adapter_control);
6847 s2io_link(nic, LINK_UP);
19a60522
SS		 6848 } else {
6849 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6850 subid)) {
6851 val64 = readq(&bar0->gpio_control);
6852 val64 &= ~GPIO_CTRL_GPIO_0;
6853 writeq(val64, &bar0->gpio_control);
6854 val64 = readq(&bar0->gpio_control);
1da177e4 6855 }
92c48799
SS		 6856 /* turn off LED */
6857 val64 = readq(&bar0->adapter_control);
6858 val64 = val64 &(~ADAPTER_LED_ON);
6859 writeq(val64, &bar0->adapter_control);
19a60522 6860 s2io_link(nic, LINK_DOWN);
1da177e4 6861 }
92b84437 6862 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6863
6864out_unlock:
d8d70caf 6865 rtnl_unlock();
1da177e4
LT		 6866}
6867
1ee6dd77
RB		 6868static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6869 struct buffAdd *ba,
6870 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6871 u64 *temp2, int size)
5d3213cc
AR		 6872{
6873 struct net_device *dev = sp->dev;
491abf25 6874 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6875
6876 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6877 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6878 /* allocate skb */
6879 if (*skb) {
6880 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6881 /*
6882 * As Rx frame are not going to be processed,
6883 * using same mapped address for the Rxd
6884 * buffer pointer
6885 */
6d517a27 6886 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6887 } else {
6888 *skb = dev_alloc_skb(size);
6889 if (!(*skb)) {
0c61ed5f 6890 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6891 DBG_PRINT(INFO_DBG, "memory to allocate ");
6892 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6893 sp->mac_control.stats_info->sw_stat. \
6894 mem_alloc_fail_cnt++;
5d3213cc
AR		 6895 return -ENOMEM ;
6896 }
8a4bdbaa 6897 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6898 += (*skb)->truesize;
5d3213cc
AR		 6899 /* storing the mapped addr in a temp variable
6900 * such it will be used for next rxd whose
6901 * Host Control is NULL
6902 */
6d517a27 6903 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6904 pci_map_single( sp->pdev, (*skb)->data,
6905 size - NET_IP_ALIGN,
6906 PCI_DMA_FROMDEVICE);
8d8bb39b 6907 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6908 goto memalloc_failed;
5d3213cc
AR		 6909 rxdp->Host_Control = (unsigned long) (*skb);
6910 }
6911 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6912 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6913 /* Two buffer Mode */
6914 if (*skb) {
6d517a27
VP		 6915 rxdp3->Buffer2_ptr = *temp2;
6916 rxdp3->Buffer0_ptr = *temp0;
6917 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6918 } else {
6919 *skb = dev_alloc_skb(size);
2ceaac75 6920 if (!(*skb)) {
c53d4945
SH		 6921 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6922 DBG_PRINT(INFO_DBG, "memory to allocate ");
6923 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6924 sp->mac_control.stats_info->sw_stat. \
6925 mem_alloc_fail_cnt++;
2ceaac75
DR		 6926 return -ENOMEM;
6927 }
8a4bdbaa 6928 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6929 += (*skb)->truesize;
6d517a27 6930 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6931 pci_map_single(sp->pdev, (*skb)->data,
6932 dev->mtu + 4,
6933 PCI_DMA_FROMDEVICE);
8d8bb39b 6934 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6935 goto memalloc_failed;
6d517a27 6936 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6937 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6938 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6939 if (pci_dma_mapping_error(sp->pdev,
6940 rxdp3->Buffer0_ptr)) {
491abf25 6941 pci_unmap_single (sp->pdev,
3e847423 6942 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6943 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6944 goto memalloc_failed;
6945 }
5d3213cc
AR		 6946 rxdp->Host_Control = (unsigned long) (*skb);
6947
6948 /* Buffer-1 will be dummy buffer not used */
6d517a27 6949 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6950 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6951 PCI_DMA_FROMDEVICE);
8d8bb39b
FT		 6952 if (pci_dma_mapping_error(sp->pdev,
6953 rxdp3->Buffer1_ptr)) {
491abf25 6954 pci_unmap_single (sp->pdev,
3e847423
AV		 6955 (dma_addr_t)rxdp3->Buffer0_ptr,
6956 BUF0_LEN, PCI_DMA_FROMDEVICE);
6957 pci_unmap_single (sp->pdev,
6958 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6959 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6960 goto memalloc_failed;
6961 }
5d3213cc
AR		 6962 }
6963 }
6964 return 0;
491abf25
VP		 6965 memalloc_failed:
6966 stats->pci_map_fail_cnt++;
6967 stats->mem_freed += (*skb)->truesize;
6968 dev_kfree_skb(*skb);
6969 return -ENOMEM;
5d3213cc 6970}
491abf25 6971
1ee6dd77
RB		 6972static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6973 int size)
5d3213cc
AR		 6974{
6975 struct net_device *dev = sp->dev;
6976 if (sp->rxd_mode == RXD_MODE_1) {
6977 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6978 } else if (sp->rxd_mode == RXD_MODE_3B) {
6979 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6980 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6981 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6982 }
6983}
6984
1ee6dd77 6985static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6986{
6987 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6988 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6989 struct config_param *config = &sp->config;
6990 struct net_device *dev = sp->dev;
1ee6dd77 6991 struct RxD_t *rxdp = NULL;
5d3213cc 6992 struct sk_buff *skb = NULL;
1ee6dd77 6993 struct buffAdd *ba = NULL;
5d3213cc
AR		 6994 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6995
6996 /* Calculate the size based on ring mode */
6997 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6998 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6999 if (sp->rxd_mode == RXD_MODE_1)
7000 size += NET_IP_ALIGN;
7001 else if (sp->rxd_mode == RXD_MODE_3B)
7002 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7003
7004 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7005 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7006 struct ring_info *ring = &mac_control->rings[i];
7007
7008 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] +1);
5d3213cc
AR		 7009
7010 for (j = 0; j < blk_cnt; j++) {
7011 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
13d866a9 7012 rxdp = ring-> rx_blocks[j].rxds[k].virt_addr;
6d517a27 7013 if(sp->rxd_mode == RXD_MODE_3B)
13d866a9 7014 ba = &ring->ba[j][k];
ac1f90d6 7015 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 7016 &skb,(u64 *)&temp0_64,
7017 (u64 *)&temp1_64,
ac1f90d6 7018 (u64 *)&temp2_64,
20cbe73c 7019 size) == -ENOMEM) {
ac1f90d6
SS		 7020 return 0;
7021 }
5d3213cc
AR		 7022
7023 set_rxd_buffer_size(sp, rxdp, size);
7024 wmb();
7025 /* flip the Ownership bit to Hardware */
7026 rxdp->Control_1 |= RXD_OWN_XENA;
7027 }
7028 }
7029 }
7030 return 0;
7031
7032}
7033
1ee6dd77 7034static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 7035{
e6a8fee2 7036 int ret = 0;
c92ca04b 7037 struct net_device *dev = sp->dev;
e6a8fee2 7038 int err = 0;
1da177e4 7039
eaae7f72 7040 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7041 ret = s2io_enable_msi_x(sp);
7042 if (ret) {
7043 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7044 sp->config.intr_type = INTA;
20346722 7045 }
1da177e4 7046
1ee6dd77 7047 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 7048 store_xmsi_data(sp);
c92ca04b 7049
e6a8fee2 7050 /* After proper initialization of H/W, register ISR */
eaae7f72 7051 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7052 int i, msix_rx_cnt = 0;
7053
f61e0a35
SH		 7054 for (i = 0; i < sp->num_entries; i++) {
7055 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7056 if (sp->s2io_entries[i].type ==
ac731ab6
SH		 7057 MSIX_RING_TYPE) {
7058 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7059 dev->name, i);
7060 err = request_irq(sp->entries[i].vector,
7061 s2io_msix_ring_handle, 0,
7062 sp->desc[i],
7063 sp->s2io_entries[i].arg);
7064 } else if (sp->s2io_entries[i].type ==
7065 MSIX_ALARM_TYPE) {
7066 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
e6a8fee2 7067 dev->name, i);
ac731ab6
SH		 7068 err = request_irq(sp->entries[i].vector,
7069 s2io_msix_fifo_handle, 0,
7070 sp->desc[i],
7071 sp->s2io_entries[i].arg);
7072
fb6a825b 7073 }
ac731ab6
SH		 7074 /* if either data or addr is zero print it. */
7075 if (!(sp->msix_info[i].addr &&
fb6a825b 7076 sp->msix_info[i].data)) {
ac731ab6
SH		 7077 DBG_PRINT(ERR_DBG,
7078 "%s @Addr:0x%llx Data:0x%llx\n",
7079 sp->desc[i],
fb6a825b
SS		 7080 (unsigned long long)
7081 sp->msix_info[i].addr,
3459feb8 7082 (unsigned long long)
ac731ab6
SH		 7083 ntohl(sp->msix_info[i].data));
7084 } else
fb6a825b 7085 msix_rx_cnt++;
ac731ab6
SH		 7086 if (err) {
7087 remove_msix_isr(sp);
7088
7089 DBG_PRINT(ERR_DBG,
7090 "%s:MSI-X-%d registration "
7091 "failed\n", dev->name, i);
7092
7093 DBG_PRINT(ERR_DBG,
7094 "%s: Defaulting to INTA\n",
7095 dev->name);
7096 sp->config.intr_type = INTA;
7097 break;
fb6a825b 7098 }
ac731ab6
SH		 7099 sp->s2io_entries[i].in_use =
7100 MSIX_REGISTERED_SUCCESS;
c92ca04b 7101 }
e6a8fee2 7102 }
18b2b7bd 7103 if (!err) {
18b2b7bd 7104 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
ac731ab6
SH		 7105 --msix_rx_cnt);
7106 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
7107 " through alarm vector\n");
18b2b7bd 7108 }
e6a8fee2 7109 }
eaae7f72 7110 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 7111 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
7112 sp->name, dev);
7113 if (err) {
7114 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7115 dev->name);
7116 return -1;
7117 }
7118 }
7119 return 0;
7120}
1ee6dd77 7121static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 7122{
18b2b7bd
SH		 7123 if (sp->config.intr_type == MSI_X)
7124 remove_msix_isr(sp);
7125 else
7126 remove_inta_isr(sp);
e6a8fee2
AR		 7127}
7128
d796fdb7 7129static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 7130{
7131 int cnt = 0;
1ee6dd77 7132 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7133 register u64 val64 = 0;
5f490c96
SH		 7134 struct config_param *config;
7135 config = &sp->config;
e6a8fee2 7136
9f74ffde
SH		 7137 if (!is_s2io_card_up(sp))
7138 return;
7139
e6a8fee2
AR		 7140 del_timer_sync(&sp->alarm_timer);
7141 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 7142 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7143 msleep(50);
7144 }
92b84437 7145 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7146
5f490c96 7147 /* Disable napi */
f61e0a35
SH		 7148 if (sp->config.napi) {
7149 int off = 0;
7150 if (config->intr_type == MSI_X) {
7151 for (; off < sp->config.rx_ring_num; off++)
7152 napi_disable(&sp->mac_control.rings[off].napi);
7153 }
7154 else
7155 napi_disable(&sp->napi);
7156 }
5f490c96 7157
e6a8fee2 7158 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7159 if (do_io)
7160 stop_nic(sp);
e6a8fee2
AR		 7161
7162 s2io_rem_isr(sp);
1da177e4 7163
01e16faa
SH		 7164 /* stop the tx queue, indicate link down */
7165 s2io_link(sp, LINK_DOWN);
7166
1da177e4 7167 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7168 while(do_io) {
5d3213cc
AR		 7169 /* As per the HW requirement we need to replenish the
7170 * receive buffer to avoid the ring bump. Since there is
7171 * no intention of processing the Rx frame at this pointwe are
7172 * just settting the ownership bit of rxd in Each Rx
7173 * ring to HW and set the appropriate buffer size
7174 * based on the ring mode
7175 */
7176 rxd_owner_bit_reset(sp);
7177
1da177e4 7178 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7179 if (verify_xena_quiescence(sp)) {
7180 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7181 break;
7182 }
7183
7184 msleep(50);
7185 cnt++;
7186 if (cnt == 10) {
7187 DBG_PRINT(ERR_DBG,
7188 "s2io_close:Device not Quiescent ");
7189 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7190 (unsigned long long) val64);
7191 break;
7192 }
d796fdb7
LV		 7193 }
7194 if (do_io)
7195 s2io_reset(sp);
1da177e4 7196
7ba013ac 7197 /* Free all Tx buffers */
1da177e4 7198 free_tx_buffers(sp);
7ba013ac 7199
7200 /* Free all Rx buffers */
1da177e4
LT		 7201 free_rx_buffers(sp);
7202
92b84437 7203 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7204}
7205
d796fdb7
LV		 7206static void s2io_card_down(struct s2io_nic * sp)
7207{
7208 do_s2io_card_down(sp, 1);
7209}
7210
1ee6dd77 7211static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7212{
cc6e7c44 7213 int i, ret = 0;
1ee6dd77 7214 struct mac_info *mac_control;
1da177e4
LT		 7215 struct config_param *config;
7216 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7217 u16 interruptible;
1da177e4
LT		 7218
7219 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7220 ret = init_nic(sp);
7221 if (ret != 0) {
1da177e4
LT		 7222 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7223 dev->name);
9f74ffde
SH		 7224 if (ret != -EIO)
7225 s2io_reset(sp);
7226 return ret;
1da177e4
LT		 7227 }
7228
20346722 7229 /*
7230 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7231 * Rx ring and initializing buffers into 30 Rx blocks
7232 */
7233 mac_control = &sp->mac_control;
7234 config = &sp->config;
7235
7236 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7237 struct ring_info *ring = &mac_control->rings[i];
7238
7239 ring->mtu = dev->mtu;
7240 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7241 if (ret) {
1da177e4
LT		 7242 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7243 dev->name);
7244 s2io_reset(sp);
7245 free_rx_buffers(sp);
7246 return -ENOMEM;
7247 }
7248 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7249 ring->rx_bufs_left);
1da177e4 7250 }
5f490c96
SH		 7251
7252 /* Initialise napi */
f61e0a35 7253 if (config->napi) {
f61e0a35
SH		 7254 if (config->intr_type == MSI_X) {
7255 for (i = 0; i < sp->config.rx_ring_num; i++)
7256 napi_enable(&sp->mac_control.rings[i].napi);
7257 } else {
7258 napi_enable(&sp->napi);
7259 }
7260 }
5f490c96 7261
19a60522
SS		 7262 /* Maintain the state prior to the open */
7263 if (sp->promisc_flg)
7264 sp->promisc_flg = 0;
7265 if (sp->m_cast_flg) {
7266 sp->m_cast_flg = 0;
7267 sp->all_multi_pos= 0;
7268 }
1da177e4
LT		 7269
7270 /* Setting its receive mode */
7271 s2io_set_multicast(dev);
7272
7d3d0439 7273 if (sp->lro) {
b41477f3 7274 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7275 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7276 /* Check if we can use(if specified) user provided value */
7277 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7278 sp->lro_max_aggr_per_sess = lro_max_pkts;
7279 }
7280
1da177e4
LT		 7281 /* Enable Rx Traffic and interrupts on the NIC */
7282 if (start_nic(sp)) {
7283 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7284 s2io_reset(sp);
e6a8fee2
AR		 7285 free_rx_buffers(sp);
7286 return -ENODEV;
7287 }
7288
7289 /* Add interrupt service routine */
7290 if (s2io_add_isr(sp) != 0) {
eaae7f72 7291 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7292 s2io_rem_isr(sp);
7293 s2io_reset(sp);
1da177e4
LT		 7294 free_rx_buffers(sp);
7295 return -ENODEV;
7296 }
7297
25fff88e 7298 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7299
01e16faa
SH		 7300 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7301
e6a8fee2 7302 /* Enable select interrupts */
9caab458 7303 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7304 if (sp->config.intr_type != INTA) {
7305 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7306 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7307 } else {
e6a8fee2 7308 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7309 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7310 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7311 }
7312
1da177e4
LT		 7313 return 0;
7314}
7315
20346722 7316/**
1da177e4
LT		 7317 * s2io_restart_nic - Resets the NIC.
7318 * @data : long pointer to the device private structure
7319 * Description:
7320 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7321 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7322 * the run time of the watch dog routine which is run holding a
7323 * spin lock.
7324 */
7325
c4028958 7326static void s2io_restart_nic(struct work_struct *work)
1da177e4 7327{
1ee6dd77 7328 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7329 struct net_device *dev = sp->dev;
1da177e4 7330
22747d6b
FR		 7331 rtnl_lock();
7332
7333 if (!netif_running(dev))
7334 goto out_unlock;
7335
e6a8fee2 7336 s2io_card_down(sp);
1da177e4
LT		 7337 if (s2io_card_up(sp)) {
7338 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7339 dev->name);
7340 }
3a3d5756 7341 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7342 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7343 dev->name);
22747d6b
FR		 7344out_unlock:
7345 rtnl_unlock();
1da177e4
LT		 7346}
7347
20346722 7348/**
7349 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7350 * @dev : Pointer to net device structure
7351 * Description:
7352 * This function is triggered if the Tx Queue is stopped
7353 * for a pre-defined amount of time when the Interface is still up.
7354 * If the Interface is jammed in such a situation, the hardware is
7355 * reset (by s2io_close) and restarted again (by s2io_open) to
7356 * overcome any problem that might have been caused in the hardware.
7357 * Return value:
7358 * void
7359 */
7360
7361static void s2io_tx_watchdog(struct net_device *dev)
7362{
4cf1653a 7363 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 7364
7365 if (netif_carrier_ok(dev)) {
c53d4945 7366 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7367 schedule_work(&sp->rst_timer_task);
bd1034f0 7368 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7369 }
7370}
7371
7372/**
7373 * rx_osm_handler - To perform some OS related operations on SKB.
7374 * @sp: private member of the device structure,pointer to s2io_nic structure.
7375 * @skb : the socket buffer pointer.
7376 * @len : length of the packet
7377 * @cksum : FCS checksum of the frame.
7378 * @ring_no : the ring from which this RxD was extracted.
20346722 7379 * Description:
b41477f3 7380 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7381 * some OS related operations on the SKB before passing it to the upper
7382 * layers. It mainly checks if the checksum is OK, if so adds it to the
7383 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7384 * to the upper layer. If the checksum is wrong, it increments the Rx
7385 * packet error count, frees the SKB and returns error.
7386 * Return value:
7387 * SUCCESS on success and -1 on failure.
7388 */
1ee6dd77 7389static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7390{
1ee6dd77 7391 struct s2io_nic *sp = ring_data->nic;
0425b46a 7392 struct net_device *dev = (struct net_device *) ring_data->dev;
20346722 7393 struct sk_buff *skb = (struct sk_buff *)
7394 ((unsigned long) rxdp->Host_Control);
7395 int ring_no = ring_data->ring_no;
1da177e4 7396 u16 l3_csum, l4_csum;
863c11a9 7397 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7398 struct lro *uninitialized_var(lro);
f9046eb3 7399 u8 err_mask;
da6971d8 7400
20346722 7401 skb->dev = dev;
c92ca04b 7402
863c11a9 7403 if (err) {
bd1034f0
AR		 7404 /* Check for parity error */
7405 if (err & 0x1) {
7406 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7407 }
f9046eb3
OH		 7408 err_mask = err >> 48;
7409 switch(err_mask) {
491976b2
SH		 7410 case 1:
7411 sp->mac_control.stats_info->sw_stat.
7412 rx_parity_err_cnt++;
7413 break;
7414
7415 case 2:
7416 sp->mac_control.stats_info->sw_stat.
7417 rx_abort_cnt++;
7418 break;
7419
7420 case 3:
7421 sp->mac_control.stats_info->sw_stat.
7422 rx_parity_abort_cnt++;
7423 break;
7424
7425 case 4:
7426 sp->mac_control.stats_info->sw_stat.
7427 rx_rda_fail_cnt++;
7428 break;
7429
7430 case 5:
7431 sp->mac_control.stats_info->sw_stat.
7432 rx_unkn_prot_cnt++;
7433 break;
7434
7435 case 6:
7436 sp->mac_control.stats_info->sw_stat.
7437 rx_fcs_err_cnt++;
7438 break;
bd1034f0 7439
491976b2
SH		 7440 case 7:
7441 sp->mac_control.stats_info->sw_stat.
7442 rx_buf_size_err_cnt++;
7443 break;
7444
7445 case 8:
7446 sp->mac_control.stats_info->sw_stat.
7447 rx_rxd_corrupt_cnt++;
7448 break;
7449
7450 case 15:
7451 sp->mac_control.stats_info->sw_stat.
7452 rx_unkn_err_cnt++;
7453 break;
7454 }
863c11a9
AR		 7455 /*
7456 * Drop the packet if bad transfer code. Exception being
7457 * 0x5, which could be due to unsupported IPv6 extension header.
7458 * In this case, we let stack handle the packet.
7459 * Note that in this case, since checksum will be incorrect,
7460 * stack will validate the same.
7461 */
f9046eb3
OH		 7462 if (err_mask != 0x5) {
7463 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7464 dev->name, err_mask);
dc56e634 7465 dev->stats.rx_crc_errors++;
8a4bdbaa 7466 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7467 += skb->truesize;
863c11a9 7468 dev_kfree_skb(skb);
0425b46a 7469 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7470 rxdp->Host_Control = 0;
7471 return 0;
7472 }
20346722 7473 }
1da177e4 7474
20346722 7475 /* Updating statistics */
0425b46a 7476 ring_data->rx_packets++;
20346722 7477 rxdp->Host_Control = 0;
da6971d8
AR		 7478 if (sp->rxd_mode == RXD_MODE_1) {
7479 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7480
0425b46a 7481 ring_data->rx_bytes += len;
da6971d8
AR		 7482 skb_put(skb, len);
7483
6d517a27 7484 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7485 int get_block = ring_data->rx_curr_get_info.block_index;
7486 int get_off = ring_data->rx_curr_get_info.offset;
7487 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7488 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7489 unsigned char *buff = skb_push(skb, buf0_len);
7490
1ee6dd77 7491 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7492 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7493 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7494 skb_put(skb, buf2_len);
da6971d8 7495 }
20346722 7496
0425b46a
SH		 7497 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!ring_data->lro) ||
7498 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 7499 (sp->rx_csum)) {
7500 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7501 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7502 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7503 /*
1da177e4
LT		 7504 * NIC verifies if the Checksum of the received
7505 * frame is Ok or not and accordingly returns
7506 * a flag in the RxD.
7507 */
7508 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7509 if (ring_data->lro) {
7d3d0439
RA		 7510 u32 tcp_len;
7511 u8 *tcp;
7512 int ret = 0;
7513
0425b46a
SH		 7514 ret = s2io_club_tcp_session(ring_data,
7515 skb->data, &tcp, &tcp_len, &lro,
7516 rxdp, sp);
7d3d0439
RA		 7517 switch (ret) {
7518 case 3: /* Begin anew */
7519 lro->parent = skb;
7520 goto aggregate;
7521 case 1: /* Aggregate */
7522 {
7523 lro_append_pkt(sp, lro,
7524 skb, tcp_len);
7525 goto aggregate;
7526 }
7527 case 4: /* Flush session */
7528 {
7529 lro_append_pkt(sp, lro,
7530 skb, tcp_len);
cdb5bf02
SH		 7531 queue_rx_frame(lro->parent,
7532 lro->vlan_tag);
7d3d0439
RA		 7533 clear_lro_session(lro);
7534 sp->mac_control.stats_info->
7535 sw_stat.flush_max_pkts++;
7536 goto aggregate;
7537 }
7538 case 2: /* Flush both */
7539 lro->parent->data_len =
7540 lro->frags_len;
7541 sp->mac_control.stats_info->
7542 sw_stat.sending_both++;
cdb5bf02
SH		 7543 queue_rx_frame(lro->parent,
7544 lro->vlan_tag);
7d3d0439
RA		 7545 clear_lro_session(lro);
7546 goto send_up;
7547 case 0: /* sessions exceeded */
c92ca04b
AR		 7548 case -1: /* non-TCP or not
7549 * L2 aggregatable
7550 */
7d3d0439
RA		 7551 case 5: /*
7552 * First pkt in session not
7553 * L3/L4 aggregatable
7554 */
7555 break;
7556 default:
7557 DBG_PRINT(ERR_DBG,
7558 "%s: Samadhana!!\n",
b39d66a8 7559 __func__);
7d3d0439
RA		 7560 BUG();
7561 }
7562 }
1da177e4 7563 } else {
20346722 7564 /*
7565 * Packet with erroneous checksum, let the
1da177e4
LT		 7566 * upper layers deal with it.
7567 */
7568 skb->ip_summed = CHECKSUM_NONE;
7569 }
cdb5bf02 7570 } else
1da177e4 7571 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7572
491976b2 7573 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439 7574send_up:
0c8dfc83 7575 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7576 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7577aggregate:
0425b46a 7578 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7579 return SUCCESS;
7580}
7581
7582/**
7583 * s2io_link - stops/starts the Tx queue.
7584 * @sp : private member of the device structure, which is a pointer to the
7585 * s2io_nic structure.
7586 * @link : inidicates whether link is UP/DOWN.
7587 * Description:
7588 * This function stops/starts the Tx queue depending on whether the link
20346722 7589 * status of the NIC is is down or up. This is called by the Alarm
7590 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7591 * Return value:
7592 * void.
7593 */
7594
1ee6dd77 7595static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7596{
7597 struct net_device *dev = (struct net_device *) sp->dev;
7598
7599 if (link != sp->last_link_state) {
b7c5678f 7600 init_tti(sp, link);
1da177e4
LT		 7601 if (link == LINK_DOWN) {
7602 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7603 s2io_stop_all_tx_queue(sp);
1da177e4 7604 netif_carrier_off(dev);
491976b2 7605 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7606 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7607 jiffies - sp->start_time;
7608 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7609 } else {
7610 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7611 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7612 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7613 jiffies - sp->start_time;
7614 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4 7615 netif_carrier_on(dev);
3a3d5756 7616 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7617 }
7618 }
7619 sp->last_link_state = link;
491976b2 7620 sp->start_time = jiffies;
1da177e4
LT		 7621}
7622
20346722 7623/**
7624 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7625 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7626 * s2io_nic structure.
7627 * Description:
7628 * This function initializes a few of the PCI and PCI-X configuration registers
7629 * with recommended values.
7630 * Return value:
7631 * void
7632 */
7633
1ee6dd77 7634static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7635{
20346722 7636 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7637
7638 /* Enable Data Parity Error Recovery in PCI-X command register. */
7639 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7640 &(pcix_cmd));
1da177e4 7641 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7642 (pcix_cmd | 1));
1da177e4 7643 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7644 &(pcix_cmd));
1da177e4
LT		 7645
7646 /* Set the PErr Response bit in PCI command register. */
7647 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7648 pci_write_config_word(sp->pdev, PCI_COMMAND,
7649 (pci_cmd | PCI_COMMAND_PARITY));
7650 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7651}
7652
3a3d5756
SH		 7653static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7654 u8 *dev_multiq)
9dc737a7 7655{
2fda096d 7656 if ((tx_fifo_num > MAX_TX_FIFOS) ||
6cfc482b 7657 (tx_fifo_num < 1)) {
2fda096d
SR		 7658 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7659 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7660
7661 if (tx_fifo_num < 1)
7662 tx_fifo_num = 1;
7663 else
7664 tx_fifo_num = MAX_TX_FIFOS;
7665
2fda096d
SR		 7666 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7667 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7668 }
2fda096d 7669
6cfc482b 7670 if (multiq)
3a3d5756 7671 *dev_multiq = multiq;
6cfc482b
SH		 7672
7673 if (tx_steering_type && (1 == tx_fifo_num)) {
7674 if (tx_steering_type != TX_DEFAULT_STEERING)
7675 DBG_PRINT(ERR_DBG,
7676 "s2io: Tx steering is not supported with "
7677 "one fifo. Disabling Tx steering.\n");
7678 tx_steering_type = NO_STEERING;
7679 }
7680
7681 if ((tx_steering_type < NO_STEERING) ||
7682 (tx_steering_type > TX_DEFAULT_STEERING)) {
7683 DBG_PRINT(ERR_DBG, "s2io: Requested transmit steering not "
7684 "supported\n");
7685 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7686 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7687 }
7688
0425b46a
SH		 7689 if (rx_ring_num > MAX_RX_RINGS) {
7690 DBG_PRINT(ERR_DBG, "s2io: Requested number of rx rings not "
9dc737a7 7691 "supported\n");
0425b46a
SH		 7692 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
7693 MAX_RX_RINGS);
7694 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7695 }
0425b46a 7696
eccb8628 7697 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7698 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7699 "Defaulting to INTA\n");
7700 *dev_intr_type = INTA;
7701 }
596c5c97 7702
9dc737a7
AR		 7703 if ((*dev_intr_type == MSI_X) &&
7704 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7705 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7706 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7707 "Defaulting to INTA\n");
7708 *dev_intr_type = INTA;
7709 }
fb6a825b 7710
6d517a27 7711 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7712 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7713 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7714 rx_ring_mode = 1;
9dc737a7
AR		 7715 }
7716 return SUCCESS;
7717}
7718
9fc93a41
SS		 7719/**
7720 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7721 * or Traffic class respectively.
b7c5678f 7722 * @nic: device private variable
9fc93a41
SS		 7723 * Description: The function configures the receive steering to
7724 * desired receive ring.
7725 * Return Value: SUCCESS on success and
7726 * '-1' on failure (endian settings incorrect).
7727 */
7728static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7729{
7730 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7731 register u64 val64 = 0;
7732
7733 if (ds_codepoint > 63)
7734 return FAILURE;
7735
7736 val64 = RTS_DS_MEM_DATA(ring);
7737 writeq(val64, &bar0->rts_ds_mem_data);
7738
7739 val64 = RTS_DS_MEM_CTRL_WE |
7740 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7741 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7742
7743 writeq(val64, &bar0->rts_ds_mem_ctrl);
7744
7745 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7746 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7747 S2IO_BIT_RESET);
7748}
7749
04025095
SH		 7750static const struct net_device_ops s2io_netdev_ops = {
7751 .ndo_open = s2io_open,
7752 .ndo_stop = s2io_close,
7753 .ndo_get_stats = s2io_get_stats,
7754 .ndo_start_xmit = s2io_xmit,
7755 .ndo_validate_addr = eth_validate_addr,
7756 .ndo_set_multicast_list = s2io_set_multicast,
7757 .ndo_do_ioctl = s2io_ioctl,
7758 .ndo_set_mac_address = s2io_set_mac_addr,
7759 .ndo_change_mtu = s2io_change_mtu,
7760 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7761 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7762 .ndo_tx_timeout = s2io_tx_watchdog,
7763#ifdef CONFIG_NET_POLL_CONTROLLER
7764 .ndo_poll_controller = s2io_netpoll,
7765#endif
7766};
7767
1da177e4 7768/**
20346722 7769 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7770 * @pdev : structure containing the PCI related information of the device.
7771 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7772 * Description:
7773 * The function initializes an adapter identified by the pci_dec structure.
20346722 7774 * All OS related initialization including memory and device structure and
7775 * initlaization of the device private variable is done. Also the swapper
7776 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7777 * registers of the device.
7778 * Return value:
7779 * returns 0 on success and negative on failure.
7780 */
7781
7782static int __devinit
7783s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7784{
1ee6dd77 7785 struct s2io_nic *sp;
1da177e4 7786 struct net_device *dev;
1da177e4 7787 int i, j, ret;
f957bcf0 7788 int dma_flag = false;
1da177e4
LT		 7789 u32 mac_up, mac_down;
7790 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7791 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7792 u16 subid;
1ee6dd77 7793 struct mac_info *mac_control;
1da177e4 7794 struct config_param *config;
541ae68f 7795 int mode;
cc6e7c44 7796 u8 dev_intr_type = intr_type;
3a3d5756 7797 u8 dev_multiq = 0;
1da177e4 7798
3a3d5756
SH		 7799 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7800 if (ret)
9dc737a7 7801 return ret;
1da177e4
LT		 7802
7803 if ((ret = pci_enable_device(pdev))) {
7804 DBG_PRINT(ERR_DBG,
7805 "s2io_init_nic: pci_enable_device failed\n");
7806 return ret;
7807 }
7808
6a35528a 7809 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7810 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
f957bcf0 7811 dma_flag = true;
1da177e4 7812 if (pci_set_consistent_dma_mask
6a35528a 7813 (pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 7814 DBG_PRINT(ERR_DBG,
7815 "Unable to obtain 64bit DMA for \
7816 consistent allocations\n");
7817 pci_disable_device(pdev);
7818 return -ENOMEM;
7819 }
284901a9 7820 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 7821 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7822 } else {
7823 pci_disable_device(pdev);
7824 return -ENOMEM;
7825 }
eccb8628 7826 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
b39d66a8 7827 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __func__, ret);
eccb8628
VP		 7828 pci_disable_device(pdev);
7829 return -ENODEV;
1da177e4 7830 }
3a3d5756 7831 if (dev_multiq)
6cfc482b 7832 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7833 else
b19fa1fa 7834 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7835 if (dev == NULL) {
7836 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7837 pci_disable_device(pdev);
7838 pci_release_regions(pdev);
7839 return -ENODEV;
7840 }
7841
7842 pci_set_master(pdev);
7843 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7844 SET_NETDEV_DEV(dev, &pdev->dev);
7845
7846 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7847 sp = netdev_priv(dev);
1ee6dd77 7848 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7849 sp->dev = dev;
7850 sp->pdev = pdev;
1da177e4 7851 sp->high_dma_flag = dma_flag;
f957bcf0 7852 sp->device_enabled_once = false;
da6971d8
AR		 7853 if (rx_ring_mode == 1)
7854 sp->rxd_mode = RXD_MODE_1;
7855 if (rx_ring_mode == 2)
7856 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7857
eaae7f72 7858 sp->config.intr_type = dev_intr_type;
1da177e4 7859
541ae68f 7860 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7861 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7862 sp->device_type = XFRAME_II_DEVICE;
7863 else
7864 sp->device_type = XFRAME_I_DEVICE;
7865
43b7c451 7866 sp->lro = lro_enable;
6aa20a22 7867
1da177e4
LT		 7868 /* Initialize some PCI/PCI-X fields of the NIC. */
7869 s2io_init_pci(sp);
7870
20346722 7871 /*
1da177e4 7872 * Setting the device configuration parameters.
20346722 7873 * Most of these parameters can be specified by the user during
7874 * module insertion as they are module loadable parameters. If
7875 * these parameters are not not specified during load time, they
1da177e4
LT		 7876 * are initialized with default values.
7877 */
7878 mac_control = &sp->mac_control;
7879 config = &sp->config;
7880
596c5c97 7881 config->napi = napi;
6cfc482b 7882 config->tx_steering_type = tx_steering_type;
596c5c97 7883
1da177e4 7884 /* Tx side parameters. */
6cfc482b
SH		 7885 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7886 config->tx_fifo_num = MAX_TX_FIFOS;
7887 else
7888 config->tx_fifo_num = tx_fifo_num;
7889
7890 /* Initialize the fifos used for tx steering */
7891 if (config->tx_fifo_num < 5) {
7892 if (config->tx_fifo_num == 1)
7893 sp->total_tcp_fifos = 1;
7894 else
7895 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7896 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7897 sp->total_udp_fifos = 1;
7898 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7899 } else {
7900 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7901 FIFO_OTHER_MAX_NUM);
7902 sp->udp_fifo_idx = sp->total_tcp_fifos;
7903 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7904 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7905 }
7906
3a3d5756 7907 config->multiq = dev_multiq;
6cfc482b 7908 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7909 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7910
7911 tx_cfg->fifo_len = tx_fifo_len[i];
7912 tx_cfg->fifo_priority = i;
1da177e4
LT		 7913 }
7914
20346722 7915 /* mapping the QoS priority to the configured fifos */
7916 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7917 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7918
6cfc482b
SH		 7919 /* map the hashing selector table to the configured fifos */
7920 for (i = 0; i < config->tx_fifo_num; i++)
7921 sp->fifo_selector[i] = fifo_selector[i];
7922
7923
1da177e4
LT		 7924 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7925 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7926 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7927
7928 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7929 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7930 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7931 break;
7932 }
7933 }
fed5eccd
AR		 7934 /* + 2 because one Txd for skb->data and one Txd for UFO */
7935 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7936
7937 /* Rx side parameters. */
1da177e4 7938 config->rx_ring_num = rx_ring_num;
0425b46a 7939 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7940 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7941 struct ring_info *ring = &mac_control->rings[i];
7942
7943 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7944 rx_cfg->ring_priority = i;
7945 ring->rx_bufs_left = 0;
7946 ring->rxd_mode = sp->rxd_mode;
7947 ring->rxd_count = rxd_count[sp->rxd_mode];
7948 ring->pdev = sp->pdev;
7949 ring->dev = sp->dev;
1da177e4
LT		 7950 }
7951
7952 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7953 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7954
7955 rx_cfg->ring_org = RING_ORG_BUFF1;
7956 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7957 }
7958
7959 /* Setting Mac Control parameters */
7960 mac_control->rmac_pause_time = rmac_pause_time;
7961 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7962 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7963
7964
1da177e4
LT		 7965 /* initialize the shared memory used by the NIC and the host */
7966 if (init_shared_mem(sp)) {
7967 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7968 dev->name);
1da177e4
LT		 7969 ret = -ENOMEM;
7970 goto mem_alloc_failed;
7971 }
7972
275f165f 7973 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7974 if (!sp->bar0) {
19a60522 7975 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7976 dev->name);
7977 ret = -ENOMEM;
7978 goto bar0_remap_failed;
7979 }
7980
275f165f 7981 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7982 if (!sp->bar1) {
19a60522 7983 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7984 dev->name);
7985 ret = -ENOMEM;
7986 goto bar1_remap_failed;
7987 }
7988
7989 dev->irq = pdev->irq;
7990 dev->base_addr = (unsigned long) sp->bar0;
7991
7992 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7993 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7994 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7995 (sp->bar1 + (j * 0x00020000));
7996 }
7997
7998 /* Driver entry points */
04025095 7999 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 8000 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8001 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 8002
1da177e4 8003 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 8004 if (sp->high_dma_flag == true)
1da177e4 8005 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8006 dev->features |= NETIF_F_TSO;
f83ef8c0 8007 dev->features |= NETIF_F_TSO6;
db874e65 8008 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8009 dev->features |= NETIF_F_UFO;
8010 dev->features |= NETIF_F_HW_CSUM;
8011 }
1da177e4 8012 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8013 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8014 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8015
e960fc5c 8016 pci_save_state(sp->pdev);
1da177e4
LT		 8017
8018 /* Setting swapper control on the NIC, for proper reset operation */
8019 if (s2io_set_swapper(sp)) {
8020 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
8021 dev->name);
8022 ret = -EAGAIN;
8023 goto set_swap_failed;
8024 }
8025
541ae68f 8026 /* Verify if the Herc works on the slot its placed into */
8027 if (sp->device_type & XFRAME_II_DEVICE) {
8028 mode = s2io_verify_pci_mode(sp);
8029 if (mode < 0) {
b39d66a8 8030 DBG_PRINT(ERR_DBG, "%s: ", __func__);
541ae68f 8031 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8032 ret = -EBADSLT;
8033 goto set_swap_failed;
8034 }
8035 }
8036
f61e0a35
SH		 8037 if (sp->config.intr_type == MSI_X) {
8038 sp->num_entries = config->rx_ring_num + 1;
8039 ret = s2io_enable_msi_x(sp);
8040
8041 if (!ret) {
8042 ret = s2io_test_msi(sp);
8043 /* rollback MSI-X, will re-enable during add_isr() */
8044 remove_msix_isr(sp);
8045 }
8046 if (ret) {
8047
8048 DBG_PRINT(ERR_DBG,
073a2436 8049 "s2io: MSI-X requested but failed to enable\n");
f61e0a35
SH		 8050 sp->config.intr_type = INTA;
8051 }
8052 }
8053
8054 if (config->intr_type == MSI_X) {
13d866a9
JP		 8055 for (i = 0; i < config->rx_ring_num ; i++) {
8056 struct ring_info *ring = &mac_control->rings[i];
8057
8058 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8059 }
f61e0a35
SH		 8060 } else {
8061 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8062 }
8063
541ae68f 8064 /* Not needed for Herc */
8065 if (sp->device_type & XFRAME_I_DEVICE) {
8066 /*
8067 * Fix for all "FFs" MAC address problems observed on
8068 * Alpha platforms
8069 */
8070 fix_mac_address(sp);
8071 s2io_reset(sp);
8072 }
1da177e4
LT		 8073
8074 /*
1da177e4
LT		 8075 * MAC address initialization.
8076 * For now only one mac address will be read and used.
8077 */
8078 bar0 = sp->bar0;
8079 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 8080 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8081 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8082 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 8083 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 8084 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8085 mac_down = (u32) tmp64;
8086 mac_up = (u32) (tmp64 >> 32);
8087
1da177e4
LT		 8088 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8089 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8090 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8091 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8092 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8093 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8094
1da177e4
LT		 8095 /* Set the factory defined MAC address initially */
8096 dev->addr_len = ETH_ALEN;
8097 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8098 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8099
faa4f796
SH		 8100 /* initialize number of multicast & unicast MAC entries variables */
8101 if (sp->device_type == XFRAME_I_DEVICE) {
8102 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8103 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8104 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8105 } else if (sp->device_type == XFRAME_II_DEVICE) {
8106 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8107 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8108 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8109 }
8110
8111 /* store mac addresses from CAM to s2io_nic structure */
8112 do_s2io_store_unicast_mc(sp);
8113
f61e0a35
SH		 8114 /* Configure MSIX vector for number of rings configured plus one */
8115 if ((sp->device_type == XFRAME_II_DEVICE) &&
8116 (config->intr_type == MSI_X))
8117 sp->num_entries = config->rx_ring_num + 1;
8118
c77dd43e
SS		 8119 /* Store the values of the MSIX table in the s2io_nic structure */
8120 store_xmsi_data(sp);
b41477f3
AR		 8121 /* reset Nic and bring it to known state */
8122 s2io_reset(sp);
8123
1da177e4 8124 /*
99993af6 8125 * Initialize link state flags
541ae68f 8126 * and the card state parameter
1da177e4 8127 */
92b84437 8128 sp->state = 0;
1da177e4 8129
1da177e4 8130 /* Initialize spinlocks */
13d866a9
JP		 8131 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8132 struct fifo_info *fifo = &mac_control->fifos[i];
8133
8134 spin_lock_init(&fifo->tx_lock);
8135 }
db874e65 8136
20346722 8137 /*
8138 * SXE-002: Configure link and activity LED to init state
8139 * on driver load.
1da177e4
LT		 8140 */
8141 subid = sp->pdev->subsystem_device;
8142 if ((subid & 0xFF) >= 0x07) {
8143 val64 = readq(&bar0->gpio_control);
8144 val64 |= 0x0000800000000000ULL;
8145 writeq(val64, &bar0->gpio_control);
8146 val64 = 0x0411040400000000ULL;
8147 writeq(val64, (void __iomem *) bar0 + 0x2700);
8148 val64 = readq(&bar0->gpio_control);
8149 }
8150
8151 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8152
8153 if (register_netdev(dev)) {
8154 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8155 ret = -ENODEV;
8156 goto register_failed;
8157 }
9dc737a7 8158 s2io_vpd_read(sp);
0c61ed5f 8159 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 8160 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 8161 sp->product_name, pdev->revision);
b41477f3
AR		 8162 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8163 s2io_driver_version);
e174961c 8164 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
19a60522 8165 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8166 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8167 mode = s2io_print_pci_mode(sp);
541ae68f 8168 if (mode < 0) {
9dc737a7 8169 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8170 ret = -EBADSLT;
9dc737a7 8171 unregister_netdev(dev);
541ae68f 8172 goto set_swap_failed;
8173 }
541ae68f 8174 }
9dc737a7
AR		 8175 switch(sp->rxd_mode) {
8176 case RXD_MODE_1:
8177 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8178 dev->name);
8179 break;
8180 case RXD_MODE_3B:
8181 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8182 dev->name);
8183 break;
9dc737a7 8184 }
db874e65 8185
f61e0a35
SH		 8186 switch (sp->config.napi) {
8187 case 0:
8188 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8189 break;
8190 case 1:
db874e65 8191 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8192 break;
8193 }
3a3d5756
SH		 8194
8195 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8196 sp->config.tx_fifo_num);
8197
0425b46a
SH		 8198 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8199 sp->config.rx_ring_num);
8200
eaae7f72 8201 switch(sp->config.intr_type) {
9dc737a7
AR		 8202 case INTA:
8203 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8204 break;
9dc737a7
AR		 8205 case MSI_X:
8206 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8207 break;
8208 }
3a3d5756 8209 if (sp->config.multiq) {
13d866a9
JP		 8210 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8211 struct fifo_info *fifo = &mac_control->fifos[i];
8212
8213 fifo->multiq = config->multiq;
8214 }
3a3d5756
SH		 8215 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8216 dev->name);
8217 } else
8218 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8219 dev->name);
8220
6cfc482b
SH		 8221 switch (sp->config.tx_steering_type) {
8222 case NO_STEERING:
8223 DBG_PRINT(ERR_DBG, "%s: No steering enabled for"
8224 " transmit\n", dev->name);
8225 break;
8226 case TX_PRIORITY_STEERING:
8227 DBG_PRINT(ERR_DBG, "%s: Priority steering enabled for"
8228 " transmit\n", dev->name);
8229 break;
8230 case TX_DEFAULT_STEERING:
8231 DBG_PRINT(ERR_DBG, "%s: Default steering enabled for"
8232 " transmit\n", dev->name);
8233 }
8234
7d3d0439
RA		 8235 if (sp->lro)
8236 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8237 dev->name);
db874e65
SS		 8238 if (ufo)
8239 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
8240 " enabled\n", dev->name);
7ba013ac 8241 /* Initialize device name */
9dc737a7 8242 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8243
cd0fce03
BL		 8244 if (vlan_tag_strip)
8245 sp->vlan_strip_flag = 1;
8246 else
8247 sp->vlan_strip_flag = 0;
8248
20346722 8249 /*
8250 * Make Link state as off at this point, when the Link change
8251 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8252 * the right state.
8253 */
8254 netif_carrier_off(dev);
1da177e4
LT		 8255
8256 return 0;
8257
8258 register_failed:
8259 set_swap_failed:
8260 iounmap(sp->bar1);
8261 bar1_remap_failed:
8262 iounmap(sp->bar0);
8263 bar0_remap_failed:
8264 mem_alloc_failed:
8265 free_shared_mem(sp);
8266 pci_disable_device(pdev);
eccb8628 8267 pci_release_regions(pdev);
1da177e4
LT		 8268 pci_set_drvdata(pdev, NULL);
8269 free_netdev(dev);
8270
8271 return ret;
8272}
8273
8274/**
20346722 8275 * s2io_rem_nic - Free the PCI device
1da177e4 8276 * @pdev: structure containing the PCI related information of the device.
20346722 8277 * Description: This function is called by the Pci subsystem to release a
1da177e4 8278 * PCI device and free up all resource held up by the device. This could
20346722 8279 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8280 * from memory.
8281 */
8282
8283static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8284{
8285 struct net_device *dev =
8286 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8287 struct s2io_nic *sp;
1da177e4
LT		 8288
8289 if (dev == NULL) {
8290 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8291 return;
8292 }
8293
22747d6b
FR		 8294 flush_scheduled_work();
8295
4cf1653a 8296 sp = netdev_priv(dev);
1da177e4
LT		 8297 unregister_netdev(dev);
8298
8299 free_shared_mem(sp);
8300 iounmap(sp->bar0);
8301 iounmap(sp->bar1);
eccb8628 8302 pci_release_regions(pdev);
1da177e4 8303 pci_set_drvdata(pdev, NULL);
1da177e4 8304 free_netdev(dev);
19a60522 8305 pci_disable_device(pdev);
1da177e4
LT		 8306}
8307
8308/**
8309 * s2io_starter - Entry point for the driver
8310 * Description: This function is the entry point for the driver. It verifies
8311 * the module loadable parameters and initializes PCI configuration space.
8312 */
8313
43b7c451 8314static int __init s2io_starter(void)
1da177e4 8315{
29917620 8316 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8317}
8318
8319/**
20346722 8320 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8321 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8322 */
8323
372cc597 8324static __exit void s2io_closer(void)
1da177e4
LT		 8325{
8326 pci_unregister_driver(&s2io_driver);
8327 DBG_PRINT(INIT_DBG, "cleanup done\n");
8328}
8329
8330module_init(s2io_starter);
8331module_exit(s2io_closer);
7d3d0439 8332
6aa20a22 8333static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
cdb5bf02
SH		 8334 struct tcphdr **tcp, struct RxD_t *rxdp,
8335 struct s2io_nic *sp)
7d3d0439
RA		 8336{
8337 int ip_off;
8338 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8339
8340 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8341 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8342 __func__);
7d3d0439
RA		 8343 return -1;
8344 }
8345
cdb5bf02
SH		 8346 /* Checking for DIX type or DIX type with VLAN */
8347 if ((l2_type == 0)
8348 || (l2_type == 4)) {
8349 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8350 /*
8351 * If vlan stripping is disabled and the frame is VLAN tagged,
8352 * shift the offset by the VLAN header size bytes.
8353 */
cd0fce03 8354 if ((!sp->vlan_strip_flag) &&
cdb5bf02
SH		 8355 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8356 ip_off += HEADER_VLAN_SIZE;
8357 } else {
7d3d0439 8358 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8359 return -1;
7d3d0439
RA		 8360 }
8361
8362 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8363 ip_len = (u8)((*ip)->ihl);
8364 ip_len <<= 2;
8365 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8366
8367 return 0;
8368}
8369
1ee6dd77 8370static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8371 struct tcphdr *tcp)
8372{
b39d66a8 8373 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8374 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8375 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8376 return -1;
8377 return 0;
8378}
8379
8380static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8381{
8382 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8383}
8384
1ee6dd77 8385static void initiate_new_session(struct lro *lro, u8 *l2h,
cdb5bf02 8386 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8387{
b39d66a8 8388 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8389 lro->l2h = l2h;
8390 lro->iph = ip;
8391 lro->tcph = tcp;
8392 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8393 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8394 lro->sg_num = 1;
8395 lro->total_len = ntohs(ip->tot_len);
8396 lro->frags_len = 0;
cdb5bf02 8397 lro->vlan_tag = vlan_tag;
6aa20a22 8398 /*
7d3d0439
RA		 8399 * check if we saw TCP timestamp. Other consistency checks have
8400 * already been done.
8401 */
8402 if (tcp->doff == 8) {
c8855953
SR		 8403 __be32 *ptr;
8404 ptr = (__be32 *)(tcp+1);
7d3d0439 8405 lro->saw_ts = 1;
c8855953 8406 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8407 lro->cur_tsecr = *(ptr+2);
8408 }
8409 lro->in_use = 1;
8410}
8411
1ee6dd77 8412static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8413{
8414 struct iphdr *ip = lro->iph;
8415 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8416 __sum16 nchk;
1ee6dd77 8417 struct stat_block *statinfo = sp->mac_control.stats_info;
b39d66a8 8418 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8419
8420 /* Update L3 header */
8421 ip->tot_len = htons(lro->total_len);
8422 ip->check = 0;
8423 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8424 ip->check = nchk;
8425
8426 /* Update L4 header */
8427 tcp->ack_seq = lro->tcp_ack;
8428 tcp->window = lro->window;
8429
8430 /* Update tsecr field if this session has timestamps enabled */
8431 if (lro->saw_ts) {
c8855953 8432 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8433 *(ptr+2) = lro->cur_tsecr;
8434 }
8435
8436 /* Update counters required for calculation of
8437 * average no. of packets aggregated.
8438 */
8439 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8440 statinfo->sw_stat.num_aggregations++;
8441}
8442
1ee6dd77 8443static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8444 struct tcphdr *tcp, u32 l4_pyld)
8445{
b39d66a8 8446 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
7d3d0439
RA		 8447 lro->total_len += l4_pyld;
8448 lro->frags_len += l4_pyld;
8449 lro->tcp_next_seq += l4_pyld;
8450 lro->sg_num++;
8451
8452 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8453 lro->tcp_ack = tcp->ack_seq;
8454 lro->window = tcp->window;
6aa20a22 8455
7d3d0439 8456 if (lro->saw_ts) {
c8855953 8457 __be32 *ptr;
7d3d0439 8458 /* Update tsecr and tsval from this packet */
c8855953
SR		 8459 ptr = (__be32 *)(tcp+1);
8460 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8461 lro->cur_tsecr = *(ptr + 2);
8462 }
8463}
8464
1ee6dd77 8465static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8466 struct tcphdr *tcp, u32 tcp_pyld_len)
8467{
7d3d0439
RA		 8468 u8 *ptr;
8469
b39d66a8 8470 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __func__);
79dc1901 8471
7d3d0439
RA		 8472 if (!tcp_pyld_len) {
8473 /* Runt frame or a pure ack */
8474 return -1;
8475 }
8476
8477 if (ip->ihl != 5) /* IP has options */
8478 return -1;
8479
75c30b13
AR		 8480 /* If we see CE codepoint in IP header, packet is not mergeable */
8481 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8482 return -1;
8483
8484 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8485 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8486 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8487 /*
8488 * Currently recognize only the ack control word and
8489 * any other control field being set would result in
8490 * flushing the LRO session
8491 */
8492 return -1;
8493 }
8494
6aa20a22 8495 /*
7d3d0439
RA		 8496 * Allow only one TCP timestamp option. Don't aggregate if
8497 * any other options are detected.
8498 */
8499 if (tcp->doff != 5 && tcp->doff != 8)
8500 return -1;
8501
8502 if (tcp->doff == 8) {
6aa20a22 8503 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8504 while (*ptr == TCPOPT_NOP)
8505 ptr++;
8506 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8507 return -1;
8508
8509 /* Ensure timestamp value increases monotonically */
8510 if (l_lro)
c8855953 8511 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8512 return -1;
8513
8514 /* timestamp echo reply should be non-zero */
c8855953 8515 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8516 return -1;
8517 }
8518
8519 return 0;
8520}
8521
8522static int
0425b46a
SH		 8523s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, u8 **tcp,
8524 u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp,
8525 struct s2io_nic *sp)
7d3d0439
RA		 8526{
8527 struct iphdr *ip;
8528 struct tcphdr *tcph;
8529 int ret = 0, i;
cdb5bf02 8530 u16 vlan_tag = 0;
7d3d0439
RA		 8531
8532 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
cdb5bf02 8533 rxdp, sp))) {
7d3d0439
RA		 8534 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8535 ip->saddr, ip->daddr);
cdb5bf02 8536 } else
7d3d0439 8537 return ret;
7d3d0439 8538
cdb5bf02 8539 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8540 tcph = (struct tcphdr *)*tcp;
8541 *tcp_len = get_l4_pyld_length(ip, tcph);
8542 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8543 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8544 if (l_lro->in_use) {
8545 if (check_for_socket_match(l_lro, ip, tcph))
8546 continue;
8547 /* Sock pair matched */
8548 *lro = l_lro;
8549
8550 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8551 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
b39d66a8 8552 "0x%x, actual 0x%x\n", __func__,
7d3d0439
RA		 8553 (*lro)->tcp_next_seq,
8554 ntohl(tcph->seq));
8555
8556 sp->mac_control.stats_info->
8557 sw_stat.outof_sequence_pkts++;
8558 ret = 2;
8559 break;
8560 }
8561
8562 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8563 ret = 1; /* Aggregate */
8564 else
8565 ret = 2; /* Flush both */
8566 break;
8567 }
8568 }
8569
8570 if (ret == 0) {
8571 /* Before searching for available LRO objects,
8572 * check if the pkt is L3/L4 aggregatable. If not
8573 * don't create new LRO session. Just send this
8574 * packet up.
8575 */
8576 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8577 return 5;
8578 }
8579
8580 for (i=0; i<MAX_LRO_SESSIONS; i++) {
0425b46a 8581 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8582 if (!(l_lro->in_use)) {
8583 *lro = l_lro;
8584 ret = 3; /* Begin anew */
8585 break;
8586 }
8587 }
8588 }
8589
8590 if (ret == 0) { /* sessions exceeded */
8591 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
b39d66a8 8592 __func__);
7d3d0439
RA		 8593 *lro = NULL;
8594 return ret;
8595 }
8596
8597 switch (ret) {
8598 case 3:
cdb5bf02
SH		 8599 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8600 vlan_tag);
7d3d0439
RA		 8601 break;
8602 case 2:
8603 update_L3L4_header(sp, *lro);
8604 break;
8605 case 1:
8606 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8607 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8608 update_L3L4_header(sp, *lro);
8609 ret = 4; /* Flush the LRO */
8610 }
8611 break;
8612 default:
8613 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
b39d66a8 8614 __func__);
7d3d0439
RA		 8615 break;
8616 }
8617
8618 return ret;
8619}
8620
1ee6dd77 8621static void clear_lro_session(struct lro *lro)
7d3d0439 8622{
1ee6dd77 8623 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8624
8625 memset(lro, 0, lro_struct_size);
8626}
8627
cdb5bf02 8628static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8629{
8630 struct net_device *dev = skb->dev;
4cf1653a 8631 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8632
8633 skb->protocol = eth_type_trans(skb, dev);
cdb5bf02 8634 if (sp->vlgrp && vlan_tag
cd0fce03 8635 && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8636 /* Queueing the vlan frame to the upper layer */
8637 if (sp->config.napi)
8638 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8639 else
8640 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8641 } else {
8642 if (sp->config.napi)
8643 netif_receive_skb(skb);
8644 else
8645 netif_rx(skb);
8646 }
7d3d0439
RA		 8647}
8648
1ee6dd77
RB		 8649static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8650 struct sk_buff *skb,
7d3d0439
RA		 8651 u32 tcp_len)
8652{
75c30b13 8653 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8654
8655 first->len += tcp_len;
8656 first->data_len = lro->frags_len;
8657 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8658 if (skb_shinfo(first)->frag_list)
8659 lro->last_frag->next = skb;
7d3d0439
RA		 8660 else
8661 skb_shinfo(first)->frag_list = skb;
372cc597 8662 first->truesize += skb->truesize;
75c30b13 8663 lro->last_frag = skb;
7d3d0439
RA		 8664 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8665 return;
8666}
d796fdb7
LV		 8667
8668/**
8669 * s2io_io_error_detected - called when PCI error is detected
8670 * @pdev: Pointer to PCI device
8453d43f 8671 * @state: The current pci connection state
d796fdb7
LV		 8672 *
8673 * This function is called after a PCI bus error affecting
8674 * this device has been detected.
8675 */
8676static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8677 pci_channel_state_t state)
8678{
8679 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8680 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8681
8682 netif_device_detach(netdev);
8683
1e3c8bd6
DN		 8684 if (state == pci_channel_io_perm_failure)
8685 return PCI_ERS_RESULT_DISCONNECT;
8686
d796fdb7
LV		 8687 if (netif_running(netdev)) {
8688 /* Bring down the card, while avoiding PCI I/O */
8689 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8690 }
8691 pci_disable_device(pdev);
8692
8693 return PCI_ERS_RESULT_NEED_RESET;
8694}
8695
8696/**
8697 * s2io_io_slot_reset - called after the pci bus has been reset.
8698 * @pdev: Pointer to PCI device
8699 *
8700 * Restart the card from scratch, as if from a cold-boot.
8701 * At this point, the card has exprienced a hard reset,
8702 * followed by fixups by BIOS, and has its config space
8703 * set up identically to what it was at cold boot.
8704 */
8705static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8706{
8707 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8708 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8709
8710 if (pci_enable_device(pdev)) {
8711 printk(KERN_ERR "s2io: "
8712 "Cannot re-enable PCI device after reset.\n");
8713 return PCI_ERS_RESULT_DISCONNECT;
8714 }
8715
8716 pci_set_master(pdev);
8717 s2io_reset(sp);
8718
8719 return PCI_ERS_RESULT_RECOVERED;
8720}
8721
8722/**
8723 * s2io_io_resume - called when traffic can start flowing again.
8724 * @pdev: Pointer to PCI device
8725 *
8726 * This callback is called when the error recovery driver tells
8727 * us that its OK to resume normal operation.
8728 */
8729static void s2io_io_resume(struct pci_dev *pdev)
8730{
8731 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8732 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8733
8734 if (netif_running(netdev)) {
8735 if (s2io_card_up(sp)) {
8736 printk(KERN_ERR "s2io: "
8737 "Can't bring device back up after reset.\n");
8738 return;
8739 }
8740
8741 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8742 s2io_card_down(sp);
8743 printk(KERN_ERR "s2io: "
8744 "Can't resetore mac addr after reset.\n");
8745 return;
8746 }
8747 }
8748
8749 netif_device_attach(netdev);
fd2ea0a7 8750 netif_tx_wake_all_queues(netdev);
d796fdb7 8751}
Linux kernel - Deliverables
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