projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
S2IO: Avoid printing the Enhanced statistics for Xframe I card.
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
1da177e4
LT		 3 * Copyright(c) 2002-2005 Neterion Inc.
4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8
AR		 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35 * values are 1, 2 and 3.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7
AR		 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 1(MSI), 2(MSI_X). Default value is '0(INTA)'
41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
1da177e4
LT		 53 ************************************************************************/
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/stddef.h>
68#include <linux/ioctl.h>
69#include <linux/timex.h>
1da177e4 70#include <linux/ethtool.h>
1da177e4 71#include <linux/workqueue.h>
be3a6b02 72#include <linux/if_vlan.h>
7d3d0439
RA		 73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <net/tcp.h>
1da177e4 76
1da177e4
LT		 77#include <asm/system.h>
78#include <asm/uaccess.h>
20346722 79#include <asm/io.h>
fe931395 80#include <asm/div64.h>
330ce0de 81#include <asm/irq.h>
1da177e4
LT		 82
83/* local include */
84#include "s2io.h"
85#include "s2io-regs.h"
86
1ee6dd77 87#define DRV_VERSION "2.0.16.1"
6c1792f4 88
1da177e4 89/* S2io Driver name & version. */
20346722 90static char s2io_driver_name[] = "Neterion";
6c1792f4 91static char s2io_driver_version[] = DRV_VERSION;
1da177e4 92
26df54bf
AB		 93static int rxd_size[4] = {32,48,48,64};
94static int rxd_count[4] = {127,85,85,63};
da6971d8 95
1ee6dd77 96static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 97{
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104}
105
20346722 106/*
1da177e4
LT		 107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
541ae68f 111#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 115
116#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119#define PANIC 1
120#define LOW 2
1ee6dd77 121static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 122{
1ee6dd77 123 struct mac_info *mac_control;
20346722 124
125 mac_control = &sp->mac_control;
863c11a9
AR		 126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
1da177e4
LT		 131}
132
133/* Ethtool related variables and Macros. */
134static char s2io_gstrings[][ETH_GSTRING_LEN] = {
135 "Register test\t(offline)",
136 "Eeprom test\t(offline)",
137 "Link test\t(online)",
138 "RLDRAM test\t(offline)",
139 "BIST Test\t(offline)"
140};
141
fa1f0cb3 142static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 143 {"tmac_frms"},
144 {"tmac_data_octets"},
145 {"tmac_drop_frms"},
146 {"tmac_mcst_frms"},
147 {"tmac_bcst_frms"},
148 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 149 {"tmac_ttl_octets"},
150 {"tmac_ucst_frms"},
151 {"tmac_nucst_frms"},
1da177e4 152 {"tmac_any_err_frms"},
bd1034f0 153 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 154 {"tmac_vld_ip_octets"},
155 {"tmac_vld_ip"},
156 {"tmac_drop_ip"},
157 {"tmac_icmp"},
158 {"tmac_rst_tcp"},
159 {"tmac_tcp"},
160 {"tmac_udp"},
161 {"rmac_vld_frms"},
162 {"rmac_data_octets"},
163 {"rmac_fcs_err_frms"},
164 {"rmac_drop_frms"},
165 {"rmac_vld_mcst_frms"},
166 {"rmac_vld_bcst_frms"},
167 {"rmac_in_rng_len_err_frms"},
bd1034f0 168 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 169 {"rmac_long_frms"},
170 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 171 {"rmac_unsup_ctrl_frms"},
172 {"rmac_ttl_octets"},
173 {"rmac_accepted_ucst_frms"},
174 {"rmac_accepted_nucst_frms"},
1da177e4 175 {"rmac_discarded_frms"},
bd1034f0
AR		 176 {"rmac_drop_events"},
177 {"rmac_ttl_less_fb_octets"},
178 {"rmac_ttl_frms"},
1da177e4
LT		 179 {"rmac_usized_frms"},
180 {"rmac_osized_frms"},
181 {"rmac_frag_frms"},
182 {"rmac_jabber_frms"},
bd1034f0
AR		 183 {"rmac_ttl_64_frms"},
184 {"rmac_ttl_65_127_frms"},
185 {"rmac_ttl_128_255_frms"},
186 {"rmac_ttl_256_511_frms"},
187 {"rmac_ttl_512_1023_frms"},
188 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 189 {"rmac_ip"},
190 {"rmac_ip_octets"},
191 {"rmac_hdr_err_ip"},
192 {"rmac_drop_ip"},
193 {"rmac_icmp"},
194 {"rmac_tcp"},
195 {"rmac_udp"},
196 {"rmac_err_drp_udp"},
bd1034f0
AR		 197 {"rmac_xgmii_err_sym"},
198 {"rmac_frms_q0"},
199 {"rmac_frms_q1"},
200 {"rmac_frms_q2"},
201 {"rmac_frms_q3"},
202 {"rmac_frms_q4"},
203 {"rmac_frms_q5"},
204 {"rmac_frms_q6"},
205 {"rmac_frms_q7"},
206 {"rmac_full_q0"},
207 {"rmac_full_q1"},
208 {"rmac_full_q2"},
209 {"rmac_full_q3"},
210 {"rmac_full_q4"},
211 {"rmac_full_q5"},
212 {"rmac_full_q6"},
213 {"rmac_full_q7"},
1da177e4 214 {"rmac_pause_cnt"},
bd1034f0
AR		 215 {"rmac_xgmii_data_err_cnt"},
216 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 217 {"rmac_accepted_ip"},
218 {"rmac_err_tcp"},
bd1034f0
AR		 219 {"rd_req_cnt"},
220 {"new_rd_req_cnt"},
221 {"new_rd_req_rtry_cnt"},
222 {"rd_rtry_cnt"},
223 {"wr_rtry_rd_ack_cnt"},
224 {"wr_req_cnt"},
225 {"new_wr_req_cnt"},
226 {"new_wr_req_rtry_cnt"},
227 {"wr_rtry_cnt"},
228 {"wr_disc_cnt"},
229 {"rd_rtry_wr_ack_cnt"},
230 {"txp_wr_cnt"},
231 {"txd_rd_cnt"},
232 {"txd_wr_cnt"},
233 {"rxd_rd_cnt"},
234 {"rxd_wr_cnt"},
235 {"txf_rd_cnt"},
fa1f0cb3
SS		 236 {"rxf_wr_cnt"}
237};
238
239static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 240 {"rmac_ttl_1519_4095_frms"},
241 {"rmac_ttl_4096_8191_frms"},
242 {"rmac_ttl_8192_max_frms"},
243 {"rmac_ttl_gt_max_frms"},
244 {"rmac_osized_alt_frms"},
245 {"rmac_jabber_alt_frms"},
246 {"rmac_gt_max_alt_frms"},
247 {"rmac_vlan_frms"},
248 {"rmac_len_discard"},
249 {"rmac_fcs_discard"},
250 {"rmac_pf_discard"},
251 {"rmac_da_discard"},
252 {"rmac_red_discard"},
253 {"rmac_rts_discard"},
254 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 255 {"link_fault_cnt"}
256};
257
258static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 259 {"\n DRIVER STATISTICS"},
260 {"single_bit_ecc_errs"},
261 {"double_bit_ecc_errs"},
bd1034f0
AR		 262 {"parity_err_cnt"},
263 {"serious_err_cnt"},
264 {"soft_reset_cnt"},
265 {"fifo_full_cnt"},
266 {"ring_full_cnt"},
267 ("alarm_transceiver_temp_high"),
268 ("alarm_transceiver_temp_low"),
269 ("alarm_laser_bias_current_high"),
270 ("alarm_laser_bias_current_low"),
271 ("alarm_laser_output_power_high"),
272 ("alarm_laser_output_power_low"),
273 ("warn_transceiver_temp_high"),
274 ("warn_transceiver_temp_low"),
275 ("warn_laser_bias_current_high"),
276 ("warn_laser_bias_current_low"),
277 ("warn_laser_output_power_high"),
278 ("warn_laser_output_power_low"),
7d3d0439
RA		 279 ("lro_aggregated_pkts"),
280 ("lro_flush_both_count"),
281 ("lro_out_of_sequence_pkts"),
282 ("lro_flush_due_to_max_pkts"),
283 ("lro_avg_aggr_pkts"),
1da177e4
LT		 284};
285
fa1f0cb3
SS		 286#define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
287#define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
288 ETH_GSTRING_LEN
289#define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
290
291#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
292#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
293
294#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
295#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4
LT		 296
297#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
298#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
299
25fff88e 300#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
301 init_timer(&timer); \
302 timer.function = handle; \
303 timer.data = (unsigned long) arg; \
304 mod_timer(&timer, (jiffies + exp)) \
305
be3a6b02 306/* Add the vlan */
307static void s2io_vlan_rx_register(struct net_device *dev,
308 struct vlan_group *grp)
309{
1ee6dd77 310 struct s2io_nic *nic = dev->priv;
be3a6b02 311 unsigned long flags;
312
313 spin_lock_irqsave(&nic->tx_lock, flags);
314 nic->vlgrp = grp;
315 spin_unlock_irqrestore(&nic->tx_lock, flags);
316}
317
926930b2
SS		 318/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
319int vlan_strip_flag;
320
be3a6b02 321/* Unregister the vlan */
322static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
323{
1ee6dd77 324 struct s2io_nic *nic = dev->priv;
be3a6b02 325 unsigned long flags;
326
327 spin_lock_irqsave(&nic->tx_lock, flags);
328 if (nic->vlgrp)
329 nic->vlgrp->vlan_devices[vid] = NULL;
330 spin_unlock_irqrestore(&nic->tx_lock, flags);
331}
332
20346722 333/*
1da177e4
LT		 334 * Constants to be programmed into the Xena's registers, to configure
335 * the XAUI.
336 */
337
1da177e4 338#define END_SIGN 0x0
f71e1309 339static const u64 herc_act_dtx_cfg[] = {
541ae68f 340 /* Set address */
e960fc5c 341 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 342 /* Write data */
e960fc5c 343 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 344 /* Set address */
345 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
346 /* Write data */
347 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
348 /* Set address */
e960fc5c 349 0x801205150D440000ULL, 0x801205150D4400E0ULL,
350 /* Write data */
351 0x801205150D440004ULL, 0x801205150D4400E4ULL,
352 /* Set address */
541ae68f 353 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
354 /* Write data */
355 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
356 /* Done */
357 END_SIGN
358};
359
f71e1309 360static const u64 xena_dtx_cfg[] = {
c92ca04b 361 /* Set address */
1da177e4 362 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 363 /* Write data */
364 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
365 /* Set address */
366 0x8001051500000000ULL, 0x80010515000000E0ULL,
367 /* Write data */
368 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
369 /* Set address */
1da177e4 370 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 371 /* Write data */
372 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 373 END_SIGN
374};
375
20346722 376/*
1da177e4
LT		 377 * Constants for Fixing the MacAddress problem seen mostly on
378 * Alpha machines.
379 */
f71e1309 380static const u64 fix_mac[] = {
1da177e4
LT		 381 0x0060000000000000ULL, 0x0060600000000000ULL,
382 0x0040600000000000ULL, 0x0000600000000000ULL,
383 0x0020600000000000ULL, 0x0060600000000000ULL,
384 0x0020600000000000ULL, 0x0060600000000000ULL,
385 0x0020600000000000ULL, 0x0060600000000000ULL,
386 0x0020600000000000ULL, 0x0060600000000000ULL,
387 0x0020600000000000ULL, 0x0060600000000000ULL,
388 0x0020600000000000ULL, 0x0060600000000000ULL,
389 0x0020600000000000ULL, 0x0060600000000000ULL,
390 0x0020600000000000ULL, 0x0060600000000000ULL,
391 0x0020600000000000ULL, 0x0060600000000000ULL,
392 0x0020600000000000ULL, 0x0060600000000000ULL,
393 0x0020600000000000ULL, 0x0000600000000000ULL,
394 0x0040600000000000ULL, 0x0060600000000000ULL,
395 END_SIGN
396};
397
b41477f3
AR		 398MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
399MODULE_LICENSE("GPL");
400MODULE_VERSION(DRV_VERSION);
401
402
1da177e4 403/* Module Loadable parameters. */
b41477f3
AR		 404S2IO_PARM_INT(tx_fifo_num, 1);
405S2IO_PARM_INT(rx_ring_num, 1);
406
407
408S2IO_PARM_INT(rx_ring_mode, 1);
409S2IO_PARM_INT(use_continuous_tx_intrs, 1);
410S2IO_PARM_INT(rmac_pause_time, 0x100);
411S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
412S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
413S2IO_PARM_INT(shared_splits, 0);
414S2IO_PARM_INT(tmac_util_period, 5);
415S2IO_PARM_INT(rmac_util_period, 5);
416S2IO_PARM_INT(bimodal, 0);
417S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 418/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 419S2IO_PARM_INT(rxsync_frequency, 3);
cc6e7c44 420/* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
b41477f3 421S2IO_PARM_INT(intr_type, 0);
7d3d0439 422/* Large receive offload feature */
b41477f3 423S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 424/* Max pkts to be aggregated by LRO at one time. If not specified,
425 * aggregation happens until we hit max IP pkt size(64K)
426 */
b41477f3 427S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 428S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 429
430S2IO_PARM_INT(napi, 1);
431S2IO_PARM_INT(ufo, 0);
926930b2 432S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 433
434static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
435 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
436static unsigned int rx_ring_sz[MAX_RX_RINGS] =
437 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
438static unsigned int rts_frm_len[MAX_RX_RINGS] =
439 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
440
441module_param_array(tx_fifo_len, uint, NULL, 0);
442module_param_array(rx_ring_sz, uint, NULL, 0);
443module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 444
20346722 445/*
1da177e4 446 * S2IO device table.
20346722 447 * This table lists all the devices that this driver supports.
1da177e4
LT		 448 */
449static struct pci_device_id s2io_tbl[] __devinitdata = {
450 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
451 PCI_ANY_ID, PCI_ANY_ID},
452 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
453 PCI_ANY_ID, PCI_ANY_ID},
454 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722 455 PCI_ANY_ID, PCI_ANY_ID},
456 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
457 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 458 {0,}
459};
460
461MODULE_DEVICE_TABLE(pci, s2io_tbl);
462
463static struct pci_driver s2io_driver = {
464 .name = "S2IO",
465 .id_table = s2io_tbl,
466 .probe = s2io_init_nic,
467 .remove = __devexit_p(s2io_rem_nic),
468};
469
470/* A simplifier macro used both by init and free shared_mem Fns(). */
471#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
472
473/**
474 * init_shared_mem - Allocation and Initialization of Memory
475 * @nic: Device private variable.
20346722 476 * Description: The function allocates all the memory areas shared
477 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 478 * Rx descriptors and the statistics block.
479 */
480
481static int init_shared_mem(struct s2io_nic *nic)
482{
483 u32 size;
484 void *tmp_v_addr, *tmp_v_addr_next;
485 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 486 struct RxD_block *pre_rxd_blk = NULL;
372cc597 487 int i, j, blk_cnt;
1da177e4
LT		 488 int lst_size, lst_per_page;
489 struct net_device *dev = nic->dev;
8ae418cf 490 unsigned long tmp;
1ee6dd77 491 struct buffAdd *ba;
1da177e4 492
1ee6dd77 493 struct mac_info *mac_control;
1da177e4
LT		 494 struct config_param *config;
495
496 mac_control = &nic->mac_control;
497 config = &nic->config;
498
499
500 /* Allocation and initialization of TXDLs in FIOFs */
501 size = 0;
502 for (i = 0; i < config->tx_fifo_num; i++) {
503 size += config->tx_cfg[i].fifo_len;
504 }
505 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 506 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 507 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 508 return -EINVAL;
1da177e4
LT		 509 }
510
1ee6dd77 511 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 512 lst_per_page = PAGE_SIZE / lst_size;
513
514 for (i = 0; i < config->tx_fifo_num; i++) {
515 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 516 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
20346722 517 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
518 GFP_KERNEL);
519 if (!mac_control->fifos[i].list_info) {
1da177e4
LT		 520 DBG_PRINT(ERR_DBG,
521 "Malloc failed for list_info\n");
522 return -ENOMEM;
523 }
20346722 524 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 525 }
526 for (i = 0; i < config->tx_fifo_num; i++) {
527 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
528 lst_per_page);
20346722 529 mac_control->fifos[i].tx_curr_put_info.offset = 0;
530 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 531 config->tx_cfg[i].fifo_len - 1;
20346722 532 mac_control->fifos[i].tx_curr_get_info.offset = 0;
533 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 534 config->tx_cfg[i].fifo_len - 1;
20346722 535 mac_control->fifos[i].fifo_no = i;
536 mac_control->fifos[i].nic = nic;
fed5eccd 537 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 538
1da177e4
LT		 539 for (j = 0; j < page_num; j++) {
540 int k = 0;
541 dma_addr_t tmp_p;
542 void *tmp_v;
543 tmp_v = pci_alloc_consistent(nic->pdev,
544 PAGE_SIZE, &tmp_p);
545 if (!tmp_v) {
546 DBG_PRINT(ERR_DBG,
547 "pci_alloc_consistent ");
548 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
549 return -ENOMEM;
550 }
776bd20f 551 /* If we got a zero DMA address(can happen on
552 * certain platforms like PPC), reallocate.
553 * Store virtual address of page we don't want,
554 * to be freed later.
555 */
556 if (!tmp_p) {
557 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 558 DBG_PRINT(INIT_DBG,
776bd20f 559 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 560 DBG_PRINT(INIT_DBG,
6b4d617d 561 "Virtual address %p\n", tmp_v);
776bd20f 562 tmp_v = pci_alloc_consistent(nic->pdev,
563 PAGE_SIZE, &tmp_p);
564 if (!tmp_v) {
565 DBG_PRINT(ERR_DBG,
566 "pci_alloc_consistent ");
567 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
568 return -ENOMEM;
569 }
570 }
1da177e4
LT		 571 while (k < lst_per_page) {
572 int l = (j * lst_per_page) + k;
573 if (l == config->tx_cfg[i].fifo_len)
20346722 574 break;
575 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 576 tmp_v + (k * lst_size);
20346722 577 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 578 tmp_p + (k * lst_size);
579 k++;
580 }
581 }
582 }
1da177e4 583
4384247b 584 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 585 if (!nic->ufo_in_band_v)
586 return -ENOMEM;
587
1da177e4
LT		 588 /* Allocation and initialization of RXDs in Rings */
589 size = 0;
590 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 591 if (config->rx_cfg[i].num_rxd %
592 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 593 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
594 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
595 i);
596 DBG_PRINT(ERR_DBG, "RxDs per Block");
597 return FAILURE;
598 }
599 size += config->rx_cfg[i].num_rxd;
20346722 600 mac_control->rings[i].block_count =
da6971d8
AR		 601 config->rx_cfg[i].num_rxd /
602 (rxd_count[nic->rxd_mode] + 1 );
603 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
604 mac_control->rings[i].block_count;
1da177e4 605 }
da6971d8 606 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 607 size = (size * (sizeof(struct RxD1)));
da6971d8 608 else
1ee6dd77 609 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 610
611 for (i = 0; i < config->rx_ring_num; i++) {
20346722 612 mac_control->rings[i].rx_curr_get_info.block_index = 0;
613 mac_control->rings[i].rx_curr_get_info.offset = 0;
614 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 615 config->rx_cfg[i].num_rxd - 1;
20346722 616 mac_control->rings[i].rx_curr_put_info.block_index = 0;
617 mac_control->rings[i].rx_curr_put_info.offset = 0;
618 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 619 config->rx_cfg[i].num_rxd - 1;
20346722 620 mac_control->rings[i].nic = nic;
621 mac_control->rings[i].ring_no = i;
622
da6971d8
AR		 623 blk_cnt = config->rx_cfg[i].num_rxd /
624 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 625 /* Allocating all the Rx blocks */
626 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 627 struct rx_block_info *rx_blocks;
da6971d8
AR		 628 int l;
629
630 rx_blocks = &mac_control->rings[i].rx_blocks[j];
631 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 632 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
633 &tmp_p_addr);
634 if (tmp_v_addr == NULL) {
635 /*
20346722 636 * In case of failure, free_shared_mem()
637 * is called, which should free any
638 * memory that was alloced till the
1da177e4
LT		 639 * failure happened.
640 */
da6971d8 641 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 642 return -ENOMEM;
643 }
644 memset(tmp_v_addr, 0, size);
da6971d8
AR		 645 rx_blocks->block_virt_addr = tmp_v_addr;
646 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 647 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 648 rxd_count[nic->rxd_mode],
649 GFP_KERNEL);
372cc597
SS		 650 if (!rx_blocks->rxds)
651 return -ENOMEM;
da6971d8
AR		 652 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
653 rx_blocks->rxds[l].virt_addr =
654 rx_blocks->block_virt_addr +
655 (rxd_size[nic->rxd_mode] * l);
656 rx_blocks->rxds[l].dma_addr =
657 rx_blocks->block_dma_addr +
658 (rxd_size[nic->rxd_mode] * l);
659 }
1da177e4
LT		 660 }
661 /* Interlinking all Rx Blocks */
662 for (j = 0; j < blk_cnt; j++) {
20346722 663 tmp_v_addr =
664 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 665 tmp_v_addr_next =
20346722 666 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 667 blk_cnt].block_virt_addr;
20346722 668 tmp_p_addr =
669 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 670 tmp_p_addr_next =
20346722 671 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 672 blk_cnt].block_dma_addr;
673
1ee6dd77 674 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 675 pre_rxd_blk->reserved_2_pNext_RxD_block =
676 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 677 pre_rxd_blk->pNext_RxD_Blk_physical =
678 (u64) tmp_p_addr_next;
679 }
680 }
da6971d8
AR		 681 if (nic->rxd_mode >= RXD_MODE_3A) {
682 /*
683 * Allocation of Storages for buffer addresses in 2BUFF mode
684 * and the buffers as well.
685 */
686 for (i = 0; i < config->rx_ring_num; i++) {
687 blk_cnt = config->rx_cfg[i].num_rxd /
688 (rxd_count[nic->rxd_mode]+ 1);
689 mac_control->rings[i].ba =
1ee6dd77 690 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 691 GFP_KERNEL);
da6971d8 692 if (!mac_control->rings[i].ba)
1da177e4 693 return -ENOMEM;
da6971d8
AR		 694 for (j = 0; j < blk_cnt; j++) {
695 int k = 0;
696 mac_control->rings[i].ba[j] =
1ee6dd77 697 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 698 (rxd_count[nic->rxd_mode] + 1)),
699 GFP_KERNEL);
700 if (!mac_control->rings[i].ba[j])
1da177e4 701 return -ENOMEM;
da6971d8
AR		 702 while (k != rxd_count[nic->rxd_mode]) {
703 ba = &mac_control->rings[i].ba[j][k];
704
705 ba->ba_0_org = (void *) kmalloc
706 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
707 if (!ba->ba_0_org)
708 return -ENOMEM;
709 tmp = (unsigned long)ba->ba_0_org;
710 tmp += ALIGN_SIZE;
711 tmp &= ~((unsigned long) ALIGN_SIZE);
712 ba->ba_0 = (void *) tmp;
713
714 ba->ba_1_org = (void *) kmalloc
715 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
716 if (!ba->ba_1_org)
717 return -ENOMEM;
718 tmp = (unsigned long) ba->ba_1_org;
719 tmp += ALIGN_SIZE;
720 tmp &= ~((unsigned long) ALIGN_SIZE);
721 ba->ba_1 = (void *) tmp;
722 k++;
723 }
1da177e4
LT		 724 }
725 }
726 }
1da177e4
LT		 727
728 /* Allocation and initialization of Statistics block */
1ee6dd77 729 size = sizeof(struct stat_block);
1da177e4
LT		 730 mac_control->stats_mem = pci_alloc_consistent
731 (nic->pdev, size, &mac_control->stats_mem_phy);
732
733 if (!mac_control->stats_mem) {
20346722 734 /*
735 * In case of failure, free_shared_mem() is called, which
736 * should free any memory that was alloced till the
1da177e4
LT		 737 * failure happened.
738 */
739 return -ENOMEM;
740 }
741 mac_control->stats_mem_sz = size;
742
743 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 744 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 745 memset(tmp_v_addr, 0, size);
1da177e4
LT		 746 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
747 (unsigned long long) tmp_p_addr);
748
749 return SUCCESS;
750}
751
20346722 752/**
753 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 754 * @nic: Device private variable.
755 * Description: This function is to free all memory locations allocated by
756 * the init_shared_mem() function and return it to the kernel.
757 */
758
759static void free_shared_mem(struct s2io_nic *nic)
760{
761 int i, j, blk_cnt, size;
762 void *tmp_v_addr;
763 dma_addr_t tmp_p_addr;
1ee6dd77 764 struct mac_info *mac_control;
1da177e4
LT		 765 struct config_param *config;
766 int lst_size, lst_per_page;
776bd20f 767 struct net_device *dev = nic->dev;
1da177e4
LT		 768
769 if (!nic)
770 return;
771
772 mac_control = &nic->mac_control;
773 config = &nic->config;
774
1ee6dd77 775 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 776 lst_per_page = PAGE_SIZE / lst_size;
777
778 for (i = 0; i < config->tx_fifo_num; i++) {
779 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
780 lst_per_page);
781 for (j = 0; j < page_num; j++) {
782 int mem_blks = (j * lst_per_page);
776bd20f 783 if (!mac_control->fifos[i].list_info)
6aa20a22 784 return;
776bd20f 785 if (!mac_control->fifos[i].list_info[mem_blks].
786 list_virt_addr)
1da177e4
LT		 787 break;
788 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722 789 mac_control->fifos[i].
790 list_info[mem_blks].
1da177e4 791 list_virt_addr,
20346722 792 mac_control->fifos[i].
793 list_info[mem_blks].
1da177e4
LT		 794 list_phy_addr);
795 }
776bd20f 796 /* If we got a zero DMA address during allocation,
797 * free the page now
798 */
799 if (mac_control->zerodma_virt_addr) {
800 pci_free_consistent(nic->pdev, PAGE_SIZE,
801 mac_control->zerodma_virt_addr,
802 (dma_addr_t)0);
6aa20a22 803 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 804 "%s: Freeing TxDL with zero DMA addr. ",
805 dev->name);
806 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
807 mac_control->zerodma_virt_addr);
776bd20f 808 }
20346722 809 kfree(mac_control->fifos[i].list_info);
1da177e4
LT		 810 }
811
1da177e4 812 size = SIZE_OF_BLOCK;
1da177e4 813 for (i = 0; i < config->rx_ring_num; i++) {
20346722 814 blk_cnt = mac_control->rings[i].block_count;
1da177e4 815 for (j = 0; j < blk_cnt; j++) {
20346722 816 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
817 block_virt_addr;
818 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
819 block_dma_addr;
1da177e4
LT		 820 if (tmp_v_addr == NULL)
821 break;
822 pci_free_consistent(nic->pdev, size,
823 tmp_v_addr, tmp_p_addr);
da6971d8 824 kfree(mac_control->rings[i].rx_blocks[j].rxds);
1da177e4
LT		 825 }
826 }
827
da6971d8
AR		 828 if (nic->rxd_mode >= RXD_MODE_3A) {
829 /* Freeing buffer storage addresses in 2BUFF mode. */
830 for (i = 0; i < config->rx_ring_num; i++) {
831 blk_cnt = config->rx_cfg[i].num_rxd /
832 (rxd_count[nic->rxd_mode] + 1);
833 for (j = 0; j < blk_cnt; j++) {
834 int k = 0;
835 if (!mac_control->rings[i].ba[j])
836 continue;
837 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 838 struct buffAdd *ba =
da6971d8
AR		 839 &mac_control->rings[i].ba[j][k];
840 kfree(ba->ba_0_org);
841 kfree(ba->ba_1_org);
842 k++;
843 }
844 kfree(mac_control->rings[i].ba[j]);
1da177e4 845 }
da6971d8 846 kfree(mac_control->rings[i].ba);
1da177e4 847 }
1da177e4 848 }
1da177e4
LT		 849
850 if (mac_control->stats_mem) {
851 pci_free_consistent(nic->pdev,
852 mac_control->stats_mem_sz,
853 mac_control->stats_mem,
854 mac_control->stats_mem_phy);
855 }
fed5eccd
AR		 856 if (nic->ufo_in_band_v)
857 kfree(nic->ufo_in_band_v);
1da177e4
LT		 858}
859
541ae68f 860/**
861 * s2io_verify_pci_mode -
862 */
863
1ee6dd77 864static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 865{
1ee6dd77 866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 867 register u64 val64 = 0;
868 int mode;
869
870 val64 = readq(&bar0->pci_mode);
871 mode = (u8)GET_PCI_MODE(val64);
872
873 if ( val64 & PCI_MODE_UNKNOWN_MODE)
874 return -1; /* Unknown PCI mode */
875 return mode;
876}
877
c92ca04b
AR		 878#define NEC_VENID 0x1033
879#define NEC_DEVID 0x0125
880static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
881{
882 struct pci_dev *tdev = NULL;
26d36b64
AC		 883 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
884 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 885 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 886 pci_dev_put(tdev);
c92ca04b
AR		 887 return 1;
888 }
889 }
890 return 0;
891}
541ae68f 892
7b32a312 893static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 894/**
895 * s2io_print_pci_mode -
896 */
1ee6dd77 897static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 898{
1ee6dd77 899 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 900 register u64 val64 = 0;
901 int mode;
902 struct config_param *config = &nic->config;
903
904 val64 = readq(&bar0->pci_mode);
905 mode = (u8)GET_PCI_MODE(val64);
906
907 if ( val64 & PCI_MODE_UNKNOWN_MODE)
908 return -1; /* Unknown PCI mode */
909
c92ca04b
AR		 910 config->bus_speed = bus_speed[mode];
911
912 if (s2io_on_nec_bridge(nic->pdev)) {
913 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
914 nic->dev->name);
915 return mode;
916 }
917
541ae68f 918 if (val64 & PCI_MODE_32_BITS) {
919 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
920 } else {
921 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
922 }
923
924 switch(mode) {
925 case PCI_MODE_PCI_33:
926 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f 927 break;
928 case PCI_MODE_PCI_66:
929 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f 930 break;
931 case PCI_MODE_PCIX_M1_66:
932 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f 933 break;
934 case PCI_MODE_PCIX_M1_100:
935 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f 936 break;
937 case PCI_MODE_PCIX_M1_133:
938 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f 939 break;
940 case PCI_MODE_PCIX_M2_66:
941 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f 942 break;
943 case PCI_MODE_PCIX_M2_100:
944 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f 945 break;
946 case PCI_MODE_PCIX_M2_133:
947 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f 948 break;
949 default:
950 return -1; /* Unsupported bus speed */
951 }
952
953 return mode;
954}
955
20346722 956/**
957 * init_nic - Initialization of hardware
1da177e4 958 * @nic: device peivate variable
20346722 959 * Description: The function sequentially configures every block
960 * of the H/W from their reset values.
961 * Return Value: SUCCESS on success and
1da177e4
LT		 962 * '-1' on failure (endian settings incorrect).
963 */
964
965static int init_nic(struct s2io_nic *nic)
966{
1ee6dd77 967 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 968 struct net_device *dev = nic->dev;
969 register u64 val64 = 0;
970 void __iomem *add;
971 u32 time;
972 int i, j;
1ee6dd77 973 struct mac_info *mac_control;
1da177e4 974 struct config_param *config;
c92ca04b 975 int dtx_cnt = 0;
1da177e4 976 unsigned long long mem_share;
20346722 977 int mem_size;
1da177e4
LT		 978
979 mac_control = &nic->mac_control;
980 config = &nic->config;
981
5e25b9dd 982 /* to set the swapper controle on the card */
20346722 983 if(s2io_set_swapper(nic)) {
1da177e4
LT		 984 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
985 return -1;
986 }
987
541ae68f 988 /*
989 * Herc requires EOI to be removed from reset before XGXS, so..
990 */
991 if (nic->device_type & XFRAME_II_DEVICE) {
992 val64 = 0xA500000000ULL;
993 writeq(val64, &bar0->sw_reset);
994 msleep(500);
995 val64 = readq(&bar0->sw_reset);
996 }
997
1da177e4
LT		 998 /* Remove XGXS from reset state */
999 val64 = 0;
1000 writeq(val64, &bar0->sw_reset);
1da177e4 1001 msleep(500);
20346722 1002 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 1003
1004 /* Enable Receiving broadcasts */
1005 add = &bar0->mac_cfg;
1006 val64 = readq(&bar0->mac_cfg);
1007 val64 |= MAC_RMAC_BCAST_ENABLE;
1008 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1009 writel((u32) val64, add);
1010 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1011 writel((u32) (val64 >> 32), (add + 4));
1012
1013 /* Read registers in all blocks */
1014 val64 = readq(&bar0->mac_int_mask);
1015 val64 = readq(&bar0->mc_int_mask);
1016 val64 = readq(&bar0->xgxs_int_mask);
1017
1018 /* Set MTU */
1019 val64 = dev->mtu;
1020 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1021
541ae68f 1022 if (nic->device_type & XFRAME_II_DEVICE) {
1023 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1024 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1025 &bar0->dtx_control, UF);
541ae68f 1026 if (dtx_cnt & 0x1)
1027 msleep(1); /* Necessary!! */
1da177e4
LT		 1028 dtx_cnt++;
1029 }
541ae68f 1030 } else {
c92ca04b
AR		 1031 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1032 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1033 &bar0->dtx_control, UF);
1034 val64 = readq(&bar0->dtx_control);
1035 dtx_cnt++;
1da177e4
LT		 1036 }
1037 }
1038
1039 /* Tx DMA Initialization */
1040 val64 = 0;
1041 writeq(val64, &bar0->tx_fifo_partition_0);
1042 writeq(val64, &bar0->tx_fifo_partition_1);
1043 writeq(val64, &bar0->tx_fifo_partition_2);
1044 writeq(val64, &bar0->tx_fifo_partition_3);
1045
1046
1047 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1048 val64 |=
1049 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1050 13) | vBIT(config->tx_cfg[i].fifo_priority,
1051 ((i * 32) + 5), 3);
1052
1053 if (i == (config->tx_fifo_num - 1)) {
1054 if (i % 2 == 0)
1055 i++;
1056 }
1057
1058 switch (i) {
1059 case 1:
1060 writeq(val64, &bar0->tx_fifo_partition_0);
1061 val64 = 0;
1062 break;
1063 case 3:
1064 writeq(val64, &bar0->tx_fifo_partition_1);
1065 val64 = 0;
1066 break;
1067 case 5:
1068 writeq(val64, &bar0->tx_fifo_partition_2);
1069 val64 = 0;
1070 break;
1071 case 7:
1072 writeq(val64, &bar0->tx_fifo_partition_3);
1073 break;
1074 }
1075 }
1076
5e25b9dd 1077 /*
1078 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1079 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1080 */
541ae68f 1081 if ((nic->device_type == XFRAME_I_DEVICE) &&
1082 (get_xena_rev_id(nic->pdev) < 4))
5e25b9dd 1083 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1084
1da177e4
LT		 1085 val64 = readq(&bar0->tx_fifo_partition_0);
1086 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1087 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1088
20346722 1089 /*
1090 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1091 * integrity checking.
1092 */
1093 val64 = readq(&bar0->tx_pa_cfg);
1094 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1095 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1096 writeq(val64, &bar0->tx_pa_cfg);
1097
1098 /* Rx DMA intialization. */
1099 val64 = 0;
1100 for (i = 0; i < config->rx_ring_num; i++) {
1101 val64 |=
1102 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1103 3);
1104 }
1105 writeq(val64, &bar0->rx_queue_priority);
1106
20346722 1107 /*
1108 * Allocating equal share of memory to all the
1da177e4
LT		 1109 * configured Rings.
1110 */
1111 val64 = 0;
541ae68f 1112 if (nic->device_type & XFRAME_II_DEVICE)
1113 mem_size = 32;
1114 else
1115 mem_size = 64;
1116
1da177e4
LT		 1117 for (i = 0; i < config->rx_ring_num; i++) {
1118 switch (i) {
1119 case 0:
20346722 1120 mem_share = (mem_size / config->rx_ring_num +
1121 mem_size % config->rx_ring_num);
1da177e4
LT		 1122 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1123 continue;
1124 case 1:
20346722 1125 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1126 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1127 continue;
1128 case 2:
20346722 1129 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1130 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1131 continue;
1132 case 3:
20346722 1133 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1134 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1135 continue;
1136 case 4:
20346722 1137 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1138 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1139 continue;
1140 case 5:
20346722 1141 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1142 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1143 continue;
1144 case 6:
20346722 1145 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1146 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1147 continue;
1148 case 7:
20346722 1149 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1150 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1151 continue;
1152 }
1153 }
1154 writeq(val64, &bar0->rx_queue_cfg);
1155
20346722 1156 /*
5e25b9dd 1157 * Filling Tx round robin registers
1158 * as per the number of FIFOs
1da177e4 1159 */
5e25b9dd 1160 switch (config->tx_fifo_num) {
1161 case 1:
1162 val64 = 0x0000000000000000ULL;
1163 writeq(val64, &bar0->tx_w_round_robin_0);
1164 writeq(val64, &bar0->tx_w_round_robin_1);
1165 writeq(val64, &bar0->tx_w_round_robin_2);
1166 writeq(val64, &bar0->tx_w_round_robin_3);
1167 writeq(val64, &bar0->tx_w_round_robin_4);
1168 break;
1169 case 2:
1170 val64 = 0x0000010000010000ULL;
1171 writeq(val64, &bar0->tx_w_round_robin_0);
1172 val64 = 0x0100000100000100ULL;
1173 writeq(val64, &bar0->tx_w_round_robin_1);
1174 val64 = 0x0001000001000001ULL;
1175 writeq(val64, &bar0->tx_w_round_robin_2);
1176 val64 = 0x0000010000010000ULL;
1177 writeq(val64, &bar0->tx_w_round_robin_3);
1178 val64 = 0x0100000000000000ULL;
1179 writeq(val64, &bar0->tx_w_round_robin_4);
1180 break;
1181 case 3:
1182 val64 = 0x0001000102000001ULL;
1183 writeq(val64, &bar0->tx_w_round_robin_0);
1184 val64 = 0x0001020000010001ULL;
1185 writeq(val64, &bar0->tx_w_round_robin_1);
1186 val64 = 0x0200000100010200ULL;
1187 writeq(val64, &bar0->tx_w_round_robin_2);
1188 val64 = 0x0001000102000001ULL;
1189 writeq(val64, &bar0->tx_w_round_robin_3);
1190 val64 = 0x0001020000000000ULL;
1191 writeq(val64, &bar0->tx_w_round_robin_4);
1192 break;
1193 case 4:
1194 val64 = 0x0001020300010200ULL;
1195 writeq(val64, &bar0->tx_w_round_robin_0);
1196 val64 = 0x0100000102030001ULL;
1197 writeq(val64, &bar0->tx_w_round_robin_1);
1198 val64 = 0x0200010000010203ULL;
1199 writeq(val64, &bar0->tx_w_round_robin_2);
1200 val64 = 0x0001020001000001ULL;
1201 writeq(val64, &bar0->tx_w_round_robin_3);
1202 val64 = 0x0203000100000000ULL;
1203 writeq(val64, &bar0->tx_w_round_robin_4);
1204 break;
1205 case 5:
1206 val64 = 0x0001000203000102ULL;
1207 writeq(val64, &bar0->tx_w_round_robin_0);
1208 val64 = 0x0001020001030004ULL;
1209 writeq(val64, &bar0->tx_w_round_robin_1);
1210 val64 = 0x0001000203000102ULL;
1211 writeq(val64, &bar0->tx_w_round_robin_2);
1212 val64 = 0x0001020001030004ULL;
1213 writeq(val64, &bar0->tx_w_round_robin_3);
1214 val64 = 0x0001000000000000ULL;
1215 writeq(val64, &bar0->tx_w_round_robin_4);
1216 break;
1217 case 6:
1218 val64 = 0x0001020304000102ULL;
1219 writeq(val64, &bar0->tx_w_round_robin_0);
1220 val64 = 0x0304050001020001ULL;
1221 writeq(val64, &bar0->tx_w_round_robin_1);
1222 val64 = 0x0203000100000102ULL;
1223 writeq(val64, &bar0->tx_w_round_robin_2);
1224 val64 = 0x0304000102030405ULL;
1225 writeq(val64, &bar0->tx_w_round_robin_3);
1226 val64 = 0x0001000200000000ULL;
1227 writeq(val64, &bar0->tx_w_round_robin_4);
1228 break;
1229 case 7:
1230 val64 = 0x0001020001020300ULL;
1231 writeq(val64, &bar0->tx_w_round_robin_0);
1232 val64 = 0x0102030400010203ULL;
1233 writeq(val64, &bar0->tx_w_round_robin_1);
1234 val64 = 0x0405060001020001ULL;
1235 writeq(val64, &bar0->tx_w_round_robin_2);
1236 val64 = 0x0304050000010200ULL;
1237 writeq(val64, &bar0->tx_w_round_robin_3);
1238 val64 = 0x0102030000000000ULL;
1239 writeq(val64, &bar0->tx_w_round_robin_4);
1240 break;
1241 case 8:
1242 val64 = 0x0001020300040105ULL;
1243 writeq(val64, &bar0->tx_w_round_robin_0);
1244 val64 = 0x0200030106000204ULL;
1245 writeq(val64, &bar0->tx_w_round_robin_1);
1246 val64 = 0x0103000502010007ULL;
1247 writeq(val64, &bar0->tx_w_round_robin_2);
1248 val64 = 0x0304010002060500ULL;
1249 writeq(val64, &bar0->tx_w_round_robin_3);
1250 val64 = 0x0103020400000000ULL;
1251 writeq(val64, &bar0->tx_w_round_robin_4);
1252 break;
1253 }
1254
b41477f3 1255 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1256 val64 = readq(&bar0->tx_fifo_partition_0);
1257 val64 |= (TX_FIFO_PARTITION_EN);
1258 writeq(val64, &bar0->tx_fifo_partition_0);
1259
5e25b9dd 1260 /* Filling the Rx round robin registers as per the
1261 * number of Rings and steering based on QoS.
1262 */
1263 switch (config->rx_ring_num) {
1264 case 1:
1265 val64 = 0x8080808080808080ULL;
1266 writeq(val64, &bar0->rts_qos_steering);
1267 break;
1268 case 2:
1269 val64 = 0x0000010000010000ULL;
1270 writeq(val64, &bar0->rx_w_round_robin_0);
1271 val64 = 0x0100000100000100ULL;
1272 writeq(val64, &bar0->rx_w_round_robin_1);
1273 val64 = 0x0001000001000001ULL;
1274 writeq(val64, &bar0->rx_w_round_robin_2);
1275 val64 = 0x0000010000010000ULL;
1276 writeq(val64, &bar0->rx_w_round_robin_3);
1277 val64 = 0x0100000000000000ULL;
1278 writeq(val64, &bar0->rx_w_round_robin_4);
1279
1280 val64 = 0x8080808040404040ULL;
1281 writeq(val64, &bar0->rts_qos_steering);
1282 break;
1283 case 3:
1284 val64 = 0x0001000102000001ULL;
1285 writeq(val64, &bar0->rx_w_round_robin_0);
1286 val64 = 0x0001020000010001ULL;
1287 writeq(val64, &bar0->rx_w_round_robin_1);
1288 val64 = 0x0200000100010200ULL;
1289 writeq(val64, &bar0->rx_w_round_robin_2);
1290 val64 = 0x0001000102000001ULL;
1291 writeq(val64, &bar0->rx_w_round_robin_3);
1292 val64 = 0x0001020000000000ULL;
1293 writeq(val64, &bar0->rx_w_round_robin_4);
1294
1295 val64 = 0x8080804040402020ULL;
1296 writeq(val64, &bar0->rts_qos_steering);
1297 break;
1298 case 4:
1299 val64 = 0x0001020300010200ULL;
1300 writeq(val64, &bar0->rx_w_round_robin_0);
1301 val64 = 0x0100000102030001ULL;
1302 writeq(val64, &bar0->rx_w_round_robin_1);
1303 val64 = 0x0200010000010203ULL;
1304 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1305 val64 = 0x0001020001000001ULL;
5e25b9dd 1306 writeq(val64, &bar0->rx_w_round_robin_3);
1307 val64 = 0x0203000100000000ULL;
1308 writeq(val64, &bar0->rx_w_round_robin_4);
1309
1310 val64 = 0x8080404020201010ULL;
1311 writeq(val64, &bar0->rts_qos_steering);
1312 break;
1313 case 5:
1314 val64 = 0x0001000203000102ULL;
1315 writeq(val64, &bar0->rx_w_round_robin_0);
1316 val64 = 0x0001020001030004ULL;
1317 writeq(val64, &bar0->rx_w_round_robin_1);
1318 val64 = 0x0001000203000102ULL;
1319 writeq(val64, &bar0->rx_w_round_robin_2);
1320 val64 = 0x0001020001030004ULL;
1321 writeq(val64, &bar0->rx_w_round_robin_3);
1322 val64 = 0x0001000000000000ULL;
1323 writeq(val64, &bar0->rx_w_round_robin_4);
1324
1325 val64 = 0x8080404020201008ULL;
1326 writeq(val64, &bar0->rts_qos_steering);
1327 break;
1328 case 6:
1329 val64 = 0x0001020304000102ULL;
1330 writeq(val64, &bar0->rx_w_round_robin_0);
1331 val64 = 0x0304050001020001ULL;
1332 writeq(val64, &bar0->rx_w_round_robin_1);
1333 val64 = 0x0203000100000102ULL;
1334 writeq(val64, &bar0->rx_w_round_robin_2);
1335 val64 = 0x0304000102030405ULL;
1336 writeq(val64, &bar0->rx_w_round_robin_3);
1337 val64 = 0x0001000200000000ULL;
1338 writeq(val64, &bar0->rx_w_round_robin_4);
1339
1340 val64 = 0x8080404020100804ULL;
1341 writeq(val64, &bar0->rts_qos_steering);
1342 break;
1343 case 7:
1344 val64 = 0x0001020001020300ULL;
1345 writeq(val64, &bar0->rx_w_round_robin_0);
1346 val64 = 0x0102030400010203ULL;
1347 writeq(val64, &bar0->rx_w_round_robin_1);
1348 val64 = 0x0405060001020001ULL;
1349 writeq(val64, &bar0->rx_w_round_robin_2);
1350 val64 = 0x0304050000010200ULL;
1351 writeq(val64, &bar0->rx_w_round_robin_3);
1352 val64 = 0x0102030000000000ULL;
1353 writeq(val64, &bar0->rx_w_round_robin_4);
1354
1355 val64 = 0x8080402010080402ULL;
1356 writeq(val64, &bar0->rts_qos_steering);
1357 break;
1358 case 8:
1359 val64 = 0x0001020300040105ULL;
1360 writeq(val64, &bar0->rx_w_round_robin_0);
1361 val64 = 0x0200030106000204ULL;
1362 writeq(val64, &bar0->rx_w_round_robin_1);
1363 val64 = 0x0103000502010007ULL;
1364 writeq(val64, &bar0->rx_w_round_robin_2);
1365 val64 = 0x0304010002060500ULL;
1366 writeq(val64, &bar0->rx_w_round_robin_3);
1367 val64 = 0x0103020400000000ULL;
1368 writeq(val64, &bar0->rx_w_round_robin_4);
1369
1370 val64 = 0x8040201008040201ULL;
1371 writeq(val64, &bar0->rts_qos_steering);
1372 break;
1373 }
1da177e4
LT		 1374
1375 /* UDP Fix */
1376 val64 = 0;
20346722 1377 for (i = 0; i < 8; i++)
1da177e4
LT		 1378 writeq(val64, &bar0->rts_frm_len_n[i]);
1379
5e25b9dd 1380 /* Set the default rts frame length for the rings configured */
1381 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1382 for (i = 0 ; i < config->rx_ring_num ; i++)
1383 writeq(val64, &bar0->rts_frm_len_n[i]);
1384
1385 /* Set the frame length for the configured rings
1386 * desired by the user
1387 */
1388 for (i = 0; i < config->rx_ring_num; i++) {
1389 /* If rts_frm_len[i] == 0 then it is assumed that user not
1390 * specified frame length steering.
1391 * If the user provides the frame length then program
1392 * the rts_frm_len register for those values or else
1393 * leave it as it is.
1394 */
1395 if (rts_frm_len[i] != 0) {
1396 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1397 &bar0->rts_frm_len_n[i]);
1398 }
1399 }
926930b2 1400
9fc93a41
SS		 1401 /* Disable differentiated services steering logic */
1402 for (i = 0; i < 64; i++) {
1403 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1404 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1405 dev->name);
1406 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1407 return FAILURE;
1408 }
1409 }
1410
20346722 1411 /* Program statistics memory */
1da177e4 1412 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1413
541ae68f 1414 if (nic->device_type == XFRAME_II_DEVICE) {
1415 val64 = STAT_BC(0x320);
1416 writeq(val64, &bar0->stat_byte_cnt);
1417 }
1418
20346722 1419 /*
1da177e4
LT		 1420 * Initializing the sampling rate for the device to calculate the
1421 * bandwidth utilization.
1422 */
1423 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1424 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1425 writeq(val64, &bar0->mac_link_util);
1426
1427
20346722 1428 /*
1429 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1430 * Scheme.
1431 */
20346722 1432 /*
1433 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1434 * 250 interrupts per sec. Continuous interrupts are enabled
1435 * by default.
1436 */
541ae68f 1437 if (nic->device_type == XFRAME_II_DEVICE) {
1438 int count = (nic->config.bus_speed * 125)/2;
1439 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1440 } else {
1441
1442 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1443 }
1444 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1445 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1446 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f 1447 if (use_continuous_tx_intrs)
1448 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1449 writeq(val64, &bar0->tti_data1_mem);
1450
1451 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1452 TTI_DATA2_MEM_TX_UFC_B(0x20) |
19a60522 1453 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1454 writeq(val64, &bar0->tti_data2_mem);
1455
1456 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1457 writeq(val64, &bar0->tti_command_mem);
1458
20346722 1459 /*
1da177e4
LT		 1460 * Once the operation completes, the Strobe bit of the command
1461 * register will be reset. We poll for this particular condition
1462 * We wait for a maximum of 500ms for the operation to complete,
1463 * if it's not complete by then we return error.
1464 */
1465 time = 0;
1466 while (TRUE) {
1467 val64 = readq(&bar0->tti_command_mem);
1468 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1469 break;
1470 }
1471 if (time > 10) {
1472 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1473 dev->name);
1474 return -1;
1475 }
1476 msleep(50);
1477 time++;
1478 }
1479
b6e3f982 1480 if (nic->config.bimodal) {
1481 int k = 0;
1482 for (k = 0; k < config->rx_ring_num; k++) {
1483 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1484 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1485 writeq(val64, &bar0->tti_command_mem);
541ae68f 1486
541ae68f 1487 /*
b6e3f982 1488 * Once the operation completes, the Strobe bit of the command
1489 * register will be reset. We poll for this particular condition
1490 * We wait for a maximum of 500ms for the operation to complete,
1491 * if it's not complete by then we return error.
1492 */
1493 time = 0;
1494 while (TRUE) {
1495 val64 = readq(&bar0->tti_command_mem);
1496 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1497 break;
1498 }
1499 if (time > 10) {
1500 DBG_PRINT(ERR_DBG,
1501 "%s: TTI init Failed\n",
1502 dev->name);
1503 return -1;
1504 }
1505 time++;
1506 msleep(50);
1507 }
1508 }
541ae68f 1509 } else {
1da177e4 1510
b6e3f982 1511 /* RTI Initialization */
1512 if (nic->device_type == XFRAME_II_DEVICE) {
1513 /*
1514 * Programmed to generate Apprx 500 Intrs per
1515 * second
1516 */
1517 int count = (nic->config.bus_speed * 125)/4;
1518 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1519 } else {
1520 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1521 }
1522 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1523 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1524 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1525
b6e3f982 1526 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1527
b6e3f982 1528 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1529 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1530 if (nic->intr_type == MSI_X)
1531 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1532 RTI_DATA2_MEM_RX_UFC_D(0x40));
1533 else
1534 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1535 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1536 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1537
b6e3f982 1538 for (i = 0; i < config->rx_ring_num; i++) {
1539 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1540 | RTI_CMD_MEM_OFFSET(i);
1541 writeq(val64, &bar0->rti_command_mem);
1542
1543 /*
1544 * Once the operation completes, the Strobe bit of the
1545 * command register will be reset. We poll for this
1546 * particular condition. We wait for a maximum of 500ms
1547 * for the operation to complete, if it's not complete
1548 * by then we return error.
1549 */
1550 time = 0;
1551 while (TRUE) {
1552 val64 = readq(&bar0->rti_command_mem);
1553 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1554 break;
1555 }
1556 if (time > 10) {
1557 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1558 dev->name);
1559 return -1;
1560 }
1561 time++;
1562 msleep(50);
1563 }
1da177e4 1564 }
1da177e4
LT		 1565 }
1566
20346722 1567 /*
1568 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1569 * the 8 Queues on Rx side.
1570 */
1571 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1572 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1573
1574 /* Disable RMAC PAD STRIPPING */
509a2671 1575 add = &bar0->mac_cfg;
1da177e4
LT		 1576 val64 = readq(&bar0->mac_cfg);
1577 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1578 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1579 writel((u32) (val64), add);
1580 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1581 writel((u32) (val64 >> 32), (add + 4));
1582 val64 = readq(&bar0->mac_cfg);
1583
7d3d0439
RA		 1584 /* Enable FCS stripping by adapter */
1585 add = &bar0->mac_cfg;
1586 val64 = readq(&bar0->mac_cfg);
1587 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1588 if (nic->device_type == XFRAME_II_DEVICE)
1589 writeq(val64, &bar0->mac_cfg);
1590 else {
1591 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1592 writel((u32) (val64), add);
1593 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1594 writel((u32) (val64 >> 32), (add + 4));
1595 }
1596
20346722 1597 /*
1598 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1599 * generated by xena.
1600 */
1601 val64 = readq(&bar0->rmac_pause_cfg);
1602 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1603 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1604 writeq(val64, &bar0->rmac_pause_cfg);
1605
20346722 1606 /*
1da177e4
LT		 1607 * Set the Threshold Limit for Generating the pause frame
1608 * If the amount of data in any Queue exceeds ratio of
1609 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1610 * pause frame is generated
1611 */
1612 val64 = 0;
1613 for (i = 0; i < 4; i++) {
1614 val64 |=
1615 (((u64) 0xFF00 | nic->mac_control.
1616 mc_pause_threshold_q0q3)
1617 << (i * 2 * 8));
1618 }
1619 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1620
1621 val64 = 0;
1622 for (i = 0; i < 4; i++) {
1623 val64 |=
1624 (((u64) 0xFF00 | nic->mac_control.
1625 mc_pause_threshold_q4q7)
1626 << (i * 2 * 8));
1627 }
1628 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1629
20346722 1630 /*
1631 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1632 * exceeded the limit pointed by shared_splits
1633 */
1634 val64 = readq(&bar0->pic_control);
1635 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1636 writeq(val64, &bar0->pic_control);
1637
863c11a9
AR		 1638 if (nic->config.bus_speed == 266) {
1639 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1640 writeq(0x0, &bar0->read_retry_delay);
1641 writeq(0x0, &bar0->write_retry_delay);
1642 }
1643
541ae68f 1644 /*
1645 * Programming the Herc to split every write transaction
1646 * that does not start on an ADB to reduce disconnects.
1647 */
1648 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1649 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1650 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1651 writeq(val64, &bar0->misc_control);
1652 val64 = readq(&bar0->pic_control2);
1653 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1654 writeq(val64, &bar0->pic_control2);
541ae68f 1655 }
c92ca04b
AR		 1656 if (strstr(nic->product_name, "CX4")) {
1657 val64 = TMAC_AVG_IPG(0x17);
1658 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1659 }
1660
1da177e4
LT		 1661 return SUCCESS;
1662}
a371a07d 1663#define LINK_UP_DOWN_INTERRUPT 1
1664#define MAC_RMAC_ERR_TIMER 2
1665
1ee6dd77 1666static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1667{
cc6e7c44
RA		 1668 if (nic->intr_type != INTA)
1669 return MAC_RMAC_ERR_TIMER;
a371a07d 1670 if (nic->device_type == XFRAME_II_DEVICE)
1671 return LINK_UP_DOWN_INTERRUPT;
1672 else
1673 return MAC_RMAC_ERR_TIMER;
1674}
1da177e4 1675
20346722 1676/**
1677 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1678 * @nic: device private variable,
1679 * @mask: A mask indicating which Intr block must be modified and,
1680 * @flag: A flag indicating whether to enable or disable the Intrs.
1681 * Description: This function will either disable or enable the interrupts
20346722 1682 * depending on the flag argument. The mask argument can be used to
1683 * enable/disable any Intr block.
1da177e4
LT		 1684 * Return Value: NONE.
1685 */
1686
1687static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1688{
1ee6dd77 1689 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1690 register u64 val64 = 0, temp64 = 0;
1691
1692 /* Top level interrupt classification */
1693 /* PIC Interrupts */
1694 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1695 /* Enable PIC Intrs in the general intr mask register */
a113ae06 1696 val64 = TXPIC_INT_M;
1da177e4
LT		 1697 if (flag == ENABLE_INTRS) {
1698 temp64 = readq(&bar0->general_int_mask);
1699 temp64 &= ~((u64) val64);
1700 writeq(temp64, &bar0->general_int_mask);
20346722 1701 /*
a371a07d 1702 * If Hercules adapter enable GPIO otherwise
b41477f3 1703 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 1704 * interrupts for now.
1705 * TODO
1da177e4 1706 */
a371a07d 1707 if (s2io_link_fault_indication(nic) ==
1708 LINK_UP_DOWN_INTERRUPT ) {
1709 temp64 = readq(&bar0->pic_int_mask);
1710 temp64 &= ~((u64) PIC_INT_GPIO);
1711 writeq(temp64, &bar0->pic_int_mask);
1712 temp64 = readq(&bar0->gpio_int_mask);
1713 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1714 writeq(temp64, &bar0->gpio_int_mask);
1715 } else {
1716 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1717 }
20346722 1718 /*
1da177e4
LT		 1719 * No MSI Support is available presently, so TTI and
1720 * RTI interrupts are also disabled.
1721 */
1722 } else if (flag == DISABLE_INTRS) {
20346722 1723 /*
1724 * Disable PIC Intrs in the general
1725 * intr mask register
1da177e4
LT		 1726 */
1727 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1728 temp64 = readq(&bar0->general_int_mask);
1729 val64 |= temp64;
1730 writeq(val64, &bar0->general_int_mask);
1731 }
1732 }
1733
1da177e4
LT		 1734 /* MAC Interrupts */
1735 /* Enabling/Disabling MAC interrupts */
1736 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1737 val64 = TXMAC_INT_M | RXMAC_INT_M;
1738 if (flag == ENABLE_INTRS) {
1739 temp64 = readq(&bar0->general_int_mask);
1740 temp64 &= ~((u64) val64);
1741 writeq(temp64, &bar0->general_int_mask);
20346722 1742 /*
1743 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1744 * TODO
1745 */
1da177e4 1746 } else if (flag == DISABLE_INTRS) {
20346722 1747 /*
1748 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1749 */
1750 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1751 writeq(DISABLE_ALL_INTRS,
1752 &bar0->mac_rmac_err_mask);
1753
1754 temp64 = readq(&bar0->general_int_mask);
1755 val64 |= temp64;
1756 writeq(val64, &bar0->general_int_mask);
1757 }
1758 }
1759
1da177e4
LT		 1760 /* Tx traffic interrupts */
1761 if (mask & TX_TRAFFIC_INTR) {
1762 val64 = TXTRAFFIC_INT_M;
1763 if (flag == ENABLE_INTRS) {
1764 temp64 = readq(&bar0->general_int_mask);
1765 temp64 &= ~((u64) val64);
1766 writeq(temp64, &bar0->general_int_mask);
20346722 1767 /*
1da177e4 1768 * Enable all the Tx side interrupts
20346722 1769 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1770 */
1771 writeq(0x0, &bar0->tx_traffic_mask);
1772 } else if (flag == DISABLE_INTRS) {
20346722 1773 /*
1774 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1775 * register.
1776 */
1777 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1778 temp64 = readq(&bar0->general_int_mask);
1779 val64 |= temp64;
1780 writeq(val64, &bar0->general_int_mask);
1781 }
1782 }
1783
1784 /* Rx traffic interrupts */
1785 if (mask & RX_TRAFFIC_INTR) {
1786 val64 = RXTRAFFIC_INT_M;
1787 if (flag == ENABLE_INTRS) {
1788 temp64 = readq(&bar0->general_int_mask);
1789 temp64 &= ~((u64) val64);
1790 writeq(temp64, &bar0->general_int_mask);
1791 /* writing 0 Enables all 8 RX interrupt levels */
1792 writeq(0x0, &bar0->rx_traffic_mask);
1793 } else if (flag == DISABLE_INTRS) {
20346722 1794 /*
1795 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1796 * register.
1797 */
1798 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1799 temp64 = readq(&bar0->general_int_mask);
1800 val64 |= temp64;
1801 writeq(val64, &bar0->general_int_mask);
1802 }
1803 }
1804}
1805
19a60522
SS		 1806/**
1807 * verify_pcc_quiescent- Checks for PCC quiescent state
1808 * Return: 1 If PCC is quiescence
1809 * 0 If PCC is not quiescence
1810 */
1ee6dd77 1811static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 1812{
19a60522 1813 int ret = 0, herc;
1ee6dd77 1814 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1815 u64 val64 = readq(&bar0->adapter_status);
1816
1817 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 1818
1819 if (flag == FALSE) {
19a60522
SS		 1820 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
1821 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1822 ret = 1;
19a60522
SS		 1823 } else {
1824 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1825 ret = 1;
20346722 1826 }
1827 } else {
19a60522 1828 if ((!herc && (get_xena_rev_id(sp->pdev) >= 4)) || herc) {
5e25b9dd 1829 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 1830 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1831 ret = 1;
5e25b9dd 1832 } else {
1833 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 1834 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1835 ret = 1;
20346722 1836 }
1837 }
1838
1839 return ret;
1840}
1841/**
1842 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 1843 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1844 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1845 * differs and the calling function passes the input argument flag to
1846 * indicate this.
20346722 1847 * Return: 1 If xena is quiescence
1da177e4
LT		 1848 * 0 If Xena is not quiescence
1849 */
1850
1ee6dd77 1851static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 1852{
19a60522 1853 int mode;
1ee6dd77 1854 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1855 u64 val64 = readq(&bar0->adapter_status);
1856 mode = s2io_verify_pci_mode(sp);
1da177e4 1857
19a60522
SS		 1858 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1859 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1860 return 0;
1861 }
1862 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1863 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1864 return 0;
1865 }
1866 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1867 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1868 return 0;
1869 }
1870 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1871 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1872 return 0;
1873 }
1874 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1875 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1876 return 0;
1877 }
1878 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1879 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1880 return 0;
1881 }
1882 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1883 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1884 return 0;
1885 }
1886 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1887 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1888 return 0;
1da177e4
LT		 1889 }
1890
19a60522
SS		 1891 /*
1892 * In PCI 33 mode, the P_PLL is not used, and therefore,
1893 * the the P_PLL_LOCK bit in the adapter_status register will
1894 * not be asserted.
1895 */
1896 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1897 sp->device_type == XFRAME_II_DEVICE && mode !=
1898 PCI_MODE_PCI_33) {
1899 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1900 return 0;
1901 }
1902 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1903 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1904 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1905 return 0;
1906 }
1907 return 1;
1da177e4
LT		 1908}
1909
1910/**
1911 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1912 * @sp: Pointer to device specifc structure
20346722 1913 * Description :
1da177e4
LT		 1914 * New procedure to clear mac address reading problems on Alpha platforms
1915 *
1916 */
1917
1ee6dd77 1918static void fix_mac_address(struct s2io_nic * sp)
1da177e4 1919{
1ee6dd77 1920 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 1921 u64 val64;
1922 int i = 0;
1923
1924 while (fix_mac[i] != END_SIGN) {
1925 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1926 udelay(10);
1da177e4
LT		 1927 val64 = readq(&bar0->gpio_control);
1928 }
1929}
1930
1931/**
20346722 1932 * start_nic - Turns the device on
1da177e4 1933 * @nic : device private variable.
20346722 1934 * Description:
1935 * This function actually turns the device on. Before this function is
1936 * called,all Registers are configured from their reset states
1937 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1938 * calling this function, the device interrupts are cleared and the NIC is
1939 * literally switched on by writing into the adapter control register.
20346722 1940 * Return Value:
1da177e4
LT		 1941 * SUCCESS on success and -1 on failure.
1942 */
1943
1944static int start_nic(struct s2io_nic *nic)
1945{
1ee6dd77 1946 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1947 struct net_device *dev = nic->dev;
1948 register u64 val64 = 0;
20346722 1949 u16 subid, i;
1ee6dd77 1950 struct mac_info *mac_control;
1da177e4
LT		 1951 struct config_param *config;
1952
1953 mac_control = &nic->mac_control;
1954 config = &nic->config;
1955
1956 /* PRC Initialization and configuration */
1957 for (i = 0; i < config->rx_ring_num; i++) {
20346722 1958 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 1959 &bar0->prc_rxd0_n[i]);
1960
1961 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982 1962 if (nic->config.bimodal)
1963 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 1964 if (nic->rxd_mode == RXD_MODE_1)
1965 val64 |= PRC_CTRL_RC_ENABLED;
1966 else
1967 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 1968 if (nic->device_type == XFRAME_II_DEVICE)
1969 val64 |= PRC_CTRL_GROUP_READS;
1970 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
1971 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 1972 writeq(val64, &bar0->prc_ctrl_n[i]);
1973 }
1974
da6971d8
AR		 1975 if (nic->rxd_mode == RXD_MODE_3B) {
1976 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
1977 val64 = readq(&bar0->rx_pa_cfg);
1978 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
1979 writeq(val64, &bar0->rx_pa_cfg);
1980 }
1da177e4 1981
926930b2
SS		 1982 if (vlan_tag_strip == 0) {
1983 val64 = readq(&bar0->rx_pa_cfg);
1984 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
1985 writeq(val64, &bar0->rx_pa_cfg);
1986 vlan_strip_flag = 0;
1987 }
1988
20346722 1989 /*
1da177e4
LT		 1990 * Enabling MC-RLDRAM. After enabling the device, we timeout
1991 * for around 100ms, which is approximately the time required
1992 * for the device to be ready for operation.
1993 */
1994 val64 = readq(&bar0->mc_rldram_mrs);
1995 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
1996 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
1997 val64 = readq(&bar0->mc_rldram_mrs);
1998
20346722 1999 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2000
2001 /* Enabling ECC Protection. */
2002 val64 = readq(&bar0->adapter_control);
2003 val64 &= ~ADAPTER_ECC_EN;
2004 writeq(val64, &bar0->adapter_control);
2005
20346722 2006 /*
2007 * Clearing any possible Link state change interrupts that
1da177e4
LT		 2008 * could have popped up just before Enabling the card.
2009 */
2010 val64 = readq(&bar0->mac_rmac_err_reg);
2011 if (val64)
2012 writeq(val64, &bar0->mac_rmac_err_reg);
2013
20346722 2014 /*
2015 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2016 * it.
2017 */
2018 val64 = readq(&bar0->adapter_status);
19a60522 2019 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2020 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2021 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2022 (unsigned long long) val64);
2023 return FAILURE;
2024 }
2025
20346722 2026 /*
1da177e4 2027 * With some switches, link might be already up at this point.
20346722 2028 * Because of this weird behavior, when we enable laser,
2029 * we may not get link. We need to handle this. We cannot
2030 * figure out which switch is misbehaving. So we are forced to
2031 * make a global change.
1da177e4
LT		 2032 */
2033
2034 /* Enabling Laser. */
2035 val64 = readq(&bar0->adapter_control);
2036 val64 |= ADAPTER_EOI_TX_ON;
2037 writeq(val64, &bar0->adapter_control);
2038
c92ca04b
AR		 2039 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2040 /*
2041 * Dont see link state interrupts initally on some switches,
2042 * so directly scheduling the link state task here.
2043 */
2044 schedule_work(&nic->set_link_task);
2045 }
1da177e4
LT		 2046 /* SXE-002: Initialize link and activity LED */
2047 subid = nic->pdev->subsystem_device;
541ae68f 2048 if (((subid & 0xFF) >= 0x07) &&
2049 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2050 val64 = readq(&bar0->gpio_control);
2051 val64 |= 0x0000800000000000ULL;
2052 writeq(val64, &bar0->gpio_control);
2053 val64 = 0x0411040400000000ULL;
509a2671 2054 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2055 }
2056
1da177e4
LT		 2057 return SUCCESS;
2058}
fed5eccd
AR		 2059/**
2060 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2061 */
1ee6dd77
RB		 2062static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2063 TxD *txdlp, int get_off)
fed5eccd 2064{
1ee6dd77 2065 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2066 struct sk_buff *skb;
1ee6dd77 2067 struct TxD *txds;
fed5eccd
AR		 2068 u16 j, frg_cnt;
2069
2070 txds = txdlp;
26b7625c 2071 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2072 pci_unmap_single(nic->pdev, (dma_addr_t)
2073 txds->Buffer_Pointer, sizeof(u64),
2074 PCI_DMA_TODEVICE);
2075 txds++;
2076 }
2077
2078 skb = (struct sk_buff *) ((unsigned long)
2079 txds->Host_Control);
2080 if (!skb) {
1ee6dd77 2081 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2082 return NULL;
2083 }
2084 pci_unmap_single(nic->pdev, (dma_addr_t)
2085 txds->Buffer_Pointer,
2086 skb->len - skb->data_len,
2087 PCI_DMA_TODEVICE);
2088 frg_cnt = skb_shinfo(skb)->nr_frags;
2089 if (frg_cnt) {
2090 txds++;
2091 for (j = 0; j < frg_cnt; j++, txds++) {
2092 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2093 if (!txds->Buffer_Pointer)
2094 break;
6aa20a22 2095 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2096 txds->Buffer_Pointer,
2097 frag->size, PCI_DMA_TODEVICE);
2098 }
2099 }
1ee6dd77 2100 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2101 return(skb);
2102}
1da177e4 2103
20346722 2104/**
2105 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2106 * @nic : device private variable.
20346722 2107 * Description:
1da177e4 2108 * Free all queued Tx buffers.
20346722 2109 * Return Value: void
1da177e4
LT		 2110*/
2111
2112static void free_tx_buffers(struct s2io_nic *nic)
2113{
2114 struct net_device *dev = nic->dev;
2115 struct sk_buff *skb;
1ee6dd77 2116 struct TxD *txdp;
1da177e4 2117 int i, j;
1ee6dd77 2118 struct mac_info *mac_control;
1da177e4 2119 struct config_param *config;
fed5eccd 2120 int cnt = 0;
1da177e4
LT		 2121
2122 mac_control = &nic->mac_control;
2123 config = &nic->config;
2124
2125 for (i = 0; i < config->tx_fifo_num; i++) {
2126 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
1ee6dd77 2127 txdp = (struct TxD *) mac_control->fifos[i].list_info[j].
1da177e4 2128 list_virt_addr;
fed5eccd
AR		 2129 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2130 if (skb) {
2131 dev_kfree_skb(skb);
2132 cnt++;
1da177e4 2133 }
1da177e4
LT		 2134 }
2135 DBG_PRINT(INTR_DBG,
2136 "%s:forcibly freeing %d skbs on FIFO%d\n",
2137 dev->name, cnt, i);
20346722 2138 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2139 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2140 }
2141}
2142
20346722 2143/**
2144 * stop_nic - To stop the nic
1da177e4 2145 * @nic ; device private variable.
20346722 2146 * Description:
2147 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2148 * function does. This function is called to stop the device.
2149 * Return Value:
2150 * void.
2151 */
2152
2153static void stop_nic(struct s2io_nic *nic)
2154{
1ee6dd77 2155 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2156 register u64 val64 = 0;
5d3213cc 2157 u16 interruptible;
1ee6dd77 2158 struct mac_info *mac_control;
1da177e4
LT		 2159 struct config_param *config;
2160
2161 mac_control = &nic->mac_control;
2162 config = &nic->config;
2163
2164 /* Disable all interrupts */
e960fc5c 2165 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d 2166 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2167 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2168 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2169
5d3213cc
AR		 2170 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2171 val64 = readq(&bar0->adapter_control);
2172 val64 &= ~(ADAPTER_CNTL_EN);
2173 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2174}
2175
1ee6dd77
RB		 2176static int fill_rxd_3buf(struct s2io_nic *nic, struct RxD_t *rxdp, struct \
2177 sk_buff *skb)
da6971d8
AR		 2178{
2179 struct net_device *dev = nic->dev;
2180 struct sk_buff *frag_list;
50eb8006 2181 void *tmp;
da6971d8
AR		 2182
2183 /* Buffer-1 receives L3/L4 headers */
1ee6dd77 2184 ((struct RxD3*)rxdp)->Buffer1_ptr = pci_map_single
da6971d8
AR		 2185 (nic->pdev, skb->data, l3l4hdr_size + 4,
2186 PCI_DMA_FROMDEVICE);
2187
2188 /* skb_shinfo(skb)->frag_list will have L4 data payload */
2189 skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2190 if (skb_shinfo(skb)->frag_list == NULL) {
2191 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2192 return -ENOMEM ;
2193 }
2194 frag_list = skb_shinfo(skb)->frag_list;
372cc597 2195 skb->truesize += frag_list->truesize;
da6971d8 2196 frag_list->next = NULL;
50eb8006
JG		 2197 tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2198 frag_list->data = tmp;
2199 frag_list->tail = tmp;
da6971d8
AR		 2200
2201 /* Buffer-2 receives L4 data payload */
1ee6dd77 2202 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
da6971d8
AR		 2203 frag_list->data, dev->mtu,
2204 PCI_DMA_FROMDEVICE);
2205 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2206 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2207
2208 return SUCCESS;
2209}
2210
20346722 2211/**
2212 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2213 * @nic: device private variable
20346722 2214 * @ring_no: ring number
2215 * Description:
1da177e4
LT		 2216 * The function allocates Rx side skbs and puts the physical
2217 * address of these buffers into the RxD buffer pointers, so that the NIC
2218 * can DMA the received frame into these locations.
2219 * The NIC supports 3 receive modes, viz
2220 * 1. single buffer,
2221 * 2. three buffer and
2222 * 3. Five buffer modes.
20346722 2223 * Each mode defines how many fragments the received frame will be split
2224 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2225 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2226 * is split into 3 fragments. As of now only single buffer mode is
2227 * supported.
2228 * Return Value:
2229 * SUCCESS on success or an appropriate -ve value on failure.
2230 */
2231
ac1f60db 2232static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2233{
2234 struct net_device *dev = nic->dev;
2235 struct sk_buff *skb;
1ee6dd77 2236 struct RxD_t *rxdp;
1da177e4 2237 int off, off1, size, block_no, block_no1;
1da177e4 2238 u32 alloc_tab = 0;
20346722 2239 u32 alloc_cnt;
1ee6dd77 2240 struct mac_info *mac_control;
1da177e4 2241 struct config_param *config;
20346722 2242 u64 tmp;
1ee6dd77 2243 struct buffAdd *ba;
1da177e4 2244 unsigned long flags;
1ee6dd77 2245 struct RxD_t *first_rxdp = NULL;
1da177e4
LT		 2246
2247 mac_control = &nic->mac_control;
2248 config = &nic->config;
20346722 2249 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2250 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2251
5d3213cc 2252 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2253 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2254 while (alloc_tab < alloc_cnt) {
20346722 2255 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2256 block_index;
20346722 2257 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2258
da6971d8
AR		 2259 rxdp = mac_control->rings[ring_no].
2260 rx_blocks[block_no].rxds[off].virt_addr;
2261
2262 if ((block_no == block_no1) && (off == off1) &&
2263 (rxdp->Host_Control)) {
2264 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2265 dev->name);
1da177e4
LT		 2266 DBG_PRINT(INTR_DBG, " info equated\n");
2267 goto end;
2268 }
da6971d8 2269 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2270 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2271 block_index++;
da6971d8
AR		 2272 if (mac_control->rings[ring_no].rx_curr_put_info.
2273 block_index == mac_control->rings[ring_no].
2274 block_count)
2275 mac_control->rings[ring_no].rx_curr_put_info.
2276 block_index = 0;
2277 block_no = mac_control->rings[ring_no].
2278 rx_curr_put_info.block_index;
2279 if (off == rxd_count[nic->rxd_mode])
2280 off = 0;
20346722 2281 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2282 offset = off;
2283 rxdp = mac_control->rings[ring_no].
2284 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2285 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2286 dev->name, rxdp);
2287 }
db874e65
SS		 2288 if(!napi) {
2289 spin_lock_irqsave(&nic->put_lock, flags);
2290 mac_control->rings[ring_no].put_pos =
2291 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2292 spin_unlock_irqrestore(&nic->put_lock, flags);
2293 } else {
2294 mac_control->rings[ring_no].put_pos =
2295 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2296 }
da6971d8
AR		 2297 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2298 ((nic->rxd_mode >= RXD_MODE_3A) &&
2299 (rxdp->Control_2 & BIT(0)))) {
20346722 2300 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2301 offset = off;
1da177e4
LT		 2302 goto end;
2303 }
da6971d8
AR		 2304 /* calculate size of skb based on ring mode */
2305 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2306 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2307 if (nic->rxd_mode == RXD_MODE_1)
2308 size += NET_IP_ALIGN;
2309 else if (nic->rxd_mode == RXD_MODE_3B)
2310 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2311 else
2312 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2313
da6971d8
AR		 2314 /* allocate skb */
2315 skb = dev_alloc_skb(size);
2316 if(!skb) {
1da177e4
LT		 2317 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2318 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
303bcb4b 2319 if (first_rxdp) {
2320 wmb();
2321 first_rxdp->Control_1 |= RXD_OWN_XENA;
2322 }
da6971d8
AR		 2323 return -ENOMEM ;
2324 }
2325 if (nic->rxd_mode == RXD_MODE_1) {
2326 /* 1 buffer mode - normal operation mode */
1ee6dd77 2327 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2328 skb_reserve(skb, NET_IP_ALIGN);
1ee6dd77 2329 ((struct RxD1*)rxdp)->Buffer0_ptr = pci_map_single
863c11a9
AR		 2330 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2331 PCI_DMA_FROMDEVICE);
2332 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8
AR		 2333
2334 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2335 /*
2336 * 2 or 3 buffer mode -
2337 * Both 2 buffer mode and 3 buffer mode provides 128
2338 * byte aligned receive buffers.
2339 *
2340 * 3 buffer mode provides header separation where in
2341 * skb->data will have L3/L4 headers where as
2342 * skb_shinfo(skb)->frag_list will have the L4 data
2343 * payload
2344 */
2345
1ee6dd77 2346 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2347 ba = &mac_control->rings[ring_no].ba[block_no][off];
2348 skb_reserve(skb, BUF0_LEN);
2349 tmp = (u64)(unsigned long) skb->data;
2350 tmp += ALIGN_SIZE;
2351 tmp &= ~ALIGN_SIZE;
2352 skb->data = (void *) (unsigned long)tmp;
2353 skb->tail = (void *) (unsigned long)tmp;
2354
1ee6dd77
RB		 2355 if (!(((struct RxD3*)rxdp)->Buffer0_ptr))
2356 ((struct RxD3*)rxdp)->Buffer0_ptr =
75c30b13 2357 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2358 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2359 else
2360 pci_dma_sync_single_for_device(nic->pdev,
1ee6dd77 2361 (dma_addr_t) ((struct RxD3*)rxdp)->Buffer0_ptr,
75c30b13 2362 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8
AR		 2363 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2364 if (nic->rxd_mode == RXD_MODE_3B) {
2365 /* Two buffer mode */
2366
2367 /*
6aa20a22 2368 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2369 * L4 payload
2370 */
1ee6dd77 2371 ((struct RxD3*)rxdp)->Buffer2_ptr = pci_map_single
da6971d8
AR		 2372 (nic->pdev, skb->data, dev->mtu + 4,
2373 PCI_DMA_FROMDEVICE);
2374
75c30b13 2375 /* Buffer-1 will be dummy buffer. Not used */
1ee6dd77
RB		 2376 if (!(((struct RxD3*)rxdp)->Buffer1_ptr)) {
2377 ((struct RxD3*)rxdp)->Buffer1_ptr =
6aa20a22 2378 pci_map_single(nic->pdev,
75c30b13
AR		 2379 ba->ba_1, BUF1_LEN,
2380 PCI_DMA_FROMDEVICE);
2381 }
da6971d8
AR		 2382 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2383 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2384 (dev->mtu + 4);
2385 } else {
2386 /* 3 buffer mode */
2387 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2388 dev_kfree_skb_irq(skb);
2389 if (first_rxdp) {
2390 wmb();
2391 first_rxdp->Control_1 |=
2392 RXD_OWN_XENA;
2393 }
2394 return -ENOMEM ;
2395 }
2396 }
2397 rxdp->Control_2 |= BIT(0);
1da177e4 2398 }
1da177e4 2399 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b 2400 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2401 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2402 off++;
da6971d8
AR		 2403 if (off == (rxd_count[nic->rxd_mode] + 1))
2404 off = 0;
20346722 2405 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2406
da6971d8 2407 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2408 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2409 if (first_rxdp) {
2410 wmb();
2411 first_rxdp->Control_1 |= RXD_OWN_XENA;
2412 }
2413 first_rxdp = rxdp;
2414 }
1da177e4
LT		 2415 atomic_inc(&nic->rx_bufs_left[ring_no]);
2416 alloc_tab++;
2417 }
2418
2419 end:
303bcb4b 2420 /* Transfer ownership of first descriptor to adapter just before
2421 * exiting. Before that, use memory barrier so that ownership
2422 * and other fields are seen by adapter correctly.
2423 */
2424 if (first_rxdp) {
2425 wmb();
2426 first_rxdp->Control_1 |= RXD_OWN_XENA;
2427 }
2428
1da177e4
LT		 2429 return SUCCESS;
2430}
2431
da6971d8
AR		 2432static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2433{
2434 struct net_device *dev = sp->dev;
2435 int j;
2436 struct sk_buff *skb;
1ee6dd77
RB		 2437 struct RxD_t *rxdp;
2438 struct mac_info *mac_control;
2439 struct buffAdd *ba;
da6971d8
AR		 2440
2441 mac_control = &sp->mac_control;
2442 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2443 rxdp = mac_control->rings[ring_no].
2444 rx_blocks[blk].rxds[j].virt_addr;
2445 skb = (struct sk_buff *)
2446 ((unsigned long) rxdp->Host_Control);
2447 if (!skb) {
2448 continue;
2449 }
2450 if (sp->rxd_mode == RXD_MODE_1) {
2451 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2452 ((struct RxD1*)rxdp)->Buffer0_ptr,
da6971d8
AR		 2453 dev->mtu +
2454 HEADER_ETHERNET_II_802_3_SIZE
2455 + HEADER_802_2_SIZE +
2456 HEADER_SNAP_SIZE,
2457 PCI_DMA_FROMDEVICE);
1ee6dd77 2458 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8
AR		 2459 } else if(sp->rxd_mode == RXD_MODE_3B) {
2460 ba = &mac_control->rings[ring_no].
2461 ba[blk][j];
2462 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2463 ((struct RxD3*)rxdp)->Buffer0_ptr,
da6971d8
AR		 2464 BUF0_LEN,
2465 PCI_DMA_FROMDEVICE);
2466 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2467 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2468 BUF1_LEN,
2469 PCI_DMA_FROMDEVICE);
2470 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2471 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8
AR		 2472 dev->mtu + 4,
2473 PCI_DMA_FROMDEVICE);
1ee6dd77 2474 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2475 } else {
2476 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2477 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
da6971d8
AR		 2478 PCI_DMA_FROMDEVICE);
2479 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2480 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2481 l3l4hdr_size + 4,
2482 PCI_DMA_FROMDEVICE);
2483 pci_unmap_single(sp->pdev, (dma_addr_t)
1ee6dd77 2484 ((struct RxD3*)rxdp)->Buffer2_ptr, dev->mtu,
da6971d8 2485 PCI_DMA_FROMDEVICE);
1ee6dd77 2486 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8
AR		 2487 }
2488 dev_kfree_skb(skb);
2489 atomic_dec(&sp->rx_bufs_left[ring_no]);
2490 }
2491}
2492
1da177e4 2493/**
20346722 2494 * free_rx_buffers - Frees all Rx buffers
1da177e4 2495 * @sp: device private variable.
20346722 2496 * Description:
1da177e4
LT		 2497 * This function will free all Rx buffers allocated by host.
2498 * Return Value:
2499 * NONE.
2500 */
2501
2502static void free_rx_buffers(struct s2io_nic *sp)
2503{
2504 struct net_device *dev = sp->dev;
da6971d8 2505 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2506 struct mac_info *mac_control;
1da177e4 2507 struct config_param *config;
1da177e4
LT		 2508
2509 mac_control = &sp->mac_control;
2510 config = &sp->config;
2511
2512 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2513 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2514 free_rxd_blk(sp,i,blk);
1da177e4 2515
20346722 2516 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2517 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2518 mac_control->rings[i].rx_curr_put_info.offset = 0;
2519 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2520 atomic_set(&sp->rx_bufs_left[i], 0);
2521 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2522 dev->name, buf_cnt, i);
2523 }
2524}
2525
2526/**
2527 * s2io_poll - Rx interrupt handler for NAPI support
2528 * @dev : pointer to the device structure.
20346722 2529 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2530 * during one pass through the 'Poll" function.
2531 * Description:
2532 * Comes into picture only if NAPI support has been incorporated. It does
2533 * the same thing that rx_intr_handler does, but not in a interrupt context
2534 * also It will process only a given number of packets.
2535 * Return value:
2536 * 0 on success and 1 if there are No Rx packets to be processed.
2537 */
2538
1da177e4
LT		 2539static int s2io_poll(struct net_device *dev, int *budget)
2540{
1ee6dd77 2541 struct s2io_nic *nic = dev->priv;
20346722 2542 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2543 struct mac_info *mac_control;
1da177e4 2544 struct config_param *config;
1ee6dd77 2545 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2546 int i;
1da177e4 2547
7ba013ac 2548 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2549 mac_control = &nic->mac_control;
2550 config = &nic->config;
2551
20346722 2552 nic->pkts_to_process = *budget;
2553 if (nic->pkts_to_process > dev->quota)
2554 nic->pkts_to_process = dev->quota;
2555 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2556
19a60522
SS		 2557 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2558 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2559
2560 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2561 rx_intr_handler(&mac_control->rings[i]);
2562 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2563 if (!nic->pkts_to_process) {
2564 /* Quota for the current iteration has been met */
2565 goto no_rx;
1da177e4 2566 }
1da177e4
LT		 2567 }
2568 if (!pkt_cnt)
2569 pkt_cnt = 1;
2570
2571 dev->quota -= pkt_cnt;
2572 *budget -= pkt_cnt;
2573 netif_rx_complete(dev);
2574
2575 for (i = 0; i < config->rx_ring_num; i++) {
2576 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2577 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2578 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2579 break;
2580 }
2581 }
2582 /* Re enable the Rx interrupts. */
c92ca04b 2583 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2584 readl(&bar0->rx_traffic_mask);
7ba013ac 2585 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2586 return 0;
2587
20346722 2588no_rx:
1da177e4
LT		 2589 dev->quota -= pkt_cnt;
2590 *budget -= pkt_cnt;
2591
2592 for (i = 0; i < config->rx_ring_num; i++) {
2593 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2594 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2595 DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2596 break;
2597 }
2598 }
7ba013ac 2599 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2600 return 1;
2601}
20346722 2602
b41477f3 2603#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2604/**
b41477f3 2605 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2606 * @dev : pointer to the device structure.
2607 * Description:
b41477f3
AR		 2608 * This function will be called by upper layer to check for events on the
2609 * interface in situations where interrupts are disabled. It is used for
2610 * specific in-kernel networking tasks, such as remote consoles and kernel
2611 * debugging over the network (example netdump in RedHat).
612eff0e 2612 */
612eff0e
BH		 2613static void s2io_netpoll(struct net_device *dev)
2614{
1ee6dd77
RB		 2615 struct s2io_nic *nic = dev->priv;
2616 struct mac_info *mac_control;
612eff0e 2617 struct config_param *config;
1ee6dd77 2618 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2619 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2620 int i;
2621
2622 disable_irq(dev->irq);
2623
2624 atomic_inc(&nic->isr_cnt);
2625 mac_control = &nic->mac_control;
2626 config = &nic->config;
2627
612eff0e 2628 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2629 writeq(val64, &bar0->tx_traffic_int);
2630
6aa20a22 2631 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2632 * run out of skbs and will fail and eventually netpoll application such
2633 * as netdump will fail.
2634 */
2635 for (i = 0; i < config->tx_fifo_num; i++)
2636 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2637
b41477f3 2638 /* check for received packet and indicate up to network */
612eff0e
BH		 2639 for (i = 0; i < config->rx_ring_num; i++)
2640 rx_intr_handler(&mac_control->rings[i]);
2641
2642 for (i = 0; i < config->rx_ring_num; i++) {
2643 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2644 DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2645 DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2646 break;
2647 }
2648 }
2649 atomic_dec(&nic->isr_cnt);
2650 enable_irq(dev->irq);
2651 return;
2652}
2653#endif
2654
20346722 2655/**
1da177e4
LT		 2656 * rx_intr_handler - Rx interrupt handler
2657 * @nic: device private variable.
20346722 2658 * Description:
2659 * If the interrupt is because of a received frame or if the
1da177e4 2660 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2661 * called. It picks out the RxD at which place the last Rx processing had
2662 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2663 * the offset.
2664 * Return Value:
2665 * NONE.
2666 */
1ee6dd77 2667static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2668{
1ee6dd77 2669 struct s2io_nic *nic = ring_data->nic;
1da177e4 2670 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2671 int get_block, put_block, put_offset;
1ee6dd77
RB		 2672 struct rx_curr_get_info get_info, put_info;
2673 struct RxD_t *rxdp;
1da177e4 2674 struct sk_buff *skb;
20346722 2675 int pkt_cnt = 0;
7d3d0439
RA		 2676 int i;
2677
7ba013ac 2678 spin_lock(&nic->rx_lock);
2679 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2680 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac 2681 __FUNCTION__, dev->name);
2682 spin_unlock(&nic->rx_lock);
776bd20f 2683 return;
7ba013ac 2684 }
2685
20346722 2686 get_info = ring_data->rx_curr_get_info;
2687 get_block = get_info.block_index;
1ee6dd77 2688 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2689 put_block = put_info.block_index;
da6971d8 2690 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2691 if (!napi) {
2692 spin_lock(&nic->put_lock);
2693 put_offset = ring_data->put_pos;
2694 spin_unlock(&nic->put_lock);
2695 } else
2696 put_offset = ring_data->put_pos;
2697
da6971d8 2698 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2699 /*
2700 * If your are next to put index then it's
2701 * FIFO full condition
2702 */
da6971d8
AR		 2703 if ((get_block == put_block) &&
2704 (get_info.offset + 1) == put_info.offset) {
75c30b13 2705 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2706 break;
2707 }
20346722 2708 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2709 if (skb == NULL) {
2710 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2711 dev->name);
2712 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2713 spin_unlock(&nic->rx_lock);
20346722 2714 return;
1da177e4 2715 }
da6971d8
AR		 2716 if (nic->rxd_mode == RXD_MODE_1) {
2717 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2718 ((struct RxD1*)rxdp)->Buffer0_ptr,
20346722 2719 dev->mtu +
2720 HEADER_ETHERNET_II_802_3_SIZE +
2721 HEADER_802_2_SIZE +
2722 HEADER_SNAP_SIZE,
2723 PCI_DMA_FROMDEVICE);
da6971d8 2724 } else if (nic->rxd_mode == RXD_MODE_3B) {
75c30b13 2725 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
1ee6dd77 2726 ((struct RxD3*)rxdp)->Buffer0_ptr,
20346722 2727 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2728 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2729 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8 2730 dev->mtu + 4,
20346722 2731 PCI_DMA_FROMDEVICE);
da6971d8 2732 } else {
75c30b13 2733 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
1ee6dd77 2734 ((struct RxD3*)rxdp)->Buffer0_ptr, BUF0_LEN,
da6971d8
AR		 2735 PCI_DMA_FROMDEVICE);
2736 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2737 ((struct RxD3*)rxdp)->Buffer1_ptr,
da6971d8
AR		 2738 l3l4hdr_size + 4,
2739 PCI_DMA_FROMDEVICE);
2740 pci_unmap_single(nic->pdev, (dma_addr_t)
1ee6dd77 2741 ((struct RxD3*)rxdp)->Buffer2_ptr,
da6971d8
AR		 2742 dev->mtu, PCI_DMA_FROMDEVICE);
2743 }
863c11a9 2744 prefetch(skb->data);
20346722 2745 rx_osm_handler(ring_data, rxdp);
2746 get_info.offset++;
da6971d8
AR		 2747 ring_data->rx_curr_get_info.offset = get_info.offset;
2748 rxdp = ring_data->rx_blocks[get_block].
2749 rxds[get_info.offset].virt_addr;
2750 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2751 get_info.offset = 0;
da6971d8 2752 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2753 get_block++;
da6971d8
AR		 2754 if (get_block == ring_data->block_count)
2755 get_block = 0;
2756 ring_data->rx_curr_get_info.block_index = get_block;
20346722 2757 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2758 }
1da177e4 2759
20346722 2760 nic->pkts_to_process -= 1;
db874e65 2761 if ((napi) && (!nic->pkts_to_process))
20346722 2762 break;
20346722 2763 pkt_cnt++;
1da177e4
LT		 2764 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2765 break;
2766 }
7d3d0439
RA		 2767 if (nic->lro) {
2768 /* Clear all LRO sessions before exiting */
2769 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2770 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2771 if (lro->in_use) {
2772 update_L3L4_header(nic, lro);
2773 queue_rx_frame(lro->parent);
2774 clear_lro_session(lro);
2775 }
2776 }
2777 }
2778
7ba013ac 2779 spin_unlock(&nic->rx_lock);
1da177e4 2780}
20346722 2781
2782/**
1da177e4
LT		 2783 * tx_intr_handler - Transmit interrupt handler
2784 * @nic : device private variable
20346722 2785 * Description:
2786 * If an interrupt was raised to indicate DMA complete of the
2787 * Tx packet, this function is called. It identifies the last TxD
2788 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2789 * DMA'ed into the NICs internal memory.
2790 * Return Value:
2791 * NONE
2792 */
2793
1ee6dd77 2794static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2795{
1ee6dd77 2796 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2797 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2798 struct tx_curr_get_info get_info, put_info;
1da177e4 2799 struct sk_buff *skb;
1ee6dd77 2800 struct TxD *txdlp;
1da177e4 2801
20346722 2802 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2803 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2804 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722 2805 list_virt_addr;
2806 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2807 (get_info.offset != put_info.offset) &&
2808 (txdlp->Host_Control)) {
2809 /* Check for TxD errors */
2810 if (txdlp->Control_1 & TXD_T_CODE) {
2811 unsigned long long err;
2812 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2813 if (err & 0x1) {
2814 nic->mac_control.stats_info->sw_stat.
2815 parity_err_cnt++;
2816 }
776bd20f 2817 if ((err >> 48) == 0xA) {
2818 DBG_PRINT(TX_DBG, "TxD returned due \
19a60522 2819 to loss of link\n");
776bd20f 2820 }
2821 else {
19a60522 2822 DBG_PRINT(ERR_DBG, "***TxD error %llx\n", err);
776bd20f 2823 }
20346722 2824 }
1da177e4 2825
fed5eccd 2826 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 2827 if (skb == NULL) {
2828 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2829 __FUNCTION__);
2830 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2831 return;
2832 }
2833
20346722 2834 /* Updating the statistics block */
20346722 2835 nic->stats.tx_bytes += skb->len;
2836 dev_kfree_skb_irq(skb);
2837
2838 get_info.offset++;
863c11a9
AR		 2839 if (get_info.offset == get_info.fifo_len + 1)
2840 get_info.offset = 0;
1ee6dd77 2841 txdlp = (struct TxD *) fifo_data->list_info
20346722 2842 [get_info.offset].list_virt_addr;
2843 fifo_data->tx_curr_get_info.offset =
2844 get_info.offset;
1da177e4
LT		 2845 }
2846
2847 spin_lock(&nic->tx_lock);
2848 if (netif_queue_stopped(dev))
2849 netif_wake_queue(dev);
2850 spin_unlock(&nic->tx_lock);
2851}
2852
bd1034f0
AR		 2853/**
2854 * s2io_mdio_write - Function to write in to MDIO registers
2855 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2856 * @addr : address value
2857 * @value : data value
2858 * @dev : pointer to net_device structure
2859 * Description:
2860 * This function is used to write values to the MDIO registers
2861 * NONE
2862 */
2863static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2864{
2865 u64 val64 = 0x0;
1ee6dd77
RB		 2866 struct s2io_nic *sp = dev->priv;
2867 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2868
2869 //address transaction
2870 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2871 | MDIO_MMD_DEV_ADDR(mmd_type)
2872 | MDIO_MMS_PRT_ADDR(0x0);
2873 writeq(val64, &bar0->mdio_control);
2874 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2875 writeq(val64, &bar0->mdio_control);
2876 udelay(100);
2877
2878 //Data transaction
2879 val64 = 0x0;
2880 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2881 | MDIO_MMD_DEV_ADDR(mmd_type)
2882 | MDIO_MMS_PRT_ADDR(0x0)
2883 | MDIO_MDIO_DATA(value)
2884 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2885 writeq(val64, &bar0->mdio_control);
2886 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2887 writeq(val64, &bar0->mdio_control);
2888 udelay(100);
2889
2890 val64 = 0x0;
2891 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2892 | MDIO_MMD_DEV_ADDR(mmd_type)
2893 | MDIO_MMS_PRT_ADDR(0x0)
2894 | MDIO_OP(MDIO_OP_READ_TRANS);
2895 writeq(val64, &bar0->mdio_control);
2896 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2897 writeq(val64, &bar0->mdio_control);
2898 udelay(100);
2899
2900}
2901
2902/**
2903 * s2io_mdio_read - Function to write in to MDIO registers
2904 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2905 * @addr : address value
2906 * @dev : pointer to net_device structure
2907 * Description:
2908 * This function is used to read values to the MDIO registers
2909 * NONE
2910 */
2911static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2912{
2913 u64 val64 = 0x0;
2914 u64 rval64 = 0x0;
1ee6dd77
RB		 2915 struct s2io_nic *sp = dev->priv;
2916 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2917
2918 /* address transaction */
2919 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2920 | MDIO_MMD_DEV_ADDR(mmd_type)
2921 | MDIO_MMS_PRT_ADDR(0x0);
2922 writeq(val64, &bar0->mdio_control);
2923 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2924 writeq(val64, &bar0->mdio_control);
2925 udelay(100);
2926
2927 /* Data transaction */
2928 val64 = 0x0;
2929 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2930 | MDIO_MMD_DEV_ADDR(mmd_type)
2931 | MDIO_MMS_PRT_ADDR(0x0)
2932 | MDIO_OP(MDIO_OP_READ_TRANS);
2933 writeq(val64, &bar0->mdio_control);
2934 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2935 writeq(val64, &bar0->mdio_control);
2936 udelay(100);
2937
2938 /* Read the value from regs */
2939 rval64 = readq(&bar0->mdio_control);
2940 rval64 = rval64 & 0xFFFF0000;
2941 rval64 = rval64 >> 16;
2942 return rval64;
2943}
2944/**
2945 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
2946 * @counter : couter value to be updated
2947 * @flag : flag to indicate the status
2948 * @type : counter type
2949 * Description:
2950 * This function is to check the status of the xpak counters value
2951 * NONE
2952 */
2953
2954static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2955{
2956 u64 mask = 0x3;
2957 u64 val64;
2958 int i;
2959 for(i = 0; i <index; i++)
2960 mask = mask << 0x2;
2961
2962 if(flag > 0)
2963 {
2964 *counter = *counter + 1;
2965 val64 = *regs_stat & mask;
2966 val64 = val64 >> (index * 0x2);
2967 val64 = val64 + 1;
2968 if(val64 == 3)
2969 {
2970 switch(type)
2971 {
2972 case 1:
2973 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2974 "service. Excessive temperatures may "
2975 "result in premature transceiver "
2976 "failure \n");
2977 break;
2978 case 2:
2979 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2980 "service Excessive bias currents may "
2981 "indicate imminent laser diode "
2982 "failure \n");
2983 break;
2984 case 3:
2985 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
2986 "service Excessive laser output "
2987 "power may saturate far-end "
2988 "receiver\n");
2989 break;
2990 default:
2991 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
2992 "type \n");
2993 }
2994 val64 = 0x0;
2995 }
2996 val64 = val64 << (index * 0x2);
2997 *regs_stat = (*regs_stat & (~mask)) | (val64);
2998
2999 } else {
3000 *regs_stat = *regs_stat & (~mask);
3001 }
3002}
3003
3004/**
3005 * s2io_updt_xpak_counter - Function to update the xpak counters
3006 * @dev : pointer to net_device struct
3007 * Description:
3008 * This function is to upate the status of the xpak counters value
3009 * NONE
3010 */
3011static void s2io_updt_xpak_counter(struct net_device *dev)
3012{
3013 u16 flag = 0x0;
3014 u16 type = 0x0;
3015 u16 val16 = 0x0;
3016 u64 val64 = 0x0;
3017 u64 addr = 0x0;
3018
1ee6dd77
RB		 3019 struct s2io_nic *sp = dev->priv;
3020 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3021
3022 /* Check the communication with the MDIO slave */
3023 addr = 0x0000;
3024 val64 = 0x0;
3025 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3026 if((val64 == 0xFFFF) || (val64 == 0x0000))
3027 {
3028 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3029 "Returned %llx\n", (unsigned long long)val64);
3030 return;
3031 }
3032
3033 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3034 if(val64 != 0x2040)
3035 {
3036 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3037 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3038 (unsigned long long)val64);
3039 return;
3040 }
3041
3042 /* Loading the DOM register to MDIO register */
3043 addr = 0xA100;
3044 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3045 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3046
3047 /* Reading the Alarm flags */
3048 addr = 0xA070;
3049 val64 = 0x0;
3050 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3051
3052 flag = CHECKBIT(val64, 0x7);
3053 type = 1;
3054 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3055 &stat_info->xpak_stat.xpak_regs_stat,
3056 0x0, flag, type);
3057
3058 if(CHECKBIT(val64, 0x6))
3059 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3060
3061 flag = CHECKBIT(val64, 0x3);
3062 type = 2;
3063 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3064 &stat_info->xpak_stat.xpak_regs_stat,
3065 0x2, flag, type);
3066
3067 if(CHECKBIT(val64, 0x2))
3068 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3069
3070 flag = CHECKBIT(val64, 0x1);
3071 type = 3;
3072 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3073 &stat_info->xpak_stat.xpak_regs_stat,
3074 0x4, flag, type);
3075
3076 if(CHECKBIT(val64, 0x0))
3077 stat_info->xpak_stat.alarm_laser_output_power_low++;
3078
3079 /* Reading the Warning flags */
3080 addr = 0xA074;
3081 val64 = 0x0;
3082 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3083
3084 if(CHECKBIT(val64, 0x7))
3085 stat_info->xpak_stat.warn_transceiver_temp_high++;
3086
3087 if(CHECKBIT(val64, 0x6))
3088 stat_info->xpak_stat.warn_transceiver_temp_low++;
3089
3090 if(CHECKBIT(val64, 0x3))
3091 stat_info->xpak_stat.warn_laser_bias_current_high++;
3092
3093 if(CHECKBIT(val64, 0x2))
3094 stat_info->xpak_stat.warn_laser_bias_current_low++;
3095
3096 if(CHECKBIT(val64, 0x1))
3097 stat_info->xpak_stat.warn_laser_output_power_high++;
3098
3099 if(CHECKBIT(val64, 0x0))
3100 stat_info->xpak_stat.warn_laser_output_power_low++;
3101}
3102
20346722 3103/**
1da177e4
LT		 3104 * alarm_intr_handler - Alarm Interrrupt handler
3105 * @nic: device private variable
20346722 3106 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3107 * complete, this function is called. If the interrupt was to indicate
20346722 3108 * a loss of link, the OSM link status handler is invoked for any other
3109 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3110 * and a H/W reset is issued.
3111 * Return Value:
3112 * NONE
3113*/
3114
3115static void alarm_intr_handler(struct s2io_nic *nic)
3116{
3117 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 3118 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 3119 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3120 u64 cnt;
3121 int i;
372cc597
SS		 3122 if (atomic_read(&nic->card_state) == CARD_DOWN)
3123 return;
bd1034f0
AR		 3124 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3125 /* Handling the XPAK counters update */
3126 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3127 /* waiting for an hour */
3128 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3129 } else {
3130 s2io_updt_xpak_counter(dev);
3131 /* reset the count to zero */
3132 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3133 }
1da177e4
LT		 3134
3135 /* Handling link status change error Intr */
a371a07d 3136 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3137 err_reg = readq(&bar0->mac_rmac_err_reg);
3138 writeq(err_reg, &bar0->mac_rmac_err_reg);
3139 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3140 schedule_work(&nic->set_link_task);
3141 }
1da177e4
LT		 3142 }
3143
5e25b9dd 3144 /* Handling Ecc errors */
3145 val64 = readq(&bar0->mc_err_reg);
3146 writeq(val64, &bar0->mc_err_reg);
3147 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3148 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac 3149 nic->mac_control.stats_info->sw_stat.
3150 double_ecc_errs++;
776bd20f 3151 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3152 dev->name);
776bd20f 3153 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3154 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3155 /* Reset XframeI only if critical error */
3156 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3157 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3158 netif_stop_queue(dev);
3159 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3160 nic->mac_control.stats_info->sw_stat.
3161 soft_reset_cnt++;
776bd20f 3162 }
e960fc5c 3163 }
5e25b9dd 3164 } else {
7ba013ac 3165 nic->mac_control.stats_info->sw_stat.
3166 single_ecc_errs++;
5e25b9dd 3167 }
3168 }
3169
1da177e4
LT		 3170 /* In case of a serious error, the device will be Reset. */
3171 val64 = readq(&bar0->serr_source);
3172 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3173 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3174 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3175 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3176 (unsigned long long)val64);
1da177e4
LT		 3177 netif_stop_queue(dev);
3178 schedule_work(&nic->rst_timer_task);
bd1034f0 3179 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3180 }
3181
3182 /*
3183 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3184 * Error occurs, the adapter will be recycled by disabling the
20346722 3185 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3186 * becomes Quiescent.
3187 */
3188 val64 = readq(&bar0->pcc_err_reg);
3189 writeq(val64, &bar0->pcc_err_reg);
3190 if (val64 & PCC_FB_ECC_DB_ERR) {
3191 u64 ac = readq(&bar0->adapter_control);
3192 ac &= ~(ADAPTER_CNTL_EN);
3193 writeq(ac, &bar0->adapter_control);
3194 ac = readq(&bar0->adapter_control);
3195 schedule_work(&nic->set_link_task);
3196 }
bd1034f0
AR		 3197 /* Check for data parity error */
3198 val64 = readq(&bar0->pic_int_status);
3199 if (val64 & PIC_INT_GPIO) {
3200 val64 = readq(&bar0->gpio_int_reg);
3201 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3202 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3203 schedule_work(&nic->rst_timer_task);
3204 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3205 }
3206 }
3207
3208 /* Check for ring full counter */
3209 if (nic->device_type & XFRAME_II_DEVICE) {
3210 val64 = readq(&bar0->ring_bump_counter1);
3211 for (i=0; i<4; i++) {
3212 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3213 cnt >>= 64 - ((i+1)*16);
3214 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3215 += cnt;
3216 }
3217
3218 val64 = readq(&bar0->ring_bump_counter2);
3219 for (i=0; i<4; i++) {
3220 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3221 cnt >>= 64 - ((i+1)*16);
3222 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3223 += cnt;
3224 }
3225 }
1da177e4
LT		 3226
3227 /* Other type of interrupts are not being handled now, TODO */
3228}
3229
20346722 3230/**
1da177e4 3231 * wait_for_cmd_complete - waits for a command to complete.
20346722 3232 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3233 * s2io_nic structure.
20346722 3234 * Description: Function that waits for a command to Write into RMAC
3235 * ADDR DATA registers to be completed and returns either success or
3236 * error depending on whether the command was complete or not.
1da177e4
LT		 3237 * Return value:
3238 * SUCCESS on success and FAILURE on failure.
3239 */
3240
9fc93a41
SS		 3241static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3242 int bit_state)
1da177e4 3243{
9fc93a41 3244 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3245 u64 val64;
3246
9fc93a41
SS		 3247 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3248 return FAILURE;
3249
3250 do {
c92ca04b 3251 val64 = readq(addr);
9fc93a41
SS		 3252 if (bit_state == S2IO_BIT_RESET) {
3253 if (!(val64 & busy_bit)) {
3254 ret = SUCCESS;
3255 break;
3256 }
3257 } else {
3258 if (!(val64 & busy_bit)) {
3259 ret = SUCCESS;
3260 break;
3261 }
1da177e4 3262 }
c92ca04b
AR		 3263
3264 if(in_interrupt())
9fc93a41 3265 mdelay(delay);
c92ca04b 3266 else
9fc93a41 3267 msleep(delay);
c92ca04b 3268
9fc93a41
SS		 3269 if (++cnt >= 10)
3270 delay = 50;
3271 } while (cnt < 20);
1da177e4
LT		 3272 return ret;
3273}
19a60522
SS		 3274/*
3275 * check_pci_device_id - Checks if the device id is supported
3276 * @id : device id
3277 * Description: Function to check if the pci device id is supported by driver.
3278 * Return value: Actual device id if supported else PCI_ANY_ID
3279 */
3280static u16 check_pci_device_id(u16 id)
3281{
3282 switch (id) {
3283 case PCI_DEVICE_ID_HERC_WIN:
3284 case PCI_DEVICE_ID_HERC_UNI:
3285 return XFRAME_II_DEVICE;
3286 case PCI_DEVICE_ID_S2IO_UNI:
3287 case PCI_DEVICE_ID_S2IO_WIN:
3288 return XFRAME_I_DEVICE;
3289 default:
3290 return PCI_ANY_ID;
3291 }
3292}
1da177e4 3293
20346722 3294/**
3295 * s2io_reset - Resets the card.
1da177e4
LT		 3296 * @sp : private member of the device structure.
3297 * Description: Function to Reset the card. This function then also
20346722 3298 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3299 * the card reset also resets the configuration space.
3300 * Return value:
3301 * void.
3302 */
3303
1ee6dd77 3304static void s2io_reset(struct s2io_nic * sp)
1da177e4 3305{
1ee6dd77 3306 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3307 u64 val64;
5e25b9dd 3308 u16 subid, pci_cmd;
19a60522
SS		 3309 int i;
3310 u16 val16;
3311 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3312 __FUNCTION__, sp->dev->name);
1da177e4 3313
0b1f7ebe 3314 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3315 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3316
19a60522
SS		 3317 if (sp->device_type == XFRAME_II_DEVICE) {
3318 int ret;
3319 ret = pci_set_power_state(sp->pdev, 3);
3320 if (!ret)
3321 ret = pci_set_power_state(sp->pdev, 0);
3322 else {
3323 DBG_PRINT(ERR_DBG,"%s PME based SW_Reset failed!\n",
3324 __FUNCTION__);
3325 goto old_way;
3326 }
3327 msleep(20);
3328 goto new_way;
3329 }
3330old_way:
1da177e4
LT		 3331 val64 = SW_RESET_ALL;
3332 writeq(val64, &bar0->sw_reset);
19a60522 3333new_way:
c92ca04b
AR		 3334 if (strstr(sp->product_name, "CX4")) {
3335 msleep(750);
3336 }
19a60522
SS		 3337 msleep(250);
3338 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3339
19a60522
SS		 3340 /* Restore the PCI state saved during initialization. */
3341 pci_restore_state(sp->pdev);
3342 pci_read_config_word(sp->pdev, 0x2, &val16);
3343 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3344 break;
3345 msleep(200);
3346 }
1da177e4 3347
19a60522
SS		 3348 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3349 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3350 }
3351
3352 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3353
3354 s2io_init_pci(sp);
1da177e4 3355
20346722 3356 /* Set swapper to enable I/O register access */
3357 s2io_set_swapper(sp);
3358
cc6e7c44
RA		 3359 /* Restore the MSIX table entries from local variables */
3360 restore_xmsi_data(sp);
3361
5e25b9dd 3362 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3363 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3364 /* Clear "detected parity error" bit */
303bcb4b 3365 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3366
303bcb4b 3367 /* Clearing PCIX Ecc status register */
3368 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3369
303bcb4b 3370 /* Clearing PCI_STATUS error reflected here */
3371 writeq(BIT(62), &bar0->txpic_int_reg);
3372 }
5e25b9dd 3373
20346722 3374 /* Reset device statistics maintained by OS */
3375 memset(&sp->stats, 0, sizeof (struct net_device_stats));
3376
1da177e4
LT		 3377 /* SXE-002: Configure link and activity LED to turn it off */
3378 subid = sp->pdev->subsystem_device;
541ae68f 3379 if (((subid & 0xFF) >= 0x07) &&
3380 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3381 val64 = readq(&bar0->gpio_control);
3382 val64 |= 0x0000800000000000ULL;
3383 writeq(val64, &bar0->gpio_control);
3384 val64 = 0x0411040400000000ULL;
509a2671 3385 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3386 }
3387
541ae68f 3388 /*
3389 * Clear spurious ECC interrupts that would have occured on
3390 * XFRAME II cards after reset.
3391 */
3392 if (sp->device_type == XFRAME_II_DEVICE) {
3393 val64 = readq(&bar0->pcc_err_reg);
3394 writeq(val64, &bar0->pcc_err_reg);
3395 }
3396
1da177e4
LT		 3397 sp->device_enabled_once = FALSE;
3398}
3399
3400/**
20346722 3401 * s2io_set_swapper - to set the swapper controle on the card
3402 * @sp : private member of the device structure,
1da177e4 3403 * pointer to the s2io_nic structure.
20346722 3404 * Description: Function to set the swapper control on the card
1da177e4
LT		 3405 * correctly depending on the 'endianness' of the system.
3406 * Return value:
3407 * SUCCESS on success and FAILURE on failure.
3408 */
3409
1ee6dd77 3410static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3411{
3412 struct net_device *dev = sp->dev;
1ee6dd77 3413 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3414 u64 val64, valt, valr;
3415
20346722 3416 /*
1da177e4
LT		 3417 * Set proper endian settings and verify the same by reading
3418 * the PIF Feed-back register.
3419 */
3420
3421 val64 = readq(&bar0->pif_rd_swapper_fb);
3422 if (val64 != 0x0123456789ABCDEFULL) {
3423 int i = 0;
3424 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3425 0x8100008181000081ULL, /* FE=1, SE=0 */
3426 0x4200004242000042ULL, /* FE=0, SE=1 */
3427 0}; /* FE=0, SE=0 */
3428
3429 while(i<4) {
3430 writeq(value[i], &bar0->swapper_ctrl);
3431 val64 = readq(&bar0->pif_rd_swapper_fb);
3432 if (val64 == 0x0123456789ABCDEFULL)
3433 break;
3434 i++;
3435 }
3436 if (i == 4) {
3437 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3438 dev->name);
3439 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3440 (unsigned long long) val64);
3441 return FAILURE;
3442 }
3443 valr = value[i];
3444 } else {
3445 valr = readq(&bar0->swapper_ctrl);
3446 }
3447
3448 valt = 0x0123456789ABCDEFULL;
3449 writeq(valt, &bar0->xmsi_address);
3450 val64 = readq(&bar0->xmsi_address);
3451
3452 if(val64 != valt) {
3453 int i = 0;
3454 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3455 0x0081810000818100ULL, /* FE=1, SE=0 */
3456 0x0042420000424200ULL, /* FE=0, SE=1 */
3457 0}; /* FE=0, SE=0 */
3458
3459 while(i<4) {
3460 writeq((value[i] | valr), &bar0->swapper_ctrl);
3461 writeq(valt, &bar0->xmsi_address);
3462 val64 = readq(&bar0->xmsi_address);
3463 if(val64 == valt)
3464 break;
3465 i++;
3466 }
3467 if(i == 4) {
20346722 3468 unsigned long long x = val64;
1da177e4 3469 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3470 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3471 return FAILURE;
3472 }
3473 }
3474 val64 = readq(&bar0->swapper_ctrl);
3475 val64 &= 0xFFFF000000000000ULL;
3476
3477#ifdef __BIG_ENDIAN
20346722 3478 /*
3479 * The device by default set to a big endian format, so a
1da177e4
LT		 3480 * big endian driver need not set anything.
3481 */
3482 val64 |= (SWAPPER_CTRL_TXP_FE |
3483 SWAPPER_CTRL_TXP_SE |
3484 SWAPPER_CTRL_TXD_R_FE |
3485 SWAPPER_CTRL_TXD_W_FE |
3486 SWAPPER_CTRL_TXF_R_FE |
3487 SWAPPER_CTRL_RXD_R_FE |
3488 SWAPPER_CTRL_RXD_W_FE |
3489 SWAPPER_CTRL_RXF_W_FE |
3490 SWAPPER_CTRL_XMSI_FE |
1da177e4 3491 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3492 if (sp->intr_type == INTA)
cc6e7c44 3493 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3494 writeq(val64, &bar0->swapper_ctrl);
3495#else
20346722 3496 /*
1da177e4 3497 * Initially we enable all bits to make it accessible by the
20346722 3498 * driver, then we selectively enable only those bits that
1da177e4
LT		 3499 * we want to set.
3500 */
3501 val64 |= (SWAPPER_CTRL_TXP_FE |
3502 SWAPPER_CTRL_TXP_SE |
3503 SWAPPER_CTRL_TXD_R_FE |
3504 SWAPPER_CTRL_TXD_R_SE |
3505 SWAPPER_CTRL_TXD_W_FE |
3506 SWAPPER_CTRL_TXD_W_SE |
3507 SWAPPER_CTRL_TXF_R_FE |
3508 SWAPPER_CTRL_RXD_R_FE |
3509 SWAPPER_CTRL_RXD_R_SE |
3510 SWAPPER_CTRL_RXD_W_FE |
3511 SWAPPER_CTRL_RXD_W_SE |
3512 SWAPPER_CTRL_RXF_W_FE |
3513 SWAPPER_CTRL_XMSI_FE |
1da177e4 3514 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3515 if (sp->intr_type == INTA)
3516 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3517 writeq(val64, &bar0->swapper_ctrl);
3518#endif
3519 val64 = readq(&bar0->swapper_ctrl);
3520
20346722 3521 /*
3522 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3523 * feedback register.
3524 */
3525 val64 = readq(&bar0->pif_rd_swapper_fb);
3526 if (val64 != 0x0123456789ABCDEFULL) {
3527 /* Endian settings are incorrect, calls for another dekko. */
3528 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3529 dev->name);
3530 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3531 (unsigned long long) val64);
3532 return FAILURE;
3533 }
3534
3535 return SUCCESS;
3536}
3537
1ee6dd77 3538static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3539{
1ee6dd77 3540 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3541 u64 val64;
3542 int ret = 0, cnt = 0;
3543
3544 do {
3545 val64 = readq(&bar0->xmsi_access);
3546 if (!(val64 & BIT(15)))
3547 break;
3548 mdelay(1);
3549 cnt++;
3550 } while(cnt < 5);
3551 if (cnt == 5) {
3552 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3553 ret = 1;
3554 }
3555
3556 return ret;
3557}
3558
1ee6dd77 3559static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3560{
1ee6dd77 3561 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3562 u64 val64;
3563 int i;
3564
75c30b13 3565 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3566 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3567 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3568 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3569 writeq(val64, &bar0->xmsi_access);
3570 if (wait_for_msix_trans(nic, i)) {
3571 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3572 continue;
3573 }
3574 }
3575}
3576
1ee6dd77 3577static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3578{
1ee6dd77 3579 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3580 u64 val64, addr, data;
3581 int i;
3582
3583 /* Store and display */
75c30b13 3584 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3585 val64 = (BIT(15) | vBIT(i, 26, 6));
3586 writeq(val64, &bar0->xmsi_access);
3587 if (wait_for_msix_trans(nic, i)) {
3588 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3589 continue;
3590 }
3591 addr = readq(&bar0->xmsi_address);
3592 data = readq(&bar0->xmsi_data);
3593 if (addr && data) {
3594 nic->msix_info[i].addr = addr;
3595 nic->msix_info[i].data = data;
3596 }
3597 }
3598}
3599
1ee6dd77 3600int s2io_enable_msi(struct s2io_nic *nic)
cc6e7c44 3601{
1ee6dd77 3602 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3603 u16 msi_ctrl, msg_val;
3604 struct config_param *config = &nic->config;
3605 struct net_device *dev = nic->dev;
3606 u64 val64, tx_mat, rx_mat;
3607 int i, err;
3608
3609 val64 = readq(&bar0->pic_control);
3610 val64 &= ~BIT(1);
3611 writeq(val64, &bar0->pic_control);
3612
3613 err = pci_enable_msi(nic->pdev);
3614 if (err) {
3615 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3616 nic->dev->name);
3617 return err;
3618 }
3619
3620 /*
3621 * Enable MSI and use MSI-1 in stead of the standard MSI-0
3622 * for interrupt handling.
3623 */
3624 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3625 msg_val ^= 0x1;
3626 pci_write_config_word(nic->pdev, 0x4c, msg_val);
3627 pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3628
3629 pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3630 msi_ctrl |= 0x10;
3631 pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3632
3633 /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3634 tx_mat = readq(&bar0->tx_mat0_n[0]);
3635 for (i=0; i<config->tx_fifo_num; i++) {
3636 tx_mat |= TX_MAT_SET(i, 1);
3637 }
3638 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3639
3640 rx_mat = readq(&bar0->rx_mat);
3641 for (i=0; i<config->rx_ring_num; i++) {
3642 rx_mat |= RX_MAT_SET(i, 1);
3643 }
3644 writeq(rx_mat, &bar0->rx_mat);
3645
3646 dev->irq = nic->pdev->irq;
3647 return 0;
3648}
3649
1ee6dd77 3650static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3651{
1ee6dd77 3652 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3653 u64 tx_mat, rx_mat;
3654 u16 msi_control; /* Temp variable */
3655 int ret, i, j, msix_indx = 1;
3656
3657 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3658 GFP_KERNEL);
3659 if (nic->entries == NULL) {
3660 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3661 return -ENOMEM;
3662 }
3663 memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3664
3665 nic->s2io_entries =
3666 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3667 GFP_KERNEL);
3668 if (nic->s2io_entries == NULL) {
3669 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3670 kfree(nic->entries);
3671 return -ENOMEM;
3672 }
3673 memset(nic->s2io_entries, 0,
3674 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3675
3676 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3677 nic->entries[i].entry = i;
3678 nic->s2io_entries[i].entry = i;
3679 nic->s2io_entries[i].arg = NULL;
3680 nic->s2io_entries[i].in_use = 0;
3681 }
3682
3683 tx_mat = readq(&bar0->tx_mat0_n[0]);
3684 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3685 tx_mat |= TX_MAT_SET(i, msix_indx);
3686 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3687 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3688 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3689 }
3690 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3691
3692 if (!nic->config.bimodal) {
3693 rx_mat = readq(&bar0->rx_mat);
3694 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3695 rx_mat |= RX_MAT_SET(j, msix_indx);
3696 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3697 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3698 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3699 }
3700 writeq(rx_mat, &bar0->rx_mat);
3701 } else {
3702 tx_mat = readq(&bar0->tx_mat0_n[7]);
3703 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3704 tx_mat |= TX_MAT_SET(i, msix_indx);
3705 nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3706 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3707 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3708 }
3709 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3710 }
3711
c92ca04b 3712 nic->avail_msix_vectors = 0;
cc6e7c44 3713 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3714 /* We fail init if error or we get less vectors than min required */
3715 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3716 nic->avail_msix_vectors = ret;
3717 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3718 }
cc6e7c44
RA		 3719 if (ret) {
3720 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3721 kfree(nic->entries);
3722 kfree(nic->s2io_entries);
3723 nic->entries = NULL;
3724 nic->s2io_entries = NULL;
c92ca04b 3725 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3726 return -ENOMEM;
3727 }
c92ca04b
AR		 3728 if (!nic->avail_msix_vectors)
3729 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3730
3731 /*
3732 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3733 * in the herc NIC. (Temp change, needs to be removed later)
3734 */
3735 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3736 msi_control |= 0x1; /* Enable MSI */
3737 pci_write_config_word(nic->pdev, 0x42, msi_control);
3738
3739 return 0;
3740}
3741
1da177e4
LT		 3742/* ********************************************************* *
3743 * Functions defined below concern the OS part of the driver *
3744 * ********************************************************* */
3745
20346722 3746/**
1da177e4
LT		 3747 * s2io_open - open entry point of the driver
3748 * @dev : pointer to the device structure.
3749 * Description:
3750 * This function is the open entry point of the driver. It mainly calls a
3751 * function to allocate Rx buffers and inserts them into the buffer
20346722 3752 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3753 * Return value:
3754 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3755 * file on failure.
3756 */
3757
ac1f60db 3758static int s2io_open(struct net_device *dev)
1da177e4 3759{
1ee6dd77 3760 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3761 int err = 0;
3762
20346722 3763 /*
3764 * Make sure you have link off by default every time
1da177e4
LT		 3765 * Nic is initialized
3766 */
3767 netif_carrier_off(dev);
0b1f7ebe 3768 sp->last_link_state = 0;
1da177e4
LT		 3769
3770 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3771 err = s2io_card_up(sp);
3772 if (err) {
1da177e4
LT		 3773 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3774 dev->name);
e6a8fee2 3775 goto hw_init_failed;
1da177e4
LT		 3776 }
3777
3778 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3779 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3780 s2io_card_down(sp);
20346722 3781 err = -ENODEV;
e6a8fee2 3782 goto hw_init_failed;
1da177e4
LT		 3783 }
3784
3785 netif_start_queue(dev);
3786 return 0;
20346722 3787
20346722 3788hw_init_failed:
cc6e7c44
RA		 3789 if (sp->intr_type == MSI_X) {
3790 if (sp->entries)
3791 kfree(sp->entries);
3792 if (sp->s2io_entries)
3793 kfree(sp->s2io_entries);
3794 }
20346722 3795 return err;
1da177e4
LT		 3796}
3797
3798/**
3799 * s2io_close -close entry point of the driver
3800 * @dev : device pointer.
3801 * Description:
3802 * This is the stop entry point of the driver. It needs to undo exactly
3803 * whatever was done by the open entry point,thus it's usually referred to
3804 * as the close function.Among other things this function mainly stops the
3805 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3806 * Return value:
3807 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3808 * file on failure.
3809 */
3810
ac1f60db 3811static int s2io_close(struct net_device *dev)
1da177e4 3812{
1ee6dd77 3813 struct s2io_nic *sp = dev->priv;
cc6e7c44 3814
1da177e4
LT		 3815 netif_stop_queue(dev);
3816 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3817 s2io_card_down(sp);
cc6e7c44 3818
1da177e4
LT		 3819 sp->device_close_flag = TRUE; /* Device is shut down. */
3820 return 0;
3821}
3822
3823/**
3824 * s2io_xmit - Tx entry point of te driver
3825 * @skb : the socket buffer containing the Tx data.
3826 * @dev : device pointer.
3827 * Description :
3828 * This function is the Tx entry point of the driver. S2IO NIC supports
3829 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3830 * NOTE: when device cant queue the pkt,just the trans_start variable will
3831 * not be upadted.
3832 * Return value:
3833 * 0 on success & 1 on failure.
3834 */
3835
ac1f60db 3836static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 3837{
1ee6dd77 3838 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3839 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3840 register u64 val64;
1ee6dd77
RB		 3841 struct TxD *txdp;
3842 struct TxFIFO_element __iomem *tx_fifo;
1da177e4 3843 unsigned long flags;
be3a6b02 3844 u16 vlan_tag = 0;
3845 int vlan_priority = 0;
1ee6dd77 3846 struct mac_info *mac_control;
1da177e4 3847 struct config_param *config;
75c30b13 3848 int offload_type;
1da177e4
LT		 3849
3850 mac_control = &sp->mac_control;
3851 config = &sp->config;
3852
20346722 3853 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
1da177e4 3854 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 3855 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 3856 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3857 dev->name);
3858 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722 3859 dev_kfree_skb(skb);
3860 return 0;
1da177e4
LT		 3861 }
3862
3863 queue = 0;
1da177e4 3864
be3a6b02 3865 /* Get Fifo number to Transmit based on vlan priority */
3866 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3867 vlan_tag = vlan_tx_tag_get(skb);
3868 vlan_priority = vlan_tag >> 13;
3869 queue = config->fifo_mapping[vlan_priority];
3870 }
3871
20346722 3872 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3873 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
1ee6dd77 3874 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
20346722 3875 list_virt_addr;
3876
3877 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3878 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3879 if (txdp->Host_Control ||
3880 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3881 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3882 netif_stop_queue(dev);
3883 dev_kfree_skb(skb);
3884 spin_unlock_irqrestore(&sp->tx_lock, flags);
3885 return 0;
3886 }
0b1f7ebe 3887
3888 /* A buffer with no data will be dropped */
3889 if (!skb->len) {
3890 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3891 dev_kfree_skb(skb);
3892 spin_unlock_irqrestore(&sp->tx_lock, flags);
3893 return 0;
3894 }
3895
75c30b13 3896 offload_type = s2io_offload_type(skb);
75c30b13 3897 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3898 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 3899 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 3900 }
84fa7933 3901 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 3902 txdp->Control_2 |=
3903 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3904 TXD_TX_CKO_UDP_EN);
3905 }
fed5eccd
AR		 3906 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3907 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 3908 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 3909
be3a6b02 3910 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3911 txdp->Control_2 |= TXD_VLAN_ENABLE;
3912 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3913 }
3914
fed5eccd 3915 frg_len = skb->len - skb->data_len;
75c30b13 3916 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 3917 int ufo_size;
3918
75c30b13 3919 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 3920 ufo_size &= ~7;
3921 txdp->Control_1 |= TXD_UFO_EN;
3922 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3923 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3924#ifdef __BIG_ENDIAN
3925 sp->ufo_in_band_v[put_off] =
3926 (u64)skb_shinfo(skb)->ip6_frag_id;
3927#else
3928 sp->ufo_in_band_v[put_off] =
3929 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3930#endif
3931 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3932 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3933 sp->ufo_in_band_v,
3934 sizeof(u64), PCI_DMA_TODEVICE);
3935 txdp++;
fed5eccd 3936 }
1da177e4 3937
fed5eccd
AR		 3938 txdp->Buffer_Pointer = pci_map_single
3939 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3940 txdp->Host_Control = (unsigned long) skb;
3941 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 3942 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3943 txdp->Control_1 |= TXD_UFO_EN;
3944
3945 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 3946 /* For fragmented SKB. */
3947 for (i = 0; i < frg_cnt; i++) {
3948 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 3949 /* A '0' length fragment will be ignored */
3950 if (!frag->size)
3951 continue;
1da177e4
LT		 3952 txdp++;
3953 txdp->Buffer_Pointer = (u64) pci_map_page
3954 (sp->pdev, frag->page, frag->page_offset,
3955 frag->size, PCI_DMA_TODEVICE);
efd51b5c 3956 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 3957 if (offload_type == SKB_GSO_UDP)
fed5eccd 3958 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 3959 }
3960 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3961
75c30b13 3962 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3963 frg_cnt++; /* as Txd0 was used for inband header */
3964
1da177e4 3965 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 3966 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 3967 writeq(val64, &tx_fifo->TxDL_Pointer);
3968
3969 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3970 TX_FIFO_LAST_LIST);
75c30b13 3971 if (offload_type)
fed5eccd 3972 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 3973
1da177e4
LT		 3974 writeq(val64, &tx_fifo->List_Control);
3975
303bcb4b 3976 mmiowb();
3977
1da177e4 3978 put_off++;
863c11a9
AR		 3979 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3980 put_off = 0;
20346722 3981 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 3982
3983 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 3984 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 3985 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 3986 DBG_PRINT(TX_DBG,
3987 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3988 put_off, get_off);
3989 netif_stop_queue(dev);
3990 }
3991
3992 dev->trans_start = jiffies;
3993 spin_unlock_irqrestore(&sp->tx_lock, flags);
3994
3995 return 0;
3996}
3997
25fff88e 3998static void
3999s2io_alarm_handle(unsigned long data)
4000{
1ee6dd77 4001 struct s2io_nic *sp = (struct s2io_nic *)data;
25fff88e 4002
4003 alarm_intr_handler(sp);
4004 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4005}
4006
1ee6dd77 4007static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4008{
4009 int rxb_size, level;
4010
4011 if (!sp->lro) {
4012 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4013 level = rx_buffer_level(sp, rxb_size, rng_n);
4014
4015 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4016 int ret;
4017 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4018 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4019 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4020 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4021 __FUNCTION__);
4022 clear_bit(0, (&sp->tasklet_status));
4023 return -1;
4024 }
4025 clear_bit(0, (&sp->tasklet_status));
4026 } else if (level == LOW)
4027 tasklet_schedule(&sp->task);
4028
4029 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4030 DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4031 DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4032 }
4033 return 0;
4034}
4035
7d12e780 4036static irqreturn_t s2io_msi_handle(int irq, void *dev_id)
cc6e7c44
RA		 4037{
4038 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77 4039 struct s2io_nic *sp = dev->priv;
cc6e7c44 4040 int i;
1ee6dd77 4041 struct mac_info *mac_control;
cc6e7c44
RA		 4042 struct config_param *config;
4043
4044 atomic_inc(&sp->isr_cnt);
4045 mac_control = &sp->mac_control;
4046 config = &sp->config;
4047 DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4048
4049 /* If Intr is because of Rx Traffic */
4050 for (i = 0; i < config->rx_ring_num; i++)
4051 rx_intr_handler(&mac_control->rings[i]);
4052
4053 /* If Intr is because of Tx Traffic */
4054 for (i = 0; i < config->tx_fifo_num; i++)
4055 tx_intr_handler(&mac_control->fifos[i]);
4056
4057 /*
4058 * If the Rx buffer count is below the panic threshold then
4059 * reallocate the buffers from the interrupt handler itself,
4060 * else schedule a tasklet to reallocate the buffers.
4061 */
75c30b13
AR		 4062 for (i = 0; i < config->rx_ring_num; i++)
4063 s2io_chk_rx_buffers(sp, i);
cc6e7c44
RA		 4064
4065 atomic_dec(&sp->isr_cnt);
4066 return IRQ_HANDLED;
4067}
4068
7d12e780 4069static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4070{
1ee6dd77
RB		 4071 struct ring_info *ring = (struct ring_info *)dev_id;
4072 struct s2io_nic *sp = ring->nic;
cc6e7c44
RA		 4073
4074 atomic_inc(&sp->isr_cnt);
cc6e7c44 4075
75c30b13
AR		 4076 rx_intr_handler(ring);
4077 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4078
cc6e7c44 4079 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4080 return IRQ_HANDLED;
4081}
4082
7d12e780 4083static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4084{
1ee6dd77
RB		 4085 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4086 struct s2io_nic *sp = fifo->nic;
cc6e7c44
RA		 4087
4088 atomic_inc(&sp->isr_cnt);
4089 tx_intr_handler(fifo);
4090 atomic_dec(&sp->isr_cnt);
4091 return IRQ_HANDLED;
4092}
1ee6dd77 4093static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4094{
1ee6dd77 4095 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4096 u64 val64;
4097
4098 val64 = readq(&bar0->pic_int_status);
4099 if (val64 & PIC_INT_GPIO) {
4100 val64 = readq(&bar0->gpio_int_reg);
4101 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4102 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4103 /*
4104 * This is unstable state so clear both up/down
4105 * interrupt and adapter to re-evaluate the link state.
4106 */
a371a07d 4107 val64 |= GPIO_INT_REG_LINK_DOWN;
4108 val64 |= GPIO_INT_REG_LINK_UP;
4109 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4110 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4111 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4112 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4113 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4114 }
c92ca04b
AR		 4115 else if (val64 & GPIO_INT_REG_LINK_UP) {
4116 val64 = readq(&bar0->adapter_status);
c92ca04b 4117 /* Enable Adapter */
19a60522
SS		 4118 val64 = readq(&bar0->adapter_control);
4119 val64 |= ADAPTER_CNTL_EN;
4120 writeq(val64, &bar0->adapter_control);
4121 val64 |= ADAPTER_LED_ON;
4122 writeq(val64, &bar0->adapter_control);
4123 if (!sp->device_enabled_once)
4124 sp->device_enabled_once = 1;
c92ca04b 4125
19a60522
SS		 4126 s2io_link(sp, LINK_UP);
4127 /*
4128 * unmask link down interrupt and mask link-up
4129 * intr
4130 */
4131 val64 = readq(&bar0->gpio_int_mask);
4132 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4133 val64 |= GPIO_INT_MASK_LINK_UP;
4134 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4135
c92ca04b
AR		 4136 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4137 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4138 s2io_link(sp, LINK_DOWN);
4139 /* Link is down so unmaks link up interrupt */
4140 val64 = readq(&bar0->gpio_int_mask);
4141 val64 &= ~GPIO_INT_MASK_LINK_UP;
4142 val64 |= GPIO_INT_MASK_LINK_DOWN;
4143 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4144
4145 /* turn off LED */
4146 val64 = readq(&bar0->adapter_control);
4147 val64 = val64 &(~ADAPTER_LED_ON);
4148 writeq(val64, &bar0->adapter_control);
a371a07d 4149 }
4150 }
c92ca04b 4151 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4152}
4153
1da177e4
LT		 4154/**
4155 * s2io_isr - ISR handler of the device .
4156 * @irq: the irq of the device.
4157 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4158 * Description: This function is the ISR handler of the device. It
4159 * identifies the reason for the interrupt and calls the relevant
4160 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4161 * recv buffers, if their numbers are below the panic value which is
4162 * presently set to 25% of the original number of rcv buffers allocated.
4163 * Return value:
20346722 4164 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4165 * IRQ_NONE: will be returned if interrupt is not from our device
4166 */
7d12e780 4167static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4168{
4169 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4170 struct s2io_nic *sp = dev->priv;
4171 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4172 int i;
19a60522 4173 u64 reason = 0;
1ee6dd77 4174 struct mac_info *mac_control;
1da177e4
LT		 4175 struct config_param *config;
4176
7ba013ac 4177 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4178 mac_control = &sp->mac_control;
4179 config = &sp->config;
4180
20346722 4181 /*
1da177e4
LT		 4182 * Identify the cause for interrupt and call the appropriate
4183 * interrupt handler. Causes for the interrupt could be;
4184 * 1. Rx of packet.
4185 * 2. Tx complete.
4186 * 3. Link down.
20346722 4187 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4188 */
4189 reason = readq(&bar0->general_int_status);
4190
4191 if (!reason) {
19a60522
SS		 4192 /* The interrupt was not raised by us. */
4193 atomic_dec(&sp->isr_cnt);
4194 return IRQ_NONE;
4195 }
4196 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4197 /* Disable device and get out */
7ba013ac 4198 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4199 return IRQ_NONE;
4200 }
5d3213cc 4201
db874e65
SS		 4202 if (napi) {
4203 if (reason & GEN_INTR_RXTRAFFIC) {
19a60522 4204 if ( likely ( netif_rx_schedule_prep(dev)) ) {
db874e65 4205 __netif_rx_schedule(dev);
19a60522 4206 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
db874e65 4207 }
19a60522
SS		 4208 else
4209 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
db874e65
SS		 4210 }
4211 } else {
4212 /*
4213 * Rx handler is called by default, without checking for the
4214 * cause of interrupt.
4215 * rx_traffic_int reg is an R1 register, writing all 1's
4216 * will ensure that the actual interrupt causing bit get's
4217 * cleared and hence a read can be avoided.
4218 */
19a60522
SS		 4219 if (reason & GEN_INTR_RXTRAFFIC)
4220 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4221
db874e65
SS		 4222 for (i = 0; i < config->rx_ring_num; i++) {
4223 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4224 }
4225 }
1da177e4 4226
863c11a9
AR		 4227 /*
4228 * tx_traffic_int reg is an R1 register, writing all 1's
4229 * will ensure that the actual interrupt causing bit get's
4230 * cleared and hence a read can be avoided.
4231 */
19a60522
SS		 4232 if (reason & GEN_INTR_TXTRAFFIC)
4233 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
fe113638 4234
863c11a9
AR		 4235 for (i = 0; i < config->tx_fifo_num; i++)
4236 tx_intr_handler(&mac_control->fifos[i]);
20346722 4237
a371a07d 4238 if (reason & GEN_INTR_TXPIC)
4239 s2io_txpic_intr_handle(sp);
20346722 4240 /*
4241 * If the Rx buffer count is below the panic threshold then
4242 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4243 * else schedule a tasklet to reallocate the buffers.
4244 */
db874e65
SS		 4245 if (!napi) {
4246 for (i = 0; i < config->rx_ring_num; i++)
4247 s2io_chk_rx_buffers(sp, i);
4248 }
4249
4250 writeq(0, &bar0->general_int_mask);
4251 readl(&bar0->general_int_status);
4252
7ba013ac 4253 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4254 return IRQ_HANDLED;
4255}
4256
7ba013ac 4257/**
4258 * s2io_updt_stats -
4259 */
1ee6dd77 4260static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4261{
1ee6dd77 4262 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4263 u64 val64;
4264 int cnt = 0;
4265
4266 if (atomic_read(&sp->card_state) == CARD_UP) {
4267 /* Apprx 30us on a 133 MHz bus */
4268 val64 = SET_UPDT_CLICKS(10) |
4269 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4270 writeq(val64, &bar0->stat_cfg);
4271 do {
4272 udelay(100);
4273 val64 = readq(&bar0->stat_cfg);
4274 if (!(val64 & BIT(0)))
4275 break;
4276 cnt++;
4277 if (cnt == 5)
4278 break; /* Updt failed */
4279 } while(1);
75c30b13 4280 } else {
1ee6dd77 4281 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
7ba013ac 4282 }
4283}
4284
1da177e4 4285/**
20346722 4286 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4287 * @dev : pointer to the device structure.
4288 * Description:
20346722 4289 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4290 * structure and returns a pointer to the same.
4291 * Return value:
4292 * pointer to the updated net_device_stats structure.
4293 */
4294
ac1f60db 4295static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4296{
1ee6dd77
RB		 4297 struct s2io_nic *sp = dev->priv;
4298 struct mac_info *mac_control;
1da177e4
LT		 4299 struct config_param *config;
4300
20346722 4301
1da177e4
LT		 4302 mac_control = &sp->mac_control;
4303 config = &sp->config;
4304
7ba013ac 4305 /* Configure Stats for immediate updt */
4306 s2io_updt_stats(sp);
4307
4308 sp->stats.tx_packets =
4309 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722 4310 sp->stats.tx_errors =
4311 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4312 sp->stats.rx_errors =
ee705dba 4313 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722 4314 sp->stats.multicast =
4315 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4316 sp->stats.rx_length_errors =
ee705dba 4317 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4318
4319 return (&sp->stats);
4320}
4321
4322/**
4323 * s2io_set_multicast - entry point for multicast address enable/disable.
4324 * @dev : pointer to the device structure
4325 * Description:
20346722 4326 * This function is a driver entry point which gets called by the kernel
4327 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4328 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4329 * determine, if multicast address must be enabled or if promiscuous mode
4330 * is to be disabled etc.
4331 * Return value:
4332 * void.
4333 */
4334
4335static void s2io_set_multicast(struct net_device *dev)
4336{
4337 int i, j, prev_cnt;
4338 struct dev_mc_list *mclist;
1ee6dd77
RB		 4339 struct s2io_nic *sp = dev->priv;
4340 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4341 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4342 0xfeffffffffffULL;
4343 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4344 void __iomem *add;
4345
4346 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4347 /* Enable all Multicast addresses */
4348 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4349 &bar0->rmac_addr_data0_mem);
4350 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4351 &bar0->rmac_addr_data1_mem);
4352 val64 = RMAC_ADDR_CMD_MEM_WE |
4353 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4354 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4355 writeq(val64, &bar0->rmac_addr_cmd_mem);
4356 /* Wait till command completes */
c92ca04b 4357 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4358 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4359 S2IO_BIT_RESET);
1da177e4
LT		 4360
4361 sp->m_cast_flg = 1;
4362 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4363 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4364 /* Disable all Multicast addresses */
4365 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4366 &bar0->rmac_addr_data0_mem);
5e25b9dd 4367 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4368 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4369 val64 = RMAC_ADDR_CMD_MEM_WE |
4370 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4371 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4372 writeq(val64, &bar0->rmac_addr_cmd_mem);
4373 /* Wait till command completes */
c92ca04b 4374 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4375 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4376 S2IO_BIT_RESET);
1da177e4
LT		 4377
4378 sp->m_cast_flg = 0;
4379 sp->all_multi_pos = 0;
4380 }
4381
4382 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4383 /* Put the NIC into promiscuous mode */
4384 add = &bar0->mac_cfg;
4385 val64 = readq(&bar0->mac_cfg);
4386 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4387
4388 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4389 writel((u32) val64, add);
4390 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4391 writel((u32) (val64 >> 32), (add + 4));
4392
926930b2
SS		 4393 if (vlan_tag_strip != 1) {
4394 val64 = readq(&bar0->rx_pa_cfg);
4395 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4396 writeq(val64, &bar0->rx_pa_cfg);
4397 vlan_strip_flag = 0;
4398 }
4399
1da177e4
LT		 4400 val64 = readq(&bar0->mac_cfg);
4401 sp->promisc_flg = 1;
776bd20f 4402 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4403 dev->name);
4404 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4405 /* Remove the NIC from promiscuous mode */
4406 add = &bar0->mac_cfg;
4407 val64 = readq(&bar0->mac_cfg);
4408 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4409
4410 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4411 writel((u32) val64, add);
4412 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4413 writel((u32) (val64 >> 32), (add + 4));
4414
926930b2
SS		 4415 if (vlan_tag_strip != 0) {
4416 val64 = readq(&bar0->rx_pa_cfg);
4417 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4418 writeq(val64, &bar0->rx_pa_cfg);
4419 vlan_strip_flag = 1;
4420 }
4421
1da177e4
LT		 4422 val64 = readq(&bar0->mac_cfg);
4423 sp->promisc_flg = 0;
776bd20f 4424 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4425 dev->name);
4426 }
4427
4428 /* Update individual M_CAST address list */
4429 if ((!sp->m_cast_flg) && dev->mc_count) {
4430 if (dev->mc_count >
4431 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4432 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4433 dev->name);
4434 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4435 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4436 return;
4437 }
4438
4439 prev_cnt = sp->mc_addr_count;
4440 sp->mc_addr_count = dev->mc_count;
4441
4442 /* Clear out the previous list of Mc in the H/W. */
4443 for (i = 0; i < prev_cnt; i++) {
4444 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4445 &bar0->rmac_addr_data0_mem);
4446 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4447 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4448 val64 = RMAC_ADDR_CMD_MEM_WE |
4449 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4450 RMAC_ADDR_CMD_MEM_OFFSET
4451 (MAC_MC_ADDR_START_OFFSET + i);
4452 writeq(val64, &bar0->rmac_addr_cmd_mem);
4453
4454 /* Wait for command completes */
c92ca04b 4455 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4456 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4457 S2IO_BIT_RESET)) {
1da177e4
LT		 4458 DBG_PRINT(ERR_DBG, "%s: Adding ",
4459 dev->name);
4460 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4461 return;
4462 }
4463 }
4464
4465 /* Create the new Rx filter list and update the same in H/W. */
4466 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4467 i++, mclist = mclist->next) {
4468 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4469 ETH_ALEN);
a7a80d5a 4470 mac_addr = 0;
1da177e4
LT		 4471 for (j = 0; j < ETH_ALEN; j++) {
4472 mac_addr |= mclist->dmi_addr[j];
4473 mac_addr <<= 8;
4474 }
4475 mac_addr >>= 8;
4476 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4477 &bar0->rmac_addr_data0_mem);
4478 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4479 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4480 val64 = RMAC_ADDR_CMD_MEM_WE |
4481 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4482 RMAC_ADDR_CMD_MEM_OFFSET
4483 (i + MAC_MC_ADDR_START_OFFSET);
4484 writeq(val64, &bar0->rmac_addr_cmd_mem);
4485
4486 /* Wait for command completes */
c92ca04b 4487 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4488 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4489 S2IO_BIT_RESET)) {
1da177e4
LT		 4490 DBG_PRINT(ERR_DBG, "%s: Adding ",
4491 dev->name);
4492 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4493 return;
4494 }
4495 }
4496 }
4497}
4498
4499/**
20346722 4500 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4501 * @dev : pointer to the device structure.
4502 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4503 * Description : This procedure will program the Xframe to receive
1da177e4 4504 * frames with new Mac Address
20346722 4505 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4506 * as defined in errno.h file on failure.
4507 */
4508
26df54bf 4509static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4 4510{
1ee6dd77
RB		 4511 struct s2io_nic *sp = dev->priv;
4512 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4513 register u64 val64, mac_addr = 0;
4514 int i;
4515
20346722 4516 /*
1da177e4
LT		 4517 * Set the new MAC address as the new unicast filter and reflect this
4518 * change on the device address registered with the OS. It will be
20346722 4519 * at offset 0.
1da177e4
LT		 4520 */
4521 for (i = 0; i < ETH_ALEN; i++) {
4522 mac_addr <<= 8;
4523 mac_addr |= addr[i];
4524 }
4525
4526 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4527 &bar0->rmac_addr_data0_mem);
4528
4529 val64 =
4530 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4531 RMAC_ADDR_CMD_MEM_OFFSET(0);
4532 writeq(val64, &bar0->rmac_addr_cmd_mem);
4533 /* Wait till command completes */
c92ca04b 4534 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 4535 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
1da177e4
LT		 4536 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4537 return FAILURE;
4538 }
4539
4540 return SUCCESS;
4541}
4542
4543/**
20346722 4544 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4545 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4546 * @info: pointer to the structure with parameters given by ethtool to set
4547 * link information.
4548 * Description:
20346722 4549 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4550 * the NIC.
4551 * Return value:
4552 * 0 on success.
4553*/
4554
4555static int s2io_ethtool_sset(struct net_device *dev,
4556 struct ethtool_cmd *info)
4557{
1ee6dd77 4558 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4559 if ((info->autoneg == AUTONEG_ENABLE) ||
4560 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4561 return -EINVAL;
4562 else {
4563 s2io_close(sp->dev);
4564 s2io_open(sp->dev);
4565 }
4566
4567 return 0;
4568}
4569
4570/**
20346722 4571 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4572 * @sp : private member of the device structure, pointer to the
4573 * s2io_nic structure.
4574 * @info : pointer to the structure with parameters given by ethtool
4575 * to return link information.
4576 * Description:
4577 * Returns link specific information like speed, duplex etc.. to ethtool.
4578 * Return value :
4579 * return 0 on success.
4580 */
4581
4582static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4583{
1ee6dd77 4584 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4585 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4586 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4587 info->port = PORT_FIBRE;
4588 /* info->transceiver?? TODO */
4589
4590 if (netif_carrier_ok(sp->dev)) {
4591 info->speed = 10000;
4592 info->duplex = DUPLEX_FULL;
4593 } else {
4594 info->speed = -1;
4595 info->duplex = -1;
4596 }
4597
4598 info->autoneg = AUTONEG_DISABLE;
4599 return 0;
4600}
4601
4602/**
20346722 4603 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4604 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4605 * s2io_nic structure.
4606 * @info : pointer to the structure with parameters given by ethtool to
4607 * return driver information.
4608 * Description:
4609 * Returns driver specefic information like name, version etc.. to ethtool.
4610 * Return value:
4611 * void
4612 */
4613
4614static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4615 struct ethtool_drvinfo *info)
4616{
1ee6dd77 4617 struct s2io_nic *sp = dev->priv;
1da177e4 4618
dbc2309d
JL		 4619 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4620 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4621 strncpy(info->fw_version, "", sizeof(info->fw_version));
4622 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4623 info->regdump_len = XENA_REG_SPACE;
4624 info->eedump_len = XENA_EEPROM_SPACE;
4625 info->testinfo_len = S2IO_TEST_LEN;
fa1f0cb3
SS		 4626
4627 if (sp->device_type == XFRAME_I_DEVICE)
4628 info->n_stats = XFRAME_I_STAT_LEN;
4629 else
4630 info->n_stats = XFRAME_II_STAT_LEN;
1da177e4
LT		 4631}
4632
4633/**
4634 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4635 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4636 * s2io_nic structure.
20346722 4637 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4638 * dumping the registers.
4639 * @reg_space: The input argumnet into which all the registers are dumped.
4640 * Description:
4641 * Dumps the entire register space of xFrame NIC into the user given
4642 * buffer area.
4643 * Return value :
4644 * void .
4645*/
4646
4647static void s2io_ethtool_gregs(struct net_device *dev,
4648 struct ethtool_regs *regs, void *space)
4649{
4650 int i;
4651 u64 reg;
4652 u8 *reg_space = (u8 *) space;
1ee6dd77 4653 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4654
4655 regs->len = XENA_REG_SPACE;
4656 regs->version = sp->pdev->subsystem_device;
4657
4658 for (i = 0; i < regs->len; i += 8) {
4659 reg = readq(sp->bar0 + i);
4660 memcpy((reg_space + i), &reg, 8);
4661 }
4662}
4663
4664/**
4665 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4666 * @data : address of the private member of the device structure, which
1da177e4 4667 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 4668 * Description: This is actually the timer function that alternates the
4669 * adapter LED bit of the adapter control bit to set/reset every time on
4670 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4671 * once every second.
4672*/
4673static void s2io_phy_id(unsigned long data)
4674{
1ee6dd77
RB		 4675 struct s2io_nic *sp = (struct s2io_nic *) data;
4676 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4677 u64 val64 = 0;
4678 u16 subid;
4679
4680 subid = sp->pdev->subsystem_device;
541ae68f 4681 if ((sp->device_type == XFRAME_II_DEVICE) ||
4682 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4683 val64 = readq(&bar0->gpio_control);
4684 val64 ^= GPIO_CTRL_GPIO_0;
4685 writeq(val64, &bar0->gpio_control);
4686 } else {
4687 val64 = readq(&bar0->adapter_control);
4688 val64 ^= ADAPTER_LED_ON;
4689 writeq(val64, &bar0->adapter_control);
4690 }
4691
4692 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4693}
4694
4695/**
4696 * s2io_ethtool_idnic - To physically identify the nic on the system.
4697 * @sp : private member of the device structure, which is a pointer to the
4698 * s2io_nic structure.
20346722 4699 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4700 * ethtool.
4701 * Description: Used to physically identify the NIC on the system.
20346722 4702 * The Link LED will blink for a time specified by the user for
1da177e4 4703 * identification.
20346722 4704 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4705 * identification is possible only if it's link is up.
4706 * Return value:
4707 * int , returns 0 on success
4708 */
4709
4710static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4711{
4712 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 4713 struct s2io_nic *sp = dev->priv;
4714 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4715 u16 subid;
4716
4717 subid = sp->pdev->subsystem_device;
4718 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f 4719 if ((sp->device_type == XFRAME_I_DEVICE) &&
4720 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4721 val64 = readq(&bar0->adapter_control);
4722 if (!(val64 & ADAPTER_CNTL_EN)) {
4723 printk(KERN_ERR
4724 "Adapter Link down, cannot blink LED\n");
4725 return -EFAULT;
4726 }
4727 }
4728 if (sp->id_timer.function == NULL) {
4729 init_timer(&sp->id_timer);
4730 sp->id_timer.function = s2io_phy_id;
4731 sp->id_timer.data = (unsigned long) sp;
4732 }
4733 mod_timer(&sp->id_timer, jiffies);
4734 if (data)
20346722 4735 msleep_interruptible(data * HZ);
1da177e4 4736 else
20346722 4737 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4738 del_timer_sync(&sp->id_timer);
4739
541ae68f 4740 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4741 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4742 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4743 }
4744
4745 return 0;
4746}
4747
4748/**
4749 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 4750 * @sp : private member of the device structure, which is a pointer to the
4751 * s2io_nic structure.
1da177e4
LT		 4752 * @ep : pointer to the structure with pause parameters given by ethtool.
4753 * Description:
4754 * Returns the Pause frame generation and reception capability of the NIC.
4755 * Return value:
4756 * void
4757 */
4758static void s2io_ethtool_getpause_data(struct net_device *dev,
4759 struct ethtool_pauseparam *ep)
4760{
4761 u64 val64;
1ee6dd77
RB		 4762 struct s2io_nic *sp = dev->priv;
4763 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4764
4765 val64 = readq(&bar0->rmac_pause_cfg);
4766 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4767 ep->tx_pause = TRUE;
4768 if (val64 & RMAC_PAUSE_RX_ENABLE)
4769 ep->rx_pause = TRUE;
4770 ep->autoneg = FALSE;
4771}
4772
4773/**
4774 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4775 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4776 * s2io_nic structure.
4777 * @ep : pointer to the structure with pause parameters given by ethtool.
4778 * Description:
4779 * It can be used to set or reset Pause frame generation or reception
4780 * support of the NIC.
4781 * Return value:
4782 * int, returns 0 on Success
4783 */
4784
4785static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4786 struct ethtool_pauseparam *ep)
1da177e4
LT		 4787{
4788 u64 val64;
1ee6dd77
RB		 4789 struct s2io_nic *sp = dev->priv;
4790 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4791
4792 val64 = readq(&bar0->rmac_pause_cfg);
4793 if (ep->tx_pause)
4794 val64 |= RMAC_PAUSE_GEN_ENABLE;
4795 else
4796 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4797 if (ep->rx_pause)
4798 val64 |= RMAC_PAUSE_RX_ENABLE;
4799 else
4800 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4801 writeq(val64, &bar0->rmac_pause_cfg);
4802 return 0;
4803}
4804
4805/**
4806 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 4807 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4808 * s2io_nic structure.
4809 * @off : offset at which the data must be written
4810 * @data : Its an output parameter where the data read at the given
20346722 4811 * offset is stored.
1da177e4 4812 * Description:
20346722 4813 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 4814 * read data.
4815 * NOTE: Will allow to read only part of the EEPROM visible through the
4816 * I2C bus.
4817 * Return value:
4818 * -1 on failure and 0 on success.
4819 */
4820
4821#define S2IO_DEV_ID 5
1ee6dd77 4822static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 4823{
4824 int ret = -1;
4825 u32 exit_cnt = 0;
4826 u64 val64;
1ee6dd77 4827 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4828
ad4ebed0 4829 if (sp->device_type == XFRAME_I_DEVICE) {
4830 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4831 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4832 I2C_CONTROL_CNTL_START;
4833 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 4834
ad4ebed0 4835 while (exit_cnt < 5) {
4836 val64 = readq(&bar0->i2c_control);
4837 if (I2C_CONTROL_CNTL_END(val64)) {
4838 *data = I2C_CONTROL_GET_DATA(val64);
4839 ret = 0;
4840 break;
4841 }
4842 msleep(50);
4843 exit_cnt++;
1da177e4 4844 }
1da177e4
LT		 4845 }
4846
ad4ebed0 4847 if (sp->device_type == XFRAME_II_DEVICE) {
4848 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4849 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 4850 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4851 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4852 val64 |= SPI_CONTROL_REQ;
4853 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4854 while (exit_cnt < 5) {
4855 val64 = readq(&bar0->spi_control);
4856 if (val64 & SPI_CONTROL_NACK) {
4857 ret = 1;
4858 break;
4859 } else if (val64 & SPI_CONTROL_DONE) {
4860 *data = readq(&bar0->spi_data);
4861 *data &= 0xffffff;
4862 ret = 0;
4863 break;
4864 }
4865 msleep(50);
4866 exit_cnt++;
4867 }
4868 }
1da177e4
LT		 4869 return ret;
4870}
4871
4872/**
4873 * write_eeprom - actually writes the relevant part of the data value.
4874 * @sp : private member of the device structure, which is a pointer to the
4875 * s2io_nic structure.
4876 * @off : offset at which the data must be written
4877 * @data : The data that is to be written
20346722 4878 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 4879 * the Eeprom. (max of 3)
4880 * Description:
4881 * Actually writes the relevant part of the data value into the Eeprom
4882 * through the I2C bus.
4883 * Return value:
4884 * 0 on success, -1 on failure.
4885 */
4886
1ee6dd77 4887static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 4888{
4889 int exit_cnt = 0, ret = -1;
4890 u64 val64;
1ee6dd77 4891 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4892
ad4ebed0 4893 if (sp->device_type == XFRAME_I_DEVICE) {
4894 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4895 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4896 I2C_CONTROL_CNTL_START;
4897 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4898
4899 while (exit_cnt < 5) {
4900 val64 = readq(&bar0->i2c_control);
4901 if (I2C_CONTROL_CNTL_END(val64)) {
4902 if (!(val64 & I2C_CONTROL_NACK))
4903 ret = 0;
4904 break;
4905 }
4906 msleep(50);
4907 exit_cnt++;
4908 }
4909 }
1da177e4 4910
ad4ebed0 4911 if (sp->device_type == XFRAME_II_DEVICE) {
4912 int write_cnt = (cnt == 8) ? 0 : cnt;
4913 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4914
4915 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4916 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 4917 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4918 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4919 val64 |= SPI_CONTROL_REQ;
4920 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4921 while (exit_cnt < 5) {
4922 val64 = readq(&bar0->spi_control);
4923 if (val64 & SPI_CONTROL_NACK) {
4924 ret = 1;
4925 break;
4926 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 4927 ret = 0;
ad4ebed0 4928 break;
4929 }
4930 msleep(50);
4931 exit_cnt++;
1da177e4 4932 }
1da177e4 4933 }
1da177e4
LT		 4934 return ret;
4935}
1ee6dd77 4936static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 4937{
b41477f3
AR		 4938 u8 *vpd_data;
4939 u8 data;
9dc737a7
AR		 4940 int i=0, cnt, fail = 0;
4941 int vpd_addr = 0x80;
4942
4943 if (nic->device_type == XFRAME_II_DEVICE) {
4944 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4945 vpd_addr = 0x80;
4946 }
4947 else {
4948 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4949 vpd_addr = 0x50;
4950 }
19a60522 4951 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 4952
b41477f3
AR		 4953 vpd_data = kmalloc(256, GFP_KERNEL);
4954 if (!vpd_data)
4955 return;
4956
9dc737a7
AR		 4957 for (i = 0; i < 256; i +=4 ) {
4958 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4959 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
4960 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4961 for (cnt = 0; cnt <5; cnt++) {
4962 msleep(2);
4963 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4964 if (data == 0x80)
4965 break;
4966 }
4967 if (cnt >= 5) {
4968 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4969 fail = 1;
4970 break;
4971 }
4972 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
4973 (u32 *)&vpd_data[i]);
4974 }
19a60522
SS		 4975
4976 if(!fail) {
4977 /* read serial number of adapter */
4978 for (cnt = 0; cnt < 256; cnt++) {
4979 if ((vpd_data[cnt] == 'S') &&
4980 (vpd_data[cnt+1] == 'N') &&
4981 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
4982 memset(nic->serial_num, 0, VPD_STRING_LEN);
4983 memcpy(nic->serial_num, &vpd_data[cnt + 3],
4984 vpd_data[cnt+2]);
4985 break;
4986 }
4987 }
4988 }
4989
4990 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 4991 memset(nic->product_name, 0, vpd_data[1]);
4992 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4993 }
b41477f3 4994 kfree(vpd_data);
9dc737a7
AR		 4995}
4996
1da177e4
LT		 4997/**
4998 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
4999 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5000 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5001 * containing all relevant information.
5002 * @data_buf : user defined value to be written into Eeprom.
5003 * Description: Reads the values stored in the Eeprom at given offset
5004 * for a given length. Stores these values int the input argument data
5005 * buffer 'data_buf' and returns these to the caller (ethtool.)
5006 * Return value:
5007 * int 0 on success
5008 */
5009
5010static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5011 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5012{
ad4ebed0 5013 u32 i, valid;
5014 u64 data;
1ee6dd77 5015 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5016
5017 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5018
5019 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5020 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5021
5022 for (i = 0; i < eeprom->len; i += 4) {
5023 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5024 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5025 return -EFAULT;
5026 }
5027 valid = INV(data);
5028 memcpy((data_buf + i), &valid, 4);
5029 }
5030 return 0;
5031}
5032
5033/**
5034 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5035 * @sp : private member of the device structure, which is a pointer to the
5036 * s2io_nic structure.
20346722 5037 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5038 * containing all relevant information.
5039 * @data_buf ; user defined value to be written into Eeprom.
5040 * Description:
5041 * Tries to write the user provided value in the Eeprom, at the offset
5042 * given by the user.
5043 * Return value:
5044 * 0 on success, -EFAULT on failure.
5045 */
5046
5047static int s2io_ethtool_seeprom(struct net_device *dev,
5048 struct ethtool_eeprom *eeprom,
5049 u8 * data_buf)
5050{
5051 int len = eeprom->len, cnt = 0;
ad4ebed0 5052 u64 valid = 0, data;
1ee6dd77 5053 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5054
5055 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5056 DBG_PRINT(ERR_DBG,
5057 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5058 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5059 eeprom->magic);
5060 return -EFAULT;
5061 }
5062
5063 while (len) {
5064 data = (u32) data_buf[cnt] & 0x000000FF;
5065 if (data) {
5066 valid = (u32) (data << 24);
5067 } else
5068 valid = data;
5069
5070 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5071 DBG_PRINT(ERR_DBG,
5072 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5073 DBG_PRINT(ERR_DBG,
5074 "write into the specified offset\n");
5075 return -EFAULT;
5076 }
5077 cnt++;
5078 len--;
5079 }
5080
5081 return 0;
5082}
5083
5084/**
20346722 5085 * s2io_register_test - reads and writes into all clock domains.
5086 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5087 * s2io_nic structure.
5088 * @data : variable that returns the result of each of the test conducted b
5089 * by the driver.
5090 * Description:
5091 * Read and write into all clock domains. The NIC has 3 clock domains,
5092 * see that registers in all the three regions are accessible.
5093 * Return value:
5094 * 0 on success.
5095 */
5096
1ee6dd77 5097static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5098{
1ee6dd77 5099 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5100 u64 val64 = 0, exp_val;
1da177e4
LT		 5101 int fail = 0;
5102
20346722 5103 val64 = readq(&bar0->pif_rd_swapper_fb);
5104 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5105 fail = 1;
5106 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5107 }
5108
5109 val64 = readq(&bar0->rmac_pause_cfg);
5110 if (val64 != 0xc000ffff00000000ULL) {
5111 fail = 1;
5112 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5113 }
5114
5115 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5116 if (sp->device_type == XFRAME_II_DEVICE)
5117 exp_val = 0x0404040404040404ULL;
5118 else
5119 exp_val = 0x0808080808080808ULL;
5120 if (val64 != exp_val) {
1da177e4
LT		 5121 fail = 1;
5122 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5123 }
5124
5125 val64 = readq(&bar0->xgxs_efifo_cfg);
5126 if (val64 != 0x000000001923141EULL) {
5127 fail = 1;
5128 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5129 }
5130
5131 val64 = 0x5A5A5A5A5A5A5A5AULL;
5132 writeq(val64, &bar0->xmsi_data);
5133 val64 = readq(&bar0->xmsi_data);
5134 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5135 fail = 1;
5136 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5137 }
5138
5139 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5140 writeq(val64, &bar0->xmsi_data);
5141 val64 = readq(&bar0->xmsi_data);
5142 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5143 fail = 1;
5144 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5145 }
5146
5147 *data = fail;
ad4ebed0 5148 return fail;
1da177e4
LT		 5149}
5150
5151/**
20346722 5152 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5153 * @sp : private member of the device structure, which is a pointer to the
5154 * s2io_nic structure.
5155 * @data:variable that returns the result of each of the test conducted by
5156 * the driver.
5157 * Description:
20346722 5158 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5159 * register.
5160 * Return value:
5161 * 0 on success.
5162 */
5163
1ee6dd77 5164static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5165{
5166 int fail = 0;
ad4ebed0 5167 u64 ret_data, org_4F0, org_7F0;
5168 u8 saved_4F0 = 0, saved_7F0 = 0;
5169 struct net_device *dev = sp->dev;
1da177e4
LT		 5170
5171 /* Test Write Error at offset 0 */
ad4ebed0 5172 /* Note that SPI interface allows write access to all areas
5173 * of EEPROM. Hence doing all negative testing only for Xframe I.
5174 */
5175 if (sp->device_type == XFRAME_I_DEVICE)
5176 if (!write_eeprom(sp, 0, 0, 3))
5177 fail = 1;
5178
5179 /* Save current values at offsets 0x4F0 and 0x7F0 */
5180 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5181 saved_4F0 = 1;
5182 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5183 saved_7F0 = 1;
1da177e4
LT		 5184
5185 /* Test Write at offset 4f0 */
ad4ebed0 5186 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5187 fail = 1;
5188 if (read_eeprom(sp, 0x4F0, &ret_data))
5189 fail = 1;
5190
ad4ebed0 5191 if (ret_data != 0x012345) {
26b7625c
AM		 5192 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5193 "Data written %llx Data read %llx\n",
5194 dev->name, (unsigned long long)0x12345,
5195 (unsigned long long)ret_data);
1da177e4 5196 fail = 1;
ad4ebed0 5197 }
1da177e4
LT		 5198
5199 /* Reset the EEPROM data go FFFF */
ad4ebed0 5200 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5201
5202 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5203 if (sp->device_type == XFRAME_I_DEVICE)
5204 if (!write_eeprom(sp, 0x07C, 0, 3))
5205 fail = 1;
1da177e4 5206
ad4ebed0 5207 /* Test Write Request at offset 0x7f0 */
5208 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5209 fail = 1;
ad4ebed0 5210 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5211 fail = 1;
5212
ad4ebed0 5213 if (ret_data != 0x012345) {
26b7625c
AM		 5214 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5215 "Data written %llx Data read %llx\n",
5216 dev->name, (unsigned long long)0x12345,
5217 (unsigned long long)ret_data);
1da177e4 5218 fail = 1;
ad4ebed0 5219 }
1da177e4
LT		 5220
5221 /* Reset the EEPROM data go FFFF */
ad4ebed0 5222 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5223
ad4ebed0 5224 if (sp->device_type == XFRAME_I_DEVICE) {
5225 /* Test Write Error at offset 0x80 */
5226 if (!write_eeprom(sp, 0x080, 0, 3))
5227 fail = 1;
1da177e4 5228
ad4ebed0 5229 /* Test Write Error at offset 0xfc */
5230 if (!write_eeprom(sp, 0x0FC, 0, 3))
5231 fail = 1;
1da177e4 5232
ad4ebed0 5233 /* Test Write Error at offset 0x100 */
5234 if (!write_eeprom(sp, 0x100, 0, 3))
5235 fail = 1;
1da177e4 5236
ad4ebed0 5237 /* Test Write Error at offset 4ec */
5238 if (!write_eeprom(sp, 0x4EC, 0, 3))
5239 fail = 1;
5240 }
5241
5242 /* Restore values at offsets 0x4F0 and 0x7F0 */
5243 if (saved_4F0)
5244 write_eeprom(sp, 0x4F0, org_4F0, 3);
5245 if (saved_7F0)
5246 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5247
5248 *data = fail;
ad4ebed0 5249 return fail;
1da177e4
LT		 5250}
5251
5252/**
5253 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5254 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5255 * s2io_nic structure.
20346722 5256 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5257 * the driver.
5258 * Description:
5259 * This invokes the MemBist test of the card. We give around
5260 * 2 secs time for the Test to complete. If it's still not complete
20346722 5261 * within this peiod, we consider that the test failed.
1da177e4
LT		 5262 * Return value:
5263 * 0 on success and -1 on failure.
5264 */
5265
1ee6dd77 5266static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5267{
5268 u8 bist = 0;
5269 int cnt = 0, ret = -1;
5270
5271 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5272 bist |= PCI_BIST_START;
5273 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5274
5275 while (cnt < 20) {
5276 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5277 if (!(bist & PCI_BIST_START)) {
5278 *data = (bist & PCI_BIST_CODE_MASK);
5279 ret = 0;
5280 break;
5281 }
5282 msleep(100);
5283 cnt++;
5284 }
5285
5286 return ret;
5287}
5288
5289/**
20346722 5290 * s2io-link_test - verifies the link state of the nic
5291 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5292 * s2io_nic structure.
5293 * @data: variable that returns the result of each of the test conducted by
5294 * the driver.
5295 * Description:
20346722 5296 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5297 * argument 'data' appropriately.
5298 * Return value:
5299 * 0 on success.
5300 */
5301
1ee6dd77 5302static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5303{
1ee6dd77 5304 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5305 u64 val64;
5306
5307 val64 = readq(&bar0->adapter_status);
c92ca04b 5308 if(!(LINK_IS_UP(val64)))
1da177e4 5309 *data = 1;
c92ca04b
AR		 5310 else
5311 *data = 0;
1da177e4 5312
b41477f3 5313 return *data;
1da177e4
LT		 5314}
5315
5316/**
20346722 5317 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5318 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5319 * s2io_nic structure.
20346722 5320 * @data - variable that returns the result of each of the test
1da177e4
LT		 5321 * conducted by the driver.
5322 * Description:
20346722 5323 * This is one of the offline test that tests the read and write
1da177e4
LT		 5324 * access to the RldRam chip on the NIC.
5325 * Return value:
5326 * 0 on success.
5327 */
5328
1ee6dd77 5329static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5330{
1ee6dd77 5331 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5332 u64 val64;
ad4ebed0 5333 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5334
5335 val64 = readq(&bar0->adapter_control);
5336 val64 &= ~ADAPTER_ECC_EN;
5337 writeq(val64, &bar0->adapter_control);
5338
5339 val64 = readq(&bar0->mc_rldram_test_ctrl);
5340 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5341 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5342
5343 val64 = readq(&bar0->mc_rldram_mrs);
5344 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5345 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5346
5347 val64 |= MC_RLDRAM_MRS_ENABLE;
5348 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5349
5350 while (iteration < 2) {
5351 val64 = 0x55555555aaaa0000ULL;
5352 if (iteration == 1) {
5353 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5354 }
5355 writeq(val64, &bar0->mc_rldram_test_d0);
5356
5357 val64 = 0xaaaa5a5555550000ULL;
5358 if (iteration == 1) {
5359 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5360 }
5361 writeq(val64, &bar0->mc_rldram_test_d1);
5362
5363 val64 = 0x55aaaaaaaa5a0000ULL;
5364 if (iteration == 1) {
5365 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5366 }
5367 writeq(val64, &bar0->mc_rldram_test_d2);
5368
ad4ebed0 5369 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5370 writeq(val64, &bar0->mc_rldram_test_add);
5371
ad4ebed0 5372 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5373 MC_RLDRAM_TEST_GO;
5374 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5375
5376 for (cnt = 0; cnt < 5; cnt++) {
5377 val64 = readq(&bar0->mc_rldram_test_ctrl);
5378 if (val64 & MC_RLDRAM_TEST_DONE)
5379 break;
5380 msleep(200);
5381 }
5382
5383 if (cnt == 5)
5384 break;
5385
ad4ebed0 5386 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5387 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5388
5389 for (cnt = 0; cnt < 5; cnt++) {
5390 val64 = readq(&bar0->mc_rldram_test_ctrl);
5391 if (val64 & MC_RLDRAM_TEST_DONE)
5392 break;
5393 msleep(500);
5394 }
5395
5396 if (cnt == 5)
5397 break;
5398
5399 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5400 if (!(val64 & MC_RLDRAM_TEST_PASS))
5401 test_fail = 1;
1da177e4
LT		 5402
5403 iteration++;
5404 }
5405
ad4ebed0 5406 *data = test_fail;
1da177e4 5407
ad4ebed0 5408 /* Bring the adapter out of test mode */
5409 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5410
5411 return test_fail;
1da177e4
LT		 5412}
5413
5414/**
5415 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5416 * @sp : private member of the device structure, which is a pointer to the
5417 * s2io_nic structure.
5418 * @ethtest : pointer to a ethtool command specific structure that will be
5419 * returned to the user.
20346722 5420 * @data : variable that returns the result of each of the test
1da177e4
LT		 5421 * conducted by the driver.
5422 * Description:
5423 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5424 * the health of the card.
5425 * Return value:
5426 * void
5427 */
5428
5429static void s2io_ethtool_test(struct net_device *dev,
5430 struct ethtool_test *ethtest,
5431 uint64_t * data)
5432{
1ee6dd77 5433 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5434 int orig_state = netif_running(sp->dev);
5435
5436 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5437 /* Offline Tests. */
20346722 5438 if (orig_state)
1da177e4 5439 s2io_close(sp->dev);
1da177e4
LT		 5440
5441 if (s2io_register_test(sp, &data[0]))
5442 ethtest->flags |= ETH_TEST_FL_FAILED;
5443
5444 s2io_reset(sp);
1da177e4
LT		 5445
5446 if (s2io_rldram_test(sp, &data[3]))
5447 ethtest->flags |= ETH_TEST_FL_FAILED;
5448
5449 s2io_reset(sp);
1da177e4
LT		 5450
5451 if (s2io_eeprom_test(sp, &data[1]))
5452 ethtest->flags |= ETH_TEST_FL_FAILED;
5453
5454 if (s2io_bist_test(sp, &data[4]))
5455 ethtest->flags |= ETH_TEST_FL_FAILED;
5456
5457 if (orig_state)
5458 s2io_open(sp->dev);
5459
5460 data[2] = 0;
5461 } else {
5462 /* Online Tests. */
5463 if (!orig_state) {
5464 DBG_PRINT(ERR_DBG,
5465 "%s: is not up, cannot run test\n",
5466 dev->name);
5467 data[0] = -1;
5468 data[1] = -1;
5469 data[2] = -1;
5470 data[3] = -1;
5471 data[4] = -1;
5472 }
5473
5474 if (s2io_link_test(sp, &data[2]))
5475 ethtest->flags |= ETH_TEST_FL_FAILED;
5476
5477 data[0] = 0;
5478 data[1] = 0;
5479 data[3] = 0;
5480 data[4] = 0;
5481 }
5482}
5483
5484static void s2io_get_ethtool_stats(struct net_device *dev,
5485 struct ethtool_stats *estats,
5486 u64 * tmp_stats)
5487{
5488 int i = 0;
1ee6dd77
RB		 5489 struct s2io_nic *sp = dev->priv;
5490 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 5491
7ba013ac 5492 s2io_updt_stats(sp);
541ae68f 5493 tmp_stats[i++] =
5494 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5495 le32_to_cpu(stat_info->tmac_frms);
5496 tmp_stats[i++] =
5497 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5498 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5499 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f 5500 tmp_stats[i++] =
5501 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5502 le32_to_cpu(stat_info->tmac_mcst_frms);
5503 tmp_stats[i++] =
5504 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5505 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5506 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5507 tmp_stats[i++] =
5508 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5509 le32_to_cpu(stat_info->tmac_ttl_octets);
5510 tmp_stats[i++] =
5511 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5512 le32_to_cpu(stat_info->tmac_ucst_frms);
5513 tmp_stats[i++] =
5514 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5515 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f 5516 tmp_stats[i++] =
5517 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5518 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5519 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5520 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f 5521 tmp_stats[i++] =
5522 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5523 le32_to_cpu(stat_info->tmac_vld_ip);
5524 tmp_stats[i++] =
5525 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5526 le32_to_cpu(stat_info->tmac_drop_ip);
5527 tmp_stats[i++] =
5528 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5529 le32_to_cpu(stat_info->tmac_icmp);
5530 tmp_stats[i++] =
5531 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5532 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5533 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f 5534 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5535 le32_to_cpu(stat_info->tmac_udp);
5536 tmp_stats[i++] =
5537 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5538 le32_to_cpu(stat_info->rmac_vld_frms);
5539 tmp_stats[i++] =
5540 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5541 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5542 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5543 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f 5544 tmp_stats[i++] =
5545 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5546 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5547 tmp_stats[i++] =
5548 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5549 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5550 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5551 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5552 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5553 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5554 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5555 tmp_stats[i++] =
5556 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5557 le32_to_cpu(stat_info->rmac_ttl_octets);
5558 tmp_stats[i++] =
5559 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5560 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5561 tmp_stats[i++] =
5562 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5563 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f 5564 tmp_stats[i++] =
5565 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5566 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5567 tmp_stats[i++] =
5568 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5569 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5570 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5571 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f 5572 tmp_stats[i++] =
5573 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5574 le32_to_cpu(stat_info->rmac_usized_frms);
5575 tmp_stats[i++] =
5576 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5577 le32_to_cpu(stat_info->rmac_osized_frms);
5578 tmp_stats[i++] =
5579 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5580 le32_to_cpu(stat_info->rmac_frag_frms);
5581 tmp_stats[i++] =
5582 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5583 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5584 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5585 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5586 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5587 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5588 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5589 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5590 tmp_stats[i++] =
5591 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5592 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5593 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5594 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5595 tmp_stats[i++] =
5596 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5597 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5598 tmp_stats[i++] =
5599 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5600 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5601 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5602 tmp_stats[i++] =
5603 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f 5604 le32_to_cpu(stat_info->rmac_udp);
5605 tmp_stats[i++] =
5606 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5607 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5608 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5609 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5610 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5611 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5612 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5613 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5614 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5615 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5616 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5617 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5618 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5619 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5620 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5621 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5622 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5623 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5624 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f 5625 tmp_stats[i++] =
5626 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5627 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5628 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5629 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f 5630 tmp_stats[i++] =
5631 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5632 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5633 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5634 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5635 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5636 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5637 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5638 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5639 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5640 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5641 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5642 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5643 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5644 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5645 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5646 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5647 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5648 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5649 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5650 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5651 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 5652
5653 /* Enhanced statistics exist only for Hercules */
5654 if(sp->device_type == XFRAME_II_DEVICE) {
5655 tmp_stats[i++] =
5656 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5657 tmp_stats[i++] =
5658 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5659 tmp_stats[i++] =
5660 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5661 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5662 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5663 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5664 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5665 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5666 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5667 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5668 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5669 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5670 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5671 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5672 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5673 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5674 }
5675
7ba013ac 5676 tmp_stats[i++] = 0;
5677 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5678 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5679 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5680 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5681 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5682 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5683 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5684 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5685 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5686 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5687 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5688 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5689 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5690 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5691 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5692 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5693 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5694 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5695 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5696 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5697 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5698 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5699 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5700 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5701 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5702 int count = 0;
6aa20a22 5703 /*
bd1034f0
AR		 5704 * Since 64-bit divide does not work on all platforms,
5705 * do repeated subtraction.
5706 */
5707 while (tmp >= stat_info->sw_stat.num_aggregations) {
5708 tmp -= stat_info->sw_stat.num_aggregations;
5709 count++;
5710 }
5711 tmp_stats[i++] = count;
fe931395 5712 }
bd1034f0
AR		 5713 else
5714 tmp_stats[i++] = 0;
1da177e4
LT		 5715}
5716
ac1f60db 5717static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5718{
5719 return (XENA_REG_SPACE);
5720}
5721
5722
ac1f60db 5723static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 5724{
1ee6dd77 5725 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5726
5727 return (sp->rx_csum);
5728}
ac1f60db
AB		 5729
5730static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 5731{
1ee6dd77 5732 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5733
5734 if (data)
5735 sp->rx_csum = 1;
5736 else
5737 sp->rx_csum = 0;
5738
5739 return 0;
5740}
ac1f60db
AB		 5741
5742static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5743{
5744 return (XENA_EEPROM_SPACE);
5745}
5746
ac1f60db 5747static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5748{
5749 return (S2IO_TEST_LEN);
5750}
ac1f60db
AB		 5751
5752static void s2io_ethtool_get_strings(struct net_device *dev,
5753 u32 stringset, u8 * data)
1da177e4 5754{
fa1f0cb3
SS		 5755 int stat_size = 0;
5756 struct s2io_nic *sp = dev->priv;
5757
1da177e4
LT		 5758 switch (stringset) {
5759 case ETH_SS_TEST:
5760 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5761 break;
5762 case ETH_SS_STATS:
fa1f0cb3
SS		 5763 stat_size = sizeof(ethtool_xena_stats_keys);
5764 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5765 if(sp->device_type == XFRAME_II_DEVICE) {
5766 memcpy(data + stat_size,
5767 &ethtool_enhanced_stats_keys,
5768 sizeof(ethtool_enhanced_stats_keys));
5769 stat_size += sizeof(ethtool_enhanced_stats_keys);
5770 }
5771
5772 memcpy(data + stat_size, &ethtool_driver_stats_keys,
5773 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 5774 }
5775}
1da177e4
LT		 5776static int s2io_ethtool_get_stats_count(struct net_device *dev)
5777{
fa1f0cb3
SS		 5778 struct s2io_nic *sp = dev->priv;
5779 int stat_count = 0;
5780 switch(sp->device_type) {
5781 case XFRAME_I_DEVICE:
5782 stat_count = XFRAME_I_STAT_LEN;
5783 break;
5784
5785 case XFRAME_II_DEVICE:
5786 stat_count = XFRAME_II_STAT_LEN;
5787 break;
5788 }
5789
5790 return stat_count;
1da177e4
LT		 5791}
5792
ac1f60db 5793static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5794{
5795 if (data)
5796 dev->features |= NETIF_F_IP_CSUM;
5797 else
5798 dev->features &= ~NETIF_F_IP_CSUM;
5799
5800 return 0;
5801}
5802
75c30b13
AR		 5803static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5804{
5805 return (dev->features & NETIF_F_TSO) != 0;
5806}
5807static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5808{
5809 if (data)
5810 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5811 else
5812 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5813
5814 return 0;
5815}
1da177e4 5816
7282d491 5817static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 5818 .get_settings = s2io_ethtool_gset,
5819 .set_settings = s2io_ethtool_sset,
5820 .get_drvinfo = s2io_ethtool_gdrvinfo,
5821 .get_regs_len = s2io_ethtool_get_regs_len,
5822 .get_regs = s2io_ethtool_gregs,
5823 .get_link = ethtool_op_get_link,
5824 .get_eeprom_len = s2io_get_eeprom_len,
5825 .get_eeprom = s2io_ethtool_geeprom,
5826 .set_eeprom = s2io_ethtool_seeprom,
5827 .get_pauseparam = s2io_ethtool_getpause_data,
5828 .set_pauseparam = s2io_ethtool_setpause_data,
5829 .get_rx_csum = s2io_ethtool_get_rx_csum,
5830 .set_rx_csum = s2io_ethtool_set_rx_csum,
5831 .get_tx_csum = ethtool_op_get_tx_csum,
5832 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5833 .get_sg = ethtool_op_get_sg,
5834 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 5835 .get_tso = s2io_ethtool_op_get_tso,
5836 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd
AR		 5837 .get_ufo = ethtool_op_get_ufo,
5838 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 5839 .self_test_count = s2io_ethtool_self_test_count,
5840 .self_test = s2io_ethtool_test,
5841 .get_strings = s2io_ethtool_get_strings,
5842 .phys_id = s2io_ethtool_idnic,
5843 .get_stats_count = s2io_ethtool_get_stats_count,
5844 .get_ethtool_stats = s2io_get_ethtool_stats
5845};
5846
5847/**
20346722 5848 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 5849 * @dev : Device pointer.
5850 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5851 * a proprietary structure used to pass information to the driver.
5852 * @cmd : This is used to distinguish between the different commands that
5853 * can be passed to the IOCTL functions.
5854 * Description:
20346722 5855 * Currently there are no special functionality supported in IOCTL, hence
5856 * function always return EOPNOTSUPPORTED
1da177e4
LT		 5857 */
5858
ac1f60db 5859static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 5860{
5861 return -EOPNOTSUPP;
5862}
5863
5864/**
5865 * s2io_change_mtu - entry point to change MTU size for the device.
5866 * @dev : device pointer.
5867 * @new_mtu : the new MTU size for the device.
5868 * Description: A driver entry point to change MTU size for the device.
5869 * Before changing the MTU the device must be stopped.
5870 * Return value:
5871 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5872 * file on failure.
5873 */
5874
ac1f60db 5875static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 5876{
1ee6dd77 5877 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5878
5879 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5880 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5881 dev->name);
5882 return -EPERM;
5883 }
5884
1da177e4 5885 dev->mtu = new_mtu;
d8892c6e 5886 if (netif_running(dev)) {
e6a8fee2 5887 s2io_card_down(sp);
d8892c6e 5888 netif_stop_queue(dev);
5889 if (s2io_card_up(sp)) {
5890 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5891 __FUNCTION__);
5892 }
5893 if (netif_queue_stopped(dev))
5894 netif_wake_queue(dev);
5895 } else { /* Device is down */
1ee6dd77 5896 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 5897 u64 val64 = new_mtu;
5898
5899 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5900 }
1da177e4
LT		 5901
5902 return 0;
5903}
5904
5905/**
5906 * s2io_tasklet - Bottom half of the ISR.
5907 * @dev_adr : address of the device structure in dma_addr_t format.
5908 * Description:
5909 * This is the tasklet or the bottom half of the ISR. This is
20346722 5910 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 5911 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 5912 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 5913 * replenish the Rx buffers in the Rx buffer descriptors.
5914 * Return value:
5915 * void.
5916 */
5917
5918static void s2io_tasklet(unsigned long dev_addr)
5919{
5920 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 5921 struct s2io_nic *sp = dev->priv;
1da177e4 5922 int i, ret;
1ee6dd77 5923 struct mac_info *mac_control;
1da177e4
LT		 5924 struct config_param *config;
5925
5926 mac_control = &sp->mac_control;
5927 config = &sp->config;
5928
5929 if (!TASKLET_IN_USE) {
5930 for (i = 0; i < config->rx_ring_num; i++) {
5931 ret = fill_rx_buffers(sp, i);
5932 if (ret == -ENOMEM) {
5933 DBG_PRINT(ERR_DBG, "%s: Out of ",
5934 dev->name);
5935 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5936 break;
5937 } else if (ret == -EFILL) {
5938 DBG_PRINT(ERR_DBG,
5939 "%s: Rx Ring %d is full\n",
5940 dev->name, i);
5941 break;
5942 }
5943 }
5944 clear_bit(0, (&sp->tasklet_status));
5945 }
5946}
5947
5948/**
5949 * s2io_set_link - Set the LInk status
5950 * @data: long pointer to device private structue
5951 * Description: Sets the link status for the adapter
5952 */
5953
c4028958 5954static void s2io_set_link(struct work_struct *work)
1da177e4 5955{
1ee6dd77 5956 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 5957 struct net_device *dev = nic->dev;
1ee6dd77 5958 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 5959 register u64 val64;
5960 u16 subid;
5961
22747d6b
FR		 5962 rtnl_lock();
5963
5964 if (!netif_running(dev))
5965 goto out_unlock;
5966
1da177e4
LT		 5967 if (test_and_set_bit(0, &(nic->link_state))) {
5968 /* The card is being reset, no point doing anything */
22747d6b 5969 goto out_unlock;
1da177e4
LT		 5970 }
5971
5972 subid = nic->pdev->subsystem_device;
a371a07d 5973 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5974 /*
5975 * Allow a small delay for the NICs self initiated
5976 * cleanup to complete.
5977 */
5978 msleep(100);
5979 }
1da177e4
LT		 5980
5981 val64 = readq(&bar0->adapter_status);
19a60522
SS		 5982 if (LINK_IS_UP(val64)) {
5983 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
5984 if (verify_xena_quiescence(nic)) {
5985 val64 = readq(&bar0->adapter_control);
5986 val64 |= ADAPTER_CNTL_EN;
1da177e4 5987 writeq(val64, &bar0->adapter_control);
19a60522
SS		 5988 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
5989 nic->device_type, subid)) {
5990 val64 = readq(&bar0->gpio_control);
5991 val64 |= GPIO_CTRL_GPIO_0;
5992 writeq(val64, &bar0->gpio_control);
5993 val64 = readq(&bar0->gpio_control);
5994 } else {
5995 val64 |= ADAPTER_LED_ON;
5996 writeq(val64, &bar0->adapter_control);
a371a07d 5997 }
1da177e4 5998 nic->device_enabled_once = TRUE;
19a60522
SS		 5999 } else {
6000 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6001 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6002 netif_stop_queue(dev);
1da177e4 6003 }
19a60522
SS		 6004 }
6005 val64 = readq(&bar0->adapter_status);
6006 if (!LINK_IS_UP(val64)) {
6007 DBG_PRINT(ERR_DBG, "%s:", dev->name);
6008 DBG_PRINT(ERR_DBG, " Link down after enabling ");
6009 DBG_PRINT(ERR_DBG, "device \n");
6010 } else
1da177e4 6011 s2io_link(nic, LINK_UP);
19a60522
SS		 6012 } else {
6013 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6014 subid)) {
6015 val64 = readq(&bar0->gpio_control);
6016 val64 &= ~GPIO_CTRL_GPIO_0;
6017 writeq(val64, &bar0->gpio_control);
6018 val64 = readq(&bar0->gpio_control);
1da177e4 6019 }
19a60522 6020 s2io_link(nic, LINK_DOWN);
1da177e4
LT		 6021 }
6022 clear_bit(0, &(nic->link_state));
22747d6b
FR		 6023
6024out_unlock:
6025 rtnl_lock();
1da177e4
LT		 6026}
6027
1ee6dd77
RB		 6028static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6029 struct buffAdd *ba,
6030 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6031 u64 *temp2, int size)
5d3213cc
AR		 6032{
6033 struct net_device *dev = sp->dev;
6034 struct sk_buff *frag_list;
6035
6036 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6037 /* allocate skb */
6038 if (*skb) {
6039 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6040 /*
6041 * As Rx frame are not going to be processed,
6042 * using same mapped address for the Rxd
6043 * buffer pointer
6044 */
1ee6dd77 6045 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0;
5d3213cc
AR		 6046 } else {
6047 *skb = dev_alloc_skb(size);
6048 if (!(*skb)) {
6049 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
6050 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
6051 return -ENOMEM ;
6052 }
6053 /* storing the mapped addr in a temp variable
6054 * such it will be used for next rxd whose
6055 * Host Control is NULL
6056 */
1ee6dd77 6057 ((struct RxD1*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6058 pci_map_single( sp->pdev, (*skb)->data,
6059 size - NET_IP_ALIGN,
6060 PCI_DMA_FROMDEVICE);
6061 rxdp->Host_Control = (unsigned long) (*skb);
6062 }
6063 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6064 /* Two buffer Mode */
6065 if (*skb) {
1ee6dd77
RB		 6066 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
6067 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6068 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
5d3213cc
AR		 6069 } else {
6070 *skb = dev_alloc_skb(size);
2ceaac75
DR		 6071 if (!(*skb)) {
6072 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
19a60522 6073 dev->name);
2ceaac75
DR		 6074 return -ENOMEM;
6075 }
1ee6dd77 6076 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6077 pci_map_single(sp->pdev, (*skb)->data,
6078 dev->mtu + 4,
6079 PCI_DMA_FROMDEVICE);
1ee6dd77 6080 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6081 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6082 PCI_DMA_FROMDEVICE);
6083 rxdp->Host_Control = (unsigned long) (*skb);
6084
6085 /* Buffer-1 will be dummy buffer not used */
1ee6dd77 6086 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
5d3213cc
AR		 6087 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6088 PCI_DMA_FROMDEVICE);
6089 }
6090 } else if ((rxdp->Host_Control == 0)) {
6091 /* Three buffer mode */
6092 if (*skb) {
1ee6dd77
RB		 6093 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0;
6094 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1;
6095 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2;
5d3213cc
AR		 6096 } else {
6097 *skb = dev_alloc_skb(size);
2ceaac75
DR		 6098 if (!(*skb)) {
6099 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n",
6100 dev->name);
6101 return -ENOMEM;
6102 }
1ee6dd77 6103 ((struct RxD3*)rxdp)->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6104 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6105 PCI_DMA_FROMDEVICE);
6106 /* Buffer-1 receives L3/L4 headers */
1ee6dd77 6107 ((struct RxD3*)rxdp)->Buffer1_ptr = *temp1 =
5d3213cc
AR		 6108 pci_map_single( sp->pdev, (*skb)->data,
6109 l3l4hdr_size + 4,
6110 PCI_DMA_FROMDEVICE);
6111 /*
6112 * skb_shinfo(skb)->frag_list will have L4
6113 * data payload
6114 */
6115 skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6116 ALIGN_SIZE);
6117 if (skb_shinfo(*skb)->frag_list == NULL) {
6118 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6119 failed\n ", dev->name);
6120 return -ENOMEM ;
6121 }
6122 frag_list = skb_shinfo(*skb)->frag_list;
6123 frag_list->next = NULL;
6124 /*
6125 * Buffer-2 receives L4 data payload
6126 */
1ee6dd77 6127 ((struct RxD3*)rxdp)->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6128 pci_map_single( sp->pdev, frag_list->data,
6129 dev->mtu, PCI_DMA_FROMDEVICE);
6130 }
6131 }
6132 return 0;
6133}
1ee6dd77
RB		 6134static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6135 int size)
5d3213cc
AR		 6136{
6137 struct net_device *dev = sp->dev;
6138 if (sp->rxd_mode == RXD_MODE_1) {
6139 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6140 } else if (sp->rxd_mode == RXD_MODE_3B) {
6141 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6142 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6143 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6144 } else {
6145 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6146 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6147 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6148 }
6149}
6150
1ee6dd77 6151static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6152{
6153 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6154 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6155 struct config_param *config = &sp->config;
6156 struct net_device *dev = sp->dev;
1ee6dd77 6157 struct RxD_t *rxdp = NULL;
5d3213cc 6158 struct sk_buff *skb = NULL;
1ee6dd77 6159 struct buffAdd *ba = NULL;
5d3213cc
AR		 6160 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6161
6162 /* Calculate the size based on ring mode */
6163 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6164 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6165 if (sp->rxd_mode == RXD_MODE_1)
6166 size += NET_IP_ALIGN;
6167 else if (sp->rxd_mode == RXD_MODE_3B)
6168 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6169 else
6170 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6171
6172 for (i = 0; i < config->rx_ring_num; i++) {
6173 blk_cnt = config->rx_cfg[i].num_rxd /
6174 (rxd_count[sp->rxd_mode] +1);
6175
6176 for (j = 0; j < blk_cnt; j++) {
6177 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6178 rxdp = mac_control->rings[i].
6179 rx_blocks[j].rxds[k].virt_addr;
6180 if(sp->rxd_mode >= RXD_MODE_3A)
6181 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6182 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6183 &skb,(u64 *)&temp0_64,
6184 (u64 *)&temp1_64,
ac1f90d6
SS		 6185 (u64 *)&temp2_64,
6186 size) == ENOMEM) {
6187 return 0;
6188 }
5d3213cc
AR		 6189
6190 set_rxd_buffer_size(sp, rxdp, size);
6191 wmb();
6192 /* flip the Ownership bit to Hardware */
6193 rxdp->Control_1 |= RXD_OWN_XENA;
6194 }
6195 }
6196 }
6197 return 0;
6198
6199}
6200
1ee6dd77 6201static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6202{
e6a8fee2 6203 int ret = 0;
c92ca04b 6204 struct net_device *dev = sp->dev;
e6a8fee2 6205 int err = 0;
1da177e4 6206
e6a8fee2
AR		 6207 if (sp->intr_type == MSI)
6208 ret = s2io_enable_msi(sp);
6209 else if (sp->intr_type == MSI_X)
6210 ret = s2io_enable_msi_x(sp);
6211 if (ret) {
6212 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6213 sp->intr_type = INTA;
20346722 6214 }
1da177e4 6215
1ee6dd77 6216 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6217 store_xmsi_data(sp);
c92ca04b 6218
e6a8fee2
AR		 6219 /* After proper initialization of H/W, register ISR */
6220 if (sp->intr_type == MSI) {
6221 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6222 IRQF_SHARED, sp->name, dev);
6223 if (err) {
6224 pci_disable_msi(sp->pdev);
6225 DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6226 dev->name);
6227 return -1;
6228 }
6229 }
6230 if (sp->intr_type == MSI_X) {
fb6a825b 6231 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6232
e6a8fee2
AR		 6233 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6234 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6235 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6236 dev->name, i);
6237 err = request_irq(sp->entries[i].vector,
6238 s2io_msix_fifo_handle, 0, sp->desc[i],
6239 sp->s2io_entries[i].arg);
fb6a825b
SS		 6240 /* If either data or addr is zero print it */
6241 if(!(sp->msix_info[i].addr &&
6242 sp->msix_info[i].data)) {
6243 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6244 "Data:0x%lx\n",sp->desc[i],
6245 (unsigned long long)
6246 sp->msix_info[i].addr,
6247 (unsigned long)
6248 ntohl(sp->msix_info[i].data));
6249 } else {
6250 msix_tx_cnt++;
6251 }
e6a8fee2
AR		 6252 } else {
6253 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6254 dev->name, i);
6255 err = request_irq(sp->entries[i].vector,
6256 s2io_msix_ring_handle, 0, sp->desc[i],
6257 sp->s2io_entries[i].arg);
fb6a825b
SS		 6258 /* If either data or addr is zero print it */
6259 if(!(sp->msix_info[i].addr &&
6260 sp->msix_info[i].data)) {
6261 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6262 "Data:0x%lx\n",sp->desc[i],
6263 (unsigned long long)
6264 sp->msix_info[i].addr,
6265 (unsigned long)
6266 ntohl(sp->msix_info[i].data));
6267 } else {
6268 msix_rx_cnt++;
6269 }
c92ca04b 6270 }
e6a8fee2
AR		 6271 if (err) {
6272 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6273 "failed\n", dev->name, i);
6274 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6275 return -1;
6276 }
6277 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6278 }
fb6a825b
SS		 6279 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6280 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
e6a8fee2
AR		 6281 }
6282 if (sp->intr_type == INTA) {
6283 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6284 sp->name, dev);
6285 if (err) {
6286 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6287 dev->name);
6288 return -1;
6289 }
6290 }
6291 return 0;
6292}
1ee6dd77 6293static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2
AR		 6294{
6295 int cnt = 0;
6296 struct net_device *dev = sp->dev;
6297
6298 if (sp->intr_type == MSI_X) {
6299 int i;
6300 u16 msi_control;
6301
6302 for (i=1; (sp->s2io_entries[i].in_use ==
6303 MSIX_REGISTERED_SUCCESS); i++) {
6304 int vector = sp->entries[i].vector;
6305 void *arg = sp->s2io_entries[i].arg;
6306
6307 free_irq(vector, arg);
6308 }
6309 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6310 msi_control &= 0xFFFE; /* Disable MSI */
6311 pci_write_config_word(sp->pdev, 0x42, msi_control);
6312
6313 pci_disable_msix(sp->pdev);
6314 } else {
6315 free_irq(sp->pdev->irq, dev);
6316 if (sp->intr_type == MSI) {
6317 u16 val;
6318
6319 pci_disable_msi(sp->pdev);
6320 pci_read_config_word(sp->pdev, 0x4c, &val);
6321 val ^= 0x1;
6322 pci_write_config_word(sp->pdev, 0x4c, val);
c92ca04b
AR		 6323 }
6324 }
6325 /* Waiting till all Interrupt handlers are complete */
6326 cnt = 0;
6327 do {
6328 msleep(10);
6329 if (!atomic_read(&sp->isr_cnt))
6330 break;
6331 cnt++;
6332 } while(cnt < 5);
e6a8fee2
AR		 6333}
6334
1ee6dd77 6335static void s2io_card_down(struct s2io_nic * sp)
e6a8fee2
AR		 6336{
6337 int cnt = 0;
1ee6dd77 6338 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6339 unsigned long flags;
6340 register u64 val64 = 0;
6341
6342 del_timer_sync(&sp->alarm_timer);
6343 /* If s2io_set_link task is executing, wait till it completes. */
6344 while (test_and_set_bit(0, &(sp->link_state))) {
6345 msleep(50);
6346 }
6347 atomic_set(&sp->card_state, CARD_DOWN);
6348
6349 /* disable Tx and Rx traffic on the NIC */
6350 stop_nic(sp);
6351
6352 s2io_rem_isr(sp);
1da177e4
LT		 6353
6354 /* Kill tasklet. */
6355 tasklet_kill(&sp->task);
6356
6357 /* Check if the device is Quiescent and then Reset the NIC */
6358 do {
5d3213cc
AR		 6359 /* As per the HW requirement we need to replenish the
6360 * receive buffer to avoid the ring bump. Since there is
6361 * no intention of processing the Rx frame at this pointwe are
6362 * just settting the ownership bit of rxd in Each Rx
6363 * ring to HW and set the appropriate buffer size
6364 * based on the ring mode
6365 */
6366 rxd_owner_bit_reset(sp);
6367
1da177e4 6368 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6369 if (verify_xena_quiescence(sp)) {
6370 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 6371 break;
6372 }
6373
6374 msleep(50);
6375 cnt++;
6376 if (cnt == 10) {
6377 DBG_PRINT(ERR_DBG,
6378 "s2io_close:Device not Quiescent ");
6379 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6380 (unsigned long long) val64);
6381 break;
6382 }
6383 } while (1);
1da177e4
LT		 6384 s2io_reset(sp);
6385
7ba013ac 6386 spin_lock_irqsave(&sp->tx_lock, flags);
6387 /* Free all Tx buffers */
1da177e4 6388 free_tx_buffers(sp);
7ba013ac 6389 spin_unlock_irqrestore(&sp->tx_lock, flags);
6390
6391 /* Free all Rx buffers */
6392 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6393 free_rx_buffers(sp);
7ba013ac 6394 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6395
1da177e4
LT		 6396 clear_bit(0, &(sp->link_state));
6397}
6398
1ee6dd77 6399static int s2io_card_up(struct s2io_nic * sp)
1da177e4 6400{
cc6e7c44 6401 int i, ret = 0;
1ee6dd77 6402 struct mac_info *mac_control;
1da177e4
LT		 6403 struct config_param *config;
6404 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6405 u16 interruptible;
1da177e4
LT		 6406
6407 /* Initialize the H/W I/O registers */
6408 if (init_nic(sp) != 0) {
6409 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6410 dev->name);
e6a8fee2 6411 s2io_reset(sp);
1da177e4
LT		 6412 return -ENODEV;
6413 }
6414
20346722 6415 /*
6416 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6417 * Rx ring and initializing buffers into 30 Rx blocks
6418 */
6419 mac_control = &sp->mac_control;
6420 config = &sp->config;
6421
6422 for (i = 0; i < config->rx_ring_num; i++) {
6423 if ((ret = fill_rx_buffers(sp, i))) {
6424 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6425 dev->name);
6426 s2io_reset(sp);
6427 free_rx_buffers(sp);
6428 return -ENOMEM;
6429 }
6430 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6431 atomic_read(&sp->rx_bufs_left[i]));
6432 }
19a60522
SS		 6433 /* Maintain the state prior to the open */
6434 if (sp->promisc_flg)
6435 sp->promisc_flg = 0;
6436 if (sp->m_cast_flg) {
6437 sp->m_cast_flg = 0;
6438 sp->all_multi_pos= 0;
6439 }
1da177e4
LT		 6440
6441 /* Setting its receive mode */
6442 s2io_set_multicast(dev);
6443
7d3d0439 6444 if (sp->lro) {
b41477f3 6445 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6446 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6447 /* Check if we can use(if specified) user provided value */
6448 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6449 sp->lro_max_aggr_per_sess = lro_max_pkts;
6450 }
6451
1da177e4
LT		 6452 /* Enable Rx Traffic and interrupts on the NIC */
6453 if (start_nic(sp)) {
6454 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6455 s2io_reset(sp);
e6a8fee2
AR		 6456 free_rx_buffers(sp);
6457 return -ENODEV;
6458 }
6459
6460 /* Add interrupt service routine */
6461 if (s2io_add_isr(sp) != 0) {
6462 if (sp->intr_type == MSI_X)
6463 s2io_rem_isr(sp);
6464 s2io_reset(sp);
1da177e4
LT		 6465 free_rx_buffers(sp);
6466 return -ENODEV;
6467 }
6468
25fff88e 6469 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6470
e6a8fee2
AR		 6471 /* Enable tasklet for the device */
6472 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6473
6474 /* Enable select interrupts */
6475 if (sp->intr_type != INTA)
6476 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6477 else {
6478 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6479 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6480 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6481 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6482 }
6483
6484
1da177e4
LT		 6485 atomic_set(&sp->card_state, CARD_UP);
6486 return 0;
6487}
6488
20346722 6489/**
1da177e4
LT		 6490 * s2io_restart_nic - Resets the NIC.
6491 * @data : long pointer to the device private structure
6492 * Description:
6493 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6494 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6495 * the run time of the watch dog routine which is run holding a
6496 * spin lock.
6497 */
6498
c4028958 6499static void s2io_restart_nic(struct work_struct *work)
1da177e4 6500{
1ee6dd77 6501 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 6502 struct net_device *dev = sp->dev;
1da177e4 6503
22747d6b
FR		 6504 rtnl_lock();
6505
6506 if (!netif_running(dev))
6507 goto out_unlock;
6508
e6a8fee2 6509 s2io_card_down(sp);
1da177e4
LT		 6510 if (s2io_card_up(sp)) {
6511 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6512 dev->name);
6513 }
6514 netif_wake_queue(dev);
6515 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6516 dev->name);
22747d6b
FR		 6517out_unlock:
6518 rtnl_unlock();
1da177e4
LT		 6519}
6520
20346722 6521/**
6522 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6523 * @dev : Pointer to net device structure
6524 * Description:
6525 * This function is triggered if the Tx Queue is stopped
6526 * for a pre-defined amount of time when the Interface is still up.
6527 * If the Interface is jammed in such a situation, the hardware is
6528 * reset (by s2io_close) and restarted again (by s2io_open) to
6529 * overcome any problem that might have been caused in the hardware.
6530 * Return value:
6531 * void
6532 */
6533
6534static void s2io_tx_watchdog(struct net_device *dev)
6535{
1ee6dd77 6536 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6537
6538 if (netif_carrier_ok(dev)) {
6539 schedule_work(&sp->rst_timer_task);
bd1034f0 6540 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6541 }
6542}
6543
6544/**
6545 * rx_osm_handler - To perform some OS related operations on SKB.
6546 * @sp: private member of the device structure,pointer to s2io_nic structure.
6547 * @skb : the socket buffer pointer.
6548 * @len : length of the packet
6549 * @cksum : FCS checksum of the frame.
6550 * @ring_no : the ring from which this RxD was extracted.
20346722 6551 * Description:
b41477f3 6552 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6553 * some OS related operations on the SKB before passing it to the upper
6554 * layers. It mainly checks if the checksum is OK, if so adds it to the
6555 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6556 * to the upper layer. If the checksum is wrong, it increments the Rx
6557 * packet error count, frees the SKB and returns error.
6558 * Return value:
6559 * SUCCESS on success and -1 on failure.
6560 */
1ee6dd77 6561static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 6562{
1ee6dd77 6563 struct s2io_nic *sp = ring_data->nic;
1da177e4 6564 struct net_device *dev = (struct net_device *) sp->dev;
20346722 6565 struct sk_buff *skb = (struct sk_buff *)
6566 ((unsigned long) rxdp->Host_Control);
6567 int ring_no = ring_data->ring_no;
1da177e4 6568 u16 l3_csum, l4_csum;
863c11a9 6569 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 6570 struct lro *lro;
da6971d8 6571
20346722 6572 skb->dev = dev;
c92ca04b 6573
863c11a9 6574 if (err) {
bd1034f0
AR		 6575 /* Check for parity error */
6576 if (err & 0x1) {
6577 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6578 }
6579
863c11a9
AR		 6580 /*
6581 * Drop the packet if bad transfer code. Exception being
6582 * 0x5, which could be due to unsupported IPv6 extension header.
6583 * In this case, we let stack handle the packet.
6584 * Note that in this case, since checksum will be incorrect,
6585 * stack will validate the same.
6586 */
6587 if (err && ((err >> 48) != 0x5)) {
6588 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6589 dev->name, err);
6590 sp->stats.rx_crc_errors++;
6591 dev_kfree_skb(skb);
6592 atomic_dec(&sp->rx_bufs_left[ring_no]);
6593 rxdp->Host_Control = 0;
6594 return 0;
6595 }
20346722 6596 }
1da177e4 6597
20346722 6598 /* Updating statistics */
6599 rxdp->Host_Control = 0;
6600 sp->rx_pkt_count++;
6601 sp->stats.rx_packets++;
da6971d8
AR		 6602 if (sp->rxd_mode == RXD_MODE_1) {
6603 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6604
da6971d8
AR		 6605 sp->stats.rx_bytes += len;
6606 skb_put(skb, len);
6607
6608 } else if (sp->rxd_mode >= RXD_MODE_3A) {
6609 int get_block = ring_data->rx_curr_get_info.block_index;
6610 int get_off = ring_data->rx_curr_get_info.offset;
6611 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6612 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6613 unsigned char *buff = skb_push(skb, buf0_len);
6614
1ee6dd77 6615 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 6616 sp->stats.rx_bytes += buf0_len + buf2_len;
6617 memcpy(buff, ba->ba_0, buf0_len);
6618
6619 if (sp->rxd_mode == RXD_MODE_3A) {
6620 int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6621
6622 skb_put(skb, buf1_len);
6623 skb->len += buf2_len;
6624 skb->data_len += buf2_len;
da6971d8
AR		 6625 skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6626 sp->stats.rx_bytes += buf1_len;
6627
6628 } else
6629 skb_put(skb, buf2_len);
6630 }
20346722 6631
7d3d0439
RA		 6632 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6633 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 6634 (sp->rx_csum)) {
6635 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6636 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6637 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6638 /*
1da177e4
LT		 6639 * NIC verifies if the Checksum of the received
6640 * frame is Ok or not and accordingly returns
6641 * a flag in the RxD.
6642 */
6643 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6644 if (sp->lro) {
6645 u32 tcp_len;
6646 u8 *tcp;
6647 int ret = 0;
6648
6649 ret = s2io_club_tcp_session(skb->data, &tcp,
6650 &tcp_len, &lro, rxdp, sp);
6651 switch (ret) {
6652 case 3: /* Begin anew */
6653 lro->parent = skb;
6654 goto aggregate;
6655 case 1: /* Aggregate */
6656 {
6657 lro_append_pkt(sp, lro,
6658 skb, tcp_len);
6659 goto aggregate;
6660 }
6661 case 4: /* Flush session */
6662 {
6663 lro_append_pkt(sp, lro,
6664 skb, tcp_len);
6665 queue_rx_frame(lro->parent);
6666 clear_lro_session(lro);
6667 sp->mac_control.stats_info->
6668 sw_stat.flush_max_pkts++;
6669 goto aggregate;
6670 }
6671 case 2: /* Flush both */
6672 lro->parent->data_len =
6673 lro->frags_len;
6674 sp->mac_control.stats_info->
6675 sw_stat.sending_both++;
6676 queue_rx_frame(lro->parent);
6677 clear_lro_session(lro);
6678 goto send_up;
6679 case 0: /* sessions exceeded */
c92ca04b
AR		 6680 case -1: /* non-TCP or not
6681 * L2 aggregatable
6682 */
7d3d0439
RA		 6683 case 5: /*
6684 * First pkt in session not
6685 * L3/L4 aggregatable
6686 */
6687 break;
6688 default:
6689 DBG_PRINT(ERR_DBG,
6690 "%s: Samadhana!!\n",
6691 __FUNCTION__);
6692 BUG();
6693 }
6694 }
1da177e4 6695 } else {
20346722 6696 /*
6697 * Packet with erroneous checksum, let the
1da177e4
LT		 6698 * upper layers deal with it.
6699 */
6700 skb->ip_summed = CHECKSUM_NONE;
6701 }
6702 } else {
6703 skb->ip_summed = CHECKSUM_NONE;
6704 }
6705
7d3d0439
RA		 6706 if (!sp->lro) {
6707 skb->protocol = eth_type_trans(skb, dev);
926930b2
SS		 6708 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
6709 vlan_strip_flag)) {
7d3d0439 6710 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 6711 if (napi)
6712 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6713 RXD_GET_VLAN_TAG(rxdp->Control_2));
6714 else
6715 vlan_hwaccel_rx(skb, sp->vlgrp,
6716 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 6717 } else {
db874e65
SS		 6718 if (napi)
6719 netif_receive_skb(skb);
6720 else
6721 netif_rx(skb);
7d3d0439 6722 }
7d3d0439
RA		 6723 } else {
6724send_up:
6725 queue_rx_frame(skb);
6aa20a22 6726 }
1da177e4 6727 dev->last_rx = jiffies;
7d3d0439 6728aggregate:
1da177e4 6729 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 6730 return SUCCESS;
6731}
6732
6733/**
6734 * s2io_link - stops/starts the Tx queue.
6735 * @sp : private member of the device structure, which is a pointer to the
6736 * s2io_nic structure.
6737 * @link : inidicates whether link is UP/DOWN.
6738 * Description:
6739 * This function stops/starts the Tx queue depending on whether the link
20346722 6740 * status of the NIC is is down or up. This is called by the Alarm
6741 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 6742 * Return value:
6743 * void.
6744 */
6745
1ee6dd77 6746static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 6747{
6748 struct net_device *dev = (struct net_device *) sp->dev;
6749
6750 if (link != sp->last_link_state) {
6751 if (link == LINK_DOWN) {
6752 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6753 netif_carrier_off(dev);
6754 } else {
6755 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6756 netif_carrier_on(dev);
6757 }
6758 }
6759 sp->last_link_state = link;
6760}
6761
6762/**
20346722 6763 * get_xena_rev_id - to identify revision ID of xena.
6764 * @pdev : PCI Dev structure
6765 * Description:
6766 * Function to identify the Revision ID of xena.
6767 * Return value:
6768 * returns the revision ID of the device.
6769 */
6770
26df54bf 6771static int get_xena_rev_id(struct pci_dev *pdev)
20346722 6772{
6773 u8 id = 0;
6774 int ret;
6775 ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6776 return id;
6777}
6778
6779/**
6780 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6781 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 6782 * s2io_nic structure.
6783 * Description:
6784 * This function initializes a few of the PCI and PCI-X configuration registers
6785 * with recommended values.
6786 * Return value:
6787 * void
6788 */
6789
1ee6dd77 6790static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 6791{
20346722 6792 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 6793
6794 /* Enable Data Parity Error Recovery in PCI-X command register. */
6795 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6796 &(pcix_cmd));
1da177e4 6797 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6798 (pcix_cmd | 1));
1da177e4 6799 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6800 &(pcix_cmd));
1da177e4
LT		 6801
6802 /* Set the PErr Response bit in PCI command register. */
6803 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6804 pci_write_config_word(sp->pdev, PCI_COMMAND,
6805 (pci_cmd | PCI_COMMAND_PARITY));
6806 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 6807}
6808
9dc737a7
AR		 6809static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6810{
6811 if ( tx_fifo_num > 8) {
6812 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6813 "supported\n");
6814 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6815 tx_fifo_num = 8;
6816 }
6817 if ( rx_ring_num > 8) {
6818 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6819 "supported\n");
6820 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6821 rx_ring_num = 8;
6822 }
db874e65
SS		 6823 if (*dev_intr_type != INTA)
6824 napi = 0;
6825
9dc737a7
AR		 6826#ifndef CONFIG_PCI_MSI
6827 if (*dev_intr_type != INTA) {
6828 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6829 "MSI/MSI-X. Defaulting to INTA\n");
6830 *dev_intr_type = INTA;
6831 }
6832#else
6833 if (*dev_intr_type > MSI_X) {
6834 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6835 "Defaulting to INTA\n");
6836 *dev_intr_type = INTA;
6837 }
6838#endif
6839 if ((*dev_intr_type == MSI_X) &&
6840 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6841 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 6842 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 6843 "Defaulting to INTA\n");
6844 *dev_intr_type = INTA;
6845 }
fb6a825b 6846
9dc737a7
AR		 6847 if (rx_ring_mode > 3) {
6848 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6849 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6850 rx_ring_mode = 3;
6851 }
6852 return SUCCESS;
6853}
6854
9fc93a41
SS		 6855/**
6856 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
6857 * or Traffic class respectively.
6858 * @nic: device peivate variable
6859 * Description: The function configures the receive steering to
6860 * desired receive ring.
6861 * Return Value: SUCCESS on success and
6862 * '-1' on failure (endian settings incorrect).
6863 */
6864static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
6865{
6866 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6867 register u64 val64 = 0;
6868
6869 if (ds_codepoint > 63)
6870 return FAILURE;
6871
6872 val64 = RTS_DS_MEM_DATA(ring);
6873 writeq(val64, &bar0->rts_ds_mem_data);
6874
6875 val64 = RTS_DS_MEM_CTRL_WE |
6876 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
6877 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
6878
6879 writeq(val64, &bar0->rts_ds_mem_ctrl);
6880
6881 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
6882 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
6883 S2IO_BIT_RESET);
6884}
6885
1da177e4 6886/**
20346722 6887 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 6888 * @pdev : structure containing the PCI related information of the device.
6889 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6890 * Description:
6891 * The function initializes an adapter identified by the pci_dec structure.
20346722 6892 * All OS related initialization including memory and device structure and
6893 * initlaization of the device private variable is done. Also the swapper
6894 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 6895 * registers of the device.
6896 * Return value:
6897 * returns 0 on success and negative on failure.
6898 */
6899
6900static int __devinit
6901s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6902{
1ee6dd77 6903 struct s2io_nic *sp;
1da177e4 6904 struct net_device *dev;
1da177e4
LT		 6905 int i, j, ret;
6906 int dma_flag = FALSE;
6907 u32 mac_up, mac_down;
6908 u64 val64 = 0, tmp64 = 0;
1ee6dd77 6909 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 6910 u16 subid;
1ee6dd77 6911 struct mac_info *mac_control;
1da177e4 6912 struct config_param *config;
541ae68f 6913 int mode;
cc6e7c44 6914 u8 dev_intr_type = intr_type;
1da177e4 6915
9dc737a7
AR		 6916 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6917 return ret;
1da177e4
LT		 6918
6919 if ((ret = pci_enable_device(pdev))) {
6920 DBG_PRINT(ERR_DBG,
6921 "s2io_init_nic: pci_enable_device failed\n");
6922 return ret;
6923 }
6924
1e7f0bd8 6925 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6926 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6927 dma_flag = TRUE;
1da177e4 6928 if (pci_set_consistent_dma_mask
1e7f0bd8 6929 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 6930 DBG_PRINT(ERR_DBG,
6931 "Unable to obtain 64bit DMA for \
6932 consistent allocations\n");
6933 pci_disable_device(pdev);
6934 return -ENOMEM;
6935 }
1e7f0bd8 6936 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 6937 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6938 } else {
6939 pci_disable_device(pdev);
6940 return -ENOMEM;
6941 }
cc6e7c44
RA		 6942 if (dev_intr_type != MSI_X) {
6943 if (pci_request_regions(pdev, s2io_driver_name)) {
b41477f3
AR		 6944 DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6945 pci_disable_device(pdev);
cc6e7c44
RA		 6946 return -ENODEV;
6947 }
6948 }
6949 else {
6950 if (!(request_mem_region(pci_resource_start(pdev, 0),
6951 pci_resource_len(pdev, 0), s2io_driver_name))) {
6952 DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6953 pci_disable_device(pdev);
6954 return -ENODEV;
6955 }
6956 if (!(request_mem_region(pci_resource_start(pdev, 2),
6957 pci_resource_len(pdev, 2), s2io_driver_name))) {
6958 DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6959 release_mem_region(pci_resource_start(pdev, 0),
6960 pci_resource_len(pdev, 0));
6961 pci_disable_device(pdev);
6962 return -ENODEV;
6963 }
1da177e4
LT		 6964 }
6965
1ee6dd77 6966 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 6967 if (dev == NULL) {
6968 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6969 pci_disable_device(pdev);
6970 pci_release_regions(pdev);
6971 return -ENODEV;
6972 }
6973
6974 pci_set_master(pdev);
6975 pci_set_drvdata(pdev, dev);
6976 SET_MODULE_OWNER(dev);
6977 SET_NETDEV_DEV(dev, &pdev->dev);
6978
6979 /* Private member variable initialized to s2io NIC structure */
6980 sp = dev->priv;
1ee6dd77 6981 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 6982 sp->dev = dev;
6983 sp->pdev = pdev;
1da177e4 6984 sp->high_dma_flag = dma_flag;
1da177e4 6985 sp->device_enabled_once = FALSE;
da6971d8
AR		 6986 if (rx_ring_mode == 1)
6987 sp->rxd_mode = RXD_MODE_1;
6988 if (rx_ring_mode == 2)
6989 sp->rxd_mode = RXD_MODE_3B;
6990 if (rx_ring_mode == 3)
6991 sp->rxd_mode = RXD_MODE_3A;
6992
cc6e7c44 6993 sp->intr_type = dev_intr_type;
1da177e4 6994
541ae68f 6995 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6996 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6997 sp->device_type = XFRAME_II_DEVICE;
6998 else
6999 sp->device_type = XFRAME_I_DEVICE;
7000
7d3d0439 7001 sp->lro = lro;
6aa20a22 7002
1da177e4
LT		 7003 /* Initialize some PCI/PCI-X fields of the NIC. */
7004 s2io_init_pci(sp);
7005
20346722 7006 /*
1da177e4 7007 * Setting the device configuration parameters.
20346722 7008 * Most of these parameters can be specified by the user during
7009 * module insertion as they are module loadable parameters. If
7010 * these parameters are not not specified during load time, they
1da177e4
LT		 7011 * are initialized with default values.
7012 */
7013 mac_control = &sp->mac_control;
7014 config = &sp->config;
7015
7016 /* Tx side parameters. */
1da177e4
LT		 7017 config->tx_fifo_num = tx_fifo_num;
7018 for (i = 0; i < MAX_TX_FIFOS; i++) {
7019 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7020 config->tx_cfg[i].fifo_priority = i;
7021 }
7022
20346722 7023 /* mapping the QoS priority to the configured fifos */
7024 for (i = 0; i < MAX_TX_FIFOS; i++)
7025 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7026
1da177e4
LT		 7027 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7028 for (i = 0; i < config->tx_fifo_num; i++) {
7029 config->tx_cfg[i].f_no_snoop =
7030 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7031 if (config->tx_cfg[i].fifo_len < 65) {
7032 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7033 break;
7034 }
7035 }
fed5eccd
AR		 7036 /* + 2 because one Txd for skb->data and one Txd for UFO */
7037 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7038
7039 /* Rx side parameters. */
1da177e4
LT		 7040 config->rx_ring_num = rx_ring_num;
7041 for (i = 0; i < MAX_RX_RINGS; i++) {
7042 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7043 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7044 config->rx_cfg[i].ring_priority = i;
7045 }
7046
7047 for (i = 0; i < rx_ring_num; i++) {
7048 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7049 config->rx_cfg[i].f_no_snoop =
7050 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7051 }
7052
7053 /* Setting Mac Control parameters */
7054 mac_control->rmac_pause_time = rmac_pause_time;
7055 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7056 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7057
7058
7059 /* Initialize Ring buffer parameters. */
7060 for (i = 0; i < config->rx_ring_num; i++)
7061 atomic_set(&sp->rx_bufs_left[i], 0);
7062
7ba013ac 7063 /* Initialize the number of ISRs currently running */
7064 atomic_set(&sp->isr_cnt, 0);
7065
1da177e4
LT		 7066 /* initialize the shared memory used by the NIC and the host */
7067 if (init_shared_mem(sp)) {
7068 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7069 dev->name);
1da177e4
LT		 7070 ret = -ENOMEM;
7071 goto mem_alloc_failed;
7072 }
7073
7074 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7075 pci_resource_len(pdev, 0));
7076 if (!sp->bar0) {
19a60522 7077 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7078 dev->name);
7079 ret = -ENOMEM;
7080 goto bar0_remap_failed;
7081 }
7082
7083 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7084 pci_resource_len(pdev, 2));
7085 if (!sp->bar1) {
19a60522 7086 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7087 dev->name);
7088 ret = -ENOMEM;
7089 goto bar1_remap_failed;
7090 }
7091
7092 dev->irq = pdev->irq;
7093 dev->base_addr = (unsigned long) sp->bar0;
7094
7095 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7096 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7097 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7098 (sp->bar1 + (j * 0x00020000));
7099 }
7100
7101 /* Driver entry points */
7102 dev->open = &s2io_open;
7103 dev->stop = &s2io_close;
7104 dev->hard_start_xmit = &s2io_xmit;
7105 dev->get_stats = &s2io_get_stats;
7106 dev->set_multicast_list = &s2io_set_multicast;
7107 dev->do_ioctl = &s2io_ioctl;
7108 dev->change_mtu = &s2io_change_mtu;
7109 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7110 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7111 dev->vlan_rx_register = s2io_vlan_rx_register;
7112 dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
20346722 7113
1da177e4
LT		 7114 /*
7115 * will use eth_mac_addr() for dev->set_mac_address
7116 * mac address will be set every time dev->open() is called
7117 */
1da177e4 7118 dev->poll = s2io_poll;
20346722 7119 dev->weight = 32;
1da177e4 7120
612eff0e
BH		 7121#ifdef CONFIG_NET_POLL_CONTROLLER
7122 dev->poll_controller = s2io_netpoll;
7123#endif
7124
1da177e4
LT		 7125 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7126 if (sp->high_dma_flag == TRUE)
7127 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7128 dev->features |= NETIF_F_TSO;
f83ef8c0 7129 dev->features |= NETIF_F_TSO6;
db874e65 7130 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7131 dev->features |= NETIF_F_UFO;
7132 dev->features |= NETIF_F_HW_CSUM;
7133 }
1da177e4
LT		 7134
7135 dev->tx_timeout = &s2io_tx_watchdog;
7136 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7137 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7138 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7139
e960fc5c 7140 pci_save_state(sp->pdev);
1da177e4
LT		 7141
7142 /* Setting swapper control on the NIC, for proper reset operation */
7143 if (s2io_set_swapper(sp)) {
7144 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7145 dev->name);
7146 ret = -EAGAIN;
7147 goto set_swap_failed;
7148 }
7149
541ae68f 7150 /* Verify if the Herc works on the slot its placed into */
7151 if (sp->device_type & XFRAME_II_DEVICE) {
7152 mode = s2io_verify_pci_mode(sp);
7153 if (mode < 0) {
7154 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7155 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7156 ret = -EBADSLT;
7157 goto set_swap_failed;
7158 }
7159 }
7160
7161 /* Not needed for Herc */
7162 if (sp->device_type & XFRAME_I_DEVICE) {
7163 /*
7164 * Fix for all "FFs" MAC address problems observed on
7165 * Alpha platforms
7166 */
7167 fix_mac_address(sp);
7168 s2io_reset(sp);
7169 }
1da177e4
LT		 7170
7171 /*
1da177e4
LT		 7172 * MAC address initialization.
7173 * For now only one mac address will be read and used.
7174 */
7175 bar0 = sp->bar0;
7176 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7177 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7178 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7179 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7180 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7181 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7182 mac_down = (u32) tmp64;
7183 mac_up = (u32) (tmp64 >> 32);
7184
7185 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7186
7187 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7188 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7189 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7190 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7191 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7192 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7193
1da177e4
LT		 7194 /* Set the factory defined MAC address initially */
7195 dev->addr_len = ETH_ALEN;
7196 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7197
b41477f3
AR		 7198 /* reset Nic and bring it to known state */
7199 s2io_reset(sp);
7200
1da177e4 7201 /*
20346722 7202 * Initialize the tasklet status and link state flags
541ae68f 7203 * and the card state parameter
1da177e4
LT		 7204 */
7205 atomic_set(&(sp->card_state), 0);
7206 sp->tasklet_status = 0;
7207 sp->link_state = 0;
7208
1da177e4
LT		 7209 /* Initialize spinlocks */
7210 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7211
7212 if (!napi)
7213 spin_lock_init(&sp->put_lock);
7ba013ac 7214 spin_lock_init(&sp->rx_lock);
1da177e4 7215
20346722 7216 /*
7217 * SXE-002: Configure link and activity LED to init state
7218 * on driver load.
1da177e4
LT		 7219 */
7220 subid = sp->pdev->subsystem_device;
7221 if ((subid & 0xFF) >= 0x07) {
7222 val64 = readq(&bar0->gpio_control);
7223 val64 |= 0x0000800000000000ULL;
7224 writeq(val64, &bar0->gpio_control);
7225 val64 = 0x0411040400000000ULL;
7226 writeq(val64, (void __iomem *) bar0 + 0x2700);
7227 val64 = readq(&bar0->gpio_control);
7228 }
7229
7230 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7231
7232 if (register_netdev(dev)) {
7233 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7234 ret = -ENODEV;
7235 goto register_failed;
7236 }
9dc737a7 7237 s2io_vpd_read(sp);
9dc737a7 7238 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
b41477f3
AR		 7239 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7240 sp->product_name, get_xena_rev_id(sp->pdev));
7241 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7242 s2io_driver_version);
9dc737a7 7243 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
19a60522 7244 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
541ae68f 7245 sp->def_mac_addr[0].mac_addr[0],
7246 sp->def_mac_addr[0].mac_addr[1],
7247 sp->def_mac_addr[0].mac_addr[2],
7248 sp->def_mac_addr[0].mac_addr[3],
7249 sp->def_mac_addr[0].mac_addr[4],
7250 sp->def_mac_addr[0].mac_addr[5]);
19a60522 7251 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7252 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7253 mode = s2io_print_pci_mode(sp);
541ae68f 7254 if (mode < 0) {
9dc737a7 7255 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7256 ret = -EBADSLT;
9dc737a7 7257 unregister_netdev(dev);
541ae68f 7258 goto set_swap_failed;
7259 }
541ae68f 7260 }
9dc737a7
AR		 7261 switch(sp->rxd_mode) {
7262 case RXD_MODE_1:
7263 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7264 dev->name);
7265 break;
7266 case RXD_MODE_3B:
7267 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7268 dev->name);
7269 break;
7270 case RXD_MODE_3A:
7271 DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7272 dev->name);
7273 break;
7274 }
db874e65
SS		 7275
7276 if (napi)
7277 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
9dc737a7
AR		 7278 switch(sp->intr_type) {
7279 case INTA:
7280 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7281 break;
7282 case MSI:
7283 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7284 break;
7285 case MSI_X:
7286 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7287 break;
7288 }
7d3d0439
RA		 7289 if (sp->lro)
7290 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7291 dev->name);
db874e65
SS		 7292 if (ufo)
7293 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7294 " enabled\n", dev->name);
7ba013ac 7295 /* Initialize device name */
9dc737a7 7296 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7297
b6e3f982 7298 /* Initialize bimodal Interrupts */
7299 sp->config.bimodal = bimodal;
7300 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7301 sp->config.bimodal = 0;
7302 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7303 dev->name);
7304 }
7305
20346722 7306 /*
7307 * Make Link state as off at this point, when the Link change
7308 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7309 * the right state.
7310 */
7311 netif_carrier_off(dev);
1da177e4
LT		 7312
7313 return 0;
7314
7315 register_failed:
7316 set_swap_failed:
7317 iounmap(sp->bar1);
7318 bar1_remap_failed:
7319 iounmap(sp->bar0);
7320 bar0_remap_failed:
7321 mem_alloc_failed:
7322 free_shared_mem(sp);
7323 pci_disable_device(pdev);
cc6e7c44
RA		 7324 if (dev_intr_type != MSI_X)
7325 pci_release_regions(pdev);
7326 else {
7327 release_mem_region(pci_resource_start(pdev, 0),
7328 pci_resource_len(pdev, 0));
7329 release_mem_region(pci_resource_start(pdev, 2),
7330 pci_resource_len(pdev, 2));
7331 }
1da177e4
LT		 7332 pci_set_drvdata(pdev, NULL);
7333 free_netdev(dev);
7334
7335 return ret;
7336}
7337
7338/**
20346722 7339 * s2io_rem_nic - Free the PCI device
1da177e4 7340 * @pdev: structure containing the PCI related information of the device.
20346722 7341 * Description: This function is called by the Pci subsystem to release a
1da177e4 7342 * PCI device and free up all resource held up by the device. This could
20346722 7343 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7344 * from memory.
7345 */
7346
7347static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7348{
7349 struct net_device *dev =
7350 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 7351 struct s2io_nic *sp;
1da177e4
LT		 7352
7353 if (dev == NULL) {
7354 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7355 return;
7356 }
7357
22747d6b
FR		 7358 flush_scheduled_work();
7359
1da177e4
LT		 7360 sp = dev->priv;
7361 unregister_netdev(dev);
7362
7363 free_shared_mem(sp);
7364 iounmap(sp->bar0);
7365 iounmap(sp->bar1);
cc6e7c44
RA		 7366 if (sp->intr_type != MSI_X)
7367 pci_release_regions(pdev);
7368 else {
7369 release_mem_region(pci_resource_start(pdev, 0),
7370 pci_resource_len(pdev, 0));
7371 release_mem_region(pci_resource_start(pdev, 2),
7372 pci_resource_len(pdev, 2));
7373 }
1da177e4 7374 pci_set_drvdata(pdev, NULL);
1da177e4 7375 free_netdev(dev);
19a60522 7376 pci_disable_device(pdev);
1da177e4
LT		 7377}
7378
7379/**
7380 * s2io_starter - Entry point for the driver
7381 * Description: This function is the entry point for the driver. It verifies
7382 * the module loadable parameters and initializes PCI configuration space.
7383 */
7384
7385int __init s2io_starter(void)
7386{
29917620 7387 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7388}
7389
7390/**
20346722 7391 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7392 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7393 */
7394
372cc597 7395static __exit void s2io_closer(void)
1da177e4
LT		 7396{
7397 pci_unregister_driver(&s2io_driver);
7398 DBG_PRINT(INIT_DBG, "cleanup done\n");
7399}
7400
7401module_init(s2io_starter);
7402module_exit(s2io_closer);
7d3d0439 7403
6aa20a22 7404static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 7405 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 7406{
7407 int ip_off;
7408 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7409
7410 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7411 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7412 __FUNCTION__);
7413 return -1;
7414 }
7415
7416 /* TODO:
7417 * By default the VLAN field in the MAC is stripped by the card, if this
7418 * feature is turned off in rx_pa_cfg register, then the ip_off field
7419 * has to be shifted by a further 2 bytes
7420 */
7421 switch (l2_type) {
7422 case 0: /* DIX type */
7423 case 4: /* DIX type with VLAN */
7424 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7425 break;
7426 /* LLC, SNAP etc are considered non-mergeable */
7427 default:
7428 return -1;
7429 }
7430
7431 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7432 ip_len = (u8)((*ip)->ihl);
7433 ip_len <<= 2;
7434 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7435
7436 return 0;
7437}
7438
1ee6dd77 7439static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7440 struct tcphdr *tcp)
7441{
7442 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7443 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7444 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7445 return -1;
7446 return 0;
7447}
7448
7449static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7450{
7451 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7452}
7453
1ee6dd77 7454static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 7455 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7456{
7457 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7458 lro->l2h = l2h;
7459 lro->iph = ip;
7460 lro->tcph = tcp;
7461 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7462 lro->tcp_ack = ntohl(tcp->ack_seq);
7463 lro->sg_num = 1;
7464 lro->total_len = ntohs(ip->tot_len);
7465 lro->frags_len = 0;
6aa20a22 7466 /*
7d3d0439
RA		 7467 * check if we saw TCP timestamp. Other consistency checks have
7468 * already been done.
7469 */
7470 if (tcp->doff == 8) {
7471 u32 *ptr;
7472 ptr = (u32 *)(tcp+1);
7473 lro->saw_ts = 1;
7474 lro->cur_tsval = *(ptr+1);
7475 lro->cur_tsecr = *(ptr+2);
7476 }
7477 lro->in_use = 1;
7478}
7479
1ee6dd77 7480static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 7481{
7482 struct iphdr *ip = lro->iph;
7483 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 7484 __sum16 nchk;
1ee6dd77 7485 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 7486 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7487
7488 /* Update L3 header */
7489 ip->tot_len = htons(lro->total_len);
7490 ip->check = 0;
7491 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7492 ip->check = nchk;
7493
7494 /* Update L4 header */
7495 tcp->ack_seq = lro->tcp_ack;
7496 tcp->window = lro->window;
7497
7498 /* Update tsecr field if this session has timestamps enabled */
7499 if (lro->saw_ts) {
7500 u32 *ptr = (u32 *)(tcp + 1);
7501 *(ptr+2) = lro->cur_tsecr;
7502 }
7503
7504 /* Update counters required for calculation of
7505 * average no. of packets aggregated.
7506 */
7507 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7508 statinfo->sw_stat.num_aggregations++;
7509}
7510
1ee6dd77 7511static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7512 struct tcphdr *tcp, u32 l4_pyld)
7513{
7514 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7515 lro->total_len += l4_pyld;
7516 lro->frags_len += l4_pyld;
7517 lro->tcp_next_seq += l4_pyld;
7518 lro->sg_num++;
7519
7520 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7521 lro->tcp_ack = tcp->ack_seq;
7522 lro->window = tcp->window;
6aa20a22 7523
7d3d0439
RA		 7524 if (lro->saw_ts) {
7525 u32 *ptr;
7526 /* Update tsecr and tsval from this packet */
7527 ptr = (u32 *) (tcp + 1);
6aa20a22 7528 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7529 lro->cur_tsecr = *(ptr + 2);
7530 }
7531}
7532
1ee6dd77 7533static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 7534 struct tcphdr *tcp, u32 tcp_pyld_len)
7535{
7d3d0439
RA		 7536 u8 *ptr;
7537
79dc1901
AM		 7538 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7539
7d3d0439
RA		 7540 if (!tcp_pyld_len) {
7541 /* Runt frame or a pure ack */
7542 return -1;
7543 }
7544
7545 if (ip->ihl != 5) /* IP has options */
7546 return -1;
7547
75c30b13
AR		 7548 /* If we see CE codepoint in IP header, packet is not mergeable */
7549 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7550 return -1;
7551
7552 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7553 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7554 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7555 /*
7556 * Currently recognize only the ack control word and
7557 * any other control field being set would result in
7558 * flushing the LRO session
7559 */
7560 return -1;
7561 }
7562
6aa20a22 7563 /*
7d3d0439
RA		 7564 * Allow only one TCP timestamp option. Don't aggregate if
7565 * any other options are detected.
7566 */
7567 if (tcp->doff != 5 && tcp->doff != 8)
7568 return -1;
7569
7570 if (tcp->doff == 8) {
6aa20a22 7571 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7572 while (*ptr == TCPOPT_NOP)
7573 ptr++;
7574 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7575 return -1;
7576
7577 /* Ensure timestamp value increases monotonically */
7578 if (l_lro)
7579 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7580 return -1;
7581
7582 /* timestamp echo reply should be non-zero */
6aa20a22 7583 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7584 return -1;
7585 }
7586
7587 return 0;
7588}
7589
7590static int
1ee6dd77
RB		 7591s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7592 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 7593{
7594 struct iphdr *ip;
7595 struct tcphdr *tcph;
7596 int ret = 0, i;
7597
7598 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7599 rxdp))) {
7600 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7601 ip->saddr, ip->daddr);
7602 } else {
7603 return ret;
7604 }
7605
7606 tcph = (struct tcphdr *)*tcp;
7607 *tcp_len = get_l4_pyld_length(ip, tcph);
7608 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7609 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7610 if (l_lro->in_use) {
7611 if (check_for_socket_match(l_lro, ip, tcph))
7612 continue;
7613 /* Sock pair matched */
7614 *lro = l_lro;
7615
7616 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7617 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7618 "0x%x, actual 0x%x\n", __FUNCTION__,
7619 (*lro)->tcp_next_seq,
7620 ntohl(tcph->seq));
7621
7622 sp->mac_control.stats_info->
7623 sw_stat.outof_sequence_pkts++;
7624 ret = 2;
7625 break;
7626 }
7627
7628 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7629 ret = 1; /* Aggregate */
7630 else
7631 ret = 2; /* Flush both */
7632 break;
7633 }
7634 }
7635
7636 if (ret == 0) {
7637 /* Before searching for available LRO objects,
7638 * check if the pkt is L3/L4 aggregatable. If not
7639 * don't create new LRO session. Just send this
7640 * packet up.
7641 */
7642 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7643 return 5;
7644 }
7645
7646 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7647 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7648 if (!(l_lro->in_use)) {
7649 *lro = l_lro;
7650 ret = 3; /* Begin anew */
7651 break;
7652 }
7653 }
7654 }
7655
7656 if (ret == 0) { /* sessions exceeded */
7657 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7658 __FUNCTION__);
7659 *lro = NULL;
7660 return ret;
7661 }
7662
7663 switch (ret) {
7664 case 3:
7665 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7666 break;
7667 case 2:
7668 update_L3L4_header(sp, *lro);
7669 break;
7670 case 1:
7671 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7672 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7673 update_L3L4_header(sp, *lro);
7674 ret = 4; /* Flush the LRO */
7675 }
7676 break;
7677 default:
7678 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7679 __FUNCTION__);
7680 break;
7681 }
7682
7683 return ret;
7684}
7685
1ee6dd77 7686static void clear_lro_session(struct lro *lro)
7d3d0439 7687{
1ee6dd77 7688 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 7689
7690 memset(lro, 0, lro_struct_size);
7691}
7692
7693static void queue_rx_frame(struct sk_buff *skb)
7694{
7695 struct net_device *dev = skb->dev;
7696
7697 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 7698 if (napi)
7699 netif_receive_skb(skb);
7700 else
7701 netif_rx(skb);
7d3d0439
RA		 7702}
7703
1ee6dd77
RB		 7704static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7705 struct sk_buff *skb,
7d3d0439
RA		 7706 u32 tcp_len)
7707{
75c30b13 7708 struct sk_buff *first = lro->parent;
7d3d0439
RA		 7709
7710 first->len += tcp_len;
7711 first->data_len = lro->frags_len;
7712 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 7713 if (skb_shinfo(first)->frag_list)
7714 lro->last_frag->next = skb;
7d3d0439
RA		 7715 else
7716 skb_shinfo(first)->frag_list = skb;
372cc597 7717 first->truesize += skb->truesize;
75c30b13 7718 lro->last_frag = skb;
7d3d0439
RA		 7719 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7720 return;
7721}
Linux kernel - Deliverables
This page took 0.674591 seconds and 5 git commands to generate.