Commit | Line | Data |
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1da177e4 | 1 | /* |
f90fdc3c | 2 | * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation |
1da177e4 LT |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation; either version 2 | |
7 | * of the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
74b0247f | 13 | * |
1da177e4 LT |
14 | * You should have received a copy of the GNU General Public License |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
17 | * | |
18 | * | |
19 | * This driver is designed for the Broadcom SiByte SOC built-in | |
20 | * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. | |
21 | */ | |
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/timer.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/init.h> | |
1da177e4 LT |
34 | #include <linux/bitops.h> |
35 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
36 | #include <asm/io.h> | |
37 | #include <asm/cache.h> | |
38 | ||
39 | /* This is only here until the firmware is ready. In that case, | |
40 | the firmware leaves the ethernet address in the register for us. */ | |
41 | #ifdef CONFIG_SIBYTE_STANDALONE | |
42 | #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00" | |
43 | #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01" | |
44 | #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02" | |
f90fdc3c | 45 | #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03" |
1da177e4 LT |
46 | #endif |
47 | ||
48 | ||
49 | /* These identify the driver base version and may not be removed. */ | |
50 | #if 0 | |
51 | static char version1[] __devinitdata = | |
52 | "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n"; | |
53 | #endif | |
54 | ||
55 | ||
56 | /* Operational parameters that usually are not changed. */ | |
57 | ||
58 | #define CONFIG_SBMAC_COALESCE | |
59 | ||
f90fdc3c | 60 | #define MAX_UNITS 4 /* More are supported, limit only on options */ |
1da177e4 LT |
61 | |
62 | /* Time in jiffies before concluding the transmitter is hung. */ | |
63 | #define TX_TIMEOUT (2*HZ) | |
64 | ||
65 | ||
66 | MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); | |
67 | MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); | |
68 | ||
69 | /* A few user-configurable values which may be modified when a driver | |
70 | module is loaded. */ | |
71 | ||
72 | /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
73 | static int debug = 1; | |
74 | module_param(debug, int, S_IRUGO); | |
75 | MODULE_PARM_DESC(debug, "Debug messages"); | |
76 | ||
77 | /* mii status msgs */ | |
78 | static int noisy_mii = 1; | |
79 | module_param(noisy_mii, int, S_IRUGO); | |
80 | MODULE_PARM_DESC(noisy_mii, "MII status messages"); | |
81 | ||
82 | /* Used to pass the media type, etc. | |
83 | Both 'options[]' and 'full_duplex[]' should exist for driver | |
84 | interoperability. | |
85 | The media type is usually passed in 'options[]'. | |
86 | */ | |
87 | #ifdef MODULE | |
f90fdc3c | 88 | static int options[MAX_UNITS] = {-1, -1, -1, -1}; |
1da177e4 LT |
89 | module_param_array(options, int, NULL, S_IRUGO); |
90 | MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS)); | |
91 | ||
f90fdc3c | 92 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1}; |
1da177e4 LT |
93 | module_param_array(full_duplex, int, NULL, S_IRUGO); |
94 | MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS)); | |
95 | #endif | |
96 | ||
97 | #ifdef CONFIG_SBMAC_COALESCE | |
693aa947 MM |
98 | static int int_pktcnt_tx = 255; |
99 | module_param(int_pktcnt_tx, int, S_IRUGO); | |
100 | MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count"); | |
1da177e4 | 101 | |
693aa947 MM |
102 | static int int_timeout_tx = 255; |
103 | module_param(int_timeout_tx, int, S_IRUGO); | |
104 | MODULE_PARM_DESC(int_timeout_tx, "TX timeout value"); | |
105 | ||
106 | static int int_pktcnt_rx = 64; | |
107 | module_param(int_pktcnt_rx, int, S_IRUGO); | |
108 | MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count"); | |
109 | ||
110 | static int int_timeout_rx = 64; | |
111 | module_param(int_timeout_rx, int, S_IRUGO); | |
112 | MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); | |
1da177e4 LT |
113 | #endif |
114 | ||
115 | #include <asm/sibyte/sb1250.h> | |
f90fdc3c RB |
116 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
117 | #include <asm/sibyte/bcm1480_regs.h> | |
118 | #include <asm/sibyte/bcm1480_int.h> | |
693aa947 | 119 | #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST |
f90fdc3c | 120 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) |
1da177e4 | 121 | #include <asm/sibyte/sb1250_regs.h> |
1da177e4 | 122 | #include <asm/sibyte/sb1250_int.h> |
f90fdc3c RB |
123 | #else |
124 | #error invalid SiByte MAC configuation | |
125 | #endif | |
1da177e4 | 126 | #include <asm/sibyte/sb1250_scd.h> |
f90fdc3c RB |
127 | #include <asm/sibyte/sb1250_mac.h> |
128 | #include <asm/sibyte/sb1250_dma.h> | |
1da177e4 | 129 | |
f90fdc3c RB |
130 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
131 | #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2)) | |
132 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
133 | #define UNIT_INT(n) (K_INT_MAC_0 + (n)) | |
134 | #else | |
135 | #error invalid SiByte MAC configuation | |
136 | #endif | |
1da177e4 LT |
137 | |
138 | /********************************************************************** | |
139 | * Simple types | |
140 | ********************************************************************* */ | |
141 | ||
142 | ||
1da177e4 LT |
143 | typedef enum { sbmac_speed_auto, sbmac_speed_10, |
144 | sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; | |
145 | ||
146 | typedef enum { sbmac_duplex_auto, sbmac_duplex_half, | |
147 | sbmac_duplex_full } sbmac_duplex_t; | |
148 | ||
149 | typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, | |
150 | sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; | |
151 | ||
74b0247f | 152 | typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, |
1da177e4 LT |
153 | sbmac_state_broken } sbmac_state_t; |
154 | ||
155 | ||
156 | /********************************************************************** | |
157 | * Macros | |
158 | ********************************************************************* */ | |
159 | ||
160 | ||
161 | #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ | |
162 | (d)->sbdma_dscrtable : (d)->f+1) | |
163 | ||
164 | ||
165 | #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) | |
166 | ||
693aa947 MM |
167 | #define SBMAC_MAX_TXDESCR 256 |
168 | #define SBMAC_MAX_RXDESCR 256 | |
1da177e4 LT |
169 | |
170 | #define ETHER_ALIGN 2 | |
171 | #define ETHER_ADDR_LEN 6 | |
74b0247f RB |
172 | #define ENET_PACKET_SIZE 1518 |
173 | /*#define ENET_PACKET_SIZE 9216 */ | |
1da177e4 LT |
174 | |
175 | /********************************************************************** | |
176 | * DMA Descriptor structure | |
177 | ********************************************************************* */ | |
178 | ||
179 | typedef struct sbdmadscr_s { | |
180 | uint64_t dscr_a; | |
181 | uint64_t dscr_b; | |
182 | } sbdmadscr_t; | |
183 | ||
184 | typedef unsigned long paddr_t; | |
185 | ||
186 | /********************************************************************** | |
187 | * DMA Controller structure | |
188 | ********************************************************************* */ | |
189 | ||
190 | typedef struct sbmacdma_s { | |
74b0247f RB |
191 | |
192 | /* | |
1da177e4 LT |
193 | * This stuff is used to identify the channel and the registers |
194 | * associated with it. | |
195 | */ | |
74b0247f | 196 | |
693aa947 MM |
197 | struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ |
198 | int sbdma_channel; /* channel number */ | |
1da177e4 | 199 | int sbdma_txdir; /* direction (1=transmit) */ |
693aa947 | 200 | int sbdma_maxdescr; /* total # of descriptors in ring */ |
1da177e4 LT |
201 | #ifdef CONFIG_SBMAC_COALESCE |
202 | int sbdma_int_pktcnt; /* # descriptors rx/tx before interrupt*/ | |
203 | int sbdma_int_timeout; /* # usec rx/tx interrupt */ | |
204 | #endif | |
205 | ||
2039973a RB |
206 | volatile void __iomem *sbdma_config0; /* DMA config register 0 */ |
207 | volatile void __iomem *sbdma_config1; /* DMA config register 1 */ | |
208 | volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */ | |
693aa947 | 209 | volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */ |
2039973a | 210 | volatile void __iomem *sbdma_curdscr; /* current descriptor address */ |
693aa947 MM |
211 | volatile void __iomem *sbdma_oodpktlost;/* pkt drop (rx only) */ |
212 | ||
74b0247f | 213 | |
1da177e4 LT |
214 | /* |
215 | * This stuff is for maintenance of the ring | |
216 | */ | |
74b0247f | 217 | |
693aa947 | 218 | sbdmadscr_t *sbdma_dscrtable_unaligned; |
1da177e4 LT |
219 | sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ |
220 | sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ | |
74b0247f | 221 | |
1da177e4 | 222 | struct sk_buff **sbdma_ctxtable; /* context table, one per descr */ |
74b0247f | 223 | |
1da177e4 LT |
224 | paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ |
225 | sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ | |
226 | sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ | |
227 | } sbmacdma_t; | |
228 | ||
229 | ||
230 | /********************************************************************** | |
231 | * Ethernet softc structure | |
232 | ********************************************************************* */ | |
233 | ||
234 | struct sbmac_softc { | |
74b0247f | 235 | |
1da177e4 LT |
236 | /* |
237 | * Linux-specific things | |
238 | */ | |
74b0247f | 239 | |
1da177e4 | 240 | struct net_device *sbm_dev; /* pointer to linux device */ |
bea3348e | 241 | struct napi_struct napi; |
1da177e4 LT |
242 | spinlock_t sbm_lock; /* spin lock */ |
243 | struct timer_list sbm_timer; /* for monitoring MII */ | |
74b0247f | 244 | struct net_device_stats sbm_stats; |
1da177e4 LT |
245 | int sbm_devflags; /* current device flags */ |
246 | ||
247 | int sbm_phy_oldbmsr; | |
248 | int sbm_phy_oldanlpar; | |
249 | int sbm_phy_oldk1stsr; | |
250 | int sbm_phy_oldlinkstat; | |
251 | int sbm_buffersize; | |
74b0247f | 252 | |
1da177e4 | 253 | unsigned char sbm_phys[2]; |
74b0247f | 254 | |
1da177e4 LT |
255 | /* |
256 | * Controller-specific things | |
257 | */ | |
74b0247f | 258 | |
8fb303c7 | 259 | void __iomem *sbm_base; /* MAC's base address */ |
1da177e4 | 260 | sbmac_state_t sbm_state; /* current state */ |
74b0247f | 261 | |
2039973a RB |
262 | volatile void __iomem *sbm_macenable; /* MAC Enable Register */ |
263 | volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */ | |
264 | volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */ | |
265 | volatile void __iomem *sbm_framecfg; /* Frame configuration register */ | |
266 | volatile void __iomem *sbm_rxfilter; /* receive filter register */ | |
267 | volatile void __iomem *sbm_isr; /* Interrupt status register */ | |
268 | volatile void __iomem *sbm_imr; /* Interrupt mask register */ | |
269 | volatile void __iomem *sbm_mdio; /* MDIO register */ | |
74b0247f | 270 | |
1da177e4 LT |
271 | sbmac_speed_t sbm_speed; /* current speed */ |
272 | sbmac_duplex_t sbm_duplex; /* current duplex */ | |
273 | sbmac_fc_t sbm_fc; /* current flow control setting */ | |
74b0247f | 274 | |
1da177e4 | 275 | unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; |
74b0247f | 276 | |
1da177e4 LT |
277 | sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ |
278 | sbmacdma_t sbm_rxdma; | |
279 | int rx_hw_checksum; | |
280 | int sbe_idx; | |
281 | }; | |
282 | ||
283 | ||
284 | /********************************************************************** | |
285 | * Externs | |
286 | ********************************************************************* */ | |
287 | ||
288 | /********************************************************************** | |
289 | * Prototypes | |
290 | ********************************************************************* */ | |
291 | ||
292 | static void sbdma_initctx(sbmacdma_t *d, | |
293 | struct sbmac_softc *s, | |
294 | int chan, | |
295 | int txrx, | |
296 | int maxdescr); | |
297 | static void sbdma_channel_start(sbmacdma_t *d, int rxtx); | |
298 | static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m); | |
299 | static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m); | |
300 | static void sbdma_emptyring(sbmacdma_t *d); | |
301 | static void sbdma_fillring(sbmacdma_t *d); | |
693aa947 MM |
302 | static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d, int work_to_do, int poll); |
303 | static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll); | |
1da177e4 LT |
304 | static int sbmac_initctx(struct sbmac_softc *s); |
305 | static void sbmac_channel_start(struct sbmac_softc *s); | |
306 | static void sbmac_channel_stop(struct sbmac_softc *s); | |
307 | static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t); | |
308 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff); | |
309 | static uint64_t sbmac_addr2reg(unsigned char *ptr); | |
7d12e780 | 310 | static irqreturn_t sbmac_intr(int irq,void *dev_instance); |
1da177e4 LT |
311 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); |
312 | static void sbmac_setmulti(struct sbmac_softc *sc); | |
313 | static int sbmac_init(struct net_device *dev, int idx); | |
314 | static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed); | |
315 | static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc); | |
316 | ||
317 | static int sbmac_open(struct net_device *dev); | |
318 | static void sbmac_timer(unsigned long data); | |
319 | static void sbmac_tx_timeout (struct net_device *dev); | |
320 | static struct net_device_stats *sbmac_get_stats(struct net_device *dev); | |
321 | static void sbmac_set_rx_mode(struct net_device *dev); | |
322 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
323 | static int sbmac_close(struct net_device *dev); | |
bea3348e | 324 | static int sbmac_poll(struct napi_struct *napi, int budget); |
693aa947 | 325 | |
1da177e4 | 326 | static int sbmac_mii_poll(struct sbmac_softc *s,int noisy); |
59b81827 | 327 | static int sbmac_mii_probe(struct net_device *dev); |
1da177e4 LT |
328 | |
329 | static void sbmac_mii_sync(struct sbmac_softc *s); | |
330 | static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt); | |
331 | static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx); | |
332 | static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, | |
333 | unsigned int regval); | |
334 | ||
335 | ||
336 | /********************************************************************** | |
337 | * Globals | |
338 | ********************************************************************* */ | |
339 | ||
340 | static uint64_t sbmac_orig_hwaddr[MAX_UNITS]; | |
341 | ||
342 | ||
343 | /********************************************************************** | |
344 | * MDIO constants | |
345 | ********************************************************************* */ | |
346 | ||
347 | #define MII_COMMAND_START 0x01 | |
348 | #define MII_COMMAND_READ 0x02 | |
349 | #define MII_COMMAND_WRITE 0x01 | |
350 | #define MII_COMMAND_ACK 0x02 | |
351 | ||
352 | #define BMCR_RESET 0x8000 | |
353 | #define BMCR_LOOPBACK 0x4000 | |
354 | #define BMCR_SPEED0 0x2000 | |
355 | #define BMCR_ANENABLE 0x1000 | |
356 | #define BMCR_POWERDOWN 0x0800 | |
357 | #define BMCR_ISOLATE 0x0400 | |
358 | #define BMCR_RESTARTAN 0x0200 | |
359 | #define BMCR_DUPLEX 0x0100 | |
360 | #define BMCR_COLTEST 0x0080 | |
361 | #define BMCR_SPEED1 0x0040 | |
362 | #define BMCR_SPEED1000 BMCR_SPEED1 | |
363 | #define BMCR_SPEED100 BMCR_SPEED0 | |
364 | #define BMCR_SPEED10 0 | |
365 | ||
366 | #define BMSR_100BT4 0x8000 | |
367 | #define BMSR_100BT_FDX 0x4000 | |
368 | #define BMSR_100BT_HDX 0x2000 | |
369 | #define BMSR_10BT_FDX 0x1000 | |
370 | #define BMSR_10BT_HDX 0x0800 | |
371 | #define BMSR_100BT2_FDX 0x0400 | |
372 | #define BMSR_100BT2_HDX 0x0200 | |
373 | #define BMSR_1000BT_XSR 0x0100 | |
374 | #define BMSR_PRESUP 0x0040 | |
375 | #define BMSR_ANCOMPLT 0x0020 | |
376 | #define BMSR_REMFAULT 0x0010 | |
377 | #define BMSR_AUTONEG 0x0008 | |
378 | #define BMSR_LINKSTAT 0x0004 | |
379 | #define BMSR_JABDETECT 0x0002 | |
380 | #define BMSR_EXTCAPAB 0x0001 | |
381 | ||
382 | #define PHYIDR1 0x2000 | |
383 | #define PHYIDR2 0x5C60 | |
384 | ||
385 | #define ANAR_NP 0x8000 | |
386 | #define ANAR_RF 0x2000 | |
387 | #define ANAR_ASYPAUSE 0x0800 | |
388 | #define ANAR_PAUSE 0x0400 | |
389 | #define ANAR_T4 0x0200 | |
390 | #define ANAR_TXFD 0x0100 | |
391 | #define ANAR_TXHD 0x0080 | |
392 | #define ANAR_10FD 0x0040 | |
393 | #define ANAR_10HD 0x0020 | |
394 | #define ANAR_PSB 0x0001 | |
395 | ||
396 | #define ANLPAR_NP 0x8000 | |
397 | #define ANLPAR_ACK 0x4000 | |
398 | #define ANLPAR_RF 0x2000 | |
399 | #define ANLPAR_ASYPAUSE 0x0800 | |
400 | #define ANLPAR_PAUSE 0x0400 | |
401 | #define ANLPAR_T4 0x0200 | |
402 | #define ANLPAR_TXFD 0x0100 | |
403 | #define ANLPAR_TXHD 0x0080 | |
404 | #define ANLPAR_10FD 0x0040 | |
405 | #define ANLPAR_10HD 0x0020 | |
406 | #define ANLPAR_PSB 0x0001 /* 802.3 */ | |
407 | ||
408 | #define ANER_PDF 0x0010 | |
409 | #define ANER_LPNPABLE 0x0008 | |
410 | #define ANER_NPABLE 0x0004 | |
411 | #define ANER_PAGERX 0x0002 | |
412 | #define ANER_LPANABLE 0x0001 | |
413 | ||
414 | #define ANNPTR_NP 0x8000 | |
415 | #define ANNPTR_MP 0x2000 | |
416 | #define ANNPTR_ACK2 0x1000 | |
417 | #define ANNPTR_TOGTX 0x0800 | |
418 | #define ANNPTR_CODE 0x0008 | |
419 | ||
420 | #define ANNPRR_NP 0x8000 | |
421 | #define ANNPRR_MP 0x2000 | |
422 | #define ANNPRR_ACK3 0x1000 | |
423 | #define ANNPRR_TOGTX 0x0800 | |
424 | #define ANNPRR_CODE 0x0008 | |
425 | ||
426 | #define K1TCR_TESTMODE 0x0000 | |
427 | #define K1TCR_MSMCE 0x1000 | |
428 | #define K1TCR_MSCV 0x0800 | |
429 | #define K1TCR_RPTR 0x0400 | |
430 | #define K1TCR_1000BT_FDX 0x200 | |
431 | #define K1TCR_1000BT_HDX 0x100 | |
432 | ||
433 | #define K1STSR_MSMCFLT 0x8000 | |
434 | #define K1STSR_MSCFGRES 0x4000 | |
435 | #define K1STSR_LRSTAT 0x2000 | |
436 | #define K1STSR_RRSTAT 0x1000 | |
437 | #define K1STSR_LP1KFD 0x0800 | |
438 | #define K1STSR_LP1KHD 0x0400 | |
439 | #define K1STSR_LPASMDIR 0x0200 | |
440 | ||
441 | #define K1SCR_1KX_FDX 0x8000 | |
442 | #define K1SCR_1KX_HDX 0x4000 | |
443 | #define K1SCR_1KT_FDX 0x2000 | |
444 | #define K1SCR_1KT_HDX 0x1000 | |
445 | ||
446 | #define STRAP_PHY1 0x0800 | |
447 | #define STRAP_NCMODE 0x0400 | |
448 | #define STRAP_MANMSCFG 0x0200 | |
449 | #define STRAP_ANENABLE 0x0100 | |
450 | #define STRAP_MSVAL 0x0080 | |
451 | #define STRAP_1KHDXADV 0x0010 | |
452 | #define STRAP_1KFDXADV 0x0008 | |
453 | #define STRAP_100ADV 0x0004 | |
454 | #define STRAP_SPEEDSEL 0x0000 | |
455 | #define STRAP_SPEED100 0x0001 | |
456 | ||
457 | #define PHYSUP_SPEED1000 0x10 | |
458 | #define PHYSUP_SPEED100 0x08 | |
459 | #define PHYSUP_SPEED10 0x00 | |
460 | #define PHYSUP_LINKUP 0x04 | |
461 | #define PHYSUP_FDX 0x02 | |
462 | ||
463 | #define MII_BMCR 0x00 /* Basic mode control register (rw) */ | |
464 | #define MII_BMSR 0x01 /* Basic mode status register (ro) */ | |
59b81827 RB |
465 | #define MII_PHYIDR1 0x02 |
466 | #define MII_PHYIDR2 0x03 | |
467 | ||
1da177e4 LT |
468 | #define MII_K1STSR 0x0A /* 1K Status Register (ro) */ |
469 | #define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ | |
470 | ||
471 | ||
472 | #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ | |
473 | ||
474 | #define ENABLE 1 | |
475 | #define DISABLE 0 | |
476 | ||
477 | /********************************************************************** | |
478 | * SBMAC_MII_SYNC(s) | |
74b0247f | 479 | * |
1da177e4 LT |
480 | * Synchronize with the MII - send a pattern of bits to the MII |
481 | * that will guarantee that it is ready to accept a command. | |
74b0247f RB |
482 | * |
483 | * Input parameters: | |
1da177e4 | 484 | * s - sbmac structure |
74b0247f | 485 | * |
1da177e4 LT |
486 | * Return value: |
487 | * nothing | |
488 | ********************************************************************* */ | |
489 | ||
490 | static void sbmac_mii_sync(struct sbmac_softc *s) | |
491 | { | |
492 | int cnt; | |
493 | uint64_t bits; | |
494 | int mac_mdio_genc; | |
495 | ||
2039973a | 496 | mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; |
74b0247f | 497 | |
1da177e4 | 498 | bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; |
74b0247f | 499 | |
2039973a | 500 | __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); |
74b0247f | 501 | |
1da177e4 | 502 | for (cnt = 0; cnt < 32; cnt++) { |
2039973a RB |
503 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); |
504 | __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); | |
1da177e4 LT |
505 | } |
506 | } | |
507 | ||
508 | /********************************************************************** | |
509 | * SBMAC_MII_SENDDATA(s,data,bitcnt) | |
74b0247f | 510 | * |
1da177e4 LT |
511 | * Send some bits to the MII. The bits to be sent are right- |
512 | * justified in the 'data' parameter. | |
74b0247f RB |
513 | * |
514 | * Input parameters: | |
1da177e4 LT |
515 | * s - sbmac structure |
516 | * data - data to send | |
517 | * bitcnt - number of bits to send | |
518 | ********************************************************************* */ | |
519 | ||
520 | static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt) | |
521 | { | |
522 | int i; | |
523 | uint64_t bits; | |
524 | unsigned int curmask; | |
525 | int mac_mdio_genc; | |
526 | ||
2039973a | 527 | mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; |
74b0247f | 528 | |
1da177e4 | 529 | bits = M_MAC_MDIO_DIR_OUTPUT; |
2039973a | 530 | __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); |
74b0247f | 531 | |
1da177e4 | 532 | curmask = 1 << (bitcnt - 1); |
74b0247f | 533 | |
1da177e4 LT |
534 | for (i = 0; i < bitcnt; i++) { |
535 | if (data & curmask) | |
536 | bits |= M_MAC_MDIO_OUT; | |
537 | else bits &= ~M_MAC_MDIO_OUT; | |
2039973a RB |
538 | __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); |
539 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); | |
540 | __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio); | |
1da177e4 LT |
541 | curmask >>= 1; |
542 | } | |
543 | } | |
544 | ||
545 | ||
546 | ||
547 | /********************************************************************** | |
548 | * SBMAC_MII_READ(s,phyaddr,regidx) | |
74b0247f | 549 | * |
1da177e4 | 550 | * Read a PHY register. |
74b0247f RB |
551 | * |
552 | * Input parameters: | |
1da177e4 LT |
553 | * s - sbmac structure |
554 | * phyaddr - PHY's address | |
555 | * regidx = index of register to read | |
74b0247f | 556 | * |
1da177e4 LT |
557 | * Return value: |
558 | * value read, or 0 if an error occurred. | |
559 | ********************************************************************* */ | |
560 | ||
561 | static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx) | |
562 | { | |
563 | int idx; | |
564 | int error; | |
565 | int regval; | |
566 | int mac_mdio_genc; | |
567 | ||
568 | /* | |
569 | * Synchronize ourselves so that the PHY knows the next | |
570 | * thing coming down is a command | |
571 | */ | |
74b0247f | 572 | |
1da177e4 | 573 | sbmac_mii_sync(s); |
74b0247f | 574 | |
1da177e4 LT |
575 | /* |
576 | * Send the data to the PHY. The sequence is | |
577 | * a "start" command (2 bits) | |
578 | * a "read" command (2 bits) | |
579 | * the PHY addr (5 bits) | |
580 | * the register index (5 bits) | |
581 | */ | |
74b0247f | 582 | |
1da177e4 LT |
583 | sbmac_mii_senddata(s,MII_COMMAND_START, 2); |
584 | sbmac_mii_senddata(s,MII_COMMAND_READ, 2); | |
585 | sbmac_mii_senddata(s,phyaddr, 5); | |
586 | sbmac_mii_senddata(s,regidx, 5); | |
74b0247f | 587 | |
2039973a | 588 | mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; |
74b0247f RB |
589 | |
590 | /* | |
1da177e4 LT |
591 | * Switch the port around without a clock transition. |
592 | */ | |
2039973a | 593 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); |
74b0247f | 594 | |
1da177e4 LT |
595 | /* |
596 | * Send out a clock pulse to signal we want the status | |
597 | */ | |
74b0247f | 598 | |
2039973a RB |
599 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); |
600 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); | |
74b0247f RB |
601 | |
602 | /* | |
1da177e4 LT |
603 | * If an error occurred, the PHY will signal '1' back |
604 | */ | |
2039973a | 605 | error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN; |
74b0247f RB |
606 | |
607 | /* | |
1da177e4 LT |
608 | * Issue an 'idle' clock pulse, but keep the direction |
609 | * the same. | |
610 | */ | |
2039973a RB |
611 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); |
612 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); | |
74b0247f | 613 | |
1da177e4 | 614 | regval = 0; |
74b0247f | 615 | |
1da177e4 LT |
616 | for (idx = 0; idx < 16; idx++) { |
617 | regval <<= 1; | |
74b0247f | 618 | |
1da177e4 | 619 | if (error == 0) { |
2039973a | 620 | if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN) |
1da177e4 LT |
621 | regval |= 1; |
622 | } | |
74b0247f | 623 | |
2039973a RB |
624 | __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio); |
625 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio); | |
1da177e4 | 626 | } |
74b0247f | 627 | |
1da177e4 | 628 | /* Switch back to output */ |
2039973a | 629 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); |
74b0247f | 630 | |
1da177e4 LT |
631 | if (error == 0) |
632 | return regval; | |
633 | return 0; | |
634 | } | |
635 | ||
636 | ||
637 | /********************************************************************** | |
638 | * SBMAC_MII_WRITE(s,phyaddr,regidx,regval) | |
74b0247f | 639 | * |
1da177e4 | 640 | * Write a value to a PHY register. |
74b0247f RB |
641 | * |
642 | * Input parameters: | |
1da177e4 LT |
643 | * s - sbmac structure |
644 | * phyaddr - PHY to use | |
645 | * regidx - register within the PHY | |
646 | * regval - data to write to register | |
74b0247f | 647 | * |
1da177e4 LT |
648 | * Return value: |
649 | * nothing | |
650 | ********************************************************************* */ | |
651 | ||
652 | static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx, | |
653 | unsigned int regval) | |
654 | { | |
655 | int mac_mdio_genc; | |
656 | ||
657 | sbmac_mii_sync(s); | |
74b0247f | 658 | |
1da177e4 LT |
659 | sbmac_mii_senddata(s,MII_COMMAND_START,2); |
660 | sbmac_mii_senddata(s,MII_COMMAND_WRITE,2); | |
661 | sbmac_mii_senddata(s,phyaddr, 5); | |
662 | sbmac_mii_senddata(s,regidx, 5); | |
663 | sbmac_mii_senddata(s,MII_COMMAND_ACK,2); | |
664 | sbmac_mii_senddata(s,regval,16); | |
665 | ||
2039973a | 666 | mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC; |
1da177e4 | 667 | |
2039973a | 668 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio); |
1da177e4 LT |
669 | } |
670 | ||
671 | ||
672 | ||
673 | /********************************************************************** | |
674 | * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) | |
74b0247f | 675 | * |
1da177e4 LT |
676 | * Initialize a DMA channel context. Since there are potentially |
677 | * eight DMA channels per MAC, it's nice to do this in a standard | |
74b0247f RB |
678 | * way. |
679 | * | |
680 | * Input parameters: | |
1da177e4 LT |
681 | * d - sbmacdma_t structure (DMA channel context) |
682 | * s - sbmac_softc structure (pointer to a MAC) | |
683 | * chan - channel number (0..1 right now) | |
684 | * txrx - Identifies DMA_TX or DMA_RX for channel direction | |
685 | * maxdescr - number of descriptors | |
74b0247f | 686 | * |
1da177e4 LT |
687 | * Return value: |
688 | * nothing | |
689 | ********************************************************************* */ | |
690 | ||
691 | static void sbdma_initctx(sbmacdma_t *d, | |
692 | struct sbmac_softc *s, | |
693 | int chan, | |
694 | int txrx, | |
695 | int maxdescr) | |
696 | { | |
693aa947 MM |
697 | #ifdef CONFIG_SBMAC_COALESCE |
698 | int int_pktcnt, int_timeout; | |
699 | #endif | |
700 | ||
74b0247f RB |
701 | /* |
702 | * Save away interesting stuff in the structure | |
1da177e4 | 703 | */ |
74b0247f | 704 | |
1da177e4 LT |
705 | d->sbdma_eth = s; |
706 | d->sbdma_channel = chan; | |
707 | d->sbdma_txdir = txrx; | |
74b0247f | 708 | |
1da177e4 LT |
709 | #if 0 |
710 | /* RMON clearing */ | |
711 | s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; | |
712 | #endif | |
713 | ||
2039973a RB |
714 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES))); |
715 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS))); | |
716 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL))); | |
717 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL))); | |
718 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR))); | |
719 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT))); | |
720 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD))); | |
721 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD))); | |
722 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT))); | |
723 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE))); | |
724 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES))); | |
725 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST))); | |
726 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST))); | |
727 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD))); | |
728 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD))); | |
729 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT))); | |
730 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE))); | |
731 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR))); | |
732 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR))); | |
733 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR))); | |
734 | __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR))); | |
1da177e4 | 735 | |
74b0247f RB |
736 | /* |
737 | * initialize register pointers | |
1da177e4 | 738 | */ |
74b0247f RB |
739 | |
740 | d->sbdma_config0 = | |
1da177e4 | 741 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); |
74b0247f | 742 | d->sbdma_config1 = |
1da177e4 | 743 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); |
74b0247f | 744 | d->sbdma_dscrbase = |
1da177e4 | 745 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); |
74b0247f | 746 | d->sbdma_dscrcnt = |
1da177e4 | 747 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); |
74b0247f | 748 | d->sbdma_curdscr = |
1da177e4 | 749 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); |
693aa947 MM |
750 | if (d->sbdma_txdir) |
751 | d->sbdma_oodpktlost = NULL; | |
752 | else | |
753 | d->sbdma_oodpktlost = | |
754 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX); | |
74b0247f | 755 | |
1da177e4 LT |
756 | /* |
757 | * Allocate memory for the ring | |
758 | */ | |
74b0247f | 759 | |
1da177e4 | 760 | d->sbdma_maxdescr = maxdescr; |
74b0247f | 761 | |
693aa947 | 762 | d->sbdma_dscrtable_unaligned = |
74b0247f | 763 | d->sbdma_dscrtable = (sbdmadscr_t *) |
04115def RB |
764 | kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL); |
765 | ||
766 | /* | |
767 | * The descriptor table must be aligned to at least 16 bytes or the | |
768 | * MAC will corrupt it. | |
769 | */ | |
770 | d->sbdma_dscrtable = (sbdmadscr_t *) | |
771 | ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t)); | |
74b0247f | 772 | |
1da177e4 | 773 | memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t)); |
74b0247f | 774 | |
1da177e4 | 775 | d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; |
74b0247f | 776 | |
1da177e4 | 777 | d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); |
74b0247f | 778 | |
1da177e4 LT |
779 | /* |
780 | * And context table | |
781 | */ | |
74b0247f RB |
782 | |
783 | d->sbdma_ctxtable = (struct sk_buff **) | |
1da177e4 | 784 | kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL); |
74b0247f | 785 | |
1da177e4 | 786 | memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *)); |
74b0247f | 787 | |
1da177e4 LT |
788 | #ifdef CONFIG_SBMAC_COALESCE |
789 | /* | |
790 | * Setup Rx/Tx DMA coalescing defaults | |
791 | */ | |
792 | ||
693aa947 | 793 | int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx; |
1da177e4 LT |
794 | if ( int_pktcnt ) { |
795 | d->sbdma_int_pktcnt = int_pktcnt; | |
796 | } else { | |
797 | d->sbdma_int_pktcnt = 1; | |
798 | } | |
74b0247f | 799 | |
693aa947 | 800 | int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx; |
1da177e4 LT |
801 | if ( int_timeout ) { |
802 | d->sbdma_int_timeout = int_timeout; | |
803 | } else { | |
804 | d->sbdma_int_timeout = 0; | |
805 | } | |
806 | #endif | |
807 | ||
808 | } | |
809 | ||
810 | /********************************************************************** | |
811 | * SBDMA_CHANNEL_START(d) | |
74b0247f | 812 | * |
1da177e4 | 813 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
814 | * |
815 | * Input parameters: | |
1da177e4 LT |
816 | * d - DMA channel to init (context must be previously init'd |
817 | * rxtx - DMA_RX or DMA_TX depending on what type of channel | |
74b0247f | 818 | * |
1da177e4 LT |
819 | * Return value: |
820 | * nothing | |
821 | ********************************************************************* */ | |
822 | ||
823 | static void sbdma_channel_start(sbmacdma_t *d, int rxtx ) | |
824 | { | |
825 | /* | |
826 | * Turn on the DMA channel | |
827 | */ | |
74b0247f | 828 | |
1da177e4 | 829 | #ifdef CONFIG_SBMAC_COALESCE |
2039973a RB |
830 | __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | |
831 | 0, d->sbdma_config1); | |
832 | __raw_writeq(M_DMA_EOP_INT_EN | | |
1da177e4 LT |
833 | V_DMA_RINGSZ(d->sbdma_maxdescr) | |
834 | V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | | |
2039973a | 835 | 0, d->sbdma_config0); |
1da177e4 | 836 | #else |
2039973a RB |
837 | __raw_writeq(0, d->sbdma_config1); |
838 | __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) | | |
839 | 0, d->sbdma_config0); | |
1da177e4 LT |
840 | #endif |
841 | ||
2039973a | 842 | __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase); |
1da177e4 LT |
843 | |
844 | /* | |
845 | * Initialize ring pointers | |
846 | */ | |
847 | ||
848 | d->sbdma_addptr = d->sbdma_dscrtable; | |
849 | d->sbdma_remptr = d->sbdma_dscrtable; | |
850 | } | |
851 | ||
852 | /********************************************************************** | |
853 | * SBDMA_CHANNEL_STOP(d) | |
74b0247f | 854 | * |
1da177e4 | 855 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
856 | * |
857 | * Input parameters: | |
1da177e4 | 858 | * d - DMA channel to init (context must be previously init'd |
74b0247f | 859 | * |
1da177e4 LT |
860 | * Return value: |
861 | * nothing | |
862 | ********************************************************************* */ | |
863 | ||
864 | static void sbdma_channel_stop(sbmacdma_t *d) | |
865 | { | |
866 | /* | |
867 | * Turn off the DMA channel | |
868 | */ | |
74b0247f | 869 | |
2039973a | 870 | __raw_writeq(0, d->sbdma_config1); |
74b0247f | 871 | |
2039973a | 872 | __raw_writeq(0, d->sbdma_dscrbase); |
74b0247f | 873 | |
2039973a | 874 | __raw_writeq(0, d->sbdma_config0); |
74b0247f | 875 | |
1da177e4 LT |
876 | /* |
877 | * Zero ring pointers | |
878 | */ | |
74b0247f | 879 | |
2039973a RB |
880 | d->sbdma_addptr = NULL; |
881 | d->sbdma_remptr = NULL; | |
1da177e4 LT |
882 | } |
883 | ||
884 | static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset) | |
885 | { | |
886 | unsigned long addr; | |
887 | unsigned long newaddr; | |
74b0247f | 888 | |
1da177e4 | 889 | addr = (unsigned long) skb->data; |
74b0247f | 890 | |
1da177e4 | 891 | newaddr = (addr + power2 - 1) & ~(power2 - 1); |
74b0247f | 892 | |
1da177e4 LT |
893 | skb_reserve(skb,newaddr-addr+offset); |
894 | } | |
895 | ||
896 | ||
897 | /********************************************************************** | |
898 | * SBDMA_ADD_RCVBUFFER(d,sb) | |
74b0247f | 899 | * |
1da177e4 LT |
900 | * Add a buffer to the specified DMA channel. For receive channels, |
901 | * this queues a buffer for inbound packets. | |
74b0247f RB |
902 | * |
903 | * Input parameters: | |
1da177e4 LT |
904 | * d - DMA channel descriptor |
905 | * sb - sk_buff to add, or NULL if we should allocate one | |
74b0247f | 906 | * |
1da177e4 LT |
907 | * Return value: |
908 | * 0 if buffer could not be added (ring is full) | |
909 | * 1 if buffer added successfully | |
910 | ********************************************************************* */ | |
911 | ||
912 | ||
913 | static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb) | |
914 | { | |
915 | sbdmadscr_t *dsc; | |
916 | sbdmadscr_t *nextdsc; | |
917 | struct sk_buff *sb_new = NULL; | |
918 | int pktsize = ENET_PACKET_SIZE; | |
74b0247f | 919 | |
1da177e4 | 920 | /* get pointer to our current place in the ring */ |
74b0247f | 921 | |
1da177e4 LT |
922 | dsc = d->sbdma_addptr; |
923 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 924 | |
1da177e4 LT |
925 | /* |
926 | * figure out if the ring is full - if the next descriptor | |
927 | * is the same as the one that we're going to remove from | |
928 | * the ring, the ring is full | |
929 | */ | |
74b0247f | 930 | |
1da177e4 LT |
931 | if (nextdsc == d->sbdma_remptr) { |
932 | return -ENOSPC; | |
933 | } | |
934 | ||
74b0247f RB |
935 | /* |
936 | * Allocate a sk_buff if we don't already have one. | |
1da177e4 LT |
937 | * If we do have an sk_buff, reset it so that it's empty. |
938 | * | |
939 | * Note: sk_buffs don't seem to be guaranteed to have any sort | |
940 | * of alignment when they are allocated. Therefore, allocate enough | |
941 | * extra space to make sure that: | |
942 | * | |
943 | * 1. the data does not start in the middle of a cache line. | |
944 | * 2. The data does not end in the middle of a cache line | |
74b0247f | 945 | * 3. The buffer can be aligned such that the IP addresses are |
1da177e4 LT |
946 | * naturally aligned. |
947 | * | |
948 | * Remember, the SOCs MAC writes whole cache lines at a time, | |
949 | * without reading the old contents first. So, if the sk_buff's | |
950 | * data portion starts in the middle of a cache line, the SOC | |
951 | * DMA will trash the beginning (and ending) portions. | |
952 | */ | |
74b0247f | 953 | |
1da177e4 LT |
954 | if (sb == NULL) { |
955 | sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); | |
956 | if (sb_new == NULL) { | |
957 | printk(KERN_INFO "%s: sk_buff allocation failed\n", | |
958 | d->sbdma_eth->sbm_dev->name); | |
959 | return -ENOBUFS; | |
960 | } | |
961 | ||
962 | sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN); | |
1da177e4 LT |
963 | } |
964 | else { | |
965 | sb_new = sb; | |
74b0247f | 966 | /* |
1da177e4 LT |
967 | * nothing special to reinit buffer, it's already aligned |
968 | * and sb->data already points to a good place. | |
969 | */ | |
970 | } | |
74b0247f | 971 | |
1da177e4 | 972 | /* |
74b0247f | 973 | * fill in the descriptor |
1da177e4 | 974 | */ |
74b0247f | 975 | |
1da177e4 LT |
976 | #ifdef CONFIG_SBMAC_COALESCE |
977 | /* | |
978 | * Do not interrupt per DMA transfer. | |
979 | */ | |
689be439 | 980 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
2039973a | 981 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0; |
1da177e4 | 982 | #else |
689be439 | 983 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
1da177e4 LT |
984 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | |
985 | M_DMA_DSCRA_INTERRUPT; | |
986 | #endif | |
987 | ||
988 | /* receiving: no options */ | |
989 | dsc->dscr_b = 0; | |
74b0247f | 990 | |
1da177e4 | 991 | /* |
74b0247f | 992 | * fill in the context |
1da177e4 | 993 | */ |
74b0247f | 994 | |
1da177e4 | 995 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; |
74b0247f RB |
996 | |
997 | /* | |
998 | * point at next packet | |
1da177e4 | 999 | */ |
74b0247f | 1000 | |
1da177e4 | 1001 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
1002 | |
1003 | /* | |
1da177e4 LT |
1004 | * Give the buffer to the DMA engine. |
1005 | */ | |
74b0247f | 1006 | |
2039973a | 1007 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 1008 | |
1da177e4 LT |
1009 | return 0; /* we did it */ |
1010 | } | |
1011 | ||
1012 | /********************************************************************** | |
1013 | * SBDMA_ADD_TXBUFFER(d,sb) | |
74b0247f | 1014 | * |
1da177e4 LT |
1015 | * Add a transmit buffer to the specified DMA channel, causing a |
1016 | * transmit to start. | |
74b0247f RB |
1017 | * |
1018 | * Input parameters: | |
1da177e4 LT |
1019 | * d - DMA channel descriptor |
1020 | * sb - sk_buff to add | |
74b0247f | 1021 | * |
1da177e4 LT |
1022 | * Return value: |
1023 | * 0 transmit queued successfully | |
1024 | * otherwise error code | |
1025 | ********************************************************************* */ | |
1026 | ||
1027 | ||
1028 | static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb) | |
1029 | { | |
1030 | sbdmadscr_t *dsc; | |
1031 | sbdmadscr_t *nextdsc; | |
1032 | uint64_t phys; | |
1033 | uint64_t ncb; | |
1034 | int length; | |
74b0247f | 1035 | |
1da177e4 | 1036 | /* get pointer to our current place in the ring */ |
74b0247f | 1037 | |
1da177e4 LT |
1038 | dsc = d->sbdma_addptr; |
1039 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 1040 | |
1da177e4 LT |
1041 | /* |
1042 | * figure out if the ring is full - if the next descriptor | |
1043 | * is the same as the one that we're going to remove from | |
1044 | * the ring, the ring is full | |
1045 | */ | |
74b0247f | 1046 | |
1da177e4 LT |
1047 | if (nextdsc == d->sbdma_remptr) { |
1048 | return -ENOSPC; | |
1049 | } | |
74b0247f | 1050 | |
1da177e4 LT |
1051 | /* |
1052 | * Under Linux, it's not necessary to copy/coalesce buffers | |
1053 | * like it is on NetBSD. We think they're all contiguous, | |
1054 | * but that may not be true for GBE. | |
1055 | */ | |
74b0247f | 1056 | |
1da177e4 | 1057 | length = sb->len; |
74b0247f | 1058 | |
1da177e4 LT |
1059 | /* |
1060 | * fill in the descriptor. Note that the number of cache | |
1061 | * blocks in the descriptor is the number of blocks | |
1062 | * *spanned*, so we need to add in the offset (if any) | |
1063 | * while doing the calculation. | |
1064 | */ | |
74b0247f | 1065 | |
1da177e4 LT |
1066 | phys = virt_to_phys(sb->data); |
1067 | ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); | |
1068 | ||
74b0247f | 1069 | dsc->dscr_a = phys | |
1da177e4 LT |
1070 | V_DMA_DSCRA_A_SIZE(ncb) | |
1071 | #ifndef CONFIG_SBMAC_COALESCE | |
1072 | M_DMA_DSCRA_INTERRUPT | | |
1073 | #endif | |
1074 | M_DMA_ETHTX_SOP; | |
74b0247f | 1075 | |
1da177e4 LT |
1076 | /* transmitting: set outbound options and length */ |
1077 | ||
1078 | dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | | |
1079 | V_DMA_DSCRB_PKT_SIZE(length); | |
74b0247f | 1080 | |
1da177e4 | 1081 | /* |
74b0247f | 1082 | * fill in the context |
1da177e4 | 1083 | */ |
74b0247f | 1084 | |
1da177e4 | 1085 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; |
74b0247f RB |
1086 | |
1087 | /* | |
1088 | * point at next packet | |
1da177e4 | 1089 | */ |
74b0247f | 1090 | |
1da177e4 | 1091 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
1092 | |
1093 | /* | |
1da177e4 LT |
1094 | * Give the buffer to the DMA engine. |
1095 | */ | |
74b0247f | 1096 | |
2039973a | 1097 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 1098 | |
1da177e4 LT |
1099 | return 0; /* we did it */ |
1100 | } | |
1101 | ||
1102 | ||
1103 | ||
1104 | ||
1105 | /********************************************************************** | |
1106 | * SBDMA_EMPTYRING(d) | |
74b0247f | 1107 | * |
1da177e4 | 1108 | * Free all allocated sk_buffs on the specified DMA channel; |
74b0247f RB |
1109 | * |
1110 | * Input parameters: | |
1da177e4 | 1111 | * d - DMA channel |
74b0247f | 1112 | * |
1da177e4 LT |
1113 | * Return value: |
1114 | * nothing | |
1115 | ********************************************************************* */ | |
1116 | ||
1117 | static void sbdma_emptyring(sbmacdma_t *d) | |
1118 | { | |
1119 | int idx; | |
1120 | struct sk_buff *sb; | |
74b0247f | 1121 | |
1da177e4 LT |
1122 | for (idx = 0; idx < d->sbdma_maxdescr; idx++) { |
1123 | sb = d->sbdma_ctxtable[idx]; | |
1124 | if (sb) { | |
1125 | dev_kfree_skb(sb); | |
1126 | d->sbdma_ctxtable[idx] = NULL; | |
1127 | } | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | ||
1132 | /********************************************************************** | |
1133 | * SBDMA_FILLRING(d) | |
74b0247f | 1134 | * |
1da177e4 LT |
1135 | * Fill the specified DMA channel (must be receive channel) |
1136 | * with sk_buffs | |
74b0247f RB |
1137 | * |
1138 | * Input parameters: | |
1da177e4 | 1139 | * d - DMA channel |
74b0247f | 1140 | * |
1da177e4 LT |
1141 | * Return value: |
1142 | * nothing | |
1143 | ********************************************************************* */ | |
1144 | ||
1145 | static void sbdma_fillring(sbmacdma_t *d) | |
1146 | { | |
1147 | int idx; | |
74b0247f | 1148 | |
1da177e4 LT |
1149 | for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) { |
1150 | if (sbdma_add_rcvbuffer(d,NULL) != 0) | |
1151 | break; | |
1152 | } | |
1153 | } | |
1154 | ||
d6830018 DS |
1155 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1156 | static void sbmac_netpoll(struct net_device *netdev) | |
1157 | { | |
1158 | struct sbmac_softc *sc = netdev_priv(netdev); | |
1159 | int irq = sc->sbm_dev->irq; | |
1160 | ||
1161 | __raw_writeq(0, sc->sbm_imr); | |
1162 | ||
0da2f0f1 | 1163 | sbmac_intr(irq, netdev); |
d6830018 DS |
1164 | |
1165 | #ifdef CONFIG_SBMAC_COALESCE | |
1166 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
1167 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
1168 | sc->sbm_imr); | |
1169 | #else | |
1170 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | | |
1171 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); | |
1172 | #endif | |
1173 | } | |
1174 | #endif | |
1da177e4 LT |
1175 | |
1176 | /********************************************************************** | |
693aa947 | 1177 | * SBDMA_RX_PROCESS(sc,d,work_to_do,poll) |
74b0247f RB |
1178 | * |
1179 | * Process "completed" receive buffers on the specified DMA channel. | |
1da177e4 | 1180 | * |
74b0247f | 1181 | * Input parameters: |
693aa947 MM |
1182 | * sc - softc structure |
1183 | * d - DMA channel context | |
1184 | * work_to_do - no. of packets to process before enabling interrupt | |
1185 | * again (for NAPI) | |
1186 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1187 | * |
1da177e4 LT |
1188 | * Return value: |
1189 | * nothing | |
1190 | ********************************************************************* */ | |
1191 | ||
693aa947 MM |
1192 | static int sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d, |
1193 | int work_to_do, int poll) | |
1da177e4 LT |
1194 | { |
1195 | int curidx; | |
1196 | int hwidx; | |
1197 | sbdmadscr_t *dsc; | |
1198 | struct sk_buff *sb; | |
1199 | int len; | |
693aa947 MM |
1200 | int work_done = 0; |
1201 | int dropped = 0; | |
74b0247f | 1202 | |
693aa947 MM |
1203 | prefetch(d); |
1204 | ||
1205 | again: | |
1206 | /* Check if the HW dropped any frames */ | |
1207 | sc->sbm_stats.rx_fifo_errors | |
1208 | += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff; | |
1209 | __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost); | |
1210 | ||
1211 | while (work_to_do-- > 0) { | |
74b0247f | 1212 | /* |
1da177e4 LT |
1213 | * figure out where we are (as an index) and where |
1214 | * the hardware is (also as an index) | |
1215 | * | |
74b0247f | 1216 | * This could be done faster if (for example) the |
1da177e4 LT |
1217 | * descriptor table was page-aligned and contiguous in |
1218 | * both virtual and physical memory -- you could then | |
1219 | * just compare the low-order bits of the virtual address | |
1220 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1221 | */ | |
74b0247f | 1222 | |
693aa947 MM |
1223 | dsc = d->sbdma_remptr; |
1224 | curidx = dsc - d->sbdma_dscrtable; | |
1225 | ||
1226 | prefetch(dsc); | |
1227 | prefetch(&d->sbdma_ctxtable[curidx]); | |
1228 | ||
2039973a | 1229 | hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1da177e4 | 1230 | d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); |
74b0247f | 1231 | |
1da177e4 LT |
1232 | /* |
1233 | * If they're the same, that means we've processed all | |
1234 | * of the descriptors up to (but not including) the one that | |
1235 | * the hardware is working on right now. | |
1236 | */ | |
74b0247f | 1237 | |
1da177e4 | 1238 | if (curidx == hwidx) |
693aa947 | 1239 | goto done; |
74b0247f | 1240 | |
1da177e4 LT |
1241 | /* |
1242 | * Otherwise, get the packet's sk_buff ptr back | |
1243 | */ | |
74b0247f | 1244 | |
1da177e4 LT |
1245 | sb = d->sbdma_ctxtable[curidx]; |
1246 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1247 | |
1da177e4 | 1248 | len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; |
74b0247f | 1249 | |
1da177e4 LT |
1250 | /* |
1251 | * Check packet status. If good, process it. | |
1252 | * If not, silently drop it and put it back on the | |
1253 | * receive ring. | |
1254 | */ | |
74b0247f | 1255 | |
693aa947 | 1256 | if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { |
74b0247f | 1257 | |
1da177e4 LT |
1258 | /* |
1259 | * Add a new buffer to replace the old one. If we fail | |
1260 | * to allocate a buffer, we're going to drop this | |
1261 | * packet and put it right back on the receive ring. | |
1262 | */ | |
74b0247f | 1263 | |
693aa947 MM |
1264 | if (unlikely (sbdma_add_rcvbuffer(d,NULL) == |
1265 | -ENOBUFS)) { | |
1266 | sc->sbm_stats.rx_dropped++; | |
1da177e4 | 1267 | sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */ |
693aa947 MM |
1268 | /* No point in continuing at the moment */ |
1269 | printk(KERN_ERR "dropped packet (1)\n"); | |
1270 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
1271 | goto done; | |
1da177e4 LT |
1272 | } else { |
1273 | /* | |
1274 | * Set length into the packet | |
1275 | */ | |
1276 | skb_put(sb,len); | |
74b0247f | 1277 | |
1da177e4 LT |
1278 | /* |
1279 | * Buffer has been replaced on the | |
1280 | * receive ring. Pass the buffer to | |
1281 | * the kernel | |
1282 | */ | |
1da177e4 LT |
1283 | sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); |
1284 | /* Check hw IPv4/TCP checksum if supported */ | |
1285 | if (sc->rx_hw_checksum == ENABLE) { | |
1286 | if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && | |
1287 | !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { | |
1288 | sb->ip_summed = CHECKSUM_UNNECESSARY; | |
1289 | /* don't need to set sb->csum */ | |
1290 | } else { | |
1291 | sb->ip_summed = CHECKSUM_NONE; | |
1292 | } | |
1293 | } | |
693aa947 MM |
1294 | prefetch(sb->data); |
1295 | prefetch((const void *)(((char *)sb->data)+32)); | |
1296 | if (poll) | |
1297 | dropped = netif_receive_skb(sb); | |
1298 | else | |
1299 | dropped = netif_rx(sb); | |
1300 | ||
1301 | if (dropped == NET_RX_DROP) { | |
1302 | sc->sbm_stats.rx_dropped++; | |
1303 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
1304 | goto done; | |
1305 | } | |
1306 | else { | |
1307 | sc->sbm_stats.rx_bytes += len; | |
1308 | sc->sbm_stats.rx_packets++; | |
1309 | } | |
1da177e4 LT |
1310 | } |
1311 | } else { | |
1312 | /* | |
1313 | * Packet was mangled somehow. Just drop it and | |
1314 | * put it back on the receive ring. | |
1315 | */ | |
1316 | sc->sbm_stats.rx_errors++; | |
1317 | sbdma_add_rcvbuffer(d,sb); | |
1318 | } | |
74b0247f RB |
1319 | |
1320 | ||
1321 | /* | |
1da177e4 LT |
1322 | * .. and advance to the next buffer. |
1323 | */ | |
74b0247f | 1324 | |
1da177e4 | 1325 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
693aa947 MM |
1326 | work_done++; |
1327 | } | |
1328 | if (!poll) { | |
1329 | work_to_do = 32; | |
1330 | goto again; /* collect fifo drop statistics again */ | |
1da177e4 | 1331 | } |
693aa947 MM |
1332 | done: |
1333 | return work_done; | |
1da177e4 LT |
1334 | } |
1335 | ||
1da177e4 LT |
1336 | /********************************************************************** |
1337 | * SBDMA_TX_PROCESS(sc,d) | |
74b0247f RB |
1338 | * |
1339 | * Process "completed" transmit buffers on the specified DMA channel. | |
1da177e4 LT |
1340 | * This is normally called within the interrupt service routine. |
1341 | * Note that this isn't really ideal for priority channels, since | |
74b0247f RB |
1342 | * it processes all of the packets on a given channel before |
1343 | * returning. | |
1da177e4 | 1344 | * |
74b0247f | 1345 | * Input parameters: |
1da177e4 | 1346 | * sc - softc structure |
693aa947 MM |
1347 | * d - DMA channel context |
1348 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1349 | * |
1da177e4 LT |
1350 | * Return value: |
1351 | * nothing | |
1352 | ********************************************************************* */ | |
1353 | ||
693aa947 | 1354 | static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d, int poll) |
1da177e4 LT |
1355 | { |
1356 | int curidx; | |
1357 | int hwidx; | |
1358 | sbdmadscr_t *dsc; | |
1359 | struct sk_buff *sb; | |
1360 | unsigned long flags; | |
693aa947 | 1361 | int packets_handled = 0; |
1da177e4 LT |
1362 | |
1363 | spin_lock_irqsave(&(sc->sbm_lock), flags); | |
74b0247f | 1364 | |
693aa947 MM |
1365 | if (d->sbdma_remptr == d->sbdma_addptr) |
1366 | goto end_unlock; | |
1367 | ||
1368 | hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - | |
1369 | d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); | |
1370 | ||
1da177e4 | 1371 | for (;;) { |
74b0247f | 1372 | /* |
1da177e4 LT |
1373 | * figure out where we are (as an index) and where |
1374 | * the hardware is (also as an index) | |
1375 | * | |
74b0247f | 1376 | * This could be done faster if (for example) the |
1da177e4 LT |
1377 | * descriptor table was page-aligned and contiguous in |
1378 | * both virtual and physical memory -- you could then | |
1379 | * just compare the low-order bits of the virtual address | |
1380 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1381 | */ | |
74b0247f | 1382 | |
1da177e4 | 1383 | curidx = d->sbdma_remptr - d->sbdma_dscrtable; |
1da177e4 LT |
1384 | |
1385 | /* | |
1386 | * If they're the same, that means we've processed all | |
1387 | * of the descriptors up to (but not including) the one that | |
1388 | * the hardware is working on right now. | |
1389 | */ | |
74b0247f | 1390 | |
1da177e4 LT |
1391 | if (curidx == hwidx) |
1392 | break; | |
74b0247f | 1393 | |
1da177e4 LT |
1394 | /* |
1395 | * Otherwise, get the packet's sk_buff ptr back | |
1396 | */ | |
74b0247f | 1397 | |
1da177e4 LT |
1398 | dsc = &(d->sbdma_dscrtable[curidx]); |
1399 | sb = d->sbdma_ctxtable[curidx]; | |
1400 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1401 | |
1da177e4 LT |
1402 | /* |
1403 | * Stats | |
1404 | */ | |
74b0247f | 1405 | |
1da177e4 LT |
1406 | sc->sbm_stats.tx_bytes += sb->len; |
1407 | sc->sbm_stats.tx_packets++; | |
74b0247f | 1408 | |
1da177e4 LT |
1409 | /* |
1410 | * for transmits, we just free buffers. | |
1411 | */ | |
74b0247f | 1412 | |
1da177e4 | 1413 | dev_kfree_skb_irq(sb); |
74b0247f RB |
1414 | |
1415 | /* | |
1da177e4 LT |
1416 | * .. and advance to the next buffer. |
1417 | */ | |
1418 | ||
1419 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
74b0247f | 1420 | |
693aa947 MM |
1421 | packets_handled++; |
1422 | ||
1da177e4 | 1423 | } |
74b0247f | 1424 | |
1da177e4 LT |
1425 | /* |
1426 | * Decide if we should wake up the protocol or not. | |
1427 | * Other drivers seem to do this when we reach a low | |
1428 | * watermark on the transmit queue. | |
1429 | */ | |
74b0247f | 1430 | |
693aa947 MM |
1431 | if (packets_handled) |
1432 | netif_wake_queue(d->sbdma_eth->sbm_dev); | |
74b0247f | 1433 | |
693aa947 | 1434 | end_unlock: |
1da177e4 | 1435 | spin_unlock_irqrestore(&(sc->sbm_lock), flags); |
74b0247f | 1436 | |
1da177e4 LT |
1437 | } |
1438 | ||
1439 | ||
1440 | ||
1441 | /********************************************************************** | |
1442 | * SBMAC_INITCTX(s) | |
74b0247f | 1443 | * |
1da177e4 LT |
1444 | * Initialize an Ethernet context structure - this is called |
1445 | * once per MAC on the 1250. Memory is allocated here, so don't | |
1446 | * call it again from inside the ioctl routines that bring the | |
1447 | * interface up/down | |
74b0247f RB |
1448 | * |
1449 | * Input parameters: | |
1da177e4 | 1450 | * s - sbmac context structure |
74b0247f | 1451 | * |
1da177e4 LT |
1452 | * Return value: |
1453 | * 0 | |
1454 | ********************************************************************* */ | |
1455 | ||
1456 | static int sbmac_initctx(struct sbmac_softc *s) | |
1457 | { | |
74b0247f RB |
1458 | |
1459 | /* | |
1460 | * figure out the addresses of some ports | |
1da177e4 | 1461 | */ |
74b0247f | 1462 | |
1da177e4 LT |
1463 | s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; |
1464 | s->sbm_maccfg = s->sbm_base + R_MAC_CFG; | |
1465 | s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; | |
1466 | s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; | |
1467 | s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; | |
1468 | s->sbm_isr = s->sbm_base + R_MAC_STATUS; | |
1469 | s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; | |
1470 | s->sbm_mdio = s->sbm_base + R_MAC_MDIO; | |
1471 | ||
1472 | s->sbm_phys[0] = 1; | |
1473 | s->sbm_phys[1] = 0; | |
1474 | ||
1475 | s->sbm_phy_oldbmsr = 0; | |
1476 | s->sbm_phy_oldanlpar = 0; | |
1477 | s->sbm_phy_oldk1stsr = 0; | |
1478 | s->sbm_phy_oldlinkstat = 0; | |
74b0247f | 1479 | |
1da177e4 LT |
1480 | /* |
1481 | * Initialize the DMA channels. Right now, only one per MAC is used | |
1482 | * Note: Only do this _once_, as it allocates memory from the kernel! | |
1483 | */ | |
74b0247f | 1484 | |
1da177e4 LT |
1485 | sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); |
1486 | sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); | |
74b0247f | 1487 | |
1da177e4 LT |
1488 | /* |
1489 | * initial state is OFF | |
1490 | */ | |
74b0247f | 1491 | |
1da177e4 | 1492 | s->sbm_state = sbmac_state_off; |
74b0247f | 1493 | |
1da177e4 LT |
1494 | /* |
1495 | * Initial speed is (XXX TEMP) 10MBit/s HDX no FC | |
1496 | */ | |
74b0247f | 1497 | |
1da177e4 LT |
1498 | s->sbm_speed = sbmac_speed_10; |
1499 | s->sbm_duplex = sbmac_duplex_half; | |
1500 | s->sbm_fc = sbmac_fc_disabled; | |
74b0247f | 1501 | |
1da177e4 LT |
1502 | return 0; |
1503 | } | |
1504 | ||
1505 | ||
1506 | static void sbdma_uninitctx(struct sbmacdma_s *d) | |
1507 | { | |
693aa947 MM |
1508 | if (d->sbdma_dscrtable_unaligned) { |
1509 | kfree(d->sbdma_dscrtable_unaligned); | |
1510 | d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL; | |
1da177e4 | 1511 | } |
74b0247f | 1512 | |
1da177e4 LT |
1513 | if (d->sbdma_ctxtable) { |
1514 | kfree(d->sbdma_ctxtable); | |
1515 | d->sbdma_ctxtable = NULL; | |
1516 | } | |
1517 | } | |
1518 | ||
1519 | ||
1520 | static void sbmac_uninitctx(struct sbmac_softc *sc) | |
1521 | { | |
1522 | sbdma_uninitctx(&(sc->sbm_txdma)); | |
1523 | sbdma_uninitctx(&(sc->sbm_rxdma)); | |
1524 | } | |
1525 | ||
1526 | ||
1527 | /********************************************************************** | |
1528 | * SBMAC_CHANNEL_START(s) | |
74b0247f | 1529 | * |
1da177e4 | 1530 | * Start packet processing on this MAC. |
74b0247f RB |
1531 | * |
1532 | * Input parameters: | |
1da177e4 | 1533 | * s - sbmac structure |
74b0247f | 1534 | * |
1da177e4 LT |
1535 | * Return value: |
1536 | * nothing | |
1537 | ********************************************************************* */ | |
1538 | ||
1539 | static void sbmac_channel_start(struct sbmac_softc *s) | |
1540 | { | |
1541 | uint64_t reg; | |
2039973a | 1542 | volatile void __iomem *port; |
1da177e4 LT |
1543 | uint64_t cfg,fifo,framecfg; |
1544 | int idx, th_value; | |
74b0247f | 1545 | |
1da177e4 LT |
1546 | /* |
1547 | * Don't do this if running | |
1548 | */ | |
1549 | ||
1550 | if (s->sbm_state == sbmac_state_on) | |
1551 | return; | |
74b0247f | 1552 | |
1da177e4 LT |
1553 | /* |
1554 | * Bring the controller out of reset, but leave it off. | |
1555 | */ | |
74b0247f | 1556 | |
2039973a | 1557 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1558 | |
1da177e4 LT |
1559 | /* |
1560 | * Ignore all received packets | |
1561 | */ | |
74b0247f | 1562 | |
2039973a | 1563 | __raw_writeq(0, s->sbm_rxfilter); |
74b0247f RB |
1564 | |
1565 | /* | |
1da177e4 LT |
1566 | * Calculate values for various control registers. |
1567 | */ | |
74b0247f | 1568 | |
1da177e4 | 1569 | cfg = M_MAC_RETRY_EN | |
74b0247f | 1570 | M_MAC_TX_HOLD_SOP_EN | |
1da177e4 LT |
1571 | V_MAC_TX_PAUSE_CNT_16K | |
1572 | M_MAC_AP_STAT_EN | | |
1573 | M_MAC_FAST_SYNC | | |
1574 | M_MAC_SS_EN | | |
1575 | 0; | |
74b0247f RB |
1576 | |
1577 | /* | |
1da177e4 LT |
1578 | * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars |
1579 | * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above | |
1580 | * Use a larger RD_THRSH for gigabit | |
1581 | */ | |
f90fdc3c | 1582 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) |
1da177e4 | 1583 | th_value = 28; |
f90fdc3c RB |
1584 | else |
1585 | th_value = 64; | |
1da177e4 LT |
1586 | |
1587 | fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ | |
1588 | ((s->sbm_speed == sbmac_speed_1000) | |
1589 | ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | | |
1590 | V_MAC_TX_RL_THRSH(4) | | |
1591 | V_MAC_RX_PL_THRSH(4) | | |
1592 | V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ | |
1593 | V_MAC_RX_PL_THRSH(4) | | |
1594 | V_MAC_RX_RL_THRSH(8) | | |
1595 | 0; | |
1596 | ||
1597 | framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | | |
1598 | V_MAC_MAX_FRAMESZ_DEFAULT | | |
1599 | V_MAC_BACKOFF_SEL(1); | |
1600 | ||
1601 | /* | |
74b0247f | 1602 | * Clear out the hash address map |
1da177e4 | 1603 | */ |
74b0247f | 1604 | |
1da177e4 LT |
1605 | port = s->sbm_base + R_MAC_HASH_BASE; |
1606 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { | |
2039973a | 1607 | __raw_writeq(0, port); |
1da177e4 LT |
1608 | port += sizeof(uint64_t); |
1609 | } | |
74b0247f | 1610 | |
1da177e4 LT |
1611 | /* |
1612 | * Clear out the exact-match table | |
1613 | */ | |
74b0247f | 1614 | |
1da177e4 LT |
1615 | port = s->sbm_base + R_MAC_ADDR_BASE; |
1616 | for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { | |
2039973a | 1617 | __raw_writeq(0, port); |
1da177e4 LT |
1618 | port += sizeof(uint64_t); |
1619 | } | |
74b0247f | 1620 | |
1da177e4 LT |
1621 | /* |
1622 | * Clear out the DMA Channel mapping table registers | |
1623 | */ | |
74b0247f | 1624 | |
1da177e4 LT |
1625 | port = s->sbm_base + R_MAC_CHUP0_BASE; |
1626 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1627 | __raw_writeq(0, port); |
1da177e4 LT |
1628 | port += sizeof(uint64_t); |
1629 | } | |
1630 | ||
1631 | ||
1632 | port = s->sbm_base + R_MAC_CHLO0_BASE; | |
1633 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1634 | __raw_writeq(0, port); |
1da177e4 LT |
1635 | port += sizeof(uint64_t); |
1636 | } | |
74b0247f | 1637 | |
1da177e4 LT |
1638 | /* |
1639 | * Program the hardware address. It goes into the hardware-address | |
1640 | * register as well as the first filter register. | |
1641 | */ | |
74b0247f | 1642 | |
1da177e4 | 1643 | reg = sbmac_addr2reg(s->sbm_hwaddr); |
74b0247f | 1644 | |
1da177e4 | 1645 | port = s->sbm_base + R_MAC_ADDR_BASE; |
2039973a | 1646 | __raw_writeq(reg, port); |
1da177e4 LT |
1647 | port = s->sbm_base + R_MAC_ETHERNET_ADDR; |
1648 | ||
1649 | #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS | |
1650 | /* | |
1651 | * Pass1 SOCs do not receive packets addressed to the | |
1652 | * destination address in the R_MAC_ETHERNET_ADDR register. | |
1653 | * Set the value to zero. | |
1654 | */ | |
2039973a | 1655 | __raw_writeq(0, port); |
1da177e4 | 1656 | #else |
2039973a | 1657 | __raw_writeq(reg, port); |
1da177e4 | 1658 | #endif |
74b0247f | 1659 | |
1da177e4 LT |
1660 | /* |
1661 | * Set the receive filter for no packets, and write values | |
1662 | * to the various config registers | |
1663 | */ | |
74b0247f | 1664 | |
2039973a RB |
1665 | __raw_writeq(0, s->sbm_rxfilter); |
1666 | __raw_writeq(0, s->sbm_imr); | |
1667 | __raw_writeq(framecfg, s->sbm_framecfg); | |
1668 | __raw_writeq(fifo, s->sbm_fifocfg); | |
1669 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1670 | |
1da177e4 LT |
1671 | /* |
1672 | * Initialize DMA channels (rings should be ok now) | |
1673 | */ | |
74b0247f | 1674 | |
1da177e4 LT |
1675 | sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); |
1676 | sbdma_channel_start(&(s->sbm_txdma), DMA_TX); | |
74b0247f | 1677 | |
1da177e4 LT |
1678 | /* |
1679 | * Configure the speed, duplex, and flow control | |
1680 | */ | |
1681 | ||
1682 | sbmac_set_speed(s,s->sbm_speed); | |
1683 | sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); | |
74b0247f | 1684 | |
1da177e4 LT |
1685 | /* |
1686 | * Fill the receive ring | |
1687 | */ | |
74b0247f | 1688 | |
1da177e4 | 1689 | sbdma_fillring(&(s->sbm_rxdma)); |
74b0247f RB |
1690 | |
1691 | /* | |
1da177e4 | 1692 | * Turn on the rest of the bits in the enable register |
74b0247f RB |
1693 | */ |
1694 | ||
f90fdc3c RB |
1695 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
1696 | __raw_writeq(M_MAC_RXDMA_EN0 | | |
1697 | M_MAC_TXDMA_EN0, s->sbm_macenable); | |
1698 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
2039973a | 1699 | __raw_writeq(M_MAC_RXDMA_EN0 | |
1da177e4 LT |
1700 | M_MAC_TXDMA_EN0 | |
1701 | M_MAC_RX_ENABLE | | |
2039973a | 1702 | M_MAC_TX_ENABLE, s->sbm_macenable); |
f90fdc3c RB |
1703 | #else |
1704 | #error invalid SiByte MAC configuation | |
1705 | #endif | |
1da177e4 LT |
1706 | |
1707 | #ifdef CONFIG_SBMAC_COALESCE | |
2039973a RB |
1708 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | |
1709 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1710 | #else |
2039973a RB |
1711 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
1712 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1713 | #endif |
74b0247f RB |
1714 | |
1715 | /* | |
1716 | * Enable receiving unicasts and broadcasts | |
1da177e4 | 1717 | */ |
74b0247f | 1718 | |
2039973a | 1719 | __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter); |
74b0247f | 1720 | |
1da177e4 | 1721 | /* |
74b0247f | 1722 | * we're running now. |
1da177e4 | 1723 | */ |
74b0247f | 1724 | |
1da177e4 | 1725 | s->sbm_state = sbmac_state_on; |
74b0247f RB |
1726 | |
1727 | /* | |
1728 | * Program multicast addresses | |
1da177e4 | 1729 | */ |
74b0247f | 1730 | |
1da177e4 | 1731 | sbmac_setmulti(s); |
74b0247f RB |
1732 | |
1733 | /* | |
1734 | * If channel was in promiscuous mode before, turn that on | |
1da177e4 | 1735 | */ |
74b0247f | 1736 | |
1da177e4 LT |
1737 | if (s->sbm_devflags & IFF_PROMISC) { |
1738 | sbmac_promiscuous_mode(s,1); | |
1739 | } | |
74b0247f | 1740 | |
1da177e4 LT |
1741 | } |
1742 | ||
1743 | ||
1744 | /********************************************************************** | |
1745 | * SBMAC_CHANNEL_STOP(s) | |
74b0247f | 1746 | * |
1da177e4 | 1747 | * Stop packet processing on this MAC. |
74b0247f RB |
1748 | * |
1749 | * Input parameters: | |
1da177e4 | 1750 | * s - sbmac structure |
74b0247f | 1751 | * |
1da177e4 LT |
1752 | * Return value: |
1753 | * nothing | |
1754 | ********************************************************************* */ | |
1755 | ||
1756 | static void sbmac_channel_stop(struct sbmac_softc *s) | |
1757 | { | |
1758 | /* don't do this if already stopped */ | |
74b0247f | 1759 | |
1da177e4 LT |
1760 | if (s->sbm_state == sbmac_state_off) |
1761 | return; | |
74b0247f | 1762 | |
1da177e4 | 1763 | /* don't accept any packets, disable all interrupts */ |
74b0247f | 1764 | |
2039973a RB |
1765 | __raw_writeq(0, s->sbm_rxfilter); |
1766 | __raw_writeq(0, s->sbm_imr); | |
74b0247f | 1767 | |
1da177e4 | 1768 | /* Turn off ticker */ |
74b0247f | 1769 | |
1da177e4 | 1770 | /* XXX */ |
74b0247f | 1771 | |
1da177e4 | 1772 | /* turn off receiver and transmitter */ |
74b0247f | 1773 | |
2039973a | 1774 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1775 | |
1da177e4 | 1776 | /* We're stopped now. */ |
74b0247f | 1777 | |
1da177e4 | 1778 | s->sbm_state = sbmac_state_off; |
74b0247f | 1779 | |
1da177e4 LT |
1780 | /* |
1781 | * Stop DMA channels (rings should be ok now) | |
1782 | */ | |
74b0247f | 1783 | |
1da177e4 LT |
1784 | sbdma_channel_stop(&(s->sbm_rxdma)); |
1785 | sbdma_channel_stop(&(s->sbm_txdma)); | |
74b0247f | 1786 | |
1da177e4 | 1787 | /* Empty the receive and transmit rings */ |
74b0247f | 1788 | |
1da177e4 LT |
1789 | sbdma_emptyring(&(s->sbm_rxdma)); |
1790 | sbdma_emptyring(&(s->sbm_txdma)); | |
74b0247f | 1791 | |
1da177e4 LT |
1792 | } |
1793 | ||
1794 | /********************************************************************** | |
1795 | * SBMAC_SET_CHANNEL_STATE(state) | |
74b0247f | 1796 | * |
1da177e4 | 1797 | * Set the channel's state ON or OFF |
74b0247f RB |
1798 | * |
1799 | * Input parameters: | |
1da177e4 | 1800 | * state - new state |
74b0247f | 1801 | * |
1da177e4 LT |
1802 | * Return value: |
1803 | * old state | |
1804 | ********************************************************************* */ | |
1805 | static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc, | |
1806 | sbmac_state_t state) | |
1807 | { | |
1808 | sbmac_state_t oldstate = sc->sbm_state; | |
74b0247f | 1809 | |
1da177e4 LT |
1810 | /* |
1811 | * If same as previous state, return | |
1812 | */ | |
74b0247f | 1813 | |
1da177e4 LT |
1814 | if (state == oldstate) { |
1815 | return oldstate; | |
1816 | } | |
74b0247f | 1817 | |
1da177e4 | 1818 | /* |
74b0247f | 1819 | * If new state is ON, turn channel on |
1da177e4 | 1820 | */ |
74b0247f | 1821 | |
1da177e4 LT |
1822 | if (state == sbmac_state_on) { |
1823 | sbmac_channel_start(sc); | |
1824 | } | |
1825 | else { | |
1826 | sbmac_channel_stop(sc); | |
1827 | } | |
74b0247f | 1828 | |
1da177e4 LT |
1829 | /* |
1830 | * Return previous state | |
1831 | */ | |
74b0247f | 1832 | |
1da177e4 LT |
1833 | return oldstate; |
1834 | } | |
1835 | ||
1836 | ||
1837 | /********************************************************************** | |
1838 | * SBMAC_PROMISCUOUS_MODE(sc,onoff) | |
74b0247f | 1839 | * |
1da177e4 | 1840 | * Turn on or off promiscuous mode |
74b0247f RB |
1841 | * |
1842 | * Input parameters: | |
1da177e4 LT |
1843 | * sc - softc |
1844 | * onoff - 1 to turn on, 0 to turn off | |
74b0247f | 1845 | * |
1da177e4 LT |
1846 | * Return value: |
1847 | * nothing | |
1848 | ********************************************************************* */ | |
1849 | ||
1850 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) | |
1851 | { | |
1852 | uint64_t reg; | |
74b0247f | 1853 | |
1da177e4 LT |
1854 | if (sc->sbm_state != sbmac_state_on) |
1855 | return; | |
74b0247f | 1856 | |
1da177e4 | 1857 | if (onoff) { |
2039973a | 1858 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1859 | reg |= M_MAC_ALLPKT_EN; |
2039973a | 1860 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1861 | } |
1da177e4 | 1862 | else { |
2039973a | 1863 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1864 | reg &= ~M_MAC_ALLPKT_EN; |
2039973a | 1865 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
1866 | } |
1867 | } | |
1868 | ||
1869 | /********************************************************************** | |
1870 | * SBMAC_SETIPHDR_OFFSET(sc,onoff) | |
74b0247f | 1871 | * |
1da177e4 | 1872 | * Set the iphdr offset as 15 assuming ethernet encapsulation |
74b0247f RB |
1873 | * |
1874 | * Input parameters: | |
1da177e4 | 1875 | * sc - softc |
74b0247f | 1876 | * |
1da177e4 LT |
1877 | * Return value: |
1878 | * nothing | |
1879 | ********************************************************************* */ | |
1880 | ||
1881 | static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) | |
1882 | { | |
1883 | uint64_t reg; | |
74b0247f | 1884 | |
1da177e4 | 1885 | /* Hard code the off set to 15 for now */ |
2039973a | 1886 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1887 | reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); |
2039973a | 1888 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1889 | |
f90fdc3c RB |
1890 | /* BCM1250 pass1 didn't have hardware checksum. Everything |
1891 | later does. */ | |
1892 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) { | |
1da177e4 | 1893 | sc->rx_hw_checksum = DISABLE; |
f90fdc3c RB |
1894 | } else { |
1895 | sc->rx_hw_checksum = ENABLE; | |
1da177e4 LT |
1896 | } |
1897 | } | |
1898 | ||
1899 | ||
1900 | /********************************************************************** | |
1901 | * SBMAC_ADDR2REG(ptr) | |
74b0247f | 1902 | * |
1da177e4 LT |
1903 | * Convert six bytes into the 64-bit register value that |
1904 | * we typically write into the SBMAC's address/mcast registers | |
74b0247f RB |
1905 | * |
1906 | * Input parameters: | |
1da177e4 | 1907 | * ptr - pointer to 6 bytes |
74b0247f | 1908 | * |
1da177e4 LT |
1909 | * Return value: |
1910 | * register value | |
1911 | ********************************************************************* */ | |
1912 | ||
1913 | static uint64_t sbmac_addr2reg(unsigned char *ptr) | |
1914 | { | |
1915 | uint64_t reg = 0; | |
74b0247f | 1916 | |
1da177e4 | 1917 | ptr += 6; |
74b0247f RB |
1918 | |
1919 | reg |= (uint64_t) *(--ptr); | |
1da177e4 | 1920 | reg <<= 8; |
74b0247f | 1921 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1922 | reg <<= 8; |
74b0247f | 1923 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1924 | reg <<= 8; |
74b0247f | 1925 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1926 | reg <<= 8; |
74b0247f | 1927 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1928 | reg <<= 8; |
74b0247f RB |
1929 | reg |= (uint64_t) *(--ptr); |
1930 | ||
1da177e4 LT |
1931 | return reg; |
1932 | } | |
1933 | ||
1934 | ||
1935 | /********************************************************************** | |
1936 | * SBMAC_SET_SPEED(s,speed) | |
74b0247f | 1937 | * |
1da177e4 LT |
1938 | * Configure LAN speed for the specified MAC. |
1939 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1940 | * |
1941 | * Input parameters: | |
1da177e4 LT |
1942 | * s - sbmac structure |
1943 | * speed - speed to set MAC to (see sbmac_speed_t enum) | |
74b0247f | 1944 | * |
1da177e4 LT |
1945 | * Return value: |
1946 | * 1 if successful | |
1947 | * 0 indicates invalid parameters | |
1948 | ********************************************************************* */ | |
1949 | ||
1950 | static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed) | |
1951 | { | |
1952 | uint64_t cfg; | |
1953 | uint64_t framecfg; | |
1954 | ||
1955 | /* | |
1956 | * Save new current values | |
1957 | */ | |
74b0247f | 1958 | |
1da177e4 | 1959 | s->sbm_speed = speed; |
74b0247f | 1960 | |
1da177e4 LT |
1961 | if (s->sbm_state == sbmac_state_on) |
1962 | return 0; /* save for next restart */ | |
1963 | ||
1964 | /* | |
74b0247f | 1965 | * Read current register values |
1da177e4 | 1966 | */ |
74b0247f | 1967 | |
2039973a RB |
1968 | cfg = __raw_readq(s->sbm_maccfg); |
1969 | framecfg = __raw_readq(s->sbm_framecfg); | |
74b0247f | 1970 | |
1da177e4 LT |
1971 | /* |
1972 | * Mask out the stuff we want to change | |
1973 | */ | |
74b0247f | 1974 | |
1da177e4 LT |
1975 | cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); |
1976 | framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | | |
1977 | M_MAC_SLOT_SIZE); | |
74b0247f | 1978 | |
1da177e4 LT |
1979 | /* |
1980 | * Now add in the new bits | |
1981 | */ | |
74b0247f | 1982 | |
1da177e4 LT |
1983 | switch (speed) { |
1984 | case sbmac_speed_10: | |
1985 | framecfg |= V_MAC_IFG_RX_10 | | |
1986 | V_MAC_IFG_TX_10 | | |
1987 | K_MAC_IFG_THRSH_10 | | |
1988 | V_MAC_SLOT_SIZE_10; | |
1989 | cfg |= V_MAC_SPEED_SEL_10MBPS; | |
1990 | break; | |
74b0247f | 1991 | |
1da177e4 LT |
1992 | case sbmac_speed_100: |
1993 | framecfg |= V_MAC_IFG_RX_100 | | |
1994 | V_MAC_IFG_TX_100 | | |
1995 | V_MAC_IFG_THRSH_100 | | |
1996 | V_MAC_SLOT_SIZE_100; | |
1997 | cfg |= V_MAC_SPEED_SEL_100MBPS ; | |
1998 | break; | |
74b0247f | 1999 | |
1da177e4 LT |
2000 | case sbmac_speed_1000: |
2001 | framecfg |= V_MAC_IFG_RX_1000 | | |
2002 | V_MAC_IFG_TX_1000 | | |
2003 | V_MAC_IFG_THRSH_1000 | | |
2004 | V_MAC_SLOT_SIZE_1000; | |
2005 | cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; | |
2006 | break; | |
74b0247f | 2007 | |
1da177e4 LT |
2008 | case sbmac_speed_auto: /* XXX not implemented */ |
2009 | /* fall through */ | |
2010 | default: | |
2011 | return 0; | |
2012 | } | |
74b0247f | 2013 | |
1da177e4 | 2014 | /* |
74b0247f | 2015 | * Send the bits back to the hardware |
1da177e4 | 2016 | */ |
74b0247f | 2017 | |
2039973a RB |
2018 | __raw_writeq(framecfg, s->sbm_framecfg); |
2019 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 2020 | |
1da177e4 LT |
2021 | return 1; |
2022 | } | |
2023 | ||
2024 | /********************************************************************** | |
2025 | * SBMAC_SET_DUPLEX(s,duplex,fc) | |
74b0247f | 2026 | * |
1da177e4 LT |
2027 | * Set Ethernet duplex and flow control options for this MAC |
2028 | * Warning: must be called when MAC is off! | |
74b0247f RB |
2029 | * |
2030 | * Input parameters: | |
1da177e4 LT |
2031 | * s - sbmac structure |
2032 | * duplex - duplex setting (see sbmac_duplex_t) | |
2033 | * fc - flow control setting (see sbmac_fc_t) | |
74b0247f | 2034 | * |
1da177e4 LT |
2035 | * Return value: |
2036 | * 1 if ok | |
2037 | * 0 if an invalid parameter combination was specified | |
2038 | ********************************************************************* */ | |
2039 | ||
2040 | static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc) | |
2041 | { | |
2042 | uint64_t cfg; | |
74b0247f | 2043 | |
1da177e4 LT |
2044 | /* |
2045 | * Save new current values | |
2046 | */ | |
74b0247f | 2047 | |
1da177e4 LT |
2048 | s->sbm_duplex = duplex; |
2049 | s->sbm_fc = fc; | |
74b0247f | 2050 | |
1da177e4 LT |
2051 | if (s->sbm_state == sbmac_state_on) |
2052 | return 0; /* save for next restart */ | |
74b0247f | 2053 | |
1da177e4 | 2054 | /* |
74b0247f | 2055 | * Read current register values |
1da177e4 | 2056 | */ |
74b0247f | 2057 | |
2039973a | 2058 | cfg = __raw_readq(s->sbm_maccfg); |
74b0247f | 2059 | |
1da177e4 LT |
2060 | /* |
2061 | * Mask off the stuff we're about to change | |
2062 | */ | |
74b0247f | 2063 | |
1da177e4 | 2064 | cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); |
74b0247f RB |
2065 | |
2066 | ||
1da177e4 LT |
2067 | switch (duplex) { |
2068 | case sbmac_duplex_half: | |
2069 | switch (fc) { | |
2070 | case sbmac_fc_disabled: | |
2071 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; | |
2072 | break; | |
74b0247f | 2073 | |
1da177e4 LT |
2074 | case sbmac_fc_collision: |
2075 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; | |
2076 | break; | |
74b0247f | 2077 | |
1da177e4 LT |
2078 | case sbmac_fc_carrier: |
2079 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; | |
2080 | break; | |
74b0247f | 2081 | |
1da177e4 | 2082 | case sbmac_fc_auto: /* XXX not implemented */ |
74b0247f | 2083 | /* fall through */ |
1da177e4 LT |
2084 | case sbmac_fc_frame: /* not valid in half duplex */ |
2085 | default: /* invalid selection */ | |
2086 | return 0; | |
2087 | } | |
2088 | break; | |
74b0247f | 2089 | |
1da177e4 LT |
2090 | case sbmac_duplex_full: |
2091 | switch (fc) { | |
2092 | case sbmac_fc_disabled: | |
2093 | cfg |= V_MAC_FC_CMD_DISABLED; | |
2094 | break; | |
74b0247f | 2095 | |
1da177e4 LT |
2096 | case sbmac_fc_frame: |
2097 | cfg |= V_MAC_FC_CMD_ENABLED; | |
2098 | break; | |
74b0247f | 2099 | |
1da177e4 LT |
2100 | case sbmac_fc_collision: /* not valid in full duplex */ |
2101 | case sbmac_fc_carrier: /* not valid in full duplex */ | |
2102 | case sbmac_fc_auto: /* XXX not implemented */ | |
74b0247f | 2103 | /* fall through */ |
1da177e4 LT |
2104 | default: |
2105 | return 0; | |
2106 | } | |
2107 | break; | |
2108 | case sbmac_duplex_auto: | |
2109 | /* XXX not implemented */ | |
2110 | break; | |
2111 | } | |
74b0247f | 2112 | |
1da177e4 | 2113 | /* |
74b0247f | 2114 | * Send the bits back to the hardware |
1da177e4 | 2115 | */ |
74b0247f | 2116 | |
2039973a | 2117 | __raw_writeq(cfg, s->sbm_maccfg); |
74b0247f | 2118 | |
1da177e4 LT |
2119 | return 1; |
2120 | } | |
2121 | ||
2122 | ||
2123 | ||
2124 | ||
2125 | /********************************************************************** | |
2126 | * SBMAC_INTR() | |
74b0247f | 2127 | * |
1da177e4 | 2128 | * Interrupt handler for MAC interrupts |
74b0247f RB |
2129 | * |
2130 | * Input parameters: | |
1da177e4 | 2131 | * MAC structure |
74b0247f | 2132 | * |
1da177e4 LT |
2133 | * Return value: |
2134 | * nothing | |
2135 | ********************************************************************* */ | |
7d12e780 | 2136 | static irqreturn_t sbmac_intr(int irq,void *dev_instance) |
1da177e4 LT |
2137 | { |
2138 | struct net_device *dev = (struct net_device *) dev_instance; | |
2139 | struct sbmac_softc *sc = netdev_priv(dev); | |
2140 | uint64_t isr; | |
2141 | int handled = 0; | |
2142 | ||
693aa947 MM |
2143 | /* |
2144 | * Read the ISR (this clears the bits in the real | |
2145 | * register, except for counter addr) | |
2146 | */ | |
74b0247f | 2147 | |
693aa947 | 2148 | isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; |
1da177e4 | 2149 | |
693aa947 MM |
2150 | if (isr == 0) |
2151 | return IRQ_RETVAL(0); | |
2152 | handled = 1; | |
74b0247f | 2153 | |
693aa947 MM |
2154 | /* |
2155 | * Transmits on channel 0 | |
2156 | */ | |
74b0247f | 2157 | |
bea3348e | 2158 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) |
693aa947 | 2159 | sbdma_tx_process(sc,&(sc->sbm_txdma), 0); |
74b0247f | 2160 | |
693aa947 | 2161 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { |
bea3348e | 2162 | if (netif_rx_schedule_prep(dev, &sc->napi)) { |
693aa947 | 2163 | __raw_writeq(0, sc->sbm_imr); |
bea3348e | 2164 | __netif_rx_schedule(dev, &sc->napi); |
693aa947 MM |
2165 | /* Depend on the exit from poll to reenable intr */ |
2166 | } | |
2167 | else { | |
2168 | /* may leave some packets behind */ | |
2169 | sbdma_rx_process(sc,&(sc->sbm_rxdma), | |
2170 | SBMAC_MAX_RXDESCR * 2, 0); | |
1da177e4 LT |
2171 | } |
2172 | } | |
2173 | return IRQ_RETVAL(handled); | |
2174 | } | |
2175 | ||
1da177e4 LT |
2176 | /********************************************************************** |
2177 | * SBMAC_START_TX(skb,dev) | |
74b0247f RB |
2178 | * |
2179 | * Start output on the specified interface. Basically, we | |
1da177e4 LT |
2180 | * queue as many buffers as we can until the ring fills up, or |
2181 | * we run off the end of the queue, whichever comes first. | |
74b0247f RB |
2182 | * |
2183 | * Input parameters: | |
2184 | * | |
2185 | * | |
1da177e4 LT |
2186 | * Return value: |
2187 | * nothing | |
2188 | ********************************************************************* */ | |
2189 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
2190 | { | |
2191 | struct sbmac_softc *sc = netdev_priv(dev); | |
74b0247f | 2192 | |
1da177e4 LT |
2193 | /* lock eth irq */ |
2194 | spin_lock_irq (&sc->sbm_lock); | |
74b0247f | 2195 | |
1da177e4 | 2196 | /* |
74b0247f | 2197 | * Put the buffer on the transmit ring. If we |
1da177e4 LT |
2198 | * don't have room, stop the queue. |
2199 | */ | |
74b0247f | 2200 | |
1da177e4 LT |
2201 | if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { |
2202 | /* XXX save skb that we could not send */ | |
2203 | netif_stop_queue(dev); | |
2204 | spin_unlock_irq(&sc->sbm_lock); | |
2205 | ||
2206 | return 1; | |
2207 | } | |
74b0247f | 2208 | |
1da177e4 | 2209 | dev->trans_start = jiffies; |
74b0247f | 2210 | |
1da177e4 | 2211 | spin_unlock_irq (&sc->sbm_lock); |
74b0247f | 2212 | |
1da177e4 LT |
2213 | return 0; |
2214 | } | |
2215 | ||
2216 | /********************************************************************** | |
2217 | * SBMAC_SETMULTI(sc) | |
74b0247f | 2218 | * |
1da177e4 LT |
2219 | * Reprogram the multicast table into the hardware, given |
2220 | * the list of multicasts associated with the interface | |
2221 | * structure. | |
74b0247f RB |
2222 | * |
2223 | * Input parameters: | |
1da177e4 | 2224 | * sc - softc |
74b0247f | 2225 | * |
1da177e4 LT |
2226 | * Return value: |
2227 | * nothing | |
2228 | ********************************************************************* */ | |
2229 | ||
2230 | static void sbmac_setmulti(struct sbmac_softc *sc) | |
2231 | { | |
2232 | uint64_t reg; | |
2039973a | 2233 | volatile void __iomem *port; |
1da177e4 LT |
2234 | int idx; |
2235 | struct dev_mc_list *mclist; | |
2236 | struct net_device *dev = sc->sbm_dev; | |
74b0247f RB |
2237 | |
2238 | /* | |
1da177e4 LT |
2239 | * Clear out entire multicast table. We do this by nuking |
2240 | * the entire hash table and all the direct matches except | |
74b0247f | 2241 | * the first one, which is used for our station address |
1da177e4 | 2242 | */ |
74b0247f | 2243 | |
1da177e4 LT |
2244 | for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { |
2245 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2246 | __raw_writeq(0, port); |
1da177e4 | 2247 | } |
74b0247f | 2248 | |
1da177e4 LT |
2249 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { |
2250 | port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2251 | __raw_writeq(0, port); |
1da177e4 | 2252 | } |
74b0247f | 2253 | |
1da177e4 LT |
2254 | /* |
2255 | * Clear the filter to say we don't want any multicasts. | |
2256 | */ | |
74b0247f | 2257 | |
2039973a | 2258 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2259 | reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2260 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 2261 | |
1da177e4 | 2262 | if (dev->flags & IFF_ALLMULTI) { |
74b0247f RB |
2263 | /* |
2264 | * Enable ALL multicasts. Do this by inverting the | |
2265 | * multicast enable bit. | |
1da177e4 | 2266 | */ |
2039973a | 2267 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2268 | reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2269 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2270 | return; |
2271 | } | |
1da177e4 | 2272 | |
74b0247f RB |
2273 | |
2274 | /* | |
1da177e4 LT |
2275 | * Progam new multicast entries. For now, only use the |
2276 | * perfect filter. In the future we'll need to use the | |
2277 | * hash filter if the perfect filter overflows | |
2278 | */ | |
74b0247f | 2279 | |
1da177e4 LT |
2280 | /* XXX only using perfect filter for now, need to use hash |
2281 | * XXX if the table overflows */ | |
74b0247f | 2282 | |
1da177e4 LT |
2283 | idx = 1; /* skip station address */ |
2284 | mclist = dev->mc_list; | |
2285 | while (mclist && (idx < MAC_ADDR_COUNT)) { | |
2286 | reg = sbmac_addr2reg(mclist->dmi_addr); | |
2287 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); | |
2039973a | 2288 | __raw_writeq(reg, port); |
1da177e4 LT |
2289 | idx++; |
2290 | mclist = mclist->next; | |
2291 | } | |
74b0247f RB |
2292 | |
2293 | /* | |
1da177e4 | 2294 | * Enable the "accept multicast bits" if we programmed at least one |
74b0247f | 2295 | * multicast. |
1da177e4 | 2296 | */ |
74b0247f | 2297 | |
1da177e4 | 2298 | if (idx > 1) { |
2039973a | 2299 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2300 | reg |= M_MAC_MCAST_EN; |
2039973a | 2301 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2302 | } |
2303 | } | |
2304 | ||
f90fdc3c | 2305 | #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) |
1da177e4 LT |
2306 | /********************************************************************** |
2307 | * SBMAC_PARSE_XDIGIT(str) | |
74b0247f | 2308 | * |
1da177e4 | 2309 | * Parse a hex digit, returning its value |
74b0247f RB |
2310 | * |
2311 | * Input parameters: | |
1da177e4 | 2312 | * str - character |
74b0247f | 2313 | * |
1da177e4 LT |
2314 | * Return value: |
2315 | * hex value, or -1 if invalid | |
2316 | ********************************************************************* */ | |
2317 | ||
2318 | static int sbmac_parse_xdigit(char str) | |
2319 | { | |
2320 | int digit; | |
74b0247f | 2321 | |
1da177e4 LT |
2322 | if ((str >= '0') && (str <= '9')) |
2323 | digit = str - '0'; | |
2324 | else if ((str >= 'a') && (str <= 'f')) | |
2325 | digit = str - 'a' + 10; | |
2326 | else if ((str >= 'A') && (str <= 'F')) | |
2327 | digit = str - 'A' + 10; | |
2328 | else | |
2329 | return -1; | |
74b0247f | 2330 | |
1da177e4 LT |
2331 | return digit; |
2332 | } | |
2333 | ||
2334 | /********************************************************************** | |
2335 | * SBMAC_PARSE_HWADDR(str,hwaddr) | |
74b0247f | 2336 | * |
1da177e4 LT |
2337 | * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte |
2338 | * Ethernet address. | |
74b0247f RB |
2339 | * |
2340 | * Input parameters: | |
1da177e4 LT |
2341 | * str - string |
2342 | * hwaddr - pointer to hardware address | |
74b0247f | 2343 | * |
1da177e4 LT |
2344 | * Return value: |
2345 | * 0 if ok, else -1 | |
2346 | ********************************************************************* */ | |
2347 | ||
2348 | static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr) | |
2349 | { | |
2350 | int digit1,digit2; | |
2351 | int idx = 6; | |
74b0247f | 2352 | |
1da177e4 LT |
2353 | while (*str && (idx > 0)) { |
2354 | digit1 = sbmac_parse_xdigit(*str); | |
2355 | if (digit1 < 0) | |
2356 | return -1; | |
2357 | str++; | |
2358 | if (!*str) | |
2359 | return -1; | |
74b0247f | 2360 | |
1da177e4 LT |
2361 | if ((*str == ':') || (*str == '-')) { |
2362 | digit2 = digit1; | |
2363 | digit1 = 0; | |
2364 | } | |
2365 | else { | |
2366 | digit2 = sbmac_parse_xdigit(*str); | |
2367 | if (digit2 < 0) | |
2368 | return -1; | |
2369 | str++; | |
2370 | } | |
74b0247f | 2371 | |
1da177e4 LT |
2372 | *hwaddr++ = (digit1 << 4) | digit2; |
2373 | idx--; | |
74b0247f | 2374 | |
1da177e4 LT |
2375 | if (*str == '-') |
2376 | str++; | |
2377 | if (*str == ':') | |
2378 | str++; | |
2379 | } | |
2380 | return 0; | |
2381 | } | |
2382 | #endif | |
2383 | ||
2384 | static int sb1250_change_mtu(struct net_device *_dev, int new_mtu) | |
2385 | { | |
2386 | if (new_mtu > ENET_PACKET_SIZE) | |
2387 | return -EINVAL; | |
2388 | _dev->mtu = new_mtu; | |
2389 | printk(KERN_INFO "changing the mtu to %d\n", new_mtu); | |
2390 | return 0; | |
2391 | } | |
2392 | ||
2393 | /********************************************************************** | |
2394 | * SBMAC_INIT(dev) | |
74b0247f | 2395 | * |
1da177e4 | 2396 | * Attach routine - init hardware and hook ourselves into linux |
74b0247f RB |
2397 | * |
2398 | * Input parameters: | |
1da177e4 | 2399 | * dev - net_device structure |
74b0247f | 2400 | * |
1da177e4 LT |
2401 | * Return value: |
2402 | * status | |
2403 | ********************************************************************* */ | |
2404 | ||
2405 | static int sbmac_init(struct net_device *dev, int idx) | |
2406 | { | |
2407 | struct sbmac_softc *sc; | |
2408 | unsigned char *eaddr; | |
2409 | uint64_t ea_reg; | |
2410 | int i; | |
2411 | int err; | |
74b0247f | 2412 | |
1da177e4 | 2413 | sc = netdev_priv(dev); |
74b0247f | 2414 | |
1da177e4 | 2415 | /* Determine controller base address */ |
74b0247f | 2416 | |
1da177e4 LT |
2417 | sc->sbm_base = IOADDR(dev->base_addr); |
2418 | sc->sbm_dev = dev; | |
2419 | sc->sbe_idx = idx; | |
74b0247f | 2420 | |
1da177e4 | 2421 | eaddr = sc->sbm_hwaddr; |
74b0247f RB |
2422 | |
2423 | /* | |
1da177e4 LT |
2424 | * Read the ethernet address. The firwmare left this programmed |
2425 | * for us in the ethernet address register for each mac. | |
2426 | */ | |
74b0247f | 2427 | |
2039973a RB |
2428 | ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR); |
2429 | __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR); | |
1da177e4 LT |
2430 | for (i = 0; i < 6; i++) { |
2431 | eaddr[i] = (uint8_t) (ea_reg & 0xFF); | |
2432 | ea_reg >>= 8; | |
2433 | } | |
74b0247f | 2434 | |
1da177e4 LT |
2435 | for (i = 0; i < 6; i++) { |
2436 | dev->dev_addr[i] = eaddr[i]; | |
2437 | } | |
74b0247f RB |
2438 | |
2439 | ||
1da177e4 | 2440 | /* |
74b0247f | 2441 | * Init packet size |
1da177e4 | 2442 | */ |
74b0247f | 2443 | |
1da177e4 LT |
2444 | sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN; |
2445 | ||
74b0247f | 2446 | /* |
1da177e4 LT |
2447 | * Initialize context (get pointers to registers and stuff), then |
2448 | * allocate the memory for the descriptor tables. | |
2449 | */ | |
74b0247f | 2450 | |
1da177e4 | 2451 | sbmac_initctx(sc); |
74b0247f | 2452 | |
1da177e4 LT |
2453 | /* |
2454 | * Set up Linux device callins | |
2455 | */ | |
74b0247f | 2456 | |
1da177e4 | 2457 | spin_lock_init(&(sc->sbm_lock)); |
74b0247f | 2458 | |
1da177e4 LT |
2459 | dev->open = sbmac_open; |
2460 | dev->hard_start_xmit = sbmac_start_tx; | |
2461 | dev->stop = sbmac_close; | |
2462 | dev->get_stats = sbmac_get_stats; | |
2463 | dev->set_multicast_list = sbmac_set_rx_mode; | |
2464 | dev->do_ioctl = sbmac_mii_ioctl; | |
2465 | dev->tx_timeout = sbmac_tx_timeout; | |
2466 | dev->watchdog_timeo = TX_TIMEOUT; | |
bea3348e SH |
2467 | |
2468 | netif_napi_add(dev, &sc->napi, sbmac_poll, 16); | |
1da177e4 LT |
2469 | |
2470 | dev->change_mtu = sb1250_change_mtu; | |
d6830018 DS |
2471 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2472 | dev->poll_controller = sbmac_netpoll; | |
2473 | #endif | |
1da177e4 LT |
2474 | |
2475 | /* This is needed for PASS2 for Rx H/W checksum feature */ | |
2476 | sbmac_set_iphdr_offset(sc); | |
2477 | ||
2478 | err = register_netdev(dev); | |
2479 | if (err) | |
2480 | goto out_uninit; | |
2481 | ||
f567ef93 | 2482 | if (sc->rx_hw_checksum == ENABLE) { |
1da177e4 LT |
2483 | printk(KERN_INFO "%s: enabling TCP rcv checksum\n", |
2484 | sc->sbm_dev->name); | |
2485 | } | |
2486 | ||
2487 | /* | |
2488 | * Display Ethernet address (this is called during the config | |
2489 | * process so we need to finish off the config message that | |
2490 | * was being displayed) | |
2491 | */ | |
2492 | printk(KERN_INFO | |
74b0247f | 2493 | "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n", |
1da177e4 LT |
2494 | dev->name, dev->base_addr, |
2495 | eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]); | |
74b0247f | 2496 | |
1da177e4 LT |
2497 | |
2498 | return 0; | |
2499 | ||
2500 | out_uninit: | |
2501 | sbmac_uninitctx(sc); | |
2502 | ||
2503 | return err; | |
2504 | } | |
2505 | ||
2506 | ||
2507 | static int sbmac_open(struct net_device *dev) | |
2508 | { | |
2509 | struct sbmac_softc *sc = netdev_priv(dev); | |
74b0247f | 2510 | |
1da177e4 LT |
2511 | if (debug > 1) { |
2512 | printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq); | |
2513 | } | |
74b0247f RB |
2514 | |
2515 | /* | |
1da177e4 LT |
2516 | * map/route interrupt (clear status first, in case something |
2517 | * weird is pending; we haven't initialized the mac registers | |
2518 | * yet) | |
2519 | */ | |
2520 | ||
2039973a | 2521 | __raw_readq(sc->sbm_isr); |
1fb9df5d | 2522 | if (request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev)) |
1da177e4 LT |
2523 | return -EBUSY; |
2524 | ||
59b81827 RB |
2525 | /* |
2526 | * Probe phy address | |
2527 | */ | |
2528 | ||
2529 | if(sbmac_mii_probe(dev) == -1) { | |
2530 | printk("%s: failed to probe PHY.\n", dev->name); | |
2531 | return -EINVAL; | |
2532 | } | |
2533 | ||
bea3348e SH |
2534 | napi_enable(&sc->napi); |
2535 | ||
1da177e4 | 2536 | /* |
74b0247f | 2537 | * Configure default speed |
1da177e4 LT |
2538 | */ |
2539 | ||
2540 | sbmac_mii_poll(sc,noisy_mii); | |
74b0247f | 2541 | |
1da177e4 LT |
2542 | /* |
2543 | * Turn on the channel | |
2544 | */ | |
2545 | ||
2546 | sbmac_set_channel_state(sc,sbmac_state_on); | |
74b0247f | 2547 | |
1da177e4 LT |
2548 | /* |
2549 | * XXX Station address is in dev->dev_addr | |
2550 | */ | |
74b0247f | 2551 | |
1da177e4 | 2552 | if (dev->if_port == 0) |
74b0247f RB |
2553 | dev->if_port = 0; |
2554 | ||
1da177e4 | 2555 | netif_start_queue(dev); |
74b0247f | 2556 | |
1da177e4 | 2557 | sbmac_set_rx_mode(dev); |
74b0247f | 2558 | |
1da177e4 LT |
2559 | /* Set the timer to check for link beat. */ |
2560 | init_timer(&sc->sbm_timer); | |
2561 | sc->sbm_timer.expires = jiffies + 2 * HZ/100; | |
2562 | sc->sbm_timer.data = (unsigned long)dev; | |
2563 | sc->sbm_timer.function = &sbmac_timer; | |
2564 | add_timer(&sc->sbm_timer); | |
74b0247f | 2565 | |
1da177e4 LT |
2566 | return 0; |
2567 | } | |
2568 | ||
59b81827 RB |
2569 | static int sbmac_mii_probe(struct net_device *dev) |
2570 | { | |
2571 | int i; | |
2572 | struct sbmac_softc *s = netdev_priv(dev); | |
2573 | u16 bmsr, id1, id2; | |
2574 | u32 vendor, device; | |
2575 | ||
2576 | for (i=1; i<31; i++) { | |
2577 | bmsr = sbmac_mii_read(s, i, MII_BMSR); | |
2578 | if (bmsr != 0) { | |
2579 | s->sbm_phys[0] = i; | |
2580 | id1 = sbmac_mii_read(s, i, MII_PHYIDR1); | |
2581 | id2 = sbmac_mii_read(s, i, MII_PHYIDR2); | |
2582 | vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f); | |
2583 | device = (id2 >> 4) & 0x3f; | |
2584 | ||
2585 | printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n", | |
2586 | dev->name, i, vendor, device); | |
2587 | return i; | |
2588 | } | |
2589 | } | |
2590 | return -1; | |
2591 | } | |
1da177e4 LT |
2592 | |
2593 | ||
2594 | static int sbmac_mii_poll(struct sbmac_softc *s,int noisy) | |
2595 | { | |
2596 | int bmsr,bmcr,k1stsr,anlpar; | |
2597 | int chg; | |
2598 | char buffer[100]; | |
2599 | char *p = buffer; | |
2600 | ||
2601 | /* Read the mode status and mode control registers. */ | |
2602 | bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR); | |
2603 | bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR); | |
2604 | ||
2605 | /* get the link partner status */ | |
2606 | anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR); | |
2607 | ||
2608 | /* if supported, read the 1000baseT register */ | |
2609 | if (bmsr & BMSR_1000BT_XSR) { | |
2610 | k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR); | |
2611 | } | |
2612 | else { | |
2613 | k1stsr = 0; | |
2614 | } | |
2615 | ||
2616 | chg = 0; | |
2617 | ||
2618 | if ((bmsr & BMSR_LINKSTAT) == 0) { | |
2619 | /* | |
2620 | * If link status is down, clear out old info so that when | |
2621 | * it comes back up it will force us to reconfigure speed | |
2622 | */ | |
2623 | s->sbm_phy_oldbmsr = 0; | |
2624 | s->sbm_phy_oldanlpar = 0; | |
2625 | s->sbm_phy_oldk1stsr = 0; | |
2626 | return 0; | |
2627 | } | |
2628 | ||
2629 | if ((s->sbm_phy_oldbmsr != bmsr) || | |
2630 | (s->sbm_phy_oldanlpar != anlpar) || | |
2631 | (s->sbm_phy_oldk1stsr != k1stsr)) { | |
2632 | if (debug > 1) { | |
2633 | printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x k1stsr:%x/%x\n", | |
2634 | s->sbm_dev->name, | |
2635 | s->sbm_phy_oldbmsr,bmsr, | |
2636 | s->sbm_phy_oldanlpar,anlpar, | |
2637 | s->sbm_phy_oldk1stsr,k1stsr); | |
2638 | } | |
2639 | s->sbm_phy_oldbmsr = bmsr; | |
2640 | s->sbm_phy_oldanlpar = anlpar; | |
2641 | s->sbm_phy_oldk1stsr = k1stsr; | |
2642 | chg = 1; | |
2643 | } | |
2644 | ||
2645 | if (chg == 0) | |
2646 | return 0; | |
2647 | ||
2648 | p += sprintf(p,"Link speed: "); | |
2649 | ||
2650 | if (k1stsr & K1STSR_LP1KFD) { | |
2651 | s->sbm_speed = sbmac_speed_1000; | |
2652 | s->sbm_duplex = sbmac_duplex_full; | |
2653 | s->sbm_fc = sbmac_fc_frame; | |
2654 | p += sprintf(p,"1000BaseT FDX"); | |
2655 | } | |
2656 | else if (k1stsr & K1STSR_LP1KHD) { | |
2657 | s->sbm_speed = sbmac_speed_1000; | |
2658 | s->sbm_duplex = sbmac_duplex_half; | |
2659 | s->sbm_fc = sbmac_fc_disabled; | |
2660 | p += sprintf(p,"1000BaseT HDX"); | |
2661 | } | |
2662 | else if (anlpar & ANLPAR_TXFD) { | |
2663 | s->sbm_speed = sbmac_speed_100; | |
2664 | s->sbm_duplex = sbmac_duplex_full; | |
2665 | s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled; | |
2666 | p += sprintf(p,"100BaseT FDX"); | |
2667 | } | |
2668 | else if (anlpar & ANLPAR_TXHD) { | |
2669 | s->sbm_speed = sbmac_speed_100; | |
2670 | s->sbm_duplex = sbmac_duplex_half; | |
2671 | s->sbm_fc = sbmac_fc_disabled; | |
2672 | p += sprintf(p,"100BaseT HDX"); | |
2673 | } | |
2674 | else if (anlpar & ANLPAR_10FD) { | |
2675 | s->sbm_speed = sbmac_speed_10; | |
2676 | s->sbm_duplex = sbmac_duplex_full; | |
2677 | s->sbm_fc = sbmac_fc_frame; | |
2678 | p += sprintf(p,"10BaseT FDX"); | |
2679 | } | |
2680 | else if (anlpar & ANLPAR_10HD) { | |
2681 | s->sbm_speed = sbmac_speed_10; | |
2682 | s->sbm_duplex = sbmac_duplex_half; | |
2683 | s->sbm_fc = sbmac_fc_collision; | |
2684 | p += sprintf(p,"10BaseT HDX"); | |
2685 | } | |
2686 | else { | |
2687 | p += sprintf(p,"Unknown"); | |
2688 | } | |
2689 | ||
2690 | if (noisy) { | |
2691 | printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer); | |
2692 | } | |
2693 | ||
2694 | return 1; | |
2695 | } | |
2696 | ||
2697 | ||
2698 | static void sbmac_timer(unsigned long data) | |
2699 | { | |
2700 | struct net_device *dev = (struct net_device *)data; | |
2701 | struct sbmac_softc *sc = netdev_priv(dev); | |
2702 | int next_tick = HZ; | |
2703 | int mii_status; | |
2704 | ||
2705 | spin_lock_irq (&sc->sbm_lock); | |
74b0247f | 2706 | |
1da177e4 LT |
2707 | /* make IFF_RUNNING follow the MII status bit "Link established" */ |
2708 | mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR); | |
74b0247f | 2709 | |
1da177e4 LT |
2710 | if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) { |
2711 | sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT; | |
2712 | if (mii_status & BMSR_LINKSTAT) { | |
2713 | netif_carrier_on(dev); | |
2714 | } | |
2715 | else { | |
74b0247f | 2716 | netif_carrier_off(dev); |
1da177e4 LT |
2717 | } |
2718 | } | |
74b0247f | 2719 | |
1da177e4 LT |
2720 | /* |
2721 | * Poll the PHY to see what speed we should be running at | |
2722 | */ | |
2723 | ||
2724 | if (sbmac_mii_poll(sc,noisy_mii)) { | |
2725 | if (sc->sbm_state != sbmac_state_off) { | |
2726 | /* | |
2727 | * something changed, restart the channel | |
2728 | */ | |
2729 | if (debug > 1) { | |
2730 | printk("%s: restarting channel because speed changed\n", | |
2731 | sc->sbm_dev->name); | |
2732 | } | |
2733 | sbmac_channel_stop(sc); | |
2734 | sbmac_channel_start(sc); | |
2735 | } | |
2736 | } | |
74b0247f | 2737 | |
1da177e4 | 2738 | spin_unlock_irq (&sc->sbm_lock); |
74b0247f | 2739 | |
1da177e4 LT |
2740 | sc->sbm_timer.expires = jiffies + next_tick; |
2741 | add_timer(&sc->sbm_timer); | |
2742 | } | |
2743 | ||
2744 | ||
2745 | static void sbmac_tx_timeout (struct net_device *dev) | |
2746 | { | |
2747 | struct sbmac_softc *sc = netdev_priv(dev); | |
74b0247f | 2748 | |
1da177e4 | 2749 | spin_lock_irq (&sc->sbm_lock); |
74b0247f RB |
2750 | |
2751 | ||
1da177e4 LT |
2752 | dev->trans_start = jiffies; |
2753 | sc->sbm_stats.tx_errors++; | |
74b0247f | 2754 | |
1da177e4 LT |
2755 | spin_unlock_irq (&sc->sbm_lock); |
2756 | ||
2757 | printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); | |
2758 | } | |
2759 | ||
2760 | ||
2761 | ||
2762 | ||
2763 | static struct net_device_stats *sbmac_get_stats(struct net_device *dev) | |
2764 | { | |
2765 | struct sbmac_softc *sc = netdev_priv(dev); | |
2766 | unsigned long flags; | |
74b0247f | 2767 | |
1da177e4 | 2768 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2769 | |
1da177e4 | 2770 | /* XXX update other stats here */ |
74b0247f | 2771 | |
1da177e4 | 2772 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
74b0247f | 2773 | |
1da177e4 LT |
2774 | return &sc->sbm_stats; |
2775 | } | |
2776 | ||
2777 | ||
2778 | ||
2779 | static void sbmac_set_rx_mode(struct net_device *dev) | |
2780 | { | |
2781 | unsigned long flags; | |
1da177e4 LT |
2782 | struct sbmac_softc *sc = netdev_priv(dev); |
2783 | ||
2784 | spin_lock_irqsave(&sc->sbm_lock, flags); | |
2785 | if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { | |
2786 | /* | |
2787 | * Promiscuous changed. | |
2788 | */ | |
74b0247f RB |
2789 | |
2790 | if (dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2791 | sbmac_promiscuous_mode(sc,1); |
2792 | } | |
2793 | else { | |
1da177e4 LT |
2794 | sbmac_promiscuous_mode(sc,0); |
2795 | } | |
2796 | } | |
2797 | spin_unlock_irqrestore(&sc->sbm_lock, flags); | |
74b0247f | 2798 | |
1da177e4 LT |
2799 | /* |
2800 | * Program the multicasts. Do this every time. | |
2801 | */ | |
74b0247f | 2802 | |
1da177e4 | 2803 | sbmac_setmulti(sc); |
74b0247f | 2804 | |
1da177e4 LT |
2805 | } |
2806 | ||
2807 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2808 | { | |
2809 | struct sbmac_softc *sc = netdev_priv(dev); | |
2810 | u16 *data = (u16 *)&rq->ifr_ifru; | |
2811 | unsigned long flags; | |
2812 | int retval; | |
74b0247f | 2813 | |
1da177e4 LT |
2814 | spin_lock_irqsave(&sc->sbm_lock, flags); |
2815 | retval = 0; | |
74b0247f | 2816 | |
1da177e4 LT |
2817 | switch(cmd) { |
2818 | case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ | |
2819 | data[0] = sc->sbm_phys[0] & 0x1f; | |
2820 | /* Fall Through */ | |
2821 | case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ | |
2822 | data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f); | |
2823 | break; | |
2824 | case SIOCDEVPRIVATE+2: /* Write the specified MII register */ | |
2825 | if (!capable(CAP_NET_ADMIN)) { | |
2826 | retval = -EPERM; | |
2827 | break; | |
2828 | } | |
2829 | if (debug > 1) { | |
2830 | printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name, | |
2831 | data[0],data[1],data[2]); | |
2832 | } | |
2833 | sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]); | |
2834 | break; | |
2835 | default: | |
2836 | retval = -EOPNOTSUPP; | |
2837 | } | |
74b0247f | 2838 | |
1da177e4 LT |
2839 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
2840 | return retval; | |
2841 | } | |
2842 | ||
2843 | static int sbmac_close(struct net_device *dev) | |
2844 | { | |
2845 | struct sbmac_softc *sc = netdev_priv(dev); | |
2846 | unsigned long flags; | |
2847 | int irq; | |
2848 | ||
bea3348e SH |
2849 | napi_disable(&sc->napi); |
2850 | ||
1da177e4 LT |
2851 | sbmac_set_channel_state(sc,sbmac_state_off); |
2852 | ||
2853 | del_timer_sync(&sc->sbm_timer); | |
2854 | ||
2855 | spin_lock_irqsave(&sc->sbm_lock, flags); | |
2856 | ||
2857 | netif_stop_queue(dev); | |
2858 | ||
2859 | if (debug > 1) { | |
2860 | printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name); | |
2861 | } | |
2862 | ||
2863 | spin_unlock_irqrestore(&sc->sbm_lock, flags); | |
2864 | ||
2865 | irq = dev->irq; | |
2866 | synchronize_irq(irq); | |
2867 | free_irq(irq, dev); | |
2868 | ||
2869 | sbdma_emptyring(&(sc->sbm_txdma)); | |
2870 | sbdma_emptyring(&(sc->sbm_rxdma)); | |
74b0247f | 2871 | |
1da177e4 LT |
2872 | return 0; |
2873 | } | |
2874 | ||
bea3348e | 2875 | static int sbmac_poll(struct napi_struct *napi, int budget) |
693aa947 | 2876 | { |
bea3348e SH |
2877 | struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi); |
2878 | struct net_device *dev = sc->sbm_dev; | |
693aa947 | 2879 | int work_done; |
1da177e4 | 2880 | |
bea3348e | 2881 | work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1); |
693aa947 MM |
2882 | sbdma_tx_process(sc, &(sc->sbm_txdma), 1); |
2883 | ||
bea3348e SH |
2884 | if (work_done < budget) { |
2885 | netif_rx_complete(dev, napi); | |
693aa947 MM |
2886 | |
2887 | #ifdef CONFIG_SBMAC_COALESCE | |
2888 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
2889 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
2890 | sc->sbm_imr); | |
2891 | #else | |
2892 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | | |
2893 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); | |
2894 | #endif | |
2895 | } | |
2896 | ||
bea3348e | 2897 | return work_done; |
693aa947 | 2898 | } |
1da177e4 | 2899 | |
f90fdc3c | 2900 | #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) |
1da177e4 LT |
2901 | static void |
2902 | sbmac_setup_hwaddr(int chan,char *addr) | |
2903 | { | |
2904 | uint8_t eaddr[6]; | |
2905 | uint64_t val; | |
2039973a | 2906 | unsigned long port; |
1da177e4 LT |
2907 | |
2908 | port = A_MAC_CHANNEL_BASE(chan); | |
2909 | sbmac_parse_hwaddr(addr,eaddr); | |
2910 | val = sbmac_addr2reg(eaddr); | |
2039973a RB |
2911 | __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR)); |
2912 | val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); | |
1da177e4 LT |
2913 | } |
2914 | #endif | |
2915 | ||
2916 | static struct net_device *dev_sbmac[MAX_UNITS]; | |
2917 | ||
2918 | static int __init | |
2919 | sbmac_init_module(void) | |
2920 | { | |
2921 | int idx; | |
2922 | struct net_device *dev; | |
2039973a | 2923 | unsigned long port; |
1da177e4 | 2924 | int chip_max_units; |
74b0247f | 2925 | |
f90fdc3c | 2926 | /* Set the number of available units based on the SOC type. */ |
1da177e4 LT |
2927 | switch (soc_type) { |
2928 | case K_SYS_SOC_TYPE_BCM1250: | |
2929 | case K_SYS_SOC_TYPE_BCM1250_ALT: | |
2930 | chip_max_units = 3; | |
2931 | break; | |
2932 | case K_SYS_SOC_TYPE_BCM1120: | |
2933 | case K_SYS_SOC_TYPE_BCM1125: | |
2934 | case K_SYS_SOC_TYPE_BCM1125H: | |
2935 | case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ | |
2936 | chip_max_units = 2; | |
2937 | break; | |
f90fdc3c RB |
2938 | case K_SYS_SOC_TYPE_BCM1x55: |
2939 | case K_SYS_SOC_TYPE_BCM1x80: | |
2940 | chip_max_units = 4; | |
2941 | break; | |
1da177e4 LT |
2942 | default: |
2943 | chip_max_units = 0; | |
2944 | break; | |
2945 | } | |
2946 | if (chip_max_units > MAX_UNITS) | |
2947 | chip_max_units = MAX_UNITS; | |
2948 | ||
f90fdc3c RB |
2949 | /* |
2950 | * For bringup when not using the firmware, we can pre-fill | |
2951 | * the MAC addresses using the environment variables | |
2952 | * specified in this file (or maybe from the config file?) | |
2953 | */ | |
2954 | #ifdef SBMAC_ETH0_HWADDR | |
2955 | if (chip_max_units > 0) | |
2956 | sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR); | |
2957 | #endif | |
2958 | #ifdef SBMAC_ETH1_HWADDR | |
2959 | if (chip_max_units > 1) | |
2960 | sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR); | |
2961 | #endif | |
2962 | #ifdef SBMAC_ETH2_HWADDR | |
2963 | if (chip_max_units > 2) | |
2964 | sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR); | |
2965 | #endif | |
2966 | #ifdef SBMAC_ETH3_HWADDR | |
2967 | if (chip_max_units > 3) | |
2968 | sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR); | |
2969 | #endif | |
2970 | ||
2971 | /* | |
2972 | * Walk through the Ethernet controllers and find | |
2973 | * those who have their MAC addresses set. | |
2974 | */ | |
1da177e4 LT |
2975 | for (idx = 0; idx < chip_max_units; idx++) { |
2976 | ||
2977 | /* | |
2978 | * This is the base address of the MAC. | |
2979 | */ | |
2980 | ||
2981 | port = A_MAC_CHANNEL_BASE(idx); | |
2982 | ||
74b0247f | 2983 | /* |
1da177e4 | 2984 | * The R_MAC_ETHERNET_ADDR register will be set to some nonzero |
693aa947 | 2985 | * value for us by the firmware if we are going to use this MAC. |
1da177e4 LT |
2986 | * If we find a zero, skip this MAC. |
2987 | */ | |
2988 | ||
2039973a | 2989 | sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR)); |
1da177e4 LT |
2990 | if (sbmac_orig_hwaddr[idx] == 0) { |
2991 | printk(KERN_DEBUG "sbmac: not configuring MAC at " | |
2992 | "%lx\n", port); | |
2993 | continue; | |
2994 | } | |
2995 | ||
2996 | /* | |
2997 | * Okay, cool. Initialize this MAC. | |
2998 | */ | |
2999 | ||
3000 | dev = alloc_etherdev(sizeof(struct sbmac_softc)); | |
74b0247f | 3001 | if (!dev) |
089fff2a | 3002 | return -ENOMEM; |
1da177e4 LT |
3003 | |
3004 | printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); | |
3005 | ||
f90fdc3c | 3006 | dev->irq = UNIT_INT(idx); |
1da177e4 LT |
3007 | dev->base_addr = port; |
3008 | dev->mem_end = 0; | |
3009 | if (sbmac_init(dev, idx)) { | |
3010 | port = A_MAC_CHANNEL_BASE(idx); | |
2039973a | 3011 | __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR)); |
1da177e4 LT |
3012 | free_netdev(dev); |
3013 | continue; | |
3014 | } | |
3015 | dev_sbmac[idx] = dev; | |
3016 | } | |
3017 | return 0; | |
3018 | } | |
3019 | ||
3020 | ||
3021 | static void __exit | |
3022 | sbmac_cleanup_module(void) | |
3023 | { | |
3024 | struct net_device *dev; | |
3025 | int idx; | |
3026 | ||
3027 | for (idx = 0; idx < MAX_UNITS; idx++) { | |
3028 | struct sbmac_softc *sc; | |
3029 | dev = dev_sbmac[idx]; | |
3030 | if (!dev) | |
3031 | continue; | |
3032 | ||
3033 | sc = netdev_priv(dev); | |
3034 | unregister_netdev(dev); | |
3035 | sbmac_uninitctx(sc); | |
3036 | free_netdev(dev); | |
3037 | } | |
3038 | } | |
3039 | ||
3040 | module_init(sbmac_init_module); | |
3041 | module_exit(sbmac_cleanup_module); |