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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 BH |
23 | #include "net_driver.h" |
24 | #include "gmii.h" | |
25 | #include "ethtool.h" | |
26 | #include "tx.h" | |
27 | #include "rx.h" | |
28 | #include "efx.h" | |
29 | #include "mdio_10g.h" | |
30 | #include "falcon.h" | |
8ceee660 BH |
31 | #include "mac.h" |
32 | ||
33 | #define EFX_MAX_MTU (9 * 1024) | |
34 | ||
35 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
36 | * a work item is pushed onto this work queue to retry the allocation later, | |
37 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
38 | * workqueue, there is nothing to be gained in making it per NIC | |
39 | */ | |
40 | static struct workqueue_struct *refill_workqueue; | |
41 | ||
1ab00629 SH |
42 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
43 | * queued onto this work queue. This is not a per-nic work queue, because | |
44 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
45 | */ | |
46 | static struct workqueue_struct *reset_workqueue; | |
47 | ||
8ceee660 BH |
48 | /************************************************************************** |
49 | * | |
50 | * Configurable values | |
51 | * | |
52 | *************************************************************************/ | |
53 | ||
54 | /* | |
55 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
56 | * | |
57 | * This sets the default for new devices. It can be controlled later | |
58 | * using ethtool. | |
59 | */ | |
dc8cfa55 | 60 | static int lro = true; |
8ceee660 BH |
61 | module_param(lro, int, 0644); |
62 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
63 | ||
64 | /* | |
65 | * Use separate channels for TX and RX events | |
66 | * | |
28b581ab NT |
67 | * Set this to 1 to use separate channels for TX and RX. It allows us |
68 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 69 | * |
28b581ab | 70 | * This is only used in MSI-X interrupt mode |
8ceee660 | 71 | */ |
28b581ab NT |
72 | static unsigned int separate_tx_channels; |
73 | module_param(separate_tx_channels, uint, 0644); | |
74 | MODULE_PARM_DESC(separate_tx_channels, | |
75 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
76 | |
77 | /* This is the weight assigned to each of the (per-channel) virtual | |
78 | * NAPI devices. | |
79 | */ | |
80 | static int napi_weight = 64; | |
81 | ||
82 | /* This is the time (in jiffies) between invocations of the hardware | |
83 | * monitor, which checks for known hardware bugs and resets the | |
84 | * hardware and driver as necessary. | |
85 | */ | |
86 | unsigned int efx_monitor_interval = 1 * HZ; | |
87 | ||
8ceee660 BH |
88 | /* This controls whether or not the driver will initialise devices |
89 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
90 | * such devices will be initialised with a random locally-generated | |
91 | * MAC address. This allows for loading the sfc_mtd driver to | |
92 | * reprogram the flash, even if the flash contents (including the MAC | |
93 | * address) have previously been erased. | |
94 | */ | |
95 | static unsigned int allow_bad_hwaddr; | |
96 | ||
97 | /* Initial interrupt moderation settings. They can be modified after | |
98 | * module load with ethtool. | |
99 | * | |
100 | * The default for RX should strike a balance between increasing the | |
101 | * round-trip latency and reducing overhead. | |
102 | */ | |
103 | static unsigned int rx_irq_mod_usec = 60; | |
104 | ||
105 | /* Initial interrupt moderation settings. They can be modified after | |
106 | * module load with ethtool. | |
107 | * | |
108 | * This default is chosen to ensure that a 10G link does not go idle | |
109 | * while a TX queue is stopped after it has become full. A queue is | |
110 | * restarted when it drops below half full. The time this takes (assuming | |
111 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
112 | * 512 / 3 * 1.2 = 205 usec. | |
113 | */ | |
114 | static unsigned int tx_irq_mod_usec = 150; | |
115 | ||
116 | /* This is the first interrupt mode to try out of: | |
117 | * 0 => MSI-X | |
118 | * 1 => MSI | |
119 | * 2 => legacy | |
120 | */ | |
121 | static unsigned int interrupt_mode; | |
122 | ||
123 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
124 | * i.e. the number of CPUs among which we may distribute simultaneous | |
125 | * interrupt handling. | |
126 | * | |
127 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
128 | * The default (0) means to assign an interrupt to each package (level II cache) | |
129 | */ | |
130 | static unsigned int rss_cpus; | |
131 | module_param(rss_cpus, uint, 0444); | |
132 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
133 | ||
84ae48fe BH |
134 | static int phy_flash_cfg; |
135 | module_param(phy_flash_cfg, int, 0644); | |
136 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
137 | ||
8ceee660 BH |
138 | /************************************************************************** |
139 | * | |
140 | * Utility functions and prototypes | |
141 | * | |
142 | *************************************************************************/ | |
143 | static void efx_remove_channel(struct efx_channel *channel); | |
144 | static void efx_remove_port(struct efx_nic *efx); | |
145 | static void efx_fini_napi(struct efx_nic *efx); | |
146 | static void efx_fini_channels(struct efx_nic *efx); | |
147 | ||
148 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
149 | do { \ | |
3c78708f | 150 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
151 | ASSERT_RTNL(); \ |
152 | } while (0) | |
153 | ||
154 | /************************************************************************** | |
155 | * | |
156 | * Event queue processing | |
157 | * | |
158 | *************************************************************************/ | |
159 | ||
160 | /* Process channel's event queue | |
161 | * | |
162 | * This function is responsible for processing the event queue of a | |
163 | * single channel. The caller must guarantee that this function will | |
164 | * never be concurrently called more than once on the same channel, | |
165 | * though different channels may be being processed concurrently. | |
166 | */ | |
4d566063 | 167 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 168 | { |
42cbe2d7 BH |
169 | struct efx_nic *efx = channel->efx; |
170 | int rx_packets; | |
8ceee660 | 171 | |
42cbe2d7 | 172 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 173 | !channel->enabled)) |
42cbe2d7 | 174 | return 0; |
8ceee660 | 175 | |
42cbe2d7 BH |
176 | rx_packets = falcon_process_eventq(channel, rx_quota); |
177 | if (rx_packets == 0) | |
178 | return 0; | |
8ceee660 BH |
179 | |
180 | /* Deliver last RX packet. */ | |
181 | if (channel->rx_pkt) { | |
182 | __efx_rx_packet(channel, channel->rx_pkt, | |
183 | channel->rx_pkt_csummed); | |
184 | channel->rx_pkt = NULL; | |
185 | } | |
186 | ||
187 | efx_flush_lro(channel); | |
188 | efx_rx_strategy(channel); | |
189 | ||
42cbe2d7 | 190 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 191 | |
42cbe2d7 | 192 | return rx_packets; |
8ceee660 BH |
193 | } |
194 | ||
195 | /* Mark channel as finished processing | |
196 | * | |
197 | * Note that since we will not receive further interrupts for this | |
198 | * channel before we finish processing and call the eventq_read_ack() | |
199 | * method, there is no need to use the interrupt hold-off timers. | |
200 | */ | |
201 | static inline void efx_channel_processed(struct efx_channel *channel) | |
202 | { | |
5b9e207c BH |
203 | /* The interrupt handler for this channel may set work_pending |
204 | * as soon as we acknowledge the events we've seen. Make sure | |
205 | * it's cleared before then. */ | |
dc8cfa55 | 206 | channel->work_pending = false; |
5b9e207c BH |
207 | smp_wmb(); |
208 | ||
8ceee660 BH |
209 | falcon_eventq_read_ack(channel); |
210 | } | |
211 | ||
212 | /* NAPI poll handler | |
213 | * | |
214 | * NAPI guarantees serialisation of polls of the same device, which | |
215 | * provides the guarantee required by efx_process_channel(). | |
216 | */ | |
217 | static int efx_poll(struct napi_struct *napi, int budget) | |
218 | { | |
219 | struct efx_channel *channel = | |
220 | container_of(napi, struct efx_channel, napi_str); | |
221 | struct net_device *napi_dev = channel->napi_dev; | |
8ceee660 BH |
222 | int rx_packets; |
223 | ||
224 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
225 | channel->channel, raw_smp_processor_id()); | |
226 | ||
42cbe2d7 | 227 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
228 | |
229 | if (rx_packets < budget) { | |
230 | /* There is no race here; although napi_disable() will | |
231 | * only wait for netif_rx_complete(), this isn't a problem | |
232 | * since efx_channel_processed() will have no effect if | |
233 | * interrupts have already been disabled. | |
234 | */ | |
235 | netif_rx_complete(napi_dev, napi); | |
236 | efx_channel_processed(channel); | |
237 | } | |
238 | ||
239 | return rx_packets; | |
240 | } | |
241 | ||
242 | /* Process the eventq of the specified channel immediately on this CPU | |
243 | * | |
244 | * Disable hardware generated interrupts, wait for any existing | |
245 | * processing to finish, then directly poll (and ack ) the eventq. | |
246 | * Finally reenable NAPI and interrupts. | |
247 | * | |
248 | * Since we are touching interrupts the caller should hold the suspend lock | |
249 | */ | |
250 | void efx_process_channel_now(struct efx_channel *channel) | |
251 | { | |
252 | struct efx_nic *efx = channel->efx; | |
253 | ||
254 | BUG_ON(!channel->used_flags); | |
255 | BUG_ON(!channel->enabled); | |
256 | ||
257 | /* Disable interrupts and wait for ISRs to complete */ | |
258 | falcon_disable_interrupts(efx); | |
259 | if (efx->legacy_irq) | |
260 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 261 | if (channel->irq) |
8ceee660 BH |
262 | synchronize_irq(channel->irq); |
263 | ||
264 | /* Wait for any NAPI processing to complete */ | |
265 | napi_disable(&channel->napi_str); | |
266 | ||
267 | /* Poll the channel */ | |
91ad757c | 268 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
269 | |
270 | /* Ack the eventq. This may cause an interrupt to be generated | |
271 | * when they are reenabled */ | |
272 | efx_channel_processed(channel); | |
273 | ||
274 | napi_enable(&channel->napi_str); | |
275 | falcon_enable_interrupts(efx); | |
276 | } | |
277 | ||
278 | /* Create event queue | |
279 | * Event queue memory allocations are done only once. If the channel | |
280 | * is reset, the memory buffer will be reused; this guards against | |
281 | * errors during channel reset and also simplifies interrupt handling. | |
282 | */ | |
283 | static int efx_probe_eventq(struct efx_channel *channel) | |
284 | { | |
285 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
286 | ||
287 | return falcon_probe_eventq(channel); | |
288 | } | |
289 | ||
290 | /* Prepare channel's event queue */ | |
bc3c90a2 | 291 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
292 | { |
293 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
294 | ||
295 | channel->eventq_read_ptr = 0; | |
296 | ||
bc3c90a2 | 297 | falcon_init_eventq(channel); |
8ceee660 BH |
298 | } |
299 | ||
300 | static void efx_fini_eventq(struct efx_channel *channel) | |
301 | { | |
302 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
303 | ||
304 | falcon_fini_eventq(channel); | |
305 | } | |
306 | ||
307 | static void efx_remove_eventq(struct efx_channel *channel) | |
308 | { | |
309 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
310 | ||
311 | falcon_remove_eventq(channel); | |
312 | } | |
313 | ||
314 | /************************************************************************** | |
315 | * | |
316 | * Channel handling | |
317 | * | |
318 | *************************************************************************/ | |
319 | ||
8ceee660 BH |
320 | static int efx_probe_channel(struct efx_channel *channel) |
321 | { | |
322 | struct efx_tx_queue *tx_queue; | |
323 | struct efx_rx_queue *rx_queue; | |
324 | int rc; | |
325 | ||
326 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
327 | ||
328 | rc = efx_probe_eventq(channel); | |
329 | if (rc) | |
330 | goto fail1; | |
331 | ||
332 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
333 | rc = efx_probe_tx_queue(tx_queue); | |
334 | if (rc) | |
335 | goto fail2; | |
336 | } | |
337 | ||
338 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
339 | rc = efx_probe_rx_queue(rx_queue); | |
340 | if (rc) | |
341 | goto fail3; | |
342 | } | |
343 | ||
344 | channel->n_rx_frm_trunc = 0; | |
345 | ||
346 | return 0; | |
347 | ||
348 | fail3: | |
349 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
350 | efx_remove_rx_queue(rx_queue); | |
351 | fail2: | |
352 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
353 | efx_remove_tx_queue(tx_queue); | |
354 | fail1: | |
355 | return rc; | |
356 | } | |
357 | ||
358 | ||
359 | /* Channels are shutdown and reinitialised whilst the NIC is running | |
360 | * to propagate configuration changes (mtu, checksum offload), or | |
361 | * to clear hardware error conditions | |
362 | */ | |
bc3c90a2 | 363 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
364 | { |
365 | struct efx_tx_queue *tx_queue; | |
366 | struct efx_rx_queue *rx_queue; | |
367 | struct efx_channel *channel; | |
8ceee660 | 368 | |
f7f13b0b BH |
369 | /* Calculate the rx buffer allocation parameters required to |
370 | * support the current MTU, including padding for header | |
371 | * alignment and overruns. | |
372 | */ | |
373 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
374 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
375 | efx->type->rx_buffer_padding); | |
376 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
377 | |
378 | /* Initialise the channels */ | |
379 | efx_for_each_channel(channel, efx) { | |
380 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
381 | ||
bc3c90a2 | 382 | efx_init_eventq(channel); |
8ceee660 | 383 | |
bc3c90a2 BH |
384 | efx_for_each_channel_tx_queue(tx_queue, channel) |
385 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
386 | |
387 | /* The rx buffer allocation strategy is MTU dependent */ | |
388 | efx_rx_strategy(channel); | |
389 | ||
bc3c90a2 BH |
390 | efx_for_each_channel_rx_queue(rx_queue, channel) |
391 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
392 | |
393 | WARN_ON(channel->rx_pkt != NULL); | |
394 | efx_rx_strategy(channel); | |
395 | } | |
8ceee660 BH |
396 | } |
397 | ||
398 | /* This enables event queue processing and packet transmission. | |
399 | * | |
400 | * Note that this function is not allowed to fail, since that would | |
401 | * introduce too much complexity into the suspend/resume path. | |
402 | */ | |
403 | static void efx_start_channel(struct efx_channel *channel) | |
404 | { | |
405 | struct efx_rx_queue *rx_queue; | |
406 | ||
407 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
408 | ||
409 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
410 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
411 | efx_poll, napi_weight); | |
412 | ||
5b9e207c BH |
413 | /* The interrupt handler for this channel may set work_pending |
414 | * as soon as we enable it. Make sure it's cleared before | |
415 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
416 | channel->work_pending = false; |
417 | channel->enabled = true; | |
5b9e207c | 418 | smp_wmb(); |
8ceee660 BH |
419 | |
420 | napi_enable(&channel->napi_str); | |
421 | ||
422 | /* Load up RX descriptors */ | |
423 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
424 | efx_fast_push_rx_descriptors(rx_queue); | |
425 | } | |
426 | ||
427 | /* This disables event queue processing and packet transmission. | |
428 | * This function does not guarantee that all queue processing | |
429 | * (e.g. RX refill) is complete. | |
430 | */ | |
431 | static void efx_stop_channel(struct efx_channel *channel) | |
432 | { | |
433 | struct efx_rx_queue *rx_queue; | |
434 | ||
435 | if (!channel->enabled) | |
436 | return; | |
437 | ||
438 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
439 | ||
dc8cfa55 | 440 | channel->enabled = false; |
8ceee660 BH |
441 | napi_disable(&channel->napi_str); |
442 | ||
443 | /* Ensure that any worker threads have exited or will be no-ops */ | |
444 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
445 | spin_lock_bh(&rx_queue->add_lock); | |
446 | spin_unlock_bh(&rx_queue->add_lock); | |
447 | } | |
448 | } | |
449 | ||
450 | static void efx_fini_channels(struct efx_nic *efx) | |
451 | { | |
452 | struct efx_channel *channel; | |
453 | struct efx_tx_queue *tx_queue; | |
454 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 455 | int rc; |
8ceee660 BH |
456 | |
457 | EFX_ASSERT_RESET_SERIALISED(efx); | |
458 | BUG_ON(efx->port_enabled); | |
459 | ||
6bc5d3a9 BH |
460 | rc = falcon_flush_queues(efx); |
461 | if (rc) | |
462 | EFX_ERR(efx, "failed to flush queues\n"); | |
463 | else | |
464 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
465 | ||
8ceee660 BH |
466 | efx_for_each_channel(channel, efx) { |
467 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
468 | ||
469 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
470 | efx_fini_rx_queue(rx_queue); | |
471 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
472 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
473 | efx_fini_eventq(channel); |
474 | } | |
475 | } | |
476 | ||
477 | static void efx_remove_channel(struct efx_channel *channel) | |
478 | { | |
479 | struct efx_tx_queue *tx_queue; | |
480 | struct efx_rx_queue *rx_queue; | |
481 | ||
482 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
483 | ||
484 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
485 | efx_remove_rx_queue(rx_queue); | |
486 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
487 | efx_remove_tx_queue(tx_queue); | |
488 | efx_remove_eventq(channel); | |
489 | ||
490 | channel->used_flags = 0; | |
491 | } | |
492 | ||
493 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
494 | { | |
495 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
496 | } | |
497 | ||
498 | /************************************************************************** | |
499 | * | |
500 | * Port handling | |
501 | * | |
502 | **************************************************************************/ | |
503 | ||
504 | /* This ensures that the kernel is kept informed (via | |
505 | * netif_carrier_on/off) of the link status, and also maintains the | |
506 | * link status's stop on the port's TX queue. | |
507 | */ | |
508 | static void efx_link_status_changed(struct efx_nic *efx) | |
509 | { | |
8ceee660 BH |
510 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
511 | * that no events are triggered between unregister_netdev() and the | |
512 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
513 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
514 | if (!netif_running(efx->net_dev)) | |
515 | return; | |
516 | ||
8c8661e4 BH |
517 | if (efx->port_inhibited) { |
518 | netif_carrier_off(efx->net_dev); | |
519 | return; | |
520 | } | |
521 | ||
dc8cfa55 | 522 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
523 | efx->n_link_state_changes++; |
524 | ||
525 | if (efx->link_up) | |
526 | netif_carrier_on(efx->net_dev); | |
527 | else | |
528 | netif_carrier_off(efx->net_dev); | |
529 | } | |
530 | ||
531 | /* Status message for kernel log */ | |
532 | if (efx->link_up) { | |
533 | struct mii_if_info *gmii = &efx->mii; | |
534 | unsigned adv, lpa; | |
535 | /* NONE here means direct XAUI from the controller, with no | |
536 | * MDIO-attached device we can query. */ | |
537 | if (efx->phy_type != PHY_TYPE_NONE) { | |
538 | adv = gmii_advertised(gmii); | |
539 | lpa = gmii_lpa(gmii); | |
540 | } else { | |
541 | lpa = GM_LPA_10000 | LPA_DUPLEX; | |
542 | adv = lpa; | |
543 | } | |
544 | EFX_INFO(efx, "link up at %dMbps %s-duplex " | |
545 | "(adv %04x lpa %04x) (MTU %d)%s\n", | |
546 | (efx->link_options & GM_LPA_10000 ? 10000 : | |
547 | (efx->link_options & GM_LPA_1000 ? 1000 : | |
548 | (efx->link_options & GM_LPA_100 ? 100 : | |
549 | 10))), | |
550 | (efx->link_options & GM_LPA_DUPLEX ? | |
551 | "full" : "half"), | |
552 | adv, lpa, | |
553 | efx->net_dev->mtu, | |
554 | (efx->promiscuous ? " [PROMISC]" : "")); | |
555 | } else { | |
556 | EFX_INFO(efx, "link down\n"); | |
557 | } | |
558 | ||
559 | } | |
560 | ||
561 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
562 | * caller must hold the mac_lock */ | |
8c8661e4 | 563 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
564 | { |
565 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
566 | ||
567 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
568 | raw_smp_processor_id()); | |
569 | ||
a816f75a BH |
570 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
571 | if (efx_dev_registered(efx)) { | |
572 | netif_addr_lock_bh(efx->net_dev); | |
573 | netif_addr_unlock_bh(efx->net_dev); | |
574 | } | |
575 | ||
8ceee660 BH |
576 | falcon_reconfigure_xmac(efx); |
577 | ||
578 | /* Inform kernel of loss/gain of carrier */ | |
579 | efx_link_status_changed(efx); | |
580 | } | |
581 | ||
582 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
583 | * disabled. */ | |
584 | void efx_reconfigure_port(struct efx_nic *efx) | |
585 | { | |
586 | EFX_ASSERT_RESET_SERIALISED(efx); | |
587 | ||
588 | mutex_lock(&efx->mac_lock); | |
589 | __efx_reconfigure_port(efx); | |
590 | mutex_unlock(&efx->mac_lock); | |
591 | } | |
592 | ||
593 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
594 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
595 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
596 | static void efx_reconfigure_work(struct work_struct *data) | |
597 | { | |
598 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
599 | reconfigure_work); | |
600 | ||
601 | mutex_lock(&efx->mac_lock); | |
602 | if (efx->port_enabled) | |
603 | __efx_reconfigure_port(efx); | |
604 | mutex_unlock(&efx->mac_lock); | |
605 | } | |
606 | ||
607 | static int efx_probe_port(struct efx_nic *efx) | |
608 | { | |
609 | int rc; | |
610 | ||
611 | EFX_LOG(efx, "create port\n"); | |
612 | ||
613 | /* Connect up MAC/PHY operations table and read MAC address */ | |
614 | rc = falcon_probe_port(efx); | |
615 | if (rc) | |
616 | goto err; | |
617 | ||
84ae48fe BH |
618 | if (phy_flash_cfg) |
619 | efx->phy_mode = PHY_MODE_SPECIAL; | |
620 | ||
8ceee660 BH |
621 | /* Sanity check MAC address */ |
622 | if (is_valid_ether_addr(efx->mac_address)) { | |
623 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
624 | } else { | |
e174961c JB |
625 | EFX_ERR(efx, "invalid MAC address %pM\n", |
626 | efx->mac_address); | |
8ceee660 BH |
627 | if (!allow_bad_hwaddr) { |
628 | rc = -EINVAL; | |
629 | goto err; | |
630 | } | |
631 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
632 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
633 | efx->net_dev->dev_addr); | |
8ceee660 BH |
634 | } |
635 | ||
636 | return 0; | |
637 | ||
638 | err: | |
639 | efx_remove_port(efx); | |
640 | return rc; | |
641 | } | |
642 | ||
643 | static int efx_init_port(struct efx_nic *efx) | |
644 | { | |
645 | int rc; | |
646 | ||
647 | EFX_LOG(efx, "init port\n"); | |
648 | ||
649 | /* Initialise the MAC and PHY */ | |
650 | rc = falcon_init_xmac(efx); | |
651 | if (rc) | |
652 | return rc; | |
653 | ||
dc8cfa55 | 654 | efx->port_initialized = true; |
8c8661e4 | 655 | efx->stats_enabled = true; |
8ceee660 BH |
656 | |
657 | /* Reconfigure port to program MAC registers */ | |
658 | falcon_reconfigure_xmac(efx); | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
664 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
665 | * efx_reconfigure_port() may have been cancelled */ | |
666 | static void efx_start_port(struct efx_nic *efx) | |
667 | { | |
668 | EFX_LOG(efx, "start port\n"); | |
669 | BUG_ON(efx->port_enabled); | |
670 | ||
671 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 672 | efx->port_enabled = true; |
8ceee660 BH |
673 | __efx_reconfigure_port(efx); |
674 | mutex_unlock(&efx->mac_lock); | |
675 | } | |
676 | ||
677 | /* Prevent efx_reconfigure_work and efx_monitor() from executing, and | |
678 | * efx_set_multicast_list() from scheduling efx_reconfigure_work. | |
679 | * efx_reconfigure_work can still be scheduled via NAPI processing | |
680 | * until efx_flush_all() is called */ | |
681 | static void efx_stop_port(struct efx_nic *efx) | |
682 | { | |
683 | EFX_LOG(efx, "stop port\n"); | |
684 | ||
685 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 686 | efx->port_enabled = false; |
8ceee660 BH |
687 | mutex_unlock(&efx->mac_lock); |
688 | ||
689 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 690 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
691 | netif_addr_lock_bh(efx->net_dev); |
692 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
693 | } |
694 | } | |
695 | ||
696 | static void efx_fini_port(struct efx_nic *efx) | |
697 | { | |
698 | EFX_LOG(efx, "shut down port\n"); | |
699 | ||
700 | if (!efx->port_initialized) | |
701 | return; | |
702 | ||
703 | falcon_fini_xmac(efx); | |
dc8cfa55 | 704 | efx->port_initialized = false; |
8ceee660 | 705 | |
dc8cfa55 | 706 | efx->link_up = false; |
8ceee660 BH |
707 | efx_link_status_changed(efx); |
708 | } | |
709 | ||
710 | static void efx_remove_port(struct efx_nic *efx) | |
711 | { | |
712 | EFX_LOG(efx, "destroying port\n"); | |
713 | ||
714 | falcon_remove_port(efx); | |
715 | } | |
716 | ||
717 | /************************************************************************** | |
718 | * | |
719 | * NIC handling | |
720 | * | |
721 | **************************************************************************/ | |
722 | ||
723 | /* This configures the PCI device to enable I/O and DMA. */ | |
724 | static int efx_init_io(struct efx_nic *efx) | |
725 | { | |
726 | struct pci_dev *pci_dev = efx->pci_dev; | |
727 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
728 | int rc; | |
729 | ||
730 | EFX_LOG(efx, "initialising I/O\n"); | |
731 | ||
732 | rc = pci_enable_device(pci_dev); | |
733 | if (rc) { | |
734 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
735 | goto fail1; | |
736 | } | |
737 | ||
738 | pci_set_master(pci_dev); | |
739 | ||
740 | /* Set the PCI DMA mask. Try all possibilities from our | |
741 | * genuine mask down to 32 bits, because some architectures | |
742 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
743 | * masks event though they reject 46 bit masks. | |
744 | */ | |
745 | while (dma_mask > 0x7fffffffUL) { | |
746 | if (pci_dma_supported(pci_dev, dma_mask) && | |
747 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
748 | break; | |
749 | dma_mask >>= 1; | |
750 | } | |
751 | if (rc) { | |
752 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
753 | goto fail2; | |
754 | } | |
755 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
756 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
757 | if (rc) { | |
758 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
759 | * fail with a mask that pci_set_dma_mask() accepted, | |
760 | * but just in case... | |
761 | */ | |
762 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
763 | goto fail2; | |
764 | } | |
765 | ||
766 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
767 | efx->type->mem_bar); | |
768 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
769 | if (rc) { | |
770 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
771 | rc = -EIO; | |
772 | goto fail3; | |
773 | } | |
774 | efx->membase = ioremap_nocache(efx->membase_phys, | |
775 | efx->type->mem_map_size); | |
776 | if (!efx->membase) { | |
086ea356 BH |
777 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
778 | efx->type->mem_bar, | |
779 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
780 | efx->type->mem_map_size); |
781 | rc = -ENOMEM; | |
782 | goto fail4; | |
783 | } | |
086ea356 BH |
784 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
785 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
786 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
787 | |
788 | return 0; | |
789 | ||
790 | fail4: | |
e1074a0d | 791 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 792 | fail3: |
2c118e0f | 793 | efx->membase_phys = 0; |
8ceee660 BH |
794 | fail2: |
795 | pci_disable_device(efx->pci_dev); | |
796 | fail1: | |
797 | return rc; | |
798 | } | |
799 | ||
800 | static void efx_fini_io(struct efx_nic *efx) | |
801 | { | |
802 | EFX_LOG(efx, "shutting down I/O\n"); | |
803 | ||
804 | if (efx->membase) { | |
805 | iounmap(efx->membase); | |
806 | efx->membase = NULL; | |
807 | } | |
808 | ||
809 | if (efx->membase_phys) { | |
810 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 811 | efx->membase_phys = 0; |
8ceee660 BH |
812 | } |
813 | ||
814 | pci_disable_device(efx->pci_dev); | |
815 | } | |
816 | ||
46123d04 BH |
817 | /* Get number of RX queues wanted. Return number of online CPU |
818 | * packages in the expectation that an IRQ balancer will spread | |
819 | * interrupts across them. */ | |
820 | static int efx_wanted_rx_queues(void) | |
821 | { | |
822 | cpumask_t core_mask; | |
823 | int count; | |
824 | int cpu; | |
825 | ||
826 | cpus_clear(core_mask); | |
827 | count = 0; | |
828 | for_each_online_cpu(cpu) { | |
829 | if (!cpu_isset(cpu, core_mask)) { | |
830 | ++count; | |
831 | cpus_or(core_mask, core_mask, | |
832 | topology_core_siblings(cpu)); | |
833 | } | |
834 | } | |
835 | ||
836 | return count; | |
837 | } | |
838 | ||
839 | /* Probe the number and type of interrupts we are able to obtain, and | |
840 | * the resulting numbers of channels and RX queues. | |
841 | */ | |
8ceee660 BH |
842 | static void efx_probe_interrupts(struct efx_nic *efx) |
843 | { | |
46123d04 BH |
844 | int max_channels = |
845 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
846 | int rc, i; |
847 | ||
848 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
849 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
850 | int wanted_ints; | |
28b581ab | 851 | int rx_queues; |
aa6ef27e | 852 | |
46123d04 BH |
853 | /* We want one RX queue and interrupt per CPU package |
854 | * (or as specified by the rss_cpus module parameter). | |
855 | * We will need one channel per interrupt. | |
856 | */ | |
28b581ab NT |
857 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
858 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
859 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 860 | |
28b581ab | 861 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 862 | xentries[i].entry = i; |
28b581ab | 863 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 864 | if (rc > 0) { |
28b581ab NT |
865 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
866 | " available (%d < %d).\n", rc, wanted_ints); | |
867 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
868 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
869 | wanted_ints = rc; | |
8ceee660 | 870 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 871 | wanted_ints); |
8ceee660 BH |
872 | } |
873 | ||
874 | if (rc == 0) { | |
28b581ab NT |
875 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
876 | efx->n_channels = wanted_ints; | |
877 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 878 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
879 | } else { |
880 | /* Fall back to single channel MSI */ | |
881 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
882 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
883 | } | |
884 | } | |
885 | ||
886 | /* Try single interrupt MSI */ | |
887 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 888 | efx->n_rx_queues = 1; |
28b581ab | 889 | efx->n_channels = 1; |
8ceee660 BH |
890 | rc = pci_enable_msi(efx->pci_dev); |
891 | if (rc == 0) { | |
892 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
893 | } else { |
894 | EFX_ERR(efx, "could not enable MSI\n"); | |
895 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
896 | } | |
897 | } | |
898 | ||
899 | /* Assume legacy interrupts */ | |
900 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 901 | efx->n_rx_queues = 1; |
28b581ab | 902 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
903 | efx->legacy_irq = efx->pci_dev->irq; |
904 | } | |
905 | } | |
906 | ||
907 | static void efx_remove_interrupts(struct efx_nic *efx) | |
908 | { | |
909 | struct efx_channel *channel; | |
910 | ||
911 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 912 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
913 | channel->irq = 0; |
914 | pci_disable_msi(efx->pci_dev); | |
915 | pci_disable_msix(efx->pci_dev); | |
916 | ||
917 | /* Remove legacy interrupt */ | |
918 | efx->legacy_irq = 0; | |
919 | } | |
920 | ||
8831da7b | 921 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
922 | { |
923 | struct efx_tx_queue *tx_queue; | |
924 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 925 | |
60ac1065 | 926 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
927 | if (separate_tx_channels) |
928 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
929 | else |
930 | tx_queue->channel = &efx->channel[0]; | |
931 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
932 | } | |
8ceee660 | 933 | |
8831da7b BH |
934 | efx_for_each_rx_queue(rx_queue, efx) { |
935 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
936 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
937 | } |
938 | } | |
939 | ||
940 | static int efx_probe_nic(struct efx_nic *efx) | |
941 | { | |
942 | int rc; | |
943 | ||
944 | EFX_LOG(efx, "creating NIC\n"); | |
945 | ||
946 | /* Carry out hardware-type specific initialisation */ | |
947 | rc = falcon_probe_nic(efx); | |
948 | if (rc) | |
949 | return rc; | |
950 | ||
951 | /* Determine the number of channels and RX queues by trying to hook | |
952 | * in MSI-X interrupts. */ | |
953 | efx_probe_interrupts(efx); | |
954 | ||
8831da7b | 955 | efx_set_channels(efx); |
8ceee660 BH |
956 | |
957 | /* Initialise the interrupt moderation settings */ | |
958 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | static void efx_remove_nic(struct efx_nic *efx) | |
964 | { | |
965 | EFX_LOG(efx, "destroying NIC\n"); | |
966 | ||
967 | efx_remove_interrupts(efx); | |
968 | falcon_remove_nic(efx); | |
969 | } | |
970 | ||
971 | /************************************************************************** | |
972 | * | |
973 | * NIC startup/shutdown | |
974 | * | |
975 | *************************************************************************/ | |
976 | ||
977 | static int efx_probe_all(struct efx_nic *efx) | |
978 | { | |
979 | struct efx_channel *channel; | |
980 | int rc; | |
981 | ||
982 | /* Create NIC */ | |
983 | rc = efx_probe_nic(efx); | |
984 | if (rc) { | |
985 | EFX_ERR(efx, "failed to create NIC\n"); | |
986 | goto fail1; | |
987 | } | |
988 | ||
989 | /* Create port */ | |
990 | rc = efx_probe_port(efx); | |
991 | if (rc) { | |
992 | EFX_ERR(efx, "failed to create port\n"); | |
993 | goto fail2; | |
994 | } | |
995 | ||
996 | /* Create channels */ | |
997 | efx_for_each_channel(channel, efx) { | |
998 | rc = efx_probe_channel(channel); | |
999 | if (rc) { | |
1000 | EFX_ERR(efx, "failed to create channel %d\n", | |
1001 | channel->channel); | |
1002 | goto fail3; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | return 0; | |
1007 | ||
1008 | fail3: | |
1009 | efx_for_each_channel(channel, efx) | |
1010 | efx_remove_channel(channel); | |
1011 | efx_remove_port(efx); | |
1012 | fail2: | |
1013 | efx_remove_nic(efx); | |
1014 | fail1: | |
1015 | return rc; | |
1016 | } | |
1017 | ||
1018 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1019 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1020 | * and ensures that the port is scheduled to be reconfigured. | |
1021 | * This function is safe to call multiple times when the NIC is in any | |
1022 | * state. */ | |
1023 | static void efx_start_all(struct efx_nic *efx) | |
1024 | { | |
1025 | struct efx_channel *channel; | |
1026 | ||
1027 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1028 | ||
1029 | /* Check that it is appropriate to restart the interface. All | |
1030 | * of these flags are safe to read under just the rtnl lock */ | |
1031 | if (efx->port_enabled) | |
1032 | return; | |
1033 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1034 | return; | |
55668611 | 1035 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1036 | return; |
1037 | ||
1038 | /* Mark the port as enabled so port reconfigurations can start, then | |
1039 | * restart the transmit interface early so the watchdog timer stops */ | |
1040 | efx_start_port(efx); | |
dacccc74 SH |
1041 | if (efx_dev_registered(efx)) |
1042 | efx_wake_queue(efx); | |
8ceee660 BH |
1043 | |
1044 | efx_for_each_channel(channel, efx) | |
1045 | efx_start_channel(channel); | |
1046 | ||
1047 | falcon_enable_interrupts(efx); | |
1048 | ||
1049 | /* Start hardware monitor if we're in RUNNING */ | |
1050 | if (efx->state == STATE_RUNNING) | |
1051 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1052 | efx_monitor_interval); | |
1053 | } | |
1054 | ||
1055 | /* Flush all delayed work. Should only be called when no more delayed work | |
1056 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1057 | * since we're holding the rtnl_lock at this point. */ | |
1058 | static void efx_flush_all(struct efx_nic *efx) | |
1059 | { | |
1060 | struct efx_rx_queue *rx_queue; | |
1061 | ||
1062 | /* Make sure the hardware monitor is stopped */ | |
1063 | cancel_delayed_work_sync(&efx->monitor_work); | |
1064 | ||
1065 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1066 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1067 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1068 | |
1069 | /* Stop scheduled port reconfigurations */ | |
1070 | cancel_work_sync(&efx->reconfigure_work); | |
1071 | ||
1072 | } | |
1073 | ||
1074 | /* Quiesce hardware and software without bringing the link down. | |
1075 | * Safe to call multiple times, when the nic and interface is in any | |
1076 | * state. The caller is guaranteed to subsequently be in a position | |
1077 | * to modify any hardware and software state they see fit without | |
1078 | * taking locks. */ | |
1079 | static void efx_stop_all(struct efx_nic *efx) | |
1080 | { | |
1081 | struct efx_channel *channel; | |
1082 | ||
1083 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1084 | ||
1085 | /* port_enabled can be read safely under the rtnl lock */ | |
1086 | if (!efx->port_enabled) | |
1087 | return; | |
1088 | ||
1089 | /* Disable interrupts and wait for ISR to complete */ | |
1090 | falcon_disable_interrupts(efx); | |
1091 | if (efx->legacy_irq) | |
1092 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1093 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1094 | if (channel->irq) |
1095 | synchronize_irq(channel->irq); | |
b3475645 | 1096 | } |
8ceee660 BH |
1097 | |
1098 | /* Stop all NAPI processing and synchronous rx refills */ | |
1099 | efx_for_each_channel(channel, efx) | |
1100 | efx_stop_channel(channel); | |
1101 | ||
1102 | /* Stop all asynchronous port reconfigurations. Since all | |
1103 | * event processing has already been stopped, there is no | |
1104 | * window to loose phy events */ | |
1105 | efx_stop_port(efx); | |
1106 | ||
1107 | /* Flush reconfigure_work, refill_workqueue, monitor_work */ | |
1108 | efx_flush_all(efx); | |
1109 | ||
1110 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1111 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1112 | falcon_drain_tx_fifo(efx); |
1113 | ||
1114 | /* Stop the kernel transmit interface late, so the watchdog | |
1115 | * timer isn't ticking over the flush */ | |
55668611 | 1116 | if (efx_dev_registered(efx)) { |
dacccc74 | 1117 | efx_stop_queue(efx); |
8ceee660 BH |
1118 | netif_tx_lock_bh(efx->net_dev); |
1119 | netif_tx_unlock_bh(efx->net_dev); | |
1120 | } | |
1121 | } | |
1122 | ||
1123 | static void efx_remove_all(struct efx_nic *efx) | |
1124 | { | |
1125 | struct efx_channel *channel; | |
1126 | ||
1127 | efx_for_each_channel(channel, efx) | |
1128 | efx_remove_channel(channel); | |
1129 | efx_remove_port(efx); | |
1130 | efx_remove_nic(efx); | |
1131 | } | |
1132 | ||
1133 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1134 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1135 | { |
8ceee660 BH |
1136 | EFX_ASSERT_RESET_SERIALISED(efx); |
1137 | ||
1138 | efx_stop_all(efx); | |
1139 | ||
1140 | efx_fini_channels(efx); | |
bc3c90a2 | 1141 | efx_init_channels(efx); |
8ceee660 BH |
1142 | |
1143 | efx_start_all(efx); | |
8ceee660 BH |
1144 | } |
1145 | ||
1146 | /************************************************************************** | |
1147 | * | |
1148 | * Interrupt moderation | |
1149 | * | |
1150 | **************************************************************************/ | |
1151 | ||
1152 | /* Set interrupt moderation parameters */ | |
1153 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1154 | { | |
1155 | struct efx_tx_queue *tx_queue; | |
1156 | struct efx_rx_queue *rx_queue; | |
1157 | ||
1158 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1159 | ||
1160 | efx_for_each_tx_queue(tx_queue, efx) | |
1161 | tx_queue->channel->irq_moderation = tx_usecs; | |
1162 | ||
1163 | efx_for_each_rx_queue(rx_queue, efx) | |
1164 | rx_queue->channel->irq_moderation = rx_usecs; | |
1165 | } | |
1166 | ||
1167 | /************************************************************************** | |
1168 | * | |
1169 | * Hardware monitor | |
1170 | * | |
1171 | **************************************************************************/ | |
1172 | ||
1173 | /* Run periodically off the general workqueue. Serialised against | |
1174 | * efx_reconfigure_port via the mac_lock */ | |
1175 | static void efx_monitor(struct work_struct *data) | |
1176 | { | |
1177 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1178 | monitor_work.work); | |
1179 | int rc = 0; | |
1180 | ||
1181 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1182 | raw_smp_processor_id()); | |
1183 | ||
1184 | ||
1185 | /* If the mac_lock is already held then it is likely a port | |
1186 | * reconfiguration is already in place, which will likely do | |
1187 | * most of the work of check_hw() anyway. */ | |
1188 | if (!mutex_trylock(&efx->mac_lock)) { | |
1189 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1190 | efx_monitor_interval); | |
1191 | return; | |
1192 | } | |
1193 | ||
1194 | if (efx->port_enabled) | |
1195 | rc = falcon_check_xmac(efx); | |
1196 | mutex_unlock(&efx->mac_lock); | |
1197 | ||
8ceee660 BH |
1198 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1199 | efx_monitor_interval); | |
1200 | } | |
1201 | ||
1202 | /************************************************************************** | |
1203 | * | |
1204 | * ioctls | |
1205 | * | |
1206 | *************************************************************************/ | |
1207 | ||
1208 | /* Net device ioctl | |
1209 | * Context: process, rtnl_lock() held. | |
1210 | */ | |
1211 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1212 | { | |
767e468c | 1213 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1214 | |
1215 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1216 | ||
1217 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1218 | } | |
1219 | ||
1220 | /************************************************************************** | |
1221 | * | |
1222 | * NAPI interface | |
1223 | * | |
1224 | **************************************************************************/ | |
1225 | ||
1226 | static int efx_init_napi(struct efx_nic *efx) | |
1227 | { | |
1228 | struct efx_channel *channel; | |
1229 | int rc; | |
1230 | ||
1231 | efx_for_each_channel(channel, efx) { | |
1232 | channel->napi_dev = efx->net_dev; | |
1233 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1234 | if (rc) | |
1235 | goto err; | |
1236 | } | |
1237 | return 0; | |
1238 | err: | |
1239 | efx_fini_napi(efx); | |
1240 | return rc; | |
1241 | } | |
1242 | ||
1243 | static void efx_fini_napi(struct efx_nic *efx) | |
1244 | { | |
1245 | struct efx_channel *channel; | |
1246 | ||
1247 | efx_for_each_channel(channel, efx) { | |
1248 | efx_lro_fini(&channel->lro_mgr); | |
1249 | channel->napi_dev = NULL; | |
1250 | } | |
1251 | } | |
1252 | ||
1253 | /************************************************************************** | |
1254 | * | |
1255 | * Kernel netpoll interface | |
1256 | * | |
1257 | *************************************************************************/ | |
1258 | ||
1259 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1260 | ||
1261 | /* Although in the common case interrupts will be disabled, this is not | |
1262 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1263 | * so no locking is required. | |
1264 | */ | |
1265 | static void efx_netpoll(struct net_device *net_dev) | |
1266 | { | |
767e468c | 1267 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1268 | struct efx_channel *channel; |
1269 | ||
64ee3120 | 1270 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1271 | efx_schedule_channel(channel); |
1272 | } | |
1273 | ||
1274 | #endif | |
1275 | ||
1276 | /************************************************************************** | |
1277 | * | |
1278 | * Kernel net device interface | |
1279 | * | |
1280 | *************************************************************************/ | |
1281 | ||
1282 | /* Context: process, rtnl_lock() held. */ | |
1283 | static int efx_net_open(struct net_device *net_dev) | |
1284 | { | |
767e468c | 1285 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1286 | EFX_ASSERT_RESET_SERIALISED(efx); |
1287 | ||
1288 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1289 | raw_smp_processor_id()); | |
1290 | ||
f8b87c17 BH |
1291 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1292 | return -EBUSY; | |
1293 | ||
8ceee660 BH |
1294 | efx_start_all(efx); |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | /* Context: process, rtnl_lock() held. | |
1299 | * Note that the kernel will ignore our return code; this method | |
1300 | * should really be a void. | |
1301 | */ | |
1302 | static int efx_net_stop(struct net_device *net_dev) | |
1303 | { | |
767e468c | 1304 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1305 | |
1306 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1307 | raw_smp_processor_id()); | |
1308 | ||
1309 | /* Stop the device and flush all the channels */ | |
1310 | efx_stop_all(efx); | |
1311 | efx_fini_channels(efx); | |
bc3c90a2 | 1312 | efx_init_channels(efx); |
8ceee660 BH |
1313 | |
1314 | return 0; | |
1315 | } | |
1316 | ||
5b9e207c | 1317 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1318 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1319 | { | |
767e468c | 1320 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1321 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1322 | struct net_device_stats *stats = &net_dev->stats; | |
1323 | ||
5b9e207c BH |
1324 | /* Update stats if possible, but do not wait if another thread |
1325 | * is updating them (or resetting the NIC); slightly stale | |
1326 | * stats are acceptable. | |
1327 | */ | |
8ceee660 BH |
1328 | if (!spin_trylock(&efx->stats_lock)) |
1329 | return stats; | |
8c8661e4 | 1330 | if (efx->stats_enabled) { |
8ceee660 BH |
1331 | falcon_update_stats_xmac(efx); |
1332 | falcon_update_nic_stats(efx); | |
1333 | } | |
1334 | spin_unlock(&efx->stats_lock); | |
1335 | ||
1336 | stats->rx_packets = mac_stats->rx_packets; | |
1337 | stats->tx_packets = mac_stats->tx_packets; | |
1338 | stats->rx_bytes = mac_stats->rx_bytes; | |
1339 | stats->tx_bytes = mac_stats->tx_bytes; | |
1340 | stats->multicast = mac_stats->rx_multicast; | |
1341 | stats->collisions = mac_stats->tx_collision; | |
1342 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1343 | mac_stats->rx_length_error); | |
1344 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1345 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1346 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1347 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1348 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1349 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1350 | ||
1351 | stats->rx_errors = (stats->rx_length_errors + | |
1352 | stats->rx_over_errors + | |
1353 | stats->rx_crc_errors + | |
1354 | stats->rx_frame_errors + | |
1355 | stats->rx_fifo_errors + | |
1356 | stats->rx_missed_errors + | |
1357 | mac_stats->rx_symbol_error); | |
1358 | stats->tx_errors = (stats->tx_window_errors + | |
1359 | mac_stats->tx_bad); | |
1360 | ||
1361 | return stats; | |
1362 | } | |
1363 | ||
1364 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1365 | static void efx_watchdog(struct net_device *net_dev) | |
1366 | { | |
767e468c | 1367 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1368 | |
739bb23d BH |
1369 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1370 | " resetting channels\n", | |
1371 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1372 | |
739bb23d | 1373 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1374 | } |
1375 | ||
1376 | ||
1377 | /* Context: process, rtnl_lock() held. */ | |
1378 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1379 | { | |
767e468c | 1380 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1381 | int rc = 0; |
1382 | ||
1383 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1384 | ||
1385 | if (new_mtu > EFX_MAX_MTU) | |
1386 | return -EINVAL; | |
1387 | ||
1388 | efx_stop_all(efx); | |
1389 | ||
1390 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1391 | ||
1392 | efx_fini_channels(efx); | |
1393 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1394 | efx_init_channels(efx); |
8ceee660 BH |
1395 | |
1396 | efx_start_all(efx); | |
1397 | return rc; | |
8ceee660 BH |
1398 | } |
1399 | ||
1400 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1401 | { | |
767e468c | 1402 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1403 | struct sockaddr *addr = data; |
1404 | char *new_addr = addr->sa_data; | |
1405 | ||
1406 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1407 | ||
1408 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1409 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1410 | new_addr); | |
8ceee660 BH |
1411 | return -EINVAL; |
1412 | } | |
1413 | ||
1414 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1415 | ||
1416 | /* Reconfigure the MAC */ | |
1417 | efx_reconfigure_port(efx); | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
a816f75a | 1422 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1423 | static void efx_set_multicast_list(struct net_device *net_dev) |
1424 | { | |
767e468c | 1425 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1426 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1427 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1428 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1429 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1430 | u32 crc; |
1431 | int bit; | |
1432 | int i; | |
1433 | ||
a816f75a | 1434 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1435 | |
1436 | /* Build multicast hash table */ | |
1437 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1438 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1439 | } else { | |
1440 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1441 | for (i = 0; i < net_dev->mc_count; i++) { | |
1442 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1443 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1444 | set_bit_le(bit, mc_hash->byte); | |
1445 | mc_list = mc_list->next; | |
1446 | } | |
1447 | } | |
1448 | ||
a816f75a BH |
1449 | if (!efx->port_enabled) |
1450 | /* Delay pushing settings until efx_start_port() */ | |
1451 | return; | |
1452 | ||
1453 | if (changed) | |
1454 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
1455 | ||
8ceee660 BH |
1456 | /* Create and activate new global multicast hash table */ |
1457 | falcon_set_multicast_hash(efx); | |
1458 | } | |
1459 | ||
c3ecb9f3 SH |
1460 | static const struct net_device_ops efx_netdev_ops = { |
1461 | .ndo_open = efx_net_open, | |
1462 | .ndo_stop = efx_net_stop, | |
1463 | .ndo_get_stats = efx_net_stats, | |
1464 | .ndo_tx_timeout = efx_watchdog, | |
1465 | .ndo_start_xmit = efx_hard_start_xmit, | |
1466 | .ndo_validate_addr = eth_validate_addr, | |
1467 | .ndo_do_ioctl = efx_ioctl, | |
1468 | .ndo_change_mtu = efx_change_mtu, | |
1469 | .ndo_set_mac_address = efx_set_mac_address, | |
1470 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1471 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1472 | .ndo_poll_controller = efx_netpoll, | |
1473 | #endif | |
1474 | }; | |
1475 | ||
8ceee660 BH |
1476 | static int efx_netdev_event(struct notifier_block *this, |
1477 | unsigned long event, void *ptr) | |
1478 | { | |
d3208b5e | 1479 | struct net_device *net_dev = ptr; |
8ceee660 | 1480 | |
c3ecb9f3 | 1481 | if (net_dev->netdev_ops == &efx_netdev_ops && event == NETDEV_CHANGENAME) { |
767e468c | 1482 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1483 | |
1484 | strcpy(efx->name, net_dev->name); | |
f4150724 | 1485 | efx_mtd_rename(efx); |
8ceee660 BH |
1486 | } |
1487 | ||
1488 | return NOTIFY_DONE; | |
1489 | } | |
1490 | ||
1491 | static struct notifier_block efx_netdev_notifier = { | |
1492 | .notifier_call = efx_netdev_event, | |
1493 | }; | |
1494 | ||
1495 | static int efx_register_netdev(struct efx_nic *efx) | |
1496 | { | |
1497 | struct net_device *net_dev = efx->net_dev; | |
1498 | int rc; | |
1499 | ||
1500 | net_dev->watchdog_timeo = 5 * HZ; | |
1501 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1502 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1503 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1504 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1505 | ||
1506 | /* Always start with carrier off; PHY events will detect the link */ | |
1507 | netif_carrier_off(efx->net_dev); | |
1508 | ||
1509 | /* Clear MAC statistics */ | |
1510 | falcon_update_stats_xmac(efx); | |
1511 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
1512 | ||
1513 | rc = register_netdev(net_dev); | |
1514 | if (rc) { | |
1515 | EFX_ERR(efx, "could not register net dev\n"); | |
1516 | return rc; | |
1517 | } | |
1518 | strcpy(efx->name, net_dev->name); | |
1519 | ||
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1524 | { | |
1525 | struct efx_tx_queue *tx_queue; | |
1526 | ||
1527 | if (!efx->net_dev) | |
1528 | return; | |
1529 | ||
767e468c | 1530 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1531 | |
1532 | /* Free up any skbs still remaining. This has to happen before | |
1533 | * we try to unregister the netdev as running their destructors | |
1534 | * may be needed to get the device ref. count to 0. */ | |
1535 | efx_for_each_tx_queue(tx_queue, efx) | |
1536 | efx_release_tx_buffers(tx_queue); | |
1537 | ||
55668611 | 1538 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1539 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1540 | unregister_netdev(efx->net_dev); | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | /************************************************************************** | |
1545 | * | |
1546 | * Device reset and suspend | |
1547 | * | |
1548 | **************************************************************************/ | |
1549 | ||
2467ca46 BH |
1550 | /* Tears down the entire software state and most of the hardware state |
1551 | * before reset. */ | |
8c8661e4 | 1552 | void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
8ceee660 BH |
1553 | { |
1554 | int rc; | |
1555 | ||
1556 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1557 | ||
2467ca46 BH |
1558 | /* The net_dev->get_stats handler is quite slow, and will fail |
1559 | * if a fetch is pending over reset. Serialise against it. */ | |
1560 | spin_lock(&efx->stats_lock); | |
8c8661e4 | 1561 | efx->stats_enabled = false; |
2467ca46 BH |
1562 | spin_unlock(&efx->stats_lock); |
1563 | ||
1564 | efx_stop_all(efx); | |
1565 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1566 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1567 | |
8ceee660 | 1568 | rc = falcon_xmac_get_settings(efx, ecmd); |
2467ca46 | 1569 | if (rc) |
8ceee660 | 1570 | EFX_ERR(efx, "could not back up PHY settings\n"); |
8ceee660 BH |
1571 | |
1572 | efx_fini_channels(efx); | |
8ceee660 BH |
1573 | } |
1574 | ||
2467ca46 BH |
1575 | /* This function will always ensure that the locks acquired in |
1576 | * efx_reset_down() are released. A failure return code indicates | |
1577 | * that we were unable to reinitialise the hardware, and the | |
1578 | * driver should be disabled. If ok is false, then the rx and tx | |
1579 | * engines are not restarted, pending a RESET_DISABLE. */ | |
8c8661e4 | 1580 | int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok) |
8ceee660 BH |
1581 | { |
1582 | int rc; | |
1583 | ||
2467ca46 | 1584 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1585 | |
2467ca46 | 1586 | rc = falcon_init_nic(efx); |
8ceee660 | 1587 | if (rc) { |
2467ca46 BH |
1588 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1589 | ok = false; | |
8ceee660 BH |
1590 | } |
1591 | ||
2467ca46 BH |
1592 | if (ok) { |
1593 | efx_init_channels(efx); | |
8ceee660 | 1594 | |
2467ca46 BH |
1595 | if (falcon_xmac_set_settings(efx, ecmd)) |
1596 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
1597 | } | |
1598 | ||
f4150724 | 1599 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1600 | mutex_unlock(&efx->mac_lock); |
1601 | ||
8c8661e4 | 1602 | if (ok) { |
2467ca46 | 1603 | efx_start_all(efx); |
8c8661e4 BH |
1604 | efx->stats_enabled = true; |
1605 | } | |
8ceee660 BH |
1606 | return rc; |
1607 | } | |
1608 | ||
1609 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1610 | * Note that the reset may fail, in which case the card will be left | |
1611 | * in a most-probably-unusable state. | |
1612 | * | |
1613 | * This function will sleep. You cannot reset from within an atomic | |
1614 | * state; use efx_schedule_reset() instead. | |
1615 | * | |
1616 | * Grabs the rtnl_lock. | |
1617 | */ | |
1618 | static int efx_reset(struct efx_nic *efx) | |
1619 | { | |
1620 | struct ethtool_cmd ecmd; | |
1621 | enum reset_type method = efx->reset_pending; | |
1622 | int rc; | |
1623 | ||
1624 | /* Serialise with kernel interfaces */ | |
1625 | rtnl_lock(); | |
1626 | ||
1627 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1628 | * flag set so that efx_pci_probe_main will be retried */ | |
1629 | if (efx->state != STATE_RUNNING) { | |
1630 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1631 | goto unlock_rtnl; | |
1632 | } | |
1633 | ||
8ceee660 BH |
1634 | EFX_INFO(efx, "resetting (%d)\n", method); |
1635 | ||
2467ca46 | 1636 | efx_reset_down(efx, &ecmd); |
8ceee660 BH |
1637 | |
1638 | rc = falcon_reset_hw(efx, method); | |
1639 | if (rc) { | |
1640 | EFX_ERR(efx, "failed to reset hardware\n"); | |
2467ca46 | 1641 | goto fail; |
8ceee660 BH |
1642 | } |
1643 | ||
1644 | /* Allow resets to be rescheduled. */ | |
1645 | efx->reset_pending = RESET_TYPE_NONE; | |
1646 | ||
1647 | /* Reinitialise bus-mastering, which may have been turned off before | |
1648 | * the reset was scheduled. This is still appropriate, even in the | |
1649 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1650 | * can respond to requests. */ | |
1651 | pci_set_master(efx->pci_dev); | |
1652 | ||
8ceee660 BH |
1653 | /* Leave device stopped if necessary */ |
1654 | if (method == RESET_TYPE_DISABLE) { | |
8ceee660 | 1655 | rc = -EIO; |
2467ca46 | 1656 | goto fail; |
8ceee660 BH |
1657 | } |
1658 | ||
2467ca46 | 1659 | rc = efx_reset_up(efx, &ecmd, true); |
8ceee660 | 1660 | if (rc) |
2467ca46 | 1661 | goto disable; |
8ceee660 | 1662 | |
8ceee660 | 1663 | EFX_LOG(efx, "reset complete\n"); |
8ceee660 BH |
1664 | unlock_rtnl: |
1665 | rtnl_unlock(); | |
1666 | return 0; | |
1667 | ||
2467ca46 BH |
1668 | fail: |
1669 | efx_reset_up(efx, &ecmd, false); | |
1670 | disable: | |
8ceee660 BH |
1671 | EFX_ERR(efx, "has been disabled\n"); |
1672 | efx->state = STATE_DISABLED; | |
1673 | ||
8ceee660 BH |
1674 | rtnl_unlock(); |
1675 | efx_unregister_netdev(efx); | |
1676 | efx_fini_port(efx); | |
1677 | return rc; | |
1678 | } | |
1679 | ||
1680 | /* The worker thread exists so that code that cannot sleep can | |
1681 | * schedule a reset for later. | |
1682 | */ | |
1683 | static void efx_reset_work(struct work_struct *data) | |
1684 | { | |
1685 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1686 | ||
1687 | efx_reset(nic); | |
1688 | } | |
1689 | ||
1690 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1691 | { | |
1692 | enum reset_type method; | |
1693 | ||
1694 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1695 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1696 | return; | |
1697 | } | |
1698 | ||
1699 | switch (type) { | |
1700 | case RESET_TYPE_INVISIBLE: | |
1701 | case RESET_TYPE_ALL: | |
1702 | case RESET_TYPE_WORLD: | |
1703 | case RESET_TYPE_DISABLE: | |
1704 | method = type; | |
1705 | break; | |
1706 | case RESET_TYPE_RX_RECOVERY: | |
1707 | case RESET_TYPE_RX_DESC_FETCH: | |
1708 | case RESET_TYPE_TX_DESC_FETCH: | |
1709 | case RESET_TYPE_TX_SKIP: | |
1710 | method = RESET_TYPE_INVISIBLE; | |
1711 | break; | |
1712 | default: | |
1713 | method = RESET_TYPE_ALL; | |
1714 | break; | |
1715 | } | |
1716 | ||
1717 | if (method != type) | |
1718 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1719 | else | |
1720 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1721 | ||
1722 | efx->reset_pending = method; | |
1723 | ||
1ab00629 | 1724 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1725 | } |
1726 | ||
1727 | /************************************************************************** | |
1728 | * | |
1729 | * List of NICs we support | |
1730 | * | |
1731 | **************************************************************************/ | |
1732 | ||
1733 | /* PCI device ID table */ | |
1734 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1735 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1736 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1737 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1738 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1739 | {0} /* end of list */ | |
1740 | }; | |
1741 | ||
1742 | /************************************************************************** | |
1743 | * | |
1744 | * Dummy PHY/MAC/Board operations | |
1745 | * | |
01aad7b6 | 1746 | * Can be used for some unimplemented operations |
8ceee660 BH |
1747 | * Needed so all function pointers are valid and do not have to be tested |
1748 | * before use | |
1749 | * | |
1750 | **************************************************************************/ | |
1751 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1752 | { | |
1753 | return 0; | |
1754 | } | |
1755 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1756 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 BH |
1757 | |
1758 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1759 | .init = efx_port_dummy_op_int, | |
1760 | .reconfigure = efx_port_dummy_op_void, | |
1761 | .check_hw = efx_port_dummy_op_int, | |
1762 | .fini = efx_port_dummy_op_void, | |
1763 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1764 | }; |
1765 | ||
8ceee660 | 1766 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 BH |
1767 | .init = efx_port_dummy_op_int, |
1768 | .init_leds = efx_port_dummy_op_int, | |
1769 | .set_fault_led = efx_port_dummy_op_blink, | |
a17102b1 | 1770 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1771 | .blink = efx_port_dummy_op_blink, |
1772 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1773 | }; |
1774 | ||
1775 | /************************************************************************** | |
1776 | * | |
1777 | * Data housekeeping | |
1778 | * | |
1779 | **************************************************************************/ | |
1780 | ||
1781 | /* This zeroes out and then fills in the invariants in a struct | |
1782 | * efx_nic (including all sub-structures). | |
1783 | */ | |
1784 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1785 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1786 | { | |
1787 | struct efx_channel *channel; | |
1788 | struct efx_tx_queue *tx_queue; | |
1789 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1790 | int i; |
8ceee660 BH |
1791 | |
1792 | /* Initialise common structures */ | |
1793 | memset(efx, 0, sizeof(*efx)); | |
1794 | spin_lock_init(&efx->biu_lock); | |
1795 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1796 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1797 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1798 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1799 | efx->pci_dev = pci_dev; | |
1800 | efx->state = STATE_INIT; | |
1801 | efx->reset_pending = RESET_TYPE_NONE; | |
1802 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1803 | efx->board_info = efx_dummy_board_info; | |
1804 | ||
1805 | efx->net_dev = net_dev; | |
dc8cfa55 | 1806 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1807 | spin_lock_init(&efx->netif_stop_lock); |
1808 | spin_lock_init(&efx->stats_lock); | |
1809 | mutex_init(&efx->mac_lock); | |
1810 | efx->phy_op = &efx_dummy_phy_operations; | |
1811 | efx->mii.dev = net_dev; | |
1812 | INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work); | |
1813 | atomic_set(&efx->netif_stop_count, 1); | |
1814 | ||
1815 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1816 | channel = &efx->channel[i]; | |
1817 | channel->efx = efx; | |
1818 | channel->channel = i; | |
dc8cfa55 | 1819 | channel->work_pending = false; |
8ceee660 | 1820 | } |
60ac1065 | 1821 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1822 | tx_queue = &efx->tx_queue[i]; |
1823 | tx_queue->efx = efx; | |
1824 | tx_queue->queue = i; | |
1825 | tx_queue->buffer = NULL; | |
1826 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1827 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1828 | } |
1829 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1830 | rx_queue = &efx->rx_queue[i]; | |
1831 | rx_queue->efx = efx; | |
1832 | rx_queue->queue = i; | |
1833 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1834 | rx_queue->buffer = NULL; | |
1835 | spin_lock_init(&rx_queue->add_lock); | |
1836 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1837 | } | |
1838 | ||
1839 | efx->type = type; | |
1840 | ||
1841 | /* Sanity-check NIC type */ | |
1842 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1843 | (efx->type->txd_ring_mask + 1)); | |
1844 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1845 | (efx->type->rxd_ring_mask + 1)); | |
1846 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1847 | (efx->type->evq_size - 1)); | |
1848 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1849 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1850 | (efx->type->txd_ring_mask + 1 + | |
1851 | efx->type->rxd_ring_mask + 1)); | |
1852 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1853 | ||
1854 | /* Higher numbered interrupt modes are less capable! */ | |
1855 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1856 | interrupt_mode); | |
1857 | ||
1858 | efx->workqueue = create_singlethread_workqueue("sfc_work"); | |
1ab00629 SH |
1859 | if (!efx->workqueue) |
1860 | return -ENOMEM; | |
8d9853d9 | 1861 | |
8ceee660 | 1862 | return 0; |
8ceee660 BH |
1863 | } |
1864 | ||
1865 | static void efx_fini_struct(struct efx_nic *efx) | |
1866 | { | |
1867 | if (efx->workqueue) { | |
1868 | destroy_workqueue(efx->workqueue); | |
1869 | efx->workqueue = NULL; | |
1870 | } | |
1871 | } | |
1872 | ||
1873 | /************************************************************************** | |
1874 | * | |
1875 | * PCI interface | |
1876 | * | |
1877 | **************************************************************************/ | |
1878 | ||
1879 | /* Main body of final NIC shutdown code | |
1880 | * This is called only at module unload (or hotplug removal). | |
1881 | */ | |
1882 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1883 | { | |
1884 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1885 | ||
1886 | /* Skip everything if we never obtained a valid membase */ | |
1887 | if (!efx->membase) | |
1888 | return; | |
1889 | ||
1890 | efx_fini_channels(efx); | |
1891 | efx_fini_port(efx); | |
1892 | ||
1893 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1894 | efx->board_info.fini(efx); |
8ceee660 BH |
1895 | falcon_fini_interrupt(efx); |
1896 | ||
1897 | efx_fini_napi(efx); | |
1898 | efx_remove_all(efx); | |
1899 | } | |
1900 | ||
1901 | /* Final NIC shutdown | |
1902 | * This is called only at module unload (or hotplug removal). | |
1903 | */ | |
1904 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1905 | { | |
1906 | struct efx_nic *efx; | |
1907 | ||
1908 | efx = pci_get_drvdata(pci_dev); | |
1909 | if (!efx) | |
1910 | return; | |
1911 | ||
f4150724 BH |
1912 | efx_mtd_remove(efx); |
1913 | ||
8ceee660 BH |
1914 | /* Mark the NIC as fini, then stop the interface */ |
1915 | rtnl_lock(); | |
1916 | efx->state = STATE_FINI; | |
1917 | dev_close(efx->net_dev); | |
1918 | ||
1919 | /* Allow any queued efx_resets() to complete */ | |
1920 | rtnl_unlock(); | |
1921 | ||
1922 | if (efx->membase == NULL) | |
1923 | goto out; | |
1924 | ||
1925 | efx_unregister_netdev(efx); | |
1926 | ||
1927 | /* Wait for any scheduled resets to complete. No more will be | |
1928 | * scheduled from this point because efx_stop_all() has been | |
1929 | * called, we are no longer registered with driverlink, and | |
1930 | * the net_device's have been removed. */ | |
1ab00629 | 1931 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
1932 | |
1933 | efx_pci_remove_main(efx); | |
1934 | ||
1935 | out: | |
1936 | efx_fini_io(efx); | |
1937 | EFX_LOG(efx, "shutdown successful\n"); | |
1938 | ||
1939 | pci_set_drvdata(pci_dev, NULL); | |
1940 | efx_fini_struct(efx); | |
1941 | free_netdev(efx->net_dev); | |
1942 | }; | |
1943 | ||
1944 | /* Main body of NIC initialisation | |
1945 | * This is called at module load (or hotplug insertion, theoretically). | |
1946 | */ | |
1947 | static int efx_pci_probe_main(struct efx_nic *efx) | |
1948 | { | |
1949 | int rc; | |
1950 | ||
1951 | /* Do start-of-day initialisation */ | |
1952 | rc = efx_probe_all(efx); | |
1953 | if (rc) | |
1954 | goto fail1; | |
1955 | ||
1956 | rc = efx_init_napi(efx); | |
1957 | if (rc) | |
1958 | goto fail2; | |
1959 | ||
1960 | /* Initialise the board */ | |
1961 | rc = efx->board_info.init(efx); | |
1962 | if (rc) { | |
1963 | EFX_ERR(efx, "failed to initialise board\n"); | |
1964 | goto fail3; | |
1965 | } | |
1966 | ||
1967 | rc = falcon_init_nic(efx); | |
1968 | if (rc) { | |
1969 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1970 | goto fail4; | |
1971 | } | |
1972 | ||
1973 | rc = efx_init_port(efx); | |
1974 | if (rc) { | |
1975 | EFX_ERR(efx, "failed to initialise port\n"); | |
1976 | goto fail5; | |
1977 | } | |
1978 | ||
bc3c90a2 | 1979 | efx_init_channels(efx); |
8ceee660 BH |
1980 | |
1981 | rc = falcon_init_interrupt(efx); | |
1982 | if (rc) | |
bc3c90a2 | 1983 | goto fail6; |
8ceee660 BH |
1984 | |
1985 | return 0; | |
1986 | ||
8ceee660 | 1987 | fail6: |
bc3c90a2 | 1988 | efx_fini_channels(efx); |
8ceee660 BH |
1989 | efx_fini_port(efx); |
1990 | fail5: | |
1991 | fail4: | |
a17102b1 | 1992 | efx->board_info.fini(efx); |
8ceee660 BH |
1993 | fail3: |
1994 | efx_fini_napi(efx); | |
1995 | fail2: | |
1996 | efx_remove_all(efx); | |
1997 | fail1: | |
1998 | return rc; | |
1999 | } | |
2000 | ||
2001 | /* NIC initialisation | |
2002 | * | |
2003 | * This is called at module load (or hotplug insertion, | |
2004 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2005 | * sets up and registers the network devices with the kernel and hooks | |
2006 | * the interrupt service routine. It does not prepare the device for | |
2007 | * transmission; this is left to the first time one of the network | |
2008 | * interfaces is brought up (i.e. efx_net_open). | |
2009 | */ | |
2010 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2011 | const struct pci_device_id *entry) | |
2012 | { | |
2013 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2014 | struct net_device *net_dev; | |
2015 | struct efx_nic *efx; | |
2016 | int i, rc; | |
2017 | ||
2018 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2019 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2020 | if (!net_dev) | |
2021 | return -ENOMEM; | |
b9b39b62 BH |
2022 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2023 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2024 | if (lro) |
2025 | net_dev->features |= NETIF_F_LRO; | |
28506563 BH |
2026 | /* Mask for features that also apply to VLAN devices */ |
2027 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2028 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2029 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2030 | pci_set_drvdata(pci_dev, efx); |
2031 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2032 | if (rc) | |
2033 | goto fail1; | |
2034 | ||
2035 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2036 | ||
2037 | /* Set up basic I/O (BAR mappings etc) */ | |
2038 | rc = efx_init_io(efx); | |
2039 | if (rc) | |
2040 | goto fail2; | |
2041 | ||
2042 | /* No serialisation is required with the reset path because | |
2043 | * we're in STATE_INIT. */ | |
2044 | for (i = 0; i < 5; i++) { | |
2045 | rc = efx_pci_probe_main(efx); | |
2046 | if (rc == 0) | |
2047 | break; | |
2048 | ||
2049 | /* Serialise against efx_reset(). No more resets will be | |
2050 | * scheduled since efx_stop_all() has been called, and we | |
2051 | * have not and never have been registered with either | |
2052 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2053 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2054 | |
2055 | /* Retry if a recoverably reset event has been scheduled */ | |
2056 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2057 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2058 | goto fail3; | |
2059 | ||
2060 | efx->reset_pending = RESET_TYPE_NONE; | |
2061 | } | |
2062 | ||
2063 | if (rc) { | |
2064 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2065 | goto fail4; | |
2066 | } | |
2067 | ||
2068 | /* Switch to the running state before we expose the device to | |
2069 | * the OS. This is to ensure that the initial gathering of | |
2070 | * MAC stats succeeds. */ | |
2071 | rtnl_lock(); | |
2072 | efx->state = STATE_RUNNING; | |
2073 | rtnl_unlock(); | |
2074 | ||
2075 | rc = efx_register_netdev(efx); | |
2076 | if (rc) | |
2077 | goto fail5; | |
2078 | ||
2079 | EFX_LOG(efx, "initialisation successful\n"); | |
2080 | ||
f4150724 | 2081 | efx_mtd_probe(efx); /* allowed to fail */ |
8ceee660 BH |
2082 | return 0; |
2083 | ||
2084 | fail5: | |
2085 | efx_pci_remove_main(efx); | |
2086 | fail4: | |
2087 | fail3: | |
2088 | efx_fini_io(efx); | |
2089 | fail2: | |
2090 | efx_fini_struct(efx); | |
2091 | fail1: | |
2092 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2093 | free_netdev(net_dev); | |
2094 | return rc; | |
2095 | } | |
2096 | ||
2097 | static struct pci_driver efx_pci_driver = { | |
2098 | .name = EFX_DRIVER_NAME, | |
2099 | .id_table = efx_pci_table, | |
2100 | .probe = efx_pci_probe, | |
2101 | .remove = efx_pci_remove, | |
2102 | }; | |
2103 | ||
2104 | /************************************************************************** | |
2105 | * | |
2106 | * Kernel module interface | |
2107 | * | |
2108 | *************************************************************************/ | |
2109 | ||
2110 | module_param(interrupt_mode, uint, 0444); | |
2111 | MODULE_PARM_DESC(interrupt_mode, | |
2112 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2113 | ||
2114 | static int __init efx_init_module(void) | |
2115 | { | |
2116 | int rc; | |
2117 | ||
2118 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2119 | ||
2120 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2121 | if (rc) | |
2122 | goto err_notifier; | |
2123 | ||
2124 | refill_workqueue = create_workqueue("sfc_refill"); | |
2125 | if (!refill_workqueue) { | |
2126 | rc = -ENOMEM; | |
2127 | goto err_refill; | |
2128 | } | |
1ab00629 SH |
2129 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2130 | if (!reset_workqueue) { | |
2131 | rc = -ENOMEM; | |
2132 | goto err_reset; | |
2133 | } | |
8ceee660 BH |
2134 | |
2135 | rc = pci_register_driver(&efx_pci_driver); | |
2136 | if (rc < 0) | |
2137 | goto err_pci; | |
2138 | ||
2139 | return 0; | |
2140 | ||
2141 | err_pci: | |
1ab00629 SH |
2142 | destroy_workqueue(reset_workqueue); |
2143 | err_reset: | |
8ceee660 BH |
2144 | destroy_workqueue(refill_workqueue); |
2145 | err_refill: | |
2146 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2147 | err_notifier: | |
2148 | return rc; | |
2149 | } | |
2150 | ||
2151 | static void __exit efx_exit_module(void) | |
2152 | { | |
2153 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2154 | ||
2155 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2156 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2157 | destroy_workqueue(refill_workqueue); |
2158 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2159 | ||
2160 | } | |
2161 | ||
2162 | module_init(efx_init_module); | |
2163 | module_exit(efx_exit_module); | |
2164 | ||
2165 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2166 | "Solarflare Communications"); | |
2167 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2168 | MODULE_LICENSE("GPL"); | |
2169 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |