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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
8ceee660 | 24 | #include "net_driver.h" |
8ceee660 BH |
25 | #include "efx.h" |
26 | #include "mdio_10g.h" | |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
c459302d BH |
71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
72 | const char *efx_reset_type_names[] = { | |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* This controls whether or not the driver will initialise devices |
126 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
127 | * such devices will be initialised with a random locally-generated | |
128 | * MAC address. This allows for loading the sfc_mtd driver to | |
129 | * reprogram the flash, even if the flash contents (including the MAC | |
130 | * address) have previously been erased. | |
131 | */ | |
132 | static unsigned int allow_bad_hwaddr; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * The default for RX should strike a balance between increasing the | |
138 | * round-trip latency and reducing overhead. | |
139 | */ | |
140 | static unsigned int rx_irq_mod_usec = 60; | |
141 | ||
142 | /* Initial interrupt moderation settings. They can be modified after | |
143 | * module load with ethtool. | |
144 | * | |
145 | * This default is chosen to ensure that a 10G link does not go idle | |
146 | * while a TX queue is stopped after it has become full. A queue is | |
147 | * restarted when it drops below half full. The time this takes (assuming | |
148 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
149 | * 512 / 3 * 1.2 = 205 usec. | |
150 | */ | |
151 | static unsigned int tx_irq_mod_usec = 150; | |
152 | ||
153 | /* This is the first interrupt mode to try out of: | |
154 | * 0 => MSI-X | |
155 | * 1 => MSI | |
156 | * 2 => legacy | |
157 | */ | |
158 | static unsigned int interrupt_mode; | |
159 | ||
160 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
161 | * i.e. the number of CPUs among which we may distribute simultaneous | |
162 | * interrupt handling. | |
163 | * | |
164 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
165 | * The default (0) means to assign an interrupt to each package (level II cache) | |
166 | */ | |
167 | static unsigned int rss_cpus; | |
168 | module_param(rss_cpus, uint, 0444); | |
169 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
170 | ||
84ae48fe BH |
171 | static int phy_flash_cfg; |
172 | module_param(phy_flash_cfg, int, 0644); | |
173 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
174 | ||
6fb70fd1 BH |
175 | static unsigned irq_adapt_low_thresh = 10000; |
176 | module_param(irq_adapt_low_thresh, uint, 0644); | |
177 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
178 | "Threshold score for reducing IRQ moderation"); | |
179 | ||
180 | static unsigned irq_adapt_high_thresh = 20000; | |
181 | module_param(irq_adapt_high_thresh, uint, 0644); | |
182 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
183 | "Threshold score for increasing IRQ moderation"); | |
184 | ||
62776d03 BH |
185 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
186 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
187 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
188 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
189 | module_param(debug, uint, 0); | |
190 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
191 | ||
8ceee660 BH |
192 | /************************************************************************** |
193 | * | |
194 | * Utility functions and prototypes | |
195 | * | |
196 | *************************************************************************/ | |
4642610c BH |
197 | |
198 | static void efx_remove_channels(struct efx_nic *efx); | |
8ceee660 BH |
199 | static void efx_remove_port(struct efx_nic *efx); |
200 | static void efx_fini_napi(struct efx_nic *efx); | |
4642610c BH |
201 | static void efx_fini_struct(struct efx_nic *efx); |
202 | static void efx_start_all(struct efx_nic *efx); | |
203 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
204 | |
205 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
206 | do { \ | |
332c1ce9 BH |
207 | if ((efx->state == STATE_RUNNING) || \ |
208 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
209 | ASSERT_RTNL(); \ |
210 | } while (0) | |
211 | ||
212 | /************************************************************************** | |
213 | * | |
214 | * Event queue processing | |
215 | * | |
216 | *************************************************************************/ | |
217 | ||
218 | /* Process channel's event queue | |
219 | * | |
220 | * This function is responsible for processing the event queue of a | |
221 | * single channel. The caller must guarantee that this function will | |
222 | * never be concurrently called more than once on the same channel, | |
223 | * though different channels may be being processed concurrently. | |
224 | */ | |
fa236e18 | 225 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 226 | { |
42cbe2d7 | 227 | struct efx_nic *efx = channel->efx; |
fa236e18 | 228 | int spent; |
8ceee660 | 229 | |
42cbe2d7 | 230 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 231 | !channel->enabled)) |
42cbe2d7 | 232 | return 0; |
8ceee660 | 233 | |
fa236e18 BH |
234 | spent = efx_nic_process_eventq(channel, budget); |
235 | if (spent == 0) | |
42cbe2d7 | 236 | return 0; |
8ceee660 BH |
237 | |
238 | /* Deliver last RX packet. */ | |
239 | if (channel->rx_pkt) { | |
240 | __efx_rx_packet(channel, channel->rx_pkt, | |
241 | channel->rx_pkt_csummed); | |
242 | channel->rx_pkt = NULL; | |
243 | } | |
244 | ||
8ceee660 BH |
245 | efx_rx_strategy(channel); |
246 | ||
f7d12cdc | 247 | efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); |
8ceee660 | 248 | |
fa236e18 | 249 | return spent; |
8ceee660 BH |
250 | } |
251 | ||
252 | /* Mark channel as finished processing | |
253 | * | |
254 | * Note that since we will not receive further interrupts for this | |
255 | * channel before we finish processing and call the eventq_read_ack() | |
256 | * method, there is no need to use the interrupt hold-off timers. | |
257 | */ | |
258 | static inline void efx_channel_processed(struct efx_channel *channel) | |
259 | { | |
5b9e207c BH |
260 | /* The interrupt handler for this channel may set work_pending |
261 | * as soon as we acknowledge the events we've seen. Make sure | |
262 | * it's cleared before then. */ | |
dc8cfa55 | 263 | channel->work_pending = false; |
5b9e207c BH |
264 | smp_wmb(); |
265 | ||
152b6a62 | 266 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
267 | } |
268 | ||
269 | /* NAPI poll handler | |
270 | * | |
271 | * NAPI guarantees serialisation of polls of the same device, which | |
272 | * provides the guarantee required by efx_process_channel(). | |
273 | */ | |
274 | static int efx_poll(struct napi_struct *napi, int budget) | |
275 | { | |
276 | struct efx_channel *channel = | |
277 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 278 | struct efx_nic *efx = channel->efx; |
fa236e18 | 279 | int spent; |
8ceee660 | 280 | |
62776d03 BH |
281 | netif_vdbg(efx, intr, efx->net_dev, |
282 | "channel %d NAPI poll executing on CPU %d\n", | |
283 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 284 | |
fa236e18 | 285 | spent = efx_process_channel(channel, budget); |
8ceee660 | 286 | |
fa236e18 | 287 | if (spent < budget) { |
a4900ac9 | 288 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
289 | efx->irq_rx_adaptive && |
290 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
291 | if (unlikely(channel->irq_mod_score < |
292 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
293 | if (channel->irq_moderation > 1) { |
294 | channel->irq_moderation -= 1; | |
ef2b90ee | 295 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 296 | } |
6fb70fd1 BH |
297 | } else if (unlikely(channel->irq_mod_score > |
298 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
299 | if (channel->irq_moderation < |
300 | efx->irq_rx_moderation) { | |
301 | channel->irq_moderation += 1; | |
ef2b90ee | 302 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 303 | } |
6fb70fd1 | 304 | } |
6fb70fd1 BH |
305 | channel->irq_count = 0; |
306 | channel->irq_mod_score = 0; | |
307 | } | |
308 | ||
8ceee660 | 309 | /* There is no race here; although napi_disable() will |
288379f0 | 310 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
311 | * since efx_channel_processed() will have no effect if |
312 | * interrupts have already been disabled. | |
313 | */ | |
288379f0 | 314 | napi_complete(napi); |
8ceee660 BH |
315 | efx_channel_processed(channel); |
316 | } | |
317 | ||
fa236e18 | 318 | return spent; |
8ceee660 BH |
319 | } |
320 | ||
321 | /* Process the eventq of the specified channel immediately on this CPU | |
322 | * | |
323 | * Disable hardware generated interrupts, wait for any existing | |
324 | * processing to finish, then directly poll (and ack ) the eventq. | |
325 | * Finally reenable NAPI and interrupts. | |
326 | * | |
327 | * Since we are touching interrupts the caller should hold the suspend lock | |
328 | */ | |
329 | void efx_process_channel_now(struct efx_channel *channel) | |
330 | { | |
331 | struct efx_nic *efx = channel->efx; | |
332 | ||
8313aca3 | 333 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 BH |
334 | BUG_ON(!channel->enabled); |
335 | ||
336 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 337 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
338 | if (efx->legacy_irq) |
339 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 340 | if (channel->irq) |
8ceee660 BH |
341 | synchronize_irq(channel->irq); |
342 | ||
343 | /* Wait for any NAPI processing to complete */ | |
344 | napi_disable(&channel->napi_str); | |
345 | ||
346 | /* Poll the channel */ | |
ecc910f5 | 347 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
348 | |
349 | /* Ack the eventq. This may cause an interrupt to be generated | |
350 | * when they are reenabled */ | |
351 | efx_channel_processed(channel); | |
352 | ||
353 | napi_enable(&channel->napi_str); | |
152b6a62 | 354 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
355 | } |
356 | ||
357 | /* Create event queue | |
358 | * Event queue memory allocations are done only once. If the channel | |
359 | * is reset, the memory buffer will be reused; this guards against | |
360 | * errors during channel reset and also simplifies interrupt handling. | |
361 | */ | |
362 | static int efx_probe_eventq(struct efx_channel *channel) | |
363 | { | |
ecc910f5 SH |
364 | struct efx_nic *efx = channel->efx; |
365 | unsigned long entries; | |
366 | ||
62776d03 BH |
367 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
368 | "chan %d create event queue\n", channel->channel); | |
8ceee660 | 369 | |
ecc910f5 SH |
370 | /* Build an event queue with room for one event per tx and rx buffer, |
371 | * plus some extra for link state events and MCDI completions. */ | |
372 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
373 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
374 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
375 | ||
152b6a62 | 376 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
377 | } |
378 | ||
379 | /* Prepare channel's event queue */ | |
bc3c90a2 | 380 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 381 | { |
62776d03 BH |
382 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
383 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
384 | |
385 | channel->eventq_read_ptr = 0; | |
386 | ||
152b6a62 | 387 | efx_nic_init_eventq(channel); |
8ceee660 BH |
388 | } |
389 | ||
390 | static void efx_fini_eventq(struct efx_channel *channel) | |
391 | { | |
62776d03 BH |
392 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
393 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 394 | |
152b6a62 | 395 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
396 | } |
397 | ||
398 | static void efx_remove_eventq(struct efx_channel *channel) | |
399 | { | |
62776d03 BH |
400 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
401 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 402 | |
152b6a62 | 403 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
404 | } |
405 | ||
406 | /************************************************************************** | |
407 | * | |
408 | * Channel handling | |
409 | * | |
410 | *************************************************************************/ | |
411 | ||
4642610c BH |
412 | /* Allocate and initialise a channel structure, optionally copying |
413 | * parameters (but not resources) from an old channel structure. */ | |
414 | static struct efx_channel * | |
415 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
416 | { | |
417 | struct efx_channel *channel; | |
418 | struct efx_rx_queue *rx_queue; | |
419 | struct efx_tx_queue *tx_queue; | |
420 | int j; | |
421 | ||
422 | if (old_channel) { | |
423 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); | |
424 | if (!channel) | |
425 | return NULL; | |
426 | ||
427 | *channel = *old_channel; | |
428 | ||
429 | memset(&channel->eventq, 0, sizeof(channel->eventq)); | |
430 | ||
431 | rx_queue = &channel->rx_queue; | |
432 | rx_queue->buffer = NULL; | |
433 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
434 | ||
435 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
436 | tx_queue = &channel->tx_queue[j]; | |
437 | if (tx_queue->channel) | |
438 | tx_queue->channel = channel; | |
439 | tx_queue->buffer = NULL; | |
440 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
441 | } | |
442 | } else { | |
443 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
444 | if (!channel) | |
445 | return NULL; | |
446 | ||
447 | channel->efx = efx; | |
448 | channel->channel = i; | |
449 | ||
450 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
451 | tx_queue = &channel->tx_queue[j]; | |
452 | tx_queue->efx = efx; | |
453 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
454 | tx_queue->channel = channel; | |
455 | } | |
456 | } | |
457 | ||
458 | spin_lock_init(&channel->tx_stop_lock); | |
459 | atomic_set(&channel->tx_stop_count, 1); | |
460 | ||
461 | rx_queue = &channel->rx_queue; | |
462 | rx_queue->efx = efx; | |
463 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
464 | (unsigned long)rx_queue); | |
465 | ||
466 | return channel; | |
467 | } | |
468 | ||
8ceee660 BH |
469 | static int efx_probe_channel(struct efx_channel *channel) |
470 | { | |
471 | struct efx_tx_queue *tx_queue; | |
472 | struct efx_rx_queue *rx_queue; | |
473 | int rc; | |
474 | ||
62776d03 BH |
475 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
476 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
477 | |
478 | rc = efx_probe_eventq(channel); | |
479 | if (rc) | |
480 | goto fail1; | |
481 | ||
482 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
483 | rc = efx_probe_tx_queue(tx_queue); | |
484 | if (rc) | |
485 | goto fail2; | |
486 | } | |
487 | ||
488 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
489 | rc = efx_probe_rx_queue(rx_queue); | |
490 | if (rc) | |
491 | goto fail3; | |
492 | } | |
493 | ||
494 | channel->n_rx_frm_trunc = 0; | |
495 | ||
496 | return 0; | |
497 | ||
498 | fail3: | |
499 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
500 | efx_remove_rx_queue(rx_queue); | |
501 | fail2: | |
502 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
503 | efx_remove_tx_queue(tx_queue); | |
504 | fail1: | |
505 | return rc; | |
506 | } | |
507 | ||
508 | ||
56536e9c BH |
509 | static void efx_set_channel_names(struct efx_nic *efx) |
510 | { | |
511 | struct efx_channel *channel; | |
512 | const char *type = ""; | |
513 | int number; | |
514 | ||
515 | efx_for_each_channel(channel, efx) { | |
516 | number = channel->channel; | |
a4900ac9 BH |
517 | if (efx->n_channels > efx->n_rx_channels) { |
518 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
519 | type = "-rx"; |
520 | } else { | |
521 | type = "-tx"; | |
a4900ac9 | 522 | number -= efx->n_rx_channels; |
56536e9c BH |
523 | } |
524 | } | |
4642610c BH |
525 | snprintf(efx->channel_name[channel->channel], |
526 | sizeof(efx->channel_name[0]), | |
56536e9c BH |
527 | "%s%s-%d", efx->name, type, number); |
528 | } | |
529 | } | |
530 | ||
4642610c BH |
531 | static int efx_probe_channels(struct efx_nic *efx) |
532 | { | |
533 | struct efx_channel *channel; | |
534 | int rc; | |
535 | ||
536 | /* Restart special buffer allocation */ | |
537 | efx->next_buffer_table = 0; | |
538 | ||
539 | efx_for_each_channel(channel, efx) { | |
540 | rc = efx_probe_channel(channel); | |
541 | if (rc) { | |
542 | netif_err(efx, probe, efx->net_dev, | |
543 | "failed to create channel %d\n", | |
544 | channel->channel); | |
545 | goto fail; | |
546 | } | |
547 | } | |
548 | efx_set_channel_names(efx); | |
549 | ||
550 | return 0; | |
551 | ||
552 | fail: | |
553 | efx_remove_channels(efx); | |
554 | return rc; | |
555 | } | |
556 | ||
8ceee660 BH |
557 | /* Channels are shutdown and reinitialised whilst the NIC is running |
558 | * to propagate configuration changes (mtu, checksum offload), or | |
559 | * to clear hardware error conditions | |
560 | */ | |
bc3c90a2 | 561 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
562 | { |
563 | struct efx_tx_queue *tx_queue; | |
564 | struct efx_rx_queue *rx_queue; | |
565 | struct efx_channel *channel; | |
8ceee660 | 566 | |
f7f13b0b BH |
567 | /* Calculate the rx buffer allocation parameters required to |
568 | * support the current MTU, including padding for header | |
569 | * alignment and overruns. | |
570 | */ | |
571 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
572 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 573 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 574 | efx->type->rx_buffer_padding); |
62b330ba SH |
575 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
576 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
577 | |
578 | /* Initialise the channels */ | |
579 | efx_for_each_channel(channel, efx) { | |
62776d03 BH |
580 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
581 | "init chan %d\n", channel->channel); | |
8ceee660 | 582 | |
bc3c90a2 | 583 | efx_init_eventq(channel); |
8ceee660 | 584 | |
bc3c90a2 BH |
585 | efx_for_each_channel_tx_queue(tx_queue, channel) |
586 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
587 | |
588 | /* The rx buffer allocation strategy is MTU dependent */ | |
589 | efx_rx_strategy(channel); | |
590 | ||
bc3c90a2 BH |
591 | efx_for_each_channel_rx_queue(rx_queue, channel) |
592 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
593 | |
594 | WARN_ON(channel->rx_pkt != NULL); | |
595 | efx_rx_strategy(channel); | |
596 | } | |
8ceee660 BH |
597 | } |
598 | ||
599 | /* This enables event queue processing and packet transmission. | |
600 | * | |
601 | * Note that this function is not allowed to fail, since that would | |
602 | * introduce too much complexity into the suspend/resume path. | |
603 | */ | |
604 | static void efx_start_channel(struct efx_channel *channel) | |
605 | { | |
606 | struct efx_rx_queue *rx_queue; | |
607 | ||
62776d03 BH |
608 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, |
609 | "starting chan %d\n", channel->channel); | |
8ceee660 | 610 | |
5b9e207c BH |
611 | /* The interrupt handler for this channel may set work_pending |
612 | * as soon as we enable it. Make sure it's cleared before | |
613 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
614 | channel->work_pending = false; |
615 | channel->enabled = true; | |
5b9e207c | 616 | smp_wmb(); |
8ceee660 | 617 | |
90d683af | 618 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
619 | efx_for_each_channel_rx_queue(rx_queue, channel) |
620 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
621 | |
622 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
623 | } |
624 | ||
625 | /* This disables event queue processing and packet transmission. | |
626 | * This function does not guarantee that all queue processing | |
627 | * (e.g. RX refill) is complete. | |
628 | */ | |
629 | static void efx_stop_channel(struct efx_channel *channel) | |
630 | { | |
8ceee660 BH |
631 | if (!channel->enabled) |
632 | return; | |
633 | ||
62776d03 BH |
634 | netif_dbg(channel->efx, ifdown, channel->efx->net_dev, |
635 | "stop chan %d\n", channel->channel); | |
8ceee660 | 636 | |
dc8cfa55 | 637 | channel->enabled = false; |
8ceee660 | 638 | napi_disable(&channel->napi_str); |
8ceee660 BH |
639 | } |
640 | ||
641 | static void efx_fini_channels(struct efx_nic *efx) | |
642 | { | |
643 | struct efx_channel *channel; | |
644 | struct efx_tx_queue *tx_queue; | |
645 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 646 | int rc; |
8ceee660 BH |
647 | |
648 | EFX_ASSERT_RESET_SERIALISED(efx); | |
649 | BUG_ON(efx->port_enabled); | |
650 | ||
152b6a62 | 651 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
652 | if (rc && EFX_WORKAROUND_7803(efx)) { |
653 | /* Schedule a reset to recover from the flush failure. The | |
654 | * descriptor caches reference memory we're about to free, | |
655 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
656 | * the MACs because of the pending reset. */ | |
62776d03 BH |
657 | netif_err(efx, drv, efx->net_dev, |
658 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
659 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
660 | } else if (rc) { | |
62776d03 | 661 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 662 | } else { |
62776d03 BH |
663 | netif_dbg(efx, drv, efx->net_dev, |
664 | "successfully flushed all queues\n"); | |
fd371e32 | 665 | } |
6bc5d3a9 | 666 | |
8ceee660 | 667 | efx_for_each_channel(channel, efx) { |
62776d03 BH |
668 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
669 | "shut down chan %d\n", channel->channel); | |
8ceee660 BH |
670 | |
671 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
672 | efx_fini_rx_queue(rx_queue); | |
673 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
674 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
675 | efx_fini_eventq(channel); |
676 | } | |
677 | } | |
678 | ||
679 | static void efx_remove_channel(struct efx_channel *channel) | |
680 | { | |
681 | struct efx_tx_queue *tx_queue; | |
682 | struct efx_rx_queue *rx_queue; | |
683 | ||
62776d03 BH |
684 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
685 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
686 | |
687 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
688 | efx_remove_rx_queue(rx_queue); | |
689 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
690 | efx_remove_tx_queue(tx_queue); | |
691 | efx_remove_eventq(channel); | |
8ceee660 BH |
692 | } |
693 | ||
4642610c BH |
694 | static void efx_remove_channels(struct efx_nic *efx) |
695 | { | |
696 | struct efx_channel *channel; | |
697 | ||
698 | efx_for_each_channel(channel, efx) | |
699 | efx_remove_channel(channel); | |
700 | } | |
701 | ||
702 | int | |
703 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
704 | { | |
705 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
706 | u32 old_rxq_entries, old_txq_entries; | |
707 | unsigned i; | |
708 | int rc; | |
709 | ||
710 | efx_stop_all(efx); | |
711 | efx_fini_channels(efx); | |
712 | ||
713 | /* Clone channels */ | |
714 | memset(other_channel, 0, sizeof(other_channel)); | |
715 | for (i = 0; i < efx->n_channels; i++) { | |
716 | channel = efx_alloc_channel(efx, i, efx->channel[i]); | |
717 | if (!channel) { | |
718 | rc = -ENOMEM; | |
719 | goto out; | |
720 | } | |
721 | other_channel[i] = channel; | |
722 | } | |
723 | ||
724 | /* Swap entry counts and channel pointers */ | |
725 | old_rxq_entries = efx->rxq_entries; | |
726 | old_txq_entries = efx->txq_entries; | |
727 | efx->rxq_entries = rxq_entries; | |
728 | efx->txq_entries = txq_entries; | |
729 | for (i = 0; i < efx->n_channels; i++) { | |
730 | channel = efx->channel[i]; | |
731 | efx->channel[i] = other_channel[i]; | |
732 | other_channel[i] = channel; | |
733 | } | |
734 | ||
735 | rc = efx_probe_channels(efx); | |
736 | if (rc) | |
737 | goto rollback; | |
738 | ||
739 | /* Destroy old channels */ | |
740 | for (i = 0; i < efx->n_channels; i++) | |
741 | efx_remove_channel(other_channel[i]); | |
742 | out: | |
743 | /* Free unused channel structures */ | |
744 | for (i = 0; i < efx->n_channels; i++) | |
745 | kfree(other_channel[i]); | |
746 | ||
747 | efx_init_channels(efx); | |
748 | efx_start_all(efx); | |
749 | return rc; | |
750 | ||
751 | rollback: | |
752 | /* Swap back */ | |
753 | efx->rxq_entries = old_rxq_entries; | |
754 | efx->txq_entries = old_txq_entries; | |
755 | for (i = 0; i < efx->n_channels; i++) { | |
756 | channel = efx->channel[i]; | |
757 | efx->channel[i] = other_channel[i]; | |
758 | other_channel[i] = channel; | |
759 | } | |
760 | goto out; | |
761 | } | |
762 | ||
90d683af | 763 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 764 | { |
90d683af | 765 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
766 | } |
767 | ||
768 | /************************************************************************** | |
769 | * | |
770 | * Port handling | |
771 | * | |
772 | **************************************************************************/ | |
773 | ||
774 | /* This ensures that the kernel is kept informed (via | |
775 | * netif_carrier_on/off) of the link status, and also maintains the | |
776 | * link status's stop on the port's TX queue. | |
777 | */ | |
fdaa9aed | 778 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 779 | { |
eb50c0d6 BH |
780 | struct efx_link_state *link_state = &efx->link_state; |
781 | ||
8ceee660 BH |
782 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
783 | * that no events are triggered between unregister_netdev() and the | |
784 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
785 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
786 | if (!netif_running(efx->net_dev)) | |
787 | return; | |
788 | ||
8c8661e4 BH |
789 | if (efx->port_inhibited) { |
790 | netif_carrier_off(efx->net_dev); | |
791 | return; | |
792 | } | |
793 | ||
eb50c0d6 | 794 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
795 | efx->n_link_state_changes++; |
796 | ||
eb50c0d6 | 797 | if (link_state->up) |
8ceee660 BH |
798 | netif_carrier_on(efx->net_dev); |
799 | else | |
800 | netif_carrier_off(efx->net_dev); | |
801 | } | |
802 | ||
803 | /* Status message for kernel log */ | |
eb50c0d6 | 804 | if (link_state->up) { |
62776d03 BH |
805 | netif_info(efx, link, efx->net_dev, |
806 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
807 | link_state->speed, link_state->fd ? "full" : "half", | |
808 | efx->net_dev->mtu, | |
809 | (efx->promiscuous ? " [PROMISC]" : "")); | |
8ceee660 | 810 | } else { |
62776d03 | 811 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
812 | } |
813 | ||
814 | } | |
815 | ||
d3245b28 BH |
816 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
817 | { | |
818 | efx->link_advertising = advertising; | |
819 | if (advertising) { | |
820 | if (advertising & ADVERTISED_Pause) | |
821 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
822 | else | |
823 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
824 | if (advertising & ADVERTISED_Asym_Pause) | |
825 | efx->wanted_fc ^= EFX_FC_TX; | |
826 | } | |
827 | } | |
828 | ||
829 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
830 | { | |
831 | efx->wanted_fc = wanted_fc; | |
832 | if (efx->link_advertising) { | |
833 | if (wanted_fc & EFX_FC_RX) | |
834 | efx->link_advertising |= (ADVERTISED_Pause | | |
835 | ADVERTISED_Asym_Pause); | |
836 | else | |
837 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
838 | ADVERTISED_Asym_Pause); | |
839 | if (wanted_fc & EFX_FC_TX) | |
840 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
841 | } | |
842 | } | |
843 | ||
115122af BH |
844 | static void efx_fini_port(struct efx_nic *efx); |
845 | ||
d3245b28 BH |
846 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
847 | * the MAC appropriately. All other PHY configuration changes are pushed | |
848 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
849 | * through efx_monitor(). | |
850 | * | |
851 | * Callers must hold the mac_lock | |
852 | */ | |
853 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 854 | { |
d3245b28 BH |
855 | enum efx_phy_mode phy_mode; |
856 | int rc; | |
8ceee660 | 857 | |
d3245b28 | 858 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 859 | |
a816f75a BH |
860 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
861 | if (efx_dev_registered(efx)) { | |
862 | netif_addr_lock_bh(efx->net_dev); | |
863 | netif_addr_unlock_bh(efx->net_dev); | |
864 | } | |
865 | ||
d3245b28 BH |
866 | /* Disable PHY transmit in mac level loopbacks */ |
867 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
868 | if (LOOPBACK_INTERNAL(efx)) |
869 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
870 | else | |
871 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 872 | |
d3245b28 | 873 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 874 | |
d3245b28 BH |
875 | if (rc) |
876 | efx->phy_mode = phy_mode; | |
177dfcd8 | 877 | |
d3245b28 | 878 | return rc; |
8ceee660 BH |
879 | } |
880 | ||
881 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
882 | * disabled. */ | |
d3245b28 | 883 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 884 | { |
d3245b28 BH |
885 | int rc; |
886 | ||
8ceee660 BH |
887 | EFX_ASSERT_RESET_SERIALISED(efx); |
888 | ||
889 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 890 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 891 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
892 | |
893 | return rc; | |
8ceee660 BH |
894 | } |
895 | ||
8be4f3e6 BH |
896 | /* Asynchronous work item for changing MAC promiscuity and multicast |
897 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
898 | * MAC directly. */ | |
766ca0fa BH |
899 | static void efx_mac_work(struct work_struct *data) |
900 | { | |
901 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
902 | ||
903 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 904 | if (efx->port_enabled) { |
ef2b90ee | 905 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
906 | efx->mac_op->reconfigure(efx); |
907 | } | |
766ca0fa BH |
908 | mutex_unlock(&efx->mac_lock); |
909 | } | |
910 | ||
8ceee660 BH |
911 | static int efx_probe_port(struct efx_nic *efx) |
912 | { | |
913 | int rc; | |
914 | ||
62776d03 | 915 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 916 | |
ff3b00a0 SH |
917 | if (phy_flash_cfg) |
918 | efx->phy_mode = PHY_MODE_SPECIAL; | |
919 | ||
ef2b90ee BH |
920 | /* Connect up MAC/PHY operations table */ |
921 | rc = efx->type->probe_port(efx); | |
8ceee660 | 922 | if (rc) |
e42de262 | 923 | return rc; |
8ceee660 BH |
924 | |
925 | /* Sanity check MAC address */ | |
926 | if (is_valid_ether_addr(efx->mac_address)) { | |
927 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
928 | } else { | |
62776d03 BH |
929 | netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n", |
930 | efx->mac_address); | |
8ceee660 BH |
931 | if (!allow_bad_hwaddr) { |
932 | rc = -EINVAL; | |
933 | goto err; | |
934 | } | |
935 | random_ether_addr(efx->net_dev->dev_addr); | |
62776d03 BH |
936 | netif_info(efx, probe, efx->net_dev, |
937 | "using locally-generated MAC %pM\n", | |
938 | efx->net_dev->dev_addr); | |
8ceee660 BH |
939 | } |
940 | ||
941 | return 0; | |
942 | ||
943 | err: | |
e42de262 | 944 | efx->type->remove_port(efx); |
8ceee660 BH |
945 | return rc; |
946 | } | |
947 | ||
948 | static int efx_init_port(struct efx_nic *efx) | |
949 | { | |
950 | int rc; | |
951 | ||
62776d03 | 952 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 953 | |
1dfc5cea BH |
954 | mutex_lock(&efx->mac_lock); |
955 | ||
177dfcd8 | 956 | rc = efx->phy_op->init(efx); |
8ceee660 | 957 | if (rc) |
1dfc5cea | 958 | goto fail1; |
8ceee660 | 959 | |
dc8cfa55 | 960 | efx->port_initialized = true; |
1dfc5cea | 961 | |
d3245b28 BH |
962 | /* Reconfigure the MAC before creating dma queues (required for |
963 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
964 | efx->mac_op->reconfigure(efx); | |
965 | ||
966 | /* Ensure the PHY advertises the correct flow control settings */ | |
967 | rc = efx->phy_op->reconfigure(efx); | |
968 | if (rc) | |
969 | goto fail2; | |
970 | ||
1dfc5cea | 971 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 972 | return 0; |
177dfcd8 | 973 | |
1dfc5cea | 974 | fail2: |
177dfcd8 | 975 | efx->phy_op->fini(efx); |
1dfc5cea BH |
976 | fail1: |
977 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 978 | return rc; |
8ceee660 BH |
979 | } |
980 | ||
8ceee660 BH |
981 | static void efx_start_port(struct efx_nic *efx) |
982 | { | |
62776d03 | 983 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
984 | BUG_ON(efx->port_enabled); |
985 | ||
986 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 987 | efx->port_enabled = true; |
8be4f3e6 BH |
988 | |
989 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
990 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 991 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
992 | efx->mac_op->reconfigure(efx); |
993 | ||
8ceee660 BH |
994 | mutex_unlock(&efx->mac_lock); |
995 | } | |
996 | ||
fdaa9aed | 997 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
998 | static void efx_stop_port(struct efx_nic *efx) |
999 | { | |
62776d03 | 1000 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1001 | |
1002 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1003 | efx->port_enabled = false; |
8ceee660 BH |
1004 | mutex_unlock(&efx->mac_lock); |
1005 | ||
1006 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 1007 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
1008 | netif_addr_lock_bh(efx->net_dev); |
1009 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1010 | } |
1011 | } | |
1012 | ||
1013 | static void efx_fini_port(struct efx_nic *efx) | |
1014 | { | |
62776d03 | 1015 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1016 | |
1017 | if (!efx->port_initialized) | |
1018 | return; | |
1019 | ||
177dfcd8 | 1020 | efx->phy_op->fini(efx); |
dc8cfa55 | 1021 | efx->port_initialized = false; |
8ceee660 | 1022 | |
eb50c0d6 | 1023 | efx->link_state.up = false; |
8ceee660 BH |
1024 | efx_link_status_changed(efx); |
1025 | } | |
1026 | ||
1027 | static void efx_remove_port(struct efx_nic *efx) | |
1028 | { | |
62776d03 | 1029 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1030 | |
ef2b90ee | 1031 | efx->type->remove_port(efx); |
8ceee660 BH |
1032 | } |
1033 | ||
1034 | /************************************************************************** | |
1035 | * | |
1036 | * NIC handling | |
1037 | * | |
1038 | **************************************************************************/ | |
1039 | ||
1040 | /* This configures the PCI device to enable I/O and DMA. */ | |
1041 | static int efx_init_io(struct efx_nic *efx) | |
1042 | { | |
1043 | struct pci_dev *pci_dev = efx->pci_dev; | |
1044 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
1045 | int rc; | |
1046 | ||
62776d03 | 1047 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1048 | |
1049 | rc = pci_enable_device(pci_dev); | |
1050 | if (rc) { | |
62776d03 BH |
1051 | netif_err(efx, probe, efx->net_dev, |
1052 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1053 | goto fail1; |
1054 | } | |
1055 | ||
1056 | pci_set_master(pci_dev); | |
1057 | ||
1058 | /* Set the PCI DMA mask. Try all possibilities from our | |
1059 | * genuine mask down to 32 bits, because some architectures | |
1060 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1061 | * masks event though they reject 46 bit masks. | |
1062 | */ | |
1063 | while (dma_mask > 0x7fffffffUL) { | |
1064 | if (pci_dma_supported(pci_dev, dma_mask) && | |
1065 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
1066 | break; | |
1067 | dma_mask >>= 1; | |
1068 | } | |
1069 | if (rc) { | |
62776d03 BH |
1070 | netif_err(efx, probe, efx->net_dev, |
1071 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1072 | goto fail2; |
1073 | } | |
62776d03 BH |
1074 | netif_dbg(efx, probe, efx->net_dev, |
1075 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1076 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1077 | if (rc) { | |
1078 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1079 | * fail with a mask that pci_set_dma_mask() accepted, | |
1080 | * but just in case... | |
1081 | */ | |
62776d03 BH |
1082 | netif_err(efx, probe, efx->net_dev, |
1083 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1084 | goto fail2; |
1085 | } | |
1086 | ||
dc803df8 BH |
1087 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1088 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1089 | if (rc) { |
62776d03 BH |
1090 | netif_err(efx, probe, efx->net_dev, |
1091 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1092 | rc = -EIO; |
1093 | goto fail3; | |
1094 | } | |
1095 | efx->membase = ioremap_nocache(efx->membase_phys, | |
1096 | efx->type->mem_map_size); | |
1097 | if (!efx->membase) { | |
62776d03 BH |
1098 | netif_err(efx, probe, efx->net_dev, |
1099 | "could not map memory BAR at %llx+%x\n", | |
1100 | (unsigned long long)efx->membase_phys, | |
1101 | efx->type->mem_map_size); | |
8ceee660 BH |
1102 | rc = -ENOMEM; |
1103 | goto fail4; | |
1104 | } | |
62776d03 BH |
1105 | netif_dbg(efx, probe, efx->net_dev, |
1106 | "memory BAR at %llx+%x (virtual %p)\n", | |
1107 | (unsigned long long)efx->membase_phys, | |
1108 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1109 | |
1110 | return 0; | |
1111 | ||
1112 | fail4: | |
dc803df8 | 1113 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1114 | fail3: |
2c118e0f | 1115 | efx->membase_phys = 0; |
8ceee660 BH |
1116 | fail2: |
1117 | pci_disable_device(efx->pci_dev); | |
1118 | fail1: | |
1119 | return rc; | |
1120 | } | |
1121 | ||
1122 | static void efx_fini_io(struct efx_nic *efx) | |
1123 | { | |
62776d03 | 1124 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1125 | |
1126 | if (efx->membase) { | |
1127 | iounmap(efx->membase); | |
1128 | efx->membase = NULL; | |
1129 | } | |
1130 | ||
1131 | if (efx->membase_phys) { | |
dc803df8 | 1132 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1133 | efx->membase_phys = 0; |
8ceee660 BH |
1134 | } |
1135 | ||
1136 | pci_disable_device(efx->pci_dev); | |
1137 | } | |
1138 | ||
a4900ac9 BH |
1139 | /* Get number of channels wanted. Each channel will have its own IRQ, |
1140 | * 1 RX queue and/or 2 TX queues. */ | |
1141 | static int efx_wanted_channels(void) | |
46123d04 | 1142 | { |
2f8975fb | 1143 | cpumask_var_t core_mask; |
46123d04 BH |
1144 | int count; |
1145 | int cpu; | |
1146 | ||
79f55997 | 1147 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 1148 | printk(KERN_WARNING |
3977d033 | 1149 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1150 | return 1; |
1151 | } | |
1152 | ||
46123d04 BH |
1153 | count = 0; |
1154 | for_each_online_cpu(cpu) { | |
2f8975fb | 1155 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 1156 | ++count; |
2f8975fb | 1157 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 1158 | topology_core_cpumask(cpu)); |
46123d04 BH |
1159 | } |
1160 | } | |
1161 | ||
2f8975fb | 1162 | free_cpumask_var(core_mask); |
46123d04 BH |
1163 | return count; |
1164 | } | |
1165 | ||
1166 | /* Probe the number and type of interrupts we are able to obtain, and | |
1167 | * the resulting numbers of channels and RX queues. | |
1168 | */ | |
8ceee660 BH |
1169 | static void efx_probe_interrupts(struct efx_nic *efx) |
1170 | { | |
46123d04 BH |
1171 | int max_channels = |
1172 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1173 | int rc, i; |
1174 | ||
1175 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1176 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1177 | int n_channels; |
aa6ef27e | 1178 | |
a4900ac9 BH |
1179 | n_channels = efx_wanted_channels(); |
1180 | if (separate_tx_channels) | |
1181 | n_channels *= 2; | |
1182 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1183 | |
a4900ac9 | 1184 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1185 | xentries[i].entry = i; |
a4900ac9 | 1186 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1187 | if (rc > 0) { |
62776d03 BH |
1188 | netif_err(efx, drv, efx->net_dev, |
1189 | "WARNING: Insufficient MSI-X vectors" | |
1190 | " available (%d < %d).\n", rc, n_channels); | |
1191 | netif_err(efx, drv, efx->net_dev, | |
1192 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1193 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1194 | n_channels = rc; | |
8ceee660 | 1195 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1196 | n_channels); |
8ceee660 BH |
1197 | } |
1198 | ||
1199 | if (rc == 0) { | |
a4900ac9 BH |
1200 | efx->n_channels = n_channels; |
1201 | if (separate_tx_channels) { | |
1202 | efx->n_tx_channels = | |
1203 | max(efx->n_channels / 2, 1U); | |
1204 | efx->n_rx_channels = | |
1205 | max(efx->n_channels - | |
1206 | efx->n_tx_channels, 1U); | |
1207 | } else { | |
1208 | efx->n_tx_channels = efx->n_channels; | |
1209 | efx->n_rx_channels = efx->n_channels; | |
1210 | } | |
1211 | for (i = 0; i < n_channels; i++) | |
f7d12cdc BH |
1212 | efx_get_channel(efx, i)->irq = |
1213 | xentries[i].vector; | |
8ceee660 BH |
1214 | } else { |
1215 | /* Fall back to single channel MSI */ | |
1216 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1217 | netif_err(efx, drv, efx->net_dev, |
1218 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1219 | } |
1220 | } | |
1221 | ||
1222 | /* Try single interrupt MSI */ | |
1223 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1224 | efx->n_channels = 1; |
a4900ac9 BH |
1225 | efx->n_rx_channels = 1; |
1226 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1227 | rc = pci_enable_msi(efx->pci_dev); |
1228 | if (rc == 0) { | |
f7d12cdc | 1229 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1230 | } else { |
62776d03 BH |
1231 | netif_err(efx, drv, efx->net_dev, |
1232 | "could not enable MSI\n"); | |
8ceee660 BH |
1233 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1234 | } | |
1235 | } | |
1236 | ||
1237 | /* Assume legacy interrupts */ | |
1238 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1239 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1240 | efx->n_rx_channels = 1; |
1241 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1242 | efx->legacy_irq = efx->pci_dev->irq; |
1243 | } | |
1244 | } | |
1245 | ||
1246 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1247 | { | |
1248 | struct efx_channel *channel; | |
1249 | ||
1250 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1251 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1252 | channel->irq = 0; |
1253 | pci_disable_msi(efx->pci_dev); | |
1254 | pci_disable_msix(efx->pci_dev); | |
1255 | ||
1256 | /* Remove legacy interrupt */ | |
1257 | efx->legacy_irq = 0; | |
1258 | } | |
1259 | ||
8313aca3 BH |
1260 | struct efx_tx_queue * |
1261 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) | |
1262 | { | |
1263 | unsigned tx_channel_offset = | |
1264 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
1265 | EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || | |
1266 | type >= EFX_TXQ_TYPES); | |
1267 | return &efx->channel[tx_channel_offset + index]->tx_queue[type]; | |
1268 | } | |
1269 | ||
8831da7b | 1270 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1271 | { |
a4900ac9 | 1272 | struct efx_channel *channel; |
8ceee660 | 1273 | struct efx_tx_queue *tx_queue; |
a4900ac9 BH |
1274 | unsigned tx_channel_offset = |
1275 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
8ceee660 | 1276 | |
8313aca3 BH |
1277 | /* Channel pointers were set in efx_init_struct() but we now |
1278 | * need to clear them for TX queues in any RX-only channels. */ | |
a4900ac9 | 1279 | efx_for_each_channel(channel, efx) { |
8313aca3 BH |
1280 | if (channel->channel - tx_channel_offset >= |
1281 | efx->n_tx_channels) { | |
a4900ac9 | 1282 | efx_for_each_channel_tx_queue(tx_queue, channel) |
8313aca3 | 1283 | tx_queue->channel = NULL; |
a4900ac9 | 1284 | } |
60ac1065 | 1285 | } |
8ceee660 BH |
1286 | } |
1287 | ||
1288 | static int efx_probe_nic(struct efx_nic *efx) | |
1289 | { | |
765c9f46 | 1290 | size_t i; |
8ceee660 BH |
1291 | int rc; |
1292 | ||
62776d03 | 1293 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1294 | |
1295 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1296 | rc = efx->type->probe(efx); |
8ceee660 BH |
1297 | if (rc) |
1298 | return rc; | |
1299 | ||
a4900ac9 | 1300 | /* Determine the number of channels and queues by trying to hook |
8ceee660 BH |
1301 | * in MSI-X interrupts. */ |
1302 | efx_probe_interrupts(efx); | |
1303 | ||
5d3a6fca BH |
1304 | if (efx->n_channels > 1) |
1305 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 BH |
1306 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
1307 | efx->rx_indir_table[i] = i % efx->n_rx_channels; | |
5d3a6fca | 1308 | |
8831da7b | 1309 | efx_set_channels(efx); |
c4f4adc7 BH |
1310 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1311 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1312 | |
1313 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1314 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1315 | |
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | static void efx_remove_nic(struct efx_nic *efx) | |
1320 | { | |
62776d03 | 1321 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1322 | |
1323 | efx_remove_interrupts(efx); | |
ef2b90ee | 1324 | efx->type->remove(efx); |
8ceee660 BH |
1325 | } |
1326 | ||
1327 | /************************************************************************** | |
1328 | * | |
1329 | * NIC startup/shutdown | |
1330 | * | |
1331 | *************************************************************************/ | |
1332 | ||
1333 | static int efx_probe_all(struct efx_nic *efx) | |
1334 | { | |
8ceee660 BH |
1335 | int rc; |
1336 | ||
8ceee660 BH |
1337 | rc = efx_probe_nic(efx); |
1338 | if (rc) { | |
62776d03 | 1339 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1340 | goto fail1; |
1341 | } | |
1342 | ||
8ceee660 BH |
1343 | rc = efx_probe_port(efx); |
1344 | if (rc) { | |
62776d03 | 1345 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1346 | goto fail2; |
1347 | } | |
1348 | ||
ecc910f5 | 1349 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
4642610c BH |
1350 | rc = efx_probe_channels(efx); |
1351 | if (rc) | |
1352 | goto fail3; | |
8ceee660 | 1353 | |
64eebcfd BH |
1354 | rc = efx_probe_filters(efx); |
1355 | if (rc) { | |
1356 | netif_err(efx, probe, efx->net_dev, | |
1357 | "failed to create filter tables\n"); | |
1358 | goto fail4; | |
1359 | } | |
1360 | ||
8ceee660 BH |
1361 | return 0; |
1362 | ||
64eebcfd BH |
1363 | fail4: |
1364 | efx_remove_channels(efx); | |
8ceee660 | 1365 | fail3: |
8ceee660 BH |
1366 | efx_remove_port(efx); |
1367 | fail2: | |
1368 | efx_remove_nic(efx); | |
1369 | fail1: | |
1370 | return rc; | |
1371 | } | |
1372 | ||
1373 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1374 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1375 | * and ensures that the port is scheduled to be reconfigured. | |
1376 | * This function is safe to call multiple times when the NIC is in any | |
1377 | * state. */ | |
1378 | static void efx_start_all(struct efx_nic *efx) | |
1379 | { | |
1380 | struct efx_channel *channel; | |
1381 | ||
1382 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1383 | ||
1384 | /* Check that it is appropriate to restart the interface. All | |
1385 | * of these flags are safe to read under just the rtnl lock */ | |
1386 | if (efx->port_enabled) | |
1387 | return; | |
1388 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1389 | return; | |
55668611 | 1390 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1391 | return; |
1392 | ||
1393 | /* Mark the port as enabled so port reconfigurations can start, then | |
1394 | * restart the transmit interface early so the watchdog timer stops */ | |
1395 | efx_start_port(efx); | |
8ceee660 | 1396 | |
a4900ac9 BH |
1397 | efx_for_each_channel(channel, efx) { |
1398 | if (efx_dev_registered(efx)) | |
1399 | efx_wake_queue(channel); | |
8ceee660 | 1400 | efx_start_channel(channel); |
a4900ac9 | 1401 | } |
8ceee660 | 1402 | |
152b6a62 | 1403 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1404 | |
8880f4ec BH |
1405 | /* Switch to event based MCDI completions after enabling interrupts. |
1406 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1407 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1408 | * reset_pending [modified from an atomic context], we instead guarantee | |
1409 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1410 | efx_mcdi_mode_event(efx); | |
1411 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1412 | efx_mcdi_mode_poll(efx); | |
1413 | ||
78c1f0a0 SH |
1414 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1415 | * event driven), we have to poll the PHY because after an event queue | |
1416 | * flush, we could have a missed a link state change */ | |
1417 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1418 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1419 | efx_monitor_interval); | |
78c1f0a0 SH |
1420 | } else { |
1421 | mutex_lock(&efx->mac_lock); | |
1422 | if (efx->phy_op->poll(efx)) | |
1423 | efx_link_status_changed(efx); | |
1424 | mutex_unlock(&efx->mac_lock); | |
1425 | } | |
55edc6e6 | 1426 | |
ef2b90ee | 1427 | efx->type->start_stats(efx); |
8ceee660 BH |
1428 | } |
1429 | ||
1430 | /* Flush all delayed work. Should only be called when no more delayed work | |
1431 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1432 | * since we're holding the rtnl_lock at this point. */ | |
1433 | static void efx_flush_all(struct efx_nic *efx) | |
1434 | { | |
8ceee660 BH |
1435 | /* Make sure the hardware monitor is stopped */ |
1436 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1437 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1438 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1439 | } |
1440 | ||
1441 | /* Quiesce hardware and software without bringing the link down. | |
1442 | * Safe to call multiple times, when the nic and interface is in any | |
1443 | * state. The caller is guaranteed to subsequently be in a position | |
1444 | * to modify any hardware and software state they see fit without | |
1445 | * taking locks. */ | |
1446 | static void efx_stop_all(struct efx_nic *efx) | |
1447 | { | |
1448 | struct efx_channel *channel; | |
1449 | ||
1450 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1451 | ||
1452 | /* port_enabled can be read safely under the rtnl lock */ | |
1453 | if (!efx->port_enabled) | |
1454 | return; | |
1455 | ||
ef2b90ee | 1456 | efx->type->stop_stats(efx); |
55edc6e6 | 1457 | |
8880f4ec BH |
1458 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1459 | efx_mcdi_mode_poll(efx); | |
1460 | ||
8ceee660 | 1461 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1462 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
1463 | if (efx->legacy_irq) |
1464 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1465 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1466 | if (channel->irq) |
1467 | synchronize_irq(channel->irq); | |
b3475645 | 1468 | } |
8ceee660 BH |
1469 | |
1470 | /* Stop all NAPI processing and synchronous rx refills */ | |
1471 | efx_for_each_channel(channel, efx) | |
1472 | efx_stop_channel(channel); | |
1473 | ||
1474 | /* Stop all asynchronous port reconfigurations. Since all | |
1475 | * event processing has already been stopped, there is no | |
1476 | * window to loose phy events */ | |
1477 | efx_stop_port(efx); | |
1478 | ||
fdaa9aed | 1479 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1480 | efx_flush_all(efx); |
1481 | ||
8ceee660 BH |
1482 | /* Stop the kernel transmit interface late, so the watchdog |
1483 | * timer isn't ticking over the flush */ | |
55668611 | 1484 | if (efx_dev_registered(efx)) { |
a4900ac9 BH |
1485 | struct efx_channel *channel; |
1486 | efx_for_each_channel(channel, efx) | |
1487 | efx_stop_queue(channel); | |
8ceee660 BH |
1488 | netif_tx_lock_bh(efx->net_dev); |
1489 | netif_tx_unlock_bh(efx->net_dev); | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | static void efx_remove_all(struct efx_nic *efx) | |
1494 | { | |
64eebcfd | 1495 | efx_remove_filters(efx); |
4642610c | 1496 | efx_remove_channels(efx); |
8ceee660 BH |
1497 | efx_remove_port(efx); |
1498 | efx_remove_nic(efx); | |
1499 | } | |
1500 | ||
8ceee660 BH |
1501 | /************************************************************************** |
1502 | * | |
1503 | * Interrupt moderation | |
1504 | * | |
1505 | **************************************************************************/ | |
1506 | ||
0d86ebd8 BH |
1507 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1508 | { | |
1509 | if (usecs <= 0) | |
1510 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1511 | if (usecs < resolution) | |
1512 | return 1; /* never round down to 0 */ | |
1513 | return usecs / resolution; | |
1514 | } | |
1515 | ||
8ceee660 | 1516 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1517 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1518 | bool rx_adaptive) | |
8ceee660 | 1519 | { |
f7d12cdc | 1520 | struct efx_channel *channel; |
152b6a62 BH |
1521 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1522 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1523 | |
1524 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1525 | ||
6fb70fd1 | 1526 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1527 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc BH |
1528 | efx_for_each_channel(channel, efx) { |
1529 | if (efx_channel_get_rx_queue(channel)) | |
1530 | channel->irq_moderation = rx_ticks; | |
1531 | else if (efx_channel_get_tx_queue(channel, 0)) | |
1532 | channel->irq_moderation = tx_ticks; | |
1533 | } | |
8ceee660 BH |
1534 | } |
1535 | ||
1536 | /************************************************************************** | |
1537 | * | |
1538 | * Hardware monitor | |
1539 | * | |
1540 | **************************************************************************/ | |
1541 | ||
e254c274 | 1542 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1543 | static void efx_monitor(struct work_struct *data) |
1544 | { | |
1545 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1546 | monitor_work.work); | |
8ceee660 | 1547 | |
62776d03 BH |
1548 | netif_vdbg(efx, timer, efx->net_dev, |
1549 | "hardware monitor executing on CPU %d\n", | |
1550 | raw_smp_processor_id()); | |
ef2b90ee | 1551 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1552 | |
8ceee660 BH |
1553 | /* If the mac_lock is already held then it is likely a port |
1554 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1555 | * most of the work of monitor() anyway. */ |
1556 | if (mutex_trylock(&efx->mac_lock)) { | |
1557 | if (efx->port_enabled) | |
1558 | efx->type->monitor(efx); | |
1559 | mutex_unlock(&efx->mac_lock); | |
1560 | } | |
8ceee660 | 1561 | |
8ceee660 BH |
1562 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1563 | efx_monitor_interval); | |
1564 | } | |
1565 | ||
1566 | /************************************************************************** | |
1567 | * | |
1568 | * ioctls | |
1569 | * | |
1570 | *************************************************************************/ | |
1571 | ||
1572 | /* Net device ioctl | |
1573 | * Context: process, rtnl_lock() held. | |
1574 | */ | |
1575 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1576 | { | |
767e468c | 1577 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1578 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1579 | |
1580 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1581 | ||
68e7f45e BH |
1582 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1583 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1584 | (data->phy_id & 0xfc00) == 0x0400) | |
1585 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1586 | ||
1587 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1588 | } |
1589 | ||
1590 | /************************************************************************** | |
1591 | * | |
1592 | * NAPI interface | |
1593 | * | |
1594 | **************************************************************************/ | |
1595 | ||
1596 | static int efx_init_napi(struct efx_nic *efx) | |
1597 | { | |
1598 | struct efx_channel *channel; | |
8ceee660 BH |
1599 | |
1600 | efx_for_each_channel(channel, efx) { | |
1601 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1602 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1603 | efx_poll, napi_weight); | |
8ceee660 BH |
1604 | } |
1605 | return 0; | |
8ceee660 BH |
1606 | } |
1607 | ||
1608 | static void efx_fini_napi(struct efx_nic *efx) | |
1609 | { | |
1610 | struct efx_channel *channel; | |
1611 | ||
1612 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1613 | if (channel->napi_dev) |
1614 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1615 | channel->napi_dev = NULL; |
1616 | } | |
1617 | } | |
1618 | ||
1619 | /************************************************************************** | |
1620 | * | |
1621 | * Kernel netpoll interface | |
1622 | * | |
1623 | *************************************************************************/ | |
1624 | ||
1625 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1626 | ||
1627 | /* Although in the common case interrupts will be disabled, this is not | |
1628 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1629 | * so no locking is required. | |
1630 | */ | |
1631 | static void efx_netpoll(struct net_device *net_dev) | |
1632 | { | |
767e468c | 1633 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1634 | struct efx_channel *channel; |
1635 | ||
64ee3120 | 1636 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1637 | efx_schedule_channel(channel); |
1638 | } | |
1639 | ||
1640 | #endif | |
1641 | ||
1642 | /************************************************************************** | |
1643 | * | |
1644 | * Kernel net device interface | |
1645 | * | |
1646 | *************************************************************************/ | |
1647 | ||
1648 | /* Context: process, rtnl_lock() held. */ | |
1649 | static int efx_net_open(struct net_device *net_dev) | |
1650 | { | |
767e468c | 1651 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1652 | EFX_ASSERT_RESET_SERIALISED(efx); |
1653 | ||
62776d03 BH |
1654 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1655 | raw_smp_processor_id()); | |
8ceee660 | 1656 | |
f4bd954e BH |
1657 | if (efx->state == STATE_DISABLED) |
1658 | return -EIO; | |
f8b87c17 BH |
1659 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1660 | return -EBUSY; | |
8880f4ec BH |
1661 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1662 | return -EIO; | |
f8b87c17 | 1663 | |
78c1f0a0 SH |
1664 | /* Notify the kernel of the link state polled during driver load, |
1665 | * before the monitor starts running */ | |
1666 | efx_link_status_changed(efx); | |
1667 | ||
8ceee660 BH |
1668 | efx_start_all(efx); |
1669 | return 0; | |
1670 | } | |
1671 | ||
1672 | /* Context: process, rtnl_lock() held. | |
1673 | * Note that the kernel will ignore our return code; this method | |
1674 | * should really be a void. | |
1675 | */ | |
1676 | static int efx_net_stop(struct net_device *net_dev) | |
1677 | { | |
767e468c | 1678 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1679 | |
62776d03 BH |
1680 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1681 | raw_smp_processor_id()); | |
8ceee660 | 1682 | |
f4bd954e BH |
1683 | if (efx->state != STATE_DISABLED) { |
1684 | /* Stop the device and flush all the channels */ | |
1685 | efx_stop_all(efx); | |
1686 | efx_fini_channels(efx); | |
1687 | efx_init_channels(efx); | |
1688 | } | |
8ceee660 BH |
1689 | |
1690 | return 0; | |
1691 | } | |
1692 | ||
5b9e207c | 1693 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
28172739 | 1694 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats) |
8ceee660 | 1695 | { |
767e468c | 1696 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1697 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1698 | |
55edc6e6 | 1699 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1700 | efx->type->update_stats(efx); |
55edc6e6 | 1701 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1702 | |
1703 | stats->rx_packets = mac_stats->rx_packets; | |
1704 | stats->tx_packets = mac_stats->tx_packets; | |
1705 | stats->rx_bytes = mac_stats->rx_bytes; | |
1706 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1707 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1708 | stats->multicast = mac_stats->rx_multicast; |
1709 | stats->collisions = mac_stats->tx_collision; | |
1710 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1711 | mac_stats->rx_length_error); | |
8ceee660 BH |
1712 | stats->rx_crc_errors = mac_stats->rx_bad; |
1713 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1714 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1715 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1716 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1717 | ||
1718 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1719 | stats->rx_crc_errors + |
1720 | stats->rx_frame_errors + | |
8ceee660 BH |
1721 | mac_stats->rx_symbol_error); |
1722 | stats->tx_errors = (stats->tx_window_errors + | |
1723 | mac_stats->tx_bad); | |
1724 | ||
1725 | return stats; | |
1726 | } | |
1727 | ||
1728 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1729 | static void efx_watchdog(struct net_device *net_dev) | |
1730 | { | |
767e468c | 1731 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1732 | |
62776d03 BH |
1733 | netif_err(efx, tx_err, efx->net_dev, |
1734 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1735 | efx->port_enabled); | |
8ceee660 | 1736 | |
739bb23d | 1737 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1738 | } |
1739 | ||
1740 | ||
1741 | /* Context: process, rtnl_lock() held. */ | |
1742 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1743 | { | |
767e468c | 1744 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1745 | int rc = 0; |
1746 | ||
1747 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1748 | ||
1749 | if (new_mtu > EFX_MAX_MTU) | |
1750 | return -EINVAL; | |
1751 | ||
1752 | efx_stop_all(efx); | |
1753 | ||
62776d03 | 1754 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 BH |
1755 | |
1756 | efx_fini_channels(efx); | |
d3245b28 BH |
1757 | |
1758 | mutex_lock(&efx->mac_lock); | |
1759 | /* Reconfigure the MAC before enabling the dma queues so that | |
1760 | * the RX buffers don't overflow */ | |
8ceee660 | 1761 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1762 | efx->mac_op->reconfigure(efx); |
1763 | mutex_unlock(&efx->mac_lock); | |
1764 | ||
bc3c90a2 | 1765 | efx_init_channels(efx); |
8ceee660 BH |
1766 | |
1767 | efx_start_all(efx); | |
1768 | return rc; | |
8ceee660 BH |
1769 | } |
1770 | ||
1771 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1772 | { | |
767e468c | 1773 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1774 | struct sockaddr *addr = data; |
1775 | char *new_addr = addr->sa_data; | |
1776 | ||
1777 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1778 | ||
1779 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1780 | netif_err(efx, drv, efx->net_dev, |
1781 | "invalid ethernet MAC address requested: %pM\n", | |
1782 | new_addr); | |
8ceee660 BH |
1783 | return -EINVAL; |
1784 | } | |
1785 | ||
1786 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1787 | ||
1788 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1789 | mutex_lock(&efx->mac_lock); |
1790 | efx->mac_op->reconfigure(efx); | |
1791 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1792 | |
1793 | return 0; | |
1794 | } | |
1795 | ||
a816f75a | 1796 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1797 | static void efx_set_multicast_list(struct net_device *net_dev) |
1798 | { | |
767e468c | 1799 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1800 | struct netdev_hw_addr *ha; |
8ceee660 | 1801 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1802 | u32 crc; |
1803 | int bit; | |
8ceee660 | 1804 | |
8be4f3e6 | 1805 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1806 | |
1807 | /* Build multicast hash table */ | |
8be4f3e6 | 1808 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1809 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1810 | } else { | |
1811 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1812 | netdev_for_each_mc_addr(ha, net_dev) { |
1813 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1814 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1815 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1816 | } |
8ceee660 | 1817 | |
8be4f3e6 BH |
1818 | /* Broadcast packets go through the multicast hash filter. |
1819 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1820 | * so we always add bit 0xff to the mask. | |
1821 | */ | |
1822 | set_bit_le(0xff, mc_hash->byte); | |
1823 | } | |
a816f75a | 1824 | |
8be4f3e6 BH |
1825 | if (efx->port_enabled) |
1826 | queue_work(efx->workqueue, &efx->mac_work); | |
1827 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1828 | } |
1829 | ||
c3ecb9f3 SH |
1830 | static const struct net_device_ops efx_netdev_ops = { |
1831 | .ndo_open = efx_net_open, | |
1832 | .ndo_stop = efx_net_stop, | |
4472702e | 1833 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1834 | .ndo_tx_timeout = efx_watchdog, |
1835 | .ndo_start_xmit = efx_hard_start_xmit, | |
1836 | .ndo_validate_addr = eth_validate_addr, | |
1837 | .ndo_do_ioctl = efx_ioctl, | |
1838 | .ndo_change_mtu = efx_change_mtu, | |
1839 | .ndo_set_mac_address = efx_set_mac_address, | |
1840 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1841 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1842 | .ndo_poll_controller = efx_netpoll, | |
1843 | #endif | |
1844 | }; | |
1845 | ||
7dde596e BH |
1846 | static void efx_update_name(struct efx_nic *efx) |
1847 | { | |
1848 | strcpy(efx->name, efx->net_dev->name); | |
1849 | efx_mtd_rename(efx); | |
1850 | efx_set_channel_names(efx); | |
1851 | } | |
1852 | ||
8ceee660 BH |
1853 | static int efx_netdev_event(struct notifier_block *this, |
1854 | unsigned long event, void *ptr) | |
1855 | { | |
d3208b5e | 1856 | struct net_device *net_dev = ptr; |
8ceee660 | 1857 | |
7dde596e BH |
1858 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1859 | event == NETDEV_CHANGENAME) | |
1860 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1861 | |
1862 | return NOTIFY_DONE; | |
1863 | } | |
1864 | ||
1865 | static struct notifier_block efx_netdev_notifier = { | |
1866 | .notifier_call = efx_netdev_event, | |
1867 | }; | |
1868 | ||
06d5e193 BH |
1869 | static ssize_t |
1870 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1871 | { | |
1872 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1873 | return sprintf(buf, "%d\n", efx->phy_type); | |
1874 | } | |
1875 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1876 | ||
8ceee660 BH |
1877 | static int efx_register_netdev(struct efx_nic *efx) |
1878 | { | |
1879 | struct net_device *net_dev = efx->net_dev; | |
1880 | int rc; | |
1881 | ||
1882 | net_dev->watchdog_timeo = 5 * HZ; | |
1883 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1884 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1885 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1886 | ||
8ceee660 | 1887 | /* Clear MAC statistics */ |
177dfcd8 | 1888 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1889 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1890 | ||
7dde596e | 1891 | rtnl_lock(); |
aed0628d BH |
1892 | |
1893 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1894 | if (rc < 0) | |
1895 | goto fail_locked; | |
7dde596e | 1896 | efx_update_name(efx); |
aed0628d BH |
1897 | |
1898 | rc = register_netdevice(net_dev); | |
1899 | if (rc) | |
1900 | goto fail_locked; | |
1901 | ||
1902 | /* Always start with carrier off; PHY events will detect the link */ | |
1903 | netif_carrier_off(efx->net_dev); | |
1904 | ||
7dde596e | 1905 | rtnl_unlock(); |
8ceee660 | 1906 | |
06d5e193 BH |
1907 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1908 | if (rc) { | |
62776d03 BH |
1909 | netif_err(efx, drv, efx->net_dev, |
1910 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1911 | goto fail_registered; |
1912 | } | |
1913 | ||
8ceee660 | 1914 | return 0; |
06d5e193 | 1915 | |
aed0628d BH |
1916 | fail_locked: |
1917 | rtnl_unlock(); | |
62776d03 | 1918 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1919 | return rc; |
1920 | ||
06d5e193 BH |
1921 | fail_registered: |
1922 | unregister_netdev(net_dev); | |
1923 | return rc; | |
8ceee660 BH |
1924 | } |
1925 | ||
1926 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1927 | { | |
f7d12cdc | 1928 | struct efx_channel *channel; |
8ceee660 BH |
1929 | struct efx_tx_queue *tx_queue; |
1930 | ||
1931 | if (!efx->net_dev) | |
1932 | return; | |
1933 | ||
767e468c | 1934 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1935 | |
1936 | /* Free up any skbs still remaining. This has to happen before | |
1937 | * we try to unregister the netdev as running their destructors | |
1938 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
1939 | efx_for_each_channel(channel, efx) { |
1940 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1941 | efx_release_tx_buffers(tx_queue); | |
1942 | } | |
8ceee660 | 1943 | |
55668611 | 1944 | if (efx_dev_registered(efx)) { |
8ceee660 | 1945 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1946 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1947 | unregister_netdev(efx->net_dev); |
1948 | } | |
1949 | } | |
1950 | ||
1951 | /************************************************************************** | |
1952 | * | |
1953 | * Device reset and suspend | |
1954 | * | |
1955 | **************************************************************************/ | |
1956 | ||
2467ca46 BH |
1957 | /* Tears down the entire software state and most of the hardware state |
1958 | * before reset. */ | |
d3245b28 | 1959 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1960 | { |
8ceee660 BH |
1961 | EFX_ASSERT_RESET_SERIALISED(efx); |
1962 | ||
2467ca46 BH |
1963 | efx_stop_all(efx); |
1964 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1965 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1966 | |
8ceee660 | 1967 | efx_fini_channels(efx); |
4b988280 SH |
1968 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1969 | efx->phy_op->fini(efx); | |
ef2b90ee | 1970 | efx->type->fini(efx); |
8ceee660 BH |
1971 | } |
1972 | ||
2467ca46 BH |
1973 | /* This function will always ensure that the locks acquired in |
1974 | * efx_reset_down() are released. A failure return code indicates | |
1975 | * that we were unable to reinitialise the hardware, and the | |
1976 | * driver should be disabled. If ok is false, then the rx and tx | |
1977 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 1978 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
1979 | { |
1980 | int rc; | |
1981 | ||
2467ca46 | 1982 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1983 | |
ef2b90ee | 1984 | rc = efx->type->init(efx); |
8ceee660 | 1985 | if (rc) { |
62776d03 | 1986 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 1987 | goto fail; |
8ceee660 BH |
1988 | } |
1989 | ||
eb9f6744 BH |
1990 | if (!ok) |
1991 | goto fail; | |
1992 | ||
4b988280 | 1993 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
1994 | rc = efx->phy_op->init(efx); |
1995 | if (rc) | |
1996 | goto fail; | |
1997 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
1998 | netif_err(efx, drv, efx->net_dev, |
1999 | "could not restore PHY settings\n"); | |
4b988280 SH |
2000 | } |
2001 | ||
eb9f6744 | 2002 | efx->mac_op->reconfigure(efx); |
8ceee660 | 2003 | |
eb9f6744 | 2004 | efx_init_channels(efx); |
64eebcfd | 2005 | efx_restore_filters(efx); |
eb9f6744 BH |
2006 | |
2007 | mutex_unlock(&efx->spi_lock); | |
2008 | mutex_unlock(&efx->mac_lock); | |
2009 | ||
2010 | efx_start_all(efx); | |
2011 | ||
2012 | return 0; | |
2013 | ||
2014 | fail: | |
2015 | efx->port_initialized = false; | |
2467ca46 | 2016 | |
f4150724 | 2017 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
2018 | mutex_unlock(&efx->mac_lock); |
2019 | ||
8ceee660 BH |
2020 | return rc; |
2021 | } | |
2022 | ||
eb9f6744 BH |
2023 | /* Reset the NIC using the specified method. Note that the reset may |
2024 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2025 | * |
eb9f6744 | 2026 | * Caller must hold the rtnl_lock. |
8ceee660 | 2027 | */ |
eb9f6744 | 2028 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2029 | { |
eb9f6744 BH |
2030 | int rc, rc2; |
2031 | bool disabled; | |
8ceee660 | 2032 | |
62776d03 BH |
2033 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2034 | RESET_TYPE(method)); | |
8ceee660 | 2035 | |
d3245b28 | 2036 | efx_reset_down(efx, method); |
8ceee660 | 2037 | |
ef2b90ee | 2038 | rc = efx->type->reset(efx, method); |
8ceee660 | 2039 | if (rc) { |
62776d03 | 2040 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2041 | goto out; |
8ceee660 BH |
2042 | } |
2043 | ||
2044 | /* Allow resets to be rescheduled. */ | |
2045 | efx->reset_pending = RESET_TYPE_NONE; | |
2046 | ||
2047 | /* Reinitialise bus-mastering, which may have been turned off before | |
2048 | * the reset was scheduled. This is still appropriate, even in the | |
2049 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2050 | * can respond to requests. */ | |
2051 | pci_set_master(efx->pci_dev); | |
2052 | ||
eb9f6744 | 2053 | out: |
8ceee660 | 2054 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2055 | disabled = rc || method == RESET_TYPE_DISABLE; |
2056 | rc2 = efx_reset_up(efx, method, !disabled); | |
2057 | if (rc2) { | |
2058 | disabled = true; | |
2059 | if (!rc) | |
2060 | rc = rc2; | |
8ceee660 BH |
2061 | } |
2062 | ||
eb9f6744 | 2063 | if (disabled) { |
f49a4589 | 2064 | dev_close(efx->net_dev); |
62776d03 | 2065 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2066 | efx->state = STATE_DISABLED; |
f4bd954e | 2067 | } else { |
62776d03 | 2068 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
f4bd954e | 2069 | } |
8ceee660 BH |
2070 | return rc; |
2071 | } | |
2072 | ||
2073 | /* The worker thread exists so that code that cannot sleep can | |
2074 | * schedule a reset for later. | |
2075 | */ | |
2076 | static void efx_reset_work(struct work_struct *data) | |
2077 | { | |
eb9f6744 | 2078 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 2079 | |
319ba649 SH |
2080 | if (efx->reset_pending == RESET_TYPE_NONE) |
2081 | return; | |
2082 | ||
eb9f6744 BH |
2083 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
2084 | * flag set so that efx_pci_probe_main will be retried */ | |
2085 | if (efx->state != STATE_RUNNING) { | |
62776d03 BH |
2086 | netif_info(efx, drv, efx->net_dev, |
2087 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2088 | return; |
2089 | } | |
2090 | ||
2091 | rtnl_lock(); | |
f49a4589 | 2092 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 2093 | rtnl_unlock(); |
8ceee660 BH |
2094 | } |
2095 | ||
2096 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2097 | { | |
2098 | enum reset_type method; | |
2099 | ||
2100 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
62776d03 BH |
2101 | netif_info(efx, drv, efx->net_dev, |
2102 | "quenching already scheduled reset\n"); | |
8ceee660 BH |
2103 | return; |
2104 | } | |
2105 | ||
2106 | switch (type) { | |
2107 | case RESET_TYPE_INVISIBLE: | |
2108 | case RESET_TYPE_ALL: | |
2109 | case RESET_TYPE_WORLD: | |
2110 | case RESET_TYPE_DISABLE: | |
2111 | method = type; | |
2112 | break; | |
2113 | case RESET_TYPE_RX_RECOVERY: | |
2114 | case RESET_TYPE_RX_DESC_FETCH: | |
2115 | case RESET_TYPE_TX_DESC_FETCH: | |
2116 | case RESET_TYPE_TX_SKIP: | |
2117 | method = RESET_TYPE_INVISIBLE; | |
2118 | break; | |
8880f4ec | 2119 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
2120 | default: |
2121 | method = RESET_TYPE_ALL; | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | if (method != type) | |
62776d03 BH |
2126 | netif_dbg(efx, drv, efx->net_dev, |
2127 | "scheduling %s reset for %s\n", | |
2128 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 2129 | else |
62776d03 BH |
2130 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2131 | RESET_TYPE(method)); | |
8ceee660 BH |
2132 | |
2133 | efx->reset_pending = method; | |
2134 | ||
8880f4ec BH |
2135 | /* efx_process_channel() will no longer read events once a |
2136 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2137 | efx_mcdi_mode_poll(efx); | |
2138 | ||
1ab00629 | 2139 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2140 | } |
2141 | ||
2142 | /************************************************************************** | |
2143 | * | |
2144 | * List of NICs we support | |
2145 | * | |
2146 | **************************************************************************/ | |
2147 | ||
2148 | /* PCI device ID table */ | |
a3aa1884 | 2149 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 2150 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 2151 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 2152 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 2153 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
2154 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
2155 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
2156 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
2157 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
2158 | {0} /* end of list */ |
2159 | }; | |
2160 | ||
2161 | /************************************************************************** | |
2162 | * | |
3759433d | 2163 | * Dummy PHY/MAC operations |
8ceee660 | 2164 | * |
01aad7b6 | 2165 | * Can be used for some unimplemented operations |
8ceee660 BH |
2166 | * Needed so all function pointers are valid and do not have to be tested |
2167 | * before use | |
2168 | * | |
2169 | **************************************************************************/ | |
2170 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2171 | { | |
2172 | return 0; | |
2173 | } | |
2174 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2175 | |
2176 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2177 | { |
2178 | return false; | |
2179 | } | |
8ceee660 BH |
2180 | |
2181 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
2182 | .init = efx_port_dummy_op_int, | |
d3245b28 | 2183 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2184 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2185 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2186 | }; |
2187 | ||
8ceee660 BH |
2188 | /************************************************************************** |
2189 | * | |
2190 | * Data housekeeping | |
2191 | * | |
2192 | **************************************************************************/ | |
2193 | ||
2194 | /* This zeroes out and then fills in the invariants in a struct | |
2195 | * efx_nic (including all sub-structures). | |
2196 | */ | |
2197 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
2198 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
2199 | { | |
4642610c | 2200 | int i; |
8ceee660 BH |
2201 | |
2202 | /* Initialise common structures */ | |
2203 | memset(efx, 0, sizeof(*efx)); | |
2204 | spin_lock_init(&efx->biu_lock); | |
ab867461 | 2205 | mutex_init(&efx->mdio_lock); |
f4150724 | 2206 | mutex_init(&efx->spi_lock); |
76884835 BH |
2207 | #ifdef CONFIG_SFC_MTD |
2208 | INIT_LIST_HEAD(&efx->mtd_list); | |
2209 | #endif | |
8ceee660 BH |
2210 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2211 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2212 | efx->pci_dev = pci_dev; | |
62776d03 | 2213 | efx->msg_enable = debug; |
8ceee660 BH |
2214 | efx->state = STATE_INIT; |
2215 | efx->reset_pending = RESET_TYPE_NONE; | |
2216 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2217 | |
2218 | efx->net_dev = net_dev; | |
dc8cfa55 | 2219 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2220 | spin_lock_init(&efx->stats_lock); |
2221 | mutex_init(&efx->mac_lock); | |
b895d73e | 2222 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2223 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2224 | efx->mdio.dev = net_dev; |
766ca0fa | 2225 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2226 | |
2227 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2228 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2229 | if (!efx->channel[i]) | |
2230 | goto fail; | |
8ceee660 BH |
2231 | } |
2232 | ||
2233 | efx->type = type; | |
2234 | ||
8ceee660 BH |
2235 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2236 | ||
2237 | /* Higher numbered interrupt modes are less capable! */ | |
2238 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2239 | interrupt_mode); | |
2240 | ||
6977dc63 BH |
2241 | /* Would be good to use the net_dev name, but we're too early */ |
2242 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2243 | pci_name(pci_dev)); | |
2244 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2245 | if (!efx->workqueue) |
4642610c | 2246 | goto fail; |
8d9853d9 | 2247 | |
8ceee660 | 2248 | return 0; |
4642610c BH |
2249 | |
2250 | fail: | |
2251 | efx_fini_struct(efx); | |
2252 | return -ENOMEM; | |
8ceee660 BH |
2253 | } |
2254 | ||
2255 | static void efx_fini_struct(struct efx_nic *efx) | |
2256 | { | |
8313aca3 BH |
2257 | int i; |
2258 | ||
2259 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2260 | kfree(efx->channel[i]); | |
2261 | ||
8ceee660 BH |
2262 | if (efx->workqueue) { |
2263 | destroy_workqueue(efx->workqueue); | |
2264 | efx->workqueue = NULL; | |
2265 | } | |
2266 | } | |
2267 | ||
2268 | /************************************************************************** | |
2269 | * | |
2270 | * PCI interface | |
2271 | * | |
2272 | **************************************************************************/ | |
2273 | ||
2274 | /* Main body of final NIC shutdown code | |
2275 | * This is called only at module unload (or hotplug removal). | |
2276 | */ | |
2277 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2278 | { | |
152b6a62 | 2279 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2280 | efx_fini_channels(efx); |
2281 | efx_fini_port(efx); | |
ef2b90ee | 2282 | efx->type->fini(efx); |
8ceee660 BH |
2283 | efx_fini_napi(efx); |
2284 | efx_remove_all(efx); | |
2285 | } | |
2286 | ||
2287 | /* Final NIC shutdown | |
2288 | * This is called only at module unload (or hotplug removal). | |
2289 | */ | |
2290 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2291 | { | |
2292 | struct efx_nic *efx; | |
2293 | ||
2294 | efx = pci_get_drvdata(pci_dev); | |
2295 | if (!efx) | |
2296 | return; | |
2297 | ||
2298 | /* Mark the NIC as fini, then stop the interface */ | |
2299 | rtnl_lock(); | |
2300 | efx->state = STATE_FINI; | |
2301 | dev_close(efx->net_dev); | |
2302 | ||
2303 | /* Allow any queued efx_resets() to complete */ | |
2304 | rtnl_unlock(); | |
2305 | ||
8ceee660 BH |
2306 | efx_unregister_netdev(efx); |
2307 | ||
7dde596e BH |
2308 | efx_mtd_remove(efx); |
2309 | ||
8ceee660 BH |
2310 | /* Wait for any scheduled resets to complete. No more will be |
2311 | * scheduled from this point because efx_stop_all() has been | |
2312 | * called, we are no longer registered with driverlink, and | |
2313 | * the net_device's have been removed. */ | |
1ab00629 | 2314 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2315 | |
2316 | efx_pci_remove_main(efx); | |
2317 | ||
8ceee660 | 2318 | efx_fini_io(efx); |
62776d03 | 2319 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2320 | |
2321 | pci_set_drvdata(pci_dev, NULL); | |
2322 | efx_fini_struct(efx); | |
2323 | free_netdev(efx->net_dev); | |
2324 | }; | |
2325 | ||
2326 | /* Main body of NIC initialisation | |
2327 | * This is called at module load (or hotplug insertion, theoretically). | |
2328 | */ | |
2329 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2330 | { | |
2331 | int rc; | |
2332 | ||
2333 | /* Do start-of-day initialisation */ | |
2334 | rc = efx_probe_all(efx); | |
2335 | if (rc) | |
2336 | goto fail1; | |
2337 | ||
2338 | rc = efx_init_napi(efx); | |
2339 | if (rc) | |
2340 | goto fail2; | |
2341 | ||
ef2b90ee | 2342 | rc = efx->type->init(efx); |
8ceee660 | 2343 | if (rc) { |
62776d03 BH |
2344 | netif_err(efx, probe, efx->net_dev, |
2345 | "failed to initialise NIC\n"); | |
278c0621 | 2346 | goto fail3; |
8ceee660 BH |
2347 | } |
2348 | ||
2349 | rc = efx_init_port(efx); | |
2350 | if (rc) { | |
62776d03 BH |
2351 | netif_err(efx, probe, efx->net_dev, |
2352 | "failed to initialise port\n"); | |
278c0621 | 2353 | goto fail4; |
8ceee660 BH |
2354 | } |
2355 | ||
bc3c90a2 | 2356 | efx_init_channels(efx); |
8ceee660 | 2357 | |
152b6a62 | 2358 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2359 | if (rc) |
278c0621 | 2360 | goto fail5; |
8ceee660 BH |
2361 | |
2362 | return 0; | |
2363 | ||
278c0621 | 2364 | fail5: |
bc3c90a2 | 2365 | efx_fini_channels(efx); |
8ceee660 | 2366 | efx_fini_port(efx); |
8ceee660 | 2367 | fail4: |
ef2b90ee | 2368 | efx->type->fini(efx); |
8ceee660 BH |
2369 | fail3: |
2370 | efx_fini_napi(efx); | |
2371 | fail2: | |
2372 | efx_remove_all(efx); | |
2373 | fail1: | |
2374 | return rc; | |
2375 | } | |
2376 | ||
2377 | /* NIC initialisation | |
2378 | * | |
2379 | * This is called at module load (or hotplug insertion, | |
2380 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2381 | * sets up and registers the network devices with the kernel and hooks | |
2382 | * the interrupt service routine. It does not prepare the device for | |
2383 | * transmission; this is left to the first time one of the network | |
2384 | * interfaces is brought up (i.e. efx_net_open). | |
2385 | */ | |
2386 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2387 | const struct pci_device_id *entry) | |
2388 | { | |
2389 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2390 | struct net_device *net_dev; | |
2391 | struct efx_nic *efx; | |
2392 | int i, rc; | |
2393 | ||
2394 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
a4900ac9 | 2395 | net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES); |
8ceee660 BH |
2396 | if (!net_dev) |
2397 | return -ENOMEM; | |
c383b537 | 2398 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2399 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2400 | NETIF_F_GRO); | |
738a8f4b BH |
2401 | if (type->offload_features & NETIF_F_V6_CSUM) |
2402 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2403 | /* Mask for features that also apply to VLAN devices */ |
2404 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2405 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2406 | efx = netdev_priv(net_dev); |
8ceee660 | 2407 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2408 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2409 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2410 | if (rc) | |
2411 | goto fail1; | |
2412 | ||
62776d03 BH |
2413 | netif_info(efx, probe, efx->net_dev, |
2414 | "Solarflare Communications NIC detected\n"); | |
8ceee660 BH |
2415 | |
2416 | /* Set up basic I/O (BAR mappings etc) */ | |
2417 | rc = efx_init_io(efx); | |
2418 | if (rc) | |
2419 | goto fail2; | |
2420 | ||
2421 | /* No serialisation is required with the reset path because | |
2422 | * we're in STATE_INIT. */ | |
2423 | for (i = 0; i < 5; i++) { | |
2424 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2425 | |
2426 | /* Serialise against efx_reset(). No more resets will be | |
2427 | * scheduled since efx_stop_all() has been called, and we | |
2428 | * have not and never have been registered with either | |
2429 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2430 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2431 | |
fa402b2e SH |
2432 | if (rc == 0) { |
2433 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2434 | /* If there was a scheduled reset during | |
2435 | * probe, the NIC is probably hosed anyway */ | |
2436 | efx_pci_remove_main(efx); | |
2437 | rc = -EIO; | |
2438 | } else { | |
2439 | break; | |
2440 | } | |
2441 | } | |
2442 | ||
8ceee660 BH |
2443 | /* Retry if a recoverably reset event has been scheduled */ |
2444 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2445 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2446 | goto fail3; | |
2447 | ||
2448 | efx->reset_pending = RESET_TYPE_NONE; | |
2449 | } | |
2450 | ||
2451 | if (rc) { | |
62776d03 | 2452 | netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); |
8ceee660 BH |
2453 | goto fail4; |
2454 | } | |
2455 | ||
55edc6e6 BH |
2456 | /* Switch to the running state before we expose the device to the OS, |
2457 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2458 | efx->state = STATE_RUNNING; |
7dde596e | 2459 | |
8ceee660 BH |
2460 | rc = efx_register_netdev(efx); |
2461 | if (rc) | |
2462 | goto fail5; | |
2463 | ||
62776d03 | 2464 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 BH |
2465 | |
2466 | rtnl_lock(); | |
2467 | efx_mtd_probe(efx); /* allowed to fail */ | |
2468 | rtnl_unlock(); | |
8ceee660 BH |
2469 | return 0; |
2470 | ||
2471 | fail5: | |
2472 | efx_pci_remove_main(efx); | |
2473 | fail4: | |
2474 | fail3: | |
2475 | efx_fini_io(efx); | |
2476 | fail2: | |
2477 | efx_fini_struct(efx); | |
2478 | fail1: | |
5e2a911c | 2479 | WARN_ON(rc > 0); |
62776d03 | 2480 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2481 | free_netdev(net_dev); |
2482 | return rc; | |
2483 | } | |
2484 | ||
89c758fa BH |
2485 | static int efx_pm_freeze(struct device *dev) |
2486 | { | |
2487 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2488 | ||
2489 | efx->state = STATE_FINI; | |
2490 | ||
2491 | netif_device_detach(efx->net_dev); | |
2492 | ||
2493 | efx_stop_all(efx); | |
2494 | efx_fini_channels(efx); | |
2495 | ||
2496 | return 0; | |
2497 | } | |
2498 | ||
2499 | static int efx_pm_thaw(struct device *dev) | |
2500 | { | |
2501 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2502 | ||
2503 | efx->state = STATE_INIT; | |
2504 | ||
2505 | efx_init_channels(efx); | |
2506 | ||
2507 | mutex_lock(&efx->mac_lock); | |
2508 | efx->phy_op->reconfigure(efx); | |
2509 | mutex_unlock(&efx->mac_lock); | |
2510 | ||
2511 | efx_start_all(efx); | |
2512 | ||
2513 | netif_device_attach(efx->net_dev); | |
2514 | ||
2515 | efx->state = STATE_RUNNING; | |
2516 | ||
2517 | efx->type->resume_wol(efx); | |
2518 | ||
319ba649 SH |
2519 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2520 | queue_work(reset_workqueue, &efx->reset_work); | |
2521 | ||
89c758fa BH |
2522 | return 0; |
2523 | } | |
2524 | ||
2525 | static int efx_pm_poweroff(struct device *dev) | |
2526 | { | |
2527 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2528 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2529 | ||
2530 | efx->type->fini(efx); | |
2531 | ||
2532 | efx->reset_pending = RESET_TYPE_NONE; | |
2533 | ||
2534 | pci_save_state(pci_dev); | |
2535 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2536 | } | |
2537 | ||
2538 | /* Used for both resume and restore */ | |
2539 | static int efx_pm_resume(struct device *dev) | |
2540 | { | |
2541 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2542 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2543 | int rc; | |
2544 | ||
2545 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2546 | if (rc) | |
2547 | return rc; | |
2548 | pci_restore_state(pci_dev); | |
2549 | rc = pci_enable_device(pci_dev); | |
2550 | if (rc) | |
2551 | return rc; | |
2552 | pci_set_master(efx->pci_dev); | |
2553 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2554 | if (rc) | |
2555 | return rc; | |
2556 | rc = efx->type->init(efx); | |
2557 | if (rc) | |
2558 | return rc; | |
2559 | efx_pm_thaw(dev); | |
2560 | return 0; | |
2561 | } | |
2562 | ||
2563 | static int efx_pm_suspend(struct device *dev) | |
2564 | { | |
2565 | int rc; | |
2566 | ||
2567 | efx_pm_freeze(dev); | |
2568 | rc = efx_pm_poweroff(dev); | |
2569 | if (rc) | |
2570 | efx_pm_resume(dev); | |
2571 | return rc; | |
2572 | } | |
2573 | ||
2574 | static struct dev_pm_ops efx_pm_ops = { | |
2575 | .suspend = efx_pm_suspend, | |
2576 | .resume = efx_pm_resume, | |
2577 | .freeze = efx_pm_freeze, | |
2578 | .thaw = efx_pm_thaw, | |
2579 | .poweroff = efx_pm_poweroff, | |
2580 | .restore = efx_pm_resume, | |
2581 | }; | |
2582 | ||
8ceee660 | 2583 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2584 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2585 | .id_table = efx_pci_table, |
2586 | .probe = efx_pci_probe, | |
2587 | .remove = efx_pci_remove, | |
89c758fa | 2588 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2589 | }; |
2590 | ||
2591 | /************************************************************************** | |
2592 | * | |
2593 | * Kernel module interface | |
2594 | * | |
2595 | *************************************************************************/ | |
2596 | ||
2597 | module_param(interrupt_mode, uint, 0444); | |
2598 | MODULE_PARM_DESC(interrupt_mode, | |
2599 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2600 | ||
2601 | static int __init efx_init_module(void) | |
2602 | { | |
2603 | int rc; | |
2604 | ||
2605 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2606 | ||
2607 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2608 | if (rc) | |
2609 | goto err_notifier; | |
2610 | ||
1ab00629 SH |
2611 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2612 | if (!reset_workqueue) { | |
2613 | rc = -ENOMEM; | |
2614 | goto err_reset; | |
2615 | } | |
8ceee660 BH |
2616 | |
2617 | rc = pci_register_driver(&efx_pci_driver); | |
2618 | if (rc < 0) | |
2619 | goto err_pci; | |
2620 | ||
2621 | return 0; | |
2622 | ||
2623 | err_pci: | |
1ab00629 SH |
2624 | destroy_workqueue(reset_workqueue); |
2625 | err_reset: | |
8ceee660 BH |
2626 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2627 | err_notifier: | |
2628 | return rc; | |
2629 | } | |
2630 | ||
2631 | static void __exit efx_exit_module(void) | |
2632 | { | |
2633 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2634 | ||
2635 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2636 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2637 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2638 | ||
2639 | } | |
2640 | ||
2641 | module_init(efx_init_module); | |
2642 | module_exit(efx_exit_module); | |
2643 | ||
906bb26c BH |
2644 | MODULE_AUTHOR("Solarflare Communications and " |
2645 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2646 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2647 | MODULE_LICENSE("GPL"); | |
2648 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |