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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "ethtool.h" |
25 | #include "tx.h" | |
26 | #include "rx.h" | |
27 | #include "efx.h" | |
28 | #include "mdio_10g.h" | |
29 | #include "falcon.h" | |
8ceee660 BH |
30 | |
31 | #define EFX_MAX_MTU (9 * 1024) | |
32 | ||
33 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
34 | * a work item is pushed onto this work queue to retry the allocation later, | |
35 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
36 | * workqueue, there is nothing to be gained in making it per NIC | |
37 | */ | |
38 | static struct workqueue_struct *refill_workqueue; | |
39 | ||
1ab00629 SH |
40 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
41 | * queued onto this work queue. This is not a per-nic work queue, because | |
42 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
43 | */ | |
44 | static struct workqueue_struct *reset_workqueue; | |
45 | ||
8ceee660 BH |
46 | /************************************************************************** |
47 | * | |
48 | * Configurable values | |
49 | * | |
50 | *************************************************************************/ | |
51 | ||
8ceee660 BH |
52 | /* |
53 | * Use separate channels for TX and RX events | |
54 | * | |
28b581ab NT |
55 | * Set this to 1 to use separate channels for TX and RX. It allows us |
56 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 57 | * |
28b581ab | 58 | * This is only used in MSI-X interrupt mode |
8ceee660 | 59 | */ |
28b581ab NT |
60 | static unsigned int separate_tx_channels; |
61 | module_param(separate_tx_channels, uint, 0644); | |
62 | MODULE_PARM_DESC(separate_tx_channels, | |
63 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
64 | |
65 | /* This is the weight assigned to each of the (per-channel) virtual | |
66 | * NAPI devices. | |
67 | */ | |
68 | static int napi_weight = 64; | |
69 | ||
70 | /* This is the time (in jiffies) between invocations of the hardware | |
71 | * monitor, which checks for known hardware bugs and resets the | |
72 | * hardware and driver as necessary. | |
73 | */ | |
74 | unsigned int efx_monitor_interval = 1 * HZ; | |
75 | ||
8ceee660 BH |
76 | /* This controls whether or not the driver will initialise devices |
77 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
78 | * such devices will be initialised with a random locally-generated | |
79 | * MAC address. This allows for loading the sfc_mtd driver to | |
80 | * reprogram the flash, even if the flash contents (including the MAC | |
81 | * address) have previously been erased. | |
82 | */ | |
83 | static unsigned int allow_bad_hwaddr; | |
84 | ||
85 | /* Initial interrupt moderation settings. They can be modified after | |
86 | * module load with ethtool. | |
87 | * | |
88 | * The default for RX should strike a balance between increasing the | |
89 | * round-trip latency and reducing overhead. | |
90 | */ | |
91 | static unsigned int rx_irq_mod_usec = 60; | |
92 | ||
93 | /* Initial interrupt moderation settings. They can be modified after | |
94 | * module load with ethtool. | |
95 | * | |
96 | * This default is chosen to ensure that a 10G link does not go idle | |
97 | * while a TX queue is stopped after it has become full. A queue is | |
98 | * restarted when it drops below half full. The time this takes (assuming | |
99 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
100 | * 512 / 3 * 1.2 = 205 usec. | |
101 | */ | |
102 | static unsigned int tx_irq_mod_usec = 150; | |
103 | ||
104 | /* This is the first interrupt mode to try out of: | |
105 | * 0 => MSI-X | |
106 | * 1 => MSI | |
107 | * 2 => legacy | |
108 | */ | |
109 | static unsigned int interrupt_mode; | |
110 | ||
111 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
112 | * i.e. the number of CPUs among which we may distribute simultaneous | |
113 | * interrupt handling. | |
114 | * | |
115 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
116 | * The default (0) means to assign an interrupt to each package (level II cache) | |
117 | */ | |
118 | static unsigned int rss_cpus; | |
119 | module_param(rss_cpus, uint, 0444); | |
120 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
121 | ||
84ae48fe BH |
122 | static int phy_flash_cfg; |
123 | module_param(phy_flash_cfg, int, 0644); | |
124 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
125 | ||
6fb70fd1 BH |
126 | static unsigned irq_adapt_low_thresh = 10000; |
127 | module_param(irq_adapt_low_thresh, uint, 0644); | |
128 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
129 | "Threshold score for reducing IRQ moderation"); | |
130 | ||
131 | static unsigned irq_adapt_high_thresh = 20000; | |
132 | module_param(irq_adapt_high_thresh, uint, 0644); | |
133 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
134 | "Threshold score for increasing IRQ moderation"); | |
135 | ||
8ceee660 BH |
136 | /************************************************************************** |
137 | * | |
138 | * Utility functions and prototypes | |
139 | * | |
140 | *************************************************************************/ | |
141 | static void efx_remove_channel(struct efx_channel *channel); | |
142 | static void efx_remove_port(struct efx_nic *efx); | |
143 | static void efx_fini_napi(struct efx_nic *efx); | |
144 | static void efx_fini_channels(struct efx_nic *efx); | |
145 | ||
146 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
147 | do { \ | |
3c78708f | 148 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
149 | ASSERT_RTNL(); \ |
150 | } while (0) | |
151 | ||
152 | /************************************************************************** | |
153 | * | |
154 | * Event queue processing | |
155 | * | |
156 | *************************************************************************/ | |
157 | ||
158 | /* Process channel's event queue | |
159 | * | |
160 | * This function is responsible for processing the event queue of a | |
161 | * single channel. The caller must guarantee that this function will | |
162 | * never be concurrently called more than once on the same channel, | |
163 | * though different channels may be being processed concurrently. | |
164 | */ | |
4d566063 | 165 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 166 | { |
42cbe2d7 BH |
167 | struct efx_nic *efx = channel->efx; |
168 | int rx_packets; | |
8ceee660 | 169 | |
42cbe2d7 | 170 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 171 | !channel->enabled)) |
42cbe2d7 | 172 | return 0; |
8ceee660 | 173 | |
42cbe2d7 BH |
174 | rx_packets = falcon_process_eventq(channel, rx_quota); |
175 | if (rx_packets == 0) | |
176 | return 0; | |
8ceee660 BH |
177 | |
178 | /* Deliver last RX packet. */ | |
179 | if (channel->rx_pkt) { | |
180 | __efx_rx_packet(channel, channel->rx_pkt, | |
181 | channel->rx_pkt_csummed); | |
182 | channel->rx_pkt = NULL; | |
183 | } | |
184 | ||
8ceee660 BH |
185 | efx_rx_strategy(channel); |
186 | ||
42cbe2d7 | 187 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 188 | |
42cbe2d7 | 189 | return rx_packets; |
8ceee660 BH |
190 | } |
191 | ||
192 | /* Mark channel as finished processing | |
193 | * | |
194 | * Note that since we will not receive further interrupts for this | |
195 | * channel before we finish processing and call the eventq_read_ack() | |
196 | * method, there is no need to use the interrupt hold-off timers. | |
197 | */ | |
198 | static inline void efx_channel_processed(struct efx_channel *channel) | |
199 | { | |
5b9e207c BH |
200 | /* The interrupt handler for this channel may set work_pending |
201 | * as soon as we acknowledge the events we've seen. Make sure | |
202 | * it's cleared before then. */ | |
dc8cfa55 | 203 | channel->work_pending = false; |
5b9e207c BH |
204 | smp_wmb(); |
205 | ||
8ceee660 BH |
206 | falcon_eventq_read_ack(channel); |
207 | } | |
208 | ||
209 | /* NAPI poll handler | |
210 | * | |
211 | * NAPI guarantees serialisation of polls of the same device, which | |
212 | * provides the guarantee required by efx_process_channel(). | |
213 | */ | |
214 | static int efx_poll(struct napi_struct *napi, int budget) | |
215 | { | |
216 | struct efx_channel *channel = | |
217 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
218 | int rx_packets; |
219 | ||
220 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
221 | channel->channel, raw_smp_processor_id()); | |
222 | ||
42cbe2d7 | 223 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
224 | |
225 | if (rx_packets < budget) { | |
6fb70fd1 BH |
226 | struct efx_nic *efx = channel->efx; |
227 | ||
228 | if (channel->used_flags & EFX_USED_BY_RX && | |
229 | efx->irq_rx_adaptive && | |
230 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
231 | if (unlikely(channel->irq_mod_score < |
232 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
233 | if (channel->irq_moderation > 1) { |
234 | channel->irq_moderation -= 1; | |
235 | falcon_set_int_moderation(channel); | |
236 | } | |
6fb70fd1 BH |
237 | } else if (unlikely(channel->irq_mod_score > |
238 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
239 | if (channel->irq_moderation < |
240 | efx->irq_rx_moderation) { | |
241 | channel->irq_moderation += 1; | |
242 | falcon_set_int_moderation(channel); | |
243 | } | |
6fb70fd1 | 244 | } |
6fb70fd1 BH |
245 | channel->irq_count = 0; |
246 | channel->irq_mod_score = 0; | |
247 | } | |
248 | ||
8ceee660 | 249 | /* There is no race here; although napi_disable() will |
288379f0 | 250 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
251 | * since efx_channel_processed() will have no effect if |
252 | * interrupts have already been disabled. | |
253 | */ | |
288379f0 | 254 | napi_complete(napi); |
8ceee660 BH |
255 | efx_channel_processed(channel); |
256 | } | |
257 | ||
258 | return rx_packets; | |
259 | } | |
260 | ||
261 | /* Process the eventq of the specified channel immediately on this CPU | |
262 | * | |
263 | * Disable hardware generated interrupts, wait for any existing | |
264 | * processing to finish, then directly poll (and ack ) the eventq. | |
265 | * Finally reenable NAPI and interrupts. | |
266 | * | |
267 | * Since we are touching interrupts the caller should hold the suspend lock | |
268 | */ | |
269 | void efx_process_channel_now(struct efx_channel *channel) | |
270 | { | |
271 | struct efx_nic *efx = channel->efx; | |
272 | ||
273 | BUG_ON(!channel->used_flags); | |
274 | BUG_ON(!channel->enabled); | |
275 | ||
276 | /* Disable interrupts and wait for ISRs to complete */ | |
277 | falcon_disable_interrupts(efx); | |
278 | if (efx->legacy_irq) | |
279 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 280 | if (channel->irq) |
8ceee660 BH |
281 | synchronize_irq(channel->irq); |
282 | ||
283 | /* Wait for any NAPI processing to complete */ | |
284 | napi_disable(&channel->napi_str); | |
285 | ||
286 | /* Poll the channel */ | |
3ffeabdd | 287 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
288 | |
289 | /* Ack the eventq. This may cause an interrupt to be generated | |
290 | * when they are reenabled */ | |
291 | efx_channel_processed(channel); | |
292 | ||
293 | napi_enable(&channel->napi_str); | |
294 | falcon_enable_interrupts(efx); | |
295 | } | |
296 | ||
297 | /* Create event queue | |
298 | * Event queue memory allocations are done only once. If the channel | |
299 | * is reset, the memory buffer will be reused; this guards against | |
300 | * errors during channel reset and also simplifies interrupt handling. | |
301 | */ | |
302 | static int efx_probe_eventq(struct efx_channel *channel) | |
303 | { | |
304 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
305 | ||
306 | return falcon_probe_eventq(channel); | |
307 | } | |
308 | ||
309 | /* Prepare channel's event queue */ | |
bc3c90a2 | 310 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
311 | { |
312 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
313 | ||
314 | channel->eventq_read_ptr = 0; | |
315 | ||
bc3c90a2 | 316 | falcon_init_eventq(channel); |
8ceee660 BH |
317 | } |
318 | ||
319 | static void efx_fini_eventq(struct efx_channel *channel) | |
320 | { | |
321 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
322 | ||
323 | falcon_fini_eventq(channel); | |
324 | } | |
325 | ||
326 | static void efx_remove_eventq(struct efx_channel *channel) | |
327 | { | |
328 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
329 | ||
330 | falcon_remove_eventq(channel); | |
331 | } | |
332 | ||
333 | /************************************************************************** | |
334 | * | |
335 | * Channel handling | |
336 | * | |
337 | *************************************************************************/ | |
338 | ||
8ceee660 BH |
339 | static int efx_probe_channel(struct efx_channel *channel) |
340 | { | |
341 | struct efx_tx_queue *tx_queue; | |
342 | struct efx_rx_queue *rx_queue; | |
343 | int rc; | |
344 | ||
345 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
346 | ||
347 | rc = efx_probe_eventq(channel); | |
348 | if (rc) | |
349 | goto fail1; | |
350 | ||
351 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
352 | rc = efx_probe_tx_queue(tx_queue); | |
353 | if (rc) | |
354 | goto fail2; | |
355 | } | |
356 | ||
357 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
358 | rc = efx_probe_rx_queue(rx_queue); | |
359 | if (rc) | |
360 | goto fail3; | |
361 | } | |
362 | ||
363 | channel->n_rx_frm_trunc = 0; | |
364 | ||
365 | return 0; | |
366 | ||
367 | fail3: | |
368 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
369 | efx_remove_rx_queue(rx_queue); | |
370 | fail2: | |
371 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
372 | efx_remove_tx_queue(tx_queue); | |
373 | fail1: | |
374 | return rc; | |
375 | } | |
376 | ||
377 | ||
56536e9c BH |
378 | static void efx_set_channel_names(struct efx_nic *efx) |
379 | { | |
380 | struct efx_channel *channel; | |
381 | const char *type = ""; | |
382 | int number; | |
383 | ||
384 | efx_for_each_channel(channel, efx) { | |
385 | number = channel->channel; | |
386 | if (efx->n_channels > efx->n_rx_queues) { | |
387 | if (channel->channel < efx->n_rx_queues) { | |
388 | type = "-rx"; | |
389 | } else { | |
390 | type = "-tx"; | |
391 | number -= efx->n_rx_queues; | |
392 | } | |
393 | } | |
394 | snprintf(channel->name, sizeof(channel->name), | |
395 | "%s%s-%d", efx->name, type, number); | |
396 | } | |
397 | } | |
398 | ||
8ceee660 BH |
399 | /* Channels are shutdown and reinitialised whilst the NIC is running |
400 | * to propagate configuration changes (mtu, checksum offload), or | |
401 | * to clear hardware error conditions | |
402 | */ | |
bc3c90a2 | 403 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
404 | { |
405 | struct efx_tx_queue *tx_queue; | |
406 | struct efx_rx_queue *rx_queue; | |
407 | struct efx_channel *channel; | |
8ceee660 | 408 | |
f7f13b0b BH |
409 | /* Calculate the rx buffer allocation parameters required to |
410 | * support the current MTU, including padding for header | |
411 | * alignment and overruns. | |
412 | */ | |
413 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
414 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
415 | efx->type->rx_buffer_padding); | |
416 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
417 | |
418 | /* Initialise the channels */ | |
419 | efx_for_each_channel(channel, efx) { | |
420 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
421 | ||
bc3c90a2 | 422 | efx_init_eventq(channel); |
8ceee660 | 423 | |
bc3c90a2 BH |
424 | efx_for_each_channel_tx_queue(tx_queue, channel) |
425 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
426 | |
427 | /* The rx buffer allocation strategy is MTU dependent */ | |
428 | efx_rx_strategy(channel); | |
429 | ||
bc3c90a2 BH |
430 | efx_for_each_channel_rx_queue(rx_queue, channel) |
431 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
432 | |
433 | WARN_ON(channel->rx_pkt != NULL); | |
434 | efx_rx_strategy(channel); | |
435 | } | |
8ceee660 BH |
436 | } |
437 | ||
438 | /* This enables event queue processing and packet transmission. | |
439 | * | |
440 | * Note that this function is not allowed to fail, since that would | |
441 | * introduce too much complexity into the suspend/resume path. | |
442 | */ | |
443 | static void efx_start_channel(struct efx_channel *channel) | |
444 | { | |
445 | struct efx_rx_queue *rx_queue; | |
446 | ||
447 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
448 | ||
5b9e207c BH |
449 | /* The interrupt handler for this channel may set work_pending |
450 | * as soon as we enable it. Make sure it's cleared before | |
451 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
452 | channel->work_pending = false; |
453 | channel->enabled = true; | |
5b9e207c | 454 | smp_wmb(); |
8ceee660 BH |
455 | |
456 | napi_enable(&channel->napi_str); | |
457 | ||
458 | /* Load up RX descriptors */ | |
459 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
460 | efx_fast_push_rx_descriptors(rx_queue); | |
461 | } | |
462 | ||
463 | /* This disables event queue processing and packet transmission. | |
464 | * This function does not guarantee that all queue processing | |
465 | * (e.g. RX refill) is complete. | |
466 | */ | |
467 | static void efx_stop_channel(struct efx_channel *channel) | |
468 | { | |
469 | struct efx_rx_queue *rx_queue; | |
470 | ||
471 | if (!channel->enabled) | |
472 | return; | |
473 | ||
474 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
475 | ||
dc8cfa55 | 476 | channel->enabled = false; |
8ceee660 BH |
477 | napi_disable(&channel->napi_str); |
478 | ||
479 | /* Ensure that any worker threads have exited or will be no-ops */ | |
480 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
481 | spin_lock_bh(&rx_queue->add_lock); | |
482 | spin_unlock_bh(&rx_queue->add_lock); | |
483 | } | |
484 | } | |
485 | ||
486 | static void efx_fini_channels(struct efx_nic *efx) | |
487 | { | |
488 | struct efx_channel *channel; | |
489 | struct efx_tx_queue *tx_queue; | |
490 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 491 | int rc; |
8ceee660 BH |
492 | |
493 | EFX_ASSERT_RESET_SERIALISED(efx); | |
494 | BUG_ON(efx->port_enabled); | |
495 | ||
6bc5d3a9 BH |
496 | rc = falcon_flush_queues(efx); |
497 | if (rc) | |
498 | EFX_ERR(efx, "failed to flush queues\n"); | |
499 | else | |
500 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
501 | ||
8ceee660 BH |
502 | efx_for_each_channel(channel, efx) { |
503 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
504 | ||
505 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
506 | efx_fini_rx_queue(rx_queue); | |
507 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
508 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
509 | efx_fini_eventq(channel); |
510 | } | |
511 | } | |
512 | ||
513 | static void efx_remove_channel(struct efx_channel *channel) | |
514 | { | |
515 | struct efx_tx_queue *tx_queue; | |
516 | struct efx_rx_queue *rx_queue; | |
517 | ||
518 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
519 | ||
520 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
521 | efx_remove_rx_queue(rx_queue); | |
522 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
523 | efx_remove_tx_queue(tx_queue); | |
524 | efx_remove_eventq(channel); | |
525 | ||
526 | channel->used_flags = 0; | |
527 | } | |
528 | ||
529 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
530 | { | |
531 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
532 | } | |
533 | ||
534 | /************************************************************************** | |
535 | * | |
536 | * Port handling | |
537 | * | |
538 | **************************************************************************/ | |
539 | ||
540 | /* This ensures that the kernel is kept informed (via | |
541 | * netif_carrier_on/off) of the link status, and also maintains the | |
542 | * link status's stop on the port's TX queue. | |
543 | */ | |
544 | static void efx_link_status_changed(struct efx_nic *efx) | |
545 | { | |
8ceee660 BH |
546 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
547 | * that no events are triggered between unregister_netdev() and the | |
548 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
549 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
550 | if (!netif_running(efx->net_dev)) | |
551 | return; | |
552 | ||
8c8661e4 BH |
553 | if (efx->port_inhibited) { |
554 | netif_carrier_off(efx->net_dev); | |
555 | return; | |
556 | } | |
557 | ||
dc8cfa55 | 558 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
559 | efx->n_link_state_changes++; |
560 | ||
561 | if (efx->link_up) | |
562 | netif_carrier_on(efx->net_dev); | |
563 | else | |
564 | netif_carrier_off(efx->net_dev); | |
565 | } | |
566 | ||
567 | /* Status message for kernel log */ | |
568 | if (efx->link_up) { | |
f31a45d2 BH |
569 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
570 | efx->link_speed, efx->link_fd ? "full" : "half", | |
8ceee660 BH |
571 | efx->net_dev->mtu, |
572 | (efx->promiscuous ? " [PROMISC]" : "")); | |
573 | } else { | |
574 | EFX_INFO(efx, "link down\n"); | |
575 | } | |
576 | ||
577 | } | |
578 | ||
115122af BH |
579 | static void efx_fini_port(struct efx_nic *efx); |
580 | ||
8ceee660 BH |
581 | /* This call reinitialises the MAC to pick up new PHY settings. The |
582 | * caller must hold the mac_lock */ | |
8c8661e4 | 583 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
584 | { |
585 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
586 | ||
587 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
588 | raw_smp_processor_id()); | |
589 | ||
a816f75a BH |
590 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
591 | if (efx_dev_registered(efx)) { | |
592 | netif_addr_lock_bh(efx->net_dev); | |
593 | netif_addr_unlock_bh(efx->net_dev); | |
594 | } | |
595 | ||
177dfcd8 BH |
596 | falcon_deconfigure_mac_wrapper(efx); |
597 | ||
598 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
599 | if (LOOPBACK_INTERNAL(efx)) | |
600 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
601 | else | |
602 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
603 | efx->phy_op->reconfigure(efx); | |
604 | ||
605 | if (falcon_switch_mac(efx)) | |
606 | goto fail; | |
607 | ||
608 | efx->mac_op->reconfigure(efx); | |
8ceee660 BH |
609 | |
610 | /* Inform kernel of loss/gain of carrier */ | |
611 | efx_link_status_changed(efx); | |
177dfcd8 BH |
612 | return; |
613 | ||
614 | fail: | |
615 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
115122af BH |
616 | efx->port_enabled = false; |
617 | efx_fini_port(efx); | |
8ceee660 BH |
618 | } |
619 | ||
620 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
621 | * disabled. */ | |
622 | void efx_reconfigure_port(struct efx_nic *efx) | |
623 | { | |
624 | EFX_ASSERT_RESET_SERIALISED(efx); | |
625 | ||
626 | mutex_lock(&efx->mac_lock); | |
627 | __efx_reconfigure_port(efx); | |
628 | mutex_unlock(&efx->mac_lock); | |
629 | } | |
630 | ||
631 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
632 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
633 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 634 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 635 | { |
766ca0fa | 636 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
637 | |
638 | mutex_lock(&efx->mac_lock); | |
639 | if (efx->port_enabled) | |
640 | __efx_reconfigure_port(efx); | |
641 | mutex_unlock(&efx->mac_lock); | |
642 | } | |
643 | ||
766ca0fa BH |
644 | static void efx_mac_work(struct work_struct *data) |
645 | { | |
646 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
647 | ||
648 | mutex_lock(&efx->mac_lock); | |
649 | if (efx->port_enabled) | |
650 | efx->mac_op->irq(efx); | |
651 | mutex_unlock(&efx->mac_lock); | |
652 | } | |
653 | ||
8ceee660 BH |
654 | static int efx_probe_port(struct efx_nic *efx) |
655 | { | |
656 | int rc; | |
657 | ||
658 | EFX_LOG(efx, "create port\n"); | |
659 | ||
660 | /* Connect up MAC/PHY operations table and read MAC address */ | |
661 | rc = falcon_probe_port(efx); | |
662 | if (rc) | |
663 | goto err; | |
664 | ||
84ae48fe BH |
665 | if (phy_flash_cfg) |
666 | efx->phy_mode = PHY_MODE_SPECIAL; | |
667 | ||
8ceee660 BH |
668 | /* Sanity check MAC address */ |
669 | if (is_valid_ether_addr(efx->mac_address)) { | |
670 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
671 | } else { | |
e174961c JB |
672 | EFX_ERR(efx, "invalid MAC address %pM\n", |
673 | efx->mac_address); | |
8ceee660 BH |
674 | if (!allow_bad_hwaddr) { |
675 | rc = -EINVAL; | |
676 | goto err; | |
677 | } | |
678 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
679 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
680 | efx->net_dev->dev_addr); | |
8ceee660 BH |
681 | } |
682 | ||
683 | return 0; | |
684 | ||
685 | err: | |
686 | efx_remove_port(efx); | |
687 | return rc; | |
688 | } | |
689 | ||
690 | static int efx_init_port(struct efx_nic *efx) | |
691 | { | |
692 | int rc; | |
693 | ||
694 | EFX_LOG(efx, "init port\n"); | |
695 | ||
177dfcd8 | 696 | rc = efx->phy_op->init(efx); |
8ceee660 BH |
697 | if (rc) |
698 | return rc; | |
177dfcd8 | 699 | mutex_lock(&efx->mac_lock); |
4b988280 | 700 | efx->phy_op->reconfigure(efx); |
177dfcd8 BH |
701 | rc = falcon_switch_mac(efx); |
702 | mutex_unlock(&efx->mac_lock); | |
703 | if (rc) | |
704 | goto fail; | |
705 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 706 | |
dc8cfa55 | 707 | efx->port_initialized = true; |
1974cc20 | 708 | efx_stats_enable(efx); |
8ceee660 | 709 | return 0; |
177dfcd8 BH |
710 | |
711 | fail: | |
712 | efx->phy_op->fini(efx); | |
713 | return rc; | |
8ceee660 BH |
714 | } |
715 | ||
716 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
717 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 718 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
719 | static void efx_start_port(struct efx_nic *efx) |
720 | { | |
721 | EFX_LOG(efx, "start port\n"); | |
722 | BUG_ON(efx->port_enabled); | |
723 | ||
724 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 725 | efx->port_enabled = true; |
8ceee660 | 726 | __efx_reconfigure_port(efx); |
766ca0fa | 727 | efx->mac_op->irq(efx); |
8ceee660 BH |
728 | mutex_unlock(&efx->mac_lock); |
729 | } | |
730 | ||
766ca0fa BH |
731 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
732 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
733 | * and efx_mac_work may still be scheduled via NAPI processing until | |
734 | * efx_flush_all() is called */ | |
8ceee660 BH |
735 | static void efx_stop_port(struct efx_nic *efx) |
736 | { | |
737 | EFX_LOG(efx, "stop port\n"); | |
738 | ||
739 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 740 | efx->port_enabled = false; |
8ceee660 BH |
741 | mutex_unlock(&efx->mac_lock); |
742 | ||
743 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 744 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
745 | netif_addr_lock_bh(efx->net_dev); |
746 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
747 | } |
748 | } | |
749 | ||
750 | static void efx_fini_port(struct efx_nic *efx) | |
751 | { | |
752 | EFX_LOG(efx, "shut down port\n"); | |
753 | ||
754 | if (!efx->port_initialized) | |
755 | return; | |
756 | ||
1974cc20 | 757 | efx_stats_disable(efx); |
177dfcd8 | 758 | efx->phy_op->fini(efx); |
dc8cfa55 | 759 | efx->port_initialized = false; |
8ceee660 | 760 | |
dc8cfa55 | 761 | efx->link_up = false; |
8ceee660 BH |
762 | efx_link_status_changed(efx); |
763 | } | |
764 | ||
765 | static void efx_remove_port(struct efx_nic *efx) | |
766 | { | |
767 | EFX_LOG(efx, "destroying port\n"); | |
768 | ||
769 | falcon_remove_port(efx); | |
770 | } | |
771 | ||
772 | /************************************************************************** | |
773 | * | |
774 | * NIC handling | |
775 | * | |
776 | **************************************************************************/ | |
777 | ||
778 | /* This configures the PCI device to enable I/O and DMA. */ | |
779 | static int efx_init_io(struct efx_nic *efx) | |
780 | { | |
781 | struct pci_dev *pci_dev = efx->pci_dev; | |
782 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
783 | int rc; | |
784 | ||
785 | EFX_LOG(efx, "initialising I/O\n"); | |
786 | ||
787 | rc = pci_enable_device(pci_dev); | |
788 | if (rc) { | |
789 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
790 | goto fail1; | |
791 | } | |
792 | ||
793 | pci_set_master(pci_dev); | |
794 | ||
795 | /* Set the PCI DMA mask. Try all possibilities from our | |
796 | * genuine mask down to 32 bits, because some architectures | |
797 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
798 | * masks event though they reject 46 bit masks. | |
799 | */ | |
800 | while (dma_mask > 0x7fffffffUL) { | |
801 | if (pci_dma_supported(pci_dev, dma_mask) && | |
802 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
803 | break; | |
804 | dma_mask >>= 1; | |
805 | } | |
806 | if (rc) { | |
807 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
808 | goto fail2; | |
809 | } | |
810 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
811 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
812 | if (rc) { | |
813 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
814 | * fail with a mask that pci_set_dma_mask() accepted, | |
815 | * but just in case... | |
816 | */ | |
817 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
818 | goto fail2; | |
819 | } | |
820 | ||
dc803df8 BH |
821 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
822 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 BH |
823 | if (rc) { |
824 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
825 | rc = -EIO; | |
826 | goto fail3; | |
827 | } | |
828 | efx->membase = ioremap_nocache(efx->membase_phys, | |
829 | efx->type->mem_map_size); | |
830 | if (!efx->membase) { | |
dc803df8 | 831 | EFX_ERR(efx, "could not map memory BAR at %llx+%x\n", |
086ea356 | 832 | (unsigned long long)efx->membase_phys, |
8ceee660 BH |
833 | efx->type->mem_map_size); |
834 | rc = -ENOMEM; | |
835 | goto fail4; | |
836 | } | |
dc803df8 BH |
837 | EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n", |
838 | (unsigned long long)efx->membase_phys, | |
086ea356 | 839 | efx->type->mem_map_size, efx->membase); |
8ceee660 BH |
840 | |
841 | return 0; | |
842 | ||
843 | fail4: | |
dc803df8 | 844 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 845 | fail3: |
2c118e0f | 846 | efx->membase_phys = 0; |
8ceee660 BH |
847 | fail2: |
848 | pci_disable_device(efx->pci_dev); | |
849 | fail1: | |
850 | return rc; | |
851 | } | |
852 | ||
853 | static void efx_fini_io(struct efx_nic *efx) | |
854 | { | |
855 | EFX_LOG(efx, "shutting down I/O\n"); | |
856 | ||
857 | if (efx->membase) { | |
858 | iounmap(efx->membase); | |
859 | efx->membase = NULL; | |
860 | } | |
861 | ||
862 | if (efx->membase_phys) { | |
dc803df8 | 863 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 864 | efx->membase_phys = 0; |
8ceee660 BH |
865 | } |
866 | ||
867 | pci_disable_device(efx->pci_dev); | |
868 | } | |
869 | ||
46123d04 BH |
870 | /* Get number of RX queues wanted. Return number of online CPU |
871 | * packages in the expectation that an IRQ balancer will spread | |
872 | * interrupts across them. */ | |
873 | static int efx_wanted_rx_queues(void) | |
874 | { | |
2f8975fb | 875 | cpumask_var_t core_mask; |
46123d04 BH |
876 | int count; |
877 | int cpu; | |
878 | ||
79f55997 | 879 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 880 | printk(KERN_WARNING |
3977d033 | 881 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
882 | return 1; |
883 | } | |
884 | ||
46123d04 BH |
885 | count = 0; |
886 | for_each_online_cpu(cpu) { | |
2f8975fb | 887 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 888 | ++count; |
2f8975fb | 889 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 890 | topology_core_cpumask(cpu)); |
46123d04 BH |
891 | } |
892 | } | |
893 | ||
2f8975fb | 894 | free_cpumask_var(core_mask); |
46123d04 BH |
895 | return count; |
896 | } | |
897 | ||
898 | /* Probe the number and type of interrupts we are able to obtain, and | |
899 | * the resulting numbers of channels and RX queues. | |
900 | */ | |
8ceee660 BH |
901 | static void efx_probe_interrupts(struct efx_nic *efx) |
902 | { | |
46123d04 BH |
903 | int max_channels = |
904 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
905 | int rc, i; |
906 | ||
907 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
908 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
909 | int wanted_ints; | |
28b581ab | 910 | int rx_queues; |
aa6ef27e | 911 | |
46123d04 BH |
912 | /* We want one RX queue and interrupt per CPU package |
913 | * (or as specified by the rss_cpus module parameter). | |
914 | * We will need one channel per interrupt. | |
915 | */ | |
28b581ab NT |
916 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
917 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
918 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 919 | |
28b581ab | 920 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 921 | xentries[i].entry = i; |
28b581ab | 922 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 923 | if (rc > 0) { |
28b581ab NT |
924 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
925 | " available (%d < %d).\n", rc, wanted_ints); | |
926 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
927 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
928 | wanted_ints = rc; | |
8ceee660 | 929 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 930 | wanted_ints); |
8ceee660 BH |
931 | } |
932 | ||
933 | if (rc == 0) { | |
28b581ab NT |
934 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
935 | efx->n_channels = wanted_ints; | |
936 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 937 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
938 | } else { |
939 | /* Fall back to single channel MSI */ | |
940 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
941 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
942 | } | |
943 | } | |
944 | ||
945 | /* Try single interrupt MSI */ | |
946 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 947 | efx->n_rx_queues = 1; |
28b581ab | 948 | efx->n_channels = 1; |
8ceee660 BH |
949 | rc = pci_enable_msi(efx->pci_dev); |
950 | if (rc == 0) { | |
951 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
952 | } else { |
953 | EFX_ERR(efx, "could not enable MSI\n"); | |
954 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
955 | } | |
956 | } | |
957 | ||
958 | /* Assume legacy interrupts */ | |
959 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 960 | efx->n_rx_queues = 1; |
28b581ab | 961 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
962 | efx->legacy_irq = efx->pci_dev->irq; |
963 | } | |
964 | } | |
965 | ||
966 | static void efx_remove_interrupts(struct efx_nic *efx) | |
967 | { | |
968 | struct efx_channel *channel; | |
969 | ||
970 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 971 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
972 | channel->irq = 0; |
973 | pci_disable_msi(efx->pci_dev); | |
974 | pci_disable_msix(efx->pci_dev); | |
975 | ||
976 | /* Remove legacy interrupt */ | |
977 | efx->legacy_irq = 0; | |
978 | } | |
979 | ||
8831da7b | 980 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
981 | { |
982 | struct efx_tx_queue *tx_queue; | |
983 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 984 | |
60ac1065 | 985 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
986 | if (separate_tx_channels) |
987 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
988 | else |
989 | tx_queue->channel = &efx->channel[0]; | |
990 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
991 | } | |
8ceee660 | 992 | |
8831da7b BH |
993 | efx_for_each_rx_queue(rx_queue, efx) { |
994 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
995 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
996 | } |
997 | } | |
998 | ||
999 | static int efx_probe_nic(struct efx_nic *efx) | |
1000 | { | |
1001 | int rc; | |
1002 | ||
1003 | EFX_LOG(efx, "creating NIC\n"); | |
1004 | ||
1005 | /* Carry out hardware-type specific initialisation */ | |
1006 | rc = falcon_probe_nic(efx); | |
1007 | if (rc) | |
1008 | return rc; | |
1009 | ||
1010 | /* Determine the number of channels and RX queues by trying to hook | |
1011 | * in MSI-X interrupts. */ | |
1012 | efx_probe_interrupts(efx); | |
1013 | ||
8831da7b | 1014 | efx_set_channels(efx); |
8ceee660 BH |
1015 | |
1016 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1017 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1018 | |
1019 | return 0; | |
1020 | } | |
1021 | ||
1022 | static void efx_remove_nic(struct efx_nic *efx) | |
1023 | { | |
1024 | EFX_LOG(efx, "destroying NIC\n"); | |
1025 | ||
1026 | efx_remove_interrupts(efx); | |
1027 | falcon_remove_nic(efx); | |
1028 | } | |
1029 | ||
1030 | /************************************************************************** | |
1031 | * | |
1032 | * NIC startup/shutdown | |
1033 | * | |
1034 | *************************************************************************/ | |
1035 | ||
1036 | static int efx_probe_all(struct efx_nic *efx) | |
1037 | { | |
1038 | struct efx_channel *channel; | |
1039 | int rc; | |
1040 | ||
1041 | /* Create NIC */ | |
1042 | rc = efx_probe_nic(efx); | |
1043 | if (rc) { | |
1044 | EFX_ERR(efx, "failed to create NIC\n"); | |
1045 | goto fail1; | |
1046 | } | |
1047 | ||
1048 | /* Create port */ | |
1049 | rc = efx_probe_port(efx); | |
1050 | if (rc) { | |
1051 | EFX_ERR(efx, "failed to create port\n"); | |
1052 | goto fail2; | |
1053 | } | |
1054 | ||
1055 | /* Create channels */ | |
1056 | efx_for_each_channel(channel, efx) { | |
1057 | rc = efx_probe_channel(channel); | |
1058 | if (rc) { | |
1059 | EFX_ERR(efx, "failed to create channel %d\n", | |
1060 | channel->channel); | |
1061 | goto fail3; | |
1062 | } | |
1063 | } | |
56536e9c | 1064 | efx_set_channel_names(efx); |
8ceee660 BH |
1065 | |
1066 | return 0; | |
1067 | ||
1068 | fail3: | |
1069 | efx_for_each_channel(channel, efx) | |
1070 | efx_remove_channel(channel); | |
1071 | efx_remove_port(efx); | |
1072 | fail2: | |
1073 | efx_remove_nic(efx); | |
1074 | fail1: | |
1075 | return rc; | |
1076 | } | |
1077 | ||
1078 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1079 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1080 | * and ensures that the port is scheduled to be reconfigured. | |
1081 | * This function is safe to call multiple times when the NIC is in any | |
1082 | * state. */ | |
1083 | static void efx_start_all(struct efx_nic *efx) | |
1084 | { | |
1085 | struct efx_channel *channel; | |
1086 | ||
1087 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1088 | ||
1089 | /* Check that it is appropriate to restart the interface. All | |
1090 | * of these flags are safe to read under just the rtnl lock */ | |
1091 | if (efx->port_enabled) | |
1092 | return; | |
1093 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1094 | return; | |
55668611 | 1095 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1096 | return; |
1097 | ||
1098 | /* Mark the port as enabled so port reconfigurations can start, then | |
1099 | * restart the transmit interface early so the watchdog timer stops */ | |
1100 | efx_start_port(efx); | |
dacccc74 SH |
1101 | if (efx_dev_registered(efx)) |
1102 | efx_wake_queue(efx); | |
8ceee660 BH |
1103 | |
1104 | efx_for_each_channel(channel, efx) | |
1105 | efx_start_channel(channel); | |
1106 | ||
1107 | falcon_enable_interrupts(efx); | |
1108 | ||
1109 | /* Start hardware monitor if we're in RUNNING */ | |
1110 | if (efx->state == STATE_RUNNING) | |
1111 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1112 | efx_monitor_interval); | |
1113 | } | |
1114 | ||
1115 | /* Flush all delayed work. Should only be called when no more delayed work | |
1116 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1117 | * since we're holding the rtnl_lock at this point. */ | |
1118 | static void efx_flush_all(struct efx_nic *efx) | |
1119 | { | |
1120 | struct efx_rx_queue *rx_queue; | |
1121 | ||
1122 | /* Make sure the hardware monitor is stopped */ | |
1123 | cancel_delayed_work_sync(&efx->monitor_work); | |
1124 | ||
1125 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1126 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1127 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1128 | |
1129 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1130 | cancel_work_sync(&efx->mac_work); |
1131 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1132 | |
1133 | } | |
1134 | ||
1135 | /* Quiesce hardware and software without bringing the link down. | |
1136 | * Safe to call multiple times, when the nic and interface is in any | |
1137 | * state. The caller is guaranteed to subsequently be in a position | |
1138 | * to modify any hardware and software state they see fit without | |
1139 | * taking locks. */ | |
1140 | static void efx_stop_all(struct efx_nic *efx) | |
1141 | { | |
1142 | struct efx_channel *channel; | |
1143 | ||
1144 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1145 | ||
1146 | /* port_enabled can be read safely under the rtnl lock */ | |
1147 | if (!efx->port_enabled) | |
1148 | return; | |
1149 | ||
1150 | /* Disable interrupts and wait for ISR to complete */ | |
1151 | falcon_disable_interrupts(efx); | |
1152 | if (efx->legacy_irq) | |
1153 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1154 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1155 | if (channel->irq) |
1156 | synchronize_irq(channel->irq); | |
b3475645 | 1157 | } |
8ceee660 BH |
1158 | |
1159 | /* Stop all NAPI processing and synchronous rx refills */ | |
1160 | efx_for_each_channel(channel, efx) | |
1161 | efx_stop_channel(channel); | |
1162 | ||
1163 | /* Stop all asynchronous port reconfigurations. Since all | |
1164 | * event processing has already been stopped, there is no | |
1165 | * window to loose phy events */ | |
1166 | efx_stop_port(efx); | |
1167 | ||
766ca0fa | 1168 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1169 | efx_flush_all(efx); |
1170 | ||
1171 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1172 | * flushes will complete in a timely fashion. */ | |
5c8af3b9 BH |
1173 | falcon_deconfigure_mac_wrapper(efx); |
1174 | msleep(10); /* Let the Rx FIFO drain */ | |
8ceee660 BH |
1175 | falcon_drain_tx_fifo(efx); |
1176 | ||
1177 | /* Stop the kernel transmit interface late, so the watchdog | |
1178 | * timer isn't ticking over the flush */ | |
55668611 | 1179 | if (efx_dev_registered(efx)) { |
dacccc74 | 1180 | efx_stop_queue(efx); |
8ceee660 BH |
1181 | netif_tx_lock_bh(efx->net_dev); |
1182 | netif_tx_unlock_bh(efx->net_dev); | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | static void efx_remove_all(struct efx_nic *efx) | |
1187 | { | |
1188 | struct efx_channel *channel; | |
1189 | ||
1190 | efx_for_each_channel(channel, efx) | |
1191 | efx_remove_channel(channel); | |
1192 | efx_remove_port(efx); | |
1193 | efx_remove_nic(efx); | |
1194 | } | |
1195 | ||
1196 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1197 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1198 | { |
8ceee660 BH |
1199 | EFX_ASSERT_RESET_SERIALISED(efx); |
1200 | ||
1201 | efx_stop_all(efx); | |
1202 | ||
1203 | efx_fini_channels(efx); | |
bc3c90a2 | 1204 | efx_init_channels(efx); |
8ceee660 BH |
1205 | |
1206 | efx_start_all(efx); | |
8ceee660 BH |
1207 | } |
1208 | ||
1209 | /************************************************************************** | |
1210 | * | |
1211 | * Interrupt moderation | |
1212 | * | |
1213 | **************************************************************************/ | |
1214 | ||
0d86ebd8 BH |
1215 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1216 | { | |
1217 | if (usecs <= 0) | |
1218 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1219 | if (usecs < resolution) | |
1220 | return 1; /* never round down to 0 */ | |
1221 | return usecs / resolution; | |
1222 | } | |
1223 | ||
8ceee660 | 1224 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1225 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1226 | bool rx_adaptive) | |
8ceee660 BH |
1227 | { |
1228 | struct efx_tx_queue *tx_queue; | |
1229 | struct efx_rx_queue *rx_queue; | |
0d86ebd8 BH |
1230 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, FALCON_IRQ_MOD_RESOLUTION); |
1231 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, FALCON_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1232 | |
1233 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1234 | ||
1235 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1236 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1237 | |
6fb70fd1 | 1238 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1239 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1240 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1241 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1242 | } |
1243 | ||
1244 | /************************************************************************** | |
1245 | * | |
1246 | * Hardware monitor | |
1247 | * | |
1248 | **************************************************************************/ | |
1249 | ||
1250 | /* Run periodically off the general workqueue. Serialised against | |
1251 | * efx_reconfigure_port via the mac_lock */ | |
1252 | static void efx_monitor(struct work_struct *data) | |
1253 | { | |
1254 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1255 | monitor_work.work); | |
766ca0fa | 1256 | int rc; |
8ceee660 BH |
1257 | |
1258 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1259 | raw_smp_processor_id()); | |
1260 | ||
8ceee660 BH |
1261 | /* If the mac_lock is already held then it is likely a port |
1262 | * reconfiguration is already in place, which will likely do | |
1263 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1264 | if (!mutex_trylock(&efx->mac_lock)) |
1265 | goto out_requeue; | |
1266 | if (!efx->port_enabled) | |
1267 | goto out_unlock; | |
278c0621 | 1268 | rc = falcon_board(efx)->monitor(efx); |
766ca0fa BH |
1269 | if (rc) { |
1270 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
1271 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
1272 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
1273 | falcon_sim_phy_event(efx); | |
8ceee660 | 1274 | } |
766ca0fa BH |
1275 | efx->phy_op->poll(efx); |
1276 | efx->mac_op->poll(efx); | |
8ceee660 | 1277 | |
766ca0fa | 1278 | out_unlock: |
8ceee660 | 1279 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1280 | out_requeue: |
8ceee660 BH |
1281 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1282 | efx_monitor_interval); | |
1283 | } | |
1284 | ||
1285 | /************************************************************************** | |
1286 | * | |
1287 | * ioctls | |
1288 | * | |
1289 | *************************************************************************/ | |
1290 | ||
1291 | /* Net device ioctl | |
1292 | * Context: process, rtnl_lock() held. | |
1293 | */ | |
1294 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1295 | { | |
767e468c | 1296 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1297 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1298 | |
1299 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1300 | ||
68e7f45e BH |
1301 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1302 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1303 | (data->phy_id & 0xfc00) == 0x0400) | |
1304 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1305 | ||
1306 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1307 | } |
1308 | ||
1309 | /************************************************************************** | |
1310 | * | |
1311 | * NAPI interface | |
1312 | * | |
1313 | **************************************************************************/ | |
1314 | ||
1315 | static int efx_init_napi(struct efx_nic *efx) | |
1316 | { | |
1317 | struct efx_channel *channel; | |
8ceee660 BH |
1318 | |
1319 | efx_for_each_channel(channel, efx) { | |
1320 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1321 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1322 | efx_poll, napi_weight); | |
8ceee660 BH |
1323 | } |
1324 | return 0; | |
8ceee660 BH |
1325 | } |
1326 | ||
1327 | static void efx_fini_napi(struct efx_nic *efx) | |
1328 | { | |
1329 | struct efx_channel *channel; | |
1330 | ||
1331 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1332 | if (channel->napi_dev) |
1333 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1334 | channel->napi_dev = NULL; |
1335 | } | |
1336 | } | |
1337 | ||
1338 | /************************************************************************** | |
1339 | * | |
1340 | * Kernel netpoll interface | |
1341 | * | |
1342 | *************************************************************************/ | |
1343 | ||
1344 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1345 | ||
1346 | /* Although in the common case interrupts will be disabled, this is not | |
1347 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1348 | * so no locking is required. | |
1349 | */ | |
1350 | static void efx_netpoll(struct net_device *net_dev) | |
1351 | { | |
767e468c | 1352 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1353 | struct efx_channel *channel; |
1354 | ||
64ee3120 | 1355 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1356 | efx_schedule_channel(channel); |
1357 | } | |
1358 | ||
1359 | #endif | |
1360 | ||
1361 | /************************************************************************** | |
1362 | * | |
1363 | * Kernel net device interface | |
1364 | * | |
1365 | *************************************************************************/ | |
1366 | ||
1367 | /* Context: process, rtnl_lock() held. */ | |
1368 | static int efx_net_open(struct net_device *net_dev) | |
1369 | { | |
767e468c | 1370 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1371 | EFX_ASSERT_RESET_SERIALISED(efx); |
1372 | ||
1373 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1374 | raw_smp_processor_id()); | |
1375 | ||
f4bd954e BH |
1376 | if (efx->state == STATE_DISABLED) |
1377 | return -EIO; | |
f8b87c17 BH |
1378 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1379 | return -EBUSY; | |
1380 | ||
8ceee660 BH |
1381 | efx_start_all(efx); |
1382 | return 0; | |
1383 | } | |
1384 | ||
1385 | /* Context: process, rtnl_lock() held. | |
1386 | * Note that the kernel will ignore our return code; this method | |
1387 | * should really be a void. | |
1388 | */ | |
1389 | static int efx_net_stop(struct net_device *net_dev) | |
1390 | { | |
767e468c | 1391 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1392 | |
1393 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1394 | raw_smp_processor_id()); | |
1395 | ||
f4bd954e BH |
1396 | if (efx->state != STATE_DISABLED) { |
1397 | /* Stop the device and flush all the channels */ | |
1398 | efx_stop_all(efx); | |
1399 | efx_fini_channels(efx); | |
1400 | efx_init_channels(efx); | |
1401 | } | |
8ceee660 BH |
1402 | |
1403 | return 0; | |
1404 | } | |
1405 | ||
1974cc20 BH |
1406 | void efx_stats_disable(struct efx_nic *efx) |
1407 | { | |
1408 | spin_lock(&efx->stats_lock); | |
1409 | ++efx->stats_disable_count; | |
1410 | spin_unlock(&efx->stats_lock); | |
1411 | } | |
1412 | ||
1413 | void efx_stats_enable(struct efx_nic *efx) | |
1414 | { | |
1415 | spin_lock(&efx->stats_lock); | |
1416 | --efx->stats_disable_count; | |
1417 | spin_unlock(&efx->stats_lock); | |
1418 | } | |
1419 | ||
5b9e207c | 1420 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1421 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1422 | { | |
767e468c | 1423 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1424 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1425 | struct net_device_stats *stats = &net_dev->stats; | |
1426 | ||
5b9e207c | 1427 | /* Update stats if possible, but do not wait if another thread |
1974cc20 BH |
1428 | * is updating them or if MAC stats fetches are temporarily |
1429 | * disabled; slightly stale stats are acceptable. | |
5b9e207c | 1430 | */ |
8ceee660 BH |
1431 | if (!spin_trylock(&efx->stats_lock)) |
1432 | return stats; | |
1974cc20 | 1433 | if (!efx->stats_disable_count) { |
177dfcd8 | 1434 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1435 | falcon_update_nic_stats(efx); |
1436 | } | |
1437 | spin_unlock(&efx->stats_lock); | |
1438 | ||
1439 | stats->rx_packets = mac_stats->rx_packets; | |
1440 | stats->tx_packets = mac_stats->tx_packets; | |
1441 | stats->rx_bytes = mac_stats->rx_bytes; | |
1442 | stats->tx_bytes = mac_stats->tx_bytes; | |
1443 | stats->multicast = mac_stats->rx_multicast; | |
1444 | stats->collisions = mac_stats->tx_collision; | |
1445 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1446 | mac_stats->rx_length_error); | |
1447 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1448 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1449 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1450 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1451 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1452 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1453 | ||
1454 | stats->rx_errors = (stats->rx_length_errors + | |
1455 | stats->rx_over_errors + | |
1456 | stats->rx_crc_errors + | |
1457 | stats->rx_frame_errors + | |
1458 | stats->rx_fifo_errors + | |
1459 | stats->rx_missed_errors + | |
1460 | mac_stats->rx_symbol_error); | |
1461 | stats->tx_errors = (stats->tx_window_errors + | |
1462 | mac_stats->tx_bad); | |
1463 | ||
1464 | return stats; | |
1465 | } | |
1466 | ||
1467 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1468 | static void efx_watchdog(struct net_device *net_dev) | |
1469 | { | |
767e468c | 1470 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1471 | |
739bb23d BH |
1472 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1473 | " resetting channels\n", | |
1474 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1475 | |
739bb23d | 1476 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1477 | } |
1478 | ||
1479 | ||
1480 | /* Context: process, rtnl_lock() held. */ | |
1481 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1482 | { | |
767e468c | 1483 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1484 | int rc = 0; |
1485 | ||
1486 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1487 | ||
1488 | if (new_mtu > EFX_MAX_MTU) | |
1489 | return -EINVAL; | |
1490 | ||
1491 | efx_stop_all(efx); | |
1492 | ||
1493 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1494 | ||
1495 | efx_fini_channels(efx); | |
1496 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1497 | efx_init_channels(efx); |
8ceee660 BH |
1498 | |
1499 | efx_start_all(efx); | |
1500 | return rc; | |
8ceee660 BH |
1501 | } |
1502 | ||
1503 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1504 | { | |
767e468c | 1505 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1506 | struct sockaddr *addr = data; |
1507 | char *new_addr = addr->sa_data; | |
1508 | ||
1509 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1510 | ||
1511 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1512 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1513 | new_addr); | |
8ceee660 BH |
1514 | return -EINVAL; |
1515 | } | |
1516 | ||
1517 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1518 | ||
1519 | /* Reconfigure the MAC */ | |
1520 | efx_reconfigure_port(efx); | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
a816f75a | 1525 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1526 | static void efx_set_multicast_list(struct net_device *net_dev) |
1527 | { | |
767e468c | 1528 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1529 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1530 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1531 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1532 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1533 | u32 crc; |
1534 | int bit; | |
1535 | int i; | |
1536 | ||
a816f75a | 1537 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1538 | |
1539 | /* Build multicast hash table */ | |
1540 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1541 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1542 | } else { | |
1543 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1544 | for (i = 0; i < net_dev->mc_count; i++) { | |
1545 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1546 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1547 | set_bit_le(bit, mc_hash->byte); | |
1548 | mc_list = mc_list->next; | |
1549 | } | |
1550 | } | |
1551 | ||
a816f75a BH |
1552 | if (!efx->port_enabled) |
1553 | /* Delay pushing settings until efx_start_port() */ | |
1554 | return; | |
1555 | ||
1556 | if (changed) | |
766ca0fa | 1557 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1558 | |
8ceee660 BH |
1559 | /* Create and activate new global multicast hash table */ |
1560 | falcon_set_multicast_hash(efx); | |
1561 | } | |
1562 | ||
c3ecb9f3 SH |
1563 | static const struct net_device_ops efx_netdev_ops = { |
1564 | .ndo_open = efx_net_open, | |
1565 | .ndo_stop = efx_net_stop, | |
1566 | .ndo_get_stats = efx_net_stats, | |
1567 | .ndo_tx_timeout = efx_watchdog, | |
1568 | .ndo_start_xmit = efx_hard_start_xmit, | |
1569 | .ndo_validate_addr = eth_validate_addr, | |
1570 | .ndo_do_ioctl = efx_ioctl, | |
1571 | .ndo_change_mtu = efx_change_mtu, | |
1572 | .ndo_set_mac_address = efx_set_mac_address, | |
1573 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1574 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1575 | .ndo_poll_controller = efx_netpoll, | |
1576 | #endif | |
1577 | }; | |
1578 | ||
7dde596e BH |
1579 | static void efx_update_name(struct efx_nic *efx) |
1580 | { | |
1581 | strcpy(efx->name, efx->net_dev->name); | |
1582 | efx_mtd_rename(efx); | |
1583 | efx_set_channel_names(efx); | |
1584 | } | |
1585 | ||
8ceee660 BH |
1586 | static int efx_netdev_event(struct notifier_block *this, |
1587 | unsigned long event, void *ptr) | |
1588 | { | |
d3208b5e | 1589 | struct net_device *net_dev = ptr; |
8ceee660 | 1590 | |
7dde596e BH |
1591 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1592 | event == NETDEV_CHANGENAME) | |
1593 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1594 | |
1595 | return NOTIFY_DONE; | |
1596 | } | |
1597 | ||
1598 | static struct notifier_block efx_netdev_notifier = { | |
1599 | .notifier_call = efx_netdev_event, | |
1600 | }; | |
1601 | ||
06d5e193 BH |
1602 | static ssize_t |
1603 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1604 | { | |
1605 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1606 | return sprintf(buf, "%d\n", efx->phy_type); | |
1607 | } | |
1608 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1609 | ||
8ceee660 BH |
1610 | static int efx_register_netdev(struct efx_nic *efx) |
1611 | { | |
1612 | struct net_device *net_dev = efx->net_dev; | |
1613 | int rc; | |
1614 | ||
1615 | net_dev->watchdog_timeo = 5 * HZ; | |
1616 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1617 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1618 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1619 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1620 | ||
8ceee660 | 1621 | /* Clear MAC statistics */ |
177dfcd8 | 1622 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1623 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1624 | ||
7dde596e | 1625 | rtnl_lock(); |
aed0628d BH |
1626 | |
1627 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1628 | if (rc < 0) | |
1629 | goto fail_locked; | |
7dde596e | 1630 | efx_update_name(efx); |
aed0628d BH |
1631 | |
1632 | rc = register_netdevice(net_dev); | |
1633 | if (rc) | |
1634 | goto fail_locked; | |
1635 | ||
1636 | /* Always start with carrier off; PHY events will detect the link */ | |
1637 | netif_carrier_off(efx->net_dev); | |
1638 | ||
7dde596e | 1639 | rtnl_unlock(); |
8ceee660 | 1640 | |
06d5e193 BH |
1641 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1642 | if (rc) { | |
1643 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1644 | goto fail_registered; | |
1645 | } | |
1646 | ||
8ceee660 | 1647 | return 0; |
06d5e193 | 1648 | |
aed0628d BH |
1649 | fail_locked: |
1650 | rtnl_unlock(); | |
1651 | EFX_ERR(efx, "could not register net dev\n"); | |
1652 | return rc; | |
1653 | ||
06d5e193 BH |
1654 | fail_registered: |
1655 | unregister_netdev(net_dev); | |
1656 | return rc; | |
8ceee660 BH |
1657 | } |
1658 | ||
1659 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1660 | { | |
1661 | struct efx_tx_queue *tx_queue; | |
1662 | ||
1663 | if (!efx->net_dev) | |
1664 | return; | |
1665 | ||
767e468c | 1666 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1667 | |
1668 | /* Free up any skbs still remaining. This has to happen before | |
1669 | * we try to unregister the netdev as running their destructors | |
1670 | * may be needed to get the device ref. count to 0. */ | |
1671 | efx_for_each_tx_queue(tx_queue, efx) | |
1672 | efx_release_tx_buffers(tx_queue); | |
1673 | ||
55668611 | 1674 | if (efx_dev_registered(efx)) { |
8ceee660 | 1675 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1676 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1677 | unregister_netdev(efx->net_dev); |
1678 | } | |
1679 | } | |
1680 | ||
1681 | /************************************************************************** | |
1682 | * | |
1683 | * Device reset and suspend | |
1684 | * | |
1685 | **************************************************************************/ | |
1686 | ||
2467ca46 BH |
1687 | /* Tears down the entire software state and most of the hardware state |
1688 | * before reset. */ | |
4b988280 SH |
1689 | void efx_reset_down(struct efx_nic *efx, enum reset_type method, |
1690 | struct ethtool_cmd *ecmd) | |
8ceee660 | 1691 | { |
8ceee660 BH |
1692 | EFX_ASSERT_RESET_SERIALISED(efx); |
1693 | ||
1974cc20 | 1694 | efx_stats_disable(efx); |
2467ca46 BH |
1695 | efx_stop_all(efx); |
1696 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1697 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1698 | |
177dfcd8 | 1699 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1700 | |
1701 | efx_fini_channels(efx); | |
4b988280 SH |
1702 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1703 | efx->phy_op->fini(efx); | |
8ceee660 BH |
1704 | } |
1705 | ||
2467ca46 BH |
1706 | /* This function will always ensure that the locks acquired in |
1707 | * efx_reset_down() are released. A failure return code indicates | |
1708 | * that we were unable to reinitialise the hardware, and the | |
1709 | * driver should be disabled. If ok is false, then the rx and tx | |
1710 | * engines are not restarted, pending a RESET_DISABLE. */ | |
4b988280 SH |
1711 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, |
1712 | struct ethtool_cmd *ecmd, bool ok) | |
8ceee660 BH |
1713 | { |
1714 | int rc; | |
1715 | ||
2467ca46 | 1716 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1717 | |
2467ca46 | 1718 | rc = falcon_init_nic(efx); |
8ceee660 | 1719 | if (rc) { |
2467ca46 BH |
1720 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1721 | ok = false; | |
8ceee660 BH |
1722 | } |
1723 | ||
4b988280 SH |
1724 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
1725 | if (ok) { | |
1726 | rc = efx->phy_op->init(efx); | |
1727 | if (rc) | |
1728 | ok = false; | |
115122af BH |
1729 | } |
1730 | if (!ok) | |
4b988280 SH |
1731 | efx->port_initialized = false; |
1732 | } | |
1733 | ||
2467ca46 BH |
1734 | if (ok) { |
1735 | efx_init_channels(efx); | |
8ceee660 | 1736 | |
177dfcd8 | 1737 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1738 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1739 | } | |
1740 | ||
f4150724 | 1741 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1742 | mutex_unlock(&efx->mac_lock); |
1743 | ||
8c8661e4 | 1744 | if (ok) { |
2467ca46 | 1745 | efx_start_all(efx); |
1974cc20 | 1746 | efx_stats_enable(efx); |
8c8661e4 | 1747 | } |
8ceee660 BH |
1748 | return rc; |
1749 | } | |
1750 | ||
1751 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1752 | * Note that the reset may fail, in which case the card will be left | |
1753 | * in a most-probably-unusable state. | |
1754 | * | |
1755 | * This function will sleep. You cannot reset from within an atomic | |
1756 | * state; use efx_schedule_reset() instead. | |
1757 | * | |
1758 | * Grabs the rtnl_lock. | |
1759 | */ | |
1760 | static int efx_reset(struct efx_nic *efx) | |
1761 | { | |
1762 | struct ethtool_cmd ecmd; | |
1763 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1764 | int rc = 0; |
8ceee660 BH |
1765 | |
1766 | /* Serialise with kernel interfaces */ | |
1767 | rtnl_lock(); | |
1768 | ||
1769 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1770 | * flag set so that efx_pci_probe_main will be retried */ | |
1771 | if (efx->state != STATE_RUNNING) { | |
1772 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1773 | goto out_unlock; |
8ceee660 BH |
1774 | } |
1775 | ||
8ceee660 BH |
1776 | EFX_INFO(efx, "resetting (%d)\n", method); |
1777 | ||
4b988280 | 1778 | efx_reset_down(efx, method, &ecmd); |
8ceee660 BH |
1779 | |
1780 | rc = falcon_reset_hw(efx, method); | |
1781 | if (rc) { | |
1782 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1783 | goto out_disable; |
8ceee660 BH |
1784 | } |
1785 | ||
1786 | /* Allow resets to be rescheduled. */ | |
1787 | efx->reset_pending = RESET_TYPE_NONE; | |
1788 | ||
1789 | /* Reinitialise bus-mastering, which may have been turned off before | |
1790 | * the reset was scheduled. This is still appropriate, even in the | |
1791 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1792 | * can respond to requests. */ | |
1793 | pci_set_master(efx->pci_dev); | |
1794 | ||
8ceee660 BH |
1795 | /* Leave device stopped if necessary */ |
1796 | if (method == RESET_TYPE_DISABLE) { | |
4b988280 | 1797 | efx_reset_up(efx, method, &ecmd, false); |
8ceee660 | 1798 | rc = -EIO; |
f4bd954e | 1799 | } else { |
4b988280 | 1800 | rc = efx_reset_up(efx, method, &ecmd, true); |
8ceee660 BH |
1801 | } |
1802 | ||
f4bd954e BH |
1803 | out_disable: |
1804 | if (rc) { | |
1805 | EFX_ERR(efx, "has been disabled\n"); | |
1806 | efx->state = STATE_DISABLED; | |
1807 | dev_close(efx->net_dev); | |
1808 | } else { | |
1809 | EFX_LOG(efx, "reset complete\n"); | |
1810 | } | |
8ceee660 | 1811 | |
f4bd954e | 1812 | out_unlock: |
8ceee660 | 1813 | rtnl_unlock(); |
8ceee660 BH |
1814 | return rc; |
1815 | } | |
1816 | ||
1817 | /* The worker thread exists so that code that cannot sleep can | |
1818 | * schedule a reset for later. | |
1819 | */ | |
1820 | static void efx_reset_work(struct work_struct *data) | |
1821 | { | |
1822 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1823 | ||
1824 | efx_reset(nic); | |
1825 | } | |
1826 | ||
1827 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1828 | { | |
1829 | enum reset_type method; | |
1830 | ||
1831 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1832 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1833 | return; | |
1834 | } | |
1835 | ||
1836 | switch (type) { | |
1837 | case RESET_TYPE_INVISIBLE: | |
1838 | case RESET_TYPE_ALL: | |
1839 | case RESET_TYPE_WORLD: | |
1840 | case RESET_TYPE_DISABLE: | |
1841 | method = type; | |
1842 | break; | |
1843 | case RESET_TYPE_RX_RECOVERY: | |
1844 | case RESET_TYPE_RX_DESC_FETCH: | |
1845 | case RESET_TYPE_TX_DESC_FETCH: | |
1846 | case RESET_TYPE_TX_SKIP: | |
1847 | method = RESET_TYPE_INVISIBLE; | |
1848 | break; | |
1849 | default: | |
1850 | method = RESET_TYPE_ALL; | |
1851 | break; | |
1852 | } | |
1853 | ||
1854 | if (method != type) | |
1855 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1856 | else | |
1857 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1858 | ||
1859 | efx->reset_pending = method; | |
1860 | ||
1ab00629 | 1861 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1862 | } |
1863 | ||
1864 | /************************************************************************** | |
1865 | * | |
1866 | * List of NICs we support | |
1867 | * | |
1868 | **************************************************************************/ | |
1869 | ||
1870 | /* PCI device ID table */ | |
1871 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1872 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1873 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1874 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1875 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1876 | {0} /* end of list */ | |
1877 | }; | |
1878 | ||
1879 | /************************************************************************** | |
1880 | * | |
1881 | * Dummy PHY/MAC/Board operations | |
1882 | * | |
01aad7b6 | 1883 | * Can be used for some unimplemented operations |
8ceee660 BH |
1884 | * Needed so all function pointers are valid and do not have to be tested |
1885 | * before use | |
1886 | * | |
1887 | **************************************************************************/ | |
1888 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1889 | { | |
1890 | return 0; | |
1891 | } | |
1892 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
1893 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1894 | { | |
1895 | } | |
8ceee660 | 1896 | |
177dfcd8 BH |
1897 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1898 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa BH |
1899 | .poll = efx_port_dummy_op_void, |
1900 | .irq = efx_port_dummy_op_void, | |
177dfcd8 BH |
1901 | }; |
1902 | ||
8ceee660 BH |
1903 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1904 | .init = efx_port_dummy_op_int, | |
1905 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1906 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1907 | .fini = efx_port_dummy_op_void, |
1908 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1909 | }; |
1910 | ||
278c0621 | 1911 | static struct falcon_board efx_dummy_board_info = { |
01aad7b6 | 1912 | .init = efx_port_dummy_op_int, |
981fc1b4 | 1913 | .init_phy = efx_port_dummy_op_void, |
398468ed | 1914 | .set_id_led = efx_port_dummy_op_set_id_led, |
a17102b1 | 1915 | .monitor = efx_port_dummy_op_int, |
01aad7b6 | 1916 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
1917 | }; |
1918 | ||
1919 | /************************************************************************** | |
1920 | * | |
1921 | * Data housekeeping | |
1922 | * | |
1923 | **************************************************************************/ | |
1924 | ||
1925 | /* This zeroes out and then fills in the invariants in a struct | |
1926 | * efx_nic (including all sub-structures). | |
1927 | */ | |
1928 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1929 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1930 | { | |
1931 | struct efx_channel *channel; | |
1932 | struct efx_tx_queue *tx_queue; | |
1933 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1934 | int i; |
8ceee660 BH |
1935 | |
1936 | /* Initialise common structures */ | |
1937 | memset(efx, 0, sizeof(*efx)); | |
1938 | spin_lock_init(&efx->biu_lock); | |
1939 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1940 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1941 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1942 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1943 | efx->pci_dev = pci_dev; | |
1944 | efx->state = STATE_INIT; | |
1945 | efx->reset_pending = RESET_TYPE_NONE; | |
1946 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1947 | efx->board_info = efx_dummy_board_info; | |
1948 | ||
1949 | efx->net_dev = net_dev; | |
dc8cfa55 | 1950 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1951 | spin_lock_init(&efx->netif_stop_lock); |
1952 | spin_lock_init(&efx->stats_lock); | |
1974cc20 | 1953 | efx->stats_disable_count = 1; |
8ceee660 | 1954 | mutex_init(&efx->mac_lock); |
177dfcd8 | 1955 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 | 1956 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 1957 | efx->mdio.dev = net_dev; |
766ca0fa BH |
1958 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1959 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1960 | atomic_set(&efx->netif_stop_count, 1); |
1961 | ||
1962 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1963 | channel = &efx->channel[i]; | |
1964 | channel->efx = efx; | |
1965 | channel->channel = i; | |
dc8cfa55 | 1966 | channel->work_pending = false; |
8ceee660 | 1967 | } |
60ac1065 | 1968 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1969 | tx_queue = &efx->tx_queue[i]; |
1970 | tx_queue->efx = efx; | |
1971 | tx_queue->queue = i; | |
1972 | tx_queue->buffer = NULL; | |
1973 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1974 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1975 | } |
1976 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1977 | rx_queue = &efx->rx_queue[i]; | |
1978 | rx_queue->efx = efx; | |
1979 | rx_queue->queue = i; | |
1980 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1981 | rx_queue->buffer = NULL; | |
1982 | spin_lock_init(&rx_queue->add_lock); | |
1983 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1984 | } | |
1985 | ||
1986 | efx->type = type; | |
1987 | ||
8ceee660 | 1988 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
1989 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
1990 | ||
8ceee660 BH |
1991 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
1992 | ||
1993 | /* Higher numbered interrupt modes are less capable! */ | |
1994 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1995 | interrupt_mode); | |
1996 | ||
6977dc63 BH |
1997 | /* Would be good to use the net_dev name, but we're too early */ |
1998 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
1999 | pci_name(pci_dev)); | |
2000 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2001 | if (!efx->workqueue) |
2002 | return -ENOMEM; | |
8d9853d9 | 2003 | |
8ceee660 | 2004 | return 0; |
8ceee660 BH |
2005 | } |
2006 | ||
2007 | static void efx_fini_struct(struct efx_nic *efx) | |
2008 | { | |
2009 | if (efx->workqueue) { | |
2010 | destroy_workqueue(efx->workqueue); | |
2011 | efx->workqueue = NULL; | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | /************************************************************************** | |
2016 | * | |
2017 | * PCI interface | |
2018 | * | |
2019 | **************************************************************************/ | |
2020 | ||
2021 | /* Main body of final NIC shutdown code | |
2022 | * This is called only at module unload (or hotplug removal). | |
2023 | */ | |
2024 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2025 | { | |
f01865f0 | 2026 | falcon_fini_interrupt(efx); |
8ceee660 BH |
2027 | efx_fini_channels(efx); |
2028 | efx_fini_port(efx); | |
8ceee660 BH |
2029 | efx_fini_napi(efx); |
2030 | efx_remove_all(efx); | |
2031 | } | |
2032 | ||
2033 | /* Final NIC shutdown | |
2034 | * This is called only at module unload (or hotplug removal). | |
2035 | */ | |
2036 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2037 | { | |
2038 | struct efx_nic *efx; | |
2039 | ||
2040 | efx = pci_get_drvdata(pci_dev); | |
2041 | if (!efx) | |
2042 | return; | |
2043 | ||
2044 | /* Mark the NIC as fini, then stop the interface */ | |
2045 | rtnl_lock(); | |
2046 | efx->state = STATE_FINI; | |
2047 | dev_close(efx->net_dev); | |
2048 | ||
2049 | /* Allow any queued efx_resets() to complete */ | |
2050 | rtnl_unlock(); | |
2051 | ||
8ceee660 BH |
2052 | efx_unregister_netdev(efx); |
2053 | ||
7dde596e BH |
2054 | efx_mtd_remove(efx); |
2055 | ||
8ceee660 BH |
2056 | /* Wait for any scheduled resets to complete. No more will be |
2057 | * scheduled from this point because efx_stop_all() has been | |
2058 | * called, we are no longer registered with driverlink, and | |
2059 | * the net_device's have been removed. */ | |
1ab00629 | 2060 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2061 | |
2062 | efx_pci_remove_main(efx); | |
2063 | ||
8ceee660 BH |
2064 | efx_fini_io(efx); |
2065 | EFX_LOG(efx, "shutdown successful\n"); | |
2066 | ||
2067 | pci_set_drvdata(pci_dev, NULL); | |
2068 | efx_fini_struct(efx); | |
2069 | free_netdev(efx->net_dev); | |
2070 | }; | |
2071 | ||
2072 | /* Main body of NIC initialisation | |
2073 | * This is called at module load (or hotplug insertion, theoretically). | |
2074 | */ | |
2075 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2076 | { | |
2077 | int rc; | |
2078 | ||
2079 | /* Do start-of-day initialisation */ | |
2080 | rc = efx_probe_all(efx); | |
2081 | if (rc) | |
2082 | goto fail1; | |
2083 | ||
2084 | rc = efx_init_napi(efx); | |
2085 | if (rc) | |
2086 | goto fail2; | |
2087 | ||
8ceee660 BH |
2088 | rc = falcon_init_nic(efx); |
2089 | if (rc) { | |
2090 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
278c0621 | 2091 | goto fail3; |
8ceee660 BH |
2092 | } |
2093 | ||
2094 | rc = efx_init_port(efx); | |
2095 | if (rc) { | |
2096 | EFX_ERR(efx, "failed to initialise port\n"); | |
278c0621 | 2097 | goto fail4; |
8ceee660 BH |
2098 | } |
2099 | ||
bc3c90a2 | 2100 | efx_init_channels(efx); |
8ceee660 BH |
2101 | |
2102 | rc = falcon_init_interrupt(efx); | |
2103 | if (rc) | |
278c0621 | 2104 | goto fail5; |
8ceee660 BH |
2105 | |
2106 | return 0; | |
2107 | ||
278c0621 | 2108 | fail5: |
bc3c90a2 | 2109 | efx_fini_channels(efx); |
8ceee660 | 2110 | efx_fini_port(efx); |
8ceee660 BH |
2111 | fail4: |
2112 | fail3: | |
2113 | efx_fini_napi(efx); | |
2114 | fail2: | |
2115 | efx_remove_all(efx); | |
2116 | fail1: | |
2117 | return rc; | |
2118 | } | |
2119 | ||
2120 | /* NIC initialisation | |
2121 | * | |
2122 | * This is called at module load (or hotplug insertion, | |
2123 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2124 | * sets up and registers the network devices with the kernel and hooks | |
2125 | * the interrupt service routine. It does not prepare the device for | |
2126 | * transmission; this is left to the first time one of the network | |
2127 | * interfaces is brought up (i.e. efx_net_open). | |
2128 | */ | |
2129 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2130 | const struct pci_device_id *entry) | |
2131 | { | |
2132 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2133 | struct net_device *net_dev; | |
2134 | struct efx_nic *efx; | |
2135 | int i, rc; | |
2136 | ||
2137 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2138 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2139 | if (!net_dev) | |
2140 | return -ENOMEM; | |
b9b39b62 | 2141 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
97bc5415 BH |
2142 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2143 | NETIF_F_GRO); | |
28506563 BH |
2144 | /* Mask for features that also apply to VLAN devices */ |
2145 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2146 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2147 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2148 | pci_set_drvdata(pci_dev, efx); |
2149 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2150 | if (rc) | |
2151 | goto fail1; | |
2152 | ||
2153 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2154 | ||
2155 | /* Set up basic I/O (BAR mappings etc) */ | |
2156 | rc = efx_init_io(efx); | |
2157 | if (rc) | |
2158 | goto fail2; | |
2159 | ||
2160 | /* No serialisation is required with the reset path because | |
2161 | * we're in STATE_INIT. */ | |
2162 | for (i = 0; i < 5; i++) { | |
2163 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2164 | |
2165 | /* Serialise against efx_reset(). No more resets will be | |
2166 | * scheduled since efx_stop_all() has been called, and we | |
2167 | * have not and never have been registered with either | |
2168 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2169 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2170 | |
fa402b2e SH |
2171 | if (rc == 0) { |
2172 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2173 | /* If there was a scheduled reset during | |
2174 | * probe, the NIC is probably hosed anyway */ | |
2175 | efx_pci_remove_main(efx); | |
2176 | rc = -EIO; | |
2177 | } else { | |
2178 | break; | |
2179 | } | |
2180 | } | |
2181 | ||
8ceee660 BH |
2182 | /* Retry if a recoverably reset event has been scheduled */ |
2183 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2184 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2185 | goto fail3; | |
2186 | ||
2187 | efx->reset_pending = RESET_TYPE_NONE; | |
2188 | } | |
2189 | ||
2190 | if (rc) { | |
2191 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2192 | goto fail4; | |
2193 | } | |
2194 | ||
2195 | /* Switch to the running state before we expose the device to | |
2196 | * the OS. This is to ensure that the initial gathering of | |
2197 | * MAC stats succeeds. */ | |
8ceee660 | 2198 | efx->state = STATE_RUNNING; |
7dde596e | 2199 | |
8ceee660 BH |
2200 | rc = efx_register_netdev(efx); |
2201 | if (rc) | |
2202 | goto fail5; | |
2203 | ||
2204 | EFX_LOG(efx, "initialisation successful\n"); | |
a5211bb5 BH |
2205 | |
2206 | rtnl_lock(); | |
2207 | efx_mtd_probe(efx); /* allowed to fail */ | |
2208 | rtnl_unlock(); | |
8ceee660 BH |
2209 | return 0; |
2210 | ||
2211 | fail5: | |
2212 | efx_pci_remove_main(efx); | |
2213 | fail4: | |
2214 | fail3: | |
2215 | efx_fini_io(efx); | |
2216 | fail2: | |
2217 | efx_fini_struct(efx); | |
2218 | fail1: | |
2219 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2220 | free_netdev(net_dev); | |
2221 | return rc; | |
2222 | } | |
2223 | ||
2224 | static struct pci_driver efx_pci_driver = { | |
2225 | .name = EFX_DRIVER_NAME, | |
2226 | .id_table = efx_pci_table, | |
2227 | .probe = efx_pci_probe, | |
2228 | .remove = efx_pci_remove, | |
2229 | }; | |
2230 | ||
2231 | /************************************************************************** | |
2232 | * | |
2233 | * Kernel module interface | |
2234 | * | |
2235 | *************************************************************************/ | |
2236 | ||
2237 | module_param(interrupt_mode, uint, 0444); | |
2238 | MODULE_PARM_DESC(interrupt_mode, | |
2239 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2240 | ||
2241 | static int __init efx_init_module(void) | |
2242 | { | |
2243 | int rc; | |
2244 | ||
2245 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2246 | ||
2247 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2248 | if (rc) | |
2249 | goto err_notifier; | |
2250 | ||
2251 | refill_workqueue = create_workqueue("sfc_refill"); | |
2252 | if (!refill_workqueue) { | |
2253 | rc = -ENOMEM; | |
2254 | goto err_refill; | |
2255 | } | |
1ab00629 SH |
2256 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2257 | if (!reset_workqueue) { | |
2258 | rc = -ENOMEM; | |
2259 | goto err_reset; | |
2260 | } | |
8ceee660 BH |
2261 | |
2262 | rc = pci_register_driver(&efx_pci_driver); | |
2263 | if (rc < 0) | |
2264 | goto err_pci; | |
2265 | ||
2266 | return 0; | |
2267 | ||
2268 | err_pci: | |
1ab00629 SH |
2269 | destroy_workqueue(reset_workqueue); |
2270 | err_reset: | |
8ceee660 BH |
2271 | destroy_workqueue(refill_workqueue); |
2272 | err_refill: | |
2273 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2274 | err_notifier: | |
2275 | return rc; | |
2276 | } | |
2277 | ||
2278 | static void __exit efx_exit_module(void) | |
2279 | { | |
2280 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2281 | ||
2282 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2283 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2284 | destroy_workqueue(refill_workqueue); |
2285 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2286 | ||
2287 | } | |
2288 | ||
2289 | module_init(efx_init_module); | |
2290 | module_exit(efx_exit_module); | |
2291 | ||
2292 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2293 | "Solarflare Communications"); | |
2294 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2295 | MODULE_LICENSE("GPL"); | |
2296 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |