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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
8ceee660 | 24 | #include "net_driver.h" |
8ceee660 BH |
25 | #include "efx.h" |
26 | #include "mdio_10g.h" | |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
71 | /* Interrupt mode names (see INT_MODE())) */ | |
72 | const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX; | |
73 | const char *efx_interrupt_mode_names[] = { | |
74 | [EFX_INT_MODE_MSIX] = "MSI-X", | |
75 | [EFX_INT_MODE_MSI] = "MSI", | |
76 | [EFX_INT_MODE_LEGACY] = "legacy", | |
77 | }; | |
78 | ||
79 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; | |
80 | const char *efx_reset_type_names[] = { | |
81 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
82 | [RESET_TYPE_ALL] = "ALL", | |
83 | [RESET_TYPE_WORLD] = "WORLD", | |
84 | [RESET_TYPE_DISABLE] = "DISABLE", | |
85 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
86 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
87 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
88 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
89 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
90 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 91 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
92 | }; |
93 | ||
8ceee660 BH |
94 | #define EFX_MAX_MTU (9 * 1024) |
95 | ||
1ab00629 SH |
96 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
97 | * queued onto this work queue. This is not a per-nic work queue, because | |
98 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
99 | */ | |
100 | static struct workqueue_struct *reset_workqueue; | |
101 | ||
8ceee660 BH |
102 | /************************************************************************** |
103 | * | |
104 | * Configurable values | |
105 | * | |
106 | *************************************************************************/ | |
107 | ||
8ceee660 BH |
108 | /* |
109 | * Use separate channels for TX and RX events | |
110 | * | |
28b581ab NT |
111 | * Set this to 1 to use separate channels for TX and RX. It allows us |
112 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 113 | * |
28b581ab | 114 | * This is only used in MSI-X interrupt mode |
8ceee660 | 115 | */ |
28b581ab NT |
116 | static unsigned int separate_tx_channels; |
117 | module_param(separate_tx_channels, uint, 0644); | |
118 | MODULE_PARM_DESC(separate_tx_channels, | |
119 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
120 | |
121 | /* This is the weight assigned to each of the (per-channel) virtual | |
122 | * NAPI devices. | |
123 | */ | |
124 | static int napi_weight = 64; | |
125 | ||
126 | /* This is the time (in jiffies) between invocations of the hardware | |
127 | * monitor, which checks for known hardware bugs and resets the | |
128 | * hardware and driver as necessary. | |
129 | */ | |
130 | unsigned int efx_monitor_interval = 1 * HZ; | |
131 | ||
8ceee660 BH |
132 | /* This controls whether or not the driver will initialise devices |
133 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
134 | * such devices will be initialised with a random locally-generated | |
135 | * MAC address. This allows for loading the sfc_mtd driver to | |
136 | * reprogram the flash, even if the flash contents (including the MAC | |
137 | * address) have previously been erased. | |
138 | */ | |
139 | static unsigned int allow_bad_hwaddr; | |
140 | ||
141 | /* Initial interrupt moderation settings. They can be modified after | |
142 | * module load with ethtool. | |
143 | * | |
144 | * The default for RX should strike a balance between increasing the | |
145 | * round-trip latency and reducing overhead. | |
146 | */ | |
147 | static unsigned int rx_irq_mod_usec = 60; | |
148 | ||
149 | /* Initial interrupt moderation settings. They can be modified after | |
150 | * module load with ethtool. | |
151 | * | |
152 | * This default is chosen to ensure that a 10G link does not go idle | |
153 | * while a TX queue is stopped after it has become full. A queue is | |
154 | * restarted when it drops below half full. The time this takes (assuming | |
155 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
156 | * 512 / 3 * 1.2 = 205 usec. | |
157 | */ | |
158 | static unsigned int tx_irq_mod_usec = 150; | |
159 | ||
160 | /* This is the first interrupt mode to try out of: | |
161 | * 0 => MSI-X | |
162 | * 1 => MSI | |
163 | * 2 => legacy | |
164 | */ | |
165 | static unsigned int interrupt_mode; | |
166 | ||
167 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
168 | * i.e. the number of CPUs among which we may distribute simultaneous | |
169 | * interrupt handling. | |
170 | * | |
171 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
172 | * The default (0) means to assign an interrupt to each package (level II cache) | |
173 | */ | |
174 | static unsigned int rss_cpus; | |
175 | module_param(rss_cpus, uint, 0444); | |
176 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
177 | ||
84ae48fe BH |
178 | static int phy_flash_cfg; |
179 | module_param(phy_flash_cfg, int, 0644); | |
180 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
181 | ||
6fb70fd1 BH |
182 | static unsigned irq_adapt_low_thresh = 10000; |
183 | module_param(irq_adapt_low_thresh, uint, 0644); | |
184 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
185 | "Threshold score for reducing IRQ moderation"); | |
186 | ||
187 | static unsigned irq_adapt_high_thresh = 20000; | |
188 | module_param(irq_adapt_high_thresh, uint, 0644); | |
189 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
190 | "Threshold score for increasing IRQ moderation"); | |
191 | ||
62776d03 BH |
192 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
193 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
194 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
195 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
196 | module_param(debug, uint, 0); | |
197 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
198 | ||
8ceee660 BH |
199 | /************************************************************************** |
200 | * | |
201 | * Utility functions and prototypes | |
202 | * | |
203 | *************************************************************************/ | |
204 | static void efx_remove_channel(struct efx_channel *channel); | |
205 | static void efx_remove_port(struct efx_nic *efx); | |
206 | static void efx_fini_napi(struct efx_nic *efx); | |
207 | static void efx_fini_channels(struct efx_nic *efx); | |
208 | ||
209 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
210 | do { \ | |
332c1ce9 BH |
211 | if ((efx->state == STATE_RUNNING) || \ |
212 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
213 | ASSERT_RTNL(); \ |
214 | } while (0) | |
215 | ||
216 | /************************************************************************** | |
217 | * | |
218 | * Event queue processing | |
219 | * | |
220 | *************************************************************************/ | |
221 | ||
222 | /* Process channel's event queue | |
223 | * | |
224 | * This function is responsible for processing the event queue of a | |
225 | * single channel. The caller must guarantee that this function will | |
226 | * never be concurrently called more than once on the same channel, | |
227 | * though different channels may be being processed concurrently. | |
228 | */ | |
fa236e18 | 229 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 230 | { |
42cbe2d7 | 231 | struct efx_nic *efx = channel->efx; |
fa236e18 | 232 | int spent; |
8ceee660 | 233 | |
42cbe2d7 | 234 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 235 | !channel->enabled)) |
42cbe2d7 | 236 | return 0; |
8ceee660 | 237 | |
fa236e18 BH |
238 | spent = efx_nic_process_eventq(channel, budget); |
239 | if (spent == 0) | |
42cbe2d7 | 240 | return 0; |
8ceee660 BH |
241 | |
242 | /* Deliver last RX packet. */ | |
243 | if (channel->rx_pkt) { | |
244 | __efx_rx_packet(channel, channel->rx_pkt, | |
245 | channel->rx_pkt_csummed); | |
246 | channel->rx_pkt = NULL; | |
247 | } | |
248 | ||
8ceee660 BH |
249 | efx_rx_strategy(channel); |
250 | ||
42cbe2d7 | 251 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 252 | |
fa236e18 | 253 | return spent; |
8ceee660 BH |
254 | } |
255 | ||
256 | /* Mark channel as finished processing | |
257 | * | |
258 | * Note that since we will not receive further interrupts for this | |
259 | * channel before we finish processing and call the eventq_read_ack() | |
260 | * method, there is no need to use the interrupt hold-off timers. | |
261 | */ | |
262 | static inline void efx_channel_processed(struct efx_channel *channel) | |
263 | { | |
5b9e207c BH |
264 | /* The interrupt handler for this channel may set work_pending |
265 | * as soon as we acknowledge the events we've seen. Make sure | |
266 | * it's cleared before then. */ | |
dc8cfa55 | 267 | channel->work_pending = false; |
5b9e207c BH |
268 | smp_wmb(); |
269 | ||
152b6a62 | 270 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
271 | } |
272 | ||
273 | /* NAPI poll handler | |
274 | * | |
275 | * NAPI guarantees serialisation of polls of the same device, which | |
276 | * provides the guarantee required by efx_process_channel(). | |
277 | */ | |
278 | static int efx_poll(struct napi_struct *napi, int budget) | |
279 | { | |
280 | struct efx_channel *channel = | |
281 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 282 | struct efx_nic *efx = channel->efx; |
fa236e18 | 283 | int spent; |
8ceee660 | 284 | |
62776d03 BH |
285 | netif_vdbg(efx, intr, efx->net_dev, |
286 | "channel %d NAPI poll executing on CPU %d\n", | |
287 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 288 | |
fa236e18 | 289 | spent = efx_process_channel(channel, budget); |
8ceee660 | 290 | |
fa236e18 | 291 | if (spent < budget) { |
a4900ac9 | 292 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
293 | efx->irq_rx_adaptive && |
294 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
295 | if (unlikely(channel->irq_mod_score < |
296 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
297 | if (channel->irq_moderation > 1) { |
298 | channel->irq_moderation -= 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 BH |
301 | } else if (unlikely(channel->irq_mod_score > |
302 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
303 | if (channel->irq_moderation < |
304 | efx->irq_rx_moderation) { | |
305 | channel->irq_moderation += 1; | |
ef2b90ee | 306 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 307 | } |
6fb70fd1 | 308 | } |
6fb70fd1 BH |
309 | channel->irq_count = 0; |
310 | channel->irq_mod_score = 0; | |
311 | } | |
312 | ||
8ceee660 | 313 | /* There is no race here; although napi_disable() will |
288379f0 | 314 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
315 | * since efx_channel_processed() will have no effect if |
316 | * interrupts have already been disabled. | |
317 | */ | |
288379f0 | 318 | napi_complete(napi); |
8ceee660 BH |
319 | efx_channel_processed(channel); |
320 | } | |
321 | ||
fa236e18 | 322 | return spent; |
8ceee660 BH |
323 | } |
324 | ||
325 | /* Process the eventq of the specified channel immediately on this CPU | |
326 | * | |
327 | * Disable hardware generated interrupts, wait for any existing | |
328 | * processing to finish, then directly poll (and ack ) the eventq. | |
329 | * Finally reenable NAPI and interrupts. | |
330 | * | |
331 | * Since we are touching interrupts the caller should hold the suspend lock | |
332 | */ | |
333 | void efx_process_channel_now(struct efx_channel *channel) | |
334 | { | |
335 | struct efx_nic *efx = channel->efx; | |
336 | ||
8ceee660 BH |
337 | BUG_ON(!channel->enabled); |
338 | ||
339 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 340 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
341 | if (efx->legacy_irq) |
342 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 343 | if (channel->irq) |
8ceee660 BH |
344 | synchronize_irq(channel->irq); |
345 | ||
346 | /* Wait for any NAPI processing to complete */ | |
347 | napi_disable(&channel->napi_str); | |
348 | ||
349 | /* Poll the channel */ | |
3ffeabdd | 350 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
351 | |
352 | /* Ack the eventq. This may cause an interrupt to be generated | |
353 | * when they are reenabled */ | |
354 | efx_channel_processed(channel); | |
355 | ||
356 | napi_enable(&channel->napi_str); | |
152b6a62 | 357 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
358 | } |
359 | ||
360 | /* Create event queue | |
361 | * Event queue memory allocations are done only once. If the channel | |
362 | * is reset, the memory buffer will be reused; this guards against | |
363 | * errors during channel reset and also simplifies interrupt handling. | |
364 | */ | |
365 | static int efx_probe_eventq(struct efx_channel *channel) | |
366 | { | |
62776d03 BH |
367 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
368 | "chan %d create event queue\n", channel->channel); | |
8ceee660 | 369 | |
152b6a62 | 370 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
371 | } |
372 | ||
373 | /* Prepare channel's event queue */ | |
bc3c90a2 | 374 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 375 | { |
62776d03 BH |
376 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
377 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
378 | |
379 | channel->eventq_read_ptr = 0; | |
380 | ||
152b6a62 | 381 | efx_nic_init_eventq(channel); |
8ceee660 BH |
382 | } |
383 | ||
384 | static void efx_fini_eventq(struct efx_channel *channel) | |
385 | { | |
62776d03 BH |
386 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
387 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 388 | |
152b6a62 | 389 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
390 | } |
391 | ||
392 | static void efx_remove_eventq(struct efx_channel *channel) | |
393 | { | |
62776d03 BH |
394 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
395 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 396 | |
152b6a62 | 397 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
398 | } |
399 | ||
400 | /************************************************************************** | |
401 | * | |
402 | * Channel handling | |
403 | * | |
404 | *************************************************************************/ | |
405 | ||
8ceee660 BH |
406 | static int efx_probe_channel(struct efx_channel *channel) |
407 | { | |
408 | struct efx_tx_queue *tx_queue; | |
409 | struct efx_rx_queue *rx_queue; | |
410 | int rc; | |
411 | ||
62776d03 BH |
412 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
413 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
414 | |
415 | rc = efx_probe_eventq(channel); | |
416 | if (rc) | |
417 | goto fail1; | |
418 | ||
419 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
420 | rc = efx_probe_tx_queue(tx_queue); | |
421 | if (rc) | |
422 | goto fail2; | |
423 | } | |
424 | ||
425 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
426 | rc = efx_probe_rx_queue(rx_queue); | |
427 | if (rc) | |
428 | goto fail3; | |
429 | } | |
430 | ||
431 | channel->n_rx_frm_trunc = 0; | |
432 | ||
433 | return 0; | |
434 | ||
435 | fail3: | |
436 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
437 | efx_remove_rx_queue(rx_queue); | |
438 | fail2: | |
439 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
440 | efx_remove_tx_queue(tx_queue); | |
441 | fail1: | |
442 | return rc; | |
443 | } | |
444 | ||
445 | ||
56536e9c BH |
446 | static void efx_set_channel_names(struct efx_nic *efx) |
447 | { | |
448 | struct efx_channel *channel; | |
449 | const char *type = ""; | |
450 | int number; | |
451 | ||
452 | efx_for_each_channel(channel, efx) { | |
453 | number = channel->channel; | |
a4900ac9 BH |
454 | if (efx->n_channels > efx->n_rx_channels) { |
455 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
456 | type = "-rx"; |
457 | } else { | |
458 | type = "-tx"; | |
a4900ac9 | 459 | number -= efx->n_rx_channels; |
56536e9c BH |
460 | } |
461 | } | |
462 | snprintf(channel->name, sizeof(channel->name), | |
463 | "%s%s-%d", efx->name, type, number); | |
464 | } | |
465 | } | |
466 | ||
8ceee660 BH |
467 | /* Channels are shutdown and reinitialised whilst the NIC is running |
468 | * to propagate configuration changes (mtu, checksum offload), or | |
469 | * to clear hardware error conditions | |
470 | */ | |
bc3c90a2 | 471 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
472 | { |
473 | struct efx_tx_queue *tx_queue; | |
474 | struct efx_rx_queue *rx_queue; | |
475 | struct efx_channel *channel; | |
8ceee660 | 476 | |
f7f13b0b BH |
477 | /* Calculate the rx buffer allocation parameters required to |
478 | * support the current MTU, including padding for header | |
479 | * alignment and overruns. | |
480 | */ | |
481 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
482 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
483 | efx->type->rx_buffer_padding); | |
62b330ba SH |
484 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
485 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
486 | |
487 | /* Initialise the channels */ | |
488 | efx_for_each_channel(channel, efx) { | |
62776d03 BH |
489 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
490 | "init chan %d\n", channel->channel); | |
8ceee660 | 491 | |
bc3c90a2 | 492 | efx_init_eventq(channel); |
8ceee660 | 493 | |
bc3c90a2 BH |
494 | efx_for_each_channel_tx_queue(tx_queue, channel) |
495 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
496 | |
497 | /* The rx buffer allocation strategy is MTU dependent */ | |
498 | efx_rx_strategy(channel); | |
499 | ||
bc3c90a2 BH |
500 | efx_for_each_channel_rx_queue(rx_queue, channel) |
501 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
502 | |
503 | WARN_ON(channel->rx_pkt != NULL); | |
504 | efx_rx_strategy(channel); | |
505 | } | |
8ceee660 BH |
506 | } |
507 | ||
508 | /* This enables event queue processing and packet transmission. | |
509 | * | |
510 | * Note that this function is not allowed to fail, since that would | |
511 | * introduce too much complexity into the suspend/resume path. | |
512 | */ | |
513 | static void efx_start_channel(struct efx_channel *channel) | |
514 | { | |
515 | struct efx_rx_queue *rx_queue; | |
516 | ||
62776d03 BH |
517 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, |
518 | "starting chan %d\n", channel->channel); | |
8ceee660 | 519 | |
5b9e207c BH |
520 | /* The interrupt handler for this channel may set work_pending |
521 | * as soon as we enable it. Make sure it's cleared before | |
522 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
523 | channel->work_pending = false; |
524 | channel->enabled = true; | |
5b9e207c | 525 | smp_wmb(); |
8ceee660 | 526 | |
90d683af | 527 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
528 | efx_for_each_channel_rx_queue(rx_queue, channel) |
529 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
530 | |
531 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
532 | } |
533 | ||
534 | /* This disables event queue processing and packet transmission. | |
535 | * This function does not guarantee that all queue processing | |
536 | * (e.g. RX refill) is complete. | |
537 | */ | |
538 | static void efx_stop_channel(struct efx_channel *channel) | |
539 | { | |
8ceee660 BH |
540 | if (!channel->enabled) |
541 | return; | |
542 | ||
62776d03 BH |
543 | netif_dbg(channel->efx, ifdown, channel->efx->net_dev, |
544 | "stop chan %d\n", channel->channel); | |
8ceee660 | 545 | |
dc8cfa55 | 546 | channel->enabled = false; |
8ceee660 | 547 | napi_disable(&channel->napi_str); |
8ceee660 BH |
548 | } |
549 | ||
550 | static void efx_fini_channels(struct efx_nic *efx) | |
551 | { | |
552 | struct efx_channel *channel; | |
553 | struct efx_tx_queue *tx_queue; | |
554 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 555 | int rc; |
8ceee660 BH |
556 | |
557 | EFX_ASSERT_RESET_SERIALISED(efx); | |
558 | BUG_ON(efx->port_enabled); | |
559 | ||
152b6a62 | 560 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
561 | if (rc && EFX_WORKAROUND_7803(efx)) { |
562 | /* Schedule a reset to recover from the flush failure. The | |
563 | * descriptor caches reference memory we're about to free, | |
564 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
565 | * the MACs because of the pending reset. */ | |
62776d03 BH |
566 | netif_err(efx, drv, efx->net_dev, |
567 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
568 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
569 | } else if (rc) { | |
62776d03 | 570 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 571 | } else { |
62776d03 BH |
572 | netif_dbg(efx, drv, efx->net_dev, |
573 | "successfully flushed all queues\n"); | |
fd371e32 | 574 | } |
6bc5d3a9 | 575 | |
8ceee660 | 576 | efx_for_each_channel(channel, efx) { |
62776d03 BH |
577 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
578 | "shut down chan %d\n", channel->channel); | |
8ceee660 BH |
579 | |
580 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
581 | efx_fini_rx_queue(rx_queue); | |
582 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
583 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
584 | efx_fini_eventq(channel); |
585 | } | |
586 | } | |
587 | ||
588 | static void efx_remove_channel(struct efx_channel *channel) | |
589 | { | |
590 | struct efx_tx_queue *tx_queue; | |
591 | struct efx_rx_queue *rx_queue; | |
592 | ||
62776d03 BH |
593 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
594 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
595 | |
596 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
597 | efx_remove_rx_queue(rx_queue); | |
598 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
599 | efx_remove_tx_queue(tx_queue); | |
600 | efx_remove_eventq(channel); | |
8ceee660 BH |
601 | } |
602 | ||
90d683af | 603 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 604 | { |
90d683af | 605 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
606 | } |
607 | ||
608 | /************************************************************************** | |
609 | * | |
610 | * Port handling | |
611 | * | |
612 | **************************************************************************/ | |
613 | ||
614 | /* This ensures that the kernel is kept informed (via | |
615 | * netif_carrier_on/off) of the link status, and also maintains the | |
616 | * link status's stop on the port's TX queue. | |
617 | */ | |
fdaa9aed | 618 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 619 | { |
eb50c0d6 BH |
620 | struct efx_link_state *link_state = &efx->link_state; |
621 | ||
8ceee660 BH |
622 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
623 | * that no events are triggered between unregister_netdev() and the | |
624 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
625 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
626 | if (!netif_running(efx->net_dev)) | |
627 | return; | |
628 | ||
8c8661e4 BH |
629 | if (efx->port_inhibited) { |
630 | netif_carrier_off(efx->net_dev); | |
631 | return; | |
632 | } | |
633 | ||
eb50c0d6 | 634 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
635 | efx->n_link_state_changes++; |
636 | ||
eb50c0d6 | 637 | if (link_state->up) |
8ceee660 BH |
638 | netif_carrier_on(efx->net_dev); |
639 | else | |
640 | netif_carrier_off(efx->net_dev); | |
641 | } | |
642 | ||
643 | /* Status message for kernel log */ | |
eb50c0d6 | 644 | if (link_state->up) { |
62776d03 BH |
645 | netif_info(efx, link, efx->net_dev, |
646 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
647 | link_state->speed, link_state->fd ? "full" : "half", | |
648 | efx->net_dev->mtu, | |
649 | (efx->promiscuous ? " [PROMISC]" : "")); | |
8ceee660 | 650 | } else { |
62776d03 | 651 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
652 | } |
653 | ||
654 | } | |
655 | ||
d3245b28 BH |
656 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
657 | { | |
658 | efx->link_advertising = advertising; | |
659 | if (advertising) { | |
660 | if (advertising & ADVERTISED_Pause) | |
661 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
662 | else | |
663 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
664 | if (advertising & ADVERTISED_Asym_Pause) | |
665 | efx->wanted_fc ^= EFX_FC_TX; | |
666 | } | |
667 | } | |
668 | ||
669 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
670 | { | |
671 | efx->wanted_fc = wanted_fc; | |
672 | if (efx->link_advertising) { | |
673 | if (wanted_fc & EFX_FC_RX) | |
674 | efx->link_advertising |= (ADVERTISED_Pause | | |
675 | ADVERTISED_Asym_Pause); | |
676 | else | |
677 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
678 | ADVERTISED_Asym_Pause); | |
679 | if (wanted_fc & EFX_FC_TX) | |
680 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
681 | } | |
682 | } | |
683 | ||
115122af BH |
684 | static void efx_fini_port(struct efx_nic *efx); |
685 | ||
d3245b28 BH |
686 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
687 | * the MAC appropriately. All other PHY configuration changes are pushed | |
688 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
689 | * through efx_monitor(). | |
690 | * | |
691 | * Callers must hold the mac_lock | |
692 | */ | |
693 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 694 | { |
d3245b28 BH |
695 | enum efx_phy_mode phy_mode; |
696 | int rc; | |
8ceee660 | 697 | |
d3245b28 | 698 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 699 | |
a816f75a BH |
700 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
701 | if (efx_dev_registered(efx)) { | |
702 | netif_addr_lock_bh(efx->net_dev); | |
703 | netif_addr_unlock_bh(efx->net_dev); | |
704 | } | |
705 | ||
d3245b28 BH |
706 | /* Disable PHY transmit in mac level loopbacks */ |
707 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
708 | if (LOOPBACK_INTERNAL(efx)) |
709 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
710 | else | |
711 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 712 | |
d3245b28 | 713 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 714 | |
d3245b28 BH |
715 | if (rc) |
716 | efx->phy_mode = phy_mode; | |
177dfcd8 | 717 | |
d3245b28 | 718 | return rc; |
8ceee660 BH |
719 | } |
720 | ||
721 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
722 | * disabled. */ | |
d3245b28 | 723 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 724 | { |
d3245b28 BH |
725 | int rc; |
726 | ||
8ceee660 BH |
727 | EFX_ASSERT_RESET_SERIALISED(efx); |
728 | ||
729 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 730 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 731 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
732 | |
733 | return rc; | |
8ceee660 BH |
734 | } |
735 | ||
8be4f3e6 BH |
736 | /* Asynchronous work item for changing MAC promiscuity and multicast |
737 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
738 | * MAC directly. */ | |
766ca0fa BH |
739 | static void efx_mac_work(struct work_struct *data) |
740 | { | |
741 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
742 | ||
743 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 744 | if (efx->port_enabled) { |
ef2b90ee | 745 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
746 | efx->mac_op->reconfigure(efx); |
747 | } | |
766ca0fa BH |
748 | mutex_unlock(&efx->mac_lock); |
749 | } | |
750 | ||
8ceee660 BH |
751 | static int efx_probe_port(struct efx_nic *efx) |
752 | { | |
753 | int rc; | |
754 | ||
62776d03 | 755 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 756 | |
ff3b00a0 SH |
757 | if (phy_flash_cfg) |
758 | efx->phy_mode = PHY_MODE_SPECIAL; | |
759 | ||
ef2b90ee BH |
760 | /* Connect up MAC/PHY operations table */ |
761 | rc = efx->type->probe_port(efx); | |
8ceee660 BH |
762 | if (rc) |
763 | goto err; | |
764 | ||
765 | /* Sanity check MAC address */ | |
766 | if (is_valid_ether_addr(efx->mac_address)) { | |
767 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
768 | } else { | |
62776d03 BH |
769 | netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n", |
770 | efx->mac_address); | |
8ceee660 BH |
771 | if (!allow_bad_hwaddr) { |
772 | rc = -EINVAL; | |
773 | goto err; | |
774 | } | |
775 | random_ether_addr(efx->net_dev->dev_addr); | |
62776d03 BH |
776 | netif_info(efx, probe, efx->net_dev, |
777 | "using locally-generated MAC %pM\n", | |
778 | efx->net_dev->dev_addr); | |
8ceee660 BH |
779 | } |
780 | ||
781 | return 0; | |
782 | ||
783 | err: | |
784 | efx_remove_port(efx); | |
785 | return rc; | |
786 | } | |
787 | ||
788 | static int efx_init_port(struct efx_nic *efx) | |
789 | { | |
790 | int rc; | |
791 | ||
62776d03 | 792 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 793 | |
1dfc5cea BH |
794 | mutex_lock(&efx->mac_lock); |
795 | ||
177dfcd8 | 796 | rc = efx->phy_op->init(efx); |
8ceee660 | 797 | if (rc) |
1dfc5cea | 798 | goto fail1; |
8ceee660 | 799 | |
dc8cfa55 | 800 | efx->port_initialized = true; |
1dfc5cea | 801 | |
d3245b28 BH |
802 | /* Reconfigure the MAC before creating dma queues (required for |
803 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
804 | efx->mac_op->reconfigure(efx); | |
805 | ||
806 | /* Ensure the PHY advertises the correct flow control settings */ | |
807 | rc = efx->phy_op->reconfigure(efx); | |
808 | if (rc) | |
809 | goto fail2; | |
810 | ||
1dfc5cea | 811 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 812 | return 0; |
177dfcd8 | 813 | |
1dfc5cea | 814 | fail2: |
177dfcd8 | 815 | efx->phy_op->fini(efx); |
1dfc5cea BH |
816 | fail1: |
817 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 818 | return rc; |
8ceee660 BH |
819 | } |
820 | ||
8ceee660 BH |
821 | static void efx_start_port(struct efx_nic *efx) |
822 | { | |
62776d03 | 823 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
824 | BUG_ON(efx->port_enabled); |
825 | ||
826 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 827 | efx->port_enabled = true; |
8be4f3e6 BH |
828 | |
829 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
830 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 831 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
832 | efx->mac_op->reconfigure(efx); |
833 | ||
8ceee660 BH |
834 | mutex_unlock(&efx->mac_lock); |
835 | } | |
836 | ||
fdaa9aed | 837 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
838 | static void efx_stop_port(struct efx_nic *efx) |
839 | { | |
62776d03 | 840 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
841 | |
842 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 843 | efx->port_enabled = false; |
8ceee660 BH |
844 | mutex_unlock(&efx->mac_lock); |
845 | ||
846 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 847 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
848 | netif_addr_lock_bh(efx->net_dev); |
849 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
850 | } |
851 | } | |
852 | ||
853 | static void efx_fini_port(struct efx_nic *efx) | |
854 | { | |
62776d03 | 855 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
856 | |
857 | if (!efx->port_initialized) | |
858 | return; | |
859 | ||
177dfcd8 | 860 | efx->phy_op->fini(efx); |
dc8cfa55 | 861 | efx->port_initialized = false; |
8ceee660 | 862 | |
eb50c0d6 | 863 | efx->link_state.up = false; |
8ceee660 BH |
864 | efx_link_status_changed(efx); |
865 | } | |
866 | ||
867 | static void efx_remove_port(struct efx_nic *efx) | |
868 | { | |
62776d03 | 869 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 870 | |
ef2b90ee | 871 | efx->type->remove_port(efx); |
8ceee660 BH |
872 | } |
873 | ||
874 | /************************************************************************** | |
875 | * | |
876 | * NIC handling | |
877 | * | |
878 | **************************************************************************/ | |
879 | ||
880 | /* This configures the PCI device to enable I/O and DMA. */ | |
881 | static int efx_init_io(struct efx_nic *efx) | |
882 | { | |
883 | struct pci_dev *pci_dev = efx->pci_dev; | |
884 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
885 | int rc; | |
886 | ||
62776d03 | 887 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
888 | |
889 | rc = pci_enable_device(pci_dev); | |
890 | if (rc) { | |
62776d03 BH |
891 | netif_err(efx, probe, efx->net_dev, |
892 | "failed to enable PCI device\n"); | |
8ceee660 BH |
893 | goto fail1; |
894 | } | |
895 | ||
896 | pci_set_master(pci_dev); | |
897 | ||
898 | /* Set the PCI DMA mask. Try all possibilities from our | |
899 | * genuine mask down to 32 bits, because some architectures | |
900 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
901 | * masks event though they reject 46 bit masks. | |
902 | */ | |
903 | while (dma_mask > 0x7fffffffUL) { | |
904 | if (pci_dma_supported(pci_dev, dma_mask) && | |
905 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
906 | break; | |
907 | dma_mask >>= 1; | |
908 | } | |
909 | if (rc) { | |
62776d03 BH |
910 | netif_err(efx, probe, efx->net_dev, |
911 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
912 | goto fail2; |
913 | } | |
62776d03 BH |
914 | netif_dbg(efx, probe, efx->net_dev, |
915 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
916 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
917 | if (rc) { | |
918 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
919 | * fail with a mask that pci_set_dma_mask() accepted, | |
920 | * but just in case... | |
921 | */ | |
62776d03 BH |
922 | netif_err(efx, probe, efx->net_dev, |
923 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
924 | goto fail2; |
925 | } | |
926 | ||
dc803df8 BH |
927 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
928 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 929 | if (rc) { |
62776d03 BH |
930 | netif_err(efx, probe, efx->net_dev, |
931 | "request for memory BAR failed\n"); | |
8ceee660 BH |
932 | rc = -EIO; |
933 | goto fail3; | |
934 | } | |
935 | efx->membase = ioremap_nocache(efx->membase_phys, | |
936 | efx->type->mem_map_size); | |
937 | if (!efx->membase) { | |
62776d03 BH |
938 | netif_err(efx, probe, efx->net_dev, |
939 | "could not map memory BAR at %llx+%x\n", | |
940 | (unsigned long long)efx->membase_phys, | |
941 | efx->type->mem_map_size); | |
8ceee660 BH |
942 | rc = -ENOMEM; |
943 | goto fail4; | |
944 | } | |
62776d03 BH |
945 | netif_dbg(efx, probe, efx->net_dev, |
946 | "memory BAR at %llx+%x (virtual %p)\n", | |
947 | (unsigned long long)efx->membase_phys, | |
948 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
949 | |
950 | return 0; | |
951 | ||
952 | fail4: | |
dc803df8 | 953 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 954 | fail3: |
2c118e0f | 955 | efx->membase_phys = 0; |
8ceee660 BH |
956 | fail2: |
957 | pci_disable_device(efx->pci_dev); | |
958 | fail1: | |
959 | return rc; | |
960 | } | |
961 | ||
962 | static void efx_fini_io(struct efx_nic *efx) | |
963 | { | |
62776d03 | 964 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
965 | |
966 | if (efx->membase) { | |
967 | iounmap(efx->membase); | |
968 | efx->membase = NULL; | |
969 | } | |
970 | ||
971 | if (efx->membase_phys) { | |
dc803df8 | 972 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 973 | efx->membase_phys = 0; |
8ceee660 BH |
974 | } |
975 | ||
976 | pci_disable_device(efx->pci_dev); | |
977 | } | |
978 | ||
a4900ac9 BH |
979 | /* Get number of channels wanted. Each channel will have its own IRQ, |
980 | * 1 RX queue and/or 2 TX queues. */ | |
981 | static int efx_wanted_channels(void) | |
46123d04 | 982 | { |
2f8975fb | 983 | cpumask_var_t core_mask; |
46123d04 BH |
984 | int count; |
985 | int cpu; | |
986 | ||
79f55997 | 987 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 988 | printk(KERN_WARNING |
3977d033 | 989 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
990 | return 1; |
991 | } | |
992 | ||
46123d04 BH |
993 | count = 0; |
994 | for_each_online_cpu(cpu) { | |
2f8975fb | 995 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 996 | ++count; |
2f8975fb | 997 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 998 | topology_core_cpumask(cpu)); |
46123d04 BH |
999 | } |
1000 | } | |
1001 | ||
2f8975fb | 1002 | free_cpumask_var(core_mask); |
46123d04 BH |
1003 | return count; |
1004 | } | |
1005 | ||
1006 | /* Probe the number and type of interrupts we are able to obtain, and | |
1007 | * the resulting numbers of channels and RX queues. | |
1008 | */ | |
8ceee660 BH |
1009 | static void efx_probe_interrupts(struct efx_nic *efx) |
1010 | { | |
46123d04 BH |
1011 | int max_channels = |
1012 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1013 | int rc, i; |
1014 | ||
1015 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1016 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1017 | int n_channels; |
aa6ef27e | 1018 | |
a4900ac9 BH |
1019 | n_channels = efx_wanted_channels(); |
1020 | if (separate_tx_channels) | |
1021 | n_channels *= 2; | |
1022 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1023 | |
a4900ac9 | 1024 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1025 | xentries[i].entry = i; |
a4900ac9 | 1026 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1027 | if (rc > 0) { |
62776d03 BH |
1028 | netif_err(efx, drv, efx->net_dev, |
1029 | "WARNING: Insufficient MSI-X vectors" | |
1030 | " available (%d < %d).\n", rc, n_channels); | |
1031 | netif_err(efx, drv, efx->net_dev, | |
1032 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1033 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1034 | n_channels = rc; | |
8ceee660 | 1035 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1036 | n_channels); |
8ceee660 BH |
1037 | } |
1038 | ||
1039 | if (rc == 0) { | |
a4900ac9 BH |
1040 | efx->n_channels = n_channels; |
1041 | if (separate_tx_channels) { | |
1042 | efx->n_tx_channels = | |
1043 | max(efx->n_channels / 2, 1U); | |
1044 | efx->n_rx_channels = | |
1045 | max(efx->n_channels - | |
1046 | efx->n_tx_channels, 1U); | |
1047 | } else { | |
1048 | efx->n_tx_channels = efx->n_channels; | |
1049 | efx->n_rx_channels = efx->n_channels; | |
1050 | } | |
1051 | for (i = 0; i < n_channels; i++) | |
8ceee660 | 1052 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
1053 | } else { |
1054 | /* Fall back to single channel MSI */ | |
1055 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1056 | netif_err(efx, drv, efx->net_dev, |
1057 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1058 | } |
1059 | } | |
1060 | ||
1061 | /* Try single interrupt MSI */ | |
1062 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1063 | efx->n_channels = 1; |
a4900ac9 BH |
1064 | efx->n_rx_channels = 1; |
1065 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1066 | rc = pci_enable_msi(efx->pci_dev); |
1067 | if (rc == 0) { | |
1068 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 | 1069 | } else { |
62776d03 BH |
1070 | netif_err(efx, drv, efx->net_dev, |
1071 | "could not enable MSI\n"); | |
8ceee660 BH |
1072 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1073 | } | |
1074 | } | |
1075 | ||
1076 | /* Assume legacy interrupts */ | |
1077 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1078 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1079 | efx->n_rx_channels = 1; |
1080 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1081 | efx->legacy_irq = efx->pci_dev->irq; |
1082 | } | |
1083 | } | |
1084 | ||
1085 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1086 | { | |
1087 | struct efx_channel *channel; | |
1088 | ||
1089 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1090 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1091 | channel->irq = 0; |
1092 | pci_disable_msi(efx->pci_dev); | |
1093 | pci_disable_msix(efx->pci_dev); | |
1094 | ||
1095 | /* Remove legacy interrupt */ | |
1096 | efx->legacy_irq = 0; | |
1097 | } | |
1098 | ||
8831da7b | 1099 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1100 | { |
a4900ac9 | 1101 | struct efx_channel *channel; |
8ceee660 BH |
1102 | struct efx_tx_queue *tx_queue; |
1103 | struct efx_rx_queue *rx_queue; | |
a4900ac9 BH |
1104 | unsigned tx_channel_offset = |
1105 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
8ceee660 | 1106 | |
a4900ac9 BH |
1107 | efx_for_each_channel(channel, efx) { |
1108 | if (channel->channel - tx_channel_offset < efx->n_tx_channels) { | |
1109 | channel->tx_queue = &efx->tx_queue[ | |
1110 | (channel->channel - tx_channel_offset) * | |
1111 | EFX_TXQ_TYPES]; | |
1112 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1113 | tx_queue->channel = channel; | |
1114 | } | |
60ac1065 | 1115 | } |
8ceee660 | 1116 | |
a4900ac9 | 1117 | efx_for_each_rx_queue(rx_queue, efx) |
8831da7b | 1118 | rx_queue->channel = &efx->channel[rx_queue->queue]; |
8ceee660 BH |
1119 | } |
1120 | ||
1121 | static int efx_probe_nic(struct efx_nic *efx) | |
1122 | { | |
1123 | int rc; | |
1124 | ||
62776d03 | 1125 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1126 | |
1127 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1128 | rc = efx->type->probe(efx); |
8ceee660 BH |
1129 | if (rc) |
1130 | return rc; | |
1131 | ||
a4900ac9 | 1132 | /* Determine the number of channels and queues by trying to hook |
8ceee660 BH |
1133 | * in MSI-X interrupts. */ |
1134 | efx_probe_interrupts(efx); | |
1135 | ||
8831da7b | 1136 | efx_set_channels(efx); |
a4900ac9 | 1137 | efx->net_dev->real_num_tx_queues = efx->n_tx_channels; |
8ceee660 BH |
1138 | |
1139 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1140 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1141 | |
1142 | return 0; | |
1143 | } | |
1144 | ||
1145 | static void efx_remove_nic(struct efx_nic *efx) | |
1146 | { | |
62776d03 | 1147 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1148 | |
1149 | efx_remove_interrupts(efx); | |
ef2b90ee | 1150 | efx->type->remove(efx); |
8ceee660 BH |
1151 | } |
1152 | ||
1153 | /************************************************************************** | |
1154 | * | |
1155 | * NIC startup/shutdown | |
1156 | * | |
1157 | *************************************************************************/ | |
1158 | ||
1159 | static int efx_probe_all(struct efx_nic *efx) | |
1160 | { | |
1161 | struct efx_channel *channel; | |
1162 | int rc; | |
1163 | ||
1164 | /* Create NIC */ | |
1165 | rc = efx_probe_nic(efx); | |
1166 | if (rc) { | |
62776d03 | 1167 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1168 | goto fail1; |
1169 | } | |
1170 | ||
1171 | /* Create port */ | |
1172 | rc = efx_probe_port(efx); | |
1173 | if (rc) { | |
62776d03 | 1174 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1175 | goto fail2; |
1176 | } | |
1177 | ||
1178 | /* Create channels */ | |
1179 | efx_for_each_channel(channel, efx) { | |
1180 | rc = efx_probe_channel(channel); | |
1181 | if (rc) { | |
62776d03 BH |
1182 | netif_err(efx, probe, efx->net_dev, |
1183 | "failed to create channel %d\n", | |
1184 | channel->channel); | |
8ceee660 BH |
1185 | goto fail3; |
1186 | } | |
1187 | } | |
56536e9c | 1188 | efx_set_channel_names(efx); |
8ceee660 BH |
1189 | |
1190 | return 0; | |
1191 | ||
1192 | fail3: | |
1193 | efx_for_each_channel(channel, efx) | |
1194 | efx_remove_channel(channel); | |
1195 | efx_remove_port(efx); | |
1196 | fail2: | |
1197 | efx_remove_nic(efx); | |
1198 | fail1: | |
1199 | return rc; | |
1200 | } | |
1201 | ||
1202 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1203 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1204 | * and ensures that the port is scheduled to be reconfigured. | |
1205 | * This function is safe to call multiple times when the NIC is in any | |
1206 | * state. */ | |
1207 | static void efx_start_all(struct efx_nic *efx) | |
1208 | { | |
1209 | struct efx_channel *channel; | |
1210 | ||
1211 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1212 | ||
1213 | /* Check that it is appropriate to restart the interface. All | |
1214 | * of these flags are safe to read under just the rtnl lock */ | |
1215 | if (efx->port_enabled) | |
1216 | return; | |
1217 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1218 | return; | |
55668611 | 1219 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1220 | return; |
1221 | ||
1222 | /* Mark the port as enabled so port reconfigurations can start, then | |
1223 | * restart the transmit interface early so the watchdog timer stops */ | |
1224 | efx_start_port(efx); | |
8ceee660 | 1225 | |
a4900ac9 BH |
1226 | efx_for_each_channel(channel, efx) { |
1227 | if (efx_dev_registered(efx)) | |
1228 | efx_wake_queue(channel); | |
8ceee660 | 1229 | efx_start_channel(channel); |
a4900ac9 | 1230 | } |
8ceee660 | 1231 | |
152b6a62 | 1232 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1233 | |
8880f4ec BH |
1234 | /* Switch to event based MCDI completions after enabling interrupts. |
1235 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1236 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1237 | * reset_pending [modified from an atomic context], we instead guarantee | |
1238 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1239 | efx_mcdi_mode_event(efx); | |
1240 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1241 | efx_mcdi_mode_poll(efx); | |
1242 | ||
78c1f0a0 SH |
1243 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1244 | * event driven), we have to poll the PHY because after an event queue | |
1245 | * flush, we could have a missed a link state change */ | |
1246 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1247 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1248 | efx_monitor_interval); | |
78c1f0a0 SH |
1249 | } else { |
1250 | mutex_lock(&efx->mac_lock); | |
1251 | if (efx->phy_op->poll(efx)) | |
1252 | efx_link_status_changed(efx); | |
1253 | mutex_unlock(&efx->mac_lock); | |
1254 | } | |
55edc6e6 | 1255 | |
ef2b90ee | 1256 | efx->type->start_stats(efx); |
8ceee660 BH |
1257 | } |
1258 | ||
1259 | /* Flush all delayed work. Should only be called when no more delayed work | |
1260 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1261 | * since we're holding the rtnl_lock at this point. */ | |
1262 | static void efx_flush_all(struct efx_nic *efx) | |
1263 | { | |
8ceee660 BH |
1264 | /* Make sure the hardware monitor is stopped */ |
1265 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1266 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1267 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1268 | } |
1269 | ||
1270 | /* Quiesce hardware and software without bringing the link down. | |
1271 | * Safe to call multiple times, when the nic and interface is in any | |
1272 | * state. The caller is guaranteed to subsequently be in a position | |
1273 | * to modify any hardware and software state they see fit without | |
1274 | * taking locks. */ | |
1275 | static void efx_stop_all(struct efx_nic *efx) | |
1276 | { | |
1277 | struct efx_channel *channel; | |
1278 | ||
1279 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1280 | ||
1281 | /* port_enabled can be read safely under the rtnl lock */ | |
1282 | if (!efx->port_enabled) | |
1283 | return; | |
1284 | ||
ef2b90ee | 1285 | efx->type->stop_stats(efx); |
55edc6e6 | 1286 | |
8880f4ec BH |
1287 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1288 | efx_mcdi_mode_poll(efx); | |
1289 | ||
8ceee660 | 1290 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1291 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
1292 | if (efx->legacy_irq) |
1293 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1294 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1295 | if (channel->irq) |
1296 | synchronize_irq(channel->irq); | |
b3475645 | 1297 | } |
8ceee660 BH |
1298 | |
1299 | /* Stop all NAPI processing and synchronous rx refills */ | |
1300 | efx_for_each_channel(channel, efx) | |
1301 | efx_stop_channel(channel); | |
1302 | ||
1303 | /* Stop all asynchronous port reconfigurations. Since all | |
1304 | * event processing has already been stopped, there is no | |
1305 | * window to loose phy events */ | |
1306 | efx_stop_port(efx); | |
1307 | ||
fdaa9aed | 1308 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1309 | efx_flush_all(efx); |
1310 | ||
8ceee660 BH |
1311 | /* Stop the kernel transmit interface late, so the watchdog |
1312 | * timer isn't ticking over the flush */ | |
55668611 | 1313 | if (efx_dev_registered(efx)) { |
a4900ac9 BH |
1314 | struct efx_channel *channel; |
1315 | efx_for_each_channel(channel, efx) | |
1316 | efx_stop_queue(channel); | |
8ceee660 BH |
1317 | netif_tx_lock_bh(efx->net_dev); |
1318 | netif_tx_unlock_bh(efx->net_dev); | |
1319 | } | |
1320 | } | |
1321 | ||
1322 | static void efx_remove_all(struct efx_nic *efx) | |
1323 | { | |
1324 | struct efx_channel *channel; | |
1325 | ||
1326 | efx_for_each_channel(channel, efx) | |
1327 | efx_remove_channel(channel); | |
1328 | efx_remove_port(efx); | |
1329 | efx_remove_nic(efx); | |
1330 | } | |
1331 | ||
8ceee660 BH |
1332 | /************************************************************************** |
1333 | * | |
1334 | * Interrupt moderation | |
1335 | * | |
1336 | **************************************************************************/ | |
1337 | ||
0d86ebd8 BH |
1338 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1339 | { | |
1340 | if (usecs <= 0) | |
1341 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1342 | if (usecs < resolution) | |
1343 | return 1; /* never round down to 0 */ | |
1344 | return usecs / resolution; | |
1345 | } | |
1346 | ||
8ceee660 | 1347 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1348 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1349 | bool rx_adaptive) | |
8ceee660 BH |
1350 | { |
1351 | struct efx_tx_queue *tx_queue; | |
1352 | struct efx_rx_queue *rx_queue; | |
152b6a62 BH |
1353 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1354 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1355 | |
1356 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1357 | ||
1358 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1359 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1360 | |
6fb70fd1 | 1361 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1362 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1363 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1364 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1365 | } |
1366 | ||
1367 | /************************************************************************** | |
1368 | * | |
1369 | * Hardware monitor | |
1370 | * | |
1371 | **************************************************************************/ | |
1372 | ||
1373 | /* Run periodically off the general workqueue. Serialised against | |
1374 | * efx_reconfigure_port via the mac_lock */ | |
1375 | static void efx_monitor(struct work_struct *data) | |
1376 | { | |
1377 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1378 | monitor_work.work); | |
8ceee660 | 1379 | |
62776d03 BH |
1380 | netif_vdbg(efx, timer, efx->net_dev, |
1381 | "hardware monitor executing on CPU %d\n", | |
1382 | raw_smp_processor_id()); | |
ef2b90ee | 1383 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1384 | |
8ceee660 BH |
1385 | /* If the mac_lock is already held then it is likely a port |
1386 | * reconfiguration is already in place, which will likely do | |
1387 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1388 | if (!mutex_trylock(&efx->mac_lock)) |
1389 | goto out_requeue; | |
1390 | if (!efx->port_enabled) | |
1391 | goto out_unlock; | |
ef2b90ee | 1392 | efx->type->monitor(efx); |
8ceee660 | 1393 | |
766ca0fa | 1394 | out_unlock: |
8ceee660 | 1395 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1396 | out_requeue: |
8ceee660 BH |
1397 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1398 | efx_monitor_interval); | |
1399 | } | |
1400 | ||
1401 | /************************************************************************** | |
1402 | * | |
1403 | * ioctls | |
1404 | * | |
1405 | *************************************************************************/ | |
1406 | ||
1407 | /* Net device ioctl | |
1408 | * Context: process, rtnl_lock() held. | |
1409 | */ | |
1410 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1411 | { | |
767e468c | 1412 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1413 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1414 | |
1415 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1416 | ||
68e7f45e BH |
1417 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1418 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1419 | (data->phy_id & 0xfc00) == 0x0400) | |
1420 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1421 | ||
1422 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1423 | } |
1424 | ||
1425 | /************************************************************************** | |
1426 | * | |
1427 | * NAPI interface | |
1428 | * | |
1429 | **************************************************************************/ | |
1430 | ||
1431 | static int efx_init_napi(struct efx_nic *efx) | |
1432 | { | |
1433 | struct efx_channel *channel; | |
8ceee660 BH |
1434 | |
1435 | efx_for_each_channel(channel, efx) { | |
1436 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1437 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1438 | efx_poll, napi_weight); | |
8ceee660 BH |
1439 | } |
1440 | return 0; | |
8ceee660 BH |
1441 | } |
1442 | ||
1443 | static void efx_fini_napi(struct efx_nic *efx) | |
1444 | { | |
1445 | struct efx_channel *channel; | |
1446 | ||
1447 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1448 | if (channel->napi_dev) |
1449 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1450 | channel->napi_dev = NULL; |
1451 | } | |
1452 | } | |
1453 | ||
1454 | /************************************************************************** | |
1455 | * | |
1456 | * Kernel netpoll interface | |
1457 | * | |
1458 | *************************************************************************/ | |
1459 | ||
1460 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1461 | ||
1462 | /* Although in the common case interrupts will be disabled, this is not | |
1463 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1464 | * so no locking is required. | |
1465 | */ | |
1466 | static void efx_netpoll(struct net_device *net_dev) | |
1467 | { | |
767e468c | 1468 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1469 | struct efx_channel *channel; |
1470 | ||
64ee3120 | 1471 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1472 | efx_schedule_channel(channel); |
1473 | } | |
1474 | ||
1475 | #endif | |
1476 | ||
1477 | /************************************************************************** | |
1478 | * | |
1479 | * Kernel net device interface | |
1480 | * | |
1481 | *************************************************************************/ | |
1482 | ||
1483 | /* Context: process, rtnl_lock() held. */ | |
1484 | static int efx_net_open(struct net_device *net_dev) | |
1485 | { | |
767e468c | 1486 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1487 | EFX_ASSERT_RESET_SERIALISED(efx); |
1488 | ||
62776d03 BH |
1489 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1490 | raw_smp_processor_id()); | |
8ceee660 | 1491 | |
f4bd954e BH |
1492 | if (efx->state == STATE_DISABLED) |
1493 | return -EIO; | |
f8b87c17 BH |
1494 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1495 | return -EBUSY; | |
8880f4ec BH |
1496 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1497 | return -EIO; | |
f8b87c17 | 1498 | |
78c1f0a0 SH |
1499 | /* Notify the kernel of the link state polled during driver load, |
1500 | * before the monitor starts running */ | |
1501 | efx_link_status_changed(efx); | |
1502 | ||
8ceee660 BH |
1503 | efx_start_all(efx); |
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | /* Context: process, rtnl_lock() held. | |
1508 | * Note that the kernel will ignore our return code; this method | |
1509 | * should really be a void. | |
1510 | */ | |
1511 | static int efx_net_stop(struct net_device *net_dev) | |
1512 | { | |
767e468c | 1513 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1514 | |
62776d03 BH |
1515 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1516 | raw_smp_processor_id()); | |
8ceee660 | 1517 | |
f4bd954e BH |
1518 | if (efx->state != STATE_DISABLED) { |
1519 | /* Stop the device and flush all the channels */ | |
1520 | efx_stop_all(efx); | |
1521 | efx_fini_channels(efx); | |
1522 | efx_init_channels(efx); | |
1523 | } | |
8ceee660 BH |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
5b9e207c | 1528 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
4472702e | 1529 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev) |
8ceee660 | 1530 | { |
767e468c | 1531 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1532 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
4472702e | 1533 | struct rtnl_link_stats64 *stats = &net_dev->stats64; |
8ceee660 | 1534 | |
55edc6e6 | 1535 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1536 | efx->type->update_stats(efx); |
55edc6e6 | 1537 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1538 | |
1539 | stats->rx_packets = mac_stats->rx_packets; | |
1540 | stats->tx_packets = mac_stats->tx_packets; | |
1541 | stats->rx_bytes = mac_stats->rx_bytes; | |
1542 | stats->tx_bytes = mac_stats->tx_bytes; | |
1543 | stats->multicast = mac_stats->rx_multicast; | |
1544 | stats->collisions = mac_stats->tx_collision; | |
1545 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1546 | mac_stats->rx_length_error); | |
1547 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1548 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1549 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1550 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1551 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1552 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1553 | ||
1554 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1555 | stats->rx_crc_errors + |
1556 | stats->rx_frame_errors + | |
8ceee660 BH |
1557 | mac_stats->rx_symbol_error); |
1558 | stats->tx_errors = (stats->tx_window_errors + | |
1559 | mac_stats->tx_bad); | |
1560 | ||
1561 | return stats; | |
1562 | } | |
1563 | ||
1564 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1565 | static void efx_watchdog(struct net_device *net_dev) | |
1566 | { | |
767e468c | 1567 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1568 | |
62776d03 BH |
1569 | netif_err(efx, tx_err, efx->net_dev, |
1570 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1571 | efx->port_enabled); | |
8ceee660 | 1572 | |
739bb23d | 1573 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1574 | } |
1575 | ||
1576 | ||
1577 | /* Context: process, rtnl_lock() held. */ | |
1578 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1579 | { | |
767e468c | 1580 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1581 | int rc = 0; |
1582 | ||
1583 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1584 | ||
1585 | if (new_mtu > EFX_MAX_MTU) | |
1586 | return -EINVAL; | |
1587 | ||
1588 | efx_stop_all(efx); | |
1589 | ||
62776d03 | 1590 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 BH |
1591 | |
1592 | efx_fini_channels(efx); | |
d3245b28 BH |
1593 | |
1594 | mutex_lock(&efx->mac_lock); | |
1595 | /* Reconfigure the MAC before enabling the dma queues so that | |
1596 | * the RX buffers don't overflow */ | |
8ceee660 | 1597 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1598 | efx->mac_op->reconfigure(efx); |
1599 | mutex_unlock(&efx->mac_lock); | |
1600 | ||
bc3c90a2 | 1601 | efx_init_channels(efx); |
8ceee660 BH |
1602 | |
1603 | efx_start_all(efx); | |
1604 | return rc; | |
8ceee660 BH |
1605 | } |
1606 | ||
1607 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1608 | { | |
767e468c | 1609 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1610 | struct sockaddr *addr = data; |
1611 | char *new_addr = addr->sa_data; | |
1612 | ||
1613 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1614 | ||
1615 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1616 | netif_err(efx, drv, efx->net_dev, |
1617 | "invalid ethernet MAC address requested: %pM\n", | |
1618 | new_addr); | |
8ceee660 BH |
1619 | return -EINVAL; |
1620 | } | |
1621 | ||
1622 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1623 | ||
1624 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1625 | mutex_lock(&efx->mac_lock); |
1626 | efx->mac_op->reconfigure(efx); | |
1627 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1628 | |
1629 | return 0; | |
1630 | } | |
1631 | ||
a816f75a | 1632 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1633 | static void efx_set_multicast_list(struct net_device *net_dev) |
1634 | { | |
767e468c | 1635 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1636 | struct netdev_hw_addr *ha; |
8ceee660 | 1637 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1638 | u32 crc; |
1639 | int bit; | |
8ceee660 | 1640 | |
8be4f3e6 | 1641 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1642 | |
1643 | /* Build multicast hash table */ | |
8be4f3e6 | 1644 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1645 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1646 | } else { | |
1647 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1648 | netdev_for_each_mc_addr(ha, net_dev) { |
1649 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1650 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1651 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1652 | } |
8ceee660 | 1653 | |
8be4f3e6 BH |
1654 | /* Broadcast packets go through the multicast hash filter. |
1655 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1656 | * so we always add bit 0xff to the mask. | |
1657 | */ | |
1658 | set_bit_le(0xff, mc_hash->byte); | |
1659 | } | |
a816f75a | 1660 | |
8be4f3e6 BH |
1661 | if (efx->port_enabled) |
1662 | queue_work(efx->workqueue, &efx->mac_work); | |
1663 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1664 | } |
1665 | ||
c3ecb9f3 SH |
1666 | static const struct net_device_ops efx_netdev_ops = { |
1667 | .ndo_open = efx_net_open, | |
1668 | .ndo_stop = efx_net_stop, | |
4472702e | 1669 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1670 | .ndo_tx_timeout = efx_watchdog, |
1671 | .ndo_start_xmit = efx_hard_start_xmit, | |
1672 | .ndo_validate_addr = eth_validate_addr, | |
1673 | .ndo_do_ioctl = efx_ioctl, | |
1674 | .ndo_change_mtu = efx_change_mtu, | |
1675 | .ndo_set_mac_address = efx_set_mac_address, | |
1676 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1677 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1678 | .ndo_poll_controller = efx_netpoll, | |
1679 | #endif | |
1680 | }; | |
1681 | ||
7dde596e BH |
1682 | static void efx_update_name(struct efx_nic *efx) |
1683 | { | |
1684 | strcpy(efx->name, efx->net_dev->name); | |
1685 | efx_mtd_rename(efx); | |
1686 | efx_set_channel_names(efx); | |
1687 | } | |
1688 | ||
8ceee660 BH |
1689 | static int efx_netdev_event(struct notifier_block *this, |
1690 | unsigned long event, void *ptr) | |
1691 | { | |
d3208b5e | 1692 | struct net_device *net_dev = ptr; |
8ceee660 | 1693 | |
7dde596e BH |
1694 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1695 | event == NETDEV_CHANGENAME) | |
1696 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1697 | |
1698 | return NOTIFY_DONE; | |
1699 | } | |
1700 | ||
1701 | static struct notifier_block efx_netdev_notifier = { | |
1702 | .notifier_call = efx_netdev_event, | |
1703 | }; | |
1704 | ||
06d5e193 BH |
1705 | static ssize_t |
1706 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1707 | { | |
1708 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1709 | return sprintf(buf, "%d\n", efx->phy_type); | |
1710 | } | |
1711 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1712 | ||
8ceee660 BH |
1713 | static int efx_register_netdev(struct efx_nic *efx) |
1714 | { | |
1715 | struct net_device *net_dev = efx->net_dev; | |
1716 | int rc; | |
1717 | ||
1718 | net_dev->watchdog_timeo = 5 * HZ; | |
1719 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1720 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1721 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1722 | ||
8ceee660 | 1723 | /* Clear MAC statistics */ |
177dfcd8 | 1724 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1725 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1726 | ||
7dde596e | 1727 | rtnl_lock(); |
aed0628d BH |
1728 | |
1729 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1730 | if (rc < 0) | |
1731 | goto fail_locked; | |
7dde596e | 1732 | efx_update_name(efx); |
aed0628d BH |
1733 | |
1734 | rc = register_netdevice(net_dev); | |
1735 | if (rc) | |
1736 | goto fail_locked; | |
1737 | ||
1738 | /* Always start with carrier off; PHY events will detect the link */ | |
1739 | netif_carrier_off(efx->net_dev); | |
1740 | ||
7dde596e | 1741 | rtnl_unlock(); |
8ceee660 | 1742 | |
06d5e193 BH |
1743 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1744 | if (rc) { | |
62776d03 BH |
1745 | netif_err(efx, drv, efx->net_dev, |
1746 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1747 | goto fail_registered; |
1748 | } | |
1749 | ||
8ceee660 | 1750 | return 0; |
06d5e193 | 1751 | |
aed0628d BH |
1752 | fail_locked: |
1753 | rtnl_unlock(); | |
62776d03 | 1754 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1755 | return rc; |
1756 | ||
06d5e193 BH |
1757 | fail_registered: |
1758 | unregister_netdev(net_dev); | |
1759 | return rc; | |
8ceee660 BH |
1760 | } |
1761 | ||
1762 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1763 | { | |
1764 | struct efx_tx_queue *tx_queue; | |
1765 | ||
1766 | if (!efx->net_dev) | |
1767 | return; | |
1768 | ||
767e468c | 1769 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1770 | |
1771 | /* Free up any skbs still remaining. This has to happen before | |
1772 | * we try to unregister the netdev as running their destructors | |
1773 | * may be needed to get the device ref. count to 0. */ | |
1774 | efx_for_each_tx_queue(tx_queue, efx) | |
1775 | efx_release_tx_buffers(tx_queue); | |
1776 | ||
55668611 | 1777 | if (efx_dev_registered(efx)) { |
8ceee660 | 1778 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1779 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1780 | unregister_netdev(efx->net_dev); |
1781 | } | |
1782 | } | |
1783 | ||
1784 | /************************************************************************** | |
1785 | * | |
1786 | * Device reset and suspend | |
1787 | * | |
1788 | **************************************************************************/ | |
1789 | ||
2467ca46 BH |
1790 | /* Tears down the entire software state and most of the hardware state |
1791 | * before reset. */ | |
d3245b28 | 1792 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1793 | { |
8ceee660 BH |
1794 | EFX_ASSERT_RESET_SERIALISED(efx); |
1795 | ||
2467ca46 BH |
1796 | efx_stop_all(efx); |
1797 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1798 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1799 | |
8ceee660 | 1800 | efx_fini_channels(efx); |
4b988280 SH |
1801 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1802 | efx->phy_op->fini(efx); | |
ef2b90ee | 1803 | efx->type->fini(efx); |
8ceee660 BH |
1804 | } |
1805 | ||
2467ca46 BH |
1806 | /* This function will always ensure that the locks acquired in |
1807 | * efx_reset_down() are released. A failure return code indicates | |
1808 | * that we were unable to reinitialise the hardware, and the | |
1809 | * driver should be disabled. If ok is false, then the rx and tx | |
1810 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 1811 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
1812 | { |
1813 | int rc; | |
1814 | ||
2467ca46 | 1815 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1816 | |
ef2b90ee | 1817 | rc = efx->type->init(efx); |
8ceee660 | 1818 | if (rc) { |
62776d03 | 1819 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 1820 | goto fail; |
8ceee660 BH |
1821 | } |
1822 | ||
eb9f6744 BH |
1823 | if (!ok) |
1824 | goto fail; | |
1825 | ||
4b988280 | 1826 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
1827 | rc = efx->phy_op->init(efx); |
1828 | if (rc) | |
1829 | goto fail; | |
1830 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
1831 | netif_err(efx, drv, efx->net_dev, |
1832 | "could not restore PHY settings\n"); | |
4b988280 SH |
1833 | } |
1834 | ||
eb9f6744 | 1835 | efx->mac_op->reconfigure(efx); |
8ceee660 | 1836 | |
eb9f6744 BH |
1837 | efx_init_channels(efx); |
1838 | ||
1839 | mutex_unlock(&efx->spi_lock); | |
1840 | mutex_unlock(&efx->mac_lock); | |
1841 | ||
1842 | efx_start_all(efx); | |
1843 | ||
1844 | return 0; | |
1845 | ||
1846 | fail: | |
1847 | efx->port_initialized = false; | |
2467ca46 | 1848 | |
f4150724 | 1849 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1850 | mutex_unlock(&efx->mac_lock); |
1851 | ||
8ceee660 BH |
1852 | return rc; |
1853 | } | |
1854 | ||
eb9f6744 BH |
1855 | /* Reset the NIC using the specified method. Note that the reset may |
1856 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 1857 | * |
eb9f6744 | 1858 | * Caller must hold the rtnl_lock. |
8ceee660 | 1859 | */ |
eb9f6744 | 1860 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1861 | { |
eb9f6744 BH |
1862 | int rc, rc2; |
1863 | bool disabled; | |
8ceee660 | 1864 | |
62776d03 BH |
1865 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
1866 | RESET_TYPE(method)); | |
8ceee660 | 1867 | |
d3245b28 | 1868 | efx_reset_down(efx, method); |
8ceee660 | 1869 | |
ef2b90ee | 1870 | rc = efx->type->reset(efx, method); |
8ceee660 | 1871 | if (rc) { |
62776d03 | 1872 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 1873 | goto out; |
8ceee660 BH |
1874 | } |
1875 | ||
1876 | /* Allow resets to be rescheduled. */ | |
1877 | efx->reset_pending = RESET_TYPE_NONE; | |
1878 | ||
1879 | /* Reinitialise bus-mastering, which may have been turned off before | |
1880 | * the reset was scheduled. This is still appropriate, even in the | |
1881 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1882 | * can respond to requests. */ | |
1883 | pci_set_master(efx->pci_dev); | |
1884 | ||
eb9f6744 | 1885 | out: |
8ceee660 | 1886 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
1887 | disabled = rc || method == RESET_TYPE_DISABLE; |
1888 | rc2 = efx_reset_up(efx, method, !disabled); | |
1889 | if (rc2) { | |
1890 | disabled = true; | |
1891 | if (!rc) | |
1892 | rc = rc2; | |
8ceee660 BH |
1893 | } |
1894 | ||
eb9f6744 | 1895 | if (disabled) { |
f49a4589 | 1896 | dev_close(efx->net_dev); |
62776d03 | 1897 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 1898 | efx->state = STATE_DISABLED; |
f4bd954e | 1899 | } else { |
62776d03 | 1900 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
f4bd954e | 1901 | } |
8ceee660 BH |
1902 | return rc; |
1903 | } | |
1904 | ||
1905 | /* The worker thread exists so that code that cannot sleep can | |
1906 | * schedule a reset for later. | |
1907 | */ | |
1908 | static void efx_reset_work(struct work_struct *data) | |
1909 | { | |
eb9f6744 | 1910 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 1911 | |
319ba649 SH |
1912 | if (efx->reset_pending == RESET_TYPE_NONE) |
1913 | return; | |
1914 | ||
eb9f6744 BH |
1915 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
1916 | * flag set so that efx_pci_probe_main will be retried */ | |
1917 | if (efx->state != STATE_RUNNING) { | |
62776d03 BH |
1918 | netif_info(efx, drv, efx->net_dev, |
1919 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
1920 | return; |
1921 | } | |
1922 | ||
1923 | rtnl_lock(); | |
f49a4589 | 1924 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 1925 | rtnl_unlock(); |
8ceee660 BH |
1926 | } |
1927 | ||
1928 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1929 | { | |
1930 | enum reset_type method; | |
1931 | ||
1932 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
62776d03 BH |
1933 | netif_info(efx, drv, efx->net_dev, |
1934 | "quenching already scheduled reset\n"); | |
8ceee660 BH |
1935 | return; |
1936 | } | |
1937 | ||
1938 | switch (type) { | |
1939 | case RESET_TYPE_INVISIBLE: | |
1940 | case RESET_TYPE_ALL: | |
1941 | case RESET_TYPE_WORLD: | |
1942 | case RESET_TYPE_DISABLE: | |
1943 | method = type; | |
1944 | break; | |
1945 | case RESET_TYPE_RX_RECOVERY: | |
1946 | case RESET_TYPE_RX_DESC_FETCH: | |
1947 | case RESET_TYPE_TX_DESC_FETCH: | |
1948 | case RESET_TYPE_TX_SKIP: | |
1949 | method = RESET_TYPE_INVISIBLE; | |
1950 | break; | |
8880f4ec | 1951 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
1952 | default: |
1953 | method = RESET_TYPE_ALL; | |
1954 | break; | |
1955 | } | |
1956 | ||
1957 | if (method != type) | |
62776d03 BH |
1958 | netif_dbg(efx, drv, efx->net_dev, |
1959 | "scheduling %s reset for %s\n", | |
1960 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 1961 | else |
62776d03 BH |
1962 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
1963 | RESET_TYPE(method)); | |
8ceee660 BH |
1964 | |
1965 | efx->reset_pending = method; | |
1966 | ||
8880f4ec BH |
1967 | /* efx_process_channel() will no longer read events once a |
1968 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
1969 | efx_mcdi_mode_poll(efx); | |
1970 | ||
1ab00629 | 1971 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1972 | } |
1973 | ||
1974 | /************************************************************************** | |
1975 | * | |
1976 | * List of NICs we support | |
1977 | * | |
1978 | **************************************************************************/ | |
1979 | ||
1980 | /* PCI device ID table */ | |
a3aa1884 | 1981 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 1982 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 1983 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 1984 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 1985 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
1986 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
1987 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
1988 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
1989 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
1990 | {0} /* end of list */ |
1991 | }; | |
1992 | ||
1993 | /************************************************************************** | |
1994 | * | |
3759433d | 1995 | * Dummy PHY/MAC operations |
8ceee660 | 1996 | * |
01aad7b6 | 1997 | * Can be used for some unimplemented operations |
8ceee660 BH |
1998 | * Needed so all function pointers are valid and do not have to be tested |
1999 | * before use | |
2000 | * | |
2001 | **************************************************************************/ | |
2002 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2003 | { | |
2004 | return 0; | |
2005 | } | |
2006 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
2007 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
2008 | { | |
2009 | } | |
fdaa9aed SH |
2010 | bool efx_port_dummy_op_poll(struct efx_nic *efx) |
2011 | { | |
2012 | return false; | |
2013 | } | |
8ceee660 BH |
2014 | |
2015 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
2016 | .init = efx_port_dummy_op_int, | |
d3245b28 | 2017 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2018 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2019 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2020 | }; |
2021 | ||
8ceee660 BH |
2022 | /************************************************************************** |
2023 | * | |
2024 | * Data housekeeping | |
2025 | * | |
2026 | **************************************************************************/ | |
2027 | ||
2028 | /* This zeroes out and then fills in the invariants in a struct | |
2029 | * efx_nic (including all sub-structures). | |
2030 | */ | |
2031 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
2032 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
2033 | { | |
2034 | struct efx_channel *channel; | |
2035 | struct efx_tx_queue *tx_queue; | |
2036 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 2037 | int i; |
8ceee660 BH |
2038 | |
2039 | /* Initialise common structures */ | |
2040 | memset(efx, 0, sizeof(*efx)); | |
2041 | spin_lock_init(&efx->biu_lock); | |
ab867461 | 2042 | mutex_init(&efx->mdio_lock); |
f4150724 | 2043 | mutex_init(&efx->spi_lock); |
76884835 BH |
2044 | #ifdef CONFIG_SFC_MTD |
2045 | INIT_LIST_HEAD(&efx->mtd_list); | |
2046 | #endif | |
8ceee660 BH |
2047 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2048 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2049 | efx->pci_dev = pci_dev; | |
62776d03 | 2050 | efx->msg_enable = debug; |
8ceee660 BH |
2051 | efx->state = STATE_INIT; |
2052 | efx->reset_pending = RESET_TYPE_NONE; | |
2053 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2054 | |
2055 | efx->net_dev = net_dev; | |
dc8cfa55 | 2056 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2057 | spin_lock_init(&efx->stats_lock); |
2058 | mutex_init(&efx->mac_lock); | |
b895d73e | 2059 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2060 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2061 | efx->mdio.dev = net_dev; |
766ca0fa | 2062 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2063 | |
2064 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
2065 | channel = &efx->channel[i]; | |
2066 | channel->efx = efx; | |
2067 | channel->channel = i; | |
dc8cfa55 | 2068 | channel->work_pending = false; |
a4900ac9 BH |
2069 | spin_lock_init(&channel->tx_stop_lock); |
2070 | atomic_set(&channel->tx_stop_count, 1); | |
8ceee660 | 2071 | } |
a4900ac9 | 2072 | for (i = 0; i < EFX_MAX_TX_QUEUES; i++) { |
8ceee660 BH |
2073 | tx_queue = &efx->tx_queue[i]; |
2074 | tx_queue->efx = efx; | |
2075 | tx_queue->queue = i; | |
2076 | tx_queue->buffer = NULL; | |
2077 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 2078 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
2079 | } |
2080 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
2081 | rx_queue = &efx->rx_queue[i]; | |
2082 | rx_queue->efx = efx; | |
2083 | rx_queue->queue = i; | |
2084 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
2085 | rx_queue->buffer = NULL; | |
90d683af SH |
2086 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
2087 | (unsigned long)rx_queue); | |
8ceee660 BH |
2088 | } |
2089 | ||
2090 | efx->type = type; | |
2091 | ||
8ceee660 | 2092 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
2093 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
2094 | ||
8ceee660 BH |
2095 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2096 | ||
2097 | /* Higher numbered interrupt modes are less capable! */ | |
2098 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2099 | interrupt_mode); | |
2100 | ||
6977dc63 BH |
2101 | /* Would be good to use the net_dev name, but we're too early */ |
2102 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2103 | pci_name(pci_dev)); | |
2104 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2105 | if (!efx->workqueue) |
2106 | return -ENOMEM; | |
8d9853d9 | 2107 | |
8ceee660 | 2108 | return 0; |
8ceee660 BH |
2109 | } |
2110 | ||
2111 | static void efx_fini_struct(struct efx_nic *efx) | |
2112 | { | |
2113 | if (efx->workqueue) { | |
2114 | destroy_workqueue(efx->workqueue); | |
2115 | efx->workqueue = NULL; | |
2116 | } | |
2117 | } | |
2118 | ||
2119 | /************************************************************************** | |
2120 | * | |
2121 | * PCI interface | |
2122 | * | |
2123 | **************************************************************************/ | |
2124 | ||
2125 | /* Main body of final NIC shutdown code | |
2126 | * This is called only at module unload (or hotplug removal). | |
2127 | */ | |
2128 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2129 | { | |
152b6a62 | 2130 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2131 | efx_fini_channels(efx); |
2132 | efx_fini_port(efx); | |
ef2b90ee | 2133 | efx->type->fini(efx); |
8ceee660 BH |
2134 | efx_fini_napi(efx); |
2135 | efx_remove_all(efx); | |
2136 | } | |
2137 | ||
2138 | /* Final NIC shutdown | |
2139 | * This is called only at module unload (or hotplug removal). | |
2140 | */ | |
2141 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2142 | { | |
2143 | struct efx_nic *efx; | |
2144 | ||
2145 | efx = pci_get_drvdata(pci_dev); | |
2146 | if (!efx) | |
2147 | return; | |
2148 | ||
2149 | /* Mark the NIC as fini, then stop the interface */ | |
2150 | rtnl_lock(); | |
2151 | efx->state = STATE_FINI; | |
2152 | dev_close(efx->net_dev); | |
2153 | ||
2154 | /* Allow any queued efx_resets() to complete */ | |
2155 | rtnl_unlock(); | |
2156 | ||
8ceee660 BH |
2157 | efx_unregister_netdev(efx); |
2158 | ||
7dde596e BH |
2159 | efx_mtd_remove(efx); |
2160 | ||
8ceee660 BH |
2161 | /* Wait for any scheduled resets to complete. No more will be |
2162 | * scheduled from this point because efx_stop_all() has been | |
2163 | * called, we are no longer registered with driverlink, and | |
2164 | * the net_device's have been removed. */ | |
1ab00629 | 2165 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2166 | |
2167 | efx_pci_remove_main(efx); | |
2168 | ||
8ceee660 | 2169 | efx_fini_io(efx); |
62776d03 | 2170 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2171 | |
2172 | pci_set_drvdata(pci_dev, NULL); | |
2173 | efx_fini_struct(efx); | |
2174 | free_netdev(efx->net_dev); | |
2175 | }; | |
2176 | ||
2177 | /* Main body of NIC initialisation | |
2178 | * This is called at module load (or hotplug insertion, theoretically). | |
2179 | */ | |
2180 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2181 | { | |
2182 | int rc; | |
2183 | ||
2184 | /* Do start-of-day initialisation */ | |
2185 | rc = efx_probe_all(efx); | |
2186 | if (rc) | |
2187 | goto fail1; | |
2188 | ||
2189 | rc = efx_init_napi(efx); | |
2190 | if (rc) | |
2191 | goto fail2; | |
2192 | ||
ef2b90ee | 2193 | rc = efx->type->init(efx); |
8ceee660 | 2194 | if (rc) { |
62776d03 BH |
2195 | netif_err(efx, probe, efx->net_dev, |
2196 | "failed to initialise NIC\n"); | |
278c0621 | 2197 | goto fail3; |
8ceee660 BH |
2198 | } |
2199 | ||
2200 | rc = efx_init_port(efx); | |
2201 | if (rc) { | |
62776d03 BH |
2202 | netif_err(efx, probe, efx->net_dev, |
2203 | "failed to initialise port\n"); | |
278c0621 | 2204 | goto fail4; |
8ceee660 BH |
2205 | } |
2206 | ||
bc3c90a2 | 2207 | efx_init_channels(efx); |
8ceee660 | 2208 | |
152b6a62 | 2209 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2210 | if (rc) |
278c0621 | 2211 | goto fail5; |
8ceee660 BH |
2212 | |
2213 | return 0; | |
2214 | ||
278c0621 | 2215 | fail5: |
bc3c90a2 | 2216 | efx_fini_channels(efx); |
8ceee660 | 2217 | efx_fini_port(efx); |
8ceee660 | 2218 | fail4: |
ef2b90ee | 2219 | efx->type->fini(efx); |
8ceee660 BH |
2220 | fail3: |
2221 | efx_fini_napi(efx); | |
2222 | fail2: | |
2223 | efx_remove_all(efx); | |
2224 | fail1: | |
2225 | return rc; | |
2226 | } | |
2227 | ||
2228 | /* NIC initialisation | |
2229 | * | |
2230 | * This is called at module load (or hotplug insertion, | |
2231 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2232 | * sets up and registers the network devices with the kernel and hooks | |
2233 | * the interrupt service routine. It does not prepare the device for | |
2234 | * transmission; this is left to the first time one of the network | |
2235 | * interfaces is brought up (i.e. efx_net_open). | |
2236 | */ | |
2237 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2238 | const struct pci_device_id *entry) | |
2239 | { | |
2240 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2241 | struct net_device *net_dev; | |
2242 | struct efx_nic *efx; | |
2243 | int i, rc; | |
2244 | ||
2245 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
a4900ac9 | 2246 | net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES); |
8ceee660 BH |
2247 | if (!net_dev) |
2248 | return -ENOMEM; | |
c383b537 | 2249 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2250 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2251 | NETIF_F_GRO); | |
738a8f4b BH |
2252 | if (type->offload_features & NETIF_F_V6_CSUM) |
2253 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2254 | /* Mask for features that also apply to VLAN devices */ |
2255 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2256 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2257 | efx = netdev_priv(net_dev); |
8ceee660 | 2258 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2259 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2260 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2261 | if (rc) | |
2262 | goto fail1; | |
2263 | ||
62776d03 BH |
2264 | netif_info(efx, probe, efx->net_dev, |
2265 | "Solarflare Communications NIC detected\n"); | |
8ceee660 BH |
2266 | |
2267 | /* Set up basic I/O (BAR mappings etc) */ | |
2268 | rc = efx_init_io(efx); | |
2269 | if (rc) | |
2270 | goto fail2; | |
2271 | ||
2272 | /* No serialisation is required with the reset path because | |
2273 | * we're in STATE_INIT. */ | |
2274 | for (i = 0; i < 5; i++) { | |
2275 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2276 | |
2277 | /* Serialise against efx_reset(). No more resets will be | |
2278 | * scheduled since efx_stop_all() has been called, and we | |
2279 | * have not and never have been registered with either | |
2280 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2281 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2282 | |
fa402b2e SH |
2283 | if (rc == 0) { |
2284 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2285 | /* If there was a scheduled reset during | |
2286 | * probe, the NIC is probably hosed anyway */ | |
2287 | efx_pci_remove_main(efx); | |
2288 | rc = -EIO; | |
2289 | } else { | |
2290 | break; | |
2291 | } | |
2292 | } | |
2293 | ||
8ceee660 BH |
2294 | /* Retry if a recoverably reset event has been scheduled */ |
2295 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2296 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2297 | goto fail3; | |
2298 | ||
2299 | efx->reset_pending = RESET_TYPE_NONE; | |
2300 | } | |
2301 | ||
2302 | if (rc) { | |
62776d03 | 2303 | netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); |
8ceee660 BH |
2304 | goto fail4; |
2305 | } | |
2306 | ||
55edc6e6 BH |
2307 | /* Switch to the running state before we expose the device to the OS, |
2308 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2309 | efx->state = STATE_RUNNING; |
7dde596e | 2310 | |
8ceee660 BH |
2311 | rc = efx_register_netdev(efx); |
2312 | if (rc) | |
2313 | goto fail5; | |
2314 | ||
62776d03 | 2315 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 BH |
2316 | |
2317 | rtnl_lock(); | |
2318 | efx_mtd_probe(efx); /* allowed to fail */ | |
2319 | rtnl_unlock(); | |
8ceee660 BH |
2320 | return 0; |
2321 | ||
2322 | fail5: | |
2323 | efx_pci_remove_main(efx); | |
2324 | fail4: | |
2325 | fail3: | |
2326 | efx_fini_io(efx); | |
2327 | fail2: | |
2328 | efx_fini_struct(efx); | |
2329 | fail1: | |
5e2a911c | 2330 | WARN_ON(rc > 0); |
62776d03 | 2331 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2332 | free_netdev(net_dev); |
2333 | return rc; | |
2334 | } | |
2335 | ||
89c758fa BH |
2336 | static int efx_pm_freeze(struct device *dev) |
2337 | { | |
2338 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2339 | ||
2340 | efx->state = STATE_FINI; | |
2341 | ||
2342 | netif_device_detach(efx->net_dev); | |
2343 | ||
2344 | efx_stop_all(efx); | |
2345 | efx_fini_channels(efx); | |
2346 | ||
2347 | return 0; | |
2348 | } | |
2349 | ||
2350 | static int efx_pm_thaw(struct device *dev) | |
2351 | { | |
2352 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2353 | ||
2354 | efx->state = STATE_INIT; | |
2355 | ||
2356 | efx_init_channels(efx); | |
2357 | ||
2358 | mutex_lock(&efx->mac_lock); | |
2359 | efx->phy_op->reconfigure(efx); | |
2360 | mutex_unlock(&efx->mac_lock); | |
2361 | ||
2362 | efx_start_all(efx); | |
2363 | ||
2364 | netif_device_attach(efx->net_dev); | |
2365 | ||
2366 | efx->state = STATE_RUNNING; | |
2367 | ||
2368 | efx->type->resume_wol(efx); | |
2369 | ||
319ba649 SH |
2370 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2371 | queue_work(reset_workqueue, &efx->reset_work); | |
2372 | ||
89c758fa BH |
2373 | return 0; |
2374 | } | |
2375 | ||
2376 | static int efx_pm_poweroff(struct device *dev) | |
2377 | { | |
2378 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2379 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2380 | ||
2381 | efx->type->fini(efx); | |
2382 | ||
2383 | efx->reset_pending = RESET_TYPE_NONE; | |
2384 | ||
2385 | pci_save_state(pci_dev); | |
2386 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2387 | } | |
2388 | ||
2389 | /* Used for both resume and restore */ | |
2390 | static int efx_pm_resume(struct device *dev) | |
2391 | { | |
2392 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2393 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2394 | int rc; | |
2395 | ||
2396 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2397 | if (rc) | |
2398 | return rc; | |
2399 | pci_restore_state(pci_dev); | |
2400 | rc = pci_enable_device(pci_dev); | |
2401 | if (rc) | |
2402 | return rc; | |
2403 | pci_set_master(efx->pci_dev); | |
2404 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2405 | if (rc) | |
2406 | return rc; | |
2407 | rc = efx->type->init(efx); | |
2408 | if (rc) | |
2409 | return rc; | |
2410 | efx_pm_thaw(dev); | |
2411 | return 0; | |
2412 | } | |
2413 | ||
2414 | static int efx_pm_suspend(struct device *dev) | |
2415 | { | |
2416 | int rc; | |
2417 | ||
2418 | efx_pm_freeze(dev); | |
2419 | rc = efx_pm_poweroff(dev); | |
2420 | if (rc) | |
2421 | efx_pm_resume(dev); | |
2422 | return rc; | |
2423 | } | |
2424 | ||
2425 | static struct dev_pm_ops efx_pm_ops = { | |
2426 | .suspend = efx_pm_suspend, | |
2427 | .resume = efx_pm_resume, | |
2428 | .freeze = efx_pm_freeze, | |
2429 | .thaw = efx_pm_thaw, | |
2430 | .poweroff = efx_pm_poweroff, | |
2431 | .restore = efx_pm_resume, | |
2432 | }; | |
2433 | ||
8ceee660 BH |
2434 | static struct pci_driver efx_pci_driver = { |
2435 | .name = EFX_DRIVER_NAME, | |
2436 | .id_table = efx_pci_table, | |
2437 | .probe = efx_pci_probe, | |
2438 | .remove = efx_pci_remove, | |
89c758fa | 2439 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2440 | }; |
2441 | ||
2442 | /************************************************************************** | |
2443 | * | |
2444 | * Kernel module interface | |
2445 | * | |
2446 | *************************************************************************/ | |
2447 | ||
2448 | module_param(interrupt_mode, uint, 0444); | |
2449 | MODULE_PARM_DESC(interrupt_mode, | |
2450 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2451 | ||
2452 | static int __init efx_init_module(void) | |
2453 | { | |
2454 | int rc; | |
2455 | ||
2456 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2457 | ||
2458 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2459 | if (rc) | |
2460 | goto err_notifier; | |
2461 | ||
1ab00629 SH |
2462 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2463 | if (!reset_workqueue) { | |
2464 | rc = -ENOMEM; | |
2465 | goto err_reset; | |
2466 | } | |
8ceee660 BH |
2467 | |
2468 | rc = pci_register_driver(&efx_pci_driver); | |
2469 | if (rc < 0) | |
2470 | goto err_pci; | |
2471 | ||
2472 | return 0; | |
2473 | ||
2474 | err_pci: | |
1ab00629 SH |
2475 | destroy_workqueue(reset_workqueue); |
2476 | err_reset: | |
8ceee660 BH |
2477 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2478 | err_notifier: | |
2479 | return rc; | |
2480 | } | |
2481 | ||
2482 | static void __exit efx_exit_module(void) | |
2483 | { | |
2484 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2485 | ||
2486 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2487 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2488 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2489 | ||
2490 | } | |
2491 | ||
2492 | module_init(efx_init_module); | |
2493 | module_exit(efx_exit_module); | |
2494 | ||
906bb26c BH |
2495 | MODULE_AUTHOR("Solarflare Communications and " |
2496 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2497 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2498 | MODULE_LICENSE("GPL"); | |
2499 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |