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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "ethtool.h" |
25 | #include "tx.h" | |
26 | #include "rx.h" | |
27 | #include "efx.h" | |
28 | #include "mdio_10g.h" | |
29 | #include "falcon.h" | |
8ceee660 BH |
30 | |
31 | #define EFX_MAX_MTU (9 * 1024) | |
32 | ||
33 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
34 | * a work item is pushed onto this work queue to retry the allocation later, | |
35 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
36 | * workqueue, there is nothing to be gained in making it per NIC | |
37 | */ | |
38 | static struct workqueue_struct *refill_workqueue; | |
39 | ||
1ab00629 SH |
40 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
41 | * queued onto this work queue. This is not a per-nic work queue, because | |
42 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
43 | */ | |
44 | static struct workqueue_struct *reset_workqueue; | |
45 | ||
8ceee660 BH |
46 | /************************************************************************** |
47 | * | |
48 | * Configurable values | |
49 | * | |
50 | *************************************************************************/ | |
51 | ||
52 | /* | |
53 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
54 | * | |
55 | * This sets the default for new devices. It can be controlled later | |
56 | * using ethtool. | |
57 | */ | |
dc8cfa55 | 58 | static int lro = true; |
8ceee660 BH |
59 | module_param(lro, int, 0644); |
60 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
61 | ||
62 | /* | |
63 | * Use separate channels for TX and RX events | |
64 | * | |
28b581ab NT |
65 | * Set this to 1 to use separate channels for TX and RX. It allows us |
66 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 67 | * |
28b581ab | 68 | * This is only used in MSI-X interrupt mode |
8ceee660 | 69 | */ |
28b581ab NT |
70 | static unsigned int separate_tx_channels; |
71 | module_param(separate_tx_channels, uint, 0644); | |
72 | MODULE_PARM_DESC(separate_tx_channels, | |
73 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
74 | |
75 | /* This is the weight assigned to each of the (per-channel) virtual | |
76 | * NAPI devices. | |
77 | */ | |
78 | static int napi_weight = 64; | |
79 | ||
80 | /* This is the time (in jiffies) between invocations of the hardware | |
81 | * monitor, which checks for known hardware bugs and resets the | |
82 | * hardware and driver as necessary. | |
83 | */ | |
84 | unsigned int efx_monitor_interval = 1 * HZ; | |
85 | ||
8ceee660 BH |
86 | /* This controls whether or not the driver will initialise devices |
87 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
88 | * such devices will be initialised with a random locally-generated | |
89 | * MAC address. This allows for loading the sfc_mtd driver to | |
90 | * reprogram the flash, even if the flash contents (including the MAC | |
91 | * address) have previously been erased. | |
92 | */ | |
93 | static unsigned int allow_bad_hwaddr; | |
94 | ||
95 | /* Initial interrupt moderation settings. They can be modified after | |
96 | * module load with ethtool. | |
97 | * | |
98 | * The default for RX should strike a balance between increasing the | |
99 | * round-trip latency and reducing overhead. | |
100 | */ | |
101 | static unsigned int rx_irq_mod_usec = 60; | |
102 | ||
103 | /* Initial interrupt moderation settings. They can be modified after | |
104 | * module load with ethtool. | |
105 | * | |
106 | * This default is chosen to ensure that a 10G link does not go idle | |
107 | * while a TX queue is stopped after it has become full. A queue is | |
108 | * restarted when it drops below half full. The time this takes (assuming | |
109 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
110 | * 512 / 3 * 1.2 = 205 usec. | |
111 | */ | |
112 | static unsigned int tx_irq_mod_usec = 150; | |
113 | ||
114 | /* This is the first interrupt mode to try out of: | |
115 | * 0 => MSI-X | |
116 | * 1 => MSI | |
117 | * 2 => legacy | |
118 | */ | |
119 | static unsigned int interrupt_mode; | |
120 | ||
121 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
122 | * i.e. the number of CPUs among which we may distribute simultaneous | |
123 | * interrupt handling. | |
124 | * | |
125 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
126 | * The default (0) means to assign an interrupt to each package (level II cache) | |
127 | */ | |
128 | static unsigned int rss_cpus; | |
129 | module_param(rss_cpus, uint, 0444); | |
130 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
131 | ||
84ae48fe BH |
132 | static int phy_flash_cfg; |
133 | module_param(phy_flash_cfg, int, 0644); | |
134 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
135 | ||
8ceee660 BH |
136 | /************************************************************************** |
137 | * | |
138 | * Utility functions and prototypes | |
139 | * | |
140 | *************************************************************************/ | |
141 | static void efx_remove_channel(struct efx_channel *channel); | |
142 | static void efx_remove_port(struct efx_nic *efx); | |
143 | static void efx_fini_napi(struct efx_nic *efx); | |
144 | static void efx_fini_channels(struct efx_nic *efx); | |
145 | ||
146 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
147 | do { \ | |
3c78708f | 148 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
149 | ASSERT_RTNL(); \ |
150 | } while (0) | |
151 | ||
152 | /************************************************************************** | |
153 | * | |
154 | * Event queue processing | |
155 | * | |
156 | *************************************************************************/ | |
157 | ||
158 | /* Process channel's event queue | |
159 | * | |
160 | * This function is responsible for processing the event queue of a | |
161 | * single channel. The caller must guarantee that this function will | |
162 | * never be concurrently called more than once on the same channel, | |
163 | * though different channels may be being processed concurrently. | |
164 | */ | |
4d566063 | 165 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 166 | { |
42cbe2d7 BH |
167 | struct efx_nic *efx = channel->efx; |
168 | int rx_packets; | |
8ceee660 | 169 | |
42cbe2d7 | 170 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 171 | !channel->enabled)) |
42cbe2d7 | 172 | return 0; |
8ceee660 | 173 | |
42cbe2d7 BH |
174 | rx_packets = falcon_process_eventq(channel, rx_quota); |
175 | if (rx_packets == 0) | |
176 | return 0; | |
8ceee660 BH |
177 | |
178 | /* Deliver last RX packet. */ | |
179 | if (channel->rx_pkt) { | |
180 | __efx_rx_packet(channel, channel->rx_pkt, | |
181 | channel->rx_pkt_csummed); | |
182 | channel->rx_pkt = NULL; | |
183 | } | |
184 | ||
185 | efx_flush_lro(channel); | |
186 | efx_rx_strategy(channel); | |
187 | ||
42cbe2d7 | 188 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 189 | |
42cbe2d7 | 190 | return rx_packets; |
8ceee660 BH |
191 | } |
192 | ||
193 | /* Mark channel as finished processing | |
194 | * | |
195 | * Note that since we will not receive further interrupts for this | |
196 | * channel before we finish processing and call the eventq_read_ack() | |
197 | * method, there is no need to use the interrupt hold-off timers. | |
198 | */ | |
199 | static inline void efx_channel_processed(struct efx_channel *channel) | |
200 | { | |
5b9e207c BH |
201 | /* The interrupt handler for this channel may set work_pending |
202 | * as soon as we acknowledge the events we've seen. Make sure | |
203 | * it's cleared before then. */ | |
dc8cfa55 | 204 | channel->work_pending = false; |
5b9e207c BH |
205 | smp_wmb(); |
206 | ||
8ceee660 BH |
207 | falcon_eventq_read_ack(channel); |
208 | } | |
209 | ||
210 | /* NAPI poll handler | |
211 | * | |
212 | * NAPI guarantees serialisation of polls of the same device, which | |
213 | * provides the guarantee required by efx_process_channel(). | |
214 | */ | |
215 | static int efx_poll(struct napi_struct *napi, int budget) | |
216 | { | |
217 | struct efx_channel *channel = | |
218 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
219 | int rx_packets; |
220 | ||
221 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
222 | channel->channel, raw_smp_processor_id()); | |
223 | ||
42cbe2d7 | 224 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
225 | |
226 | if (rx_packets < budget) { | |
227 | /* There is no race here; although napi_disable() will | |
228 | * only wait for netif_rx_complete(), this isn't a problem | |
229 | * since efx_channel_processed() will have no effect if | |
230 | * interrupts have already been disabled. | |
231 | */ | |
908a7a16 | 232 | netif_rx_complete(napi); |
8ceee660 BH |
233 | efx_channel_processed(channel); |
234 | } | |
235 | ||
236 | return rx_packets; | |
237 | } | |
238 | ||
239 | /* Process the eventq of the specified channel immediately on this CPU | |
240 | * | |
241 | * Disable hardware generated interrupts, wait for any existing | |
242 | * processing to finish, then directly poll (and ack ) the eventq. | |
243 | * Finally reenable NAPI and interrupts. | |
244 | * | |
245 | * Since we are touching interrupts the caller should hold the suspend lock | |
246 | */ | |
247 | void efx_process_channel_now(struct efx_channel *channel) | |
248 | { | |
249 | struct efx_nic *efx = channel->efx; | |
250 | ||
251 | BUG_ON(!channel->used_flags); | |
252 | BUG_ON(!channel->enabled); | |
253 | ||
254 | /* Disable interrupts and wait for ISRs to complete */ | |
255 | falcon_disable_interrupts(efx); | |
256 | if (efx->legacy_irq) | |
257 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 258 | if (channel->irq) |
8ceee660 BH |
259 | synchronize_irq(channel->irq); |
260 | ||
261 | /* Wait for any NAPI processing to complete */ | |
262 | napi_disable(&channel->napi_str); | |
263 | ||
264 | /* Poll the channel */ | |
91ad757c | 265 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
266 | |
267 | /* Ack the eventq. This may cause an interrupt to be generated | |
268 | * when they are reenabled */ | |
269 | efx_channel_processed(channel); | |
270 | ||
271 | napi_enable(&channel->napi_str); | |
272 | falcon_enable_interrupts(efx); | |
273 | } | |
274 | ||
275 | /* Create event queue | |
276 | * Event queue memory allocations are done only once. If the channel | |
277 | * is reset, the memory buffer will be reused; this guards against | |
278 | * errors during channel reset and also simplifies interrupt handling. | |
279 | */ | |
280 | static int efx_probe_eventq(struct efx_channel *channel) | |
281 | { | |
282 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
283 | ||
284 | return falcon_probe_eventq(channel); | |
285 | } | |
286 | ||
287 | /* Prepare channel's event queue */ | |
bc3c90a2 | 288 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
289 | { |
290 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
291 | ||
292 | channel->eventq_read_ptr = 0; | |
293 | ||
bc3c90a2 | 294 | falcon_init_eventq(channel); |
8ceee660 BH |
295 | } |
296 | ||
297 | static void efx_fini_eventq(struct efx_channel *channel) | |
298 | { | |
299 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
300 | ||
301 | falcon_fini_eventq(channel); | |
302 | } | |
303 | ||
304 | static void efx_remove_eventq(struct efx_channel *channel) | |
305 | { | |
306 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
307 | ||
308 | falcon_remove_eventq(channel); | |
309 | } | |
310 | ||
311 | /************************************************************************** | |
312 | * | |
313 | * Channel handling | |
314 | * | |
315 | *************************************************************************/ | |
316 | ||
8ceee660 BH |
317 | static int efx_probe_channel(struct efx_channel *channel) |
318 | { | |
319 | struct efx_tx_queue *tx_queue; | |
320 | struct efx_rx_queue *rx_queue; | |
321 | int rc; | |
322 | ||
323 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
324 | ||
325 | rc = efx_probe_eventq(channel); | |
326 | if (rc) | |
327 | goto fail1; | |
328 | ||
329 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
330 | rc = efx_probe_tx_queue(tx_queue); | |
331 | if (rc) | |
332 | goto fail2; | |
333 | } | |
334 | ||
335 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
336 | rc = efx_probe_rx_queue(rx_queue); | |
337 | if (rc) | |
338 | goto fail3; | |
339 | } | |
340 | ||
341 | channel->n_rx_frm_trunc = 0; | |
342 | ||
343 | return 0; | |
344 | ||
345 | fail3: | |
346 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
347 | efx_remove_rx_queue(rx_queue); | |
348 | fail2: | |
349 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
350 | efx_remove_tx_queue(tx_queue); | |
351 | fail1: | |
352 | return rc; | |
353 | } | |
354 | ||
355 | ||
56536e9c BH |
356 | static void efx_set_channel_names(struct efx_nic *efx) |
357 | { | |
358 | struct efx_channel *channel; | |
359 | const char *type = ""; | |
360 | int number; | |
361 | ||
362 | efx_for_each_channel(channel, efx) { | |
363 | number = channel->channel; | |
364 | if (efx->n_channels > efx->n_rx_queues) { | |
365 | if (channel->channel < efx->n_rx_queues) { | |
366 | type = "-rx"; | |
367 | } else { | |
368 | type = "-tx"; | |
369 | number -= efx->n_rx_queues; | |
370 | } | |
371 | } | |
372 | snprintf(channel->name, sizeof(channel->name), | |
373 | "%s%s-%d", efx->name, type, number); | |
374 | } | |
375 | } | |
376 | ||
8ceee660 BH |
377 | /* Channels are shutdown and reinitialised whilst the NIC is running |
378 | * to propagate configuration changes (mtu, checksum offload), or | |
379 | * to clear hardware error conditions | |
380 | */ | |
bc3c90a2 | 381 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
382 | { |
383 | struct efx_tx_queue *tx_queue; | |
384 | struct efx_rx_queue *rx_queue; | |
385 | struct efx_channel *channel; | |
8ceee660 | 386 | |
f7f13b0b BH |
387 | /* Calculate the rx buffer allocation parameters required to |
388 | * support the current MTU, including padding for header | |
389 | * alignment and overruns. | |
390 | */ | |
391 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
392 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
393 | efx->type->rx_buffer_padding); | |
394 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
395 | |
396 | /* Initialise the channels */ | |
397 | efx_for_each_channel(channel, efx) { | |
398 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
399 | ||
bc3c90a2 | 400 | efx_init_eventq(channel); |
8ceee660 | 401 | |
bc3c90a2 BH |
402 | efx_for_each_channel_tx_queue(tx_queue, channel) |
403 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
404 | |
405 | /* The rx buffer allocation strategy is MTU dependent */ | |
406 | efx_rx_strategy(channel); | |
407 | ||
bc3c90a2 BH |
408 | efx_for_each_channel_rx_queue(rx_queue, channel) |
409 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
410 | |
411 | WARN_ON(channel->rx_pkt != NULL); | |
412 | efx_rx_strategy(channel); | |
413 | } | |
8ceee660 BH |
414 | } |
415 | ||
416 | /* This enables event queue processing and packet transmission. | |
417 | * | |
418 | * Note that this function is not allowed to fail, since that would | |
419 | * introduce too much complexity into the suspend/resume path. | |
420 | */ | |
421 | static void efx_start_channel(struct efx_channel *channel) | |
422 | { | |
423 | struct efx_rx_queue *rx_queue; | |
424 | ||
425 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
426 | ||
427 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
428 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
429 | efx_poll, napi_weight); | |
430 | ||
5b9e207c BH |
431 | /* The interrupt handler for this channel may set work_pending |
432 | * as soon as we enable it. Make sure it's cleared before | |
433 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
434 | channel->work_pending = false; |
435 | channel->enabled = true; | |
5b9e207c | 436 | smp_wmb(); |
8ceee660 BH |
437 | |
438 | napi_enable(&channel->napi_str); | |
439 | ||
440 | /* Load up RX descriptors */ | |
441 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
442 | efx_fast_push_rx_descriptors(rx_queue); | |
443 | } | |
444 | ||
445 | /* This disables event queue processing and packet transmission. | |
446 | * This function does not guarantee that all queue processing | |
447 | * (e.g. RX refill) is complete. | |
448 | */ | |
449 | static void efx_stop_channel(struct efx_channel *channel) | |
450 | { | |
451 | struct efx_rx_queue *rx_queue; | |
452 | ||
453 | if (!channel->enabled) | |
454 | return; | |
455 | ||
456 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
457 | ||
dc8cfa55 | 458 | channel->enabled = false; |
8ceee660 BH |
459 | napi_disable(&channel->napi_str); |
460 | ||
461 | /* Ensure that any worker threads have exited or will be no-ops */ | |
462 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
463 | spin_lock_bh(&rx_queue->add_lock); | |
464 | spin_unlock_bh(&rx_queue->add_lock); | |
465 | } | |
466 | } | |
467 | ||
468 | static void efx_fini_channels(struct efx_nic *efx) | |
469 | { | |
470 | struct efx_channel *channel; | |
471 | struct efx_tx_queue *tx_queue; | |
472 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 473 | int rc; |
8ceee660 BH |
474 | |
475 | EFX_ASSERT_RESET_SERIALISED(efx); | |
476 | BUG_ON(efx->port_enabled); | |
477 | ||
6bc5d3a9 BH |
478 | rc = falcon_flush_queues(efx); |
479 | if (rc) | |
480 | EFX_ERR(efx, "failed to flush queues\n"); | |
481 | else | |
482 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
483 | ||
8ceee660 BH |
484 | efx_for_each_channel(channel, efx) { |
485 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
486 | ||
487 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
488 | efx_fini_rx_queue(rx_queue); | |
489 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
490 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
491 | efx_fini_eventq(channel); |
492 | } | |
493 | } | |
494 | ||
495 | static void efx_remove_channel(struct efx_channel *channel) | |
496 | { | |
497 | struct efx_tx_queue *tx_queue; | |
498 | struct efx_rx_queue *rx_queue; | |
499 | ||
500 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
501 | ||
502 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
503 | efx_remove_rx_queue(rx_queue); | |
504 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
505 | efx_remove_tx_queue(tx_queue); | |
506 | efx_remove_eventq(channel); | |
507 | ||
508 | channel->used_flags = 0; | |
509 | } | |
510 | ||
511 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
512 | { | |
513 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
514 | } | |
515 | ||
516 | /************************************************************************** | |
517 | * | |
518 | * Port handling | |
519 | * | |
520 | **************************************************************************/ | |
521 | ||
522 | /* This ensures that the kernel is kept informed (via | |
523 | * netif_carrier_on/off) of the link status, and also maintains the | |
524 | * link status's stop on the port's TX queue. | |
525 | */ | |
526 | static void efx_link_status_changed(struct efx_nic *efx) | |
527 | { | |
8ceee660 BH |
528 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
529 | * that no events are triggered between unregister_netdev() and the | |
530 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
531 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
532 | if (!netif_running(efx->net_dev)) | |
533 | return; | |
534 | ||
8c8661e4 BH |
535 | if (efx->port_inhibited) { |
536 | netif_carrier_off(efx->net_dev); | |
537 | return; | |
538 | } | |
539 | ||
dc8cfa55 | 540 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
541 | efx->n_link_state_changes++; |
542 | ||
543 | if (efx->link_up) | |
544 | netif_carrier_on(efx->net_dev); | |
545 | else | |
546 | netif_carrier_off(efx->net_dev); | |
547 | } | |
548 | ||
549 | /* Status message for kernel log */ | |
550 | if (efx->link_up) { | |
f31a45d2 BH |
551 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
552 | efx->link_speed, efx->link_fd ? "full" : "half", | |
8ceee660 BH |
553 | efx->net_dev->mtu, |
554 | (efx->promiscuous ? " [PROMISC]" : "")); | |
555 | } else { | |
556 | EFX_INFO(efx, "link down\n"); | |
557 | } | |
558 | ||
559 | } | |
560 | ||
561 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
562 | * caller must hold the mac_lock */ | |
8c8661e4 | 563 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
564 | { |
565 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
566 | ||
567 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
568 | raw_smp_processor_id()); | |
569 | ||
a816f75a BH |
570 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
571 | if (efx_dev_registered(efx)) { | |
572 | netif_addr_lock_bh(efx->net_dev); | |
573 | netif_addr_unlock_bh(efx->net_dev); | |
574 | } | |
575 | ||
177dfcd8 BH |
576 | falcon_deconfigure_mac_wrapper(efx); |
577 | ||
578 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
579 | if (LOOPBACK_INTERNAL(efx)) | |
580 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
581 | else | |
582 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
583 | efx->phy_op->reconfigure(efx); | |
584 | ||
585 | if (falcon_switch_mac(efx)) | |
586 | goto fail; | |
587 | ||
588 | efx->mac_op->reconfigure(efx); | |
8ceee660 BH |
589 | |
590 | /* Inform kernel of loss/gain of carrier */ | |
591 | efx_link_status_changed(efx); | |
177dfcd8 BH |
592 | return; |
593 | ||
594 | fail: | |
595 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
596 | efx->phy_op->fini(efx); | |
597 | efx->port_initialized = false; | |
8ceee660 BH |
598 | } |
599 | ||
600 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
601 | * disabled. */ | |
602 | void efx_reconfigure_port(struct efx_nic *efx) | |
603 | { | |
604 | EFX_ASSERT_RESET_SERIALISED(efx); | |
605 | ||
606 | mutex_lock(&efx->mac_lock); | |
607 | __efx_reconfigure_port(efx); | |
608 | mutex_unlock(&efx->mac_lock); | |
609 | } | |
610 | ||
611 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
612 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
613 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 614 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 615 | { |
766ca0fa | 616 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
617 | |
618 | mutex_lock(&efx->mac_lock); | |
619 | if (efx->port_enabled) | |
620 | __efx_reconfigure_port(efx); | |
621 | mutex_unlock(&efx->mac_lock); | |
622 | } | |
623 | ||
766ca0fa BH |
624 | static void efx_mac_work(struct work_struct *data) |
625 | { | |
626 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
627 | ||
628 | mutex_lock(&efx->mac_lock); | |
629 | if (efx->port_enabled) | |
630 | efx->mac_op->irq(efx); | |
631 | mutex_unlock(&efx->mac_lock); | |
632 | } | |
633 | ||
8ceee660 BH |
634 | static int efx_probe_port(struct efx_nic *efx) |
635 | { | |
636 | int rc; | |
637 | ||
638 | EFX_LOG(efx, "create port\n"); | |
639 | ||
640 | /* Connect up MAC/PHY operations table and read MAC address */ | |
641 | rc = falcon_probe_port(efx); | |
642 | if (rc) | |
643 | goto err; | |
644 | ||
84ae48fe BH |
645 | if (phy_flash_cfg) |
646 | efx->phy_mode = PHY_MODE_SPECIAL; | |
647 | ||
8ceee660 BH |
648 | /* Sanity check MAC address */ |
649 | if (is_valid_ether_addr(efx->mac_address)) { | |
650 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
651 | } else { | |
e174961c JB |
652 | EFX_ERR(efx, "invalid MAC address %pM\n", |
653 | efx->mac_address); | |
8ceee660 BH |
654 | if (!allow_bad_hwaddr) { |
655 | rc = -EINVAL; | |
656 | goto err; | |
657 | } | |
658 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
659 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
660 | efx->net_dev->dev_addr); | |
8ceee660 BH |
661 | } |
662 | ||
663 | return 0; | |
664 | ||
665 | err: | |
666 | efx_remove_port(efx); | |
667 | return rc; | |
668 | } | |
669 | ||
670 | static int efx_init_port(struct efx_nic *efx) | |
671 | { | |
672 | int rc; | |
673 | ||
674 | EFX_LOG(efx, "init port\n"); | |
675 | ||
177dfcd8 | 676 | rc = efx->phy_op->init(efx); |
8ceee660 BH |
677 | if (rc) |
678 | return rc; | |
177dfcd8 BH |
679 | efx->phy_op->reconfigure(efx); |
680 | ||
681 | mutex_lock(&efx->mac_lock); | |
682 | rc = falcon_switch_mac(efx); | |
683 | mutex_unlock(&efx->mac_lock); | |
684 | if (rc) | |
685 | goto fail; | |
686 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 687 | |
dc8cfa55 | 688 | efx->port_initialized = true; |
8c8661e4 | 689 | efx->stats_enabled = true; |
8ceee660 | 690 | return 0; |
177dfcd8 BH |
691 | |
692 | fail: | |
693 | efx->phy_op->fini(efx); | |
694 | return rc; | |
8ceee660 BH |
695 | } |
696 | ||
697 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
698 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 699 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
700 | static void efx_start_port(struct efx_nic *efx) |
701 | { | |
702 | EFX_LOG(efx, "start port\n"); | |
703 | BUG_ON(efx->port_enabled); | |
704 | ||
705 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 706 | efx->port_enabled = true; |
8ceee660 | 707 | __efx_reconfigure_port(efx); |
766ca0fa | 708 | efx->mac_op->irq(efx); |
8ceee660 BH |
709 | mutex_unlock(&efx->mac_lock); |
710 | } | |
711 | ||
766ca0fa BH |
712 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
713 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
714 | * and efx_mac_work may still be scheduled via NAPI processing until | |
715 | * efx_flush_all() is called */ | |
8ceee660 BH |
716 | static void efx_stop_port(struct efx_nic *efx) |
717 | { | |
718 | EFX_LOG(efx, "stop port\n"); | |
719 | ||
720 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 721 | efx->port_enabled = false; |
8ceee660 BH |
722 | mutex_unlock(&efx->mac_lock); |
723 | ||
724 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 725 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
726 | netif_addr_lock_bh(efx->net_dev); |
727 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
728 | } |
729 | } | |
730 | ||
731 | static void efx_fini_port(struct efx_nic *efx) | |
732 | { | |
733 | EFX_LOG(efx, "shut down port\n"); | |
734 | ||
735 | if (!efx->port_initialized) | |
736 | return; | |
737 | ||
177dfcd8 | 738 | efx->phy_op->fini(efx); |
dc8cfa55 | 739 | efx->port_initialized = false; |
8ceee660 | 740 | |
dc8cfa55 | 741 | efx->link_up = false; |
8ceee660 BH |
742 | efx_link_status_changed(efx); |
743 | } | |
744 | ||
745 | static void efx_remove_port(struct efx_nic *efx) | |
746 | { | |
747 | EFX_LOG(efx, "destroying port\n"); | |
748 | ||
749 | falcon_remove_port(efx); | |
750 | } | |
751 | ||
752 | /************************************************************************** | |
753 | * | |
754 | * NIC handling | |
755 | * | |
756 | **************************************************************************/ | |
757 | ||
758 | /* This configures the PCI device to enable I/O and DMA. */ | |
759 | static int efx_init_io(struct efx_nic *efx) | |
760 | { | |
761 | struct pci_dev *pci_dev = efx->pci_dev; | |
762 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
763 | int rc; | |
764 | ||
765 | EFX_LOG(efx, "initialising I/O\n"); | |
766 | ||
767 | rc = pci_enable_device(pci_dev); | |
768 | if (rc) { | |
769 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
770 | goto fail1; | |
771 | } | |
772 | ||
773 | pci_set_master(pci_dev); | |
774 | ||
775 | /* Set the PCI DMA mask. Try all possibilities from our | |
776 | * genuine mask down to 32 bits, because some architectures | |
777 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
778 | * masks event though they reject 46 bit masks. | |
779 | */ | |
780 | while (dma_mask > 0x7fffffffUL) { | |
781 | if (pci_dma_supported(pci_dev, dma_mask) && | |
782 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
783 | break; | |
784 | dma_mask >>= 1; | |
785 | } | |
786 | if (rc) { | |
787 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
788 | goto fail2; | |
789 | } | |
790 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
791 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
792 | if (rc) { | |
793 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
794 | * fail with a mask that pci_set_dma_mask() accepted, | |
795 | * but just in case... | |
796 | */ | |
797 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
798 | goto fail2; | |
799 | } | |
800 | ||
801 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
802 | efx->type->mem_bar); | |
803 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
804 | if (rc) { | |
805 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
806 | rc = -EIO; | |
807 | goto fail3; | |
808 | } | |
809 | efx->membase = ioremap_nocache(efx->membase_phys, | |
810 | efx->type->mem_map_size); | |
811 | if (!efx->membase) { | |
086ea356 BH |
812 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
813 | efx->type->mem_bar, | |
814 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
815 | efx->type->mem_map_size); |
816 | rc = -ENOMEM; | |
817 | goto fail4; | |
818 | } | |
086ea356 BH |
819 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
820 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
821 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
822 | |
823 | return 0; | |
824 | ||
825 | fail4: | |
e1074a0d | 826 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 827 | fail3: |
2c118e0f | 828 | efx->membase_phys = 0; |
8ceee660 BH |
829 | fail2: |
830 | pci_disable_device(efx->pci_dev); | |
831 | fail1: | |
832 | return rc; | |
833 | } | |
834 | ||
835 | static void efx_fini_io(struct efx_nic *efx) | |
836 | { | |
837 | EFX_LOG(efx, "shutting down I/O\n"); | |
838 | ||
839 | if (efx->membase) { | |
840 | iounmap(efx->membase); | |
841 | efx->membase = NULL; | |
842 | } | |
843 | ||
844 | if (efx->membase_phys) { | |
845 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 846 | efx->membase_phys = 0; |
8ceee660 BH |
847 | } |
848 | ||
849 | pci_disable_device(efx->pci_dev); | |
850 | } | |
851 | ||
46123d04 BH |
852 | /* Get number of RX queues wanted. Return number of online CPU |
853 | * packages in the expectation that an IRQ balancer will spread | |
854 | * interrupts across them. */ | |
855 | static int efx_wanted_rx_queues(void) | |
856 | { | |
857 | cpumask_t core_mask; | |
858 | int count; | |
859 | int cpu; | |
860 | ||
861 | cpus_clear(core_mask); | |
862 | count = 0; | |
863 | for_each_online_cpu(cpu) { | |
864 | if (!cpu_isset(cpu, core_mask)) { | |
865 | ++count; | |
866 | cpus_or(core_mask, core_mask, | |
867 | topology_core_siblings(cpu)); | |
868 | } | |
869 | } | |
870 | ||
871 | return count; | |
872 | } | |
873 | ||
874 | /* Probe the number and type of interrupts we are able to obtain, and | |
875 | * the resulting numbers of channels and RX queues. | |
876 | */ | |
8ceee660 BH |
877 | static void efx_probe_interrupts(struct efx_nic *efx) |
878 | { | |
46123d04 BH |
879 | int max_channels = |
880 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
881 | int rc, i; |
882 | ||
883 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
884 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
885 | int wanted_ints; | |
28b581ab | 886 | int rx_queues; |
aa6ef27e | 887 | |
46123d04 BH |
888 | /* We want one RX queue and interrupt per CPU package |
889 | * (or as specified by the rss_cpus module parameter). | |
890 | * We will need one channel per interrupt. | |
891 | */ | |
28b581ab NT |
892 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
893 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
894 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 895 | |
28b581ab | 896 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 897 | xentries[i].entry = i; |
28b581ab | 898 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 899 | if (rc > 0) { |
28b581ab NT |
900 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
901 | " available (%d < %d).\n", rc, wanted_ints); | |
902 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
903 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
904 | wanted_ints = rc; | |
8ceee660 | 905 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 906 | wanted_ints); |
8ceee660 BH |
907 | } |
908 | ||
909 | if (rc == 0) { | |
28b581ab NT |
910 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
911 | efx->n_channels = wanted_ints; | |
912 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 913 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
914 | } else { |
915 | /* Fall back to single channel MSI */ | |
916 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
917 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
918 | } | |
919 | } | |
920 | ||
921 | /* Try single interrupt MSI */ | |
922 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 923 | efx->n_rx_queues = 1; |
28b581ab | 924 | efx->n_channels = 1; |
8ceee660 BH |
925 | rc = pci_enable_msi(efx->pci_dev); |
926 | if (rc == 0) { | |
927 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
928 | } else { |
929 | EFX_ERR(efx, "could not enable MSI\n"); | |
930 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
931 | } | |
932 | } | |
933 | ||
934 | /* Assume legacy interrupts */ | |
935 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 936 | efx->n_rx_queues = 1; |
28b581ab | 937 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
938 | efx->legacy_irq = efx->pci_dev->irq; |
939 | } | |
940 | } | |
941 | ||
942 | static void efx_remove_interrupts(struct efx_nic *efx) | |
943 | { | |
944 | struct efx_channel *channel; | |
945 | ||
946 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 947 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
948 | channel->irq = 0; |
949 | pci_disable_msi(efx->pci_dev); | |
950 | pci_disable_msix(efx->pci_dev); | |
951 | ||
952 | /* Remove legacy interrupt */ | |
953 | efx->legacy_irq = 0; | |
954 | } | |
955 | ||
8831da7b | 956 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
957 | { |
958 | struct efx_tx_queue *tx_queue; | |
959 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 960 | |
60ac1065 | 961 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
962 | if (separate_tx_channels) |
963 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
964 | else |
965 | tx_queue->channel = &efx->channel[0]; | |
966 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
967 | } | |
8ceee660 | 968 | |
8831da7b BH |
969 | efx_for_each_rx_queue(rx_queue, efx) { |
970 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
971 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
972 | } |
973 | } | |
974 | ||
975 | static int efx_probe_nic(struct efx_nic *efx) | |
976 | { | |
977 | int rc; | |
978 | ||
979 | EFX_LOG(efx, "creating NIC\n"); | |
980 | ||
981 | /* Carry out hardware-type specific initialisation */ | |
982 | rc = falcon_probe_nic(efx); | |
983 | if (rc) | |
984 | return rc; | |
985 | ||
986 | /* Determine the number of channels and RX queues by trying to hook | |
987 | * in MSI-X interrupts. */ | |
988 | efx_probe_interrupts(efx); | |
989 | ||
8831da7b | 990 | efx_set_channels(efx); |
8ceee660 BH |
991 | |
992 | /* Initialise the interrupt moderation settings */ | |
993 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
994 | ||
995 | return 0; | |
996 | } | |
997 | ||
998 | static void efx_remove_nic(struct efx_nic *efx) | |
999 | { | |
1000 | EFX_LOG(efx, "destroying NIC\n"); | |
1001 | ||
1002 | efx_remove_interrupts(efx); | |
1003 | falcon_remove_nic(efx); | |
1004 | } | |
1005 | ||
1006 | /************************************************************************** | |
1007 | * | |
1008 | * NIC startup/shutdown | |
1009 | * | |
1010 | *************************************************************************/ | |
1011 | ||
1012 | static int efx_probe_all(struct efx_nic *efx) | |
1013 | { | |
1014 | struct efx_channel *channel; | |
1015 | int rc; | |
1016 | ||
1017 | /* Create NIC */ | |
1018 | rc = efx_probe_nic(efx); | |
1019 | if (rc) { | |
1020 | EFX_ERR(efx, "failed to create NIC\n"); | |
1021 | goto fail1; | |
1022 | } | |
1023 | ||
1024 | /* Create port */ | |
1025 | rc = efx_probe_port(efx); | |
1026 | if (rc) { | |
1027 | EFX_ERR(efx, "failed to create port\n"); | |
1028 | goto fail2; | |
1029 | } | |
1030 | ||
1031 | /* Create channels */ | |
1032 | efx_for_each_channel(channel, efx) { | |
1033 | rc = efx_probe_channel(channel); | |
1034 | if (rc) { | |
1035 | EFX_ERR(efx, "failed to create channel %d\n", | |
1036 | channel->channel); | |
1037 | goto fail3; | |
1038 | } | |
1039 | } | |
56536e9c | 1040 | efx_set_channel_names(efx); |
8ceee660 BH |
1041 | |
1042 | return 0; | |
1043 | ||
1044 | fail3: | |
1045 | efx_for_each_channel(channel, efx) | |
1046 | efx_remove_channel(channel); | |
1047 | efx_remove_port(efx); | |
1048 | fail2: | |
1049 | efx_remove_nic(efx); | |
1050 | fail1: | |
1051 | return rc; | |
1052 | } | |
1053 | ||
1054 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1055 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1056 | * and ensures that the port is scheduled to be reconfigured. | |
1057 | * This function is safe to call multiple times when the NIC is in any | |
1058 | * state. */ | |
1059 | static void efx_start_all(struct efx_nic *efx) | |
1060 | { | |
1061 | struct efx_channel *channel; | |
1062 | ||
1063 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1064 | ||
1065 | /* Check that it is appropriate to restart the interface. All | |
1066 | * of these flags are safe to read under just the rtnl lock */ | |
1067 | if (efx->port_enabled) | |
1068 | return; | |
1069 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1070 | return; | |
55668611 | 1071 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1072 | return; |
1073 | ||
1074 | /* Mark the port as enabled so port reconfigurations can start, then | |
1075 | * restart the transmit interface early so the watchdog timer stops */ | |
1076 | efx_start_port(efx); | |
dacccc74 SH |
1077 | if (efx_dev_registered(efx)) |
1078 | efx_wake_queue(efx); | |
8ceee660 BH |
1079 | |
1080 | efx_for_each_channel(channel, efx) | |
1081 | efx_start_channel(channel); | |
1082 | ||
1083 | falcon_enable_interrupts(efx); | |
1084 | ||
1085 | /* Start hardware monitor if we're in RUNNING */ | |
1086 | if (efx->state == STATE_RUNNING) | |
1087 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1088 | efx_monitor_interval); | |
1089 | } | |
1090 | ||
1091 | /* Flush all delayed work. Should only be called when no more delayed work | |
1092 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1093 | * since we're holding the rtnl_lock at this point. */ | |
1094 | static void efx_flush_all(struct efx_nic *efx) | |
1095 | { | |
1096 | struct efx_rx_queue *rx_queue; | |
1097 | ||
1098 | /* Make sure the hardware monitor is stopped */ | |
1099 | cancel_delayed_work_sync(&efx->monitor_work); | |
1100 | ||
1101 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1102 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1103 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1104 | |
1105 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1106 | cancel_work_sync(&efx->mac_work); |
1107 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1108 | |
1109 | } | |
1110 | ||
1111 | /* Quiesce hardware and software without bringing the link down. | |
1112 | * Safe to call multiple times, when the nic and interface is in any | |
1113 | * state. The caller is guaranteed to subsequently be in a position | |
1114 | * to modify any hardware and software state they see fit without | |
1115 | * taking locks. */ | |
1116 | static void efx_stop_all(struct efx_nic *efx) | |
1117 | { | |
1118 | struct efx_channel *channel; | |
1119 | ||
1120 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1121 | ||
1122 | /* port_enabled can be read safely under the rtnl lock */ | |
1123 | if (!efx->port_enabled) | |
1124 | return; | |
1125 | ||
1126 | /* Disable interrupts and wait for ISR to complete */ | |
1127 | falcon_disable_interrupts(efx); | |
1128 | if (efx->legacy_irq) | |
1129 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1130 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1131 | if (channel->irq) |
1132 | synchronize_irq(channel->irq); | |
b3475645 | 1133 | } |
8ceee660 BH |
1134 | |
1135 | /* Stop all NAPI processing and synchronous rx refills */ | |
1136 | efx_for_each_channel(channel, efx) | |
1137 | efx_stop_channel(channel); | |
1138 | ||
1139 | /* Stop all asynchronous port reconfigurations. Since all | |
1140 | * event processing has already been stopped, there is no | |
1141 | * window to loose phy events */ | |
1142 | efx_stop_port(efx); | |
1143 | ||
766ca0fa | 1144 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1145 | efx_flush_all(efx); |
1146 | ||
1147 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1148 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1149 | falcon_drain_tx_fifo(efx); |
1150 | ||
1151 | /* Stop the kernel transmit interface late, so the watchdog | |
1152 | * timer isn't ticking over the flush */ | |
55668611 | 1153 | if (efx_dev_registered(efx)) { |
dacccc74 | 1154 | efx_stop_queue(efx); |
8ceee660 BH |
1155 | netif_tx_lock_bh(efx->net_dev); |
1156 | netif_tx_unlock_bh(efx->net_dev); | |
1157 | } | |
1158 | } | |
1159 | ||
1160 | static void efx_remove_all(struct efx_nic *efx) | |
1161 | { | |
1162 | struct efx_channel *channel; | |
1163 | ||
1164 | efx_for_each_channel(channel, efx) | |
1165 | efx_remove_channel(channel); | |
1166 | efx_remove_port(efx); | |
1167 | efx_remove_nic(efx); | |
1168 | } | |
1169 | ||
1170 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1171 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1172 | { |
8ceee660 BH |
1173 | EFX_ASSERT_RESET_SERIALISED(efx); |
1174 | ||
1175 | efx_stop_all(efx); | |
1176 | ||
1177 | efx_fini_channels(efx); | |
bc3c90a2 | 1178 | efx_init_channels(efx); |
8ceee660 BH |
1179 | |
1180 | efx_start_all(efx); | |
8ceee660 BH |
1181 | } |
1182 | ||
1183 | /************************************************************************** | |
1184 | * | |
1185 | * Interrupt moderation | |
1186 | * | |
1187 | **************************************************************************/ | |
1188 | ||
1189 | /* Set interrupt moderation parameters */ | |
1190 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1191 | { | |
1192 | struct efx_tx_queue *tx_queue; | |
1193 | struct efx_rx_queue *rx_queue; | |
1194 | ||
1195 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1196 | ||
1197 | efx_for_each_tx_queue(tx_queue, efx) | |
1198 | tx_queue->channel->irq_moderation = tx_usecs; | |
1199 | ||
1200 | efx_for_each_rx_queue(rx_queue, efx) | |
1201 | rx_queue->channel->irq_moderation = rx_usecs; | |
1202 | } | |
1203 | ||
1204 | /************************************************************************** | |
1205 | * | |
1206 | * Hardware monitor | |
1207 | * | |
1208 | **************************************************************************/ | |
1209 | ||
1210 | /* Run periodically off the general workqueue. Serialised against | |
1211 | * efx_reconfigure_port via the mac_lock */ | |
1212 | static void efx_monitor(struct work_struct *data) | |
1213 | { | |
1214 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1215 | monitor_work.work); | |
766ca0fa | 1216 | int rc; |
8ceee660 BH |
1217 | |
1218 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1219 | raw_smp_processor_id()); | |
1220 | ||
8ceee660 BH |
1221 | /* If the mac_lock is already held then it is likely a port |
1222 | * reconfiguration is already in place, which will likely do | |
1223 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1224 | if (!mutex_trylock(&efx->mac_lock)) |
1225 | goto out_requeue; | |
1226 | if (!efx->port_enabled) | |
1227 | goto out_unlock; | |
1228 | rc = efx->board_info.monitor(efx); | |
1229 | if (rc) { | |
1230 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
1231 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
1232 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
1233 | falcon_sim_phy_event(efx); | |
8ceee660 | 1234 | } |
766ca0fa BH |
1235 | efx->phy_op->poll(efx); |
1236 | efx->mac_op->poll(efx); | |
8ceee660 | 1237 | |
766ca0fa | 1238 | out_unlock: |
8ceee660 | 1239 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1240 | out_requeue: |
8ceee660 BH |
1241 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1242 | efx_monitor_interval); | |
1243 | } | |
1244 | ||
1245 | /************************************************************************** | |
1246 | * | |
1247 | * ioctls | |
1248 | * | |
1249 | *************************************************************************/ | |
1250 | ||
1251 | /* Net device ioctl | |
1252 | * Context: process, rtnl_lock() held. | |
1253 | */ | |
1254 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1255 | { | |
767e468c | 1256 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1257 | |
1258 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1259 | ||
1260 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1261 | } | |
1262 | ||
1263 | /************************************************************************** | |
1264 | * | |
1265 | * NAPI interface | |
1266 | * | |
1267 | **************************************************************************/ | |
1268 | ||
1269 | static int efx_init_napi(struct efx_nic *efx) | |
1270 | { | |
1271 | struct efx_channel *channel; | |
1272 | int rc; | |
1273 | ||
1274 | efx_for_each_channel(channel, efx) { | |
1275 | channel->napi_dev = efx->net_dev; | |
1276 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1277 | if (rc) | |
1278 | goto err; | |
1279 | } | |
1280 | return 0; | |
1281 | err: | |
1282 | efx_fini_napi(efx); | |
1283 | return rc; | |
1284 | } | |
1285 | ||
1286 | static void efx_fini_napi(struct efx_nic *efx) | |
1287 | { | |
1288 | struct efx_channel *channel; | |
1289 | ||
1290 | efx_for_each_channel(channel, efx) { | |
1291 | efx_lro_fini(&channel->lro_mgr); | |
1292 | channel->napi_dev = NULL; | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | /************************************************************************** | |
1297 | * | |
1298 | * Kernel netpoll interface | |
1299 | * | |
1300 | *************************************************************************/ | |
1301 | ||
1302 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1303 | ||
1304 | /* Although in the common case interrupts will be disabled, this is not | |
1305 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1306 | * so no locking is required. | |
1307 | */ | |
1308 | static void efx_netpoll(struct net_device *net_dev) | |
1309 | { | |
767e468c | 1310 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1311 | struct efx_channel *channel; |
1312 | ||
64ee3120 | 1313 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1314 | efx_schedule_channel(channel); |
1315 | } | |
1316 | ||
1317 | #endif | |
1318 | ||
1319 | /************************************************************************** | |
1320 | * | |
1321 | * Kernel net device interface | |
1322 | * | |
1323 | *************************************************************************/ | |
1324 | ||
1325 | /* Context: process, rtnl_lock() held. */ | |
1326 | static int efx_net_open(struct net_device *net_dev) | |
1327 | { | |
767e468c | 1328 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1329 | EFX_ASSERT_RESET_SERIALISED(efx); |
1330 | ||
1331 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1332 | raw_smp_processor_id()); | |
1333 | ||
f4bd954e BH |
1334 | if (efx->state == STATE_DISABLED) |
1335 | return -EIO; | |
f8b87c17 BH |
1336 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1337 | return -EBUSY; | |
1338 | ||
8ceee660 BH |
1339 | efx_start_all(efx); |
1340 | return 0; | |
1341 | } | |
1342 | ||
1343 | /* Context: process, rtnl_lock() held. | |
1344 | * Note that the kernel will ignore our return code; this method | |
1345 | * should really be a void. | |
1346 | */ | |
1347 | static int efx_net_stop(struct net_device *net_dev) | |
1348 | { | |
767e468c | 1349 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1350 | |
1351 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1352 | raw_smp_processor_id()); | |
1353 | ||
f4bd954e BH |
1354 | if (efx->state != STATE_DISABLED) { |
1355 | /* Stop the device and flush all the channels */ | |
1356 | efx_stop_all(efx); | |
1357 | efx_fini_channels(efx); | |
1358 | efx_init_channels(efx); | |
1359 | } | |
8ceee660 BH |
1360 | |
1361 | return 0; | |
1362 | } | |
1363 | ||
5b9e207c | 1364 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1365 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1366 | { | |
767e468c | 1367 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1368 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1369 | struct net_device_stats *stats = &net_dev->stats; | |
1370 | ||
5b9e207c BH |
1371 | /* Update stats if possible, but do not wait if another thread |
1372 | * is updating them (or resetting the NIC); slightly stale | |
1373 | * stats are acceptable. | |
1374 | */ | |
8ceee660 BH |
1375 | if (!spin_trylock(&efx->stats_lock)) |
1376 | return stats; | |
8c8661e4 | 1377 | if (efx->stats_enabled) { |
177dfcd8 | 1378 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1379 | falcon_update_nic_stats(efx); |
1380 | } | |
1381 | spin_unlock(&efx->stats_lock); | |
1382 | ||
1383 | stats->rx_packets = mac_stats->rx_packets; | |
1384 | stats->tx_packets = mac_stats->tx_packets; | |
1385 | stats->rx_bytes = mac_stats->rx_bytes; | |
1386 | stats->tx_bytes = mac_stats->tx_bytes; | |
1387 | stats->multicast = mac_stats->rx_multicast; | |
1388 | stats->collisions = mac_stats->tx_collision; | |
1389 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1390 | mac_stats->rx_length_error); | |
1391 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1392 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1393 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1394 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1395 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1396 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1397 | ||
1398 | stats->rx_errors = (stats->rx_length_errors + | |
1399 | stats->rx_over_errors + | |
1400 | stats->rx_crc_errors + | |
1401 | stats->rx_frame_errors + | |
1402 | stats->rx_fifo_errors + | |
1403 | stats->rx_missed_errors + | |
1404 | mac_stats->rx_symbol_error); | |
1405 | stats->tx_errors = (stats->tx_window_errors + | |
1406 | mac_stats->tx_bad); | |
1407 | ||
1408 | return stats; | |
1409 | } | |
1410 | ||
1411 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1412 | static void efx_watchdog(struct net_device *net_dev) | |
1413 | { | |
767e468c | 1414 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1415 | |
739bb23d BH |
1416 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1417 | " resetting channels\n", | |
1418 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1419 | |
739bb23d | 1420 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1421 | } |
1422 | ||
1423 | ||
1424 | /* Context: process, rtnl_lock() held. */ | |
1425 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1426 | { | |
767e468c | 1427 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1428 | int rc = 0; |
1429 | ||
1430 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1431 | ||
1432 | if (new_mtu > EFX_MAX_MTU) | |
1433 | return -EINVAL; | |
1434 | ||
1435 | efx_stop_all(efx); | |
1436 | ||
1437 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1438 | ||
1439 | efx_fini_channels(efx); | |
1440 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1441 | efx_init_channels(efx); |
8ceee660 BH |
1442 | |
1443 | efx_start_all(efx); | |
1444 | return rc; | |
8ceee660 BH |
1445 | } |
1446 | ||
1447 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1448 | { | |
767e468c | 1449 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1450 | struct sockaddr *addr = data; |
1451 | char *new_addr = addr->sa_data; | |
1452 | ||
1453 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1454 | ||
1455 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1456 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1457 | new_addr); | |
8ceee660 BH |
1458 | return -EINVAL; |
1459 | } | |
1460 | ||
1461 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1462 | ||
1463 | /* Reconfigure the MAC */ | |
1464 | efx_reconfigure_port(efx); | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
a816f75a | 1469 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1470 | static void efx_set_multicast_list(struct net_device *net_dev) |
1471 | { | |
767e468c | 1472 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1473 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1474 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1475 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1476 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1477 | u32 crc; |
1478 | int bit; | |
1479 | int i; | |
1480 | ||
a816f75a | 1481 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1482 | |
1483 | /* Build multicast hash table */ | |
1484 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1485 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1486 | } else { | |
1487 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1488 | for (i = 0; i < net_dev->mc_count; i++) { | |
1489 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1490 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1491 | set_bit_le(bit, mc_hash->byte); | |
1492 | mc_list = mc_list->next; | |
1493 | } | |
1494 | } | |
1495 | ||
a816f75a BH |
1496 | if (!efx->port_enabled) |
1497 | /* Delay pushing settings until efx_start_port() */ | |
1498 | return; | |
1499 | ||
1500 | if (changed) | |
766ca0fa | 1501 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1502 | |
8ceee660 BH |
1503 | /* Create and activate new global multicast hash table */ |
1504 | falcon_set_multicast_hash(efx); | |
1505 | } | |
1506 | ||
c3ecb9f3 SH |
1507 | static const struct net_device_ops efx_netdev_ops = { |
1508 | .ndo_open = efx_net_open, | |
1509 | .ndo_stop = efx_net_stop, | |
1510 | .ndo_get_stats = efx_net_stats, | |
1511 | .ndo_tx_timeout = efx_watchdog, | |
1512 | .ndo_start_xmit = efx_hard_start_xmit, | |
1513 | .ndo_validate_addr = eth_validate_addr, | |
1514 | .ndo_do_ioctl = efx_ioctl, | |
1515 | .ndo_change_mtu = efx_change_mtu, | |
1516 | .ndo_set_mac_address = efx_set_mac_address, | |
1517 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1518 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1519 | .ndo_poll_controller = efx_netpoll, | |
1520 | #endif | |
1521 | }; | |
1522 | ||
7dde596e BH |
1523 | static void efx_update_name(struct efx_nic *efx) |
1524 | { | |
1525 | strcpy(efx->name, efx->net_dev->name); | |
1526 | efx_mtd_rename(efx); | |
1527 | efx_set_channel_names(efx); | |
1528 | } | |
1529 | ||
8ceee660 BH |
1530 | static int efx_netdev_event(struct notifier_block *this, |
1531 | unsigned long event, void *ptr) | |
1532 | { | |
d3208b5e | 1533 | struct net_device *net_dev = ptr; |
8ceee660 | 1534 | |
7dde596e BH |
1535 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1536 | event == NETDEV_CHANGENAME) | |
1537 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1538 | |
1539 | return NOTIFY_DONE; | |
1540 | } | |
1541 | ||
1542 | static struct notifier_block efx_netdev_notifier = { | |
1543 | .notifier_call = efx_netdev_event, | |
1544 | }; | |
1545 | ||
06d5e193 BH |
1546 | static ssize_t |
1547 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1548 | { | |
1549 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1550 | return sprintf(buf, "%d\n", efx->phy_type); | |
1551 | } | |
1552 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1553 | ||
8ceee660 BH |
1554 | static int efx_register_netdev(struct efx_nic *efx) |
1555 | { | |
1556 | struct net_device *net_dev = efx->net_dev; | |
1557 | int rc; | |
1558 | ||
1559 | net_dev->watchdog_timeo = 5 * HZ; | |
1560 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1561 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1562 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1563 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1564 | ||
1565 | /* Always start with carrier off; PHY events will detect the link */ | |
1566 | netif_carrier_off(efx->net_dev); | |
1567 | ||
1568 | /* Clear MAC statistics */ | |
177dfcd8 | 1569 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1570 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1571 | ||
1572 | rc = register_netdev(net_dev); | |
1573 | if (rc) { | |
1574 | EFX_ERR(efx, "could not register net dev\n"); | |
1575 | return rc; | |
1576 | } | |
7dde596e BH |
1577 | |
1578 | rtnl_lock(); | |
1579 | efx_update_name(efx); | |
1580 | rtnl_unlock(); | |
8ceee660 | 1581 | |
06d5e193 BH |
1582 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1583 | if (rc) { | |
1584 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1585 | goto fail_registered; | |
1586 | } | |
1587 | ||
8ceee660 | 1588 | return 0; |
06d5e193 BH |
1589 | |
1590 | fail_registered: | |
1591 | unregister_netdev(net_dev); | |
1592 | return rc; | |
8ceee660 BH |
1593 | } |
1594 | ||
1595 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1596 | { | |
1597 | struct efx_tx_queue *tx_queue; | |
1598 | ||
1599 | if (!efx->net_dev) | |
1600 | return; | |
1601 | ||
767e468c | 1602 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1603 | |
1604 | /* Free up any skbs still remaining. This has to happen before | |
1605 | * we try to unregister the netdev as running their destructors | |
1606 | * may be needed to get the device ref. count to 0. */ | |
1607 | efx_for_each_tx_queue(tx_queue, efx) | |
1608 | efx_release_tx_buffers(tx_queue); | |
1609 | ||
55668611 | 1610 | if (efx_dev_registered(efx)) { |
8ceee660 | 1611 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1612 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1613 | unregister_netdev(efx->net_dev); |
1614 | } | |
1615 | } | |
1616 | ||
1617 | /************************************************************************** | |
1618 | * | |
1619 | * Device reset and suspend | |
1620 | * | |
1621 | **************************************************************************/ | |
1622 | ||
2467ca46 BH |
1623 | /* Tears down the entire software state and most of the hardware state |
1624 | * before reset. */ | |
8c8661e4 | 1625 | void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
8ceee660 | 1626 | { |
8ceee660 BH |
1627 | EFX_ASSERT_RESET_SERIALISED(efx); |
1628 | ||
2467ca46 BH |
1629 | /* The net_dev->get_stats handler is quite slow, and will fail |
1630 | * if a fetch is pending over reset. Serialise against it. */ | |
1631 | spin_lock(&efx->stats_lock); | |
8c8661e4 | 1632 | efx->stats_enabled = false; |
2467ca46 BH |
1633 | spin_unlock(&efx->stats_lock); |
1634 | ||
1635 | efx_stop_all(efx); | |
1636 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1637 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1638 | |
177dfcd8 | 1639 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1640 | |
1641 | efx_fini_channels(efx); | |
8ceee660 BH |
1642 | } |
1643 | ||
2467ca46 BH |
1644 | /* This function will always ensure that the locks acquired in |
1645 | * efx_reset_down() are released. A failure return code indicates | |
1646 | * that we were unable to reinitialise the hardware, and the | |
1647 | * driver should be disabled. If ok is false, then the rx and tx | |
1648 | * engines are not restarted, pending a RESET_DISABLE. */ | |
8c8661e4 | 1649 | int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok) |
8ceee660 BH |
1650 | { |
1651 | int rc; | |
1652 | ||
2467ca46 | 1653 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1654 | |
2467ca46 | 1655 | rc = falcon_init_nic(efx); |
8ceee660 | 1656 | if (rc) { |
2467ca46 BH |
1657 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1658 | ok = false; | |
8ceee660 BH |
1659 | } |
1660 | ||
2467ca46 BH |
1661 | if (ok) { |
1662 | efx_init_channels(efx); | |
8ceee660 | 1663 | |
177dfcd8 | 1664 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1665 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1666 | } | |
1667 | ||
f4150724 | 1668 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1669 | mutex_unlock(&efx->mac_lock); |
1670 | ||
8c8661e4 | 1671 | if (ok) { |
2467ca46 | 1672 | efx_start_all(efx); |
8c8661e4 BH |
1673 | efx->stats_enabled = true; |
1674 | } | |
8ceee660 BH |
1675 | return rc; |
1676 | } | |
1677 | ||
1678 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1679 | * Note that the reset may fail, in which case the card will be left | |
1680 | * in a most-probably-unusable state. | |
1681 | * | |
1682 | * This function will sleep. You cannot reset from within an atomic | |
1683 | * state; use efx_schedule_reset() instead. | |
1684 | * | |
1685 | * Grabs the rtnl_lock. | |
1686 | */ | |
1687 | static int efx_reset(struct efx_nic *efx) | |
1688 | { | |
1689 | struct ethtool_cmd ecmd; | |
1690 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1691 | int rc = 0; |
8ceee660 BH |
1692 | |
1693 | /* Serialise with kernel interfaces */ | |
1694 | rtnl_lock(); | |
1695 | ||
1696 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1697 | * flag set so that efx_pci_probe_main will be retried */ | |
1698 | if (efx->state != STATE_RUNNING) { | |
1699 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1700 | goto out_unlock; |
8ceee660 BH |
1701 | } |
1702 | ||
8ceee660 BH |
1703 | EFX_INFO(efx, "resetting (%d)\n", method); |
1704 | ||
2467ca46 | 1705 | efx_reset_down(efx, &ecmd); |
8ceee660 BH |
1706 | |
1707 | rc = falcon_reset_hw(efx, method); | |
1708 | if (rc) { | |
1709 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1710 | goto out_disable; |
8ceee660 BH |
1711 | } |
1712 | ||
1713 | /* Allow resets to be rescheduled. */ | |
1714 | efx->reset_pending = RESET_TYPE_NONE; | |
1715 | ||
1716 | /* Reinitialise bus-mastering, which may have been turned off before | |
1717 | * the reset was scheduled. This is still appropriate, even in the | |
1718 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1719 | * can respond to requests. */ | |
1720 | pci_set_master(efx->pci_dev); | |
1721 | ||
8ceee660 BH |
1722 | /* Leave device stopped if necessary */ |
1723 | if (method == RESET_TYPE_DISABLE) { | |
f4bd954e | 1724 | efx_reset_up(efx, &ecmd, false); |
8ceee660 | 1725 | rc = -EIO; |
f4bd954e BH |
1726 | } else { |
1727 | rc = efx_reset_up(efx, &ecmd, true); | |
8ceee660 BH |
1728 | } |
1729 | ||
f4bd954e BH |
1730 | out_disable: |
1731 | if (rc) { | |
1732 | EFX_ERR(efx, "has been disabled\n"); | |
1733 | efx->state = STATE_DISABLED; | |
1734 | dev_close(efx->net_dev); | |
1735 | } else { | |
1736 | EFX_LOG(efx, "reset complete\n"); | |
1737 | } | |
8ceee660 | 1738 | |
f4bd954e | 1739 | out_unlock: |
8ceee660 | 1740 | rtnl_unlock(); |
8ceee660 BH |
1741 | return rc; |
1742 | } | |
1743 | ||
1744 | /* The worker thread exists so that code that cannot sleep can | |
1745 | * schedule a reset for later. | |
1746 | */ | |
1747 | static void efx_reset_work(struct work_struct *data) | |
1748 | { | |
1749 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1750 | ||
1751 | efx_reset(nic); | |
1752 | } | |
1753 | ||
1754 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1755 | { | |
1756 | enum reset_type method; | |
1757 | ||
1758 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1759 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1760 | return; | |
1761 | } | |
1762 | ||
1763 | switch (type) { | |
1764 | case RESET_TYPE_INVISIBLE: | |
1765 | case RESET_TYPE_ALL: | |
1766 | case RESET_TYPE_WORLD: | |
1767 | case RESET_TYPE_DISABLE: | |
1768 | method = type; | |
1769 | break; | |
1770 | case RESET_TYPE_RX_RECOVERY: | |
1771 | case RESET_TYPE_RX_DESC_FETCH: | |
1772 | case RESET_TYPE_TX_DESC_FETCH: | |
1773 | case RESET_TYPE_TX_SKIP: | |
1774 | method = RESET_TYPE_INVISIBLE; | |
1775 | break; | |
1776 | default: | |
1777 | method = RESET_TYPE_ALL; | |
1778 | break; | |
1779 | } | |
1780 | ||
1781 | if (method != type) | |
1782 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1783 | else | |
1784 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1785 | ||
1786 | efx->reset_pending = method; | |
1787 | ||
1ab00629 | 1788 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1789 | } |
1790 | ||
1791 | /************************************************************************** | |
1792 | * | |
1793 | * List of NICs we support | |
1794 | * | |
1795 | **************************************************************************/ | |
1796 | ||
1797 | /* PCI device ID table */ | |
1798 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1799 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1800 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1801 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1802 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1803 | {0} /* end of list */ | |
1804 | }; | |
1805 | ||
1806 | /************************************************************************** | |
1807 | * | |
1808 | * Dummy PHY/MAC/Board operations | |
1809 | * | |
01aad7b6 | 1810 | * Can be used for some unimplemented operations |
8ceee660 BH |
1811 | * Needed so all function pointers are valid and do not have to be tested |
1812 | * before use | |
1813 | * | |
1814 | **************************************************************************/ | |
1815 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1816 | { | |
1817 | return 0; | |
1818 | } | |
1819 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1820 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 | 1821 | |
177dfcd8 BH |
1822 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1823 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa BH |
1824 | .poll = efx_port_dummy_op_void, |
1825 | .irq = efx_port_dummy_op_void, | |
177dfcd8 BH |
1826 | }; |
1827 | ||
8ceee660 BH |
1828 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1829 | .init = efx_port_dummy_op_int, | |
1830 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1831 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1832 | .fini = efx_port_dummy_op_void, |
1833 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1834 | }; |
1835 | ||
8ceee660 | 1836 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 BH |
1837 | .init = efx_port_dummy_op_int, |
1838 | .init_leds = efx_port_dummy_op_int, | |
1839 | .set_fault_led = efx_port_dummy_op_blink, | |
a17102b1 | 1840 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1841 | .blink = efx_port_dummy_op_blink, |
1842 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1843 | }; |
1844 | ||
1845 | /************************************************************************** | |
1846 | * | |
1847 | * Data housekeeping | |
1848 | * | |
1849 | **************************************************************************/ | |
1850 | ||
1851 | /* This zeroes out and then fills in the invariants in a struct | |
1852 | * efx_nic (including all sub-structures). | |
1853 | */ | |
1854 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1855 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1856 | { | |
1857 | struct efx_channel *channel; | |
1858 | struct efx_tx_queue *tx_queue; | |
1859 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1860 | int i; |
8ceee660 BH |
1861 | |
1862 | /* Initialise common structures */ | |
1863 | memset(efx, 0, sizeof(*efx)); | |
1864 | spin_lock_init(&efx->biu_lock); | |
1865 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1866 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1867 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1868 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1869 | efx->pci_dev = pci_dev; | |
1870 | efx->state = STATE_INIT; | |
1871 | efx->reset_pending = RESET_TYPE_NONE; | |
1872 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1873 | efx->board_info = efx_dummy_board_info; | |
1874 | ||
1875 | efx->net_dev = net_dev; | |
dc8cfa55 | 1876 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1877 | spin_lock_init(&efx->netif_stop_lock); |
1878 | spin_lock_init(&efx->stats_lock); | |
1879 | mutex_init(&efx->mac_lock); | |
177dfcd8 | 1880 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 BH |
1881 | efx->phy_op = &efx_dummy_phy_operations; |
1882 | efx->mii.dev = net_dev; | |
766ca0fa BH |
1883 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1884 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1885 | atomic_set(&efx->netif_stop_count, 1); |
1886 | ||
1887 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1888 | channel = &efx->channel[i]; | |
1889 | channel->efx = efx; | |
1890 | channel->channel = i; | |
dc8cfa55 | 1891 | channel->work_pending = false; |
8ceee660 | 1892 | } |
60ac1065 | 1893 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1894 | tx_queue = &efx->tx_queue[i]; |
1895 | tx_queue->efx = efx; | |
1896 | tx_queue->queue = i; | |
1897 | tx_queue->buffer = NULL; | |
1898 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1899 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1900 | } |
1901 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1902 | rx_queue = &efx->rx_queue[i]; | |
1903 | rx_queue->efx = efx; | |
1904 | rx_queue->queue = i; | |
1905 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1906 | rx_queue->buffer = NULL; | |
1907 | spin_lock_init(&rx_queue->add_lock); | |
1908 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1909 | } | |
1910 | ||
1911 | efx->type = type; | |
1912 | ||
1913 | /* Sanity-check NIC type */ | |
1914 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1915 | (efx->type->txd_ring_mask + 1)); | |
1916 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1917 | (efx->type->rxd_ring_mask + 1)); | |
1918 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1919 | (efx->type->evq_size - 1)); | |
1920 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1921 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1922 | (efx->type->txd_ring_mask + 1 + | |
1923 | efx->type->rxd_ring_mask + 1)); | |
1924 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1925 | ||
1926 | /* Higher numbered interrupt modes are less capable! */ | |
1927 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1928 | interrupt_mode); | |
1929 | ||
6977dc63 BH |
1930 | /* Would be good to use the net_dev name, but we're too early */ |
1931 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
1932 | pci_name(pci_dev)); | |
1933 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
1934 | if (!efx->workqueue) |
1935 | return -ENOMEM; | |
8d9853d9 | 1936 | |
8ceee660 | 1937 | return 0; |
8ceee660 BH |
1938 | } |
1939 | ||
1940 | static void efx_fini_struct(struct efx_nic *efx) | |
1941 | { | |
1942 | if (efx->workqueue) { | |
1943 | destroy_workqueue(efx->workqueue); | |
1944 | efx->workqueue = NULL; | |
1945 | } | |
1946 | } | |
1947 | ||
1948 | /************************************************************************** | |
1949 | * | |
1950 | * PCI interface | |
1951 | * | |
1952 | **************************************************************************/ | |
1953 | ||
1954 | /* Main body of final NIC shutdown code | |
1955 | * This is called only at module unload (or hotplug removal). | |
1956 | */ | |
1957 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1958 | { | |
1959 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1960 | ||
1961 | /* Skip everything if we never obtained a valid membase */ | |
1962 | if (!efx->membase) | |
1963 | return; | |
1964 | ||
1965 | efx_fini_channels(efx); | |
1966 | efx_fini_port(efx); | |
1967 | ||
1968 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1969 | efx->board_info.fini(efx); |
8ceee660 BH |
1970 | falcon_fini_interrupt(efx); |
1971 | ||
1972 | efx_fini_napi(efx); | |
1973 | efx_remove_all(efx); | |
1974 | } | |
1975 | ||
1976 | /* Final NIC shutdown | |
1977 | * This is called only at module unload (or hotplug removal). | |
1978 | */ | |
1979 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1980 | { | |
1981 | struct efx_nic *efx; | |
1982 | ||
1983 | efx = pci_get_drvdata(pci_dev); | |
1984 | if (!efx) | |
1985 | return; | |
1986 | ||
1987 | /* Mark the NIC as fini, then stop the interface */ | |
1988 | rtnl_lock(); | |
1989 | efx->state = STATE_FINI; | |
1990 | dev_close(efx->net_dev); | |
1991 | ||
1992 | /* Allow any queued efx_resets() to complete */ | |
1993 | rtnl_unlock(); | |
1994 | ||
1995 | if (efx->membase == NULL) | |
1996 | goto out; | |
1997 | ||
1998 | efx_unregister_netdev(efx); | |
1999 | ||
7dde596e BH |
2000 | efx_mtd_remove(efx); |
2001 | ||
8ceee660 BH |
2002 | /* Wait for any scheduled resets to complete. No more will be |
2003 | * scheduled from this point because efx_stop_all() has been | |
2004 | * called, we are no longer registered with driverlink, and | |
2005 | * the net_device's have been removed. */ | |
1ab00629 | 2006 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2007 | |
2008 | efx_pci_remove_main(efx); | |
2009 | ||
2010 | out: | |
2011 | efx_fini_io(efx); | |
2012 | EFX_LOG(efx, "shutdown successful\n"); | |
2013 | ||
2014 | pci_set_drvdata(pci_dev, NULL); | |
2015 | efx_fini_struct(efx); | |
2016 | free_netdev(efx->net_dev); | |
2017 | }; | |
2018 | ||
2019 | /* Main body of NIC initialisation | |
2020 | * This is called at module load (or hotplug insertion, theoretically). | |
2021 | */ | |
2022 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2023 | { | |
2024 | int rc; | |
2025 | ||
2026 | /* Do start-of-day initialisation */ | |
2027 | rc = efx_probe_all(efx); | |
2028 | if (rc) | |
2029 | goto fail1; | |
2030 | ||
2031 | rc = efx_init_napi(efx); | |
2032 | if (rc) | |
2033 | goto fail2; | |
2034 | ||
2035 | /* Initialise the board */ | |
2036 | rc = efx->board_info.init(efx); | |
2037 | if (rc) { | |
2038 | EFX_ERR(efx, "failed to initialise board\n"); | |
2039 | goto fail3; | |
2040 | } | |
2041 | ||
2042 | rc = falcon_init_nic(efx); | |
2043 | if (rc) { | |
2044 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
2045 | goto fail4; | |
2046 | } | |
2047 | ||
2048 | rc = efx_init_port(efx); | |
2049 | if (rc) { | |
2050 | EFX_ERR(efx, "failed to initialise port\n"); | |
2051 | goto fail5; | |
2052 | } | |
2053 | ||
bc3c90a2 | 2054 | efx_init_channels(efx); |
8ceee660 BH |
2055 | |
2056 | rc = falcon_init_interrupt(efx); | |
2057 | if (rc) | |
bc3c90a2 | 2058 | goto fail6; |
8ceee660 BH |
2059 | |
2060 | return 0; | |
2061 | ||
8ceee660 | 2062 | fail6: |
bc3c90a2 | 2063 | efx_fini_channels(efx); |
8ceee660 BH |
2064 | efx_fini_port(efx); |
2065 | fail5: | |
2066 | fail4: | |
a17102b1 | 2067 | efx->board_info.fini(efx); |
8ceee660 BH |
2068 | fail3: |
2069 | efx_fini_napi(efx); | |
2070 | fail2: | |
2071 | efx_remove_all(efx); | |
2072 | fail1: | |
2073 | return rc; | |
2074 | } | |
2075 | ||
2076 | /* NIC initialisation | |
2077 | * | |
2078 | * This is called at module load (or hotplug insertion, | |
2079 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2080 | * sets up and registers the network devices with the kernel and hooks | |
2081 | * the interrupt service routine. It does not prepare the device for | |
2082 | * transmission; this is left to the first time one of the network | |
2083 | * interfaces is brought up (i.e. efx_net_open). | |
2084 | */ | |
2085 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2086 | const struct pci_device_id *entry) | |
2087 | { | |
2088 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2089 | struct net_device *net_dev; | |
2090 | struct efx_nic *efx; | |
2091 | int i, rc; | |
2092 | ||
2093 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2094 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2095 | if (!net_dev) | |
2096 | return -ENOMEM; | |
b9b39b62 BH |
2097 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2098 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2099 | if (lro) |
2100 | net_dev->features |= NETIF_F_LRO; | |
28506563 BH |
2101 | /* Mask for features that also apply to VLAN devices */ |
2102 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2103 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2104 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2105 | pci_set_drvdata(pci_dev, efx); |
2106 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2107 | if (rc) | |
2108 | goto fail1; | |
2109 | ||
2110 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2111 | ||
2112 | /* Set up basic I/O (BAR mappings etc) */ | |
2113 | rc = efx_init_io(efx); | |
2114 | if (rc) | |
2115 | goto fail2; | |
2116 | ||
2117 | /* No serialisation is required with the reset path because | |
2118 | * we're in STATE_INIT. */ | |
2119 | for (i = 0; i < 5; i++) { | |
2120 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2121 | |
2122 | /* Serialise against efx_reset(). No more resets will be | |
2123 | * scheduled since efx_stop_all() has been called, and we | |
2124 | * have not and never have been registered with either | |
2125 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2126 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2127 | |
fa402b2e SH |
2128 | if (rc == 0) { |
2129 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2130 | /* If there was a scheduled reset during | |
2131 | * probe, the NIC is probably hosed anyway */ | |
2132 | efx_pci_remove_main(efx); | |
2133 | rc = -EIO; | |
2134 | } else { | |
2135 | break; | |
2136 | } | |
2137 | } | |
2138 | ||
8ceee660 BH |
2139 | /* Retry if a recoverably reset event has been scheduled */ |
2140 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2141 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2142 | goto fail3; | |
2143 | ||
2144 | efx->reset_pending = RESET_TYPE_NONE; | |
2145 | } | |
2146 | ||
2147 | if (rc) { | |
2148 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2149 | goto fail4; | |
2150 | } | |
2151 | ||
2152 | /* Switch to the running state before we expose the device to | |
2153 | * the OS. This is to ensure that the initial gathering of | |
2154 | * MAC stats succeeds. */ | |
8ceee660 | 2155 | efx->state = STATE_RUNNING; |
7dde596e BH |
2156 | |
2157 | efx_mtd_probe(efx); /* allowed to fail */ | |
8ceee660 BH |
2158 | |
2159 | rc = efx_register_netdev(efx); | |
2160 | if (rc) | |
2161 | goto fail5; | |
2162 | ||
2163 | EFX_LOG(efx, "initialisation successful\n"); | |
8ceee660 BH |
2164 | return 0; |
2165 | ||
2166 | fail5: | |
2167 | efx_pci_remove_main(efx); | |
2168 | fail4: | |
2169 | fail3: | |
2170 | efx_fini_io(efx); | |
2171 | fail2: | |
2172 | efx_fini_struct(efx); | |
2173 | fail1: | |
2174 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2175 | free_netdev(net_dev); | |
2176 | return rc; | |
2177 | } | |
2178 | ||
2179 | static struct pci_driver efx_pci_driver = { | |
2180 | .name = EFX_DRIVER_NAME, | |
2181 | .id_table = efx_pci_table, | |
2182 | .probe = efx_pci_probe, | |
2183 | .remove = efx_pci_remove, | |
2184 | }; | |
2185 | ||
2186 | /************************************************************************** | |
2187 | * | |
2188 | * Kernel module interface | |
2189 | * | |
2190 | *************************************************************************/ | |
2191 | ||
2192 | module_param(interrupt_mode, uint, 0444); | |
2193 | MODULE_PARM_DESC(interrupt_mode, | |
2194 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2195 | ||
2196 | static int __init efx_init_module(void) | |
2197 | { | |
2198 | int rc; | |
2199 | ||
2200 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2201 | ||
2202 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2203 | if (rc) | |
2204 | goto err_notifier; | |
2205 | ||
2206 | refill_workqueue = create_workqueue("sfc_refill"); | |
2207 | if (!refill_workqueue) { | |
2208 | rc = -ENOMEM; | |
2209 | goto err_refill; | |
2210 | } | |
1ab00629 SH |
2211 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2212 | if (!reset_workqueue) { | |
2213 | rc = -ENOMEM; | |
2214 | goto err_reset; | |
2215 | } | |
8ceee660 BH |
2216 | |
2217 | rc = pci_register_driver(&efx_pci_driver); | |
2218 | if (rc < 0) | |
2219 | goto err_pci; | |
2220 | ||
2221 | return 0; | |
2222 | ||
2223 | err_pci: | |
1ab00629 SH |
2224 | destroy_workqueue(reset_workqueue); |
2225 | err_reset: | |
8ceee660 BH |
2226 | destroy_workqueue(refill_workqueue); |
2227 | err_refill: | |
2228 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2229 | err_notifier: | |
2230 | return rc; | |
2231 | } | |
2232 | ||
2233 | static void __exit efx_exit_module(void) | |
2234 | { | |
2235 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2236 | ||
2237 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2238 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2239 | destroy_workqueue(refill_workqueue); |
2240 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2241 | ||
2242 | } | |
2243 | ||
2244 | module_init(efx_init_module); | |
2245 | module_exit(efx_exit_module); | |
2246 | ||
2247 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2248 | "Solarflare Communications"); | |
2249 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2250 | MODULE_LICENSE("GPL"); | |
2251 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |