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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 BH |
23 | #include "net_driver.h" |
24 | #include "gmii.h" | |
25 | #include "ethtool.h" | |
26 | #include "tx.h" | |
27 | #include "rx.h" | |
28 | #include "efx.h" | |
29 | #include "mdio_10g.h" | |
30 | #include "falcon.h" | |
8ceee660 BH |
31 | #include "mac.h" |
32 | ||
33 | #define EFX_MAX_MTU (9 * 1024) | |
34 | ||
35 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
36 | * a work item is pushed onto this work queue to retry the allocation later, | |
37 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
38 | * workqueue, there is nothing to be gained in making it per NIC | |
39 | */ | |
40 | static struct workqueue_struct *refill_workqueue; | |
41 | ||
1ab00629 SH |
42 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
43 | * queued onto this work queue. This is not a per-nic work queue, because | |
44 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
45 | */ | |
46 | static struct workqueue_struct *reset_workqueue; | |
47 | ||
8ceee660 BH |
48 | /************************************************************************** |
49 | * | |
50 | * Configurable values | |
51 | * | |
52 | *************************************************************************/ | |
53 | ||
54 | /* | |
55 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
56 | * | |
57 | * This sets the default for new devices. It can be controlled later | |
58 | * using ethtool. | |
59 | */ | |
dc8cfa55 | 60 | static int lro = true; |
8ceee660 BH |
61 | module_param(lro, int, 0644); |
62 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
63 | ||
64 | /* | |
65 | * Use separate channels for TX and RX events | |
66 | * | |
67 | * Set this to 1 to use separate channels for TX and RX. It allows us to | |
68 | * apply a higher level of interrupt moderation to TX events. | |
69 | * | |
70 | * This is forced to 0 for MSI interrupt mode as the interrupt vector | |
71 | * is not written | |
72 | */ | |
dc8cfa55 | 73 | static unsigned int separate_tx_and_rx_channels = true; |
8ceee660 BH |
74 | |
75 | /* This is the weight assigned to each of the (per-channel) virtual | |
76 | * NAPI devices. | |
77 | */ | |
78 | static int napi_weight = 64; | |
79 | ||
80 | /* This is the time (in jiffies) between invocations of the hardware | |
81 | * monitor, which checks for known hardware bugs and resets the | |
82 | * hardware and driver as necessary. | |
83 | */ | |
84 | unsigned int efx_monitor_interval = 1 * HZ; | |
85 | ||
8ceee660 BH |
86 | /* This controls whether or not the driver will initialise devices |
87 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
88 | * such devices will be initialised with a random locally-generated | |
89 | * MAC address. This allows for loading the sfc_mtd driver to | |
90 | * reprogram the flash, even if the flash contents (including the MAC | |
91 | * address) have previously been erased. | |
92 | */ | |
93 | static unsigned int allow_bad_hwaddr; | |
94 | ||
95 | /* Initial interrupt moderation settings. They can be modified after | |
96 | * module load with ethtool. | |
97 | * | |
98 | * The default for RX should strike a balance between increasing the | |
99 | * round-trip latency and reducing overhead. | |
100 | */ | |
101 | static unsigned int rx_irq_mod_usec = 60; | |
102 | ||
103 | /* Initial interrupt moderation settings. They can be modified after | |
104 | * module load with ethtool. | |
105 | * | |
106 | * This default is chosen to ensure that a 10G link does not go idle | |
107 | * while a TX queue is stopped after it has become full. A queue is | |
108 | * restarted when it drops below half full. The time this takes (assuming | |
109 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
110 | * 512 / 3 * 1.2 = 205 usec. | |
111 | */ | |
112 | static unsigned int tx_irq_mod_usec = 150; | |
113 | ||
114 | /* This is the first interrupt mode to try out of: | |
115 | * 0 => MSI-X | |
116 | * 1 => MSI | |
117 | * 2 => legacy | |
118 | */ | |
119 | static unsigned int interrupt_mode; | |
120 | ||
121 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
122 | * i.e. the number of CPUs among which we may distribute simultaneous | |
123 | * interrupt handling. | |
124 | * | |
125 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
126 | * The default (0) means to assign an interrupt to each package (level II cache) | |
127 | */ | |
128 | static unsigned int rss_cpus; | |
129 | module_param(rss_cpus, uint, 0444); | |
130 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
131 | ||
84ae48fe BH |
132 | static int phy_flash_cfg; |
133 | module_param(phy_flash_cfg, int, 0644); | |
134 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
135 | ||
8ceee660 BH |
136 | /************************************************************************** |
137 | * | |
138 | * Utility functions and prototypes | |
139 | * | |
140 | *************************************************************************/ | |
141 | static void efx_remove_channel(struct efx_channel *channel); | |
142 | static void efx_remove_port(struct efx_nic *efx); | |
143 | static void efx_fini_napi(struct efx_nic *efx); | |
144 | static void efx_fini_channels(struct efx_nic *efx); | |
145 | ||
146 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
147 | do { \ | |
3c78708f | 148 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
149 | ASSERT_RTNL(); \ |
150 | } while (0) | |
151 | ||
152 | /************************************************************************** | |
153 | * | |
154 | * Event queue processing | |
155 | * | |
156 | *************************************************************************/ | |
157 | ||
158 | /* Process channel's event queue | |
159 | * | |
160 | * This function is responsible for processing the event queue of a | |
161 | * single channel. The caller must guarantee that this function will | |
162 | * never be concurrently called more than once on the same channel, | |
163 | * though different channels may be being processed concurrently. | |
164 | */ | |
4d566063 | 165 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 166 | { |
42cbe2d7 BH |
167 | struct efx_nic *efx = channel->efx; |
168 | int rx_packets; | |
8ceee660 | 169 | |
42cbe2d7 | 170 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 171 | !channel->enabled)) |
42cbe2d7 | 172 | return 0; |
8ceee660 | 173 | |
42cbe2d7 BH |
174 | rx_packets = falcon_process_eventq(channel, rx_quota); |
175 | if (rx_packets == 0) | |
176 | return 0; | |
8ceee660 BH |
177 | |
178 | /* Deliver last RX packet. */ | |
179 | if (channel->rx_pkt) { | |
180 | __efx_rx_packet(channel, channel->rx_pkt, | |
181 | channel->rx_pkt_csummed); | |
182 | channel->rx_pkt = NULL; | |
183 | } | |
184 | ||
185 | efx_flush_lro(channel); | |
186 | efx_rx_strategy(channel); | |
187 | ||
42cbe2d7 | 188 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 189 | |
42cbe2d7 | 190 | return rx_packets; |
8ceee660 BH |
191 | } |
192 | ||
193 | /* Mark channel as finished processing | |
194 | * | |
195 | * Note that since we will not receive further interrupts for this | |
196 | * channel before we finish processing and call the eventq_read_ack() | |
197 | * method, there is no need to use the interrupt hold-off timers. | |
198 | */ | |
199 | static inline void efx_channel_processed(struct efx_channel *channel) | |
200 | { | |
5b9e207c BH |
201 | /* The interrupt handler for this channel may set work_pending |
202 | * as soon as we acknowledge the events we've seen. Make sure | |
203 | * it's cleared before then. */ | |
dc8cfa55 | 204 | channel->work_pending = false; |
5b9e207c BH |
205 | smp_wmb(); |
206 | ||
8ceee660 BH |
207 | falcon_eventq_read_ack(channel); |
208 | } | |
209 | ||
210 | /* NAPI poll handler | |
211 | * | |
212 | * NAPI guarantees serialisation of polls of the same device, which | |
213 | * provides the guarantee required by efx_process_channel(). | |
214 | */ | |
215 | static int efx_poll(struct napi_struct *napi, int budget) | |
216 | { | |
217 | struct efx_channel *channel = | |
218 | container_of(napi, struct efx_channel, napi_str); | |
219 | struct net_device *napi_dev = channel->napi_dev; | |
8ceee660 BH |
220 | int rx_packets; |
221 | ||
222 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
223 | channel->channel, raw_smp_processor_id()); | |
224 | ||
42cbe2d7 | 225 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
226 | |
227 | if (rx_packets < budget) { | |
228 | /* There is no race here; although napi_disable() will | |
229 | * only wait for netif_rx_complete(), this isn't a problem | |
230 | * since efx_channel_processed() will have no effect if | |
231 | * interrupts have already been disabled. | |
232 | */ | |
233 | netif_rx_complete(napi_dev, napi); | |
234 | efx_channel_processed(channel); | |
235 | } | |
236 | ||
237 | return rx_packets; | |
238 | } | |
239 | ||
240 | /* Process the eventq of the specified channel immediately on this CPU | |
241 | * | |
242 | * Disable hardware generated interrupts, wait for any existing | |
243 | * processing to finish, then directly poll (and ack ) the eventq. | |
244 | * Finally reenable NAPI and interrupts. | |
245 | * | |
246 | * Since we are touching interrupts the caller should hold the suspend lock | |
247 | */ | |
248 | void efx_process_channel_now(struct efx_channel *channel) | |
249 | { | |
250 | struct efx_nic *efx = channel->efx; | |
251 | ||
252 | BUG_ON(!channel->used_flags); | |
253 | BUG_ON(!channel->enabled); | |
254 | ||
255 | /* Disable interrupts and wait for ISRs to complete */ | |
256 | falcon_disable_interrupts(efx); | |
257 | if (efx->legacy_irq) | |
258 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 259 | if (channel->irq) |
8ceee660 BH |
260 | synchronize_irq(channel->irq); |
261 | ||
262 | /* Wait for any NAPI processing to complete */ | |
263 | napi_disable(&channel->napi_str); | |
264 | ||
265 | /* Poll the channel */ | |
91ad757c | 266 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
267 | |
268 | /* Ack the eventq. This may cause an interrupt to be generated | |
269 | * when they are reenabled */ | |
270 | efx_channel_processed(channel); | |
271 | ||
272 | napi_enable(&channel->napi_str); | |
273 | falcon_enable_interrupts(efx); | |
274 | } | |
275 | ||
276 | /* Create event queue | |
277 | * Event queue memory allocations are done only once. If the channel | |
278 | * is reset, the memory buffer will be reused; this guards against | |
279 | * errors during channel reset and also simplifies interrupt handling. | |
280 | */ | |
281 | static int efx_probe_eventq(struct efx_channel *channel) | |
282 | { | |
283 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
284 | ||
285 | return falcon_probe_eventq(channel); | |
286 | } | |
287 | ||
288 | /* Prepare channel's event queue */ | |
bc3c90a2 | 289 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
290 | { |
291 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
292 | ||
293 | channel->eventq_read_ptr = 0; | |
294 | ||
bc3c90a2 | 295 | falcon_init_eventq(channel); |
8ceee660 BH |
296 | } |
297 | ||
298 | static void efx_fini_eventq(struct efx_channel *channel) | |
299 | { | |
300 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
301 | ||
302 | falcon_fini_eventq(channel); | |
303 | } | |
304 | ||
305 | static void efx_remove_eventq(struct efx_channel *channel) | |
306 | { | |
307 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
308 | ||
309 | falcon_remove_eventq(channel); | |
310 | } | |
311 | ||
312 | /************************************************************************** | |
313 | * | |
314 | * Channel handling | |
315 | * | |
316 | *************************************************************************/ | |
317 | ||
8ceee660 BH |
318 | static int efx_probe_channel(struct efx_channel *channel) |
319 | { | |
320 | struct efx_tx_queue *tx_queue; | |
321 | struct efx_rx_queue *rx_queue; | |
322 | int rc; | |
323 | ||
324 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
325 | ||
326 | rc = efx_probe_eventq(channel); | |
327 | if (rc) | |
328 | goto fail1; | |
329 | ||
330 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
331 | rc = efx_probe_tx_queue(tx_queue); | |
332 | if (rc) | |
333 | goto fail2; | |
334 | } | |
335 | ||
336 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
337 | rc = efx_probe_rx_queue(rx_queue); | |
338 | if (rc) | |
339 | goto fail3; | |
340 | } | |
341 | ||
342 | channel->n_rx_frm_trunc = 0; | |
343 | ||
344 | return 0; | |
345 | ||
346 | fail3: | |
347 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
348 | efx_remove_rx_queue(rx_queue); | |
349 | fail2: | |
350 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
351 | efx_remove_tx_queue(tx_queue); | |
352 | fail1: | |
353 | return rc; | |
354 | } | |
355 | ||
356 | ||
357 | /* Channels are shutdown and reinitialised whilst the NIC is running | |
358 | * to propagate configuration changes (mtu, checksum offload), or | |
359 | * to clear hardware error conditions | |
360 | */ | |
bc3c90a2 | 361 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
362 | { |
363 | struct efx_tx_queue *tx_queue; | |
364 | struct efx_rx_queue *rx_queue; | |
365 | struct efx_channel *channel; | |
8ceee660 | 366 | |
f7f13b0b BH |
367 | /* Calculate the rx buffer allocation parameters required to |
368 | * support the current MTU, including padding for header | |
369 | * alignment and overruns. | |
370 | */ | |
371 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
372 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
373 | efx->type->rx_buffer_padding); | |
374 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
375 | |
376 | /* Initialise the channels */ | |
377 | efx_for_each_channel(channel, efx) { | |
378 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
379 | ||
bc3c90a2 | 380 | efx_init_eventq(channel); |
8ceee660 | 381 | |
bc3c90a2 BH |
382 | efx_for_each_channel_tx_queue(tx_queue, channel) |
383 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
384 | |
385 | /* The rx buffer allocation strategy is MTU dependent */ | |
386 | efx_rx_strategy(channel); | |
387 | ||
bc3c90a2 BH |
388 | efx_for_each_channel_rx_queue(rx_queue, channel) |
389 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
390 | |
391 | WARN_ON(channel->rx_pkt != NULL); | |
392 | efx_rx_strategy(channel); | |
393 | } | |
8ceee660 BH |
394 | } |
395 | ||
396 | /* This enables event queue processing and packet transmission. | |
397 | * | |
398 | * Note that this function is not allowed to fail, since that would | |
399 | * introduce too much complexity into the suspend/resume path. | |
400 | */ | |
401 | static void efx_start_channel(struct efx_channel *channel) | |
402 | { | |
403 | struct efx_rx_queue *rx_queue; | |
404 | ||
405 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
406 | ||
407 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
408 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
409 | efx_poll, napi_weight); | |
410 | ||
5b9e207c BH |
411 | /* The interrupt handler for this channel may set work_pending |
412 | * as soon as we enable it. Make sure it's cleared before | |
413 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
414 | channel->work_pending = false; |
415 | channel->enabled = true; | |
5b9e207c | 416 | smp_wmb(); |
8ceee660 BH |
417 | |
418 | napi_enable(&channel->napi_str); | |
419 | ||
420 | /* Load up RX descriptors */ | |
421 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
422 | efx_fast_push_rx_descriptors(rx_queue); | |
423 | } | |
424 | ||
425 | /* This disables event queue processing and packet transmission. | |
426 | * This function does not guarantee that all queue processing | |
427 | * (e.g. RX refill) is complete. | |
428 | */ | |
429 | static void efx_stop_channel(struct efx_channel *channel) | |
430 | { | |
431 | struct efx_rx_queue *rx_queue; | |
432 | ||
433 | if (!channel->enabled) | |
434 | return; | |
435 | ||
436 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
437 | ||
dc8cfa55 | 438 | channel->enabled = false; |
8ceee660 BH |
439 | napi_disable(&channel->napi_str); |
440 | ||
441 | /* Ensure that any worker threads have exited or will be no-ops */ | |
442 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
443 | spin_lock_bh(&rx_queue->add_lock); | |
444 | spin_unlock_bh(&rx_queue->add_lock); | |
445 | } | |
446 | } | |
447 | ||
448 | static void efx_fini_channels(struct efx_nic *efx) | |
449 | { | |
450 | struct efx_channel *channel; | |
451 | struct efx_tx_queue *tx_queue; | |
452 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 453 | int rc; |
8ceee660 BH |
454 | |
455 | EFX_ASSERT_RESET_SERIALISED(efx); | |
456 | BUG_ON(efx->port_enabled); | |
457 | ||
6bc5d3a9 BH |
458 | rc = falcon_flush_queues(efx); |
459 | if (rc) | |
460 | EFX_ERR(efx, "failed to flush queues\n"); | |
461 | else | |
462 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
463 | ||
8ceee660 BH |
464 | efx_for_each_channel(channel, efx) { |
465 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
466 | ||
467 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
468 | efx_fini_rx_queue(rx_queue); | |
469 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
470 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
471 | efx_fini_eventq(channel); |
472 | } | |
473 | } | |
474 | ||
475 | static void efx_remove_channel(struct efx_channel *channel) | |
476 | { | |
477 | struct efx_tx_queue *tx_queue; | |
478 | struct efx_rx_queue *rx_queue; | |
479 | ||
480 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
481 | ||
482 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
483 | efx_remove_rx_queue(rx_queue); | |
484 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
485 | efx_remove_tx_queue(tx_queue); | |
486 | efx_remove_eventq(channel); | |
487 | ||
488 | channel->used_flags = 0; | |
489 | } | |
490 | ||
491 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
492 | { | |
493 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
494 | } | |
495 | ||
496 | /************************************************************************** | |
497 | * | |
498 | * Port handling | |
499 | * | |
500 | **************************************************************************/ | |
501 | ||
502 | /* This ensures that the kernel is kept informed (via | |
503 | * netif_carrier_on/off) of the link status, and also maintains the | |
504 | * link status's stop on the port's TX queue. | |
505 | */ | |
506 | static void efx_link_status_changed(struct efx_nic *efx) | |
507 | { | |
8ceee660 BH |
508 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
509 | * that no events are triggered between unregister_netdev() and the | |
510 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
511 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
512 | if (!netif_running(efx->net_dev)) | |
513 | return; | |
514 | ||
8c8661e4 BH |
515 | if (efx->port_inhibited) { |
516 | netif_carrier_off(efx->net_dev); | |
517 | return; | |
518 | } | |
519 | ||
dc8cfa55 | 520 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
521 | efx->n_link_state_changes++; |
522 | ||
523 | if (efx->link_up) | |
524 | netif_carrier_on(efx->net_dev); | |
525 | else | |
526 | netif_carrier_off(efx->net_dev); | |
527 | } | |
528 | ||
529 | /* Status message for kernel log */ | |
530 | if (efx->link_up) { | |
531 | struct mii_if_info *gmii = &efx->mii; | |
532 | unsigned adv, lpa; | |
533 | /* NONE here means direct XAUI from the controller, with no | |
534 | * MDIO-attached device we can query. */ | |
535 | if (efx->phy_type != PHY_TYPE_NONE) { | |
536 | adv = gmii_advertised(gmii); | |
537 | lpa = gmii_lpa(gmii); | |
538 | } else { | |
539 | lpa = GM_LPA_10000 | LPA_DUPLEX; | |
540 | adv = lpa; | |
541 | } | |
542 | EFX_INFO(efx, "link up at %dMbps %s-duplex " | |
543 | "(adv %04x lpa %04x) (MTU %d)%s\n", | |
544 | (efx->link_options & GM_LPA_10000 ? 10000 : | |
545 | (efx->link_options & GM_LPA_1000 ? 1000 : | |
546 | (efx->link_options & GM_LPA_100 ? 100 : | |
547 | 10))), | |
548 | (efx->link_options & GM_LPA_DUPLEX ? | |
549 | "full" : "half"), | |
550 | adv, lpa, | |
551 | efx->net_dev->mtu, | |
552 | (efx->promiscuous ? " [PROMISC]" : "")); | |
553 | } else { | |
554 | EFX_INFO(efx, "link down\n"); | |
555 | } | |
556 | ||
557 | } | |
558 | ||
559 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
560 | * caller must hold the mac_lock */ | |
8c8661e4 | 561 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
562 | { |
563 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
564 | ||
565 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
566 | raw_smp_processor_id()); | |
567 | ||
a816f75a BH |
568 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
569 | if (efx_dev_registered(efx)) { | |
570 | netif_addr_lock_bh(efx->net_dev); | |
571 | netif_addr_unlock_bh(efx->net_dev); | |
572 | } | |
573 | ||
8ceee660 BH |
574 | falcon_reconfigure_xmac(efx); |
575 | ||
576 | /* Inform kernel of loss/gain of carrier */ | |
577 | efx_link_status_changed(efx); | |
578 | } | |
579 | ||
580 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
581 | * disabled. */ | |
582 | void efx_reconfigure_port(struct efx_nic *efx) | |
583 | { | |
584 | EFX_ASSERT_RESET_SERIALISED(efx); | |
585 | ||
586 | mutex_lock(&efx->mac_lock); | |
587 | __efx_reconfigure_port(efx); | |
588 | mutex_unlock(&efx->mac_lock); | |
589 | } | |
590 | ||
591 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
592 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
593 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
594 | static void efx_reconfigure_work(struct work_struct *data) | |
595 | { | |
596 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
597 | reconfigure_work); | |
598 | ||
599 | mutex_lock(&efx->mac_lock); | |
600 | if (efx->port_enabled) | |
601 | __efx_reconfigure_port(efx); | |
602 | mutex_unlock(&efx->mac_lock); | |
603 | } | |
604 | ||
605 | static int efx_probe_port(struct efx_nic *efx) | |
606 | { | |
607 | int rc; | |
608 | ||
609 | EFX_LOG(efx, "create port\n"); | |
610 | ||
611 | /* Connect up MAC/PHY operations table and read MAC address */ | |
612 | rc = falcon_probe_port(efx); | |
613 | if (rc) | |
614 | goto err; | |
615 | ||
84ae48fe BH |
616 | if (phy_flash_cfg) |
617 | efx->phy_mode = PHY_MODE_SPECIAL; | |
618 | ||
8ceee660 BH |
619 | /* Sanity check MAC address */ |
620 | if (is_valid_ether_addr(efx->mac_address)) { | |
621 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
622 | } else { | |
e174961c JB |
623 | EFX_ERR(efx, "invalid MAC address %pM\n", |
624 | efx->mac_address); | |
8ceee660 BH |
625 | if (!allow_bad_hwaddr) { |
626 | rc = -EINVAL; | |
627 | goto err; | |
628 | } | |
629 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
630 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
631 | efx->net_dev->dev_addr); | |
8ceee660 BH |
632 | } |
633 | ||
634 | return 0; | |
635 | ||
636 | err: | |
637 | efx_remove_port(efx); | |
638 | return rc; | |
639 | } | |
640 | ||
641 | static int efx_init_port(struct efx_nic *efx) | |
642 | { | |
643 | int rc; | |
644 | ||
645 | EFX_LOG(efx, "init port\n"); | |
646 | ||
647 | /* Initialise the MAC and PHY */ | |
648 | rc = falcon_init_xmac(efx); | |
649 | if (rc) | |
650 | return rc; | |
651 | ||
dc8cfa55 | 652 | efx->port_initialized = true; |
8c8661e4 | 653 | efx->stats_enabled = true; |
8ceee660 BH |
654 | |
655 | /* Reconfigure port to program MAC registers */ | |
656 | falcon_reconfigure_xmac(efx); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
662 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
663 | * efx_reconfigure_port() may have been cancelled */ | |
664 | static void efx_start_port(struct efx_nic *efx) | |
665 | { | |
666 | EFX_LOG(efx, "start port\n"); | |
667 | BUG_ON(efx->port_enabled); | |
668 | ||
669 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 670 | efx->port_enabled = true; |
8ceee660 BH |
671 | __efx_reconfigure_port(efx); |
672 | mutex_unlock(&efx->mac_lock); | |
673 | } | |
674 | ||
675 | /* Prevent efx_reconfigure_work and efx_monitor() from executing, and | |
676 | * efx_set_multicast_list() from scheduling efx_reconfigure_work. | |
677 | * efx_reconfigure_work can still be scheduled via NAPI processing | |
678 | * until efx_flush_all() is called */ | |
679 | static void efx_stop_port(struct efx_nic *efx) | |
680 | { | |
681 | EFX_LOG(efx, "stop port\n"); | |
682 | ||
683 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 684 | efx->port_enabled = false; |
8ceee660 BH |
685 | mutex_unlock(&efx->mac_lock); |
686 | ||
687 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 688 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
689 | netif_addr_lock_bh(efx->net_dev); |
690 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
691 | } |
692 | } | |
693 | ||
694 | static void efx_fini_port(struct efx_nic *efx) | |
695 | { | |
696 | EFX_LOG(efx, "shut down port\n"); | |
697 | ||
698 | if (!efx->port_initialized) | |
699 | return; | |
700 | ||
701 | falcon_fini_xmac(efx); | |
dc8cfa55 | 702 | efx->port_initialized = false; |
8ceee660 | 703 | |
dc8cfa55 | 704 | efx->link_up = false; |
8ceee660 BH |
705 | efx_link_status_changed(efx); |
706 | } | |
707 | ||
708 | static void efx_remove_port(struct efx_nic *efx) | |
709 | { | |
710 | EFX_LOG(efx, "destroying port\n"); | |
711 | ||
712 | falcon_remove_port(efx); | |
713 | } | |
714 | ||
715 | /************************************************************************** | |
716 | * | |
717 | * NIC handling | |
718 | * | |
719 | **************************************************************************/ | |
720 | ||
721 | /* This configures the PCI device to enable I/O and DMA. */ | |
722 | static int efx_init_io(struct efx_nic *efx) | |
723 | { | |
724 | struct pci_dev *pci_dev = efx->pci_dev; | |
725 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
726 | int rc; | |
727 | ||
728 | EFX_LOG(efx, "initialising I/O\n"); | |
729 | ||
730 | rc = pci_enable_device(pci_dev); | |
731 | if (rc) { | |
732 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
733 | goto fail1; | |
734 | } | |
735 | ||
736 | pci_set_master(pci_dev); | |
737 | ||
738 | /* Set the PCI DMA mask. Try all possibilities from our | |
739 | * genuine mask down to 32 bits, because some architectures | |
740 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
741 | * masks event though they reject 46 bit masks. | |
742 | */ | |
743 | while (dma_mask > 0x7fffffffUL) { | |
744 | if (pci_dma_supported(pci_dev, dma_mask) && | |
745 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
746 | break; | |
747 | dma_mask >>= 1; | |
748 | } | |
749 | if (rc) { | |
750 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
751 | goto fail2; | |
752 | } | |
753 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
754 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
755 | if (rc) { | |
756 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
757 | * fail with a mask that pci_set_dma_mask() accepted, | |
758 | * but just in case... | |
759 | */ | |
760 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
761 | goto fail2; | |
762 | } | |
763 | ||
764 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
765 | efx->type->mem_bar); | |
766 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
767 | if (rc) { | |
768 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
769 | rc = -EIO; | |
770 | goto fail3; | |
771 | } | |
772 | efx->membase = ioremap_nocache(efx->membase_phys, | |
773 | efx->type->mem_map_size); | |
774 | if (!efx->membase) { | |
086ea356 BH |
775 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
776 | efx->type->mem_bar, | |
777 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
778 | efx->type->mem_map_size); |
779 | rc = -ENOMEM; | |
780 | goto fail4; | |
781 | } | |
086ea356 BH |
782 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
783 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
784 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
785 | |
786 | return 0; | |
787 | ||
788 | fail4: | |
e1074a0d | 789 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 790 | fail3: |
2c118e0f | 791 | efx->membase_phys = 0; |
8ceee660 BH |
792 | fail2: |
793 | pci_disable_device(efx->pci_dev); | |
794 | fail1: | |
795 | return rc; | |
796 | } | |
797 | ||
798 | static void efx_fini_io(struct efx_nic *efx) | |
799 | { | |
800 | EFX_LOG(efx, "shutting down I/O\n"); | |
801 | ||
802 | if (efx->membase) { | |
803 | iounmap(efx->membase); | |
804 | efx->membase = NULL; | |
805 | } | |
806 | ||
807 | if (efx->membase_phys) { | |
808 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 809 | efx->membase_phys = 0; |
8ceee660 BH |
810 | } |
811 | ||
812 | pci_disable_device(efx->pci_dev); | |
813 | } | |
814 | ||
46123d04 BH |
815 | /* Get number of RX queues wanted. Return number of online CPU |
816 | * packages in the expectation that an IRQ balancer will spread | |
817 | * interrupts across them. */ | |
818 | static int efx_wanted_rx_queues(void) | |
819 | { | |
820 | cpumask_t core_mask; | |
821 | int count; | |
822 | int cpu; | |
823 | ||
824 | cpus_clear(core_mask); | |
825 | count = 0; | |
826 | for_each_online_cpu(cpu) { | |
827 | if (!cpu_isset(cpu, core_mask)) { | |
828 | ++count; | |
829 | cpus_or(core_mask, core_mask, | |
830 | topology_core_siblings(cpu)); | |
831 | } | |
832 | } | |
833 | ||
834 | return count; | |
835 | } | |
836 | ||
837 | /* Probe the number and type of interrupts we are able to obtain, and | |
838 | * the resulting numbers of channels and RX queues. | |
839 | */ | |
8ceee660 BH |
840 | static void efx_probe_interrupts(struct efx_nic *efx) |
841 | { | |
46123d04 BH |
842 | int max_channels = |
843 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
844 | int rc, i; |
845 | ||
846 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
847 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
848 | int wanted_ints; | |
aa6ef27e | 849 | |
46123d04 BH |
850 | /* We want one RX queue and interrupt per CPU package |
851 | * (or as specified by the rss_cpus module parameter). | |
852 | * We will need one channel per interrupt. | |
853 | */ | |
854 | wanted_ints = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); | |
8831da7b | 855 | efx->n_rx_queues = min(wanted_ints, max_channels); |
8ceee660 | 856 | |
8831da7b | 857 | for (i = 0; i < efx->n_rx_queues; i++) |
8ceee660 | 858 | xentries[i].entry = i; |
8831da7b | 859 | rc = pci_enable_msix(efx->pci_dev, xentries, efx->n_rx_queues); |
8ceee660 | 860 | if (rc > 0) { |
8831da7b BH |
861 | EFX_BUG_ON_PARANOID(rc >= efx->n_rx_queues); |
862 | efx->n_rx_queues = rc; | |
8ceee660 | 863 | rc = pci_enable_msix(efx->pci_dev, xentries, |
8831da7b | 864 | efx->n_rx_queues); |
8ceee660 BH |
865 | } |
866 | ||
867 | if (rc == 0) { | |
8831da7b | 868 | for (i = 0; i < efx->n_rx_queues; i++) |
8ceee660 | 869 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
870 | } else { |
871 | /* Fall back to single channel MSI */ | |
872 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
873 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
874 | } | |
875 | } | |
876 | ||
877 | /* Try single interrupt MSI */ | |
878 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 879 | efx->n_rx_queues = 1; |
8ceee660 BH |
880 | rc = pci_enable_msi(efx->pci_dev); |
881 | if (rc == 0) { | |
882 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
883 | } else { |
884 | EFX_ERR(efx, "could not enable MSI\n"); | |
885 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
886 | } | |
887 | } | |
888 | ||
889 | /* Assume legacy interrupts */ | |
890 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 891 | efx->n_rx_queues = 1; |
8ceee660 BH |
892 | efx->legacy_irq = efx->pci_dev->irq; |
893 | } | |
894 | } | |
895 | ||
896 | static void efx_remove_interrupts(struct efx_nic *efx) | |
897 | { | |
898 | struct efx_channel *channel; | |
899 | ||
900 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 901 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
902 | channel->irq = 0; |
903 | pci_disable_msi(efx->pci_dev); | |
904 | pci_disable_msix(efx->pci_dev); | |
905 | ||
906 | /* Remove legacy interrupt */ | |
907 | efx->legacy_irq = 0; | |
908 | } | |
909 | ||
8831da7b | 910 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
911 | { |
912 | struct efx_tx_queue *tx_queue; | |
913 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 914 | |
60ac1065 BH |
915 | efx_for_each_tx_queue(tx_queue, efx) { |
916 | if (!EFX_INT_MODE_USE_MSI(efx) && separate_tx_and_rx_channels) | |
917 | tx_queue->channel = &efx->channel[1]; | |
918 | else | |
919 | tx_queue->channel = &efx->channel[0]; | |
920 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
921 | } | |
8ceee660 | 922 | |
8831da7b BH |
923 | efx_for_each_rx_queue(rx_queue, efx) { |
924 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
925 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
926 | } |
927 | } | |
928 | ||
929 | static int efx_probe_nic(struct efx_nic *efx) | |
930 | { | |
931 | int rc; | |
932 | ||
933 | EFX_LOG(efx, "creating NIC\n"); | |
934 | ||
935 | /* Carry out hardware-type specific initialisation */ | |
936 | rc = falcon_probe_nic(efx); | |
937 | if (rc) | |
938 | return rc; | |
939 | ||
940 | /* Determine the number of channels and RX queues by trying to hook | |
941 | * in MSI-X interrupts. */ | |
942 | efx_probe_interrupts(efx); | |
943 | ||
8831da7b | 944 | efx_set_channels(efx); |
8ceee660 BH |
945 | |
946 | /* Initialise the interrupt moderation settings */ | |
947 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
952 | static void efx_remove_nic(struct efx_nic *efx) | |
953 | { | |
954 | EFX_LOG(efx, "destroying NIC\n"); | |
955 | ||
956 | efx_remove_interrupts(efx); | |
957 | falcon_remove_nic(efx); | |
958 | } | |
959 | ||
960 | /************************************************************************** | |
961 | * | |
962 | * NIC startup/shutdown | |
963 | * | |
964 | *************************************************************************/ | |
965 | ||
966 | static int efx_probe_all(struct efx_nic *efx) | |
967 | { | |
968 | struct efx_channel *channel; | |
969 | int rc; | |
970 | ||
971 | /* Create NIC */ | |
972 | rc = efx_probe_nic(efx); | |
973 | if (rc) { | |
974 | EFX_ERR(efx, "failed to create NIC\n"); | |
975 | goto fail1; | |
976 | } | |
977 | ||
978 | /* Create port */ | |
979 | rc = efx_probe_port(efx); | |
980 | if (rc) { | |
981 | EFX_ERR(efx, "failed to create port\n"); | |
982 | goto fail2; | |
983 | } | |
984 | ||
985 | /* Create channels */ | |
986 | efx_for_each_channel(channel, efx) { | |
987 | rc = efx_probe_channel(channel); | |
988 | if (rc) { | |
989 | EFX_ERR(efx, "failed to create channel %d\n", | |
990 | channel->channel); | |
991 | goto fail3; | |
992 | } | |
993 | } | |
994 | ||
995 | return 0; | |
996 | ||
997 | fail3: | |
998 | efx_for_each_channel(channel, efx) | |
999 | efx_remove_channel(channel); | |
1000 | efx_remove_port(efx); | |
1001 | fail2: | |
1002 | efx_remove_nic(efx); | |
1003 | fail1: | |
1004 | return rc; | |
1005 | } | |
1006 | ||
1007 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1008 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1009 | * and ensures that the port is scheduled to be reconfigured. | |
1010 | * This function is safe to call multiple times when the NIC is in any | |
1011 | * state. */ | |
1012 | static void efx_start_all(struct efx_nic *efx) | |
1013 | { | |
1014 | struct efx_channel *channel; | |
1015 | ||
1016 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1017 | ||
1018 | /* Check that it is appropriate to restart the interface. All | |
1019 | * of these flags are safe to read under just the rtnl lock */ | |
1020 | if (efx->port_enabled) | |
1021 | return; | |
1022 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1023 | return; | |
55668611 | 1024 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1025 | return; |
1026 | ||
1027 | /* Mark the port as enabled so port reconfigurations can start, then | |
1028 | * restart the transmit interface early so the watchdog timer stops */ | |
1029 | efx_start_port(efx); | |
dacccc74 SH |
1030 | if (efx_dev_registered(efx)) |
1031 | efx_wake_queue(efx); | |
8ceee660 BH |
1032 | |
1033 | efx_for_each_channel(channel, efx) | |
1034 | efx_start_channel(channel); | |
1035 | ||
1036 | falcon_enable_interrupts(efx); | |
1037 | ||
1038 | /* Start hardware monitor if we're in RUNNING */ | |
1039 | if (efx->state == STATE_RUNNING) | |
1040 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1041 | efx_monitor_interval); | |
1042 | } | |
1043 | ||
1044 | /* Flush all delayed work. Should only be called when no more delayed work | |
1045 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1046 | * since we're holding the rtnl_lock at this point. */ | |
1047 | static void efx_flush_all(struct efx_nic *efx) | |
1048 | { | |
1049 | struct efx_rx_queue *rx_queue; | |
1050 | ||
1051 | /* Make sure the hardware monitor is stopped */ | |
1052 | cancel_delayed_work_sync(&efx->monitor_work); | |
1053 | ||
1054 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1055 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1056 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1057 | |
1058 | /* Stop scheduled port reconfigurations */ | |
1059 | cancel_work_sync(&efx->reconfigure_work); | |
1060 | ||
1061 | } | |
1062 | ||
1063 | /* Quiesce hardware and software without bringing the link down. | |
1064 | * Safe to call multiple times, when the nic and interface is in any | |
1065 | * state. The caller is guaranteed to subsequently be in a position | |
1066 | * to modify any hardware and software state they see fit without | |
1067 | * taking locks. */ | |
1068 | static void efx_stop_all(struct efx_nic *efx) | |
1069 | { | |
1070 | struct efx_channel *channel; | |
1071 | ||
1072 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1073 | ||
1074 | /* port_enabled can be read safely under the rtnl lock */ | |
1075 | if (!efx->port_enabled) | |
1076 | return; | |
1077 | ||
1078 | /* Disable interrupts and wait for ISR to complete */ | |
1079 | falcon_disable_interrupts(efx); | |
1080 | if (efx->legacy_irq) | |
1081 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1082 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1083 | if (channel->irq) |
1084 | synchronize_irq(channel->irq); | |
b3475645 | 1085 | } |
8ceee660 BH |
1086 | |
1087 | /* Stop all NAPI processing and synchronous rx refills */ | |
1088 | efx_for_each_channel(channel, efx) | |
1089 | efx_stop_channel(channel); | |
1090 | ||
1091 | /* Stop all asynchronous port reconfigurations. Since all | |
1092 | * event processing has already been stopped, there is no | |
1093 | * window to loose phy events */ | |
1094 | efx_stop_port(efx); | |
1095 | ||
1096 | /* Flush reconfigure_work, refill_workqueue, monitor_work */ | |
1097 | efx_flush_all(efx); | |
1098 | ||
1099 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1100 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1101 | falcon_drain_tx_fifo(efx); |
1102 | ||
1103 | /* Stop the kernel transmit interface late, so the watchdog | |
1104 | * timer isn't ticking over the flush */ | |
55668611 | 1105 | if (efx_dev_registered(efx)) { |
dacccc74 | 1106 | efx_stop_queue(efx); |
8ceee660 BH |
1107 | netif_tx_lock_bh(efx->net_dev); |
1108 | netif_tx_unlock_bh(efx->net_dev); | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | static void efx_remove_all(struct efx_nic *efx) | |
1113 | { | |
1114 | struct efx_channel *channel; | |
1115 | ||
1116 | efx_for_each_channel(channel, efx) | |
1117 | efx_remove_channel(channel); | |
1118 | efx_remove_port(efx); | |
1119 | efx_remove_nic(efx); | |
1120 | } | |
1121 | ||
1122 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1123 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1124 | { |
8ceee660 BH |
1125 | EFX_ASSERT_RESET_SERIALISED(efx); |
1126 | ||
1127 | efx_stop_all(efx); | |
1128 | ||
1129 | efx_fini_channels(efx); | |
bc3c90a2 | 1130 | efx_init_channels(efx); |
8ceee660 BH |
1131 | |
1132 | efx_start_all(efx); | |
8ceee660 BH |
1133 | } |
1134 | ||
1135 | /************************************************************************** | |
1136 | * | |
1137 | * Interrupt moderation | |
1138 | * | |
1139 | **************************************************************************/ | |
1140 | ||
1141 | /* Set interrupt moderation parameters */ | |
1142 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1143 | { | |
1144 | struct efx_tx_queue *tx_queue; | |
1145 | struct efx_rx_queue *rx_queue; | |
1146 | ||
1147 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1148 | ||
1149 | efx_for_each_tx_queue(tx_queue, efx) | |
1150 | tx_queue->channel->irq_moderation = tx_usecs; | |
1151 | ||
1152 | efx_for_each_rx_queue(rx_queue, efx) | |
1153 | rx_queue->channel->irq_moderation = rx_usecs; | |
1154 | } | |
1155 | ||
1156 | /************************************************************************** | |
1157 | * | |
1158 | * Hardware monitor | |
1159 | * | |
1160 | **************************************************************************/ | |
1161 | ||
1162 | /* Run periodically off the general workqueue. Serialised against | |
1163 | * efx_reconfigure_port via the mac_lock */ | |
1164 | static void efx_monitor(struct work_struct *data) | |
1165 | { | |
1166 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1167 | monitor_work.work); | |
1168 | int rc = 0; | |
1169 | ||
1170 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1171 | raw_smp_processor_id()); | |
1172 | ||
1173 | ||
1174 | /* If the mac_lock is already held then it is likely a port | |
1175 | * reconfiguration is already in place, which will likely do | |
1176 | * most of the work of check_hw() anyway. */ | |
1177 | if (!mutex_trylock(&efx->mac_lock)) { | |
1178 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1179 | efx_monitor_interval); | |
1180 | return; | |
1181 | } | |
1182 | ||
1183 | if (efx->port_enabled) | |
1184 | rc = falcon_check_xmac(efx); | |
1185 | mutex_unlock(&efx->mac_lock); | |
1186 | ||
8ceee660 BH |
1187 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1188 | efx_monitor_interval); | |
1189 | } | |
1190 | ||
1191 | /************************************************************************** | |
1192 | * | |
1193 | * ioctls | |
1194 | * | |
1195 | *************************************************************************/ | |
1196 | ||
1197 | /* Net device ioctl | |
1198 | * Context: process, rtnl_lock() held. | |
1199 | */ | |
1200 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1201 | { | |
767e468c | 1202 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1203 | |
1204 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1205 | ||
1206 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1207 | } | |
1208 | ||
1209 | /************************************************************************** | |
1210 | * | |
1211 | * NAPI interface | |
1212 | * | |
1213 | **************************************************************************/ | |
1214 | ||
1215 | static int efx_init_napi(struct efx_nic *efx) | |
1216 | { | |
1217 | struct efx_channel *channel; | |
1218 | int rc; | |
1219 | ||
1220 | efx_for_each_channel(channel, efx) { | |
1221 | channel->napi_dev = efx->net_dev; | |
1222 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1223 | if (rc) | |
1224 | goto err; | |
1225 | } | |
1226 | return 0; | |
1227 | err: | |
1228 | efx_fini_napi(efx); | |
1229 | return rc; | |
1230 | } | |
1231 | ||
1232 | static void efx_fini_napi(struct efx_nic *efx) | |
1233 | { | |
1234 | struct efx_channel *channel; | |
1235 | ||
1236 | efx_for_each_channel(channel, efx) { | |
1237 | efx_lro_fini(&channel->lro_mgr); | |
1238 | channel->napi_dev = NULL; | |
1239 | } | |
1240 | } | |
1241 | ||
1242 | /************************************************************************** | |
1243 | * | |
1244 | * Kernel netpoll interface | |
1245 | * | |
1246 | *************************************************************************/ | |
1247 | ||
1248 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1249 | ||
1250 | /* Although in the common case interrupts will be disabled, this is not | |
1251 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1252 | * so no locking is required. | |
1253 | */ | |
1254 | static void efx_netpoll(struct net_device *net_dev) | |
1255 | { | |
767e468c | 1256 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1257 | struct efx_channel *channel; |
1258 | ||
64ee3120 | 1259 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1260 | efx_schedule_channel(channel); |
1261 | } | |
1262 | ||
1263 | #endif | |
1264 | ||
1265 | /************************************************************************** | |
1266 | * | |
1267 | * Kernel net device interface | |
1268 | * | |
1269 | *************************************************************************/ | |
1270 | ||
1271 | /* Context: process, rtnl_lock() held. */ | |
1272 | static int efx_net_open(struct net_device *net_dev) | |
1273 | { | |
767e468c | 1274 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1275 | EFX_ASSERT_RESET_SERIALISED(efx); |
1276 | ||
1277 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1278 | raw_smp_processor_id()); | |
1279 | ||
f8b87c17 BH |
1280 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1281 | return -EBUSY; | |
1282 | ||
8ceee660 BH |
1283 | efx_start_all(efx); |
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | /* Context: process, rtnl_lock() held. | |
1288 | * Note that the kernel will ignore our return code; this method | |
1289 | * should really be a void. | |
1290 | */ | |
1291 | static int efx_net_stop(struct net_device *net_dev) | |
1292 | { | |
767e468c | 1293 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1294 | |
1295 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1296 | raw_smp_processor_id()); | |
1297 | ||
1298 | /* Stop the device and flush all the channels */ | |
1299 | efx_stop_all(efx); | |
1300 | efx_fini_channels(efx); | |
bc3c90a2 | 1301 | efx_init_channels(efx); |
8ceee660 BH |
1302 | |
1303 | return 0; | |
1304 | } | |
1305 | ||
5b9e207c | 1306 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1307 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1308 | { | |
767e468c | 1309 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1310 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1311 | struct net_device_stats *stats = &net_dev->stats; | |
1312 | ||
5b9e207c BH |
1313 | /* Update stats if possible, but do not wait if another thread |
1314 | * is updating them (or resetting the NIC); slightly stale | |
1315 | * stats are acceptable. | |
1316 | */ | |
8ceee660 BH |
1317 | if (!spin_trylock(&efx->stats_lock)) |
1318 | return stats; | |
8c8661e4 | 1319 | if (efx->stats_enabled) { |
8ceee660 BH |
1320 | falcon_update_stats_xmac(efx); |
1321 | falcon_update_nic_stats(efx); | |
1322 | } | |
1323 | spin_unlock(&efx->stats_lock); | |
1324 | ||
1325 | stats->rx_packets = mac_stats->rx_packets; | |
1326 | stats->tx_packets = mac_stats->tx_packets; | |
1327 | stats->rx_bytes = mac_stats->rx_bytes; | |
1328 | stats->tx_bytes = mac_stats->tx_bytes; | |
1329 | stats->multicast = mac_stats->rx_multicast; | |
1330 | stats->collisions = mac_stats->tx_collision; | |
1331 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1332 | mac_stats->rx_length_error); | |
1333 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1334 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1335 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1336 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1337 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1338 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1339 | ||
1340 | stats->rx_errors = (stats->rx_length_errors + | |
1341 | stats->rx_over_errors + | |
1342 | stats->rx_crc_errors + | |
1343 | stats->rx_frame_errors + | |
1344 | stats->rx_fifo_errors + | |
1345 | stats->rx_missed_errors + | |
1346 | mac_stats->rx_symbol_error); | |
1347 | stats->tx_errors = (stats->tx_window_errors + | |
1348 | mac_stats->tx_bad); | |
1349 | ||
1350 | return stats; | |
1351 | } | |
1352 | ||
1353 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1354 | static void efx_watchdog(struct net_device *net_dev) | |
1355 | { | |
767e468c | 1356 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1357 | |
739bb23d BH |
1358 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1359 | " resetting channels\n", | |
1360 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1361 | |
739bb23d | 1362 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1363 | } |
1364 | ||
1365 | ||
1366 | /* Context: process, rtnl_lock() held. */ | |
1367 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1368 | { | |
767e468c | 1369 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1370 | int rc = 0; |
1371 | ||
1372 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1373 | ||
1374 | if (new_mtu > EFX_MAX_MTU) | |
1375 | return -EINVAL; | |
1376 | ||
1377 | efx_stop_all(efx); | |
1378 | ||
1379 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1380 | ||
1381 | efx_fini_channels(efx); | |
1382 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1383 | efx_init_channels(efx); |
8ceee660 BH |
1384 | |
1385 | efx_start_all(efx); | |
1386 | return rc; | |
8ceee660 BH |
1387 | } |
1388 | ||
1389 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1390 | { | |
767e468c | 1391 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1392 | struct sockaddr *addr = data; |
1393 | char *new_addr = addr->sa_data; | |
1394 | ||
1395 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1396 | ||
1397 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1398 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1399 | new_addr); | |
8ceee660 BH |
1400 | return -EINVAL; |
1401 | } | |
1402 | ||
1403 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1404 | ||
1405 | /* Reconfigure the MAC */ | |
1406 | efx_reconfigure_port(efx); | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
a816f75a | 1411 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1412 | static void efx_set_multicast_list(struct net_device *net_dev) |
1413 | { | |
767e468c | 1414 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1415 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1416 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1417 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1418 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1419 | u32 crc; |
1420 | int bit; | |
1421 | int i; | |
1422 | ||
a816f75a | 1423 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1424 | |
1425 | /* Build multicast hash table */ | |
1426 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1427 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1428 | } else { | |
1429 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1430 | for (i = 0; i < net_dev->mc_count; i++) { | |
1431 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1432 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1433 | set_bit_le(bit, mc_hash->byte); | |
1434 | mc_list = mc_list->next; | |
1435 | } | |
1436 | } | |
1437 | ||
a816f75a BH |
1438 | if (!efx->port_enabled) |
1439 | /* Delay pushing settings until efx_start_port() */ | |
1440 | return; | |
1441 | ||
1442 | if (changed) | |
1443 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
1444 | ||
8ceee660 BH |
1445 | /* Create and activate new global multicast hash table */ |
1446 | falcon_set_multicast_hash(efx); | |
1447 | } | |
1448 | ||
c3ecb9f3 SH |
1449 | static const struct net_device_ops efx_netdev_ops = { |
1450 | .ndo_open = efx_net_open, | |
1451 | .ndo_stop = efx_net_stop, | |
1452 | .ndo_get_stats = efx_net_stats, | |
1453 | .ndo_tx_timeout = efx_watchdog, | |
1454 | .ndo_start_xmit = efx_hard_start_xmit, | |
1455 | .ndo_validate_addr = eth_validate_addr, | |
1456 | .ndo_do_ioctl = efx_ioctl, | |
1457 | .ndo_change_mtu = efx_change_mtu, | |
1458 | .ndo_set_mac_address = efx_set_mac_address, | |
1459 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1460 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1461 | .ndo_poll_controller = efx_netpoll, | |
1462 | #endif | |
1463 | }; | |
1464 | ||
8ceee660 BH |
1465 | static int efx_netdev_event(struct notifier_block *this, |
1466 | unsigned long event, void *ptr) | |
1467 | { | |
d3208b5e | 1468 | struct net_device *net_dev = ptr; |
8ceee660 | 1469 | |
c3ecb9f3 | 1470 | if (net_dev->netdev_ops == &efx_netdev_ops && event == NETDEV_CHANGENAME) { |
767e468c | 1471 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1472 | |
1473 | strcpy(efx->name, net_dev->name); | |
f4150724 | 1474 | efx_mtd_rename(efx); |
8ceee660 BH |
1475 | } |
1476 | ||
1477 | return NOTIFY_DONE; | |
1478 | } | |
1479 | ||
1480 | static struct notifier_block efx_netdev_notifier = { | |
1481 | .notifier_call = efx_netdev_event, | |
1482 | }; | |
1483 | ||
1484 | static int efx_register_netdev(struct efx_nic *efx) | |
1485 | { | |
1486 | struct net_device *net_dev = efx->net_dev; | |
1487 | int rc; | |
1488 | ||
1489 | net_dev->watchdog_timeo = 5 * HZ; | |
1490 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1491 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1492 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1493 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1494 | ||
1495 | /* Always start with carrier off; PHY events will detect the link */ | |
1496 | netif_carrier_off(efx->net_dev); | |
1497 | ||
1498 | /* Clear MAC statistics */ | |
1499 | falcon_update_stats_xmac(efx); | |
1500 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
1501 | ||
1502 | rc = register_netdev(net_dev); | |
1503 | if (rc) { | |
1504 | EFX_ERR(efx, "could not register net dev\n"); | |
1505 | return rc; | |
1506 | } | |
1507 | strcpy(efx->name, net_dev->name); | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1513 | { | |
1514 | struct efx_tx_queue *tx_queue; | |
1515 | ||
1516 | if (!efx->net_dev) | |
1517 | return; | |
1518 | ||
767e468c | 1519 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1520 | |
1521 | /* Free up any skbs still remaining. This has to happen before | |
1522 | * we try to unregister the netdev as running their destructors | |
1523 | * may be needed to get the device ref. count to 0. */ | |
1524 | efx_for_each_tx_queue(tx_queue, efx) | |
1525 | efx_release_tx_buffers(tx_queue); | |
1526 | ||
55668611 | 1527 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1528 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1529 | unregister_netdev(efx->net_dev); | |
1530 | } | |
1531 | } | |
1532 | ||
1533 | /************************************************************************** | |
1534 | * | |
1535 | * Device reset and suspend | |
1536 | * | |
1537 | **************************************************************************/ | |
1538 | ||
2467ca46 BH |
1539 | /* Tears down the entire software state and most of the hardware state |
1540 | * before reset. */ | |
8c8661e4 | 1541 | void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
8ceee660 BH |
1542 | { |
1543 | int rc; | |
1544 | ||
1545 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1546 | ||
2467ca46 BH |
1547 | /* The net_dev->get_stats handler is quite slow, and will fail |
1548 | * if a fetch is pending over reset. Serialise against it. */ | |
1549 | spin_lock(&efx->stats_lock); | |
8c8661e4 | 1550 | efx->stats_enabled = false; |
2467ca46 BH |
1551 | spin_unlock(&efx->stats_lock); |
1552 | ||
1553 | efx_stop_all(efx); | |
1554 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1555 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1556 | |
8ceee660 | 1557 | rc = falcon_xmac_get_settings(efx, ecmd); |
2467ca46 | 1558 | if (rc) |
8ceee660 | 1559 | EFX_ERR(efx, "could not back up PHY settings\n"); |
8ceee660 BH |
1560 | |
1561 | efx_fini_channels(efx); | |
8ceee660 BH |
1562 | } |
1563 | ||
2467ca46 BH |
1564 | /* This function will always ensure that the locks acquired in |
1565 | * efx_reset_down() are released. A failure return code indicates | |
1566 | * that we were unable to reinitialise the hardware, and the | |
1567 | * driver should be disabled. If ok is false, then the rx and tx | |
1568 | * engines are not restarted, pending a RESET_DISABLE. */ | |
8c8661e4 | 1569 | int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok) |
8ceee660 BH |
1570 | { |
1571 | int rc; | |
1572 | ||
2467ca46 | 1573 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1574 | |
2467ca46 | 1575 | rc = falcon_init_nic(efx); |
8ceee660 | 1576 | if (rc) { |
2467ca46 BH |
1577 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1578 | ok = false; | |
8ceee660 BH |
1579 | } |
1580 | ||
2467ca46 BH |
1581 | if (ok) { |
1582 | efx_init_channels(efx); | |
8ceee660 | 1583 | |
2467ca46 BH |
1584 | if (falcon_xmac_set_settings(efx, ecmd)) |
1585 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
1586 | } | |
1587 | ||
f4150724 | 1588 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1589 | mutex_unlock(&efx->mac_lock); |
1590 | ||
8c8661e4 | 1591 | if (ok) { |
2467ca46 | 1592 | efx_start_all(efx); |
8c8661e4 BH |
1593 | efx->stats_enabled = true; |
1594 | } | |
8ceee660 BH |
1595 | return rc; |
1596 | } | |
1597 | ||
1598 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1599 | * Note that the reset may fail, in which case the card will be left | |
1600 | * in a most-probably-unusable state. | |
1601 | * | |
1602 | * This function will sleep. You cannot reset from within an atomic | |
1603 | * state; use efx_schedule_reset() instead. | |
1604 | * | |
1605 | * Grabs the rtnl_lock. | |
1606 | */ | |
1607 | static int efx_reset(struct efx_nic *efx) | |
1608 | { | |
1609 | struct ethtool_cmd ecmd; | |
1610 | enum reset_type method = efx->reset_pending; | |
1611 | int rc; | |
1612 | ||
1613 | /* Serialise with kernel interfaces */ | |
1614 | rtnl_lock(); | |
1615 | ||
1616 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1617 | * flag set so that efx_pci_probe_main will be retried */ | |
1618 | if (efx->state != STATE_RUNNING) { | |
1619 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1620 | goto unlock_rtnl; | |
1621 | } | |
1622 | ||
8ceee660 BH |
1623 | EFX_INFO(efx, "resetting (%d)\n", method); |
1624 | ||
2467ca46 | 1625 | efx_reset_down(efx, &ecmd); |
8ceee660 BH |
1626 | |
1627 | rc = falcon_reset_hw(efx, method); | |
1628 | if (rc) { | |
1629 | EFX_ERR(efx, "failed to reset hardware\n"); | |
2467ca46 | 1630 | goto fail; |
8ceee660 BH |
1631 | } |
1632 | ||
1633 | /* Allow resets to be rescheduled. */ | |
1634 | efx->reset_pending = RESET_TYPE_NONE; | |
1635 | ||
1636 | /* Reinitialise bus-mastering, which may have been turned off before | |
1637 | * the reset was scheduled. This is still appropriate, even in the | |
1638 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1639 | * can respond to requests. */ | |
1640 | pci_set_master(efx->pci_dev); | |
1641 | ||
8ceee660 BH |
1642 | /* Leave device stopped if necessary */ |
1643 | if (method == RESET_TYPE_DISABLE) { | |
8ceee660 | 1644 | rc = -EIO; |
2467ca46 | 1645 | goto fail; |
8ceee660 BH |
1646 | } |
1647 | ||
2467ca46 | 1648 | rc = efx_reset_up(efx, &ecmd, true); |
8ceee660 | 1649 | if (rc) |
2467ca46 | 1650 | goto disable; |
8ceee660 | 1651 | |
8ceee660 | 1652 | EFX_LOG(efx, "reset complete\n"); |
8ceee660 BH |
1653 | unlock_rtnl: |
1654 | rtnl_unlock(); | |
1655 | return 0; | |
1656 | ||
2467ca46 BH |
1657 | fail: |
1658 | efx_reset_up(efx, &ecmd, false); | |
1659 | disable: | |
8ceee660 BH |
1660 | EFX_ERR(efx, "has been disabled\n"); |
1661 | efx->state = STATE_DISABLED; | |
1662 | ||
8ceee660 BH |
1663 | rtnl_unlock(); |
1664 | efx_unregister_netdev(efx); | |
1665 | efx_fini_port(efx); | |
1666 | return rc; | |
1667 | } | |
1668 | ||
1669 | /* The worker thread exists so that code that cannot sleep can | |
1670 | * schedule a reset for later. | |
1671 | */ | |
1672 | static void efx_reset_work(struct work_struct *data) | |
1673 | { | |
1674 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1675 | ||
1676 | efx_reset(nic); | |
1677 | } | |
1678 | ||
1679 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1680 | { | |
1681 | enum reset_type method; | |
1682 | ||
1683 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1684 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1685 | return; | |
1686 | } | |
1687 | ||
1688 | switch (type) { | |
1689 | case RESET_TYPE_INVISIBLE: | |
1690 | case RESET_TYPE_ALL: | |
1691 | case RESET_TYPE_WORLD: | |
1692 | case RESET_TYPE_DISABLE: | |
1693 | method = type; | |
1694 | break; | |
1695 | case RESET_TYPE_RX_RECOVERY: | |
1696 | case RESET_TYPE_RX_DESC_FETCH: | |
1697 | case RESET_TYPE_TX_DESC_FETCH: | |
1698 | case RESET_TYPE_TX_SKIP: | |
1699 | method = RESET_TYPE_INVISIBLE; | |
1700 | break; | |
1701 | default: | |
1702 | method = RESET_TYPE_ALL; | |
1703 | break; | |
1704 | } | |
1705 | ||
1706 | if (method != type) | |
1707 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1708 | else | |
1709 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1710 | ||
1711 | efx->reset_pending = method; | |
1712 | ||
1ab00629 | 1713 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1714 | } |
1715 | ||
1716 | /************************************************************************** | |
1717 | * | |
1718 | * List of NICs we support | |
1719 | * | |
1720 | **************************************************************************/ | |
1721 | ||
1722 | /* PCI device ID table */ | |
1723 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1724 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1725 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1726 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1727 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1728 | {0} /* end of list */ | |
1729 | }; | |
1730 | ||
1731 | /************************************************************************** | |
1732 | * | |
1733 | * Dummy PHY/MAC/Board operations | |
1734 | * | |
01aad7b6 | 1735 | * Can be used for some unimplemented operations |
8ceee660 BH |
1736 | * Needed so all function pointers are valid and do not have to be tested |
1737 | * before use | |
1738 | * | |
1739 | **************************************************************************/ | |
1740 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1741 | { | |
1742 | return 0; | |
1743 | } | |
1744 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1745 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 BH |
1746 | |
1747 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1748 | .init = efx_port_dummy_op_int, | |
1749 | .reconfigure = efx_port_dummy_op_void, | |
1750 | .check_hw = efx_port_dummy_op_int, | |
1751 | .fini = efx_port_dummy_op_void, | |
1752 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1753 | }; |
1754 | ||
8ceee660 | 1755 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 BH |
1756 | .init = efx_port_dummy_op_int, |
1757 | .init_leds = efx_port_dummy_op_int, | |
1758 | .set_fault_led = efx_port_dummy_op_blink, | |
a17102b1 | 1759 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1760 | .blink = efx_port_dummy_op_blink, |
1761 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1762 | }; |
1763 | ||
1764 | /************************************************************************** | |
1765 | * | |
1766 | * Data housekeeping | |
1767 | * | |
1768 | **************************************************************************/ | |
1769 | ||
1770 | /* This zeroes out and then fills in the invariants in a struct | |
1771 | * efx_nic (including all sub-structures). | |
1772 | */ | |
1773 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1774 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1775 | { | |
1776 | struct efx_channel *channel; | |
1777 | struct efx_tx_queue *tx_queue; | |
1778 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1779 | int i; |
8ceee660 BH |
1780 | |
1781 | /* Initialise common structures */ | |
1782 | memset(efx, 0, sizeof(*efx)); | |
1783 | spin_lock_init(&efx->biu_lock); | |
1784 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1785 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1786 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1787 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1788 | efx->pci_dev = pci_dev; | |
1789 | efx->state = STATE_INIT; | |
1790 | efx->reset_pending = RESET_TYPE_NONE; | |
1791 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1792 | efx->board_info = efx_dummy_board_info; | |
1793 | ||
1794 | efx->net_dev = net_dev; | |
dc8cfa55 | 1795 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1796 | spin_lock_init(&efx->netif_stop_lock); |
1797 | spin_lock_init(&efx->stats_lock); | |
1798 | mutex_init(&efx->mac_lock); | |
1799 | efx->phy_op = &efx_dummy_phy_operations; | |
1800 | efx->mii.dev = net_dev; | |
1801 | INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work); | |
1802 | atomic_set(&efx->netif_stop_count, 1); | |
1803 | ||
1804 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1805 | channel = &efx->channel[i]; | |
1806 | channel->efx = efx; | |
1807 | channel->channel = i; | |
dc8cfa55 | 1808 | channel->work_pending = false; |
8ceee660 | 1809 | } |
60ac1065 | 1810 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1811 | tx_queue = &efx->tx_queue[i]; |
1812 | tx_queue->efx = efx; | |
1813 | tx_queue->queue = i; | |
1814 | tx_queue->buffer = NULL; | |
1815 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1816 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1817 | } |
1818 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1819 | rx_queue = &efx->rx_queue[i]; | |
1820 | rx_queue->efx = efx; | |
1821 | rx_queue->queue = i; | |
1822 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1823 | rx_queue->buffer = NULL; | |
1824 | spin_lock_init(&rx_queue->add_lock); | |
1825 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1826 | } | |
1827 | ||
1828 | efx->type = type; | |
1829 | ||
1830 | /* Sanity-check NIC type */ | |
1831 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1832 | (efx->type->txd_ring_mask + 1)); | |
1833 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1834 | (efx->type->rxd_ring_mask + 1)); | |
1835 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1836 | (efx->type->evq_size - 1)); | |
1837 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1838 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1839 | (efx->type->txd_ring_mask + 1 + | |
1840 | efx->type->rxd_ring_mask + 1)); | |
1841 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1842 | ||
1843 | /* Higher numbered interrupt modes are less capable! */ | |
1844 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1845 | interrupt_mode); | |
1846 | ||
1847 | efx->workqueue = create_singlethread_workqueue("sfc_work"); | |
1ab00629 SH |
1848 | if (!efx->workqueue) |
1849 | return -ENOMEM; | |
8d9853d9 | 1850 | |
8ceee660 | 1851 | return 0; |
8ceee660 BH |
1852 | } |
1853 | ||
1854 | static void efx_fini_struct(struct efx_nic *efx) | |
1855 | { | |
1856 | if (efx->workqueue) { | |
1857 | destroy_workqueue(efx->workqueue); | |
1858 | efx->workqueue = NULL; | |
1859 | } | |
1860 | } | |
1861 | ||
1862 | /************************************************************************** | |
1863 | * | |
1864 | * PCI interface | |
1865 | * | |
1866 | **************************************************************************/ | |
1867 | ||
1868 | /* Main body of final NIC shutdown code | |
1869 | * This is called only at module unload (or hotplug removal). | |
1870 | */ | |
1871 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1872 | { | |
1873 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1874 | ||
1875 | /* Skip everything if we never obtained a valid membase */ | |
1876 | if (!efx->membase) | |
1877 | return; | |
1878 | ||
1879 | efx_fini_channels(efx); | |
1880 | efx_fini_port(efx); | |
1881 | ||
1882 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1883 | efx->board_info.fini(efx); |
8ceee660 BH |
1884 | falcon_fini_interrupt(efx); |
1885 | ||
1886 | efx_fini_napi(efx); | |
1887 | efx_remove_all(efx); | |
1888 | } | |
1889 | ||
1890 | /* Final NIC shutdown | |
1891 | * This is called only at module unload (or hotplug removal). | |
1892 | */ | |
1893 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1894 | { | |
1895 | struct efx_nic *efx; | |
1896 | ||
1897 | efx = pci_get_drvdata(pci_dev); | |
1898 | if (!efx) | |
1899 | return; | |
1900 | ||
f4150724 BH |
1901 | efx_mtd_remove(efx); |
1902 | ||
8ceee660 BH |
1903 | /* Mark the NIC as fini, then stop the interface */ |
1904 | rtnl_lock(); | |
1905 | efx->state = STATE_FINI; | |
1906 | dev_close(efx->net_dev); | |
1907 | ||
1908 | /* Allow any queued efx_resets() to complete */ | |
1909 | rtnl_unlock(); | |
1910 | ||
1911 | if (efx->membase == NULL) | |
1912 | goto out; | |
1913 | ||
1914 | efx_unregister_netdev(efx); | |
1915 | ||
1916 | /* Wait for any scheduled resets to complete. No more will be | |
1917 | * scheduled from this point because efx_stop_all() has been | |
1918 | * called, we are no longer registered with driverlink, and | |
1919 | * the net_device's have been removed. */ | |
1ab00629 | 1920 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
1921 | |
1922 | efx_pci_remove_main(efx); | |
1923 | ||
1924 | out: | |
1925 | efx_fini_io(efx); | |
1926 | EFX_LOG(efx, "shutdown successful\n"); | |
1927 | ||
1928 | pci_set_drvdata(pci_dev, NULL); | |
1929 | efx_fini_struct(efx); | |
1930 | free_netdev(efx->net_dev); | |
1931 | }; | |
1932 | ||
1933 | /* Main body of NIC initialisation | |
1934 | * This is called at module load (or hotplug insertion, theoretically). | |
1935 | */ | |
1936 | static int efx_pci_probe_main(struct efx_nic *efx) | |
1937 | { | |
1938 | int rc; | |
1939 | ||
1940 | /* Do start-of-day initialisation */ | |
1941 | rc = efx_probe_all(efx); | |
1942 | if (rc) | |
1943 | goto fail1; | |
1944 | ||
1945 | rc = efx_init_napi(efx); | |
1946 | if (rc) | |
1947 | goto fail2; | |
1948 | ||
1949 | /* Initialise the board */ | |
1950 | rc = efx->board_info.init(efx); | |
1951 | if (rc) { | |
1952 | EFX_ERR(efx, "failed to initialise board\n"); | |
1953 | goto fail3; | |
1954 | } | |
1955 | ||
1956 | rc = falcon_init_nic(efx); | |
1957 | if (rc) { | |
1958 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1959 | goto fail4; | |
1960 | } | |
1961 | ||
1962 | rc = efx_init_port(efx); | |
1963 | if (rc) { | |
1964 | EFX_ERR(efx, "failed to initialise port\n"); | |
1965 | goto fail5; | |
1966 | } | |
1967 | ||
bc3c90a2 | 1968 | efx_init_channels(efx); |
8ceee660 BH |
1969 | |
1970 | rc = falcon_init_interrupt(efx); | |
1971 | if (rc) | |
bc3c90a2 | 1972 | goto fail6; |
8ceee660 BH |
1973 | |
1974 | return 0; | |
1975 | ||
8ceee660 | 1976 | fail6: |
bc3c90a2 | 1977 | efx_fini_channels(efx); |
8ceee660 BH |
1978 | efx_fini_port(efx); |
1979 | fail5: | |
1980 | fail4: | |
a17102b1 | 1981 | efx->board_info.fini(efx); |
8ceee660 BH |
1982 | fail3: |
1983 | efx_fini_napi(efx); | |
1984 | fail2: | |
1985 | efx_remove_all(efx); | |
1986 | fail1: | |
1987 | return rc; | |
1988 | } | |
1989 | ||
1990 | /* NIC initialisation | |
1991 | * | |
1992 | * This is called at module load (or hotplug insertion, | |
1993 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
1994 | * sets up and registers the network devices with the kernel and hooks | |
1995 | * the interrupt service routine. It does not prepare the device for | |
1996 | * transmission; this is left to the first time one of the network | |
1997 | * interfaces is brought up (i.e. efx_net_open). | |
1998 | */ | |
1999 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2000 | const struct pci_device_id *entry) | |
2001 | { | |
2002 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2003 | struct net_device *net_dev; | |
2004 | struct efx_nic *efx; | |
2005 | int i, rc; | |
2006 | ||
2007 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2008 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2009 | if (!net_dev) | |
2010 | return -ENOMEM; | |
b9b39b62 BH |
2011 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2012 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2013 | if (lro) |
2014 | net_dev->features |= NETIF_F_LRO; | |
28506563 BH |
2015 | /* Mask for features that also apply to VLAN devices */ |
2016 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2017 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2018 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2019 | pci_set_drvdata(pci_dev, efx); |
2020 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2021 | if (rc) | |
2022 | goto fail1; | |
2023 | ||
2024 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2025 | ||
2026 | /* Set up basic I/O (BAR mappings etc) */ | |
2027 | rc = efx_init_io(efx); | |
2028 | if (rc) | |
2029 | goto fail2; | |
2030 | ||
2031 | /* No serialisation is required with the reset path because | |
2032 | * we're in STATE_INIT. */ | |
2033 | for (i = 0; i < 5; i++) { | |
2034 | rc = efx_pci_probe_main(efx); | |
2035 | if (rc == 0) | |
2036 | break; | |
2037 | ||
2038 | /* Serialise against efx_reset(). No more resets will be | |
2039 | * scheduled since efx_stop_all() has been called, and we | |
2040 | * have not and never have been registered with either | |
2041 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2042 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2043 | |
2044 | /* Retry if a recoverably reset event has been scheduled */ | |
2045 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2046 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2047 | goto fail3; | |
2048 | ||
2049 | efx->reset_pending = RESET_TYPE_NONE; | |
2050 | } | |
2051 | ||
2052 | if (rc) { | |
2053 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2054 | goto fail4; | |
2055 | } | |
2056 | ||
2057 | /* Switch to the running state before we expose the device to | |
2058 | * the OS. This is to ensure that the initial gathering of | |
2059 | * MAC stats succeeds. */ | |
2060 | rtnl_lock(); | |
2061 | efx->state = STATE_RUNNING; | |
2062 | rtnl_unlock(); | |
2063 | ||
2064 | rc = efx_register_netdev(efx); | |
2065 | if (rc) | |
2066 | goto fail5; | |
2067 | ||
2068 | EFX_LOG(efx, "initialisation successful\n"); | |
2069 | ||
f4150724 | 2070 | efx_mtd_probe(efx); /* allowed to fail */ |
8ceee660 BH |
2071 | return 0; |
2072 | ||
2073 | fail5: | |
2074 | efx_pci_remove_main(efx); | |
2075 | fail4: | |
2076 | fail3: | |
2077 | efx_fini_io(efx); | |
2078 | fail2: | |
2079 | efx_fini_struct(efx); | |
2080 | fail1: | |
2081 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2082 | free_netdev(net_dev); | |
2083 | return rc; | |
2084 | } | |
2085 | ||
2086 | static struct pci_driver efx_pci_driver = { | |
2087 | .name = EFX_DRIVER_NAME, | |
2088 | .id_table = efx_pci_table, | |
2089 | .probe = efx_pci_probe, | |
2090 | .remove = efx_pci_remove, | |
2091 | }; | |
2092 | ||
2093 | /************************************************************************** | |
2094 | * | |
2095 | * Kernel module interface | |
2096 | * | |
2097 | *************************************************************************/ | |
2098 | ||
2099 | module_param(interrupt_mode, uint, 0444); | |
2100 | MODULE_PARM_DESC(interrupt_mode, | |
2101 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2102 | ||
2103 | static int __init efx_init_module(void) | |
2104 | { | |
2105 | int rc; | |
2106 | ||
2107 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2108 | ||
2109 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2110 | if (rc) | |
2111 | goto err_notifier; | |
2112 | ||
2113 | refill_workqueue = create_workqueue("sfc_refill"); | |
2114 | if (!refill_workqueue) { | |
2115 | rc = -ENOMEM; | |
2116 | goto err_refill; | |
2117 | } | |
1ab00629 SH |
2118 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2119 | if (!reset_workqueue) { | |
2120 | rc = -ENOMEM; | |
2121 | goto err_reset; | |
2122 | } | |
8ceee660 BH |
2123 | |
2124 | rc = pci_register_driver(&efx_pci_driver); | |
2125 | if (rc < 0) | |
2126 | goto err_pci; | |
2127 | ||
2128 | return 0; | |
2129 | ||
2130 | err_pci: | |
1ab00629 SH |
2131 | destroy_workqueue(reset_workqueue); |
2132 | err_reset: | |
8ceee660 BH |
2133 | destroy_workqueue(refill_workqueue); |
2134 | err_refill: | |
2135 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2136 | err_notifier: | |
2137 | return rc; | |
2138 | } | |
2139 | ||
2140 | static void __exit efx_exit_module(void) | |
2141 | { | |
2142 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2143 | ||
2144 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2145 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2146 | destroy_workqueue(refill_workqueue); |
2147 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2148 | ||
2149 | } | |
2150 | ||
2151 | module_init(efx_init_module); | |
2152 | module_exit(efx_exit_module); | |
2153 | ||
2154 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2155 | "Solarflare Communications"); | |
2156 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2157 | MODULE_LICENSE("GPL"); | |
2158 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |