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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "efx.h" |
25 | #include "mdio_10g.h" | |
26 | #include "falcon.h" | |
8ceee660 | 27 | |
c459302d BH |
28 | /************************************************************************** |
29 | * | |
30 | * Type name strings | |
31 | * | |
32 | ************************************************************************** | |
33 | */ | |
34 | ||
35 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
36 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
37 | const char *efx_loopback_mode_names[] = { | |
38 | [LOOPBACK_NONE] = "NONE", | |
39 | [LOOPBACK_GMAC] = "GMAC", | |
40 | [LOOPBACK_XGMII] = "XGMII", | |
41 | [LOOPBACK_XGXS] = "XGXS", | |
42 | [LOOPBACK_XAUI] = "XAUI", | |
43 | [LOOPBACK_GPHY] = "GPHY", | |
44 | [LOOPBACK_PHYXS] = "PHYXS", | |
45 | [LOOPBACK_PCS] = "PCS", | |
46 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
47 | [LOOPBACK_NETWORK] = "NETWORK", | |
48 | }; | |
49 | ||
50 | /* Interrupt mode names (see INT_MODE())) */ | |
51 | const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX; | |
52 | const char *efx_interrupt_mode_names[] = { | |
53 | [EFX_INT_MODE_MSIX] = "MSI-X", | |
54 | [EFX_INT_MODE_MSI] = "MSI", | |
55 | [EFX_INT_MODE_LEGACY] = "legacy", | |
56 | }; | |
57 | ||
58 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; | |
59 | const char *efx_reset_type_names[] = { | |
60 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
61 | [RESET_TYPE_ALL] = "ALL", | |
62 | [RESET_TYPE_WORLD] = "WORLD", | |
63 | [RESET_TYPE_DISABLE] = "DISABLE", | |
64 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
65 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
66 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
67 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
68 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
69 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
70 | }; | |
71 | ||
8ceee660 BH |
72 | #define EFX_MAX_MTU (9 * 1024) |
73 | ||
74 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
75 | * a work item is pushed onto this work queue to retry the allocation later, | |
76 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
77 | * workqueue, there is nothing to be gained in making it per NIC | |
78 | */ | |
79 | static struct workqueue_struct *refill_workqueue; | |
80 | ||
1ab00629 SH |
81 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
82 | * queued onto this work queue. This is not a per-nic work queue, because | |
83 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
84 | */ | |
85 | static struct workqueue_struct *reset_workqueue; | |
86 | ||
8ceee660 BH |
87 | /************************************************************************** |
88 | * | |
89 | * Configurable values | |
90 | * | |
91 | *************************************************************************/ | |
92 | ||
8ceee660 BH |
93 | /* |
94 | * Use separate channels for TX and RX events | |
95 | * | |
28b581ab NT |
96 | * Set this to 1 to use separate channels for TX and RX. It allows us |
97 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 98 | * |
28b581ab | 99 | * This is only used in MSI-X interrupt mode |
8ceee660 | 100 | */ |
28b581ab NT |
101 | static unsigned int separate_tx_channels; |
102 | module_param(separate_tx_channels, uint, 0644); | |
103 | MODULE_PARM_DESC(separate_tx_channels, | |
104 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
105 | |
106 | /* This is the weight assigned to each of the (per-channel) virtual | |
107 | * NAPI devices. | |
108 | */ | |
109 | static int napi_weight = 64; | |
110 | ||
111 | /* This is the time (in jiffies) between invocations of the hardware | |
112 | * monitor, which checks for known hardware bugs and resets the | |
113 | * hardware and driver as necessary. | |
114 | */ | |
115 | unsigned int efx_monitor_interval = 1 * HZ; | |
116 | ||
8ceee660 BH |
117 | /* This controls whether or not the driver will initialise devices |
118 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
119 | * such devices will be initialised with a random locally-generated | |
120 | * MAC address. This allows for loading the sfc_mtd driver to | |
121 | * reprogram the flash, even if the flash contents (including the MAC | |
122 | * address) have previously been erased. | |
123 | */ | |
124 | static unsigned int allow_bad_hwaddr; | |
125 | ||
126 | /* Initial interrupt moderation settings. They can be modified after | |
127 | * module load with ethtool. | |
128 | * | |
129 | * The default for RX should strike a balance between increasing the | |
130 | * round-trip latency and reducing overhead. | |
131 | */ | |
132 | static unsigned int rx_irq_mod_usec = 60; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * This default is chosen to ensure that a 10G link does not go idle | |
138 | * while a TX queue is stopped after it has become full. A queue is | |
139 | * restarted when it drops below half full. The time this takes (assuming | |
140 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
141 | * 512 / 3 * 1.2 = 205 usec. | |
142 | */ | |
143 | static unsigned int tx_irq_mod_usec = 150; | |
144 | ||
145 | /* This is the first interrupt mode to try out of: | |
146 | * 0 => MSI-X | |
147 | * 1 => MSI | |
148 | * 2 => legacy | |
149 | */ | |
150 | static unsigned int interrupt_mode; | |
151 | ||
152 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
153 | * i.e. the number of CPUs among which we may distribute simultaneous | |
154 | * interrupt handling. | |
155 | * | |
156 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
157 | * The default (0) means to assign an interrupt to each package (level II cache) | |
158 | */ | |
159 | static unsigned int rss_cpus; | |
160 | module_param(rss_cpus, uint, 0444); | |
161 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
162 | ||
84ae48fe BH |
163 | static int phy_flash_cfg; |
164 | module_param(phy_flash_cfg, int, 0644); | |
165 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
166 | ||
6fb70fd1 BH |
167 | static unsigned irq_adapt_low_thresh = 10000; |
168 | module_param(irq_adapt_low_thresh, uint, 0644); | |
169 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
170 | "Threshold score for reducing IRQ moderation"); | |
171 | ||
172 | static unsigned irq_adapt_high_thresh = 20000; | |
173 | module_param(irq_adapt_high_thresh, uint, 0644); | |
174 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
175 | "Threshold score for increasing IRQ moderation"); | |
176 | ||
8ceee660 BH |
177 | /************************************************************************** |
178 | * | |
179 | * Utility functions and prototypes | |
180 | * | |
181 | *************************************************************************/ | |
182 | static void efx_remove_channel(struct efx_channel *channel); | |
183 | static void efx_remove_port(struct efx_nic *efx); | |
184 | static void efx_fini_napi(struct efx_nic *efx); | |
185 | static void efx_fini_channels(struct efx_nic *efx); | |
186 | ||
187 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
188 | do { \ | |
332c1ce9 BH |
189 | if ((efx->state == STATE_RUNNING) || \ |
190 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
191 | ASSERT_RTNL(); \ |
192 | } while (0) | |
193 | ||
194 | /************************************************************************** | |
195 | * | |
196 | * Event queue processing | |
197 | * | |
198 | *************************************************************************/ | |
199 | ||
200 | /* Process channel's event queue | |
201 | * | |
202 | * This function is responsible for processing the event queue of a | |
203 | * single channel. The caller must guarantee that this function will | |
204 | * never be concurrently called more than once on the same channel, | |
205 | * though different channels may be being processed concurrently. | |
206 | */ | |
4d566063 | 207 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 208 | { |
42cbe2d7 BH |
209 | struct efx_nic *efx = channel->efx; |
210 | int rx_packets; | |
8ceee660 | 211 | |
42cbe2d7 | 212 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 213 | !channel->enabled)) |
42cbe2d7 | 214 | return 0; |
8ceee660 | 215 | |
42cbe2d7 BH |
216 | rx_packets = falcon_process_eventq(channel, rx_quota); |
217 | if (rx_packets == 0) | |
218 | return 0; | |
8ceee660 BH |
219 | |
220 | /* Deliver last RX packet. */ | |
221 | if (channel->rx_pkt) { | |
222 | __efx_rx_packet(channel, channel->rx_pkt, | |
223 | channel->rx_pkt_csummed); | |
224 | channel->rx_pkt = NULL; | |
225 | } | |
226 | ||
8ceee660 BH |
227 | efx_rx_strategy(channel); |
228 | ||
42cbe2d7 | 229 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 230 | |
42cbe2d7 | 231 | return rx_packets; |
8ceee660 BH |
232 | } |
233 | ||
234 | /* Mark channel as finished processing | |
235 | * | |
236 | * Note that since we will not receive further interrupts for this | |
237 | * channel before we finish processing and call the eventq_read_ack() | |
238 | * method, there is no need to use the interrupt hold-off timers. | |
239 | */ | |
240 | static inline void efx_channel_processed(struct efx_channel *channel) | |
241 | { | |
5b9e207c BH |
242 | /* The interrupt handler for this channel may set work_pending |
243 | * as soon as we acknowledge the events we've seen. Make sure | |
244 | * it's cleared before then. */ | |
dc8cfa55 | 245 | channel->work_pending = false; |
5b9e207c BH |
246 | smp_wmb(); |
247 | ||
8ceee660 BH |
248 | falcon_eventq_read_ack(channel); |
249 | } | |
250 | ||
251 | /* NAPI poll handler | |
252 | * | |
253 | * NAPI guarantees serialisation of polls of the same device, which | |
254 | * provides the guarantee required by efx_process_channel(). | |
255 | */ | |
256 | static int efx_poll(struct napi_struct *napi, int budget) | |
257 | { | |
258 | struct efx_channel *channel = | |
259 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
260 | int rx_packets; |
261 | ||
262 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
263 | channel->channel, raw_smp_processor_id()); | |
264 | ||
42cbe2d7 | 265 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
266 | |
267 | if (rx_packets < budget) { | |
6fb70fd1 BH |
268 | struct efx_nic *efx = channel->efx; |
269 | ||
270 | if (channel->used_flags & EFX_USED_BY_RX && | |
271 | efx->irq_rx_adaptive && | |
272 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
273 | if (unlikely(channel->irq_mod_score < |
274 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
275 | if (channel->irq_moderation > 1) { |
276 | channel->irq_moderation -= 1; | |
277 | falcon_set_int_moderation(channel); | |
278 | } | |
6fb70fd1 BH |
279 | } else if (unlikely(channel->irq_mod_score > |
280 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
281 | if (channel->irq_moderation < |
282 | efx->irq_rx_moderation) { | |
283 | channel->irq_moderation += 1; | |
284 | falcon_set_int_moderation(channel); | |
285 | } | |
6fb70fd1 | 286 | } |
6fb70fd1 BH |
287 | channel->irq_count = 0; |
288 | channel->irq_mod_score = 0; | |
289 | } | |
290 | ||
8ceee660 | 291 | /* There is no race here; although napi_disable() will |
288379f0 | 292 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
293 | * since efx_channel_processed() will have no effect if |
294 | * interrupts have already been disabled. | |
295 | */ | |
288379f0 | 296 | napi_complete(napi); |
8ceee660 BH |
297 | efx_channel_processed(channel); |
298 | } | |
299 | ||
300 | return rx_packets; | |
301 | } | |
302 | ||
303 | /* Process the eventq of the specified channel immediately on this CPU | |
304 | * | |
305 | * Disable hardware generated interrupts, wait for any existing | |
306 | * processing to finish, then directly poll (and ack ) the eventq. | |
307 | * Finally reenable NAPI and interrupts. | |
308 | * | |
309 | * Since we are touching interrupts the caller should hold the suspend lock | |
310 | */ | |
311 | void efx_process_channel_now(struct efx_channel *channel) | |
312 | { | |
313 | struct efx_nic *efx = channel->efx; | |
314 | ||
315 | BUG_ON(!channel->used_flags); | |
316 | BUG_ON(!channel->enabled); | |
317 | ||
318 | /* Disable interrupts and wait for ISRs to complete */ | |
319 | falcon_disable_interrupts(efx); | |
320 | if (efx->legacy_irq) | |
321 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 322 | if (channel->irq) |
8ceee660 BH |
323 | synchronize_irq(channel->irq); |
324 | ||
325 | /* Wait for any NAPI processing to complete */ | |
326 | napi_disable(&channel->napi_str); | |
327 | ||
328 | /* Poll the channel */ | |
3ffeabdd | 329 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
330 | |
331 | /* Ack the eventq. This may cause an interrupt to be generated | |
332 | * when they are reenabled */ | |
333 | efx_channel_processed(channel); | |
334 | ||
335 | napi_enable(&channel->napi_str); | |
336 | falcon_enable_interrupts(efx); | |
337 | } | |
338 | ||
339 | /* Create event queue | |
340 | * Event queue memory allocations are done only once. If the channel | |
341 | * is reset, the memory buffer will be reused; this guards against | |
342 | * errors during channel reset and also simplifies interrupt handling. | |
343 | */ | |
344 | static int efx_probe_eventq(struct efx_channel *channel) | |
345 | { | |
346 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
347 | ||
348 | return falcon_probe_eventq(channel); | |
349 | } | |
350 | ||
351 | /* Prepare channel's event queue */ | |
bc3c90a2 | 352 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
353 | { |
354 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
355 | ||
356 | channel->eventq_read_ptr = 0; | |
357 | ||
bc3c90a2 | 358 | falcon_init_eventq(channel); |
8ceee660 BH |
359 | } |
360 | ||
361 | static void efx_fini_eventq(struct efx_channel *channel) | |
362 | { | |
363 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
364 | ||
365 | falcon_fini_eventq(channel); | |
366 | } | |
367 | ||
368 | static void efx_remove_eventq(struct efx_channel *channel) | |
369 | { | |
370 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
371 | ||
372 | falcon_remove_eventq(channel); | |
373 | } | |
374 | ||
375 | /************************************************************************** | |
376 | * | |
377 | * Channel handling | |
378 | * | |
379 | *************************************************************************/ | |
380 | ||
8ceee660 BH |
381 | static int efx_probe_channel(struct efx_channel *channel) |
382 | { | |
383 | struct efx_tx_queue *tx_queue; | |
384 | struct efx_rx_queue *rx_queue; | |
385 | int rc; | |
386 | ||
387 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
388 | ||
389 | rc = efx_probe_eventq(channel); | |
390 | if (rc) | |
391 | goto fail1; | |
392 | ||
393 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
394 | rc = efx_probe_tx_queue(tx_queue); | |
395 | if (rc) | |
396 | goto fail2; | |
397 | } | |
398 | ||
399 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
400 | rc = efx_probe_rx_queue(rx_queue); | |
401 | if (rc) | |
402 | goto fail3; | |
403 | } | |
404 | ||
405 | channel->n_rx_frm_trunc = 0; | |
406 | ||
407 | return 0; | |
408 | ||
409 | fail3: | |
410 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
411 | efx_remove_rx_queue(rx_queue); | |
412 | fail2: | |
413 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
414 | efx_remove_tx_queue(tx_queue); | |
415 | fail1: | |
416 | return rc; | |
417 | } | |
418 | ||
419 | ||
56536e9c BH |
420 | static void efx_set_channel_names(struct efx_nic *efx) |
421 | { | |
422 | struct efx_channel *channel; | |
423 | const char *type = ""; | |
424 | int number; | |
425 | ||
426 | efx_for_each_channel(channel, efx) { | |
427 | number = channel->channel; | |
428 | if (efx->n_channels > efx->n_rx_queues) { | |
429 | if (channel->channel < efx->n_rx_queues) { | |
430 | type = "-rx"; | |
431 | } else { | |
432 | type = "-tx"; | |
433 | number -= efx->n_rx_queues; | |
434 | } | |
435 | } | |
436 | snprintf(channel->name, sizeof(channel->name), | |
437 | "%s%s-%d", efx->name, type, number); | |
438 | } | |
439 | } | |
440 | ||
8ceee660 BH |
441 | /* Channels are shutdown and reinitialised whilst the NIC is running |
442 | * to propagate configuration changes (mtu, checksum offload), or | |
443 | * to clear hardware error conditions | |
444 | */ | |
bc3c90a2 | 445 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
446 | { |
447 | struct efx_tx_queue *tx_queue; | |
448 | struct efx_rx_queue *rx_queue; | |
449 | struct efx_channel *channel; | |
8ceee660 | 450 | |
f7f13b0b BH |
451 | /* Calculate the rx buffer allocation parameters required to |
452 | * support the current MTU, including padding for header | |
453 | * alignment and overruns. | |
454 | */ | |
455 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
456 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
457 | efx->type->rx_buffer_padding); | |
458 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
459 | |
460 | /* Initialise the channels */ | |
461 | efx_for_each_channel(channel, efx) { | |
462 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
463 | ||
bc3c90a2 | 464 | efx_init_eventq(channel); |
8ceee660 | 465 | |
bc3c90a2 BH |
466 | efx_for_each_channel_tx_queue(tx_queue, channel) |
467 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
468 | |
469 | /* The rx buffer allocation strategy is MTU dependent */ | |
470 | efx_rx_strategy(channel); | |
471 | ||
bc3c90a2 BH |
472 | efx_for_each_channel_rx_queue(rx_queue, channel) |
473 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
474 | |
475 | WARN_ON(channel->rx_pkt != NULL); | |
476 | efx_rx_strategy(channel); | |
477 | } | |
8ceee660 BH |
478 | } |
479 | ||
480 | /* This enables event queue processing and packet transmission. | |
481 | * | |
482 | * Note that this function is not allowed to fail, since that would | |
483 | * introduce too much complexity into the suspend/resume path. | |
484 | */ | |
485 | static void efx_start_channel(struct efx_channel *channel) | |
486 | { | |
487 | struct efx_rx_queue *rx_queue; | |
488 | ||
489 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
490 | ||
5b9e207c BH |
491 | /* The interrupt handler for this channel may set work_pending |
492 | * as soon as we enable it. Make sure it's cleared before | |
493 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
494 | channel->work_pending = false; |
495 | channel->enabled = true; | |
5b9e207c | 496 | smp_wmb(); |
8ceee660 BH |
497 | |
498 | napi_enable(&channel->napi_str); | |
499 | ||
500 | /* Load up RX descriptors */ | |
501 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
502 | efx_fast_push_rx_descriptors(rx_queue); | |
503 | } | |
504 | ||
505 | /* This disables event queue processing and packet transmission. | |
506 | * This function does not guarantee that all queue processing | |
507 | * (e.g. RX refill) is complete. | |
508 | */ | |
509 | static void efx_stop_channel(struct efx_channel *channel) | |
510 | { | |
511 | struct efx_rx_queue *rx_queue; | |
512 | ||
513 | if (!channel->enabled) | |
514 | return; | |
515 | ||
516 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
517 | ||
dc8cfa55 | 518 | channel->enabled = false; |
8ceee660 BH |
519 | napi_disable(&channel->napi_str); |
520 | ||
521 | /* Ensure that any worker threads have exited or will be no-ops */ | |
522 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
523 | spin_lock_bh(&rx_queue->add_lock); | |
524 | spin_unlock_bh(&rx_queue->add_lock); | |
525 | } | |
526 | } | |
527 | ||
528 | static void efx_fini_channels(struct efx_nic *efx) | |
529 | { | |
530 | struct efx_channel *channel; | |
531 | struct efx_tx_queue *tx_queue; | |
532 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 533 | int rc; |
8ceee660 BH |
534 | |
535 | EFX_ASSERT_RESET_SERIALISED(efx); | |
536 | BUG_ON(efx->port_enabled); | |
537 | ||
6bc5d3a9 BH |
538 | rc = falcon_flush_queues(efx); |
539 | if (rc) | |
540 | EFX_ERR(efx, "failed to flush queues\n"); | |
541 | else | |
542 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
543 | ||
8ceee660 BH |
544 | efx_for_each_channel(channel, efx) { |
545 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
546 | ||
547 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
548 | efx_fini_rx_queue(rx_queue); | |
549 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
550 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
551 | efx_fini_eventq(channel); |
552 | } | |
553 | } | |
554 | ||
555 | static void efx_remove_channel(struct efx_channel *channel) | |
556 | { | |
557 | struct efx_tx_queue *tx_queue; | |
558 | struct efx_rx_queue *rx_queue; | |
559 | ||
560 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
561 | ||
562 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
563 | efx_remove_rx_queue(rx_queue); | |
564 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
565 | efx_remove_tx_queue(tx_queue); | |
566 | efx_remove_eventq(channel); | |
567 | ||
568 | channel->used_flags = 0; | |
569 | } | |
570 | ||
571 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
572 | { | |
573 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
574 | } | |
575 | ||
576 | /************************************************************************** | |
577 | * | |
578 | * Port handling | |
579 | * | |
580 | **************************************************************************/ | |
581 | ||
582 | /* This ensures that the kernel is kept informed (via | |
583 | * netif_carrier_on/off) of the link status, and also maintains the | |
584 | * link status's stop on the port's TX queue. | |
585 | */ | |
586 | static void efx_link_status_changed(struct efx_nic *efx) | |
587 | { | |
eb50c0d6 BH |
588 | struct efx_link_state *link_state = &efx->link_state; |
589 | ||
8ceee660 BH |
590 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
591 | * that no events are triggered between unregister_netdev() and the | |
592 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
593 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
594 | if (!netif_running(efx->net_dev)) | |
595 | return; | |
596 | ||
8c8661e4 BH |
597 | if (efx->port_inhibited) { |
598 | netif_carrier_off(efx->net_dev); | |
599 | return; | |
600 | } | |
601 | ||
eb50c0d6 | 602 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
603 | efx->n_link_state_changes++; |
604 | ||
eb50c0d6 | 605 | if (link_state->up) |
8ceee660 BH |
606 | netif_carrier_on(efx->net_dev); |
607 | else | |
608 | netif_carrier_off(efx->net_dev); | |
609 | } | |
610 | ||
611 | /* Status message for kernel log */ | |
eb50c0d6 | 612 | if (link_state->up) { |
f31a45d2 | 613 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
eb50c0d6 | 614 | link_state->speed, link_state->fd ? "full" : "half", |
8ceee660 BH |
615 | efx->net_dev->mtu, |
616 | (efx->promiscuous ? " [PROMISC]" : "")); | |
617 | } else { | |
618 | EFX_INFO(efx, "link down\n"); | |
619 | } | |
620 | ||
621 | } | |
622 | ||
115122af BH |
623 | static void efx_fini_port(struct efx_nic *efx); |
624 | ||
8ceee660 BH |
625 | /* This call reinitialises the MAC to pick up new PHY settings. The |
626 | * caller must hold the mac_lock */ | |
8c8661e4 | 627 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
628 | { |
629 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
630 | ||
631 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
632 | raw_smp_processor_id()); | |
633 | ||
a816f75a BH |
634 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
635 | if (efx_dev_registered(efx)) { | |
636 | netif_addr_lock_bh(efx->net_dev); | |
637 | netif_addr_unlock_bh(efx->net_dev); | |
638 | } | |
639 | ||
55edc6e6 | 640 | falcon_stop_nic_stats(efx); |
177dfcd8 BH |
641 | falcon_deconfigure_mac_wrapper(efx); |
642 | ||
643 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
644 | if (LOOPBACK_INTERNAL(efx)) | |
645 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
646 | else | |
647 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
648 | efx->phy_op->reconfigure(efx); | |
649 | ||
650 | if (falcon_switch_mac(efx)) | |
651 | goto fail; | |
652 | ||
653 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 654 | |
55edc6e6 BH |
655 | falcon_start_nic_stats(efx); |
656 | ||
8ceee660 BH |
657 | /* Inform kernel of loss/gain of carrier */ |
658 | efx_link_status_changed(efx); | |
177dfcd8 BH |
659 | return; |
660 | ||
661 | fail: | |
662 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
115122af BH |
663 | efx->port_enabled = false; |
664 | efx_fini_port(efx); | |
8ceee660 BH |
665 | } |
666 | ||
667 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
668 | * disabled. */ | |
669 | void efx_reconfigure_port(struct efx_nic *efx) | |
670 | { | |
671 | EFX_ASSERT_RESET_SERIALISED(efx); | |
672 | ||
673 | mutex_lock(&efx->mac_lock); | |
674 | __efx_reconfigure_port(efx); | |
675 | mutex_unlock(&efx->mac_lock); | |
676 | } | |
677 | ||
678 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
679 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
680 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 681 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 682 | { |
766ca0fa | 683 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
684 | |
685 | mutex_lock(&efx->mac_lock); | |
686 | if (efx->port_enabled) | |
687 | __efx_reconfigure_port(efx); | |
688 | mutex_unlock(&efx->mac_lock); | |
689 | } | |
690 | ||
766ca0fa BH |
691 | static void efx_mac_work(struct work_struct *data) |
692 | { | |
693 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
694 | ||
695 | mutex_lock(&efx->mac_lock); | |
766ca0fa BH |
696 | mutex_unlock(&efx->mac_lock); |
697 | } | |
698 | ||
8ceee660 BH |
699 | static int efx_probe_port(struct efx_nic *efx) |
700 | { | |
701 | int rc; | |
702 | ||
703 | EFX_LOG(efx, "create port\n"); | |
704 | ||
705 | /* Connect up MAC/PHY operations table and read MAC address */ | |
706 | rc = falcon_probe_port(efx); | |
707 | if (rc) | |
708 | goto err; | |
709 | ||
84ae48fe BH |
710 | if (phy_flash_cfg) |
711 | efx->phy_mode = PHY_MODE_SPECIAL; | |
712 | ||
8ceee660 BH |
713 | /* Sanity check MAC address */ |
714 | if (is_valid_ether_addr(efx->mac_address)) { | |
715 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
716 | } else { | |
e174961c JB |
717 | EFX_ERR(efx, "invalid MAC address %pM\n", |
718 | efx->mac_address); | |
8ceee660 BH |
719 | if (!allow_bad_hwaddr) { |
720 | rc = -EINVAL; | |
721 | goto err; | |
722 | } | |
723 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
724 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
725 | efx->net_dev->dev_addr); | |
8ceee660 BH |
726 | } |
727 | ||
728 | return 0; | |
729 | ||
730 | err: | |
731 | efx_remove_port(efx); | |
732 | return rc; | |
733 | } | |
734 | ||
735 | static int efx_init_port(struct efx_nic *efx) | |
736 | { | |
737 | int rc; | |
738 | ||
739 | EFX_LOG(efx, "init port\n"); | |
740 | ||
1dfc5cea BH |
741 | mutex_lock(&efx->mac_lock); |
742 | ||
177dfcd8 | 743 | rc = efx->phy_op->init(efx); |
8ceee660 | 744 | if (rc) |
1dfc5cea | 745 | goto fail1; |
4b988280 | 746 | efx->phy_op->reconfigure(efx); |
177dfcd8 | 747 | rc = falcon_switch_mac(efx); |
177dfcd8 | 748 | if (rc) |
1dfc5cea | 749 | goto fail2; |
177dfcd8 | 750 | efx->mac_op->reconfigure(efx); |
8ceee660 | 751 | |
dc8cfa55 | 752 | efx->port_initialized = true; |
1dfc5cea BH |
753 | |
754 | mutex_unlock(&efx->mac_lock); | |
8ceee660 | 755 | return 0; |
177dfcd8 | 756 | |
1dfc5cea | 757 | fail2: |
177dfcd8 | 758 | efx->phy_op->fini(efx); |
1dfc5cea BH |
759 | fail1: |
760 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 761 | return rc; |
8ceee660 BH |
762 | } |
763 | ||
764 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
765 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 766 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
767 | static void efx_start_port(struct efx_nic *efx) |
768 | { | |
769 | EFX_LOG(efx, "start port\n"); | |
770 | BUG_ON(efx->port_enabled); | |
771 | ||
772 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 773 | efx->port_enabled = true; |
8ceee660 BH |
774 | __efx_reconfigure_port(efx); |
775 | mutex_unlock(&efx->mac_lock); | |
776 | } | |
777 | ||
766ca0fa BH |
778 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
779 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
780 | * and efx_mac_work may still be scheduled via NAPI processing until | |
781 | * efx_flush_all() is called */ | |
8ceee660 BH |
782 | static void efx_stop_port(struct efx_nic *efx) |
783 | { | |
784 | EFX_LOG(efx, "stop port\n"); | |
785 | ||
786 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 787 | efx->port_enabled = false; |
8ceee660 BH |
788 | mutex_unlock(&efx->mac_lock); |
789 | ||
790 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 791 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
792 | netif_addr_lock_bh(efx->net_dev); |
793 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
794 | } |
795 | } | |
796 | ||
797 | static void efx_fini_port(struct efx_nic *efx) | |
798 | { | |
799 | EFX_LOG(efx, "shut down port\n"); | |
800 | ||
801 | if (!efx->port_initialized) | |
802 | return; | |
803 | ||
177dfcd8 | 804 | efx->phy_op->fini(efx); |
dc8cfa55 | 805 | efx->port_initialized = false; |
8ceee660 | 806 | |
eb50c0d6 | 807 | efx->link_state.up = false; |
8ceee660 BH |
808 | efx_link_status_changed(efx); |
809 | } | |
810 | ||
811 | static void efx_remove_port(struct efx_nic *efx) | |
812 | { | |
813 | EFX_LOG(efx, "destroying port\n"); | |
814 | ||
815 | falcon_remove_port(efx); | |
816 | } | |
817 | ||
818 | /************************************************************************** | |
819 | * | |
820 | * NIC handling | |
821 | * | |
822 | **************************************************************************/ | |
823 | ||
824 | /* This configures the PCI device to enable I/O and DMA. */ | |
825 | static int efx_init_io(struct efx_nic *efx) | |
826 | { | |
827 | struct pci_dev *pci_dev = efx->pci_dev; | |
828 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
829 | int rc; | |
830 | ||
831 | EFX_LOG(efx, "initialising I/O\n"); | |
832 | ||
833 | rc = pci_enable_device(pci_dev); | |
834 | if (rc) { | |
835 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
836 | goto fail1; | |
837 | } | |
838 | ||
839 | pci_set_master(pci_dev); | |
840 | ||
841 | /* Set the PCI DMA mask. Try all possibilities from our | |
842 | * genuine mask down to 32 bits, because some architectures | |
843 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
844 | * masks event though they reject 46 bit masks. | |
845 | */ | |
846 | while (dma_mask > 0x7fffffffUL) { | |
847 | if (pci_dma_supported(pci_dev, dma_mask) && | |
848 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
849 | break; | |
850 | dma_mask >>= 1; | |
851 | } | |
852 | if (rc) { | |
853 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
854 | goto fail2; | |
855 | } | |
856 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
857 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
858 | if (rc) { | |
859 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
860 | * fail with a mask that pci_set_dma_mask() accepted, | |
861 | * but just in case... | |
862 | */ | |
863 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
864 | goto fail2; | |
865 | } | |
866 | ||
dc803df8 BH |
867 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
868 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 BH |
869 | if (rc) { |
870 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
871 | rc = -EIO; | |
872 | goto fail3; | |
873 | } | |
874 | efx->membase = ioremap_nocache(efx->membase_phys, | |
875 | efx->type->mem_map_size); | |
876 | if (!efx->membase) { | |
dc803df8 | 877 | EFX_ERR(efx, "could not map memory BAR at %llx+%x\n", |
086ea356 | 878 | (unsigned long long)efx->membase_phys, |
8ceee660 BH |
879 | efx->type->mem_map_size); |
880 | rc = -ENOMEM; | |
881 | goto fail4; | |
882 | } | |
dc803df8 BH |
883 | EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n", |
884 | (unsigned long long)efx->membase_phys, | |
086ea356 | 885 | efx->type->mem_map_size, efx->membase); |
8ceee660 BH |
886 | |
887 | return 0; | |
888 | ||
889 | fail4: | |
dc803df8 | 890 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 891 | fail3: |
2c118e0f | 892 | efx->membase_phys = 0; |
8ceee660 BH |
893 | fail2: |
894 | pci_disable_device(efx->pci_dev); | |
895 | fail1: | |
896 | return rc; | |
897 | } | |
898 | ||
899 | static void efx_fini_io(struct efx_nic *efx) | |
900 | { | |
901 | EFX_LOG(efx, "shutting down I/O\n"); | |
902 | ||
903 | if (efx->membase) { | |
904 | iounmap(efx->membase); | |
905 | efx->membase = NULL; | |
906 | } | |
907 | ||
908 | if (efx->membase_phys) { | |
dc803df8 | 909 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 910 | efx->membase_phys = 0; |
8ceee660 BH |
911 | } |
912 | ||
913 | pci_disable_device(efx->pci_dev); | |
914 | } | |
915 | ||
46123d04 BH |
916 | /* Get number of RX queues wanted. Return number of online CPU |
917 | * packages in the expectation that an IRQ balancer will spread | |
918 | * interrupts across them. */ | |
919 | static int efx_wanted_rx_queues(void) | |
920 | { | |
2f8975fb | 921 | cpumask_var_t core_mask; |
46123d04 BH |
922 | int count; |
923 | int cpu; | |
924 | ||
79f55997 | 925 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 926 | printk(KERN_WARNING |
3977d033 | 927 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
928 | return 1; |
929 | } | |
930 | ||
46123d04 BH |
931 | count = 0; |
932 | for_each_online_cpu(cpu) { | |
2f8975fb | 933 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 934 | ++count; |
2f8975fb | 935 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 936 | topology_core_cpumask(cpu)); |
46123d04 BH |
937 | } |
938 | } | |
939 | ||
2f8975fb | 940 | free_cpumask_var(core_mask); |
46123d04 BH |
941 | return count; |
942 | } | |
943 | ||
944 | /* Probe the number and type of interrupts we are able to obtain, and | |
945 | * the resulting numbers of channels and RX queues. | |
946 | */ | |
8ceee660 BH |
947 | static void efx_probe_interrupts(struct efx_nic *efx) |
948 | { | |
46123d04 BH |
949 | int max_channels = |
950 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
951 | int rc, i; |
952 | ||
953 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
954 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
955 | int wanted_ints; | |
28b581ab | 956 | int rx_queues; |
aa6ef27e | 957 | |
46123d04 BH |
958 | /* We want one RX queue and interrupt per CPU package |
959 | * (or as specified by the rss_cpus module parameter). | |
960 | * We will need one channel per interrupt. | |
961 | */ | |
28b581ab NT |
962 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
963 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
964 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 965 | |
28b581ab | 966 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 967 | xentries[i].entry = i; |
28b581ab | 968 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 969 | if (rc > 0) { |
28b581ab NT |
970 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
971 | " available (%d < %d).\n", rc, wanted_ints); | |
972 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
973 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
974 | wanted_ints = rc; | |
8ceee660 | 975 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 976 | wanted_ints); |
8ceee660 BH |
977 | } |
978 | ||
979 | if (rc == 0) { | |
28b581ab NT |
980 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
981 | efx->n_channels = wanted_ints; | |
982 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 983 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
984 | } else { |
985 | /* Fall back to single channel MSI */ | |
986 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
987 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
988 | } | |
989 | } | |
990 | ||
991 | /* Try single interrupt MSI */ | |
992 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 993 | efx->n_rx_queues = 1; |
28b581ab | 994 | efx->n_channels = 1; |
8ceee660 BH |
995 | rc = pci_enable_msi(efx->pci_dev); |
996 | if (rc == 0) { | |
997 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
998 | } else { |
999 | EFX_ERR(efx, "could not enable MSI\n"); | |
1000 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
1001 | } | |
1002 | } | |
1003 | ||
1004 | /* Assume legacy interrupts */ | |
1005 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 1006 | efx->n_rx_queues = 1; |
28b581ab | 1007 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
1008 | efx->legacy_irq = efx->pci_dev->irq; |
1009 | } | |
1010 | } | |
1011 | ||
1012 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1013 | { | |
1014 | struct efx_channel *channel; | |
1015 | ||
1016 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1017 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1018 | channel->irq = 0; |
1019 | pci_disable_msi(efx->pci_dev); | |
1020 | pci_disable_msix(efx->pci_dev); | |
1021 | ||
1022 | /* Remove legacy interrupt */ | |
1023 | efx->legacy_irq = 0; | |
1024 | } | |
1025 | ||
8831da7b | 1026 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
1027 | { |
1028 | struct efx_tx_queue *tx_queue; | |
1029 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 1030 | |
60ac1065 | 1031 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
1032 | if (separate_tx_channels) |
1033 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
1034 | else |
1035 | tx_queue->channel = &efx->channel[0]; | |
1036 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
1037 | } | |
8ceee660 | 1038 | |
8831da7b BH |
1039 | efx_for_each_rx_queue(rx_queue, efx) { |
1040 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
1041 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
1042 | } |
1043 | } | |
1044 | ||
1045 | static int efx_probe_nic(struct efx_nic *efx) | |
1046 | { | |
1047 | int rc; | |
1048 | ||
1049 | EFX_LOG(efx, "creating NIC\n"); | |
1050 | ||
1051 | /* Carry out hardware-type specific initialisation */ | |
1052 | rc = falcon_probe_nic(efx); | |
1053 | if (rc) | |
1054 | return rc; | |
1055 | ||
1056 | /* Determine the number of channels and RX queues by trying to hook | |
1057 | * in MSI-X interrupts. */ | |
1058 | efx_probe_interrupts(efx); | |
1059 | ||
8831da7b | 1060 | efx_set_channels(efx); |
8ceee660 BH |
1061 | |
1062 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1063 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1064 | |
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static void efx_remove_nic(struct efx_nic *efx) | |
1069 | { | |
1070 | EFX_LOG(efx, "destroying NIC\n"); | |
1071 | ||
1072 | efx_remove_interrupts(efx); | |
1073 | falcon_remove_nic(efx); | |
1074 | } | |
1075 | ||
1076 | /************************************************************************** | |
1077 | * | |
1078 | * NIC startup/shutdown | |
1079 | * | |
1080 | *************************************************************************/ | |
1081 | ||
1082 | static int efx_probe_all(struct efx_nic *efx) | |
1083 | { | |
1084 | struct efx_channel *channel; | |
1085 | int rc; | |
1086 | ||
1087 | /* Create NIC */ | |
1088 | rc = efx_probe_nic(efx); | |
1089 | if (rc) { | |
1090 | EFX_ERR(efx, "failed to create NIC\n"); | |
1091 | goto fail1; | |
1092 | } | |
1093 | ||
1094 | /* Create port */ | |
1095 | rc = efx_probe_port(efx); | |
1096 | if (rc) { | |
1097 | EFX_ERR(efx, "failed to create port\n"); | |
1098 | goto fail2; | |
1099 | } | |
1100 | ||
1101 | /* Create channels */ | |
1102 | efx_for_each_channel(channel, efx) { | |
1103 | rc = efx_probe_channel(channel); | |
1104 | if (rc) { | |
1105 | EFX_ERR(efx, "failed to create channel %d\n", | |
1106 | channel->channel); | |
1107 | goto fail3; | |
1108 | } | |
1109 | } | |
56536e9c | 1110 | efx_set_channel_names(efx); |
8ceee660 BH |
1111 | |
1112 | return 0; | |
1113 | ||
1114 | fail3: | |
1115 | efx_for_each_channel(channel, efx) | |
1116 | efx_remove_channel(channel); | |
1117 | efx_remove_port(efx); | |
1118 | fail2: | |
1119 | efx_remove_nic(efx); | |
1120 | fail1: | |
1121 | return rc; | |
1122 | } | |
1123 | ||
1124 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1125 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1126 | * and ensures that the port is scheduled to be reconfigured. | |
1127 | * This function is safe to call multiple times when the NIC is in any | |
1128 | * state. */ | |
1129 | static void efx_start_all(struct efx_nic *efx) | |
1130 | { | |
1131 | struct efx_channel *channel; | |
1132 | ||
1133 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1134 | ||
1135 | /* Check that it is appropriate to restart the interface. All | |
1136 | * of these flags are safe to read under just the rtnl lock */ | |
1137 | if (efx->port_enabled) | |
1138 | return; | |
1139 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1140 | return; | |
55668611 | 1141 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1142 | return; |
1143 | ||
1144 | /* Mark the port as enabled so port reconfigurations can start, then | |
1145 | * restart the transmit interface early so the watchdog timer stops */ | |
1146 | efx_start_port(efx); | |
dacccc74 SH |
1147 | if (efx_dev_registered(efx)) |
1148 | efx_wake_queue(efx); | |
8ceee660 BH |
1149 | |
1150 | efx_for_each_channel(channel, efx) | |
1151 | efx_start_channel(channel); | |
1152 | ||
1153 | falcon_enable_interrupts(efx); | |
1154 | ||
1155 | /* Start hardware monitor if we're in RUNNING */ | |
1156 | if (efx->state == STATE_RUNNING) | |
1157 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1158 | efx_monitor_interval); | |
55edc6e6 BH |
1159 | |
1160 | falcon_start_nic_stats(efx); | |
8ceee660 BH |
1161 | } |
1162 | ||
1163 | /* Flush all delayed work. Should only be called when no more delayed work | |
1164 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1165 | * since we're holding the rtnl_lock at this point. */ | |
1166 | static void efx_flush_all(struct efx_nic *efx) | |
1167 | { | |
1168 | struct efx_rx_queue *rx_queue; | |
1169 | ||
1170 | /* Make sure the hardware monitor is stopped */ | |
1171 | cancel_delayed_work_sync(&efx->monitor_work); | |
1172 | ||
1173 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1174 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1175 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1176 | |
1177 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1178 | cancel_work_sync(&efx->mac_work); |
1179 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1180 | |
1181 | } | |
1182 | ||
1183 | /* Quiesce hardware and software without bringing the link down. | |
1184 | * Safe to call multiple times, when the nic and interface is in any | |
1185 | * state. The caller is guaranteed to subsequently be in a position | |
1186 | * to modify any hardware and software state they see fit without | |
1187 | * taking locks. */ | |
1188 | static void efx_stop_all(struct efx_nic *efx) | |
1189 | { | |
1190 | struct efx_channel *channel; | |
1191 | ||
1192 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1193 | ||
1194 | /* port_enabled can be read safely under the rtnl lock */ | |
1195 | if (!efx->port_enabled) | |
1196 | return; | |
1197 | ||
55edc6e6 BH |
1198 | falcon_stop_nic_stats(efx); |
1199 | ||
8ceee660 BH |
1200 | /* Disable interrupts and wait for ISR to complete */ |
1201 | falcon_disable_interrupts(efx); | |
1202 | if (efx->legacy_irq) | |
1203 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1204 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1205 | if (channel->irq) |
1206 | synchronize_irq(channel->irq); | |
b3475645 | 1207 | } |
8ceee660 BH |
1208 | |
1209 | /* Stop all NAPI processing and synchronous rx refills */ | |
1210 | efx_for_each_channel(channel, efx) | |
1211 | efx_stop_channel(channel); | |
1212 | ||
1213 | /* Stop all asynchronous port reconfigurations. Since all | |
1214 | * event processing has already been stopped, there is no | |
1215 | * window to loose phy events */ | |
1216 | efx_stop_port(efx); | |
1217 | ||
766ca0fa | 1218 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1219 | efx_flush_all(efx); |
1220 | ||
1221 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1222 | * flushes will complete in a timely fashion. */ | |
5c8af3b9 BH |
1223 | falcon_deconfigure_mac_wrapper(efx); |
1224 | msleep(10); /* Let the Rx FIFO drain */ | |
8ceee660 BH |
1225 | falcon_drain_tx_fifo(efx); |
1226 | ||
1227 | /* Stop the kernel transmit interface late, so the watchdog | |
1228 | * timer isn't ticking over the flush */ | |
55668611 | 1229 | if (efx_dev_registered(efx)) { |
dacccc74 | 1230 | efx_stop_queue(efx); |
8ceee660 BH |
1231 | netif_tx_lock_bh(efx->net_dev); |
1232 | netif_tx_unlock_bh(efx->net_dev); | |
1233 | } | |
1234 | } | |
1235 | ||
1236 | static void efx_remove_all(struct efx_nic *efx) | |
1237 | { | |
1238 | struct efx_channel *channel; | |
1239 | ||
1240 | efx_for_each_channel(channel, efx) | |
1241 | efx_remove_channel(channel); | |
1242 | efx_remove_port(efx); | |
1243 | efx_remove_nic(efx); | |
1244 | } | |
1245 | ||
8ceee660 BH |
1246 | /************************************************************************** |
1247 | * | |
1248 | * Interrupt moderation | |
1249 | * | |
1250 | **************************************************************************/ | |
1251 | ||
0d86ebd8 BH |
1252 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1253 | { | |
1254 | if (usecs <= 0) | |
1255 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1256 | if (usecs < resolution) | |
1257 | return 1; /* never round down to 0 */ | |
1258 | return usecs / resolution; | |
1259 | } | |
1260 | ||
8ceee660 | 1261 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1262 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1263 | bool rx_adaptive) | |
8ceee660 BH |
1264 | { |
1265 | struct efx_tx_queue *tx_queue; | |
1266 | struct efx_rx_queue *rx_queue; | |
0d86ebd8 BH |
1267 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, FALCON_IRQ_MOD_RESOLUTION); |
1268 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, FALCON_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1269 | |
1270 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1271 | ||
1272 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1273 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1274 | |
6fb70fd1 | 1275 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1276 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1277 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1278 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1279 | } |
1280 | ||
1281 | /************************************************************************** | |
1282 | * | |
1283 | * Hardware monitor | |
1284 | * | |
1285 | **************************************************************************/ | |
1286 | ||
1287 | /* Run periodically off the general workqueue. Serialised against | |
1288 | * efx_reconfigure_port via the mac_lock */ | |
1289 | static void efx_monitor(struct work_struct *data) | |
1290 | { | |
1291 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1292 | monitor_work.work); | |
8ceee660 BH |
1293 | |
1294 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1295 | raw_smp_processor_id()); | |
1296 | ||
8ceee660 BH |
1297 | /* If the mac_lock is already held then it is likely a port |
1298 | * reconfiguration is already in place, which will likely do | |
1299 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1300 | if (!mutex_trylock(&efx->mac_lock)) |
1301 | goto out_requeue; | |
1302 | if (!efx->port_enabled) | |
1303 | goto out_unlock; | |
fe75820b | 1304 | falcon_monitor(efx); |
8ceee660 | 1305 | |
766ca0fa | 1306 | out_unlock: |
8ceee660 | 1307 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1308 | out_requeue: |
8ceee660 BH |
1309 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1310 | efx_monitor_interval); | |
1311 | } | |
1312 | ||
1313 | /************************************************************************** | |
1314 | * | |
1315 | * ioctls | |
1316 | * | |
1317 | *************************************************************************/ | |
1318 | ||
1319 | /* Net device ioctl | |
1320 | * Context: process, rtnl_lock() held. | |
1321 | */ | |
1322 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1323 | { | |
767e468c | 1324 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1325 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1326 | |
1327 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1328 | ||
68e7f45e BH |
1329 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1330 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1331 | (data->phy_id & 0xfc00) == 0x0400) | |
1332 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1333 | ||
1334 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1335 | } |
1336 | ||
1337 | /************************************************************************** | |
1338 | * | |
1339 | * NAPI interface | |
1340 | * | |
1341 | **************************************************************************/ | |
1342 | ||
1343 | static int efx_init_napi(struct efx_nic *efx) | |
1344 | { | |
1345 | struct efx_channel *channel; | |
8ceee660 BH |
1346 | |
1347 | efx_for_each_channel(channel, efx) { | |
1348 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1349 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1350 | efx_poll, napi_weight); | |
8ceee660 BH |
1351 | } |
1352 | return 0; | |
8ceee660 BH |
1353 | } |
1354 | ||
1355 | static void efx_fini_napi(struct efx_nic *efx) | |
1356 | { | |
1357 | struct efx_channel *channel; | |
1358 | ||
1359 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1360 | if (channel->napi_dev) |
1361 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1362 | channel->napi_dev = NULL; |
1363 | } | |
1364 | } | |
1365 | ||
1366 | /************************************************************************** | |
1367 | * | |
1368 | * Kernel netpoll interface | |
1369 | * | |
1370 | *************************************************************************/ | |
1371 | ||
1372 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1373 | ||
1374 | /* Although in the common case interrupts will be disabled, this is not | |
1375 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1376 | * so no locking is required. | |
1377 | */ | |
1378 | static void efx_netpoll(struct net_device *net_dev) | |
1379 | { | |
767e468c | 1380 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1381 | struct efx_channel *channel; |
1382 | ||
64ee3120 | 1383 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1384 | efx_schedule_channel(channel); |
1385 | } | |
1386 | ||
1387 | #endif | |
1388 | ||
1389 | /************************************************************************** | |
1390 | * | |
1391 | * Kernel net device interface | |
1392 | * | |
1393 | *************************************************************************/ | |
1394 | ||
1395 | /* Context: process, rtnl_lock() held. */ | |
1396 | static int efx_net_open(struct net_device *net_dev) | |
1397 | { | |
767e468c | 1398 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1399 | EFX_ASSERT_RESET_SERIALISED(efx); |
1400 | ||
1401 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1402 | raw_smp_processor_id()); | |
1403 | ||
f4bd954e BH |
1404 | if (efx->state == STATE_DISABLED) |
1405 | return -EIO; | |
f8b87c17 BH |
1406 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1407 | return -EBUSY; | |
1408 | ||
8ceee660 BH |
1409 | efx_start_all(efx); |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | /* Context: process, rtnl_lock() held. | |
1414 | * Note that the kernel will ignore our return code; this method | |
1415 | * should really be a void. | |
1416 | */ | |
1417 | static int efx_net_stop(struct net_device *net_dev) | |
1418 | { | |
767e468c | 1419 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1420 | |
1421 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1422 | raw_smp_processor_id()); | |
1423 | ||
f4bd954e BH |
1424 | if (efx->state != STATE_DISABLED) { |
1425 | /* Stop the device and flush all the channels */ | |
1426 | efx_stop_all(efx); | |
1427 | efx_fini_channels(efx); | |
1428 | efx_init_channels(efx); | |
1429 | } | |
8ceee660 BH |
1430 | |
1431 | return 0; | |
1432 | } | |
1433 | ||
5b9e207c | 1434 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1435 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1436 | { | |
767e468c | 1437 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1438 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1439 | struct net_device_stats *stats = &net_dev->stats; | |
1440 | ||
55edc6e6 BH |
1441 | spin_lock_bh(&efx->stats_lock); |
1442 | falcon_update_nic_stats(efx); | |
1443 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1444 | |
1445 | stats->rx_packets = mac_stats->rx_packets; | |
1446 | stats->tx_packets = mac_stats->tx_packets; | |
1447 | stats->rx_bytes = mac_stats->rx_bytes; | |
1448 | stats->tx_bytes = mac_stats->tx_bytes; | |
1449 | stats->multicast = mac_stats->rx_multicast; | |
1450 | stats->collisions = mac_stats->tx_collision; | |
1451 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1452 | mac_stats->rx_length_error); | |
1453 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1454 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1455 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1456 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1457 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1458 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1459 | ||
1460 | stats->rx_errors = (stats->rx_length_errors + | |
1461 | stats->rx_over_errors + | |
1462 | stats->rx_crc_errors + | |
1463 | stats->rx_frame_errors + | |
1464 | stats->rx_fifo_errors + | |
1465 | stats->rx_missed_errors + | |
1466 | mac_stats->rx_symbol_error); | |
1467 | stats->tx_errors = (stats->tx_window_errors + | |
1468 | mac_stats->tx_bad); | |
1469 | ||
1470 | return stats; | |
1471 | } | |
1472 | ||
1473 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1474 | static void efx_watchdog(struct net_device *net_dev) | |
1475 | { | |
767e468c | 1476 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1477 | |
739bb23d BH |
1478 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1479 | " resetting channels\n", | |
1480 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1481 | |
739bb23d | 1482 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1483 | } |
1484 | ||
1485 | ||
1486 | /* Context: process, rtnl_lock() held. */ | |
1487 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1488 | { | |
767e468c | 1489 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1490 | int rc = 0; |
1491 | ||
1492 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1493 | ||
1494 | if (new_mtu > EFX_MAX_MTU) | |
1495 | return -EINVAL; | |
1496 | ||
1497 | efx_stop_all(efx); | |
1498 | ||
1499 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1500 | ||
1501 | efx_fini_channels(efx); | |
1502 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1503 | efx_init_channels(efx); |
8ceee660 BH |
1504 | |
1505 | efx_start_all(efx); | |
1506 | return rc; | |
8ceee660 BH |
1507 | } |
1508 | ||
1509 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1510 | { | |
767e468c | 1511 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1512 | struct sockaddr *addr = data; |
1513 | char *new_addr = addr->sa_data; | |
1514 | ||
1515 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1516 | ||
1517 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1518 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1519 | new_addr); | |
8ceee660 BH |
1520 | return -EINVAL; |
1521 | } | |
1522 | ||
1523 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1524 | ||
1525 | /* Reconfigure the MAC */ | |
1526 | efx_reconfigure_port(efx); | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
a816f75a | 1531 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1532 | static void efx_set_multicast_list(struct net_device *net_dev) |
1533 | { | |
767e468c | 1534 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1535 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1536 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1537 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1538 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1539 | u32 crc; |
1540 | int bit; | |
1541 | int i; | |
1542 | ||
a816f75a | 1543 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1544 | |
1545 | /* Build multicast hash table */ | |
1546 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1547 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1548 | } else { | |
1549 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1550 | for (i = 0; i < net_dev->mc_count; i++) { | |
1551 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1552 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1553 | set_bit_le(bit, mc_hash->byte); | |
1554 | mc_list = mc_list->next; | |
1555 | } | |
1556 | } | |
1557 | ||
a816f75a BH |
1558 | if (!efx->port_enabled) |
1559 | /* Delay pushing settings until efx_start_port() */ | |
1560 | return; | |
1561 | ||
1562 | if (changed) | |
766ca0fa | 1563 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1564 | |
8ceee660 BH |
1565 | /* Create and activate new global multicast hash table */ |
1566 | falcon_set_multicast_hash(efx); | |
1567 | } | |
1568 | ||
c3ecb9f3 SH |
1569 | static const struct net_device_ops efx_netdev_ops = { |
1570 | .ndo_open = efx_net_open, | |
1571 | .ndo_stop = efx_net_stop, | |
1572 | .ndo_get_stats = efx_net_stats, | |
1573 | .ndo_tx_timeout = efx_watchdog, | |
1574 | .ndo_start_xmit = efx_hard_start_xmit, | |
1575 | .ndo_validate_addr = eth_validate_addr, | |
1576 | .ndo_do_ioctl = efx_ioctl, | |
1577 | .ndo_change_mtu = efx_change_mtu, | |
1578 | .ndo_set_mac_address = efx_set_mac_address, | |
1579 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1580 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1581 | .ndo_poll_controller = efx_netpoll, | |
1582 | #endif | |
1583 | }; | |
1584 | ||
7dde596e BH |
1585 | static void efx_update_name(struct efx_nic *efx) |
1586 | { | |
1587 | strcpy(efx->name, efx->net_dev->name); | |
1588 | efx_mtd_rename(efx); | |
1589 | efx_set_channel_names(efx); | |
1590 | } | |
1591 | ||
8ceee660 BH |
1592 | static int efx_netdev_event(struct notifier_block *this, |
1593 | unsigned long event, void *ptr) | |
1594 | { | |
d3208b5e | 1595 | struct net_device *net_dev = ptr; |
8ceee660 | 1596 | |
7dde596e BH |
1597 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1598 | event == NETDEV_CHANGENAME) | |
1599 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1600 | |
1601 | return NOTIFY_DONE; | |
1602 | } | |
1603 | ||
1604 | static struct notifier_block efx_netdev_notifier = { | |
1605 | .notifier_call = efx_netdev_event, | |
1606 | }; | |
1607 | ||
06d5e193 BH |
1608 | static ssize_t |
1609 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1610 | { | |
1611 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1612 | return sprintf(buf, "%d\n", efx->phy_type); | |
1613 | } | |
1614 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1615 | ||
8ceee660 BH |
1616 | static int efx_register_netdev(struct efx_nic *efx) |
1617 | { | |
1618 | struct net_device *net_dev = efx->net_dev; | |
1619 | int rc; | |
1620 | ||
1621 | net_dev->watchdog_timeo = 5 * HZ; | |
1622 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1623 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1624 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1625 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1626 | ||
8ceee660 | 1627 | /* Clear MAC statistics */ |
177dfcd8 | 1628 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1629 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1630 | ||
7dde596e | 1631 | rtnl_lock(); |
aed0628d BH |
1632 | |
1633 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1634 | if (rc < 0) | |
1635 | goto fail_locked; | |
7dde596e | 1636 | efx_update_name(efx); |
aed0628d BH |
1637 | |
1638 | rc = register_netdevice(net_dev); | |
1639 | if (rc) | |
1640 | goto fail_locked; | |
1641 | ||
1642 | /* Always start with carrier off; PHY events will detect the link */ | |
1643 | netif_carrier_off(efx->net_dev); | |
1644 | ||
7dde596e | 1645 | rtnl_unlock(); |
8ceee660 | 1646 | |
06d5e193 BH |
1647 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1648 | if (rc) { | |
1649 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1650 | goto fail_registered; | |
1651 | } | |
1652 | ||
8ceee660 | 1653 | return 0; |
06d5e193 | 1654 | |
aed0628d BH |
1655 | fail_locked: |
1656 | rtnl_unlock(); | |
1657 | EFX_ERR(efx, "could not register net dev\n"); | |
1658 | return rc; | |
1659 | ||
06d5e193 BH |
1660 | fail_registered: |
1661 | unregister_netdev(net_dev); | |
1662 | return rc; | |
8ceee660 BH |
1663 | } |
1664 | ||
1665 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1666 | { | |
1667 | struct efx_tx_queue *tx_queue; | |
1668 | ||
1669 | if (!efx->net_dev) | |
1670 | return; | |
1671 | ||
767e468c | 1672 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1673 | |
1674 | /* Free up any skbs still remaining. This has to happen before | |
1675 | * we try to unregister the netdev as running their destructors | |
1676 | * may be needed to get the device ref. count to 0. */ | |
1677 | efx_for_each_tx_queue(tx_queue, efx) | |
1678 | efx_release_tx_buffers(tx_queue); | |
1679 | ||
55668611 | 1680 | if (efx_dev_registered(efx)) { |
8ceee660 | 1681 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1682 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1683 | unregister_netdev(efx->net_dev); |
1684 | } | |
1685 | } | |
1686 | ||
1687 | /************************************************************************** | |
1688 | * | |
1689 | * Device reset and suspend | |
1690 | * | |
1691 | **************************************************************************/ | |
1692 | ||
2467ca46 BH |
1693 | /* Tears down the entire software state and most of the hardware state |
1694 | * before reset. */ | |
4b988280 SH |
1695 | void efx_reset_down(struct efx_nic *efx, enum reset_type method, |
1696 | struct ethtool_cmd *ecmd) | |
8ceee660 | 1697 | { |
8ceee660 BH |
1698 | EFX_ASSERT_RESET_SERIALISED(efx); |
1699 | ||
2467ca46 BH |
1700 | efx_stop_all(efx); |
1701 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1702 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1703 | |
177dfcd8 | 1704 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1705 | |
1706 | efx_fini_channels(efx); | |
4b988280 SH |
1707 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1708 | efx->phy_op->fini(efx); | |
8ceee660 BH |
1709 | } |
1710 | ||
2467ca46 BH |
1711 | /* This function will always ensure that the locks acquired in |
1712 | * efx_reset_down() are released. A failure return code indicates | |
1713 | * that we were unable to reinitialise the hardware, and the | |
1714 | * driver should be disabled. If ok is false, then the rx and tx | |
1715 | * engines are not restarted, pending a RESET_DISABLE. */ | |
4b988280 SH |
1716 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, |
1717 | struct ethtool_cmd *ecmd, bool ok) | |
8ceee660 BH |
1718 | { |
1719 | int rc; | |
1720 | ||
2467ca46 | 1721 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1722 | |
2467ca46 | 1723 | rc = falcon_init_nic(efx); |
8ceee660 | 1724 | if (rc) { |
2467ca46 BH |
1725 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1726 | ok = false; | |
8ceee660 BH |
1727 | } |
1728 | ||
4b988280 SH |
1729 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
1730 | if (ok) { | |
1731 | rc = efx->phy_op->init(efx); | |
1732 | if (rc) | |
1733 | ok = false; | |
115122af BH |
1734 | } |
1735 | if (!ok) | |
4b988280 SH |
1736 | efx->port_initialized = false; |
1737 | } | |
1738 | ||
2467ca46 BH |
1739 | if (ok) { |
1740 | efx_init_channels(efx); | |
8ceee660 | 1741 | |
177dfcd8 | 1742 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1743 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1744 | } | |
1745 | ||
f4150724 | 1746 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1747 | mutex_unlock(&efx->mac_lock); |
1748 | ||
55edc6e6 | 1749 | if (ok) |
2467ca46 | 1750 | efx_start_all(efx); |
8ceee660 BH |
1751 | return rc; |
1752 | } | |
1753 | ||
1754 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1755 | * Note that the reset may fail, in which case the card will be left | |
1756 | * in a most-probably-unusable state. | |
1757 | * | |
1758 | * This function will sleep. You cannot reset from within an atomic | |
1759 | * state; use efx_schedule_reset() instead. | |
1760 | * | |
1761 | * Grabs the rtnl_lock. | |
1762 | */ | |
1763 | static int efx_reset(struct efx_nic *efx) | |
1764 | { | |
1765 | struct ethtool_cmd ecmd; | |
1766 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1767 | int rc = 0; |
8ceee660 BH |
1768 | |
1769 | /* Serialise with kernel interfaces */ | |
1770 | rtnl_lock(); | |
1771 | ||
1772 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1773 | * flag set so that efx_pci_probe_main will be retried */ | |
1774 | if (efx->state != STATE_RUNNING) { | |
1775 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1776 | goto out_unlock; |
8ceee660 BH |
1777 | } |
1778 | ||
c459302d | 1779 | EFX_INFO(efx, "resetting (%s)\n", RESET_TYPE(method)); |
8ceee660 | 1780 | |
4b988280 | 1781 | efx_reset_down(efx, method, &ecmd); |
8ceee660 BH |
1782 | |
1783 | rc = falcon_reset_hw(efx, method); | |
1784 | if (rc) { | |
1785 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1786 | goto out_disable; |
8ceee660 BH |
1787 | } |
1788 | ||
1789 | /* Allow resets to be rescheduled. */ | |
1790 | efx->reset_pending = RESET_TYPE_NONE; | |
1791 | ||
1792 | /* Reinitialise bus-mastering, which may have been turned off before | |
1793 | * the reset was scheduled. This is still appropriate, even in the | |
1794 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1795 | * can respond to requests. */ | |
1796 | pci_set_master(efx->pci_dev); | |
1797 | ||
8ceee660 BH |
1798 | /* Leave device stopped if necessary */ |
1799 | if (method == RESET_TYPE_DISABLE) { | |
4b988280 | 1800 | efx_reset_up(efx, method, &ecmd, false); |
8ceee660 | 1801 | rc = -EIO; |
f4bd954e | 1802 | } else { |
4b988280 | 1803 | rc = efx_reset_up(efx, method, &ecmd, true); |
8ceee660 BH |
1804 | } |
1805 | ||
f4bd954e BH |
1806 | out_disable: |
1807 | if (rc) { | |
1808 | EFX_ERR(efx, "has been disabled\n"); | |
1809 | efx->state = STATE_DISABLED; | |
1810 | dev_close(efx->net_dev); | |
1811 | } else { | |
1812 | EFX_LOG(efx, "reset complete\n"); | |
1813 | } | |
8ceee660 | 1814 | |
f4bd954e | 1815 | out_unlock: |
8ceee660 | 1816 | rtnl_unlock(); |
8ceee660 BH |
1817 | return rc; |
1818 | } | |
1819 | ||
1820 | /* The worker thread exists so that code that cannot sleep can | |
1821 | * schedule a reset for later. | |
1822 | */ | |
1823 | static void efx_reset_work(struct work_struct *data) | |
1824 | { | |
1825 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1826 | ||
1827 | efx_reset(nic); | |
1828 | } | |
1829 | ||
1830 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1831 | { | |
1832 | enum reset_type method; | |
1833 | ||
1834 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1835 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1836 | return; | |
1837 | } | |
1838 | ||
1839 | switch (type) { | |
1840 | case RESET_TYPE_INVISIBLE: | |
1841 | case RESET_TYPE_ALL: | |
1842 | case RESET_TYPE_WORLD: | |
1843 | case RESET_TYPE_DISABLE: | |
1844 | method = type; | |
1845 | break; | |
1846 | case RESET_TYPE_RX_RECOVERY: | |
1847 | case RESET_TYPE_RX_DESC_FETCH: | |
1848 | case RESET_TYPE_TX_DESC_FETCH: | |
1849 | case RESET_TYPE_TX_SKIP: | |
1850 | method = RESET_TYPE_INVISIBLE; | |
1851 | break; | |
1852 | default: | |
1853 | method = RESET_TYPE_ALL; | |
1854 | break; | |
1855 | } | |
1856 | ||
1857 | if (method != type) | |
c459302d BH |
1858 | EFX_LOG(efx, "scheduling %s reset for %s\n", |
1859 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 1860 | else |
c459302d | 1861 | EFX_LOG(efx, "scheduling %s reset\n", RESET_TYPE(method)); |
8ceee660 BH |
1862 | |
1863 | efx->reset_pending = method; | |
1864 | ||
1ab00629 | 1865 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1866 | } |
1867 | ||
1868 | /************************************************************************** | |
1869 | * | |
1870 | * List of NICs we support | |
1871 | * | |
1872 | **************************************************************************/ | |
1873 | ||
1874 | /* PCI device ID table */ | |
1875 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1876 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1877 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1878 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1879 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1880 | {0} /* end of list */ | |
1881 | }; | |
1882 | ||
1883 | /************************************************************************** | |
1884 | * | |
3759433d | 1885 | * Dummy PHY/MAC operations |
8ceee660 | 1886 | * |
01aad7b6 | 1887 | * Can be used for some unimplemented operations |
8ceee660 BH |
1888 | * Needed so all function pointers are valid and do not have to be tested |
1889 | * before use | |
1890 | * | |
1891 | **************************************************************************/ | |
1892 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1893 | { | |
1894 | return 0; | |
1895 | } | |
1896 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
1897 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1898 | { | |
1899 | } | |
8ceee660 | 1900 | |
177dfcd8 BH |
1901 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1902 | .reconfigure = efx_port_dummy_op_void, | |
1903 | }; | |
1904 | ||
8ceee660 BH |
1905 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1906 | .init = efx_port_dummy_op_int, | |
1907 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1908 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1909 | .fini = efx_port_dummy_op_void, |
1910 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1911 | }; |
1912 | ||
8ceee660 BH |
1913 | /************************************************************************** |
1914 | * | |
1915 | * Data housekeeping | |
1916 | * | |
1917 | **************************************************************************/ | |
1918 | ||
1919 | /* This zeroes out and then fills in the invariants in a struct | |
1920 | * efx_nic (including all sub-structures). | |
1921 | */ | |
1922 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1923 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1924 | { | |
1925 | struct efx_channel *channel; | |
1926 | struct efx_tx_queue *tx_queue; | |
1927 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1928 | int i; |
8ceee660 BH |
1929 | |
1930 | /* Initialise common structures */ | |
1931 | memset(efx, 0, sizeof(*efx)); | |
1932 | spin_lock_init(&efx->biu_lock); | |
1933 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1934 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1935 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1936 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1937 | efx->pci_dev = pci_dev; | |
1938 | efx->state = STATE_INIT; | |
1939 | efx->reset_pending = RESET_TYPE_NONE; | |
1940 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
1941 | |
1942 | efx->net_dev = net_dev; | |
dc8cfa55 | 1943 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1944 | spin_lock_init(&efx->netif_stop_lock); |
1945 | spin_lock_init(&efx->stats_lock); | |
1946 | mutex_init(&efx->mac_lock); | |
177dfcd8 | 1947 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 | 1948 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 1949 | efx->mdio.dev = net_dev; |
766ca0fa BH |
1950 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1951 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1952 | atomic_set(&efx->netif_stop_count, 1); |
1953 | ||
1954 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1955 | channel = &efx->channel[i]; | |
1956 | channel->efx = efx; | |
1957 | channel->channel = i; | |
dc8cfa55 | 1958 | channel->work_pending = false; |
8ceee660 | 1959 | } |
60ac1065 | 1960 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1961 | tx_queue = &efx->tx_queue[i]; |
1962 | tx_queue->efx = efx; | |
1963 | tx_queue->queue = i; | |
1964 | tx_queue->buffer = NULL; | |
1965 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1966 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1967 | } |
1968 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1969 | rx_queue = &efx->rx_queue[i]; | |
1970 | rx_queue->efx = efx; | |
1971 | rx_queue->queue = i; | |
1972 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1973 | rx_queue->buffer = NULL; | |
1974 | spin_lock_init(&rx_queue->add_lock); | |
1975 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1976 | } | |
1977 | ||
1978 | efx->type = type; | |
1979 | ||
8ceee660 | 1980 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
1981 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
1982 | ||
8ceee660 BH |
1983 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
1984 | ||
1985 | /* Higher numbered interrupt modes are less capable! */ | |
1986 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1987 | interrupt_mode); | |
1988 | ||
6977dc63 BH |
1989 | /* Would be good to use the net_dev name, but we're too early */ |
1990 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
1991 | pci_name(pci_dev)); | |
1992 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
1993 | if (!efx->workqueue) |
1994 | return -ENOMEM; | |
8d9853d9 | 1995 | |
8ceee660 | 1996 | return 0; |
8ceee660 BH |
1997 | } |
1998 | ||
1999 | static void efx_fini_struct(struct efx_nic *efx) | |
2000 | { | |
2001 | if (efx->workqueue) { | |
2002 | destroy_workqueue(efx->workqueue); | |
2003 | efx->workqueue = NULL; | |
2004 | } | |
2005 | } | |
2006 | ||
2007 | /************************************************************************** | |
2008 | * | |
2009 | * PCI interface | |
2010 | * | |
2011 | **************************************************************************/ | |
2012 | ||
2013 | /* Main body of final NIC shutdown code | |
2014 | * This is called only at module unload (or hotplug removal). | |
2015 | */ | |
2016 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2017 | { | |
f01865f0 | 2018 | falcon_fini_interrupt(efx); |
8ceee660 BH |
2019 | efx_fini_channels(efx); |
2020 | efx_fini_port(efx); | |
8ceee660 BH |
2021 | efx_fini_napi(efx); |
2022 | efx_remove_all(efx); | |
2023 | } | |
2024 | ||
2025 | /* Final NIC shutdown | |
2026 | * This is called only at module unload (or hotplug removal). | |
2027 | */ | |
2028 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2029 | { | |
2030 | struct efx_nic *efx; | |
2031 | ||
2032 | efx = pci_get_drvdata(pci_dev); | |
2033 | if (!efx) | |
2034 | return; | |
2035 | ||
2036 | /* Mark the NIC as fini, then stop the interface */ | |
2037 | rtnl_lock(); | |
2038 | efx->state = STATE_FINI; | |
2039 | dev_close(efx->net_dev); | |
2040 | ||
2041 | /* Allow any queued efx_resets() to complete */ | |
2042 | rtnl_unlock(); | |
2043 | ||
8ceee660 BH |
2044 | efx_unregister_netdev(efx); |
2045 | ||
7dde596e BH |
2046 | efx_mtd_remove(efx); |
2047 | ||
8ceee660 BH |
2048 | /* Wait for any scheduled resets to complete. No more will be |
2049 | * scheduled from this point because efx_stop_all() has been | |
2050 | * called, we are no longer registered with driverlink, and | |
2051 | * the net_device's have been removed. */ | |
1ab00629 | 2052 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2053 | |
2054 | efx_pci_remove_main(efx); | |
2055 | ||
8ceee660 BH |
2056 | efx_fini_io(efx); |
2057 | EFX_LOG(efx, "shutdown successful\n"); | |
2058 | ||
2059 | pci_set_drvdata(pci_dev, NULL); | |
2060 | efx_fini_struct(efx); | |
2061 | free_netdev(efx->net_dev); | |
2062 | }; | |
2063 | ||
2064 | /* Main body of NIC initialisation | |
2065 | * This is called at module load (or hotplug insertion, theoretically). | |
2066 | */ | |
2067 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2068 | { | |
2069 | int rc; | |
2070 | ||
2071 | /* Do start-of-day initialisation */ | |
2072 | rc = efx_probe_all(efx); | |
2073 | if (rc) | |
2074 | goto fail1; | |
2075 | ||
2076 | rc = efx_init_napi(efx); | |
2077 | if (rc) | |
2078 | goto fail2; | |
2079 | ||
8ceee660 BH |
2080 | rc = falcon_init_nic(efx); |
2081 | if (rc) { | |
2082 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
278c0621 | 2083 | goto fail3; |
8ceee660 BH |
2084 | } |
2085 | ||
2086 | rc = efx_init_port(efx); | |
2087 | if (rc) { | |
2088 | EFX_ERR(efx, "failed to initialise port\n"); | |
278c0621 | 2089 | goto fail4; |
8ceee660 BH |
2090 | } |
2091 | ||
bc3c90a2 | 2092 | efx_init_channels(efx); |
8ceee660 BH |
2093 | |
2094 | rc = falcon_init_interrupt(efx); | |
2095 | if (rc) | |
278c0621 | 2096 | goto fail5; |
8ceee660 BH |
2097 | |
2098 | return 0; | |
2099 | ||
278c0621 | 2100 | fail5: |
bc3c90a2 | 2101 | efx_fini_channels(efx); |
8ceee660 | 2102 | efx_fini_port(efx); |
8ceee660 BH |
2103 | fail4: |
2104 | fail3: | |
2105 | efx_fini_napi(efx); | |
2106 | fail2: | |
2107 | efx_remove_all(efx); | |
2108 | fail1: | |
2109 | return rc; | |
2110 | } | |
2111 | ||
2112 | /* NIC initialisation | |
2113 | * | |
2114 | * This is called at module load (or hotplug insertion, | |
2115 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2116 | * sets up and registers the network devices with the kernel and hooks | |
2117 | * the interrupt service routine. It does not prepare the device for | |
2118 | * transmission; this is left to the first time one of the network | |
2119 | * interfaces is brought up (i.e. efx_net_open). | |
2120 | */ | |
2121 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2122 | const struct pci_device_id *entry) | |
2123 | { | |
2124 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2125 | struct net_device *net_dev; | |
2126 | struct efx_nic *efx; | |
2127 | int i, rc; | |
2128 | ||
2129 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2130 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2131 | if (!net_dev) | |
2132 | return -ENOMEM; | |
b9b39b62 | 2133 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
97bc5415 BH |
2134 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2135 | NETIF_F_GRO); | |
28506563 BH |
2136 | /* Mask for features that also apply to VLAN devices */ |
2137 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2138 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2139 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2140 | pci_set_drvdata(pci_dev, efx); |
2141 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2142 | if (rc) | |
2143 | goto fail1; | |
2144 | ||
2145 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2146 | ||
2147 | /* Set up basic I/O (BAR mappings etc) */ | |
2148 | rc = efx_init_io(efx); | |
2149 | if (rc) | |
2150 | goto fail2; | |
2151 | ||
2152 | /* No serialisation is required with the reset path because | |
2153 | * we're in STATE_INIT. */ | |
2154 | for (i = 0; i < 5; i++) { | |
2155 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2156 | |
2157 | /* Serialise against efx_reset(). No more resets will be | |
2158 | * scheduled since efx_stop_all() has been called, and we | |
2159 | * have not and never have been registered with either | |
2160 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2161 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2162 | |
fa402b2e SH |
2163 | if (rc == 0) { |
2164 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2165 | /* If there was a scheduled reset during | |
2166 | * probe, the NIC is probably hosed anyway */ | |
2167 | efx_pci_remove_main(efx); | |
2168 | rc = -EIO; | |
2169 | } else { | |
2170 | break; | |
2171 | } | |
2172 | } | |
2173 | ||
8ceee660 BH |
2174 | /* Retry if a recoverably reset event has been scheduled */ |
2175 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2176 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2177 | goto fail3; | |
2178 | ||
2179 | efx->reset_pending = RESET_TYPE_NONE; | |
2180 | } | |
2181 | ||
2182 | if (rc) { | |
2183 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2184 | goto fail4; | |
2185 | } | |
2186 | ||
55edc6e6 BH |
2187 | /* Switch to the running state before we expose the device to the OS, |
2188 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2189 | efx->state = STATE_RUNNING; |
7dde596e | 2190 | |
8ceee660 BH |
2191 | rc = efx_register_netdev(efx); |
2192 | if (rc) | |
2193 | goto fail5; | |
2194 | ||
2195 | EFX_LOG(efx, "initialisation successful\n"); | |
a5211bb5 BH |
2196 | |
2197 | rtnl_lock(); | |
2198 | efx_mtd_probe(efx); /* allowed to fail */ | |
2199 | rtnl_unlock(); | |
8ceee660 BH |
2200 | return 0; |
2201 | ||
2202 | fail5: | |
2203 | efx_pci_remove_main(efx); | |
2204 | fail4: | |
2205 | fail3: | |
2206 | efx_fini_io(efx); | |
2207 | fail2: | |
2208 | efx_fini_struct(efx); | |
2209 | fail1: | |
2210 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2211 | free_netdev(net_dev); | |
2212 | return rc; | |
2213 | } | |
2214 | ||
2215 | static struct pci_driver efx_pci_driver = { | |
2216 | .name = EFX_DRIVER_NAME, | |
2217 | .id_table = efx_pci_table, | |
2218 | .probe = efx_pci_probe, | |
2219 | .remove = efx_pci_remove, | |
2220 | }; | |
2221 | ||
2222 | /************************************************************************** | |
2223 | * | |
2224 | * Kernel module interface | |
2225 | * | |
2226 | *************************************************************************/ | |
2227 | ||
2228 | module_param(interrupt_mode, uint, 0444); | |
2229 | MODULE_PARM_DESC(interrupt_mode, | |
2230 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2231 | ||
2232 | static int __init efx_init_module(void) | |
2233 | { | |
2234 | int rc; | |
2235 | ||
2236 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2237 | ||
2238 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2239 | if (rc) | |
2240 | goto err_notifier; | |
2241 | ||
2242 | refill_workqueue = create_workqueue("sfc_refill"); | |
2243 | if (!refill_workqueue) { | |
2244 | rc = -ENOMEM; | |
2245 | goto err_refill; | |
2246 | } | |
1ab00629 SH |
2247 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2248 | if (!reset_workqueue) { | |
2249 | rc = -ENOMEM; | |
2250 | goto err_reset; | |
2251 | } | |
8ceee660 BH |
2252 | |
2253 | rc = pci_register_driver(&efx_pci_driver); | |
2254 | if (rc < 0) | |
2255 | goto err_pci; | |
2256 | ||
2257 | return 0; | |
2258 | ||
2259 | err_pci: | |
1ab00629 SH |
2260 | destroy_workqueue(reset_workqueue); |
2261 | err_reset: | |
8ceee660 BH |
2262 | destroy_workqueue(refill_workqueue); |
2263 | err_refill: | |
2264 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2265 | err_notifier: | |
2266 | return rc; | |
2267 | } | |
2268 | ||
2269 | static void __exit efx_exit_module(void) | |
2270 | { | |
2271 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2272 | ||
2273 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2274 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2275 | destroy_workqueue(refill_workqueue); |
2276 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2277 | ||
2278 | } | |
2279 | ||
2280 | module_init(efx_init_module); | |
2281 | module_exit(efx_exit_module); | |
2282 | ||
2283 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2284 | "Solarflare Communications"); | |
2285 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2286 | MODULE_LICENSE("GPL"); | |
2287 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |