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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
0a6f40c6 | 4 | * Copyright 2005-2011 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
64d8ad6d | 24 | #include <linux/cpu_rmap.h> |
8ceee660 | 25 | #include "net_driver.h" |
8ceee660 | 26 | #include "efx.h" |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
c459302d BH |
71 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; |
72 | const char *efx_reset_type_names[] = { | |
73 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
74 | [RESET_TYPE_ALL] = "ALL", | |
75 | [RESET_TYPE_WORLD] = "WORLD", | |
76 | [RESET_TYPE_DISABLE] = "DISABLE", | |
77 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
78 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
79 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
80 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
81 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
82 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 83 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
84 | }; |
85 | ||
8ceee660 BH |
86 | #define EFX_MAX_MTU (9 * 1024) |
87 | ||
1ab00629 SH |
88 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
89 | * queued onto this work queue. This is not a per-nic work queue, because | |
90 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
91 | */ | |
92 | static struct workqueue_struct *reset_workqueue; | |
93 | ||
8ceee660 BH |
94 | /************************************************************************** |
95 | * | |
96 | * Configurable values | |
97 | * | |
98 | *************************************************************************/ | |
99 | ||
8ceee660 BH |
100 | /* |
101 | * Use separate channels for TX and RX events | |
102 | * | |
28b581ab NT |
103 | * Set this to 1 to use separate channels for TX and RX. It allows us |
104 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 105 | * |
28b581ab | 106 | * This is only used in MSI-X interrupt mode |
8ceee660 | 107 | */ |
28b581ab | 108 | static unsigned int separate_tx_channels; |
8313aca3 | 109 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
110 | MODULE_PARM_DESC(separate_tx_channels, |
111 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
112 | |
113 | /* This is the weight assigned to each of the (per-channel) virtual | |
114 | * NAPI devices. | |
115 | */ | |
116 | static int napi_weight = 64; | |
117 | ||
118 | /* This is the time (in jiffies) between invocations of the hardware | |
e254c274 BH |
119 | * monitor. On Falcon-based NICs, this will: |
120 | * - Check the on-board hardware monitor; | |
121 | * - Poll the link state and reconfigure the hardware as necessary. | |
8ceee660 | 122 | */ |
d215697f | 123 | static unsigned int efx_monitor_interval = 1 * HZ; |
8ceee660 | 124 | |
8ceee660 BH |
125 | /* This controls whether or not the driver will initialise devices |
126 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
127 | * such devices will be initialised with a random locally-generated | |
128 | * MAC address. This allows for loading the sfc_mtd driver to | |
129 | * reprogram the flash, even if the flash contents (including the MAC | |
130 | * address) have previously been erased. | |
131 | */ | |
132 | static unsigned int allow_bad_hwaddr; | |
133 | ||
134 | /* Initial interrupt moderation settings. They can be modified after | |
135 | * module load with ethtool. | |
136 | * | |
137 | * The default for RX should strike a balance between increasing the | |
138 | * round-trip latency and reducing overhead. | |
139 | */ | |
140 | static unsigned int rx_irq_mod_usec = 60; | |
141 | ||
142 | /* Initial interrupt moderation settings. They can be modified after | |
143 | * module load with ethtool. | |
144 | * | |
145 | * This default is chosen to ensure that a 10G link does not go idle | |
146 | * while a TX queue is stopped after it has become full. A queue is | |
147 | * restarted when it drops below half full. The time this takes (assuming | |
148 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
149 | * 512 / 3 * 1.2 = 205 usec. | |
150 | */ | |
151 | static unsigned int tx_irq_mod_usec = 150; | |
152 | ||
153 | /* This is the first interrupt mode to try out of: | |
154 | * 0 => MSI-X | |
155 | * 1 => MSI | |
156 | * 2 => legacy | |
157 | */ | |
158 | static unsigned int interrupt_mode; | |
159 | ||
160 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
161 | * i.e. the number of CPUs among which we may distribute simultaneous | |
162 | * interrupt handling. | |
163 | * | |
164 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
165 | * The default (0) means to assign an interrupt to each package (level II cache) | |
166 | */ | |
167 | static unsigned int rss_cpus; | |
168 | module_param(rss_cpus, uint, 0444); | |
169 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
170 | ||
84ae48fe BH |
171 | static int phy_flash_cfg; |
172 | module_param(phy_flash_cfg, int, 0644); | |
173 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
174 | ||
6fb70fd1 BH |
175 | static unsigned irq_adapt_low_thresh = 10000; |
176 | module_param(irq_adapt_low_thresh, uint, 0644); | |
177 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
178 | "Threshold score for reducing IRQ moderation"); | |
179 | ||
180 | static unsigned irq_adapt_high_thresh = 20000; | |
181 | module_param(irq_adapt_high_thresh, uint, 0644); | |
182 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
183 | "Threshold score for increasing IRQ moderation"); | |
184 | ||
62776d03 BH |
185 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
186 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
187 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
188 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
189 | module_param(debug, uint, 0); | |
190 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
191 | ||
8ceee660 BH |
192 | /************************************************************************** |
193 | * | |
194 | * Utility functions and prototypes | |
195 | * | |
196 | *************************************************************************/ | |
4642610c BH |
197 | |
198 | static void efx_remove_channels(struct efx_nic *efx); | |
8ceee660 | 199 | static void efx_remove_port(struct efx_nic *efx); |
e8f14992 | 200 | static void efx_init_napi(struct efx_nic *efx); |
8ceee660 | 201 | static void efx_fini_napi(struct efx_nic *efx); |
e8f14992 | 202 | static void efx_fini_napi_channel(struct efx_channel *channel); |
4642610c BH |
203 | static void efx_fini_struct(struct efx_nic *efx); |
204 | static void efx_start_all(struct efx_nic *efx); | |
205 | static void efx_stop_all(struct efx_nic *efx); | |
8ceee660 BH |
206 | |
207 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
208 | do { \ | |
332c1ce9 BH |
209 | if ((efx->state == STATE_RUNNING) || \ |
210 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
211 | ASSERT_RTNL(); \ |
212 | } while (0) | |
213 | ||
214 | /************************************************************************** | |
215 | * | |
216 | * Event queue processing | |
217 | * | |
218 | *************************************************************************/ | |
219 | ||
220 | /* Process channel's event queue | |
221 | * | |
222 | * This function is responsible for processing the event queue of a | |
223 | * single channel. The caller must guarantee that this function will | |
224 | * never be concurrently called more than once on the same channel, | |
225 | * though different channels may be being processed concurrently. | |
226 | */ | |
fa236e18 | 227 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 228 | { |
42cbe2d7 | 229 | struct efx_nic *efx = channel->efx; |
fa236e18 | 230 | int spent; |
8ceee660 | 231 | |
42cbe2d7 | 232 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 233 | !channel->enabled)) |
42cbe2d7 | 234 | return 0; |
8ceee660 | 235 | |
fa236e18 BH |
236 | spent = efx_nic_process_eventq(channel, budget); |
237 | if (spent == 0) | |
42cbe2d7 | 238 | return 0; |
8ceee660 BH |
239 | |
240 | /* Deliver last RX packet. */ | |
241 | if (channel->rx_pkt) { | |
242 | __efx_rx_packet(channel, channel->rx_pkt, | |
243 | channel->rx_pkt_csummed); | |
244 | channel->rx_pkt = NULL; | |
245 | } | |
246 | ||
8ceee660 BH |
247 | efx_rx_strategy(channel); |
248 | ||
f7d12cdc | 249 | efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); |
8ceee660 | 250 | |
fa236e18 | 251 | return spent; |
8ceee660 BH |
252 | } |
253 | ||
254 | /* Mark channel as finished processing | |
255 | * | |
256 | * Note that since we will not receive further interrupts for this | |
257 | * channel before we finish processing and call the eventq_read_ack() | |
258 | * method, there is no need to use the interrupt hold-off timers. | |
259 | */ | |
260 | static inline void efx_channel_processed(struct efx_channel *channel) | |
261 | { | |
5b9e207c BH |
262 | /* The interrupt handler for this channel may set work_pending |
263 | * as soon as we acknowledge the events we've seen. Make sure | |
264 | * it's cleared before then. */ | |
dc8cfa55 | 265 | channel->work_pending = false; |
5b9e207c BH |
266 | smp_wmb(); |
267 | ||
152b6a62 | 268 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
269 | } |
270 | ||
271 | /* NAPI poll handler | |
272 | * | |
273 | * NAPI guarantees serialisation of polls of the same device, which | |
274 | * provides the guarantee required by efx_process_channel(). | |
275 | */ | |
276 | static int efx_poll(struct napi_struct *napi, int budget) | |
277 | { | |
278 | struct efx_channel *channel = | |
279 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 280 | struct efx_nic *efx = channel->efx; |
fa236e18 | 281 | int spent; |
8ceee660 | 282 | |
62776d03 BH |
283 | netif_vdbg(efx, intr, efx->net_dev, |
284 | "channel %d NAPI poll executing on CPU %d\n", | |
285 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 286 | |
fa236e18 | 287 | spent = efx_process_channel(channel, budget); |
8ceee660 | 288 | |
fa236e18 | 289 | if (spent < budget) { |
a4900ac9 | 290 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
291 | efx->irq_rx_adaptive && |
292 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
293 | if (unlikely(channel->irq_mod_score < |
294 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
295 | if (channel->irq_moderation > 1) { |
296 | channel->irq_moderation -= 1; | |
ef2b90ee | 297 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 298 | } |
6fb70fd1 BH |
299 | } else if (unlikely(channel->irq_mod_score > |
300 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
301 | if (channel->irq_moderation < |
302 | efx->irq_rx_moderation) { | |
303 | channel->irq_moderation += 1; | |
ef2b90ee | 304 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 305 | } |
6fb70fd1 | 306 | } |
6fb70fd1 BH |
307 | channel->irq_count = 0; |
308 | channel->irq_mod_score = 0; | |
309 | } | |
310 | ||
64d8ad6d BH |
311 | efx_filter_rfs_expire(channel); |
312 | ||
8ceee660 | 313 | /* There is no race here; although napi_disable() will |
288379f0 | 314 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
315 | * since efx_channel_processed() will have no effect if |
316 | * interrupts have already been disabled. | |
317 | */ | |
288379f0 | 318 | napi_complete(napi); |
8ceee660 BH |
319 | efx_channel_processed(channel); |
320 | } | |
321 | ||
fa236e18 | 322 | return spent; |
8ceee660 BH |
323 | } |
324 | ||
325 | /* Process the eventq of the specified channel immediately on this CPU | |
326 | * | |
327 | * Disable hardware generated interrupts, wait for any existing | |
328 | * processing to finish, then directly poll (and ack ) the eventq. | |
329 | * Finally reenable NAPI and interrupts. | |
330 | * | |
331 | * Since we are touching interrupts the caller should hold the suspend lock | |
332 | */ | |
333 | void efx_process_channel_now(struct efx_channel *channel) | |
334 | { | |
335 | struct efx_nic *efx = channel->efx; | |
336 | ||
8313aca3 | 337 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 BH |
338 | BUG_ON(!channel->enabled); |
339 | ||
340 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 341 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 342 | if (efx->legacy_irq) { |
8ceee660 | 343 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
344 | efx->legacy_irq_enabled = false; |
345 | } | |
64ee3120 | 346 | if (channel->irq) |
8ceee660 BH |
347 | synchronize_irq(channel->irq); |
348 | ||
349 | /* Wait for any NAPI processing to complete */ | |
350 | napi_disable(&channel->napi_str); | |
351 | ||
352 | /* Poll the channel */ | |
ecc910f5 | 353 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
354 | |
355 | /* Ack the eventq. This may cause an interrupt to be generated | |
356 | * when they are reenabled */ | |
357 | efx_channel_processed(channel); | |
358 | ||
359 | napi_enable(&channel->napi_str); | |
94dec6a2 BH |
360 | if (efx->legacy_irq) |
361 | efx->legacy_irq_enabled = true; | |
152b6a62 | 362 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
363 | } |
364 | ||
365 | /* Create event queue | |
366 | * Event queue memory allocations are done only once. If the channel | |
367 | * is reset, the memory buffer will be reused; this guards against | |
368 | * errors during channel reset and also simplifies interrupt handling. | |
369 | */ | |
370 | static int efx_probe_eventq(struct efx_channel *channel) | |
371 | { | |
ecc910f5 SH |
372 | struct efx_nic *efx = channel->efx; |
373 | unsigned long entries; | |
374 | ||
62776d03 BH |
375 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
376 | "chan %d create event queue\n", channel->channel); | |
8ceee660 | 377 | |
ecc910f5 SH |
378 | /* Build an event queue with room for one event per tx and rx buffer, |
379 | * plus some extra for link state events and MCDI completions. */ | |
380 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
381 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
382 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
383 | ||
152b6a62 | 384 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
385 | } |
386 | ||
387 | /* Prepare channel's event queue */ | |
bc3c90a2 | 388 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 389 | { |
62776d03 BH |
390 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
391 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
392 | |
393 | channel->eventq_read_ptr = 0; | |
394 | ||
152b6a62 | 395 | efx_nic_init_eventq(channel); |
8ceee660 BH |
396 | } |
397 | ||
398 | static void efx_fini_eventq(struct efx_channel *channel) | |
399 | { | |
62776d03 BH |
400 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
401 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 402 | |
152b6a62 | 403 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
404 | } |
405 | ||
406 | static void efx_remove_eventq(struct efx_channel *channel) | |
407 | { | |
62776d03 BH |
408 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
409 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 410 | |
152b6a62 | 411 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
412 | } |
413 | ||
414 | /************************************************************************** | |
415 | * | |
416 | * Channel handling | |
417 | * | |
418 | *************************************************************************/ | |
419 | ||
4642610c BH |
420 | /* Allocate and initialise a channel structure, optionally copying |
421 | * parameters (but not resources) from an old channel structure. */ | |
422 | static struct efx_channel * | |
423 | efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel) | |
424 | { | |
425 | struct efx_channel *channel; | |
426 | struct efx_rx_queue *rx_queue; | |
427 | struct efx_tx_queue *tx_queue; | |
428 | int j; | |
429 | ||
430 | if (old_channel) { | |
431 | channel = kmalloc(sizeof(*channel), GFP_KERNEL); | |
432 | if (!channel) | |
433 | return NULL; | |
434 | ||
435 | *channel = *old_channel; | |
436 | ||
e8f14992 | 437 | channel->napi_dev = NULL; |
4642610c BH |
438 | memset(&channel->eventq, 0, sizeof(channel->eventq)); |
439 | ||
440 | rx_queue = &channel->rx_queue; | |
441 | rx_queue->buffer = NULL; | |
442 | memset(&rx_queue->rxd, 0, sizeof(rx_queue->rxd)); | |
443 | ||
444 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
445 | tx_queue = &channel->tx_queue[j]; | |
446 | if (tx_queue->channel) | |
447 | tx_queue->channel = channel; | |
448 | tx_queue->buffer = NULL; | |
449 | memset(&tx_queue->txd, 0, sizeof(tx_queue->txd)); | |
450 | } | |
451 | } else { | |
452 | channel = kzalloc(sizeof(*channel), GFP_KERNEL); | |
453 | if (!channel) | |
454 | return NULL; | |
455 | ||
456 | channel->efx = efx; | |
457 | channel->channel = i; | |
458 | ||
459 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
460 | tx_queue = &channel->tx_queue[j]; | |
461 | tx_queue->efx = efx; | |
462 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
463 | tx_queue->channel = channel; | |
464 | } | |
465 | } | |
466 | ||
4642610c BH |
467 | rx_queue = &channel->rx_queue; |
468 | rx_queue->efx = efx; | |
469 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, | |
470 | (unsigned long)rx_queue); | |
471 | ||
472 | return channel; | |
473 | } | |
474 | ||
8ceee660 BH |
475 | static int efx_probe_channel(struct efx_channel *channel) |
476 | { | |
477 | struct efx_tx_queue *tx_queue; | |
478 | struct efx_rx_queue *rx_queue; | |
479 | int rc; | |
480 | ||
62776d03 BH |
481 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
482 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
483 | |
484 | rc = efx_probe_eventq(channel); | |
485 | if (rc) | |
486 | goto fail1; | |
487 | ||
488 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
489 | rc = efx_probe_tx_queue(tx_queue); | |
490 | if (rc) | |
491 | goto fail2; | |
492 | } | |
493 | ||
494 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
495 | rc = efx_probe_rx_queue(rx_queue); | |
496 | if (rc) | |
497 | goto fail3; | |
498 | } | |
499 | ||
500 | channel->n_rx_frm_trunc = 0; | |
501 | ||
502 | return 0; | |
503 | ||
504 | fail3: | |
505 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
506 | efx_remove_rx_queue(rx_queue); | |
507 | fail2: | |
508 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
509 | efx_remove_tx_queue(tx_queue); | |
510 | fail1: | |
511 | return rc; | |
512 | } | |
513 | ||
514 | ||
56536e9c BH |
515 | static void efx_set_channel_names(struct efx_nic *efx) |
516 | { | |
517 | struct efx_channel *channel; | |
518 | const char *type = ""; | |
519 | int number; | |
520 | ||
521 | efx_for_each_channel(channel, efx) { | |
522 | number = channel->channel; | |
a4900ac9 BH |
523 | if (efx->n_channels > efx->n_rx_channels) { |
524 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
525 | type = "-rx"; |
526 | } else { | |
527 | type = "-tx"; | |
a4900ac9 | 528 | number -= efx->n_rx_channels; |
56536e9c BH |
529 | } |
530 | } | |
4642610c BH |
531 | snprintf(efx->channel_name[channel->channel], |
532 | sizeof(efx->channel_name[0]), | |
56536e9c BH |
533 | "%s%s-%d", efx->name, type, number); |
534 | } | |
535 | } | |
536 | ||
4642610c BH |
537 | static int efx_probe_channels(struct efx_nic *efx) |
538 | { | |
539 | struct efx_channel *channel; | |
540 | int rc; | |
541 | ||
542 | /* Restart special buffer allocation */ | |
543 | efx->next_buffer_table = 0; | |
544 | ||
545 | efx_for_each_channel(channel, efx) { | |
546 | rc = efx_probe_channel(channel); | |
547 | if (rc) { | |
548 | netif_err(efx, probe, efx->net_dev, | |
549 | "failed to create channel %d\n", | |
550 | channel->channel); | |
551 | goto fail; | |
552 | } | |
553 | } | |
554 | efx_set_channel_names(efx); | |
555 | ||
556 | return 0; | |
557 | ||
558 | fail: | |
559 | efx_remove_channels(efx); | |
560 | return rc; | |
561 | } | |
562 | ||
8ceee660 BH |
563 | /* Channels are shutdown and reinitialised whilst the NIC is running |
564 | * to propagate configuration changes (mtu, checksum offload), or | |
565 | * to clear hardware error conditions | |
566 | */ | |
bc3c90a2 | 567 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
568 | { |
569 | struct efx_tx_queue *tx_queue; | |
570 | struct efx_rx_queue *rx_queue; | |
571 | struct efx_channel *channel; | |
8ceee660 | 572 | |
f7f13b0b BH |
573 | /* Calculate the rx buffer allocation parameters required to |
574 | * support the current MTU, including padding for header | |
575 | * alignment and overruns. | |
576 | */ | |
577 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
578 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 579 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 580 | efx->type->rx_buffer_padding); |
62b330ba SH |
581 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
582 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
583 | |
584 | /* Initialise the channels */ | |
585 | efx_for_each_channel(channel, efx) { | |
62776d03 BH |
586 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
587 | "init chan %d\n", channel->channel); | |
8ceee660 | 588 | |
bc3c90a2 | 589 | efx_init_eventq(channel); |
8ceee660 | 590 | |
bc3c90a2 BH |
591 | efx_for_each_channel_tx_queue(tx_queue, channel) |
592 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
593 | |
594 | /* The rx buffer allocation strategy is MTU dependent */ | |
595 | efx_rx_strategy(channel); | |
596 | ||
bc3c90a2 BH |
597 | efx_for_each_channel_rx_queue(rx_queue, channel) |
598 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
599 | |
600 | WARN_ON(channel->rx_pkt != NULL); | |
601 | efx_rx_strategy(channel); | |
602 | } | |
8ceee660 BH |
603 | } |
604 | ||
605 | /* This enables event queue processing and packet transmission. | |
606 | * | |
607 | * Note that this function is not allowed to fail, since that would | |
608 | * introduce too much complexity into the suspend/resume path. | |
609 | */ | |
610 | static void efx_start_channel(struct efx_channel *channel) | |
611 | { | |
612 | struct efx_rx_queue *rx_queue; | |
613 | ||
62776d03 BH |
614 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, |
615 | "starting chan %d\n", channel->channel); | |
8ceee660 | 616 | |
5b9e207c BH |
617 | /* The interrupt handler for this channel may set work_pending |
618 | * as soon as we enable it. Make sure it's cleared before | |
619 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
620 | channel->work_pending = false; |
621 | channel->enabled = true; | |
5b9e207c | 622 | smp_wmb(); |
8ceee660 | 623 | |
90d683af | 624 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
625 | efx_for_each_channel_rx_queue(rx_queue, channel) |
626 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
627 | |
628 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
629 | } |
630 | ||
631 | /* This disables event queue processing and packet transmission. | |
632 | * This function does not guarantee that all queue processing | |
633 | * (e.g. RX refill) is complete. | |
634 | */ | |
635 | static void efx_stop_channel(struct efx_channel *channel) | |
636 | { | |
8ceee660 BH |
637 | if (!channel->enabled) |
638 | return; | |
639 | ||
62776d03 BH |
640 | netif_dbg(channel->efx, ifdown, channel->efx->net_dev, |
641 | "stop chan %d\n", channel->channel); | |
8ceee660 | 642 | |
dc8cfa55 | 643 | channel->enabled = false; |
8ceee660 | 644 | napi_disable(&channel->napi_str); |
8ceee660 BH |
645 | } |
646 | ||
647 | static void efx_fini_channels(struct efx_nic *efx) | |
648 | { | |
649 | struct efx_channel *channel; | |
650 | struct efx_tx_queue *tx_queue; | |
651 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 652 | int rc; |
8ceee660 BH |
653 | |
654 | EFX_ASSERT_RESET_SERIALISED(efx); | |
655 | BUG_ON(efx->port_enabled); | |
656 | ||
152b6a62 | 657 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
658 | if (rc && EFX_WORKAROUND_7803(efx)) { |
659 | /* Schedule a reset to recover from the flush failure. The | |
660 | * descriptor caches reference memory we're about to free, | |
661 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
662 | * the MACs because of the pending reset. */ | |
62776d03 BH |
663 | netif_err(efx, drv, efx->net_dev, |
664 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
665 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
666 | } else if (rc) { | |
62776d03 | 667 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 668 | } else { |
62776d03 BH |
669 | netif_dbg(efx, drv, efx->net_dev, |
670 | "successfully flushed all queues\n"); | |
fd371e32 | 671 | } |
6bc5d3a9 | 672 | |
8ceee660 | 673 | efx_for_each_channel(channel, efx) { |
62776d03 BH |
674 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
675 | "shut down chan %d\n", channel->channel); | |
8ceee660 BH |
676 | |
677 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
678 | efx_fini_rx_queue(rx_queue); | |
94b274bf | 679 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 | 680 | efx_fini_tx_queue(tx_queue); |
8ceee660 BH |
681 | efx_fini_eventq(channel); |
682 | } | |
683 | } | |
684 | ||
685 | static void efx_remove_channel(struct efx_channel *channel) | |
686 | { | |
687 | struct efx_tx_queue *tx_queue; | |
688 | struct efx_rx_queue *rx_queue; | |
689 | ||
62776d03 BH |
690 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
691 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
692 | |
693 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
694 | efx_remove_rx_queue(rx_queue); | |
94b274bf | 695 | efx_for_each_possible_channel_tx_queue(tx_queue, channel) |
8ceee660 BH |
696 | efx_remove_tx_queue(tx_queue); |
697 | efx_remove_eventq(channel); | |
8ceee660 BH |
698 | } |
699 | ||
4642610c BH |
700 | static void efx_remove_channels(struct efx_nic *efx) |
701 | { | |
702 | struct efx_channel *channel; | |
703 | ||
704 | efx_for_each_channel(channel, efx) | |
705 | efx_remove_channel(channel); | |
706 | } | |
707 | ||
708 | int | |
709 | efx_realloc_channels(struct efx_nic *efx, u32 rxq_entries, u32 txq_entries) | |
710 | { | |
711 | struct efx_channel *other_channel[EFX_MAX_CHANNELS], *channel; | |
712 | u32 old_rxq_entries, old_txq_entries; | |
713 | unsigned i; | |
714 | int rc; | |
715 | ||
716 | efx_stop_all(efx); | |
717 | efx_fini_channels(efx); | |
718 | ||
719 | /* Clone channels */ | |
720 | memset(other_channel, 0, sizeof(other_channel)); | |
721 | for (i = 0; i < efx->n_channels; i++) { | |
722 | channel = efx_alloc_channel(efx, i, efx->channel[i]); | |
723 | if (!channel) { | |
724 | rc = -ENOMEM; | |
725 | goto out; | |
726 | } | |
727 | other_channel[i] = channel; | |
728 | } | |
729 | ||
730 | /* Swap entry counts and channel pointers */ | |
731 | old_rxq_entries = efx->rxq_entries; | |
732 | old_txq_entries = efx->txq_entries; | |
733 | efx->rxq_entries = rxq_entries; | |
734 | efx->txq_entries = txq_entries; | |
735 | for (i = 0; i < efx->n_channels; i++) { | |
736 | channel = efx->channel[i]; | |
737 | efx->channel[i] = other_channel[i]; | |
738 | other_channel[i] = channel; | |
739 | } | |
740 | ||
741 | rc = efx_probe_channels(efx); | |
742 | if (rc) | |
743 | goto rollback; | |
744 | ||
e8f14992 BH |
745 | efx_init_napi(efx); |
746 | ||
4642610c | 747 | /* Destroy old channels */ |
e8f14992 BH |
748 | for (i = 0; i < efx->n_channels; i++) { |
749 | efx_fini_napi_channel(other_channel[i]); | |
4642610c | 750 | efx_remove_channel(other_channel[i]); |
e8f14992 | 751 | } |
4642610c BH |
752 | out: |
753 | /* Free unused channel structures */ | |
754 | for (i = 0; i < efx->n_channels; i++) | |
755 | kfree(other_channel[i]); | |
756 | ||
757 | efx_init_channels(efx); | |
758 | efx_start_all(efx); | |
759 | return rc; | |
760 | ||
761 | rollback: | |
762 | /* Swap back */ | |
763 | efx->rxq_entries = old_rxq_entries; | |
764 | efx->txq_entries = old_txq_entries; | |
765 | for (i = 0; i < efx->n_channels; i++) { | |
766 | channel = efx->channel[i]; | |
767 | efx->channel[i] = other_channel[i]; | |
768 | other_channel[i] = channel; | |
769 | } | |
770 | goto out; | |
771 | } | |
772 | ||
90d683af | 773 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 774 | { |
90d683af | 775 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
776 | } |
777 | ||
778 | /************************************************************************** | |
779 | * | |
780 | * Port handling | |
781 | * | |
782 | **************************************************************************/ | |
783 | ||
784 | /* This ensures that the kernel is kept informed (via | |
785 | * netif_carrier_on/off) of the link status, and also maintains the | |
786 | * link status's stop on the port's TX queue. | |
787 | */ | |
fdaa9aed | 788 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 789 | { |
eb50c0d6 BH |
790 | struct efx_link_state *link_state = &efx->link_state; |
791 | ||
8ceee660 BH |
792 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
793 | * that no events are triggered between unregister_netdev() and the | |
794 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
795 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
796 | if (!netif_running(efx->net_dev)) | |
797 | return; | |
798 | ||
8c8661e4 BH |
799 | if (efx->port_inhibited) { |
800 | netif_carrier_off(efx->net_dev); | |
801 | return; | |
802 | } | |
803 | ||
eb50c0d6 | 804 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
805 | efx->n_link_state_changes++; |
806 | ||
eb50c0d6 | 807 | if (link_state->up) |
8ceee660 BH |
808 | netif_carrier_on(efx->net_dev); |
809 | else | |
810 | netif_carrier_off(efx->net_dev); | |
811 | } | |
812 | ||
813 | /* Status message for kernel log */ | |
eb50c0d6 | 814 | if (link_state->up) { |
62776d03 BH |
815 | netif_info(efx, link, efx->net_dev, |
816 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
817 | link_state->speed, link_state->fd ? "full" : "half", | |
818 | efx->net_dev->mtu, | |
819 | (efx->promiscuous ? " [PROMISC]" : "")); | |
8ceee660 | 820 | } else { |
62776d03 | 821 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
822 | } |
823 | ||
824 | } | |
825 | ||
d3245b28 BH |
826 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
827 | { | |
828 | efx->link_advertising = advertising; | |
829 | if (advertising) { | |
830 | if (advertising & ADVERTISED_Pause) | |
831 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
832 | else | |
833 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
834 | if (advertising & ADVERTISED_Asym_Pause) | |
835 | efx->wanted_fc ^= EFX_FC_TX; | |
836 | } | |
837 | } | |
838 | ||
839 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
840 | { | |
841 | efx->wanted_fc = wanted_fc; | |
842 | if (efx->link_advertising) { | |
843 | if (wanted_fc & EFX_FC_RX) | |
844 | efx->link_advertising |= (ADVERTISED_Pause | | |
845 | ADVERTISED_Asym_Pause); | |
846 | else | |
847 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
848 | ADVERTISED_Asym_Pause); | |
849 | if (wanted_fc & EFX_FC_TX) | |
850 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
851 | } | |
852 | } | |
853 | ||
115122af BH |
854 | static void efx_fini_port(struct efx_nic *efx); |
855 | ||
d3245b28 BH |
856 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
857 | * the MAC appropriately. All other PHY configuration changes are pushed | |
858 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
859 | * through efx_monitor(). | |
860 | * | |
861 | * Callers must hold the mac_lock | |
862 | */ | |
863 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 864 | { |
d3245b28 BH |
865 | enum efx_phy_mode phy_mode; |
866 | int rc; | |
8ceee660 | 867 | |
d3245b28 | 868 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 869 | |
a816f75a BH |
870 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
871 | if (efx_dev_registered(efx)) { | |
872 | netif_addr_lock_bh(efx->net_dev); | |
873 | netif_addr_unlock_bh(efx->net_dev); | |
874 | } | |
875 | ||
d3245b28 BH |
876 | /* Disable PHY transmit in mac level loopbacks */ |
877 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
878 | if (LOOPBACK_INTERNAL(efx)) |
879 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
880 | else | |
881 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 882 | |
d3245b28 | 883 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 884 | |
d3245b28 BH |
885 | if (rc) |
886 | efx->phy_mode = phy_mode; | |
177dfcd8 | 887 | |
d3245b28 | 888 | return rc; |
8ceee660 BH |
889 | } |
890 | ||
891 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
892 | * disabled. */ | |
d3245b28 | 893 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 894 | { |
d3245b28 BH |
895 | int rc; |
896 | ||
8ceee660 BH |
897 | EFX_ASSERT_RESET_SERIALISED(efx); |
898 | ||
899 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 900 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 901 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
902 | |
903 | return rc; | |
8ceee660 BH |
904 | } |
905 | ||
8be4f3e6 BH |
906 | /* Asynchronous work item for changing MAC promiscuity and multicast |
907 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
908 | * MAC directly. */ | |
766ca0fa BH |
909 | static void efx_mac_work(struct work_struct *data) |
910 | { | |
911 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
912 | ||
913 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 914 | if (efx->port_enabled) { |
ef2b90ee | 915 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
916 | efx->mac_op->reconfigure(efx); |
917 | } | |
766ca0fa BH |
918 | mutex_unlock(&efx->mac_lock); |
919 | } | |
920 | ||
8ceee660 BH |
921 | static int efx_probe_port(struct efx_nic *efx) |
922 | { | |
7e300bc8 | 923 | unsigned char *perm_addr; |
8ceee660 BH |
924 | int rc; |
925 | ||
62776d03 | 926 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 927 | |
ff3b00a0 SH |
928 | if (phy_flash_cfg) |
929 | efx->phy_mode = PHY_MODE_SPECIAL; | |
930 | ||
ef2b90ee BH |
931 | /* Connect up MAC/PHY operations table */ |
932 | rc = efx->type->probe_port(efx); | |
8ceee660 | 933 | if (rc) |
e42de262 | 934 | return rc; |
8ceee660 BH |
935 | |
936 | /* Sanity check MAC address */ | |
7e300bc8 BH |
937 | perm_addr = efx->net_dev->perm_addr; |
938 | if (is_valid_ether_addr(perm_addr)) { | |
939 | memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN); | |
8ceee660 | 940 | } else { |
62776d03 | 941 | netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n", |
7e300bc8 | 942 | perm_addr); |
8ceee660 BH |
943 | if (!allow_bad_hwaddr) { |
944 | rc = -EINVAL; | |
945 | goto err; | |
946 | } | |
947 | random_ether_addr(efx->net_dev->dev_addr); | |
62776d03 BH |
948 | netif_info(efx, probe, efx->net_dev, |
949 | "using locally-generated MAC %pM\n", | |
950 | efx->net_dev->dev_addr); | |
8ceee660 BH |
951 | } |
952 | ||
953 | return 0; | |
954 | ||
955 | err: | |
e42de262 | 956 | efx->type->remove_port(efx); |
8ceee660 BH |
957 | return rc; |
958 | } | |
959 | ||
960 | static int efx_init_port(struct efx_nic *efx) | |
961 | { | |
962 | int rc; | |
963 | ||
62776d03 | 964 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 965 | |
1dfc5cea BH |
966 | mutex_lock(&efx->mac_lock); |
967 | ||
177dfcd8 | 968 | rc = efx->phy_op->init(efx); |
8ceee660 | 969 | if (rc) |
1dfc5cea | 970 | goto fail1; |
8ceee660 | 971 | |
dc8cfa55 | 972 | efx->port_initialized = true; |
1dfc5cea | 973 | |
d3245b28 BH |
974 | /* Reconfigure the MAC before creating dma queues (required for |
975 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
976 | efx->mac_op->reconfigure(efx); | |
977 | ||
978 | /* Ensure the PHY advertises the correct flow control settings */ | |
979 | rc = efx->phy_op->reconfigure(efx); | |
980 | if (rc) | |
981 | goto fail2; | |
982 | ||
1dfc5cea | 983 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 984 | return 0; |
177dfcd8 | 985 | |
1dfc5cea | 986 | fail2: |
177dfcd8 | 987 | efx->phy_op->fini(efx); |
1dfc5cea BH |
988 | fail1: |
989 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 990 | return rc; |
8ceee660 BH |
991 | } |
992 | ||
8ceee660 BH |
993 | static void efx_start_port(struct efx_nic *efx) |
994 | { | |
62776d03 | 995 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
996 | BUG_ON(efx->port_enabled); |
997 | ||
998 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 999 | efx->port_enabled = true; |
8be4f3e6 BH |
1000 | |
1001 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
1002 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 1003 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
1004 | efx->mac_op->reconfigure(efx); |
1005 | ||
8ceee660 BH |
1006 | mutex_unlock(&efx->mac_lock); |
1007 | } | |
1008 | ||
fdaa9aed | 1009 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
1010 | static void efx_stop_port(struct efx_nic *efx) |
1011 | { | |
62776d03 | 1012 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
1013 | |
1014 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 1015 | efx->port_enabled = false; |
8ceee660 BH |
1016 | mutex_unlock(&efx->mac_lock); |
1017 | ||
1018 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 1019 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
1020 | netif_addr_lock_bh(efx->net_dev); |
1021 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
1022 | } |
1023 | } | |
1024 | ||
1025 | static void efx_fini_port(struct efx_nic *efx) | |
1026 | { | |
62776d03 | 1027 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
1028 | |
1029 | if (!efx->port_initialized) | |
1030 | return; | |
1031 | ||
177dfcd8 | 1032 | efx->phy_op->fini(efx); |
dc8cfa55 | 1033 | efx->port_initialized = false; |
8ceee660 | 1034 | |
eb50c0d6 | 1035 | efx->link_state.up = false; |
8ceee660 BH |
1036 | efx_link_status_changed(efx); |
1037 | } | |
1038 | ||
1039 | static void efx_remove_port(struct efx_nic *efx) | |
1040 | { | |
62776d03 | 1041 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 1042 | |
ef2b90ee | 1043 | efx->type->remove_port(efx); |
8ceee660 BH |
1044 | } |
1045 | ||
1046 | /************************************************************************** | |
1047 | * | |
1048 | * NIC handling | |
1049 | * | |
1050 | **************************************************************************/ | |
1051 | ||
1052 | /* This configures the PCI device to enable I/O and DMA. */ | |
1053 | static int efx_init_io(struct efx_nic *efx) | |
1054 | { | |
1055 | struct pci_dev *pci_dev = efx->pci_dev; | |
1056 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
d88d6b05 | 1057 | bool use_wc; |
8ceee660 BH |
1058 | int rc; |
1059 | ||
62776d03 | 1060 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
1061 | |
1062 | rc = pci_enable_device(pci_dev); | |
1063 | if (rc) { | |
62776d03 BH |
1064 | netif_err(efx, probe, efx->net_dev, |
1065 | "failed to enable PCI device\n"); | |
8ceee660 BH |
1066 | goto fail1; |
1067 | } | |
1068 | ||
1069 | pci_set_master(pci_dev); | |
1070 | ||
1071 | /* Set the PCI DMA mask. Try all possibilities from our | |
1072 | * genuine mask down to 32 bits, because some architectures | |
1073 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
1074 | * masks event though they reject 46 bit masks. | |
1075 | */ | |
1076 | while (dma_mask > 0x7fffffffUL) { | |
1077 | if (pci_dma_supported(pci_dev, dma_mask) && | |
1078 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
1079 | break; | |
1080 | dma_mask >>= 1; | |
1081 | } | |
1082 | if (rc) { | |
62776d03 BH |
1083 | netif_err(efx, probe, efx->net_dev, |
1084 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
1085 | goto fail2; |
1086 | } | |
62776d03 BH |
1087 | netif_dbg(efx, probe, efx->net_dev, |
1088 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
1089 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
1090 | if (rc) { | |
1091 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
1092 | * fail with a mask that pci_set_dma_mask() accepted, | |
1093 | * but just in case... | |
1094 | */ | |
62776d03 BH |
1095 | netif_err(efx, probe, efx->net_dev, |
1096 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
1097 | goto fail2; |
1098 | } | |
1099 | ||
dc803df8 BH |
1100 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
1101 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 1102 | if (rc) { |
62776d03 BH |
1103 | netif_err(efx, probe, efx->net_dev, |
1104 | "request for memory BAR failed\n"); | |
8ceee660 BH |
1105 | rc = -EIO; |
1106 | goto fail3; | |
1107 | } | |
d88d6b05 SH |
1108 | |
1109 | /* bug22643: If SR-IOV is enabled then tx push over a write combined | |
1110 | * mapping is unsafe. We need to disable write combining in this case. | |
1111 | * MSI is unsupported when SR-IOV is enabled, and the firmware will | |
1112 | * have removed the MSI capability. So write combining is safe if | |
1113 | * there is an MSI capability. | |
1114 | */ | |
1115 | use_wc = (!EFX_WORKAROUND_22643(efx) || | |
1116 | pci_find_capability(pci_dev, PCI_CAP_ID_MSI)); | |
1117 | if (use_wc) | |
1118 | efx->membase = ioremap_wc(efx->membase_phys, | |
1119 | efx->type->mem_map_size); | |
1120 | else | |
1121 | efx->membase = ioremap_nocache(efx->membase_phys, | |
1122 | efx->type->mem_map_size); | |
8ceee660 | 1123 | if (!efx->membase) { |
62776d03 BH |
1124 | netif_err(efx, probe, efx->net_dev, |
1125 | "could not map memory BAR at %llx+%x\n", | |
1126 | (unsigned long long)efx->membase_phys, | |
1127 | efx->type->mem_map_size); | |
8ceee660 BH |
1128 | rc = -ENOMEM; |
1129 | goto fail4; | |
1130 | } | |
62776d03 BH |
1131 | netif_dbg(efx, probe, efx->net_dev, |
1132 | "memory BAR at %llx+%x (virtual %p)\n", | |
1133 | (unsigned long long)efx->membase_phys, | |
1134 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
1135 | |
1136 | return 0; | |
1137 | ||
1138 | fail4: | |
dc803df8 | 1139 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 1140 | fail3: |
2c118e0f | 1141 | efx->membase_phys = 0; |
8ceee660 BH |
1142 | fail2: |
1143 | pci_disable_device(efx->pci_dev); | |
1144 | fail1: | |
1145 | return rc; | |
1146 | } | |
1147 | ||
1148 | static void efx_fini_io(struct efx_nic *efx) | |
1149 | { | |
62776d03 | 1150 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
1151 | |
1152 | if (efx->membase) { | |
1153 | iounmap(efx->membase); | |
1154 | efx->membase = NULL; | |
1155 | } | |
1156 | ||
1157 | if (efx->membase_phys) { | |
dc803df8 | 1158 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 1159 | efx->membase_phys = 0; |
8ceee660 BH |
1160 | } |
1161 | ||
1162 | pci_disable_device(efx->pci_dev); | |
1163 | } | |
1164 | ||
a4900ac9 BH |
1165 | /* Get number of channels wanted. Each channel will have its own IRQ, |
1166 | * 1 RX queue and/or 2 TX queues. */ | |
1167 | static int efx_wanted_channels(void) | |
46123d04 | 1168 | { |
2f8975fb | 1169 | cpumask_var_t core_mask; |
46123d04 BH |
1170 | int count; |
1171 | int cpu; | |
5b874e25 BH |
1172 | |
1173 | if (rss_cpus) | |
1174 | return rss_cpus; | |
46123d04 | 1175 | |
79f55997 | 1176 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 1177 | printk(KERN_WARNING |
3977d033 | 1178 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1179 | return 1; |
1180 | } | |
1181 | ||
46123d04 BH |
1182 | count = 0; |
1183 | for_each_online_cpu(cpu) { | |
2f8975fb | 1184 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 1185 | ++count; |
2f8975fb | 1186 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 1187 | topology_core_cpumask(cpu)); |
46123d04 BH |
1188 | } |
1189 | } | |
1190 | ||
2f8975fb | 1191 | free_cpumask_var(core_mask); |
46123d04 BH |
1192 | return count; |
1193 | } | |
1194 | ||
64d8ad6d BH |
1195 | static int |
1196 | efx_init_rx_cpu_rmap(struct efx_nic *efx, struct msix_entry *xentries) | |
1197 | { | |
1198 | #ifdef CONFIG_RFS_ACCEL | |
1199 | int i, rc; | |
1200 | ||
1201 | efx->net_dev->rx_cpu_rmap = alloc_irq_cpu_rmap(efx->n_rx_channels); | |
1202 | if (!efx->net_dev->rx_cpu_rmap) | |
1203 | return -ENOMEM; | |
1204 | for (i = 0; i < efx->n_rx_channels; i++) { | |
1205 | rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap, | |
1206 | xentries[i].vector); | |
1207 | if (rc) { | |
1208 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
1209 | efx->net_dev->rx_cpu_rmap = NULL; | |
1210 | return rc; | |
1211 | } | |
1212 | } | |
1213 | #endif | |
1214 | return 0; | |
1215 | } | |
1216 | ||
46123d04 BH |
1217 | /* Probe the number and type of interrupts we are able to obtain, and |
1218 | * the resulting numbers of channels and RX queues. | |
1219 | */ | |
64d8ad6d | 1220 | static int efx_probe_interrupts(struct efx_nic *efx) |
8ceee660 | 1221 | { |
46123d04 BH |
1222 | int max_channels = |
1223 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1224 | int rc, i; |
1225 | ||
1226 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1227 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1228 | int n_channels; |
aa6ef27e | 1229 | |
a4900ac9 BH |
1230 | n_channels = efx_wanted_channels(); |
1231 | if (separate_tx_channels) | |
1232 | n_channels *= 2; | |
1233 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1234 | |
a4900ac9 | 1235 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1236 | xentries[i].entry = i; |
a4900ac9 | 1237 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1238 | if (rc > 0) { |
62776d03 BH |
1239 | netif_err(efx, drv, efx->net_dev, |
1240 | "WARNING: Insufficient MSI-X vectors" | |
1241 | " available (%d < %d).\n", rc, n_channels); | |
1242 | netif_err(efx, drv, efx->net_dev, | |
1243 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1244 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1245 | n_channels = rc; | |
8ceee660 | 1246 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1247 | n_channels); |
8ceee660 BH |
1248 | } |
1249 | ||
1250 | if (rc == 0) { | |
a4900ac9 BH |
1251 | efx->n_channels = n_channels; |
1252 | if (separate_tx_channels) { | |
1253 | efx->n_tx_channels = | |
1254 | max(efx->n_channels / 2, 1U); | |
1255 | efx->n_rx_channels = | |
1256 | max(efx->n_channels - | |
1257 | efx->n_tx_channels, 1U); | |
1258 | } else { | |
1259 | efx->n_tx_channels = efx->n_channels; | |
1260 | efx->n_rx_channels = efx->n_channels; | |
1261 | } | |
64d8ad6d BH |
1262 | rc = efx_init_rx_cpu_rmap(efx, xentries); |
1263 | if (rc) { | |
1264 | pci_disable_msix(efx->pci_dev); | |
1265 | return rc; | |
1266 | } | |
a4900ac9 | 1267 | for (i = 0; i < n_channels; i++) |
f7d12cdc BH |
1268 | efx_get_channel(efx, i)->irq = |
1269 | xentries[i].vector; | |
8ceee660 BH |
1270 | } else { |
1271 | /* Fall back to single channel MSI */ | |
1272 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1273 | netif_err(efx, drv, efx->net_dev, |
1274 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1275 | } |
1276 | } | |
1277 | ||
1278 | /* Try single interrupt MSI */ | |
1279 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1280 | efx->n_channels = 1; |
a4900ac9 BH |
1281 | efx->n_rx_channels = 1; |
1282 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1283 | rc = pci_enable_msi(efx->pci_dev); |
1284 | if (rc == 0) { | |
f7d12cdc | 1285 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1286 | } else { |
62776d03 BH |
1287 | netif_err(efx, drv, efx->net_dev, |
1288 | "could not enable MSI\n"); | |
8ceee660 BH |
1289 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1290 | } | |
1291 | } | |
1292 | ||
1293 | /* Assume legacy interrupts */ | |
1294 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1295 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1296 | efx->n_rx_channels = 1; |
1297 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1298 | efx->legacy_irq = efx->pci_dev->irq; |
1299 | } | |
64d8ad6d BH |
1300 | |
1301 | return 0; | |
8ceee660 BH |
1302 | } |
1303 | ||
1304 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1305 | { | |
1306 | struct efx_channel *channel; | |
1307 | ||
1308 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1309 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1310 | channel->irq = 0; |
1311 | pci_disable_msi(efx->pci_dev); | |
1312 | pci_disable_msix(efx->pci_dev); | |
1313 | ||
1314 | /* Remove legacy interrupt */ | |
1315 | efx->legacy_irq = 0; | |
1316 | } | |
1317 | ||
8831da7b | 1318 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1319 | { |
97653431 | 1320 | efx->tx_channel_offset = |
a4900ac9 | 1321 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; |
8ceee660 BH |
1322 | } |
1323 | ||
1324 | static int efx_probe_nic(struct efx_nic *efx) | |
1325 | { | |
765c9f46 | 1326 | size_t i; |
8ceee660 BH |
1327 | int rc; |
1328 | ||
62776d03 | 1329 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1330 | |
1331 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1332 | rc = efx->type->probe(efx); |
8ceee660 BH |
1333 | if (rc) |
1334 | return rc; | |
1335 | ||
a4900ac9 | 1336 | /* Determine the number of channels and queues by trying to hook |
8ceee660 | 1337 | * in MSI-X interrupts. */ |
64d8ad6d BH |
1338 | rc = efx_probe_interrupts(efx); |
1339 | if (rc) | |
1340 | goto fail; | |
8ceee660 | 1341 | |
5d3a6fca BH |
1342 | if (efx->n_channels > 1) |
1343 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 BH |
1344 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
1345 | efx->rx_indir_table[i] = i % efx->n_rx_channels; | |
5d3a6fca | 1346 | |
8831da7b | 1347 | efx_set_channels(efx); |
c4f4adc7 BH |
1348 | netif_set_real_num_tx_queues(efx->net_dev, efx->n_tx_channels); |
1349 | netif_set_real_num_rx_queues(efx->net_dev, efx->n_rx_channels); | |
8ceee660 BH |
1350 | |
1351 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1352 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1353 | |
1354 | return 0; | |
64d8ad6d BH |
1355 | |
1356 | fail: | |
1357 | efx->type->remove(efx); | |
1358 | return rc; | |
8ceee660 BH |
1359 | } |
1360 | ||
1361 | static void efx_remove_nic(struct efx_nic *efx) | |
1362 | { | |
62776d03 | 1363 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1364 | |
1365 | efx_remove_interrupts(efx); | |
ef2b90ee | 1366 | efx->type->remove(efx); |
8ceee660 BH |
1367 | } |
1368 | ||
1369 | /************************************************************************** | |
1370 | * | |
1371 | * NIC startup/shutdown | |
1372 | * | |
1373 | *************************************************************************/ | |
1374 | ||
1375 | static int efx_probe_all(struct efx_nic *efx) | |
1376 | { | |
8ceee660 BH |
1377 | int rc; |
1378 | ||
8ceee660 BH |
1379 | rc = efx_probe_nic(efx); |
1380 | if (rc) { | |
62776d03 | 1381 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1382 | goto fail1; |
1383 | } | |
1384 | ||
8ceee660 BH |
1385 | rc = efx_probe_port(efx); |
1386 | if (rc) { | |
62776d03 | 1387 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1388 | goto fail2; |
1389 | } | |
1390 | ||
ecc910f5 | 1391 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
4642610c BH |
1392 | rc = efx_probe_channels(efx); |
1393 | if (rc) | |
1394 | goto fail3; | |
8ceee660 | 1395 | |
64eebcfd BH |
1396 | rc = efx_probe_filters(efx); |
1397 | if (rc) { | |
1398 | netif_err(efx, probe, efx->net_dev, | |
1399 | "failed to create filter tables\n"); | |
1400 | goto fail4; | |
1401 | } | |
1402 | ||
8ceee660 BH |
1403 | return 0; |
1404 | ||
64eebcfd BH |
1405 | fail4: |
1406 | efx_remove_channels(efx); | |
8ceee660 | 1407 | fail3: |
8ceee660 BH |
1408 | efx_remove_port(efx); |
1409 | fail2: | |
1410 | efx_remove_nic(efx); | |
1411 | fail1: | |
1412 | return rc; | |
1413 | } | |
1414 | ||
1415 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1416 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1417 | * and ensures that the port is scheduled to be reconfigured. | |
1418 | * This function is safe to call multiple times when the NIC is in any | |
1419 | * state. */ | |
1420 | static void efx_start_all(struct efx_nic *efx) | |
1421 | { | |
1422 | struct efx_channel *channel; | |
1423 | ||
1424 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1425 | ||
1426 | /* Check that it is appropriate to restart the interface. All | |
1427 | * of these flags are safe to read under just the rtnl lock */ | |
1428 | if (efx->port_enabled) | |
1429 | return; | |
1430 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1431 | return; | |
55668611 | 1432 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1433 | return; |
1434 | ||
1435 | /* Mark the port as enabled so port reconfigurations can start, then | |
1436 | * restart the transmit interface early so the watchdog timer stops */ | |
1437 | efx_start_port(efx); | |
8ceee660 | 1438 | |
9d1aea62 | 1439 | if (efx_dev_registered(efx) && !efx->port_inhibited) |
c04bfc6b BH |
1440 | netif_tx_wake_all_queues(efx->net_dev); |
1441 | ||
1442 | efx_for_each_channel(channel, efx) | |
8ceee660 BH |
1443 | efx_start_channel(channel); |
1444 | ||
94dec6a2 BH |
1445 | if (efx->legacy_irq) |
1446 | efx->legacy_irq_enabled = true; | |
152b6a62 | 1447 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1448 | |
8880f4ec BH |
1449 | /* Switch to event based MCDI completions after enabling interrupts. |
1450 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1451 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1452 | * reset_pending [modified from an atomic context], we instead guarantee | |
1453 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1454 | efx_mcdi_mode_event(efx); | |
1455 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1456 | efx_mcdi_mode_poll(efx); | |
1457 | ||
78c1f0a0 SH |
1458 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1459 | * event driven), we have to poll the PHY because after an event queue | |
1460 | * flush, we could have a missed a link state change */ | |
1461 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1462 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1463 | efx_monitor_interval); | |
78c1f0a0 SH |
1464 | } else { |
1465 | mutex_lock(&efx->mac_lock); | |
1466 | if (efx->phy_op->poll(efx)) | |
1467 | efx_link_status_changed(efx); | |
1468 | mutex_unlock(&efx->mac_lock); | |
1469 | } | |
55edc6e6 | 1470 | |
ef2b90ee | 1471 | efx->type->start_stats(efx); |
8ceee660 BH |
1472 | } |
1473 | ||
1474 | /* Flush all delayed work. Should only be called when no more delayed work | |
1475 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1476 | * since we're holding the rtnl_lock at this point. */ | |
1477 | static void efx_flush_all(struct efx_nic *efx) | |
1478 | { | |
8ceee660 BH |
1479 | /* Make sure the hardware monitor is stopped */ |
1480 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1481 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1482 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1483 | } |
1484 | ||
1485 | /* Quiesce hardware and software without bringing the link down. | |
1486 | * Safe to call multiple times, when the nic and interface is in any | |
1487 | * state. The caller is guaranteed to subsequently be in a position | |
1488 | * to modify any hardware and software state they see fit without | |
1489 | * taking locks. */ | |
1490 | static void efx_stop_all(struct efx_nic *efx) | |
1491 | { | |
1492 | struct efx_channel *channel; | |
1493 | ||
1494 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1495 | ||
1496 | /* port_enabled can be read safely under the rtnl lock */ | |
1497 | if (!efx->port_enabled) | |
1498 | return; | |
1499 | ||
ef2b90ee | 1500 | efx->type->stop_stats(efx); |
55edc6e6 | 1501 | |
8880f4ec BH |
1502 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1503 | efx_mcdi_mode_poll(efx); | |
1504 | ||
8ceee660 | 1505 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1506 | efx_nic_disable_interrupts(efx); |
94dec6a2 | 1507 | if (efx->legacy_irq) { |
8ceee660 | 1508 | synchronize_irq(efx->legacy_irq); |
94dec6a2 BH |
1509 | efx->legacy_irq_enabled = false; |
1510 | } | |
64ee3120 | 1511 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1512 | if (channel->irq) |
1513 | synchronize_irq(channel->irq); | |
b3475645 | 1514 | } |
8ceee660 BH |
1515 | |
1516 | /* Stop all NAPI processing and synchronous rx refills */ | |
1517 | efx_for_each_channel(channel, efx) | |
1518 | efx_stop_channel(channel); | |
1519 | ||
1520 | /* Stop all asynchronous port reconfigurations. Since all | |
1521 | * event processing has already been stopped, there is no | |
1522 | * window to loose phy events */ | |
1523 | efx_stop_port(efx); | |
1524 | ||
fdaa9aed | 1525 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1526 | efx_flush_all(efx); |
1527 | ||
8ceee660 BH |
1528 | /* Stop the kernel transmit interface late, so the watchdog |
1529 | * timer isn't ticking over the flush */ | |
55668611 | 1530 | if (efx_dev_registered(efx)) { |
c04bfc6b | 1531 | netif_tx_stop_all_queues(efx->net_dev); |
8ceee660 BH |
1532 | netif_tx_lock_bh(efx->net_dev); |
1533 | netif_tx_unlock_bh(efx->net_dev); | |
1534 | } | |
1535 | } | |
1536 | ||
1537 | static void efx_remove_all(struct efx_nic *efx) | |
1538 | { | |
64eebcfd | 1539 | efx_remove_filters(efx); |
4642610c | 1540 | efx_remove_channels(efx); |
8ceee660 BH |
1541 | efx_remove_port(efx); |
1542 | efx_remove_nic(efx); | |
1543 | } | |
1544 | ||
8ceee660 BH |
1545 | /************************************************************************** |
1546 | * | |
1547 | * Interrupt moderation | |
1548 | * | |
1549 | **************************************************************************/ | |
1550 | ||
0d86ebd8 BH |
1551 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1552 | { | |
1553 | if (usecs <= 0) | |
1554 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1555 | if (usecs < resolution) | |
1556 | return 1; /* never round down to 0 */ | |
1557 | return usecs / resolution; | |
1558 | } | |
1559 | ||
8ceee660 | 1560 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1561 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1562 | bool rx_adaptive) | |
8ceee660 | 1563 | { |
f7d12cdc | 1564 | struct efx_channel *channel; |
152b6a62 BH |
1565 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1566 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1567 | |
1568 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1569 | ||
6fb70fd1 | 1570 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1571 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc | 1572 | efx_for_each_channel(channel, efx) { |
525da907 | 1573 | if (efx_channel_has_rx_queue(channel)) |
f7d12cdc | 1574 | channel->irq_moderation = rx_ticks; |
525da907 | 1575 | else if (efx_channel_has_tx_queues(channel)) |
f7d12cdc BH |
1576 | channel->irq_moderation = tx_ticks; |
1577 | } | |
8ceee660 BH |
1578 | } |
1579 | ||
1580 | /************************************************************************** | |
1581 | * | |
1582 | * Hardware monitor | |
1583 | * | |
1584 | **************************************************************************/ | |
1585 | ||
e254c274 | 1586 | /* Run periodically off the general workqueue */ |
8ceee660 BH |
1587 | static void efx_monitor(struct work_struct *data) |
1588 | { | |
1589 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1590 | monitor_work.work); | |
8ceee660 | 1591 | |
62776d03 BH |
1592 | netif_vdbg(efx, timer, efx->net_dev, |
1593 | "hardware monitor executing on CPU %d\n", | |
1594 | raw_smp_processor_id()); | |
ef2b90ee | 1595 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1596 | |
8ceee660 BH |
1597 | /* If the mac_lock is already held then it is likely a port |
1598 | * reconfiguration is already in place, which will likely do | |
e254c274 BH |
1599 | * most of the work of monitor() anyway. */ |
1600 | if (mutex_trylock(&efx->mac_lock)) { | |
1601 | if (efx->port_enabled) | |
1602 | efx->type->monitor(efx); | |
1603 | mutex_unlock(&efx->mac_lock); | |
1604 | } | |
8ceee660 | 1605 | |
8ceee660 BH |
1606 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1607 | efx_monitor_interval); | |
1608 | } | |
1609 | ||
1610 | /************************************************************************** | |
1611 | * | |
1612 | * ioctls | |
1613 | * | |
1614 | *************************************************************************/ | |
1615 | ||
1616 | /* Net device ioctl | |
1617 | * Context: process, rtnl_lock() held. | |
1618 | */ | |
1619 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1620 | { | |
767e468c | 1621 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1622 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1623 | |
1624 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1625 | ||
68e7f45e BH |
1626 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1627 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1628 | (data->phy_id & 0xfc00) == 0x0400) | |
1629 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1630 | ||
1631 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1632 | } |
1633 | ||
1634 | /************************************************************************** | |
1635 | * | |
1636 | * NAPI interface | |
1637 | * | |
1638 | **************************************************************************/ | |
1639 | ||
e8f14992 | 1640 | static void efx_init_napi(struct efx_nic *efx) |
8ceee660 BH |
1641 | { |
1642 | struct efx_channel *channel; | |
8ceee660 BH |
1643 | |
1644 | efx_for_each_channel(channel, efx) { | |
1645 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1646 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1647 | efx_poll, napi_weight); | |
8ceee660 | 1648 | } |
e8f14992 BH |
1649 | } |
1650 | ||
1651 | static void efx_fini_napi_channel(struct efx_channel *channel) | |
1652 | { | |
1653 | if (channel->napi_dev) | |
1654 | netif_napi_del(&channel->napi_str); | |
1655 | channel->napi_dev = NULL; | |
8ceee660 BH |
1656 | } |
1657 | ||
1658 | static void efx_fini_napi(struct efx_nic *efx) | |
1659 | { | |
1660 | struct efx_channel *channel; | |
1661 | ||
e8f14992 BH |
1662 | efx_for_each_channel(channel, efx) |
1663 | efx_fini_napi_channel(channel); | |
8ceee660 BH |
1664 | } |
1665 | ||
1666 | /************************************************************************** | |
1667 | * | |
1668 | * Kernel netpoll interface | |
1669 | * | |
1670 | *************************************************************************/ | |
1671 | ||
1672 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1673 | ||
1674 | /* Although in the common case interrupts will be disabled, this is not | |
1675 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1676 | * so no locking is required. | |
1677 | */ | |
1678 | static void efx_netpoll(struct net_device *net_dev) | |
1679 | { | |
767e468c | 1680 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1681 | struct efx_channel *channel; |
1682 | ||
64ee3120 | 1683 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1684 | efx_schedule_channel(channel); |
1685 | } | |
1686 | ||
1687 | #endif | |
1688 | ||
1689 | /************************************************************************** | |
1690 | * | |
1691 | * Kernel net device interface | |
1692 | * | |
1693 | *************************************************************************/ | |
1694 | ||
1695 | /* Context: process, rtnl_lock() held. */ | |
1696 | static int efx_net_open(struct net_device *net_dev) | |
1697 | { | |
767e468c | 1698 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1699 | EFX_ASSERT_RESET_SERIALISED(efx); |
1700 | ||
62776d03 BH |
1701 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1702 | raw_smp_processor_id()); | |
8ceee660 | 1703 | |
f4bd954e BH |
1704 | if (efx->state == STATE_DISABLED) |
1705 | return -EIO; | |
f8b87c17 BH |
1706 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1707 | return -EBUSY; | |
8880f4ec BH |
1708 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1709 | return -EIO; | |
f8b87c17 | 1710 | |
78c1f0a0 SH |
1711 | /* Notify the kernel of the link state polled during driver load, |
1712 | * before the monitor starts running */ | |
1713 | efx_link_status_changed(efx); | |
1714 | ||
8ceee660 BH |
1715 | efx_start_all(efx); |
1716 | return 0; | |
1717 | } | |
1718 | ||
1719 | /* Context: process, rtnl_lock() held. | |
1720 | * Note that the kernel will ignore our return code; this method | |
1721 | * should really be a void. | |
1722 | */ | |
1723 | static int efx_net_stop(struct net_device *net_dev) | |
1724 | { | |
767e468c | 1725 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1726 | |
62776d03 BH |
1727 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1728 | raw_smp_processor_id()); | |
8ceee660 | 1729 | |
f4bd954e BH |
1730 | if (efx->state != STATE_DISABLED) { |
1731 | /* Stop the device and flush all the channels */ | |
1732 | efx_stop_all(efx); | |
1733 | efx_fini_channels(efx); | |
1734 | efx_init_channels(efx); | |
1735 | } | |
8ceee660 BH |
1736 | |
1737 | return 0; | |
1738 | } | |
1739 | ||
5b9e207c | 1740 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
28172739 | 1741 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats) |
8ceee660 | 1742 | { |
767e468c | 1743 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1744 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1745 | |
55edc6e6 | 1746 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1747 | efx->type->update_stats(efx); |
55edc6e6 | 1748 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1749 | |
1750 | stats->rx_packets = mac_stats->rx_packets; | |
1751 | stats->tx_packets = mac_stats->tx_packets; | |
1752 | stats->rx_bytes = mac_stats->rx_bytes; | |
1753 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1754 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1755 | stats->multicast = mac_stats->rx_multicast; |
1756 | stats->collisions = mac_stats->tx_collision; | |
1757 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1758 | mac_stats->rx_length_error); | |
8ceee660 BH |
1759 | stats->rx_crc_errors = mac_stats->rx_bad; |
1760 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1761 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1762 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1763 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1764 | ||
1765 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1766 | stats->rx_crc_errors + |
1767 | stats->rx_frame_errors + | |
8ceee660 BH |
1768 | mac_stats->rx_symbol_error); |
1769 | stats->tx_errors = (stats->tx_window_errors + | |
1770 | mac_stats->tx_bad); | |
1771 | ||
1772 | return stats; | |
1773 | } | |
1774 | ||
1775 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1776 | static void efx_watchdog(struct net_device *net_dev) | |
1777 | { | |
767e468c | 1778 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1779 | |
62776d03 BH |
1780 | netif_err(efx, tx_err, efx->net_dev, |
1781 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1782 | efx->port_enabled); | |
8ceee660 | 1783 | |
739bb23d | 1784 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1785 | } |
1786 | ||
1787 | ||
1788 | /* Context: process, rtnl_lock() held. */ | |
1789 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1790 | { | |
767e468c | 1791 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1792 | int rc = 0; |
1793 | ||
1794 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1795 | ||
1796 | if (new_mtu > EFX_MAX_MTU) | |
1797 | return -EINVAL; | |
1798 | ||
1799 | efx_stop_all(efx); | |
1800 | ||
62776d03 | 1801 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 BH |
1802 | |
1803 | efx_fini_channels(efx); | |
d3245b28 BH |
1804 | |
1805 | mutex_lock(&efx->mac_lock); | |
1806 | /* Reconfigure the MAC before enabling the dma queues so that | |
1807 | * the RX buffers don't overflow */ | |
8ceee660 | 1808 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1809 | efx->mac_op->reconfigure(efx); |
1810 | mutex_unlock(&efx->mac_lock); | |
1811 | ||
bc3c90a2 | 1812 | efx_init_channels(efx); |
8ceee660 BH |
1813 | |
1814 | efx_start_all(efx); | |
1815 | return rc; | |
8ceee660 BH |
1816 | } |
1817 | ||
1818 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1819 | { | |
767e468c | 1820 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1821 | struct sockaddr *addr = data; |
1822 | char *new_addr = addr->sa_data; | |
1823 | ||
1824 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1825 | ||
1826 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1827 | netif_err(efx, drv, efx->net_dev, |
1828 | "invalid ethernet MAC address requested: %pM\n", | |
1829 | new_addr); | |
8ceee660 BH |
1830 | return -EINVAL; |
1831 | } | |
1832 | ||
1833 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1834 | ||
1835 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1836 | mutex_lock(&efx->mac_lock); |
1837 | efx->mac_op->reconfigure(efx); | |
1838 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1839 | |
1840 | return 0; | |
1841 | } | |
1842 | ||
a816f75a | 1843 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1844 | static void efx_set_multicast_list(struct net_device *net_dev) |
1845 | { | |
767e468c | 1846 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1847 | struct netdev_hw_addr *ha; |
8ceee660 | 1848 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1849 | u32 crc; |
1850 | int bit; | |
8ceee660 | 1851 | |
8be4f3e6 | 1852 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1853 | |
1854 | /* Build multicast hash table */ | |
8be4f3e6 | 1855 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1856 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1857 | } else { | |
1858 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1859 | netdev_for_each_mc_addr(ha, net_dev) { |
1860 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1861 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1862 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1863 | } |
8ceee660 | 1864 | |
8be4f3e6 BH |
1865 | /* Broadcast packets go through the multicast hash filter. |
1866 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1867 | * so we always add bit 0xff to the mask. | |
1868 | */ | |
1869 | set_bit_le(0xff, mc_hash->byte); | |
1870 | } | |
a816f75a | 1871 | |
8be4f3e6 BH |
1872 | if (efx->port_enabled) |
1873 | queue_work(efx->workqueue, &efx->mac_work); | |
1874 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1875 | } |
1876 | ||
c3ecb9f3 SH |
1877 | static const struct net_device_ops efx_netdev_ops = { |
1878 | .ndo_open = efx_net_open, | |
1879 | .ndo_stop = efx_net_stop, | |
4472702e | 1880 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1881 | .ndo_tx_timeout = efx_watchdog, |
1882 | .ndo_start_xmit = efx_hard_start_xmit, | |
1883 | .ndo_validate_addr = eth_validate_addr, | |
1884 | .ndo_do_ioctl = efx_ioctl, | |
1885 | .ndo_change_mtu = efx_change_mtu, | |
1886 | .ndo_set_mac_address = efx_set_mac_address, | |
1887 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1888 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1889 | .ndo_poll_controller = efx_netpoll, | |
1890 | #endif | |
94b274bf | 1891 | .ndo_setup_tc = efx_setup_tc, |
64d8ad6d BH |
1892 | #ifdef CONFIG_RFS_ACCEL |
1893 | .ndo_rx_flow_steer = efx_filter_rfs, | |
1894 | #endif | |
c3ecb9f3 SH |
1895 | }; |
1896 | ||
7dde596e BH |
1897 | static void efx_update_name(struct efx_nic *efx) |
1898 | { | |
1899 | strcpy(efx->name, efx->net_dev->name); | |
1900 | efx_mtd_rename(efx); | |
1901 | efx_set_channel_names(efx); | |
1902 | } | |
1903 | ||
8ceee660 BH |
1904 | static int efx_netdev_event(struct notifier_block *this, |
1905 | unsigned long event, void *ptr) | |
1906 | { | |
d3208b5e | 1907 | struct net_device *net_dev = ptr; |
8ceee660 | 1908 | |
7dde596e BH |
1909 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1910 | event == NETDEV_CHANGENAME) | |
1911 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1912 | |
1913 | return NOTIFY_DONE; | |
1914 | } | |
1915 | ||
1916 | static struct notifier_block efx_netdev_notifier = { | |
1917 | .notifier_call = efx_netdev_event, | |
1918 | }; | |
1919 | ||
06d5e193 BH |
1920 | static ssize_t |
1921 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1922 | { | |
1923 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1924 | return sprintf(buf, "%d\n", efx->phy_type); | |
1925 | } | |
1926 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1927 | ||
8ceee660 BH |
1928 | static int efx_register_netdev(struct efx_nic *efx) |
1929 | { | |
1930 | struct net_device *net_dev = efx->net_dev; | |
c04bfc6b | 1931 | struct efx_channel *channel; |
8ceee660 BH |
1932 | int rc; |
1933 | ||
1934 | net_dev->watchdog_timeo = 5 * HZ; | |
1935 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1936 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1937 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1938 | ||
8ceee660 | 1939 | /* Clear MAC statistics */ |
177dfcd8 | 1940 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1941 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1942 | ||
7dde596e | 1943 | rtnl_lock(); |
aed0628d BH |
1944 | |
1945 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1946 | if (rc < 0) | |
1947 | goto fail_locked; | |
7dde596e | 1948 | efx_update_name(efx); |
aed0628d BH |
1949 | |
1950 | rc = register_netdevice(net_dev); | |
1951 | if (rc) | |
1952 | goto fail_locked; | |
1953 | ||
c04bfc6b BH |
1954 | efx_for_each_channel(channel, efx) { |
1955 | struct efx_tx_queue *tx_queue; | |
60031fcc BH |
1956 | efx_for_each_channel_tx_queue(tx_queue, channel) |
1957 | efx_init_tx_queue_core_txq(tx_queue); | |
c04bfc6b BH |
1958 | } |
1959 | ||
aed0628d BH |
1960 | /* Always start with carrier off; PHY events will detect the link */ |
1961 | netif_carrier_off(efx->net_dev); | |
1962 | ||
7dde596e | 1963 | rtnl_unlock(); |
8ceee660 | 1964 | |
06d5e193 BH |
1965 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1966 | if (rc) { | |
62776d03 BH |
1967 | netif_err(efx, drv, efx->net_dev, |
1968 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1969 | goto fail_registered; |
1970 | } | |
1971 | ||
8ceee660 | 1972 | return 0; |
06d5e193 | 1973 | |
aed0628d BH |
1974 | fail_locked: |
1975 | rtnl_unlock(); | |
62776d03 | 1976 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1977 | return rc; |
1978 | ||
06d5e193 BH |
1979 | fail_registered: |
1980 | unregister_netdev(net_dev); | |
1981 | return rc; | |
8ceee660 BH |
1982 | } |
1983 | ||
1984 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1985 | { | |
f7d12cdc | 1986 | struct efx_channel *channel; |
8ceee660 BH |
1987 | struct efx_tx_queue *tx_queue; |
1988 | ||
1989 | if (!efx->net_dev) | |
1990 | return; | |
1991 | ||
767e468c | 1992 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1993 | |
1994 | /* Free up any skbs still remaining. This has to happen before | |
1995 | * we try to unregister the netdev as running their destructors | |
1996 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
1997 | efx_for_each_channel(channel, efx) { |
1998 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1999 | efx_release_tx_buffers(tx_queue); | |
2000 | } | |
8ceee660 | 2001 | |
55668611 | 2002 | if (efx_dev_registered(efx)) { |
8ceee660 | 2003 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 2004 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
2005 | unregister_netdev(efx->net_dev); |
2006 | } | |
2007 | } | |
2008 | ||
2009 | /************************************************************************** | |
2010 | * | |
2011 | * Device reset and suspend | |
2012 | * | |
2013 | **************************************************************************/ | |
2014 | ||
2467ca46 BH |
2015 | /* Tears down the entire software state and most of the hardware state |
2016 | * before reset. */ | |
d3245b28 | 2017 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2018 | { |
8ceee660 BH |
2019 | EFX_ASSERT_RESET_SERIALISED(efx); |
2020 | ||
2467ca46 BH |
2021 | efx_stop_all(efx); |
2022 | mutex_lock(&efx->mac_lock); | |
2023 | ||
8ceee660 | 2024 | efx_fini_channels(efx); |
4b988280 SH |
2025 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
2026 | efx->phy_op->fini(efx); | |
ef2b90ee | 2027 | efx->type->fini(efx); |
8ceee660 BH |
2028 | } |
2029 | ||
2467ca46 BH |
2030 | /* This function will always ensure that the locks acquired in |
2031 | * efx_reset_down() are released. A failure return code indicates | |
2032 | * that we were unable to reinitialise the hardware, and the | |
2033 | * driver should be disabled. If ok is false, then the rx and tx | |
2034 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 2035 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
2036 | { |
2037 | int rc; | |
2038 | ||
2467ca46 | 2039 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 2040 | |
ef2b90ee | 2041 | rc = efx->type->init(efx); |
8ceee660 | 2042 | if (rc) { |
62776d03 | 2043 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 2044 | goto fail; |
8ceee660 BH |
2045 | } |
2046 | ||
eb9f6744 BH |
2047 | if (!ok) |
2048 | goto fail; | |
2049 | ||
4b988280 | 2050 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
2051 | rc = efx->phy_op->init(efx); |
2052 | if (rc) | |
2053 | goto fail; | |
2054 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
2055 | netif_err(efx, drv, efx->net_dev, |
2056 | "could not restore PHY settings\n"); | |
4b988280 SH |
2057 | } |
2058 | ||
eb9f6744 | 2059 | efx->mac_op->reconfigure(efx); |
8ceee660 | 2060 | |
eb9f6744 | 2061 | efx_init_channels(efx); |
64eebcfd | 2062 | efx_restore_filters(efx); |
eb9f6744 | 2063 | |
eb9f6744 BH |
2064 | mutex_unlock(&efx->mac_lock); |
2065 | ||
2066 | efx_start_all(efx); | |
2067 | ||
2068 | return 0; | |
2069 | ||
2070 | fail: | |
2071 | efx->port_initialized = false; | |
2467ca46 BH |
2072 | |
2073 | mutex_unlock(&efx->mac_lock); | |
2074 | ||
8ceee660 BH |
2075 | return rc; |
2076 | } | |
2077 | ||
eb9f6744 BH |
2078 | /* Reset the NIC using the specified method. Note that the reset may |
2079 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 2080 | * |
eb9f6744 | 2081 | * Caller must hold the rtnl_lock. |
8ceee660 | 2082 | */ |
eb9f6744 | 2083 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 2084 | { |
eb9f6744 BH |
2085 | int rc, rc2; |
2086 | bool disabled; | |
8ceee660 | 2087 | |
62776d03 BH |
2088 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
2089 | RESET_TYPE(method)); | |
8ceee660 | 2090 | |
d3245b28 | 2091 | efx_reset_down(efx, method); |
8ceee660 | 2092 | |
ef2b90ee | 2093 | rc = efx->type->reset(efx, method); |
8ceee660 | 2094 | if (rc) { |
62776d03 | 2095 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 2096 | goto out; |
8ceee660 BH |
2097 | } |
2098 | ||
2099 | /* Allow resets to be rescheduled. */ | |
2100 | efx->reset_pending = RESET_TYPE_NONE; | |
2101 | ||
2102 | /* Reinitialise bus-mastering, which may have been turned off before | |
2103 | * the reset was scheduled. This is still appropriate, even in the | |
2104 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
2105 | * can respond to requests. */ | |
2106 | pci_set_master(efx->pci_dev); | |
2107 | ||
eb9f6744 | 2108 | out: |
8ceee660 | 2109 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
2110 | disabled = rc || method == RESET_TYPE_DISABLE; |
2111 | rc2 = efx_reset_up(efx, method, !disabled); | |
2112 | if (rc2) { | |
2113 | disabled = true; | |
2114 | if (!rc) | |
2115 | rc = rc2; | |
8ceee660 BH |
2116 | } |
2117 | ||
eb9f6744 | 2118 | if (disabled) { |
f49a4589 | 2119 | dev_close(efx->net_dev); |
62776d03 | 2120 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 2121 | efx->state = STATE_DISABLED; |
f4bd954e | 2122 | } else { |
62776d03 | 2123 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
f4bd954e | 2124 | } |
8ceee660 BH |
2125 | return rc; |
2126 | } | |
2127 | ||
2128 | /* The worker thread exists so that code that cannot sleep can | |
2129 | * schedule a reset for later. | |
2130 | */ | |
2131 | static void efx_reset_work(struct work_struct *data) | |
2132 | { | |
eb9f6744 | 2133 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 2134 | |
319ba649 SH |
2135 | if (efx->reset_pending == RESET_TYPE_NONE) |
2136 | return; | |
2137 | ||
eb9f6744 BH |
2138 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
2139 | * flag set so that efx_pci_probe_main will be retried */ | |
2140 | if (efx->state != STATE_RUNNING) { | |
62776d03 BH |
2141 | netif_info(efx, drv, efx->net_dev, |
2142 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
2143 | return; |
2144 | } | |
2145 | ||
2146 | rtnl_lock(); | |
f49a4589 | 2147 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 2148 | rtnl_unlock(); |
8ceee660 BH |
2149 | } |
2150 | ||
2151 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
2152 | { | |
2153 | enum reset_type method; | |
2154 | ||
2155 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
62776d03 BH |
2156 | netif_info(efx, drv, efx->net_dev, |
2157 | "quenching already scheduled reset\n"); | |
8ceee660 BH |
2158 | return; |
2159 | } | |
2160 | ||
2161 | switch (type) { | |
2162 | case RESET_TYPE_INVISIBLE: | |
2163 | case RESET_TYPE_ALL: | |
2164 | case RESET_TYPE_WORLD: | |
2165 | case RESET_TYPE_DISABLE: | |
2166 | method = type; | |
2167 | break; | |
2168 | case RESET_TYPE_RX_RECOVERY: | |
2169 | case RESET_TYPE_RX_DESC_FETCH: | |
2170 | case RESET_TYPE_TX_DESC_FETCH: | |
2171 | case RESET_TYPE_TX_SKIP: | |
2172 | method = RESET_TYPE_INVISIBLE; | |
2173 | break; | |
8880f4ec | 2174 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
2175 | default: |
2176 | method = RESET_TYPE_ALL; | |
2177 | break; | |
2178 | } | |
2179 | ||
2180 | if (method != type) | |
62776d03 BH |
2181 | netif_dbg(efx, drv, efx->net_dev, |
2182 | "scheduling %s reset for %s\n", | |
2183 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 2184 | else |
62776d03 BH |
2185 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
2186 | RESET_TYPE(method)); | |
8ceee660 BH |
2187 | |
2188 | efx->reset_pending = method; | |
2189 | ||
8880f4ec BH |
2190 | /* efx_process_channel() will no longer read events once a |
2191 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
2192 | efx_mcdi_mode_poll(efx); | |
2193 | ||
1ab00629 | 2194 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
2195 | } |
2196 | ||
2197 | /************************************************************************** | |
2198 | * | |
2199 | * List of NICs we support | |
2200 | * | |
2201 | **************************************************************************/ | |
2202 | ||
2203 | /* PCI device ID table */ | |
a3aa1884 | 2204 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 2205 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 2206 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 2207 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 2208 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
2209 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
2210 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
2211 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
2212 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
2213 | {0} /* end of list */ |
2214 | }; | |
2215 | ||
2216 | /************************************************************************** | |
2217 | * | |
3759433d | 2218 | * Dummy PHY/MAC operations |
8ceee660 | 2219 | * |
01aad7b6 | 2220 | * Can be used for some unimplemented operations |
8ceee660 BH |
2221 | * Needed so all function pointers are valid and do not have to be tested |
2222 | * before use | |
2223 | * | |
2224 | **************************************************************************/ | |
2225 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2226 | { | |
2227 | return 0; | |
2228 | } | |
2229 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
d215697f | 2230 | |
2231 | static bool efx_port_dummy_op_poll(struct efx_nic *efx) | |
fdaa9aed SH |
2232 | { |
2233 | return false; | |
2234 | } | |
8ceee660 BH |
2235 | |
2236 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
2237 | .init = efx_port_dummy_op_int, | |
d3245b28 | 2238 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2239 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2240 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2241 | }; |
2242 | ||
8ceee660 BH |
2243 | /************************************************************************** |
2244 | * | |
2245 | * Data housekeeping | |
2246 | * | |
2247 | **************************************************************************/ | |
2248 | ||
2249 | /* This zeroes out and then fills in the invariants in a struct | |
2250 | * efx_nic (including all sub-structures). | |
2251 | */ | |
2252 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
2253 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
2254 | { | |
4642610c | 2255 | int i; |
8ceee660 BH |
2256 | |
2257 | /* Initialise common structures */ | |
2258 | memset(efx, 0, sizeof(*efx)); | |
2259 | spin_lock_init(&efx->biu_lock); | |
76884835 BH |
2260 | #ifdef CONFIG_SFC_MTD |
2261 | INIT_LIST_HEAD(&efx->mtd_list); | |
2262 | #endif | |
8ceee660 BH |
2263 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2264 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2265 | efx->pci_dev = pci_dev; | |
62776d03 | 2266 | efx->msg_enable = debug; |
8ceee660 BH |
2267 | efx->state = STATE_INIT; |
2268 | efx->reset_pending = RESET_TYPE_NONE; | |
2269 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2270 | |
2271 | efx->net_dev = net_dev; | |
dc8cfa55 | 2272 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2273 | spin_lock_init(&efx->stats_lock); |
2274 | mutex_init(&efx->mac_lock); | |
b895d73e | 2275 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2276 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2277 | efx->mdio.dev = net_dev; |
766ca0fa | 2278 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2279 | |
2280 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
4642610c BH |
2281 | efx->channel[i] = efx_alloc_channel(efx, i, NULL); |
2282 | if (!efx->channel[i]) | |
2283 | goto fail; | |
8ceee660 BH |
2284 | } |
2285 | ||
2286 | efx->type = type; | |
2287 | ||
8ceee660 BH |
2288 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2289 | ||
2290 | /* Higher numbered interrupt modes are less capable! */ | |
2291 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2292 | interrupt_mode); | |
2293 | ||
6977dc63 BH |
2294 | /* Would be good to use the net_dev name, but we're too early */ |
2295 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2296 | pci_name(pci_dev)); | |
2297 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 | 2298 | if (!efx->workqueue) |
4642610c | 2299 | goto fail; |
8d9853d9 | 2300 | |
8ceee660 | 2301 | return 0; |
4642610c BH |
2302 | |
2303 | fail: | |
2304 | efx_fini_struct(efx); | |
2305 | return -ENOMEM; | |
8ceee660 BH |
2306 | } |
2307 | ||
2308 | static void efx_fini_struct(struct efx_nic *efx) | |
2309 | { | |
8313aca3 BH |
2310 | int i; |
2311 | ||
2312 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2313 | kfree(efx->channel[i]); | |
2314 | ||
8ceee660 BH |
2315 | if (efx->workqueue) { |
2316 | destroy_workqueue(efx->workqueue); | |
2317 | efx->workqueue = NULL; | |
2318 | } | |
2319 | } | |
2320 | ||
2321 | /************************************************************************** | |
2322 | * | |
2323 | * PCI interface | |
2324 | * | |
2325 | **************************************************************************/ | |
2326 | ||
2327 | /* Main body of final NIC shutdown code | |
2328 | * This is called only at module unload (or hotplug removal). | |
2329 | */ | |
2330 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2331 | { | |
64d8ad6d BH |
2332 | #ifdef CONFIG_RFS_ACCEL |
2333 | free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap); | |
2334 | efx->net_dev->rx_cpu_rmap = NULL; | |
2335 | #endif | |
152b6a62 | 2336 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2337 | efx_fini_channels(efx); |
2338 | efx_fini_port(efx); | |
ef2b90ee | 2339 | efx->type->fini(efx); |
8ceee660 BH |
2340 | efx_fini_napi(efx); |
2341 | efx_remove_all(efx); | |
2342 | } | |
2343 | ||
2344 | /* Final NIC shutdown | |
2345 | * This is called only at module unload (or hotplug removal). | |
2346 | */ | |
2347 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2348 | { | |
2349 | struct efx_nic *efx; | |
2350 | ||
2351 | efx = pci_get_drvdata(pci_dev); | |
2352 | if (!efx) | |
2353 | return; | |
2354 | ||
2355 | /* Mark the NIC as fini, then stop the interface */ | |
2356 | rtnl_lock(); | |
2357 | efx->state = STATE_FINI; | |
2358 | dev_close(efx->net_dev); | |
2359 | ||
2360 | /* Allow any queued efx_resets() to complete */ | |
2361 | rtnl_unlock(); | |
2362 | ||
8ceee660 BH |
2363 | efx_unregister_netdev(efx); |
2364 | ||
7dde596e BH |
2365 | efx_mtd_remove(efx); |
2366 | ||
8ceee660 BH |
2367 | /* Wait for any scheduled resets to complete. No more will be |
2368 | * scheduled from this point because efx_stop_all() has been | |
2369 | * called, we are no longer registered with driverlink, and | |
2370 | * the net_device's have been removed. */ | |
1ab00629 | 2371 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2372 | |
2373 | efx_pci_remove_main(efx); | |
2374 | ||
8ceee660 | 2375 | efx_fini_io(efx); |
62776d03 | 2376 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2377 | |
2378 | pci_set_drvdata(pci_dev, NULL); | |
2379 | efx_fini_struct(efx); | |
2380 | free_netdev(efx->net_dev); | |
2381 | }; | |
2382 | ||
2383 | /* Main body of NIC initialisation | |
2384 | * This is called at module load (or hotplug insertion, theoretically). | |
2385 | */ | |
2386 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2387 | { | |
2388 | int rc; | |
2389 | ||
2390 | /* Do start-of-day initialisation */ | |
2391 | rc = efx_probe_all(efx); | |
2392 | if (rc) | |
2393 | goto fail1; | |
2394 | ||
e8f14992 | 2395 | efx_init_napi(efx); |
8ceee660 | 2396 | |
ef2b90ee | 2397 | rc = efx->type->init(efx); |
8ceee660 | 2398 | if (rc) { |
62776d03 BH |
2399 | netif_err(efx, probe, efx->net_dev, |
2400 | "failed to initialise NIC\n"); | |
278c0621 | 2401 | goto fail3; |
8ceee660 BH |
2402 | } |
2403 | ||
2404 | rc = efx_init_port(efx); | |
2405 | if (rc) { | |
62776d03 BH |
2406 | netif_err(efx, probe, efx->net_dev, |
2407 | "failed to initialise port\n"); | |
278c0621 | 2408 | goto fail4; |
8ceee660 BH |
2409 | } |
2410 | ||
bc3c90a2 | 2411 | efx_init_channels(efx); |
8ceee660 | 2412 | |
152b6a62 | 2413 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2414 | if (rc) |
278c0621 | 2415 | goto fail5; |
8ceee660 BH |
2416 | |
2417 | return 0; | |
2418 | ||
278c0621 | 2419 | fail5: |
bc3c90a2 | 2420 | efx_fini_channels(efx); |
8ceee660 | 2421 | efx_fini_port(efx); |
8ceee660 | 2422 | fail4: |
ef2b90ee | 2423 | efx->type->fini(efx); |
8ceee660 BH |
2424 | fail3: |
2425 | efx_fini_napi(efx); | |
8ceee660 BH |
2426 | efx_remove_all(efx); |
2427 | fail1: | |
2428 | return rc; | |
2429 | } | |
2430 | ||
2431 | /* NIC initialisation | |
2432 | * | |
2433 | * This is called at module load (or hotplug insertion, | |
2434 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2435 | * sets up and registers the network devices with the kernel and hooks | |
2436 | * the interrupt service routine. It does not prepare the device for | |
2437 | * transmission; this is left to the first time one of the network | |
2438 | * interfaces is brought up (i.e. efx_net_open). | |
2439 | */ | |
2440 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2441 | const struct pci_device_id *entry) | |
2442 | { | |
2443 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2444 | struct net_device *net_dev; | |
2445 | struct efx_nic *efx; | |
2446 | int i, rc; | |
2447 | ||
2448 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
94b274bf BH |
2449 | net_dev = alloc_etherdev_mqs(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES, |
2450 | EFX_MAX_RX_QUEUES); | |
8ceee660 BH |
2451 | if (!net_dev) |
2452 | return -ENOMEM; | |
c383b537 | 2453 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2454 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2455 | NETIF_F_GRO); | |
738a8f4b BH |
2456 | if (type->offload_features & NETIF_F_V6_CSUM) |
2457 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2458 | /* Mask for features that also apply to VLAN devices */ |
2459 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2460 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2461 | efx = netdev_priv(net_dev); |
8ceee660 | 2462 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2463 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2464 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2465 | if (rc) | |
2466 | goto fail1; | |
2467 | ||
62776d03 BH |
2468 | netif_info(efx, probe, efx->net_dev, |
2469 | "Solarflare Communications NIC detected\n"); | |
8ceee660 BH |
2470 | |
2471 | /* Set up basic I/O (BAR mappings etc) */ | |
2472 | rc = efx_init_io(efx); | |
2473 | if (rc) | |
2474 | goto fail2; | |
2475 | ||
2476 | /* No serialisation is required with the reset path because | |
2477 | * we're in STATE_INIT. */ | |
2478 | for (i = 0; i < 5; i++) { | |
2479 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2480 | |
2481 | /* Serialise against efx_reset(). No more resets will be | |
2482 | * scheduled since efx_stop_all() has been called, and we | |
2483 | * have not and never have been registered with either | |
2484 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2485 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2486 | |
fa402b2e SH |
2487 | if (rc == 0) { |
2488 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2489 | /* If there was a scheduled reset during | |
2490 | * probe, the NIC is probably hosed anyway */ | |
2491 | efx_pci_remove_main(efx); | |
2492 | rc = -EIO; | |
2493 | } else { | |
2494 | break; | |
2495 | } | |
2496 | } | |
2497 | ||
8ceee660 BH |
2498 | /* Retry if a recoverably reset event has been scheduled */ |
2499 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2500 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2501 | goto fail3; | |
2502 | ||
2503 | efx->reset_pending = RESET_TYPE_NONE; | |
2504 | } | |
2505 | ||
2506 | if (rc) { | |
62776d03 | 2507 | netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); |
8ceee660 BH |
2508 | goto fail4; |
2509 | } | |
2510 | ||
55edc6e6 BH |
2511 | /* Switch to the running state before we expose the device to the OS, |
2512 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2513 | efx->state = STATE_RUNNING; |
7dde596e | 2514 | |
8ceee660 BH |
2515 | rc = efx_register_netdev(efx); |
2516 | if (rc) | |
2517 | goto fail5; | |
2518 | ||
62776d03 | 2519 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 BH |
2520 | |
2521 | rtnl_lock(); | |
2522 | efx_mtd_probe(efx); /* allowed to fail */ | |
2523 | rtnl_unlock(); | |
8ceee660 BH |
2524 | return 0; |
2525 | ||
2526 | fail5: | |
2527 | efx_pci_remove_main(efx); | |
2528 | fail4: | |
2529 | fail3: | |
2530 | efx_fini_io(efx); | |
2531 | fail2: | |
2532 | efx_fini_struct(efx); | |
2533 | fail1: | |
5e2a911c | 2534 | WARN_ON(rc > 0); |
62776d03 | 2535 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2536 | free_netdev(net_dev); |
2537 | return rc; | |
2538 | } | |
2539 | ||
89c758fa BH |
2540 | static int efx_pm_freeze(struct device *dev) |
2541 | { | |
2542 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2543 | ||
2544 | efx->state = STATE_FINI; | |
2545 | ||
2546 | netif_device_detach(efx->net_dev); | |
2547 | ||
2548 | efx_stop_all(efx); | |
2549 | efx_fini_channels(efx); | |
2550 | ||
2551 | return 0; | |
2552 | } | |
2553 | ||
2554 | static int efx_pm_thaw(struct device *dev) | |
2555 | { | |
2556 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2557 | ||
2558 | efx->state = STATE_INIT; | |
2559 | ||
2560 | efx_init_channels(efx); | |
2561 | ||
2562 | mutex_lock(&efx->mac_lock); | |
2563 | efx->phy_op->reconfigure(efx); | |
2564 | mutex_unlock(&efx->mac_lock); | |
2565 | ||
2566 | efx_start_all(efx); | |
2567 | ||
2568 | netif_device_attach(efx->net_dev); | |
2569 | ||
2570 | efx->state = STATE_RUNNING; | |
2571 | ||
2572 | efx->type->resume_wol(efx); | |
2573 | ||
319ba649 SH |
2574 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2575 | queue_work(reset_workqueue, &efx->reset_work); | |
2576 | ||
89c758fa BH |
2577 | return 0; |
2578 | } | |
2579 | ||
2580 | static int efx_pm_poweroff(struct device *dev) | |
2581 | { | |
2582 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2583 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2584 | ||
2585 | efx->type->fini(efx); | |
2586 | ||
2587 | efx->reset_pending = RESET_TYPE_NONE; | |
2588 | ||
2589 | pci_save_state(pci_dev); | |
2590 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2591 | } | |
2592 | ||
2593 | /* Used for both resume and restore */ | |
2594 | static int efx_pm_resume(struct device *dev) | |
2595 | { | |
2596 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2597 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2598 | int rc; | |
2599 | ||
2600 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2601 | if (rc) | |
2602 | return rc; | |
2603 | pci_restore_state(pci_dev); | |
2604 | rc = pci_enable_device(pci_dev); | |
2605 | if (rc) | |
2606 | return rc; | |
2607 | pci_set_master(efx->pci_dev); | |
2608 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2609 | if (rc) | |
2610 | return rc; | |
2611 | rc = efx->type->init(efx); | |
2612 | if (rc) | |
2613 | return rc; | |
2614 | efx_pm_thaw(dev); | |
2615 | return 0; | |
2616 | } | |
2617 | ||
2618 | static int efx_pm_suspend(struct device *dev) | |
2619 | { | |
2620 | int rc; | |
2621 | ||
2622 | efx_pm_freeze(dev); | |
2623 | rc = efx_pm_poweroff(dev); | |
2624 | if (rc) | |
2625 | efx_pm_resume(dev); | |
2626 | return rc; | |
2627 | } | |
2628 | ||
2629 | static struct dev_pm_ops efx_pm_ops = { | |
2630 | .suspend = efx_pm_suspend, | |
2631 | .resume = efx_pm_resume, | |
2632 | .freeze = efx_pm_freeze, | |
2633 | .thaw = efx_pm_thaw, | |
2634 | .poweroff = efx_pm_poweroff, | |
2635 | .restore = efx_pm_resume, | |
2636 | }; | |
2637 | ||
8ceee660 | 2638 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2639 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2640 | .id_table = efx_pci_table, |
2641 | .probe = efx_pci_probe, | |
2642 | .remove = efx_pci_remove, | |
89c758fa | 2643 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2644 | }; |
2645 | ||
2646 | /************************************************************************** | |
2647 | * | |
2648 | * Kernel module interface | |
2649 | * | |
2650 | *************************************************************************/ | |
2651 | ||
2652 | module_param(interrupt_mode, uint, 0444); | |
2653 | MODULE_PARM_DESC(interrupt_mode, | |
2654 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2655 | ||
2656 | static int __init efx_init_module(void) | |
2657 | { | |
2658 | int rc; | |
2659 | ||
2660 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2661 | ||
2662 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2663 | if (rc) | |
2664 | goto err_notifier; | |
2665 | ||
1ab00629 SH |
2666 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2667 | if (!reset_workqueue) { | |
2668 | rc = -ENOMEM; | |
2669 | goto err_reset; | |
2670 | } | |
8ceee660 BH |
2671 | |
2672 | rc = pci_register_driver(&efx_pci_driver); | |
2673 | if (rc < 0) | |
2674 | goto err_pci; | |
2675 | ||
2676 | return 0; | |
2677 | ||
2678 | err_pci: | |
1ab00629 SH |
2679 | destroy_workqueue(reset_workqueue); |
2680 | err_reset: | |
8ceee660 BH |
2681 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2682 | err_notifier: | |
2683 | return rc; | |
2684 | } | |
2685 | ||
2686 | static void __exit efx_exit_module(void) | |
2687 | { | |
2688 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2689 | ||
2690 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2691 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2692 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2693 | ||
2694 | } | |
2695 | ||
2696 | module_init(efx_init_module); | |
2697 | module_exit(efx_exit_module); | |
2698 | ||
906bb26c BH |
2699 | MODULE_AUTHOR("Solarflare Communications and " |
2700 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2701 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2702 | MODULE_LICENSE("GPL"); | |
2703 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |