Commit | Line | Data |
---|---|---|
8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 BH |
23 | #include "net_driver.h" |
24 | #include "gmii.h" | |
25 | #include "ethtool.h" | |
26 | #include "tx.h" | |
27 | #include "rx.h" | |
28 | #include "efx.h" | |
29 | #include "mdio_10g.h" | |
30 | #include "falcon.h" | |
8ceee660 BH |
31 | #include "mac.h" |
32 | ||
33 | #define EFX_MAX_MTU (9 * 1024) | |
34 | ||
35 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
36 | * a work item is pushed onto this work queue to retry the allocation later, | |
37 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
38 | * workqueue, there is nothing to be gained in making it per NIC | |
39 | */ | |
40 | static struct workqueue_struct *refill_workqueue; | |
41 | ||
42 | /************************************************************************** | |
43 | * | |
44 | * Configurable values | |
45 | * | |
46 | *************************************************************************/ | |
47 | ||
48 | /* | |
49 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
50 | * | |
51 | * This sets the default for new devices. It can be controlled later | |
52 | * using ethtool. | |
53 | */ | |
dc8cfa55 | 54 | static int lro = true; |
8ceee660 BH |
55 | module_param(lro, int, 0644); |
56 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
57 | ||
58 | /* | |
59 | * Use separate channels for TX and RX events | |
60 | * | |
61 | * Set this to 1 to use separate channels for TX and RX. It allows us to | |
62 | * apply a higher level of interrupt moderation to TX events. | |
63 | * | |
64 | * This is forced to 0 for MSI interrupt mode as the interrupt vector | |
65 | * is not written | |
66 | */ | |
dc8cfa55 | 67 | static unsigned int separate_tx_and_rx_channels = true; |
8ceee660 BH |
68 | |
69 | /* This is the weight assigned to each of the (per-channel) virtual | |
70 | * NAPI devices. | |
71 | */ | |
72 | static int napi_weight = 64; | |
73 | ||
74 | /* This is the time (in jiffies) between invocations of the hardware | |
75 | * monitor, which checks for known hardware bugs and resets the | |
76 | * hardware and driver as necessary. | |
77 | */ | |
78 | unsigned int efx_monitor_interval = 1 * HZ; | |
79 | ||
80 | /* This controls whether or not the hardware monitor will trigger a | |
81 | * reset when it detects an error condition. | |
82 | */ | |
dc8cfa55 | 83 | static unsigned int monitor_reset = true; |
8ceee660 BH |
84 | |
85 | /* This controls whether or not the driver will initialise devices | |
86 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
87 | * such devices will be initialised with a random locally-generated | |
88 | * MAC address. This allows for loading the sfc_mtd driver to | |
89 | * reprogram the flash, even if the flash contents (including the MAC | |
90 | * address) have previously been erased. | |
91 | */ | |
92 | static unsigned int allow_bad_hwaddr; | |
93 | ||
94 | /* Initial interrupt moderation settings. They can be modified after | |
95 | * module load with ethtool. | |
96 | * | |
97 | * The default for RX should strike a balance between increasing the | |
98 | * round-trip latency and reducing overhead. | |
99 | */ | |
100 | static unsigned int rx_irq_mod_usec = 60; | |
101 | ||
102 | /* Initial interrupt moderation settings. They can be modified after | |
103 | * module load with ethtool. | |
104 | * | |
105 | * This default is chosen to ensure that a 10G link does not go idle | |
106 | * while a TX queue is stopped after it has become full. A queue is | |
107 | * restarted when it drops below half full. The time this takes (assuming | |
108 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
109 | * 512 / 3 * 1.2 = 205 usec. | |
110 | */ | |
111 | static unsigned int tx_irq_mod_usec = 150; | |
112 | ||
113 | /* This is the first interrupt mode to try out of: | |
114 | * 0 => MSI-X | |
115 | * 1 => MSI | |
116 | * 2 => legacy | |
117 | */ | |
118 | static unsigned int interrupt_mode; | |
119 | ||
120 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
121 | * i.e. the number of CPUs among which we may distribute simultaneous | |
122 | * interrupt handling. | |
123 | * | |
124 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
125 | * The default (0) means to assign an interrupt to each package (level II cache) | |
126 | */ | |
127 | static unsigned int rss_cpus; | |
128 | module_param(rss_cpus, uint, 0444); | |
129 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
130 | ||
131 | /************************************************************************** | |
132 | * | |
133 | * Utility functions and prototypes | |
134 | * | |
135 | *************************************************************************/ | |
136 | static void efx_remove_channel(struct efx_channel *channel); | |
137 | static void efx_remove_port(struct efx_nic *efx); | |
138 | static void efx_fini_napi(struct efx_nic *efx); | |
139 | static void efx_fini_channels(struct efx_nic *efx); | |
140 | ||
141 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
142 | do { \ | |
143 | if ((efx->state == STATE_RUNNING) || \ | |
144 | (efx->state == STATE_RESETTING)) \ | |
145 | ASSERT_RTNL(); \ | |
146 | } while (0) | |
147 | ||
148 | /************************************************************************** | |
149 | * | |
150 | * Event queue processing | |
151 | * | |
152 | *************************************************************************/ | |
153 | ||
154 | /* Process channel's event queue | |
155 | * | |
156 | * This function is responsible for processing the event queue of a | |
157 | * single channel. The caller must guarantee that this function will | |
158 | * never be concurrently called more than once on the same channel, | |
159 | * though different channels may be being processed concurrently. | |
160 | */ | |
4d566063 | 161 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 162 | { |
42cbe2d7 BH |
163 | struct efx_nic *efx = channel->efx; |
164 | int rx_packets; | |
8ceee660 | 165 | |
42cbe2d7 | 166 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 167 | !channel->enabled)) |
42cbe2d7 | 168 | return 0; |
8ceee660 | 169 | |
42cbe2d7 BH |
170 | rx_packets = falcon_process_eventq(channel, rx_quota); |
171 | if (rx_packets == 0) | |
172 | return 0; | |
8ceee660 BH |
173 | |
174 | /* Deliver last RX packet. */ | |
175 | if (channel->rx_pkt) { | |
176 | __efx_rx_packet(channel, channel->rx_pkt, | |
177 | channel->rx_pkt_csummed); | |
178 | channel->rx_pkt = NULL; | |
179 | } | |
180 | ||
181 | efx_flush_lro(channel); | |
182 | efx_rx_strategy(channel); | |
183 | ||
42cbe2d7 | 184 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 185 | |
42cbe2d7 | 186 | return rx_packets; |
8ceee660 BH |
187 | } |
188 | ||
189 | /* Mark channel as finished processing | |
190 | * | |
191 | * Note that since we will not receive further interrupts for this | |
192 | * channel before we finish processing and call the eventq_read_ack() | |
193 | * method, there is no need to use the interrupt hold-off timers. | |
194 | */ | |
195 | static inline void efx_channel_processed(struct efx_channel *channel) | |
196 | { | |
5b9e207c BH |
197 | /* The interrupt handler for this channel may set work_pending |
198 | * as soon as we acknowledge the events we've seen. Make sure | |
199 | * it's cleared before then. */ | |
dc8cfa55 | 200 | channel->work_pending = false; |
5b9e207c BH |
201 | smp_wmb(); |
202 | ||
8ceee660 BH |
203 | falcon_eventq_read_ack(channel); |
204 | } | |
205 | ||
206 | /* NAPI poll handler | |
207 | * | |
208 | * NAPI guarantees serialisation of polls of the same device, which | |
209 | * provides the guarantee required by efx_process_channel(). | |
210 | */ | |
211 | static int efx_poll(struct napi_struct *napi, int budget) | |
212 | { | |
213 | struct efx_channel *channel = | |
214 | container_of(napi, struct efx_channel, napi_str); | |
215 | struct net_device *napi_dev = channel->napi_dev; | |
8ceee660 BH |
216 | int rx_packets; |
217 | ||
218 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
219 | channel->channel, raw_smp_processor_id()); | |
220 | ||
42cbe2d7 | 221 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
222 | |
223 | if (rx_packets < budget) { | |
224 | /* There is no race here; although napi_disable() will | |
225 | * only wait for netif_rx_complete(), this isn't a problem | |
226 | * since efx_channel_processed() will have no effect if | |
227 | * interrupts have already been disabled. | |
228 | */ | |
229 | netif_rx_complete(napi_dev, napi); | |
230 | efx_channel_processed(channel); | |
231 | } | |
232 | ||
233 | return rx_packets; | |
234 | } | |
235 | ||
236 | /* Process the eventq of the specified channel immediately on this CPU | |
237 | * | |
238 | * Disable hardware generated interrupts, wait for any existing | |
239 | * processing to finish, then directly poll (and ack ) the eventq. | |
240 | * Finally reenable NAPI and interrupts. | |
241 | * | |
242 | * Since we are touching interrupts the caller should hold the suspend lock | |
243 | */ | |
244 | void efx_process_channel_now(struct efx_channel *channel) | |
245 | { | |
246 | struct efx_nic *efx = channel->efx; | |
247 | ||
248 | BUG_ON(!channel->used_flags); | |
249 | BUG_ON(!channel->enabled); | |
250 | ||
251 | /* Disable interrupts and wait for ISRs to complete */ | |
252 | falcon_disable_interrupts(efx); | |
253 | if (efx->legacy_irq) | |
254 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 255 | if (channel->irq) |
8ceee660 BH |
256 | synchronize_irq(channel->irq); |
257 | ||
258 | /* Wait for any NAPI processing to complete */ | |
259 | napi_disable(&channel->napi_str); | |
260 | ||
261 | /* Poll the channel */ | |
91ad757c | 262 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
263 | |
264 | /* Ack the eventq. This may cause an interrupt to be generated | |
265 | * when they are reenabled */ | |
266 | efx_channel_processed(channel); | |
267 | ||
268 | napi_enable(&channel->napi_str); | |
269 | falcon_enable_interrupts(efx); | |
270 | } | |
271 | ||
272 | /* Create event queue | |
273 | * Event queue memory allocations are done only once. If the channel | |
274 | * is reset, the memory buffer will be reused; this guards against | |
275 | * errors during channel reset and also simplifies interrupt handling. | |
276 | */ | |
277 | static int efx_probe_eventq(struct efx_channel *channel) | |
278 | { | |
279 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
280 | ||
281 | return falcon_probe_eventq(channel); | |
282 | } | |
283 | ||
284 | /* Prepare channel's event queue */ | |
bc3c90a2 | 285 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
286 | { |
287 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
288 | ||
289 | channel->eventq_read_ptr = 0; | |
290 | ||
bc3c90a2 | 291 | falcon_init_eventq(channel); |
8ceee660 BH |
292 | } |
293 | ||
294 | static void efx_fini_eventq(struct efx_channel *channel) | |
295 | { | |
296 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
297 | ||
298 | falcon_fini_eventq(channel); | |
299 | } | |
300 | ||
301 | static void efx_remove_eventq(struct efx_channel *channel) | |
302 | { | |
303 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
304 | ||
305 | falcon_remove_eventq(channel); | |
306 | } | |
307 | ||
308 | /************************************************************************** | |
309 | * | |
310 | * Channel handling | |
311 | * | |
312 | *************************************************************************/ | |
313 | ||
8ceee660 BH |
314 | static int efx_probe_channel(struct efx_channel *channel) |
315 | { | |
316 | struct efx_tx_queue *tx_queue; | |
317 | struct efx_rx_queue *rx_queue; | |
318 | int rc; | |
319 | ||
320 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
321 | ||
322 | rc = efx_probe_eventq(channel); | |
323 | if (rc) | |
324 | goto fail1; | |
325 | ||
326 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
327 | rc = efx_probe_tx_queue(tx_queue); | |
328 | if (rc) | |
329 | goto fail2; | |
330 | } | |
331 | ||
332 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
333 | rc = efx_probe_rx_queue(rx_queue); | |
334 | if (rc) | |
335 | goto fail3; | |
336 | } | |
337 | ||
338 | channel->n_rx_frm_trunc = 0; | |
339 | ||
340 | return 0; | |
341 | ||
342 | fail3: | |
343 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
344 | efx_remove_rx_queue(rx_queue); | |
345 | fail2: | |
346 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
347 | efx_remove_tx_queue(tx_queue); | |
348 | fail1: | |
349 | return rc; | |
350 | } | |
351 | ||
352 | ||
353 | /* Channels are shutdown and reinitialised whilst the NIC is running | |
354 | * to propagate configuration changes (mtu, checksum offload), or | |
355 | * to clear hardware error conditions | |
356 | */ | |
bc3c90a2 | 357 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
358 | { |
359 | struct efx_tx_queue *tx_queue; | |
360 | struct efx_rx_queue *rx_queue; | |
361 | struct efx_channel *channel; | |
8ceee660 | 362 | |
f7f13b0b BH |
363 | /* Calculate the rx buffer allocation parameters required to |
364 | * support the current MTU, including padding for header | |
365 | * alignment and overruns. | |
366 | */ | |
367 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
368 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
369 | efx->type->rx_buffer_padding); | |
370 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
371 | |
372 | /* Initialise the channels */ | |
373 | efx_for_each_channel(channel, efx) { | |
374 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
375 | ||
bc3c90a2 | 376 | efx_init_eventq(channel); |
8ceee660 | 377 | |
bc3c90a2 BH |
378 | efx_for_each_channel_tx_queue(tx_queue, channel) |
379 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
380 | |
381 | /* The rx buffer allocation strategy is MTU dependent */ | |
382 | efx_rx_strategy(channel); | |
383 | ||
bc3c90a2 BH |
384 | efx_for_each_channel_rx_queue(rx_queue, channel) |
385 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
386 | |
387 | WARN_ON(channel->rx_pkt != NULL); | |
388 | efx_rx_strategy(channel); | |
389 | } | |
8ceee660 BH |
390 | } |
391 | ||
392 | /* This enables event queue processing and packet transmission. | |
393 | * | |
394 | * Note that this function is not allowed to fail, since that would | |
395 | * introduce too much complexity into the suspend/resume path. | |
396 | */ | |
397 | static void efx_start_channel(struct efx_channel *channel) | |
398 | { | |
399 | struct efx_rx_queue *rx_queue; | |
400 | ||
401 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
402 | ||
403 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
404 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
405 | efx_poll, napi_weight); | |
406 | ||
5b9e207c BH |
407 | /* The interrupt handler for this channel may set work_pending |
408 | * as soon as we enable it. Make sure it's cleared before | |
409 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
410 | channel->work_pending = false; |
411 | channel->enabled = true; | |
5b9e207c | 412 | smp_wmb(); |
8ceee660 BH |
413 | |
414 | napi_enable(&channel->napi_str); | |
415 | ||
416 | /* Load up RX descriptors */ | |
417 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
418 | efx_fast_push_rx_descriptors(rx_queue); | |
419 | } | |
420 | ||
421 | /* This disables event queue processing and packet transmission. | |
422 | * This function does not guarantee that all queue processing | |
423 | * (e.g. RX refill) is complete. | |
424 | */ | |
425 | static void efx_stop_channel(struct efx_channel *channel) | |
426 | { | |
427 | struct efx_rx_queue *rx_queue; | |
428 | ||
429 | if (!channel->enabled) | |
430 | return; | |
431 | ||
432 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
433 | ||
dc8cfa55 | 434 | channel->enabled = false; |
8ceee660 BH |
435 | napi_disable(&channel->napi_str); |
436 | ||
437 | /* Ensure that any worker threads have exited or will be no-ops */ | |
438 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
439 | spin_lock_bh(&rx_queue->add_lock); | |
440 | spin_unlock_bh(&rx_queue->add_lock); | |
441 | } | |
442 | } | |
443 | ||
444 | static void efx_fini_channels(struct efx_nic *efx) | |
445 | { | |
446 | struct efx_channel *channel; | |
447 | struct efx_tx_queue *tx_queue; | |
448 | struct efx_rx_queue *rx_queue; | |
449 | ||
450 | EFX_ASSERT_RESET_SERIALISED(efx); | |
451 | BUG_ON(efx->port_enabled); | |
452 | ||
453 | efx_for_each_channel(channel, efx) { | |
454 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
455 | ||
456 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
457 | efx_fini_rx_queue(rx_queue); | |
458 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
459 | efx_fini_tx_queue(tx_queue); | |
460 | } | |
461 | ||
462 | /* Do the event queues last so that we can handle flush events | |
463 | * for all DMA queues. */ | |
464 | efx_for_each_channel(channel, efx) { | |
465 | EFX_LOG(channel->efx, "shut down evq %d\n", channel->channel); | |
466 | ||
467 | efx_fini_eventq(channel); | |
468 | } | |
469 | } | |
470 | ||
471 | static void efx_remove_channel(struct efx_channel *channel) | |
472 | { | |
473 | struct efx_tx_queue *tx_queue; | |
474 | struct efx_rx_queue *rx_queue; | |
475 | ||
476 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
477 | ||
478 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
479 | efx_remove_rx_queue(rx_queue); | |
480 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
481 | efx_remove_tx_queue(tx_queue); | |
482 | efx_remove_eventq(channel); | |
483 | ||
484 | channel->used_flags = 0; | |
485 | } | |
486 | ||
487 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
488 | { | |
489 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
490 | } | |
491 | ||
492 | /************************************************************************** | |
493 | * | |
494 | * Port handling | |
495 | * | |
496 | **************************************************************************/ | |
497 | ||
498 | /* This ensures that the kernel is kept informed (via | |
499 | * netif_carrier_on/off) of the link status, and also maintains the | |
500 | * link status's stop on the port's TX queue. | |
501 | */ | |
502 | static void efx_link_status_changed(struct efx_nic *efx) | |
503 | { | |
8ceee660 BH |
504 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
505 | * that no events are triggered between unregister_netdev() and the | |
506 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
507 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
508 | if (!netif_running(efx->net_dev)) | |
509 | return; | |
510 | ||
dc8cfa55 | 511 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
512 | efx->n_link_state_changes++; |
513 | ||
514 | if (efx->link_up) | |
515 | netif_carrier_on(efx->net_dev); | |
516 | else | |
517 | netif_carrier_off(efx->net_dev); | |
518 | } | |
519 | ||
520 | /* Status message for kernel log */ | |
521 | if (efx->link_up) { | |
522 | struct mii_if_info *gmii = &efx->mii; | |
523 | unsigned adv, lpa; | |
524 | /* NONE here means direct XAUI from the controller, with no | |
525 | * MDIO-attached device we can query. */ | |
526 | if (efx->phy_type != PHY_TYPE_NONE) { | |
527 | adv = gmii_advertised(gmii); | |
528 | lpa = gmii_lpa(gmii); | |
529 | } else { | |
530 | lpa = GM_LPA_10000 | LPA_DUPLEX; | |
531 | adv = lpa; | |
532 | } | |
533 | EFX_INFO(efx, "link up at %dMbps %s-duplex " | |
534 | "(adv %04x lpa %04x) (MTU %d)%s\n", | |
535 | (efx->link_options & GM_LPA_10000 ? 10000 : | |
536 | (efx->link_options & GM_LPA_1000 ? 1000 : | |
537 | (efx->link_options & GM_LPA_100 ? 100 : | |
538 | 10))), | |
539 | (efx->link_options & GM_LPA_DUPLEX ? | |
540 | "full" : "half"), | |
541 | adv, lpa, | |
542 | efx->net_dev->mtu, | |
543 | (efx->promiscuous ? " [PROMISC]" : "")); | |
544 | } else { | |
545 | EFX_INFO(efx, "link down\n"); | |
546 | } | |
547 | ||
548 | } | |
549 | ||
550 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
551 | * caller must hold the mac_lock */ | |
552 | static void __efx_reconfigure_port(struct efx_nic *efx) | |
553 | { | |
554 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
555 | ||
556 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
557 | raw_smp_processor_id()); | |
558 | ||
559 | falcon_reconfigure_xmac(efx); | |
560 | ||
561 | /* Inform kernel of loss/gain of carrier */ | |
562 | efx_link_status_changed(efx); | |
563 | } | |
564 | ||
565 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
566 | * disabled. */ | |
567 | void efx_reconfigure_port(struct efx_nic *efx) | |
568 | { | |
569 | EFX_ASSERT_RESET_SERIALISED(efx); | |
570 | ||
571 | mutex_lock(&efx->mac_lock); | |
572 | __efx_reconfigure_port(efx); | |
573 | mutex_unlock(&efx->mac_lock); | |
574 | } | |
575 | ||
576 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
577 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
578 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
579 | static void efx_reconfigure_work(struct work_struct *data) | |
580 | { | |
581 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
582 | reconfigure_work); | |
583 | ||
584 | mutex_lock(&efx->mac_lock); | |
585 | if (efx->port_enabled) | |
586 | __efx_reconfigure_port(efx); | |
587 | mutex_unlock(&efx->mac_lock); | |
588 | } | |
589 | ||
590 | static int efx_probe_port(struct efx_nic *efx) | |
591 | { | |
592 | int rc; | |
593 | ||
594 | EFX_LOG(efx, "create port\n"); | |
595 | ||
596 | /* Connect up MAC/PHY operations table and read MAC address */ | |
597 | rc = falcon_probe_port(efx); | |
598 | if (rc) | |
599 | goto err; | |
600 | ||
601 | /* Sanity check MAC address */ | |
602 | if (is_valid_ether_addr(efx->mac_address)) { | |
603 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
604 | } else { | |
605 | DECLARE_MAC_BUF(mac); | |
606 | ||
607 | EFX_ERR(efx, "invalid MAC address %s\n", | |
608 | print_mac(mac, efx->mac_address)); | |
609 | if (!allow_bad_hwaddr) { | |
610 | rc = -EINVAL; | |
611 | goto err; | |
612 | } | |
613 | random_ether_addr(efx->net_dev->dev_addr); | |
614 | EFX_INFO(efx, "using locally-generated MAC %s\n", | |
615 | print_mac(mac, efx->net_dev->dev_addr)); | |
616 | } | |
617 | ||
618 | return 0; | |
619 | ||
620 | err: | |
621 | efx_remove_port(efx); | |
622 | return rc; | |
623 | } | |
624 | ||
625 | static int efx_init_port(struct efx_nic *efx) | |
626 | { | |
627 | int rc; | |
628 | ||
629 | EFX_LOG(efx, "init port\n"); | |
630 | ||
631 | /* Initialise the MAC and PHY */ | |
632 | rc = falcon_init_xmac(efx); | |
633 | if (rc) | |
634 | return rc; | |
635 | ||
dc8cfa55 | 636 | efx->port_initialized = true; |
8ceee660 BH |
637 | |
638 | /* Reconfigure port to program MAC registers */ | |
639 | falcon_reconfigure_xmac(efx); | |
640 | ||
641 | return 0; | |
642 | } | |
643 | ||
644 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
645 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
646 | * efx_reconfigure_port() may have been cancelled */ | |
647 | static void efx_start_port(struct efx_nic *efx) | |
648 | { | |
649 | EFX_LOG(efx, "start port\n"); | |
650 | BUG_ON(efx->port_enabled); | |
651 | ||
652 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 653 | efx->port_enabled = true; |
8ceee660 BH |
654 | __efx_reconfigure_port(efx); |
655 | mutex_unlock(&efx->mac_lock); | |
656 | } | |
657 | ||
658 | /* Prevent efx_reconfigure_work and efx_monitor() from executing, and | |
659 | * efx_set_multicast_list() from scheduling efx_reconfigure_work. | |
660 | * efx_reconfigure_work can still be scheduled via NAPI processing | |
661 | * until efx_flush_all() is called */ | |
662 | static void efx_stop_port(struct efx_nic *efx) | |
663 | { | |
664 | EFX_LOG(efx, "stop port\n"); | |
665 | ||
666 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 667 | efx->port_enabled = false; |
8ceee660 BH |
668 | mutex_unlock(&efx->mac_lock); |
669 | ||
670 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 671 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
672 | netif_addr_lock_bh(efx->net_dev); |
673 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
674 | } |
675 | } | |
676 | ||
677 | static void efx_fini_port(struct efx_nic *efx) | |
678 | { | |
679 | EFX_LOG(efx, "shut down port\n"); | |
680 | ||
681 | if (!efx->port_initialized) | |
682 | return; | |
683 | ||
684 | falcon_fini_xmac(efx); | |
dc8cfa55 | 685 | efx->port_initialized = false; |
8ceee660 | 686 | |
dc8cfa55 | 687 | efx->link_up = false; |
8ceee660 BH |
688 | efx_link_status_changed(efx); |
689 | } | |
690 | ||
691 | static void efx_remove_port(struct efx_nic *efx) | |
692 | { | |
693 | EFX_LOG(efx, "destroying port\n"); | |
694 | ||
695 | falcon_remove_port(efx); | |
696 | } | |
697 | ||
698 | /************************************************************************** | |
699 | * | |
700 | * NIC handling | |
701 | * | |
702 | **************************************************************************/ | |
703 | ||
704 | /* This configures the PCI device to enable I/O and DMA. */ | |
705 | static int efx_init_io(struct efx_nic *efx) | |
706 | { | |
707 | struct pci_dev *pci_dev = efx->pci_dev; | |
708 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
709 | int rc; | |
710 | ||
711 | EFX_LOG(efx, "initialising I/O\n"); | |
712 | ||
713 | rc = pci_enable_device(pci_dev); | |
714 | if (rc) { | |
715 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
716 | goto fail1; | |
717 | } | |
718 | ||
719 | pci_set_master(pci_dev); | |
720 | ||
721 | /* Set the PCI DMA mask. Try all possibilities from our | |
722 | * genuine mask down to 32 bits, because some architectures | |
723 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
724 | * masks event though they reject 46 bit masks. | |
725 | */ | |
726 | while (dma_mask > 0x7fffffffUL) { | |
727 | if (pci_dma_supported(pci_dev, dma_mask) && | |
728 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
729 | break; | |
730 | dma_mask >>= 1; | |
731 | } | |
732 | if (rc) { | |
733 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
734 | goto fail2; | |
735 | } | |
736 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
737 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
738 | if (rc) { | |
739 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
740 | * fail with a mask that pci_set_dma_mask() accepted, | |
741 | * but just in case... | |
742 | */ | |
743 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
744 | goto fail2; | |
745 | } | |
746 | ||
747 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
748 | efx->type->mem_bar); | |
749 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
750 | if (rc) { | |
751 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
752 | rc = -EIO; | |
753 | goto fail3; | |
754 | } | |
755 | efx->membase = ioremap_nocache(efx->membase_phys, | |
756 | efx->type->mem_map_size); | |
757 | if (!efx->membase) { | |
086ea356 BH |
758 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
759 | efx->type->mem_bar, | |
760 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
761 | efx->type->mem_map_size); |
762 | rc = -ENOMEM; | |
763 | goto fail4; | |
764 | } | |
086ea356 BH |
765 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
766 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
767 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
768 | |
769 | return 0; | |
770 | ||
771 | fail4: | |
772 | release_mem_region(efx->membase_phys, efx->type->mem_map_size); | |
773 | fail3: | |
2c118e0f | 774 | efx->membase_phys = 0; |
8ceee660 BH |
775 | fail2: |
776 | pci_disable_device(efx->pci_dev); | |
777 | fail1: | |
778 | return rc; | |
779 | } | |
780 | ||
781 | static void efx_fini_io(struct efx_nic *efx) | |
782 | { | |
783 | EFX_LOG(efx, "shutting down I/O\n"); | |
784 | ||
785 | if (efx->membase) { | |
786 | iounmap(efx->membase); | |
787 | efx->membase = NULL; | |
788 | } | |
789 | ||
790 | if (efx->membase_phys) { | |
791 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 792 | efx->membase_phys = 0; |
8ceee660 BH |
793 | } |
794 | ||
795 | pci_disable_device(efx->pci_dev); | |
796 | } | |
797 | ||
46123d04 BH |
798 | /* Get number of RX queues wanted. Return number of online CPU |
799 | * packages in the expectation that an IRQ balancer will spread | |
800 | * interrupts across them. */ | |
801 | static int efx_wanted_rx_queues(void) | |
802 | { | |
803 | cpumask_t core_mask; | |
804 | int count; | |
805 | int cpu; | |
806 | ||
807 | cpus_clear(core_mask); | |
808 | count = 0; | |
809 | for_each_online_cpu(cpu) { | |
810 | if (!cpu_isset(cpu, core_mask)) { | |
811 | ++count; | |
812 | cpus_or(core_mask, core_mask, | |
813 | topology_core_siblings(cpu)); | |
814 | } | |
815 | } | |
816 | ||
817 | return count; | |
818 | } | |
819 | ||
820 | /* Probe the number and type of interrupts we are able to obtain, and | |
821 | * the resulting numbers of channels and RX queues. | |
822 | */ | |
8ceee660 BH |
823 | static void efx_probe_interrupts(struct efx_nic *efx) |
824 | { | |
46123d04 BH |
825 | int max_channels = |
826 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
827 | int rc, i; |
828 | ||
829 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
830 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
831 | int wanted_ints; | |
aa6ef27e | 832 | |
46123d04 BH |
833 | /* We want one RX queue and interrupt per CPU package |
834 | * (or as specified by the rss_cpus module parameter). | |
835 | * We will need one channel per interrupt. | |
836 | */ | |
837 | wanted_ints = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); | |
8831da7b | 838 | efx->n_rx_queues = min(wanted_ints, max_channels); |
8ceee660 | 839 | |
8831da7b | 840 | for (i = 0; i < efx->n_rx_queues; i++) |
8ceee660 | 841 | xentries[i].entry = i; |
8831da7b | 842 | rc = pci_enable_msix(efx->pci_dev, xentries, efx->n_rx_queues); |
8ceee660 | 843 | if (rc > 0) { |
8831da7b BH |
844 | EFX_BUG_ON_PARANOID(rc >= efx->n_rx_queues); |
845 | efx->n_rx_queues = rc; | |
8ceee660 | 846 | rc = pci_enable_msix(efx->pci_dev, xentries, |
8831da7b | 847 | efx->n_rx_queues); |
8ceee660 BH |
848 | } |
849 | ||
850 | if (rc == 0) { | |
8831da7b | 851 | for (i = 0; i < efx->n_rx_queues; i++) |
8ceee660 | 852 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
853 | } else { |
854 | /* Fall back to single channel MSI */ | |
855 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
856 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
857 | } | |
858 | } | |
859 | ||
860 | /* Try single interrupt MSI */ | |
861 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 862 | efx->n_rx_queues = 1; |
8ceee660 BH |
863 | rc = pci_enable_msi(efx->pci_dev); |
864 | if (rc == 0) { | |
865 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
866 | } else { |
867 | EFX_ERR(efx, "could not enable MSI\n"); | |
868 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
869 | } | |
870 | } | |
871 | ||
872 | /* Assume legacy interrupts */ | |
873 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 874 | efx->n_rx_queues = 1; |
8ceee660 BH |
875 | efx->legacy_irq = efx->pci_dev->irq; |
876 | } | |
877 | } | |
878 | ||
879 | static void efx_remove_interrupts(struct efx_nic *efx) | |
880 | { | |
881 | struct efx_channel *channel; | |
882 | ||
883 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 884 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
885 | channel->irq = 0; |
886 | pci_disable_msi(efx->pci_dev); | |
887 | pci_disable_msix(efx->pci_dev); | |
888 | ||
889 | /* Remove legacy interrupt */ | |
890 | efx->legacy_irq = 0; | |
891 | } | |
892 | ||
8831da7b | 893 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
894 | { |
895 | struct efx_tx_queue *tx_queue; | |
896 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 897 | |
60ac1065 BH |
898 | efx_for_each_tx_queue(tx_queue, efx) { |
899 | if (!EFX_INT_MODE_USE_MSI(efx) && separate_tx_and_rx_channels) | |
900 | tx_queue->channel = &efx->channel[1]; | |
901 | else | |
902 | tx_queue->channel = &efx->channel[0]; | |
903 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
904 | } | |
8ceee660 | 905 | |
8831da7b BH |
906 | efx_for_each_rx_queue(rx_queue, efx) { |
907 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
908 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
909 | } |
910 | } | |
911 | ||
912 | static int efx_probe_nic(struct efx_nic *efx) | |
913 | { | |
914 | int rc; | |
915 | ||
916 | EFX_LOG(efx, "creating NIC\n"); | |
917 | ||
918 | /* Carry out hardware-type specific initialisation */ | |
919 | rc = falcon_probe_nic(efx); | |
920 | if (rc) | |
921 | return rc; | |
922 | ||
923 | /* Determine the number of channels and RX queues by trying to hook | |
924 | * in MSI-X interrupts. */ | |
925 | efx_probe_interrupts(efx); | |
926 | ||
8831da7b | 927 | efx_set_channels(efx); |
8ceee660 BH |
928 | |
929 | /* Initialise the interrupt moderation settings */ | |
930 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
935 | static void efx_remove_nic(struct efx_nic *efx) | |
936 | { | |
937 | EFX_LOG(efx, "destroying NIC\n"); | |
938 | ||
939 | efx_remove_interrupts(efx); | |
940 | falcon_remove_nic(efx); | |
941 | } | |
942 | ||
943 | /************************************************************************** | |
944 | * | |
945 | * NIC startup/shutdown | |
946 | * | |
947 | *************************************************************************/ | |
948 | ||
949 | static int efx_probe_all(struct efx_nic *efx) | |
950 | { | |
951 | struct efx_channel *channel; | |
952 | int rc; | |
953 | ||
954 | /* Create NIC */ | |
955 | rc = efx_probe_nic(efx); | |
956 | if (rc) { | |
957 | EFX_ERR(efx, "failed to create NIC\n"); | |
958 | goto fail1; | |
959 | } | |
960 | ||
961 | /* Create port */ | |
962 | rc = efx_probe_port(efx); | |
963 | if (rc) { | |
964 | EFX_ERR(efx, "failed to create port\n"); | |
965 | goto fail2; | |
966 | } | |
967 | ||
968 | /* Create channels */ | |
969 | efx_for_each_channel(channel, efx) { | |
970 | rc = efx_probe_channel(channel); | |
971 | if (rc) { | |
972 | EFX_ERR(efx, "failed to create channel %d\n", | |
973 | channel->channel); | |
974 | goto fail3; | |
975 | } | |
976 | } | |
977 | ||
978 | return 0; | |
979 | ||
980 | fail3: | |
981 | efx_for_each_channel(channel, efx) | |
982 | efx_remove_channel(channel); | |
983 | efx_remove_port(efx); | |
984 | fail2: | |
985 | efx_remove_nic(efx); | |
986 | fail1: | |
987 | return rc; | |
988 | } | |
989 | ||
990 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
991 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
992 | * and ensures that the port is scheduled to be reconfigured. | |
993 | * This function is safe to call multiple times when the NIC is in any | |
994 | * state. */ | |
995 | static void efx_start_all(struct efx_nic *efx) | |
996 | { | |
997 | struct efx_channel *channel; | |
998 | ||
999 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1000 | ||
1001 | /* Check that it is appropriate to restart the interface. All | |
1002 | * of these flags are safe to read under just the rtnl lock */ | |
1003 | if (efx->port_enabled) | |
1004 | return; | |
1005 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1006 | return; | |
55668611 | 1007 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1008 | return; |
1009 | ||
1010 | /* Mark the port as enabled so port reconfigurations can start, then | |
1011 | * restart the transmit interface early so the watchdog timer stops */ | |
1012 | efx_start_port(efx); | |
dacccc74 SH |
1013 | if (efx_dev_registered(efx)) |
1014 | efx_wake_queue(efx); | |
8ceee660 BH |
1015 | |
1016 | efx_for_each_channel(channel, efx) | |
1017 | efx_start_channel(channel); | |
1018 | ||
1019 | falcon_enable_interrupts(efx); | |
1020 | ||
1021 | /* Start hardware monitor if we're in RUNNING */ | |
1022 | if (efx->state == STATE_RUNNING) | |
1023 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1024 | efx_monitor_interval); | |
1025 | } | |
1026 | ||
1027 | /* Flush all delayed work. Should only be called when no more delayed work | |
1028 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1029 | * since we're holding the rtnl_lock at this point. */ | |
1030 | static void efx_flush_all(struct efx_nic *efx) | |
1031 | { | |
1032 | struct efx_rx_queue *rx_queue; | |
1033 | ||
1034 | /* Make sure the hardware monitor is stopped */ | |
1035 | cancel_delayed_work_sync(&efx->monitor_work); | |
1036 | ||
1037 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1038 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1039 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1040 | |
1041 | /* Stop scheduled port reconfigurations */ | |
1042 | cancel_work_sync(&efx->reconfigure_work); | |
1043 | ||
1044 | } | |
1045 | ||
1046 | /* Quiesce hardware and software without bringing the link down. | |
1047 | * Safe to call multiple times, when the nic and interface is in any | |
1048 | * state. The caller is guaranteed to subsequently be in a position | |
1049 | * to modify any hardware and software state they see fit without | |
1050 | * taking locks. */ | |
1051 | static void efx_stop_all(struct efx_nic *efx) | |
1052 | { | |
1053 | struct efx_channel *channel; | |
1054 | ||
1055 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1056 | ||
1057 | /* port_enabled can be read safely under the rtnl lock */ | |
1058 | if (!efx->port_enabled) | |
1059 | return; | |
1060 | ||
1061 | /* Disable interrupts and wait for ISR to complete */ | |
1062 | falcon_disable_interrupts(efx); | |
1063 | if (efx->legacy_irq) | |
1064 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1065 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1066 | if (channel->irq) |
1067 | synchronize_irq(channel->irq); | |
b3475645 | 1068 | } |
8ceee660 BH |
1069 | |
1070 | /* Stop all NAPI processing and synchronous rx refills */ | |
1071 | efx_for_each_channel(channel, efx) | |
1072 | efx_stop_channel(channel); | |
1073 | ||
1074 | /* Stop all asynchronous port reconfigurations. Since all | |
1075 | * event processing has already been stopped, there is no | |
1076 | * window to loose phy events */ | |
1077 | efx_stop_port(efx); | |
1078 | ||
1079 | /* Flush reconfigure_work, refill_workqueue, monitor_work */ | |
1080 | efx_flush_all(efx); | |
1081 | ||
1082 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1083 | * flushes will complete in a timely fashion. */ | |
1084 | falcon_deconfigure_mac_wrapper(efx); | |
1085 | falcon_drain_tx_fifo(efx); | |
1086 | ||
1087 | /* Stop the kernel transmit interface late, so the watchdog | |
1088 | * timer isn't ticking over the flush */ | |
55668611 | 1089 | if (efx_dev_registered(efx)) { |
dacccc74 | 1090 | efx_stop_queue(efx); |
8ceee660 BH |
1091 | netif_tx_lock_bh(efx->net_dev); |
1092 | netif_tx_unlock_bh(efx->net_dev); | |
1093 | } | |
1094 | } | |
1095 | ||
1096 | static void efx_remove_all(struct efx_nic *efx) | |
1097 | { | |
1098 | struct efx_channel *channel; | |
1099 | ||
1100 | efx_for_each_channel(channel, efx) | |
1101 | efx_remove_channel(channel); | |
1102 | efx_remove_port(efx); | |
1103 | efx_remove_nic(efx); | |
1104 | } | |
1105 | ||
1106 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1107 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1108 | { |
8ceee660 BH |
1109 | EFX_ASSERT_RESET_SERIALISED(efx); |
1110 | ||
1111 | efx_stop_all(efx); | |
1112 | ||
1113 | efx_fini_channels(efx); | |
bc3c90a2 | 1114 | efx_init_channels(efx); |
8ceee660 BH |
1115 | |
1116 | efx_start_all(efx); | |
8ceee660 BH |
1117 | } |
1118 | ||
1119 | /************************************************************************** | |
1120 | * | |
1121 | * Interrupt moderation | |
1122 | * | |
1123 | **************************************************************************/ | |
1124 | ||
1125 | /* Set interrupt moderation parameters */ | |
1126 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1127 | { | |
1128 | struct efx_tx_queue *tx_queue; | |
1129 | struct efx_rx_queue *rx_queue; | |
1130 | ||
1131 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1132 | ||
1133 | efx_for_each_tx_queue(tx_queue, efx) | |
1134 | tx_queue->channel->irq_moderation = tx_usecs; | |
1135 | ||
1136 | efx_for_each_rx_queue(rx_queue, efx) | |
1137 | rx_queue->channel->irq_moderation = rx_usecs; | |
1138 | } | |
1139 | ||
1140 | /************************************************************************** | |
1141 | * | |
1142 | * Hardware monitor | |
1143 | * | |
1144 | **************************************************************************/ | |
1145 | ||
1146 | /* Run periodically off the general workqueue. Serialised against | |
1147 | * efx_reconfigure_port via the mac_lock */ | |
1148 | static void efx_monitor(struct work_struct *data) | |
1149 | { | |
1150 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1151 | monitor_work.work); | |
1152 | int rc = 0; | |
1153 | ||
1154 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1155 | raw_smp_processor_id()); | |
1156 | ||
1157 | ||
1158 | /* If the mac_lock is already held then it is likely a port | |
1159 | * reconfiguration is already in place, which will likely do | |
1160 | * most of the work of check_hw() anyway. */ | |
1161 | if (!mutex_trylock(&efx->mac_lock)) { | |
1162 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1163 | efx_monitor_interval); | |
1164 | return; | |
1165 | } | |
1166 | ||
1167 | if (efx->port_enabled) | |
1168 | rc = falcon_check_xmac(efx); | |
1169 | mutex_unlock(&efx->mac_lock); | |
1170 | ||
1171 | if (rc) { | |
1172 | if (monitor_reset) { | |
1173 | EFX_ERR(efx, "hardware monitor detected a fault: " | |
1174 | "triggering reset\n"); | |
1175 | efx_schedule_reset(efx, RESET_TYPE_MONITOR); | |
1176 | } else { | |
1177 | EFX_ERR(efx, "hardware monitor detected a fault, " | |
1178 | "skipping reset\n"); | |
1179 | } | |
1180 | } | |
1181 | ||
1182 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1183 | efx_monitor_interval); | |
1184 | } | |
1185 | ||
1186 | /************************************************************************** | |
1187 | * | |
1188 | * ioctls | |
1189 | * | |
1190 | *************************************************************************/ | |
1191 | ||
1192 | /* Net device ioctl | |
1193 | * Context: process, rtnl_lock() held. | |
1194 | */ | |
1195 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1196 | { | |
767e468c | 1197 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1198 | |
1199 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1200 | ||
1201 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1202 | } | |
1203 | ||
1204 | /************************************************************************** | |
1205 | * | |
1206 | * NAPI interface | |
1207 | * | |
1208 | **************************************************************************/ | |
1209 | ||
1210 | static int efx_init_napi(struct efx_nic *efx) | |
1211 | { | |
1212 | struct efx_channel *channel; | |
1213 | int rc; | |
1214 | ||
1215 | efx_for_each_channel(channel, efx) { | |
1216 | channel->napi_dev = efx->net_dev; | |
1217 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1218 | if (rc) | |
1219 | goto err; | |
1220 | } | |
1221 | return 0; | |
1222 | err: | |
1223 | efx_fini_napi(efx); | |
1224 | return rc; | |
1225 | } | |
1226 | ||
1227 | static void efx_fini_napi(struct efx_nic *efx) | |
1228 | { | |
1229 | struct efx_channel *channel; | |
1230 | ||
1231 | efx_for_each_channel(channel, efx) { | |
1232 | efx_lro_fini(&channel->lro_mgr); | |
1233 | channel->napi_dev = NULL; | |
1234 | } | |
1235 | } | |
1236 | ||
1237 | /************************************************************************** | |
1238 | * | |
1239 | * Kernel netpoll interface | |
1240 | * | |
1241 | *************************************************************************/ | |
1242 | ||
1243 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1244 | ||
1245 | /* Although in the common case interrupts will be disabled, this is not | |
1246 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1247 | * so no locking is required. | |
1248 | */ | |
1249 | static void efx_netpoll(struct net_device *net_dev) | |
1250 | { | |
767e468c | 1251 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1252 | struct efx_channel *channel; |
1253 | ||
64ee3120 | 1254 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1255 | efx_schedule_channel(channel); |
1256 | } | |
1257 | ||
1258 | #endif | |
1259 | ||
1260 | /************************************************************************** | |
1261 | * | |
1262 | * Kernel net device interface | |
1263 | * | |
1264 | *************************************************************************/ | |
1265 | ||
1266 | /* Context: process, rtnl_lock() held. */ | |
1267 | static int efx_net_open(struct net_device *net_dev) | |
1268 | { | |
767e468c | 1269 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1270 | EFX_ASSERT_RESET_SERIALISED(efx); |
1271 | ||
1272 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1273 | raw_smp_processor_id()); | |
1274 | ||
f8b87c17 BH |
1275 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1276 | return -EBUSY; | |
1277 | ||
8ceee660 BH |
1278 | efx_start_all(efx); |
1279 | return 0; | |
1280 | } | |
1281 | ||
1282 | /* Context: process, rtnl_lock() held. | |
1283 | * Note that the kernel will ignore our return code; this method | |
1284 | * should really be a void. | |
1285 | */ | |
1286 | static int efx_net_stop(struct net_device *net_dev) | |
1287 | { | |
767e468c | 1288 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1289 | |
1290 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1291 | raw_smp_processor_id()); | |
1292 | ||
1293 | /* Stop the device and flush all the channels */ | |
1294 | efx_stop_all(efx); | |
1295 | efx_fini_channels(efx); | |
bc3c90a2 | 1296 | efx_init_channels(efx); |
8ceee660 BH |
1297 | |
1298 | return 0; | |
1299 | } | |
1300 | ||
5b9e207c | 1301 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1302 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1303 | { | |
767e468c | 1304 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1305 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1306 | struct net_device_stats *stats = &net_dev->stats; | |
1307 | ||
5b9e207c BH |
1308 | /* Update stats if possible, but do not wait if another thread |
1309 | * is updating them (or resetting the NIC); slightly stale | |
1310 | * stats are acceptable. | |
1311 | */ | |
8ceee660 BH |
1312 | if (!spin_trylock(&efx->stats_lock)) |
1313 | return stats; | |
1314 | if (efx->state == STATE_RUNNING) { | |
1315 | falcon_update_stats_xmac(efx); | |
1316 | falcon_update_nic_stats(efx); | |
1317 | } | |
1318 | spin_unlock(&efx->stats_lock); | |
1319 | ||
1320 | stats->rx_packets = mac_stats->rx_packets; | |
1321 | stats->tx_packets = mac_stats->tx_packets; | |
1322 | stats->rx_bytes = mac_stats->rx_bytes; | |
1323 | stats->tx_bytes = mac_stats->tx_bytes; | |
1324 | stats->multicast = mac_stats->rx_multicast; | |
1325 | stats->collisions = mac_stats->tx_collision; | |
1326 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1327 | mac_stats->rx_length_error); | |
1328 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1329 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1330 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1331 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1332 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1333 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1334 | ||
1335 | stats->rx_errors = (stats->rx_length_errors + | |
1336 | stats->rx_over_errors + | |
1337 | stats->rx_crc_errors + | |
1338 | stats->rx_frame_errors + | |
1339 | stats->rx_fifo_errors + | |
1340 | stats->rx_missed_errors + | |
1341 | mac_stats->rx_symbol_error); | |
1342 | stats->tx_errors = (stats->tx_window_errors + | |
1343 | mac_stats->tx_bad); | |
1344 | ||
1345 | return stats; | |
1346 | } | |
1347 | ||
1348 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1349 | static void efx_watchdog(struct net_device *net_dev) | |
1350 | { | |
767e468c | 1351 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1352 | |
1353 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d: %s\n", | |
1354 | atomic_read(&efx->netif_stop_count), efx->port_enabled, | |
1355 | monitor_reset ? "resetting channels" : "skipping reset"); | |
1356 | ||
1357 | if (monitor_reset) | |
1358 | efx_schedule_reset(efx, RESET_TYPE_MONITOR); | |
1359 | } | |
1360 | ||
1361 | ||
1362 | /* Context: process, rtnl_lock() held. */ | |
1363 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1364 | { | |
767e468c | 1365 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1366 | int rc = 0; |
1367 | ||
1368 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1369 | ||
1370 | if (new_mtu > EFX_MAX_MTU) | |
1371 | return -EINVAL; | |
1372 | ||
1373 | efx_stop_all(efx); | |
1374 | ||
1375 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1376 | ||
1377 | efx_fini_channels(efx); | |
1378 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1379 | efx_init_channels(efx); |
8ceee660 BH |
1380 | |
1381 | efx_start_all(efx); | |
1382 | return rc; | |
8ceee660 BH |
1383 | } |
1384 | ||
1385 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1386 | { | |
767e468c | 1387 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1388 | struct sockaddr *addr = data; |
1389 | char *new_addr = addr->sa_data; | |
1390 | ||
1391 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1392 | ||
1393 | if (!is_valid_ether_addr(new_addr)) { | |
1394 | DECLARE_MAC_BUF(mac); | |
1395 | EFX_ERR(efx, "invalid ethernet MAC address requested: %s\n", | |
1396 | print_mac(mac, new_addr)); | |
1397 | return -EINVAL; | |
1398 | } | |
1399 | ||
1400 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1401 | ||
1402 | /* Reconfigure the MAC */ | |
1403 | efx_reconfigure_port(efx); | |
1404 | ||
1405 | return 0; | |
1406 | } | |
1407 | ||
1408 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1409 | static void efx_set_multicast_list(struct net_device *net_dev) | |
1410 | { | |
767e468c | 1411 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1412 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1413 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
dc8cfa55 | 1414 | bool promiscuous; |
8ceee660 BH |
1415 | u32 crc; |
1416 | int bit; | |
1417 | int i; | |
1418 | ||
1419 | /* Set per-MAC promiscuity flag and reconfigure MAC if necessary */ | |
dc8cfa55 | 1420 | promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1421 | if (efx->promiscuous != promiscuous) { |
1422 | efx->promiscuous = promiscuous; | |
1423 | /* Close the window between efx_stop_port() and efx_flush_all() | |
1424 | * by only queuing work when the port is enabled. */ | |
1425 | if (efx->port_enabled) | |
1426 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
1427 | } | |
1428 | ||
1429 | /* Build multicast hash table */ | |
1430 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1431 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1432 | } else { | |
1433 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1434 | for (i = 0; i < net_dev->mc_count; i++) { | |
1435 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1436 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1437 | set_bit_le(bit, mc_hash->byte); | |
1438 | mc_list = mc_list->next; | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | /* Create and activate new global multicast hash table */ | |
1443 | falcon_set_multicast_hash(efx); | |
1444 | } | |
1445 | ||
1446 | static int efx_netdev_event(struct notifier_block *this, | |
1447 | unsigned long event, void *ptr) | |
1448 | { | |
d3208b5e | 1449 | struct net_device *net_dev = ptr; |
8ceee660 BH |
1450 | |
1451 | if (net_dev->open == efx_net_open && event == NETDEV_CHANGENAME) { | |
767e468c | 1452 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1453 | |
1454 | strcpy(efx->name, net_dev->name); | |
1455 | } | |
1456 | ||
1457 | return NOTIFY_DONE; | |
1458 | } | |
1459 | ||
1460 | static struct notifier_block efx_netdev_notifier = { | |
1461 | .notifier_call = efx_netdev_event, | |
1462 | }; | |
1463 | ||
1464 | static int efx_register_netdev(struct efx_nic *efx) | |
1465 | { | |
1466 | struct net_device *net_dev = efx->net_dev; | |
1467 | int rc; | |
1468 | ||
1469 | net_dev->watchdog_timeo = 5 * HZ; | |
1470 | net_dev->irq = efx->pci_dev->irq; | |
1471 | net_dev->open = efx_net_open; | |
1472 | net_dev->stop = efx_net_stop; | |
1473 | net_dev->get_stats = efx_net_stats; | |
1474 | net_dev->tx_timeout = &efx_watchdog; | |
1475 | net_dev->hard_start_xmit = efx_hard_start_xmit; | |
1476 | net_dev->do_ioctl = efx_ioctl; | |
1477 | net_dev->change_mtu = efx_change_mtu; | |
1478 | net_dev->set_mac_address = efx_set_mac_address; | |
1479 | net_dev->set_multicast_list = efx_set_multicast_list; | |
1480 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1481 | net_dev->poll_controller = efx_netpoll; | |
1482 | #endif | |
1483 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); | |
1484 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1485 | ||
1486 | /* Always start with carrier off; PHY events will detect the link */ | |
1487 | netif_carrier_off(efx->net_dev); | |
1488 | ||
1489 | /* Clear MAC statistics */ | |
1490 | falcon_update_stats_xmac(efx); | |
1491 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
1492 | ||
1493 | rc = register_netdev(net_dev); | |
1494 | if (rc) { | |
1495 | EFX_ERR(efx, "could not register net dev\n"); | |
1496 | return rc; | |
1497 | } | |
1498 | strcpy(efx->name, net_dev->name); | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1504 | { | |
1505 | struct efx_tx_queue *tx_queue; | |
1506 | ||
1507 | if (!efx->net_dev) | |
1508 | return; | |
1509 | ||
767e468c | 1510 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1511 | |
1512 | /* Free up any skbs still remaining. This has to happen before | |
1513 | * we try to unregister the netdev as running their destructors | |
1514 | * may be needed to get the device ref. count to 0. */ | |
1515 | efx_for_each_tx_queue(tx_queue, efx) | |
1516 | efx_release_tx_buffers(tx_queue); | |
1517 | ||
55668611 | 1518 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1519 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1520 | unregister_netdev(efx->net_dev); | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | /************************************************************************** | |
1525 | * | |
1526 | * Device reset and suspend | |
1527 | * | |
1528 | **************************************************************************/ | |
1529 | ||
1530 | /* The final hardware and software finalisation before reset. */ | |
1531 | static int efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
1532 | { | |
1533 | int rc; | |
1534 | ||
1535 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1536 | ||
1537 | rc = falcon_xmac_get_settings(efx, ecmd); | |
1538 | if (rc) { | |
1539 | EFX_ERR(efx, "could not back up PHY settings\n"); | |
1540 | goto fail; | |
1541 | } | |
1542 | ||
1543 | efx_fini_channels(efx); | |
1544 | return 0; | |
1545 | ||
1546 | fail: | |
1547 | return rc; | |
1548 | } | |
1549 | ||
1550 | /* The first part of software initialisation after a hardware reset | |
1551 | * This function does not handle serialisation with the kernel, it | |
1552 | * assumes the caller has done this */ | |
1553 | static int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
1554 | { | |
1555 | int rc; | |
1556 | ||
bc3c90a2 | 1557 | efx_init_channels(efx); |
8ceee660 BH |
1558 | |
1559 | /* Restore MAC and PHY settings. */ | |
1560 | rc = falcon_xmac_set_settings(efx, ecmd); | |
1561 | if (rc) { | |
1562 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
bc3c90a2 | 1563 | goto fail; |
8ceee660 BH |
1564 | } |
1565 | ||
1566 | return 0; | |
1567 | ||
bc3c90a2 | 1568 | fail: |
8ceee660 | 1569 | efx_fini_channels(efx); |
8ceee660 BH |
1570 | return rc; |
1571 | } | |
1572 | ||
1573 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1574 | * Note that the reset may fail, in which case the card will be left | |
1575 | * in a most-probably-unusable state. | |
1576 | * | |
1577 | * This function will sleep. You cannot reset from within an atomic | |
1578 | * state; use efx_schedule_reset() instead. | |
1579 | * | |
1580 | * Grabs the rtnl_lock. | |
1581 | */ | |
1582 | static int efx_reset(struct efx_nic *efx) | |
1583 | { | |
1584 | struct ethtool_cmd ecmd; | |
1585 | enum reset_type method = efx->reset_pending; | |
1586 | int rc; | |
1587 | ||
1588 | /* Serialise with kernel interfaces */ | |
1589 | rtnl_lock(); | |
1590 | ||
1591 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1592 | * flag set so that efx_pci_probe_main will be retried */ | |
1593 | if (efx->state != STATE_RUNNING) { | |
1594 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1595 | goto unlock_rtnl; | |
1596 | } | |
1597 | ||
1598 | efx->state = STATE_RESETTING; | |
1599 | EFX_INFO(efx, "resetting (%d)\n", method); | |
1600 | ||
1601 | /* The net_dev->get_stats handler is quite slow, and will fail | |
1602 | * if a fetch is pending over reset. Serialise against it. */ | |
1603 | spin_lock(&efx->stats_lock); | |
1604 | spin_unlock(&efx->stats_lock); | |
1605 | ||
1606 | efx_stop_all(efx); | |
1607 | mutex_lock(&efx->mac_lock); | |
1608 | ||
1609 | rc = efx_reset_down(efx, &ecmd); | |
1610 | if (rc) | |
1611 | goto fail1; | |
1612 | ||
1613 | rc = falcon_reset_hw(efx, method); | |
1614 | if (rc) { | |
1615 | EFX_ERR(efx, "failed to reset hardware\n"); | |
1616 | goto fail2; | |
1617 | } | |
1618 | ||
1619 | /* Allow resets to be rescheduled. */ | |
1620 | efx->reset_pending = RESET_TYPE_NONE; | |
1621 | ||
1622 | /* Reinitialise bus-mastering, which may have been turned off before | |
1623 | * the reset was scheduled. This is still appropriate, even in the | |
1624 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1625 | * can respond to requests. */ | |
1626 | pci_set_master(efx->pci_dev); | |
1627 | ||
1628 | /* Reinitialise device. This is appropriate in the RESET_TYPE_DISABLE | |
1629 | * case so the driver can talk to external SRAM */ | |
1630 | rc = falcon_init_nic(efx); | |
1631 | if (rc) { | |
1632 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1633 | goto fail3; | |
1634 | } | |
1635 | ||
1636 | /* Leave device stopped if necessary */ | |
1637 | if (method == RESET_TYPE_DISABLE) { | |
1638 | /* Reinitialise the device anyway so the driver unload sequence | |
1639 | * can talk to the external SRAM */ | |
91ad757c | 1640 | falcon_init_nic(efx); |
8ceee660 BH |
1641 | rc = -EIO; |
1642 | goto fail4; | |
1643 | } | |
1644 | ||
1645 | rc = efx_reset_up(efx, &ecmd); | |
1646 | if (rc) | |
1647 | goto fail5; | |
1648 | ||
1649 | mutex_unlock(&efx->mac_lock); | |
1650 | EFX_LOG(efx, "reset complete\n"); | |
1651 | ||
1652 | efx->state = STATE_RUNNING; | |
1653 | efx_start_all(efx); | |
1654 | ||
1655 | unlock_rtnl: | |
1656 | rtnl_unlock(); | |
1657 | return 0; | |
1658 | ||
1659 | fail5: | |
1660 | fail4: | |
1661 | fail3: | |
1662 | fail2: | |
1663 | fail1: | |
1664 | EFX_ERR(efx, "has been disabled\n"); | |
1665 | efx->state = STATE_DISABLED; | |
1666 | ||
1667 | mutex_unlock(&efx->mac_lock); | |
1668 | rtnl_unlock(); | |
1669 | efx_unregister_netdev(efx); | |
1670 | efx_fini_port(efx); | |
1671 | return rc; | |
1672 | } | |
1673 | ||
1674 | /* The worker thread exists so that code that cannot sleep can | |
1675 | * schedule a reset for later. | |
1676 | */ | |
1677 | static void efx_reset_work(struct work_struct *data) | |
1678 | { | |
1679 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1680 | ||
1681 | efx_reset(nic); | |
1682 | } | |
1683 | ||
1684 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1685 | { | |
1686 | enum reset_type method; | |
1687 | ||
1688 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1689 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1690 | return; | |
1691 | } | |
1692 | ||
1693 | switch (type) { | |
1694 | case RESET_TYPE_INVISIBLE: | |
1695 | case RESET_TYPE_ALL: | |
1696 | case RESET_TYPE_WORLD: | |
1697 | case RESET_TYPE_DISABLE: | |
1698 | method = type; | |
1699 | break; | |
1700 | case RESET_TYPE_RX_RECOVERY: | |
1701 | case RESET_TYPE_RX_DESC_FETCH: | |
1702 | case RESET_TYPE_TX_DESC_FETCH: | |
1703 | case RESET_TYPE_TX_SKIP: | |
1704 | method = RESET_TYPE_INVISIBLE; | |
1705 | break; | |
1706 | default: | |
1707 | method = RESET_TYPE_ALL; | |
1708 | break; | |
1709 | } | |
1710 | ||
1711 | if (method != type) | |
1712 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1713 | else | |
1714 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1715 | ||
1716 | efx->reset_pending = method; | |
1717 | ||
8d9853d9 | 1718 | queue_work(efx->reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1719 | } |
1720 | ||
1721 | /************************************************************************** | |
1722 | * | |
1723 | * List of NICs we support | |
1724 | * | |
1725 | **************************************************************************/ | |
1726 | ||
1727 | /* PCI device ID table */ | |
1728 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1729 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1730 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1731 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1732 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1733 | {0} /* end of list */ | |
1734 | }; | |
1735 | ||
1736 | /************************************************************************** | |
1737 | * | |
1738 | * Dummy PHY/MAC/Board operations | |
1739 | * | |
01aad7b6 | 1740 | * Can be used for some unimplemented operations |
8ceee660 BH |
1741 | * Needed so all function pointers are valid and do not have to be tested |
1742 | * before use | |
1743 | * | |
1744 | **************************************************************************/ | |
1745 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1746 | { | |
1747 | return 0; | |
1748 | } | |
1749 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1750 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 BH |
1751 | |
1752 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1753 | .init = efx_port_dummy_op_int, | |
1754 | .reconfigure = efx_port_dummy_op_void, | |
1755 | .check_hw = efx_port_dummy_op_int, | |
1756 | .fini = efx_port_dummy_op_void, | |
1757 | .clear_interrupt = efx_port_dummy_op_void, | |
1758 | .reset_xaui = efx_port_dummy_op_void, | |
1759 | }; | |
1760 | ||
8ceee660 | 1761 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 BH |
1762 | .init = efx_port_dummy_op_int, |
1763 | .init_leds = efx_port_dummy_op_int, | |
1764 | .set_fault_led = efx_port_dummy_op_blink, | |
1765 | .blink = efx_port_dummy_op_blink, | |
1766 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1767 | }; |
1768 | ||
1769 | /************************************************************************** | |
1770 | * | |
1771 | * Data housekeeping | |
1772 | * | |
1773 | **************************************************************************/ | |
1774 | ||
1775 | /* This zeroes out and then fills in the invariants in a struct | |
1776 | * efx_nic (including all sub-structures). | |
1777 | */ | |
1778 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1779 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1780 | { | |
1781 | struct efx_channel *channel; | |
1782 | struct efx_tx_queue *tx_queue; | |
1783 | struct efx_rx_queue *rx_queue; | |
1784 | int i, rc; | |
1785 | ||
1786 | /* Initialise common structures */ | |
1787 | memset(efx, 0, sizeof(*efx)); | |
1788 | spin_lock_init(&efx->biu_lock); | |
1789 | spin_lock_init(&efx->phy_lock); | |
1790 | INIT_WORK(&efx->reset_work, efx_reset_work); | |
1791 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1792 | efx->pci_dev = pci_dev; | |
1793 | efx->state = STATE_INIT; | |
1794 | efx->reset_pending = RESET_TYPE_NONE; | |
1795 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1796 | efx->board_info = efx_dummy_board_info; | |
1797 | ||
1798 | efx->net_dev = net_dev; | |
dc8cfa55 | 1799 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1800 | spin_lock_init(&efx->netif_stop_lock); |
1801 | spin_lock_init(&efx->stats_lock); | |
1802 | mutex_init(&efx->mac_lock); | |
1803 | efx->phy_op = &efx_dummy_phy_operations; | |
1804 | efx->mii.dev = net_dev; | |
1805 | INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work); | |
1806 | atomic_set(&efx->netif_stop_count, 1); | |
1807 | ||
1808 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1809 | channel = &efx->channel[i]; | |
1810 | channel->efx = efx; | |
1811 | channel->channel = i; | |
dc8cfa55 | 1812 | channel->work_pending = false; |
8ceee660 | 1813 | } |
60ac1065 | 1814 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1815 | tx_queue = &efx->tx_queue[i]; |
1816 | tx_queue->efx = efx; | |
1817 | tx_queue->queue = i; | |
1818 | tx_queue->buffer = NULL; | |
1819 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1820 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1821 | } |
1822 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1823 | rx_queue = &efx->rx_queue[i]; | |
1824 | rx_queue->efx = efx; | |
1825 | rx_queue->queue = i; | |
1826 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1827 | rx_queue->buffer = NULL; | |
1828 | spin_lock_init(&rx_queue->add_lock); | |
1829 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1830 | } | |
1831 | ||
1832 | efx->type = type; | |
1833 | ||
1834 | /* Sanity-check NIC type */ | |
1835 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1836 | (efx->type->txd_ring_mask + 1)); | |
1837 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1838 | (efx->type->rxd_ring_mask + 1)); | |
1839 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1840 | (efx->type->evq_size - 1)); | |
1841 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1842 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1843 | (efx->type->txd_ring_mask + 1 + | |
1844 | efx->type->rxd_ring_mask + 1)); | |
1845 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1846 | ||
1847 | /* Higher numbered interrupt modes are less capable! */ | |
1848 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1849 | interrupt_mode); | |
1850 | ||
1851 | efx->workqueue = create_singlethread_workqueue("sfc_work"); | |
1852 | if (!efx->workqueue) { | |
1853 | rc = -ENOMEM; | |
1854 | goto fail1; | |
1855 | } | |
1856 | ||
8d9853d9 BH |
1857 | efx->reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
1858 | if (!efx->reset_workqueue) { | |
1859 | rc = -ENOMEM; | |
1860 | goto fail2; | |
1861 | } | |
1862 | ||
8ceee660 BH |
1863 | return 0; |
1864 | ||
8d9853d9 BH |
1865 | fail2: |
1866 | destroy_workqueue(efx->workqueue); | |
1867 | efx->workqueue = NULL; | |
1868 | ||
8ceee660 BH |
1869 | fail1: |
1870 | return rc; | |
1871 | } | |
1872 | ||
1873 | static void efx_fini_struct(struct efx_nic *efx) | |
1874 | { | |
8d9853d9 BH |
1875 | if (efx->reset_workqueue) { |
1876 | destroy_workqueue(efx->reset_workqueue); | |
1877 | efx->reset_workqueue = NULL; | |
1878 | } | |
8ceee660 BH |
1879 | if (efx->workqueue) { |
1880 | destroy_workqueue(efx->workqueue); | |
1881 | efx->workqueue = NULL; | |
1882 | } | |
1883 | } | |
1884 | ||
1885 | /************************************************************************** | |
1886 | * | |
1887 | * PCI interface | |
1888 | * | |
1889 | **************************************************************************/ | |
1890 | ||
1891 | /* Main body of final NIC shutdown code | |
1892 | * This is called only at module unload (or hotplug removal). | |
1893 | */ | |
1894 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1895 | { | |
1896 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1897 | ||
1898 | /* Skip everything if we never obtained a valid membase */ | |
1899 | if (!efx->membase) | |
1900 | return; | |
1901 | ||
1902 | efx_fini_channels(efx); | |
1903 | efx_fini_port(efx); | |
1904 | ||
1905 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1906 | efx->board_info.fini(efx); |
8ceee660 BH |
1907 | falcon_fini_interrupt(efx); |
1908 | ||
1909 | efx_fini_napi(efx); | |
1910 | efx_remove_all(efx); | |
1911 | } | |
1912 | ||
1913 | /* Final NIC shutdown | |
1914 | * This is called only at module unload (or hotplug removal). | |
1915 | */ | |
1916 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1917 | { | |
1918 | struct efx_nic *efx; | |
1919 | ||
1920 | efx = pci_get_drvdata(pci_dev); | |
1921 | if (!efx) | |
1922 | return; | |
1923 | ||
1924 | /* Mark the NIC as fini, then stop the interface */ | |
1925 | rtnl_lock(); | |
1926 | efx->state = STATE_FINI; | |
1927 | dev_close(efx->net_dev); | |
1928 | ||
1929 | /* Allow any queued efx_resets() to complete */ | |
1930 | rtnl_unlock(); | |
1931 | ||
1932 | if (efx->membase == NULL) | |
1933 | goto out; | |
1934 | ||
1935 | efx_unregister_netdev(efx); | |
1936 | ||
1937 | /* Wait for any scheduled resets to complete. No more will be | |
1938 | * scheduled from this point because efx_stop_all() has been | |
1939 | * called, we are no longer registered with driverlink, and | |
1940 | * the net_device's have been removed. */ | |
8d9853d9 | 1941 | flush_workqueue(efx->reset_workqueue); |
8ceee660 BH |
1942 | |
1943 | efx_pci_remove_main(efx); | |
1944 | ||
1945 | out: | |
1946 | efx_fini_io(efx); | |
1947 | EFX_LOG(efx, "shutdown successful\n"); | |
1948 | ||
1949 | pci_set_drvdata(pci_dev, NULL); | |
1950 | efx_fini_struct(efx); | |
1951 | free_netdev(efx->net_dev); | |
1952 | }; | |
1953 | ||
1954 | /* Main body of NIC initialisation | |
1955 | * This is called at module load (or hotplug insertion, theoretically). | |
1956 | */ | |
1957 | static int efx_pci_probe_main(struct efx_nic *efx) | |
1958 | { | |
1959 | int rc; | |
1960 | ||
1961 | /* Do start-of-day initialisation */ | |
1962 | rc = efx_probe_all(efx); | |
1963 | if (rc) | |
1964 | goto fail1; | |
1965 | ||
1966 | rc = efx_init_napi(efx); | |
1967 | if (rc) | |
1968 | goto fail2; | |
1969 | ||
1970 | /* Initialise the board */ | |
1971 | rc = efx->board_info.init(efx); | |
1972 | if (rc) { | |
1973 | EFX_ERR(efx, "failed to initialise board\n"); | |
1974 | goto fail3; | |
1975 | } | |
1976 | ||
1977 | rc = falcon_init_nic(efx); | |
1978 | if (rc) { | |
1979 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1980 | goto fail4; | |
1981 | } | |
1982 | ||
1983 | rc = efx_init_port(efx); | |
1984 | if (rc) { | |
1985 | EFX_ERR(efx, "failed to initialise port\n"); | |
1986 | goto fail5; | |
1987 | } | |
1988 | ||
bc3c90a2 | 1989 | efx_init_channels(efx); |
8ceee660 BH |
1990 | |
1991 | rc = falcon_init_interrupt(efx); | |
1992 | if (rc) | |
bc3c90a2 | 1993 | goto fail6; |
8ceee660 BH |
1994 | |
1995 | return 0; | |
1996 | ||
8ceee660 | 1997 | fail6: |
bc3c90a2 | 1998 | efx_fini_channels(efx); |
8ceee660 BH |
1999 | efx_fini_port(efx); |
2000 | fail5: | |
2001 | fail4: | |
2002 | fail3: | |
2003 | efx_fini_napi(efx); | |
2004 | fail2: | |
2005 | efx_remove_all(efx); | |
2006 | fail1: | |
2007 | return rc; | |
2008 | } | |
2009 | ||
2010 | /* NIC initialisation | |
2011 | * | |
2012 | * This is called at module load (or hotplug insertion, | |
2013 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2014 | * sets up and registers the network devices with the kernel and hooks | |
2015 | * the interrupt service routine. It does not prepare the device for | |
2016 | * transmission; this is left to the first time one of the network | |
2017 | * interfaces is brought up (i.e. efx_net_open). | |
2018 | */ | |
2019 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2020 | const struct pci_device_id *entry) | |
2021 | { | |
2022 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2023 | struct net_device *net_dev; | |
2024 | struct efx_nic *efx; | |
2025 | int i, rc; | |
2026 | ||
2027 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2028 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2029 | if (!net_dev) | |
2030 | return -ENOMEM; | |
b9b39b62 BH |
2031 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2032 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2033 | if (lro) |
2034 | net_dev->features |= NETIF_F_LRO; | |
28506563 BH |
2035 | /* Mask for features that also apply to VLAN devices */ |
2036 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2037 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2038 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2039 | pci_set_drvdata(pci_dev, efx); |
2040 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2041 | if (rc) | |
2042 | goto fail1; | |
2043 | ||
2044 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2045 | ||
2046 | /* Set up basic I/O (BAR mappings etc) */ | |
2047 | rc = efx_init_io(efx); | |
2048 | if (rc) | |
2049 | goto fail2; | |
2050 | ||
2051 | /* No serialisation is required with the reset path because | |
2052 | * we're in STATE_INIT. */ | |
2053 | for (i = 0; i < 5; i++) { | |
2054 | rc = efx_pci_probe_main(efx); | |
2055 | if (rc == 0) | |
2056 | break; | |
2057 | ||
2058 | /* Serialise against efx_reset(). No more resets will be | |
2059 | * scheduled since efx_stop_all() has been called, and we | |
2060 | * have not and never have been registered with either | |
2061 | * the rtnetlink or driverlink layers. */ | |
8d9853d9 | 2062 | flush_workqueue(efx->reset_workqueue); |
8ceee660 BH |
2063 | |
2064 | /* Retry if a recoverably reset event has been scheduled */ | |
2065 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2066 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2067 | goto fail3; | |
2068 | ||
2069 | efx->reset_pending = RESET_TYPE_NONE; | |
2070 | } | |
2071 | ||
2072 | if (rc) { | |
2073 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2074 | goto fail4; | |
2075 | } | |
2076 | ||
2077 | /* Switch to the running state before we expose the device to | |
2078 | * the OS. This is to ensure that the initial gathering of | |
2079 | * MAC stats succeeds. */ | |
2080 | rtnl_lock(); | |
2081 | efx->state = STATE_RUNNING; | |
2082 | rtnl_unlock(); | |
2083 | ||
2084 | rc = efx_register_netdev(efx); | |
2085 | if (rc) | |
2086 | goto fail5; | |
2087 | ||
2088 | EFX_LOG(efx, "initialisation successful\n"); | |
2089 | ||
2090 | return 0; | |
2091 | ||
2092 | fail5: | |
2093 | efx_pci_remove_main(efx); | |
2094 | fail4: | |
2095 | fail3: | |
2096 | efx_fini_io(efx); | |
2097 | fail2: | |
2098 | efx_fini_struct(efx); | |
2099 | fail1: | |
2100 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2101 | free_netdev(net_dev); | |
2102 | return rc; | |
2103 | } | |
2104 | ||
2105 | static struct pci_driver efx_pci_driver = { | |
2106 | .name = EFX_DRIVER_NAME, | |
2107 | .id_table = efx_pci_table, | |
2108 | .probe = efx_pci_probe, | |
2109 | .remove = efx_pci_remove, | |
2110 | }; | |
2111 | ||
2112 | /************************************************************************** | |
2113 | * | |
2114 | * Kernel module interface | |
2115 | * | |
2116 | *************************************************************************/ | |
2117 | ||
2118 | module_param(interrupt_mode, uint, 0444); | |
2119 | MODULE_PARM_DESC(interrupt_mode, | |
2120 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2121 | ||
2122 | static int __init efx_init_module(void) | |
2123 | { | |
2124 | int rc; | |
2125 | ||
2126 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2127 | ||
2128 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2129 | if (rc) | |
2130 | goto err_notifier; | |
2131 | ||
2132 | refill_workqueue = create_workqueue("sfc_refill"); | |
2133 | if (!refill_workqueue) { | |
2134 | rc = -ENOMEM; | |
2135 | goto err_refill; | |
2136 | } | |
2137 | ||
2138 | rc = pci_register_driver(&efx_pci_driver); | |
2139 | if (rc < 0) | |
2140 | goto err_pci; | |
2141 | ||
2142 | return 0; | |
2143 | ||
2144 | err_pci: | |
2145 | destroy_workqueue(refill_workqueue); | |
2146 | err_refill: | |
2147 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2148 | err_notifier: | |
2149 | return rc; | |
2150 | } | |
2151 | ||
2152 | static void __exit efx_exit_module(void) | |
2153 | { | |
2154 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2155 | ||
2156 | pci_unregister_driver(&efx_pci_driver); | |
2157 | destroy_workqueue(refill_workqueue); | |
2158 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2159 | ||
2160 | } | |
2161 | ||
2162 | module_init(efx_init_module); | |
2163 | module_exit(efx_exit_module); | |
2164 | ||
2165 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2166 | "Solarflare Communications"); | |
2167 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2168 | MODULE_LICENSE("GPL"); | |
2169 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |