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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
8ceee660 | 24 | #include "net_driver.h" |
8ceee660 BH |
25 | #include "efx.h" |
26 | #include "mdio_10g.h" | |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
71 | /* Interrupt mode names (see INT_MODE())) */ | |
72 | const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX; | |
73 | const char *efx_interrupt_mode_names[] = { | |
74 | [EFX_INT_MODE_MSIX] = "MSI-X", | |
75 | [EFX_INT_MODE_MSI] = "MSI", | |
76 | [EFX_INT_MODE_LEGACY] = "legacy", | |
77 | }; | |
78 | ||
79 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; | |
80 | const char *efx_reset_type_names[] = { | |
81 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
82 | [RESET_TYPE_ALL] = "ALL", | |
83 | [RESET_TYPE_WORLD] = "WORLD", | |
84 | [RESET_TYPE_DISABLE] = "DISABLE", | |
85 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
86 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
87 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
88 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
89 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
90 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 91 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
92 | }; |
93 | ||
8ceee660 BH |
94 | #define EFX_MAX_MTU (9 * 1024) |
95 | ||
1ab00629 SH |
96 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
97 | * queued onto this work queue. This is not a per-nic work queue, because | |
98 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
99 | */ | |
100 | static struct workqueue_struct *reset_workqueue; | |
101 | ||
8ceee660 BH |
102 | /************************************************************************** |
103 | * | |
104 | * Configurable values | |
105 | * | |
106 | *************************************************************************/ | |
107 | ||
8ceee660 BH |
108 | /* |
109 | * Use separate channels for TX and RX events | |
110 | * | |
28b581ab NT |
111 | * Set this to 1 to use separate channels for TX and RX. It allows us |
112 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 113 | * |
28b581ab | 114 | * This is only used in MSI-X interrupt mode |
8ceee660 | 115 | */ |
28b581ab NT |
116 | static unsigned int separate_tx_channels; |
117 | module_param(separate_tx_channels, uint, 0644); | |
118 | MODULE_PARM_DESC(separate_tx_channels, | |
119 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
120 | |
121 | /* This is the weight assigned to each of the (per-channel) virtual | |
122 | * NAPI devices. | |
123 | */ | |
124 | static int napi_weight = 64; | |
125 | ||
126 | /* This is the time (in jiffies) between invocations of the hardware | |
127 | * monitor, which checks for known hardware bugs and resets the | |
128 | * hardware and driver as necessary. | |
129 | */ | |
130 | unsigned int efx_monitor_interval = 1 * HZ; | |
131 | ||
8ceee660 BH |
132 | /* This controls whether or not the driver will initialise devices |
133 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
134 | * such devices will be initialised with a random locally-generated | |
135 | * MAC address. This allows for loading the sfc_mtd driver to | |
136 | * reprogram the flash, even if the flash contents (including the MAC | |
137 | * address) have previously been erased. | |
138 | */ | |
139 | static unsigned int allow_bad_hwaddr; | |
140 | ||
141 | /* Initial interrupt moderation settings. They can be modified after | |
142 | * module load with ethtool. | |
143 | * | |
144 | * The default for RX should strike a balance between increasing the | |
145 | * round-trip latency and reducing overhead. | |
146 | */ | |
147 | static unsigned int rx_irq_mod_usec = 60; | |
148 | ||
149 | /* Initial interrupt moderation settings. They can be modified after | |
150 | * module load with ethtool. | |
151 | * | |
152 | * This default is chosen to ensure that a 10G link does not go idle | |
153 | * while a TX queue is stopped after it has become full. A queue is | |
154 | * restarted when it drops below half full. The time this takes (assuming | |
155 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
156 | * 512 / 3 * 1.2 = 205 usec. | |
157 | */ | |
158 | static unsigned int tx_irq_mod_usec = 150; | |
159 | ||
160 | /* This is the first interrupt mode to try out of: | |
161 | * 0 => MSI-X | |
162 | * 1 => MSI | |
163 | * 2 => legacy | |
164 | */ | |
165 | static unsigned int interrupt_mode; | |
166 | ||
167 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
168 | * i.e. the number of CPUs among which we may distribute simultaneous | |
169 | * interrupt handling. | |
170 | * | |
171 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
172 | * The default (0) means to assign an interrupt to each package (level II cache) | |
173 | */ | |
174 | static unsigned int rss_cpus; | |
175 | module_param(rss_cpus, uint, 0444); | |
176 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
177 | ||
84ae48fe BH |
178 | static int phy_flash_cfg; |
179 | module_param(phy_flash_cfg, int, 0644); | |
180 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
181 | ||
6fb70fd1 BH |
182 | static unsigned irq_adapt_low_thresh = 10000; |
183 | module_param(irq_adapt_low_thresh, uint, 0644); | |
184 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
185 | "Threshold score for reducing IRQ moderation"); | |
186 | ||
187 | static unsigned irq_adapt_high_thresh = 20000; | |
188 | module_param(irq_adapt_high_thresh, uint, 0644); | |
189 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
190 | "Threshold score for increasing IRQ moderation"); | |
191 | ||
8ceee660 BH |
192 | /************************************************************************** |
193 | * | |
194 | * Utility functions and prototypes | |
195 | * | |
196 | *************************************************************************/ | |
197 | static void efx_remove_channel(struct efx_channel *channel); | |
198 | static void efx_remove_port(struct efx_nic *efx); | |
199 | static void efx_fini_napi(struct efx_nic *efx); | |
200 | static void efx_fini_channels(struct efx_nic *efx); | |
201 | ||
202 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
203 | do { \ | |
332c1ce9 BH |
204 | if ((efx->state == STATE_RUNNING) || \ |
205 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
206 | ASSERT_RTNL(); \ |
207 | } while (0) | |
208 | ||
209 | /************************************************************************** | |
210 | * | |
211 | * Event queue processing | |
212 | * | |
213 | *************************************************************************/ | |
214 | ||
215 | /* Process channel's event queue | |
216 | * | |
217 | * This function is responsible for processing the event queue of a | |
218 | * single channel. The caller must guarantee that this function will | |
219 | * never be concurrently called more than once on the same channel, | |
220 | * though different channels may be being processed concurrently. | |
221 | */ | |
fa236e18 | 222 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 223 | { |
42cbe2d7 | 224 | struct efx_nic *efx = channel->efx; |
fa236e18 | 225 | int spent; |
8ceee660 | 226 | |
42cbe2d7 | 227 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 228 | !channel->enabled)) |
42cbe2d7 | 229 | return 0; |
8ceee660 | 230 | |
fa236e18 BH |
231 | spent = efx_nic_process_eventq(channel, budget); |
232 | if (spent == 0) | |
42cbe2d7 | 233 | return 0; |
8ceee660 BH |
234 | |
235 | /* Deliver last RX packet. */ | |
236 | if (channel->rx_pkt) { | |
237 | __efx_rx_packet(channel, channel->rx_pkt, | |
238 | channel->rx_pkt_csummed); | |
239 | channel->rx_pkt = NULL; | |
240 | } | |
241 | ||
8ceee660 BH |
242 | efx_rx_strategy(channel); |
243 | ||
42cbe2d7 | 244 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 245 | |
fa236e18 | 246 | return spent; |
8ceee660 BH |
247 | } |
248 | ||
249 | /* Mark channel as finished processing | |
250 | * | |
251 | * Note that since we will not receive further interrupts for this | |
252 | * channel before we finish processing and call the eventq_read_ack() | |
253 | * method, there is no need to use the interrupt hold-off timers. | |
254 | */ | |
255 | static inline void efx_channel_processed(struct efx_channel *channel) | |
256 | { | |
5b9e207c BH |
257 | /* The interrupt handler for this channel may set work_pending |
258 | * as soon as we acknowledge the events we've seen. Make sure | |
259 | * it's cleared before then. */ | |
dc8cfa55 | 260 | channel->work_pending = false; |
5b9e207c BH |
261 | smp_wmb(); |
262 | ||
152b6a62 | 263 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
264 | } |
265 | ||
266 | /* NAPI poll handler | |
267 | * | |
268 | * NAPI guarantees serialisation of polls of the same device, which | |
269 | * provides the guarantee required by efx_process_channel(). | |
270 | */ | |
271 | static int efx_poll(struct napi_struct *napi, int budget) | |
272 | { | |
273 | struct efx_channel *channel = | |
274 | container_of(napi, struct efx_channel, napi_str); | |
fa236e18 | 275 | int spent; |
8ceee660 BH |
276 | |
277 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
278 | channel->channel, raw_smp_processor_id()); | |
279 | ||
fa236e18 | 280 | spent = efx_process_channel(channel, budget); |
8ceee660 | 281 | |
fa236e18 | 282 | if (spent < budget) { |
6fb70fd1 BH |
283 | struct efx_nic *efx = channel->efx; |
284 | ||
a4900ac9 | 285 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
286 | efx->irq_rx_adaptive && |
287 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
288 | if (unlikely(channel->irq_mod_score < |
289 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
290 | if (channel->irq_moderation > 1) { |
291 | channel->irq_moderation -= 1; | |
ef2b90ee | 292 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 293 | } |
6fb70fd1 BH |
294 | } else if (unlikely(channel->irq_mod_score > |
295 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
296 | if (channel->irq_moderation < |
297 | efx->irq_rx_moderation) { | |
298 | channel->irq_moderation += 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 | 301 | } |
6fb70fd1 BH |
302 | channel->irq_count = 0; |
303 | channel->irq_mod_score = 0; | |
304 | } | |
305 | ||
8ceee660 | 306 | /* There is no race here; although napi_disable() will |
288379f0 | 307 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
308 | * since efx_channel_processed() will have no effect if |
309 | * interrupts have already been disabled. | |
310 | */ | |
288379f0 | 311 | napi_complete(napi); |
8ceee660 BH |
312 | efx_channel_processed(channel); |
313 | } | |
314 | ||
fa236e18 | 315 | return spent; |
8ceee660 BH |
316 | } |
317 | ||
318 | /* Process the eventq of the specified channel immediately on this CPU | |
319 | * | |
320 | * Disable hardware generated interrupts, wait for any existing | |
321 | * processing to finish, then directly poll (and ack ) the eventq. | |
322 | * Finally reenable NAPI and interrupts. | |
323 | * | |
324 | * Since we are touching interrupts the caller should hold the suspend lock | |
325 | */ | |
326 | void efx_process_channel_now(struct efx_channel *channel) | |
327 | { | |
328 | struct efx_nic *efx = channel->efx; | |
329 | ||
8ceee660 BH |
330 | BUG_ON(!channel->enabled); |
331 | ||
332 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 333 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
334 | if (efx->legacy_irq) |
335 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 336 | if (channel->irq) |
8ceee660 BH |
337 | synchronize_irq(channel->irq); |
338 | ||
339 | /* Wait for any NAPI processing to complete */ | |
340 | napi_disable(&channel->napi_str); | |
341 | ||
342 | /* Poll the channel */ | |
3ffeabdd | 343 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
344 | |
345 | /* Ack the eventq. This may cause an interrupt to be generated | |
346 | * when they are reenabled */ | |
347 | efx_channel_processed(channel); | |
348 | ||
349 | napi_enable(&channel->napi_str); | |
152b6a62 | 350 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
351 | } |
352 | ||
353 | /* Create event queue | |
354 | * Event queue memory allocations are done only once. If the channel | |
355 | * is reset, the memory buffer will be reused; this guards against | |
356 | * errors during channel reset and also simplifies interrupt handling. | |
357 | */ | |
358 | static int efx_probe_eventq(struct efx_channel *channel) | |
359 | { | |
360 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
361 | ||
152b6a62 | 362 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
363 | } |
364 | ||
365 | /* Prepare channel's event queue */ | |
bc3c90a2 | 366 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
367 | { |
368 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
369 | ||
370 | channel->eventq_read_ptr = 0; | |
371 | ||
152b6a62 | 372 | efx_nic_init_eventq(channel); |
8ceee660 BH |
373 | } |
374 | ||
375 | static void efx_fini_eventq(struct efx_channel *channel) | |
376 | { | |
377 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
378 | ||
152b6a62 | 379 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
380 | } |
381 | ||
382 | static void efx_remove_eventq(struct efx_channel *channel) | |
383 | { | |
384 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
385 | ||
152b6a62 | 386 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
387 | } |
388 | ||
389 | /************************************************************************** | |
390 | * | |
391 | * Channel handling | |
392 | * | |
393 | *************************************************************************/ | |
394 | ||
8ceee660 BH |
395 | static int efx_probe_channel(struct efx_channel *channel) |
396 | { | |
397 | struct efx_tx_queue *tx_queue; | |
398 | struct efx_rx_queue *rx_queue; | |
399 | int rc; | |
400 | ||
401 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
402 | ||
403 | rc = efx_probe_eventq(channel); | |
404 | if (rc) | |
405 | goto fail1; | |
406 | ||
407 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
408 | rc = efx_probe_tx_queue(tx_queue); | |
409 | if (rc) | |
410 | goto fail2; | |
411 | } | |
412 | ||
413 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
414 | rc = efx_probe_rx_queue(rx_queue); | |
415 | if (rc) | |
416 | goto fail3; | |
417 | } | |
418 | ||
419 | channel->n_rx_frm_trunc = 0; | |
420 | ||
421 | return 0; | |
422 | ||
423 | fail3: | |
424 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
425 | efx_remove_rx_queue(rx_queue); | |
426 | fail2: | |
427 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
428 | efx_remove_tx_queue(tx_queue); | |
429 | fail1: | |
430 | return rc; | |
431 | } | |
432 | ||
433 | ||
56536e9c BH |
434 | static void efx_set_channel_names(struct efx_nic *efx) |
435 | { | |
436 | struct efx_channel *channel; | |
437 | const char *type = ""; | |
438 | int number; | |
439 | ||
440 | efx_for_each_channel(channel, efx) { | |
441 | number = channel->channel; | |
a4900ac9 BH |
442 | if (efx->n_channels > efx->n_rx_channels) { |
443 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
444 | type = "-rx"; |
445 | } else { | |
446 | type = "-tx"; | |
a4900ac9 | 447 | number -= efx->n_rx_channels; |
56536e9c BH |
448 | } |
449 | } | |
450 | snprintf(channel->name, sizeof(channel->name), | |
451 | "%s%s-%d", efx->name, type, number); | |
452 | } | |
453 | } | |
454 | ||
8ceee660 BH |
455 | /* Channels are shutdown and reinitialised whilst the NIC is running |
456 | * to propagate configuration changes (mtu, checksum offload), or | |
457 | * to clear hardware error conditions | |
458 | */ | |
bc3c90a2 | 459 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
460 | { |
461 | struct efx_tx_queue *tx_queue; | |
462 | struct efx_rx_queue *rx_queue; | |
463 | struct efx_channel *channel; | |
8ceee660 | 464 | |
f7f13b0b BH |
465 | /* Calculate the rx buffer allocation parameters required to |
466 | * support the current MTU, including padding for header | |
467 | * alignment and overruns. | |
468 | */ | |
469 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
470 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
471 | efx->type->rx_buffer_padding); | |
62b330ba SH |
472 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
473 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
474 | |
475 | /* Initialise the channels */ | |
476 | efx_for_each_channel(channel, efx) { | |
477 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
478 | ||
bc3c90a2 | 479 | efx_init_eventq(channel); |
8ceee660 | 480 | |
bc3c90a2 BH |
481 | efx_for_each_channel_tx_queue(tx_queue, channel) |
482 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
483 | |
484 | /* The rx buffer allocation strategy is MTU dependent */ | |
485 | efx_rx_strategy(channel); | |
486 | ||
bc3c90a2 BH |
487 | efx_for_each_channel_rx_queue(rx_queue, channel) |
488 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
489 | |
490 | WARN_ON(channel->rx_pkt != NULL); | |
491 | efx_rx_strategy(channel); | |
492 | } | |
8ceee660 BH |
493 | } |
494 | ||
495 | /* This enables event queue processing and packet transmission. | |
496 | * | |
497 | * Note that this function is not allowed to fail, since that would | |
498 | * introduce too much complexity into the suspend/resume path. | |
499 | */ | |
500 | static void efx_start_channel(struct efx_channel *channel) | |
501 | { | |
502 | struct efx_rx_queue *rx_queue; | |
503 | ||
504 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
505 | ||
5b9e207c BH |
506 | /* The interrupt handler for this channel may set work_pending |
507 | * as soon as we enable it. Make sure it's cleared before | |
508 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
509 | channel->work_pending = false; |
510 | channel->enabled = true; | |
5b9e207c | 511 | smp_wmb(); |
8ceee660 | 512 | |
90d683af | 513 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
514 | efx_for_each_channel_rx_queue(rx_queue, channel) |
515 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
516 | |
517 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
518 | } |
519 | ||
520 | /* This disables event queue processing and packet transmission. | |
521 | * This function does not guarantee that all queue processing | |
522 | * (e.g. RX refill) is complete. | |
523 | */ | |
524 | static void efx_stop_channel(struct efx_channel *channel) | |
525 | { | |
8ceee660 BH |
526 | if (!channel->enabled) |
527 | return; | |
528 | ||
529 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
530 | ||
dc8cfa55 | 531 | channel->enabled = false; |
8ceee660 | 532 | napi_disable(&channel->napi_str); |
8ceee660 BH |
533 | } |
534 | ||
535 | static void efx_fini_channels(struct efx_nic *efx) | |
536 | { | |
537 | struct efx_channel *channel; | |
538 | struct efx_tx_queue *tx_queue; | |
539 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 540 | int rc; |
8ceee660 BH |
541 | |
542 | EFX_ASSERT_RESET_SERIALISED(efx); | |
543 | BUG_ON(efx->port_enabled); | |
544 | ||
152b6a62 | 545 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
546 | if (rc && EFX_WORKAROUND_7803(efx)) { |
547 | /* Schedule a reset to recover from the flush failure. The | |
548 | * descriptor caches reference memory we're about to free, | |
549 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
550 | * the MACs because of the pending reset. */ | |
551 | EFX_ERR(efx, "Resetting to recover from flush failure\n"); | |
552 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
553 | } else if (rc) { | |
6bc5d3a9 | 554 | EFX_ERR(efx, "failed to flush queues\n"); |
fd371e32 | 555 | } else { |
6bc5d3a9 | 556 | EFX_LOG(efx, "successfully flushed all queues\n"); |
fd371e32 | 557 | } |
6bc5d3a9 | 558 | |
8ceee660 BH |
559 | efx_for_each_channel(channel, efx) { |
560 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
561 | ||
562 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
563 | efx_fini_rx_queue(rx_queue); | |
564 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
565 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
566 | efx_fini_eventq(channel); |
567 | } | |
568 | } | |
569 | ||
570 | static void efx_remove_channel(struct efx_channel *channel) | |
571 | { | |
572 | struct efx_tx_queue *tx_queue; | |
573 | struct efx_rx_queue *rx_queue; | |
574 | ||
575 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
576 | ||
577 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
578 | efx_remove_rx_queue(rx_queue); | |
579 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
580 | efx_remove_tx_queue(tx_queue); | |
581 | efx_remove_eventq(channel); | |
8ceee660 BH |
582 | } |
583 | ||
90d683af | 584 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 585 | { |
90d683af | 586 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
587 | } |
588 | ||
589 | /************************************************************************** | |
590 | * | |
591 | * Port handling | |
592 | * | |
593 | **************************************************************************/ | |
594 | ||
595 | /* This ensures that the kernel is kept informed (via | |
596 | * netif_carrier_on/off) of the link status, and also maintains the | |
597 | * link status's stop on the port's TX queue. | |
598 | */ | |
fdaa9aed | 599 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 600 | { |
eb50c0d6 BH |
601 | struct efx_link_state *link_state = &efx->link_state; |
602 | ||
8ceee660 BH |
603 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
604 | * that no events are triggered between unregister_netdev() and the | |
605 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
606 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
607 | if (!netif_running(efx->net_dev)) | |
608 | return; | |
609 | ||
8c8661e4 BH |
610 | if (efx->port_inhibited) { |
611 | netif_carrier_off(efx->net_dev); | |
612 | return; | |
613 | } | |
614 | ||
eb50c0d6 | 615 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
616 | efx->n_link_state_changes++; |
617 | ||
eb50c0d6 | 618 | if (link_state->up) |
8ceee660 BH |
619 | netif_carrier_on(efx->net_dev); |
620 | else | |
621 | netif_carrier_off(efx->net_dev); | |
622 | } | |
623 | ||
624 | /* Status message for kernel log */ | |
eb50c0d6 | 625 | if (link_state->up) { |
f31a45d2 | 626 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
eb50c0d6 | 627 | link_state->speed, link_state->fd ? "full" : "half", |
8ceee660 BH |
628 | efx->net_dev->mtu, |
629 | (efx->promiscuous ? " [PROMISC]" : "")); | |
630 | } else { | |
631 | EFX_INFO(efx, "link down\n"); | |
632 | } | |
633 | ||
634 | } | |
635 | ||
d3245b28 BH |
636 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
637 | { | |
638 | efx->link_advertising = advertising; | |
639 | if (advertising) { | |
640 | if (advertising & ADVERTISED_Pause) | |
641 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
642 | else | |
643 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
644 | if (advertising & ADVERTISED_Asym_Pause) | |
645 | efx->wanted_fc ^= EFX_FC_TX; | |
646 | } | |
647 | } | |
648 | ||
649 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
650 | { | |
651 | efx->wanted_fc = wanted_fc; | |
652 | if (efx->link_advertising) { | |
653 | if (wanted_fc & EFX_FC_RX) | |
654 | efx->link_advertising |= (ADVERTISED_Pause | | |
655 | ADVERTISED_Asym_Pause); | |
656 | else | |
657 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
658 | ADVERTISED_Asym_Pause); | |
659 | if (wanted_fc & EFX_FC_TX) | |
660 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
661 | } | |
662 | } | |
663 | ||
115122af BH |
664 | static void efx_fini_port(struct efx_nic *efx); |
665 | ||
d3245b28 BH |
666 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
667 | * the MAC appropriately. All other PHY configuration changes are pushed | |
668 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
669 | * through efx_monitor(). | |
670 | * | |
671 | * Callers must hold the mac_lock | |
672 | */ | |
673 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 674 | { |
d3245b28 BH |
675 | enum efx_phy_mode phy_mode; |
676 | int rc; | |
8ceee660 | 677 | |
d3245b28 | 678 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 679 | |
a816f75a BH |
680 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
681 | if (efx_dev_registered(efx)) { | |
682 | netif_addr_lock_bh(efx->net_dev); | |
683 | netif_addr_unlock_bh(efx->net_dev); | |
684 | } | |
685 | ||
d3245b28 BH |
686 | /* Disable PHY transmit in mac level loopbacks */ |
687 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
688 | if (LOOPBACK_INTERNAL(efx)) |
689 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
690 | else | |
691 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 692 | |
d3245b28 | 693 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 694 | |
d3245b28 BH |
695 | if (rc) |
696 | efx->phy_mode = phy_mode; | |
177dfcd8 | 697 | |
d3245b28 | 698 | return rc; |
8ceee660 BH |
699 | } |
700 | ||
701 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
702 | * disabled. */ | |
d3245b28 | 703 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 704 | { |
d3245b28 BH |
705 | int rc; |
706 | ||
8ceee660 BH |
707 | EFX_ASSERT_RESET_SERIALISED(efx); |
708 | ||
709 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 710 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 711 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
712 | |
713 | return rc; | |
8ceee660 BH |
714 | } |
715 | ||
8be4f3e6 BH |
716 | /* Asynchronous work item for changing MAC promiscuity and multicast |
717 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
718 | * MAC directly. */ | |
766ca0fa BH |
719 | static void efx_mac_work(struct work_struct *data) |
720 | { | |
721 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
722 | ||
723 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 724 | if (efx->port_enabled) { |
ef2b90ee | 725 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
726 | efx->mac_op->reconfigure(efx); |
727 | } | |
766ca0fa BH |
728 | mutex_unlock(&efx->mac_lock); |
729 | } | |
730 | ||
8ceee660 BH |
731 | static int efx_probe_port(struct efx_nic *efx) |
732 | { | |
733 | int rc; | |
734 | ||
735 | EFX_LOG(efx, "create port\n"); | |
736 | ||
ff3b00a0 SH |
737 | if (phy_flash_cfg) |
738 | efx->phy_mode = PHY_MODE_SPECIAL; | |
739 | ||
ef2b90ee BH |
740 | /* Connect up MAC/PHY operations table */ |
741 | rc = efx->type->probe_port(efx); | |
8ceee660 BH |
742 | if (rc) |
743 | goto err; | |
744 | ||
745 | /* Sanity check MAC address */ | |
746 | if (is_valid_ether_addr(efx->mac_address)) { | |
747 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
748 | } else { | |
e174961c JB |
749 | EFX_ERR(efx, "invalid MAC address %pM\n", |
750 | efx->mac_address); | |
8ceee660 BH |
751 | if (!allow_bad_hwaddr) { |
752 | rc = -EINVAL; | |
753 | goto err; | |
754 | } | |
755 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
756 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
757 | efx->net_dev->dev_addr); | |
8ceee660 BH |
758 | } |
759 | ||
760 | return 0; | |
761 | ||
762 | err: | |
763 | efx_remove_port(efx); | |
764 | return rc; | |
765 | } | |
766 | ||
767 | static int efx_init_port(struct efx_nic *efx) | |
768 | { | |
769 | int rc; | |
770 | ||
771 | EFX_LOG(efx, "init port\n"); | |
772 | ||
1dfc5cea BH |
773 | mutex_lock(&efx->mac_lock); |
774 | ||
177dfcd8 | 775 | rc = efx->phy_op->init(efx); |
8ceee660 | 776 | if (rc) |
1dfc5cea | 777 | goto fail1; |
8ceee660 | 778 | |
dc8cfa55 | 779 | efx->port_initialized = true; |
1dfc5cea | 780 | |
d3245b28 BH |
781 | /* Reconfigure the MAC before creating dma queues (required for |
782 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
783 | efx->mac_op->reconfigure(efx); | |
784 | ||
785 | /* Ensure the PHY advertises the correct flow control settings */ | |
786 | rc = efx->phy_op->reconfigure(efx); | |
787 | if (rc) | |
788 | goto fail2; | |
789 | ||
1dfc5cea | 790 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 791 | return 0; |
177dfcd8 | 792 | |
1dfc5cea | 793 | fail2: |
177dfcd8 | 794 | efx->phy_op->fini(efx); |
1dfc5cea BH |
795 | fail1: |
796 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 797 | return rc; |
8ceee660 BH |
798 | } |
799 | ||
8ceee660 BH |
800 | static void efx_start_port(struct efx_nic *efx) |
801 | { | |
802 | EFX_LOG(efx, "start port\n"); | |
803 | BUG_ON(efx->port_enabled); | |
804 | ||
805 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 806 | efx->port_enabled = true; |
8be4f3e6 BH |
807 | |
808 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
809 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 810 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
811 | efx->mac_op->reconfigure(efx); |
812 | ||
8ceee660 BH |
813 | mutex_unlock(&efx->mac_lock); |
814 | } | |
815 | ||
fdaa9aed | 816 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
817 | static void efx_stop_port(struct efx_nic *efx) |
818 | { | |
819 | EFX_LOG(efx, "stop port\n"); | |
820 | ||
821 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 822 | efx->port_enabled = false; |
8ceee660 BH |
823 | mutex_unlock(&efx->mac_lock); |
824 | ||
825 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 826 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
827 | netif_addr_lock_bh(efx->net_dev); |
828 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
829 | } |
830 | } | |
831 | ||
832 | static void efx_fini_port(struct efx_nic *efx) | |
833 | { | |
834 | EFX_LOG(efx, "shut down port\n"); | |
835 | ||
836 | if (!efx->port_initialized) | |
837 | return; | |
838 | ||
177dfcd8 | 839 | efx->phy_op->fini(efx); |
dc8cfa55 | 840 | efx->port_initialized = false; |
8ceee660 | 841 | |
eb50c0d6 | 842 | efx->link_state.up = false; |
8ceee660 BH |
843 | efx_link_status_changed(efx); |
844 | } | |
845 | ||
846 | static void efx_remove_port(struct efx_nic *efx) | |
847 | { | |
848 | EFX_LOG(efx, "destroying port\n"); | |
849 | ||
ef2b90ee | 850 | efx->type->remove_port(efx); |
8ceee660 BH |
851 | } |
852 | ||
853 | /************************************************************************** | |
854 | * | |
855 | * NIC handling | |
856 | * | |
857 | **************************************************************************/ | |
858 | ||
859 | /* This configures the PCI device to enable I/O and DMA. */ | |
860 | static int efx_init_io(struct efx_nic *efx) | |
861 | { | |
862 | struct pci_dev *pci_dev = efx->pci_dev; | |
863 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
864 | int rc; | |
865 | ||
866 | EFX_LOG(efx, "initialising I/O\n"); | |
867 | ||
868 | rc = pci_enable_device(pci_dev); | |
869 | if (rc) { | |
870 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
871 | goto fail1; | |
872 | } | |
873 | ||
874 | pci_set_master(pci_dev); | |
875 | ||
876 | /* Set the PCI DMA mask. Try all possibilities from our | |
877 | * genuine mask down to 32 bits, because some architectures | |
878 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
879 | * masks event though they reject 46 bit masks. | |
880 | */ | |
881 | while (dma_mask > 0x7fffffffUL) { | |
882 | if (pci_dma_supported(pci_dev, dma_mask) && | |
883 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
884 | break; | |
885 | dma_mask >>= 1; | |
886 | } | |
887 | if (rc) { | |
888 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
889 | goto fail2; | |
890 | } | |
891 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
892 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
893 | if (rc) { | |
894 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
895 | * fail with a mask that pci_set_dma_mask() accepted, | |
896 | * but just in case... | |
897 | */ | |
898 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
899 | goto fail2; | |
900 | } | |
901 | ||
dc803df8 BH |
902 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
903 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 BH |
904 | if (rc) { |
905 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
906 | rc = -EIO; | |
907 | goto fail3; | |
908 | } | |
909 | efx->membase = ioremap_nocache(efx->membase_phys, | |
910 | efx->type->mem_map_size); | |
911 | if (!efx->membase) { | |
dc803df8 | 912 | EFX_ERR(efx, "could not map memory BAR at %llx+%x\n", |
086ea356 | 913 | (unsigned long long)efx->membase_phys, |
8ceee660 BH |
914 | efx->type->mem_map_size); |
915 | rc = -ENOMEM; | |
916 | goto fail4; | |
917 | } | |
dc803df8 BH |
918 | EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n", |
919 | (unsigned long long)efx->membase_phys, | |
086ea356 | 920 | efx->type->mem_map_size, efx->membase); |
8ceee660 BH |
921 | |
922 | return 0; | |
923 | ||
924 | fail4: | |
dc803df8 | 925 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 926 | fail3: |
2c118e0f | 927 | efx->membase_phys = 0; |
8ceee660 BH |
928 | fail2: |
929 | pci_disable_device(efx->pci_dev); | |
930 | fail1: | |
931 | return rc; | |
932 | } | |
933 | ||
934 | static void efx_fini_io(struct efx_nic *efx) | |
935 | { | |
936 | EFX_LOG(efx, "shutting down I/O\n"); | |
937 | ||
938 | if (efx->membase) { | |
939 | iounmap(efx->membase); | |
940 | efx->membase = NULL; | |
941 | } | |
942 | ||
943 | if (efx->membase_phys) { | |
dc803df8 | 944 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 945 | efx->membase_phys = 0; |
8ceee660 BH |
946 | } |
947 | ||
948 | pci_disable_device(efx->pci_dev); | |
949 | } | |
950 | ||
a4900ac9 BH |
951 | /* Get number of channels wanted. Each channel will have its own IRQ, |
952 | * 1 RX queue and/or 2 TX queues. */ | |
953 | static int efx_wanted_channels(void) | |
46123d04 | 954 | { |
2f8975fb | 955 | cpumask_var_t core_mask; |
46123d04 BH |
956 | int count; |
957 | int cpu; | |
958 | ||
79f55997 | 959 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 960 | printk(KERN_WARNING |
3977d033 | 961 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
962 | return 1; |
963 | } | |
964 | ||
46123d04 BH |
965 | count = 0; |
966 | for_each_online_cpu(cpu) { | |
2f8975fb | 967 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 968 | ++count; |
2f8975fb | 969 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 970 | topology_core_cpumask(cpu)); |
46123d04 BH |
971 | } |
972 | } | |
973 | ||
2f8975fb | 974 | free_cpumask_var(core_mask); |
46123d04 BH |
975 | return count; |
976 | } | |
977 | ||
978 | /* Probe the number and type of interrupts we are able to obtain, and | |
979 | * the resulting numbers of channels and RX queues. | |
980 | */ | |
8ceee660 BH |
981 | static void efx_probe_interrupts(struct efx_nic *efx) |
982 | { | |
46123d04 BH |
983 | int max_channels = |
984 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
985 | int rc, i; |
986 | ||
987 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 988 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 989 | int n_channels; |
aa6ef27e | 990 | |
a4900ac9 BH |
991 | n_channels = efx_wanted_channels(); |
992 | if (separate_tx_channels) | |
993 | n_channels *= 2; | |
994 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 995 | |
a4900ac9 | 996 | for (i = 0; i < n_channels; i++) |
8ceee660 | 997 | xentries[i].entry = i; |
a4900ac9 | 998 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 999 | if (rc > 0) { |
28b581ab | 1000 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
a4900ac9 | 1001 | " available (%d < %d).\n", rc, n_channels); |
28b581ab | 1002 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); |
a4900ac9 BH |
1003 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1004 | n_channels = rc; | |
8ceee660 | 1005 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1006 | n_channels); |
8ceee660 BH |
1007 | } |
1008 | ||
1009 | if (rc == 0) { | |
a4900ac9 BH |
1010 | efx->n_channels = n_channels; |
1011 | if (separate_tx_channels) { | |
1012 | efx->n_tx_channels = | |
1013 | max(efx->n_channels / 2, 1U); | |
1014 | efx->n_rx_channels = | |
1015 | max(efx->n_channels - | |
1016 | efx->n_tx_channels, 1U); | |
1017 | } else { | |
1018 | efx->n_tx_channels = efx->n_channels; | |
1019 | efx->n_rx_channels = efx->n_channels; | |
1020 | } | |
1021 | for (i = 0; i < n_channels; i++) | |
8ceee660 | 1022 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
1023 | } else { |
1024 | /* Fall back to single channel MSI */ | |
1025 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1026 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | /* Try single interrupt MSI */ | |
1031 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1032 | efx->n_channels = 1; |
a4900ac9 BH |
1033 | efx->n_rx_channels = 1; |
1034 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1035 | rc = pci_enable_msi(efx->pci_dev); |
1036 | if (rc == 0) { | |
1037 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
1038 | } else { |
1039 | EFX_ERR(efx, "could not enable MSI\n"); | |
1040 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | /* Assume legacy interrupts */ | |
1045 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1046 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1047 | efx->n_rx_channels = 1; |
1048 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1049 | efx->legacy_irq = efx->pci_dev->irq; |
1050 | } | |
1051 | } | |
1052 | ||
1053 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1054 | { | |
1055 | struct efx_channel *channel; | |
1056 | ||
1057 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1058 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1059 | channel->irq = 0; |
1060 | pci_disable_msi(efx->pci_dev); | |
1061 | pci_disable_msix(efx->pci_dev); | |
1062 | ||
1063 | /* Remove legacy interrupt */ | |
1064 | efx->legacy_irq = 0; | |
1065 | } | |
1066 | ||
8831da7b | 1067 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1068 | { |
a4900ac9 | 1069 | struct efx_channel *channel; |
8ceee660 BH |
1070 | struct efx_tx_queue *tx_queue; |
1071 | struct efx_rx_queue *rx_queue; | |
a4900ac9 BH |
1072 | unsigned tx_channel_offset = |
1073 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
8ceee660 | 1074 | |
a4900ac9 BH |
1075 | efx_for_each_channel(channel, efx) { |
1076 | if (channel->channel - tx_channel_offset < efx->n_tx_channels) { | |
1077 | channel->tx_queue = &efx->tx_queue[ | |
1078 | (channel->channel - tx_channel_offset) * | |
1079 | EFX_TXQ_TYPES]; | |
1080 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1081 | tx_queue->channel = channel; | |
1082 | } | |
60ac1065 | 1083 | } |
8ceee660 | 1084 | |
a4900ac9 | 1085 | efx_for_each_rx_queue(rx_queue, efx) |
8831da7b | 1086 | rx_queue->channel = &efx->channel[rx_queue->queue]; |
8ceee660 BH |
1087 | } |
1088 | ||
1089 | static int efx_probe_nic(struct efx_nic *efx) | |
1090 | { | |
1091 | int rc; | |
1092 | ||
1093 | EFX_LOG(efx, "creating NIC\n"); | |
1094 | ||
1095 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1096 | rc = efx->type->probe(efx); |
8ceee660 BH |
1097 | if (rc) |
1098 | return rc; | |
1099 | ||
a4900ac9 | 1100 | /* Determine the number of channels and queues by trying to hook |
8ceee660 BH |
1101 | * in MSI-X interrupts. */ |
1102 | efx_probe_interrupts(efx); | |
1103 | ||
8831da7b | 1104 | efx_set_channels(efx); |
a4900ac9 | 1105 | efx->net_dev->real_num_tx_queues = efx->n_tx_channels; |
8ceee660 BH |
1106 | |
1107 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1108 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1109 | |
1110 | return 0; | |
1111 | } | |
1112 | ||
1113 | static void efx_remove_nic(struct efx_nic *efx) | |
1114 | { | |
1115 | EFX_LOG(efx, "destroying NIC\n"); | |
1116 | ||
1117 | efx_remove_interrupts(efx); | |
ef2b90ee | 1118 | efx->type->remove(efx); |
8ceee660 BH |
1119 | } |
1120 | ||
1121 | /************************************************************************** | |
1122 | * | |
1123 | * NIC startup/shutdown | |
1124 | * | |
1125 | *************************************************************************/ | |
1126 | ||
1127 | static int efx_probe_all(struct efx_nic *efx) | |
1128 | { | |
1129 | struct efx_channel *channel; | |
1130 | int rc; | |
1131 | ||
1132 | /* Create NIC */ | |
1133 | rc = efx_probe_nic(efx); | |
1134 | if (rc) { | |
1135 | EFX_ERR(efx, "failed to create NIC\n"); | |
1136 | goto fail1; | |
1137 | } | |
1138 | ||
1139 | /* Create port */ | |
1140 | rc = efx_probe_port(efx); | |
1141 | if (rc) { | |
1142 | EFX_ERR(efx, "failed to create port\n"); | |
1143 | goto fail2; | |
1144 | } | |
1145 | ||
1146 | /* Create channels */ | |
1147 | efx_for_each_channel(channel, efx) { | |
1148 | rc = efx_probe_channel(channel); | |
1149 | if (rc) { | |
1150 | EFX_ERR(efx, "failed to create channel %d\n", | |
1151 | channel->channel); | |
1152 | goto fail3; | |
1153 | } | |
1154 | } | |
56536e9c | 1155 | efx_set_channel_names(efx); |
8ceee660 BH |
1156 | |
1157 | return 0; | |
1158 | ||
1159 | fail3: | |
1160 | efx_for_each_channel(channel, efx) | |
1161 | efx_remove_channel(channel); | |
1162 | efx_remove_port(efx); | |
1163 | fail2: | |
1164 | efx_remove_nic(efx); | |
1165 | fail1: | |
1166 | return rc; | |
1167 | } | |
1168 | ||
1169 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1170 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1171 | * and ensures that the port is scheduled to be reconfigured. | |
1172 | * This function is safe to call multiple times when the NIC is in any | |
1173 | * state. */ | |
1174 | static void efx_start_all(struct efx_nic *efx) | |
1175 | { | |
1176 | struct efx_channel *channel; | |
1177 | ||
1178 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1179 | ||
1180 | /* Check that it is appropriate to restart the interface. All | |
1181 | * of these flags are safe to read under just the rtnl lock */ | |
1182 | if (efx->port_enabled) | |
1183 | return; | |
1184 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1185 | return; | |
55668611 | 1186 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1187 | return; |
1188 | ||
1189 | /* Mark the port as enabled so port reconfigurations can start, then | |
1190 | * restart the transmit interface early so the watchdog timer stops */ | |
1191 | efx_start_port(efx); | |
8ceee660 | 1192 | |
a4900ac9 BH |
1193 | efx_for_each_channel(channel, efx) { |
1194 | if (efx_dev_registered(efx)) | |
1195 | efx_wake_queue(channel); | |
8ceee660 | 1196 | efx_start_channel(channel); |
a4900ac9 | 1197 | } |
8ceee660 | 1198 | |
152b6a62 | 1199 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1200 | |
8880f4ec BH |
1201 | /* Switch to event based MCDI completions after enabling interrupts. |
1202 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1203 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1204 | * reset_pending [modified from an atomic context], we instead guarantee | |
1205 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1206 | efx_mcdi_mode_event(efx); | |
1207 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1208 | efx_mcdi_mode_poll(efx); | |
1209 | ||
78c1f0a0 SH |
1210 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1211 | * event driven), we have to poll the PHY because after an event queue | |
1212 | * flush, we could have a missed a link state change */ | |
1213 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1214 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1215 | efx_monitor_interval); | |
78c1f0a0 SH |
1216 | } else { |
1217 | mutex_lock(&efx->mac_lock); | |
1218 | if (efx->phy_op->poll(efx)) | |
1219 | efx_link_status_changed(efx); | |
1220 | mutex_unlock(&efx->mac_lock); | |
1221 | } | |
55edc6e6 | 1222 | |
ef2b90ee | 1223 | efx->type->start_stats(efx); |
8ceee660 BH |
1224 | } |
1225 | ||
1226 | /* Flush all delayed work. Should only be called when no more delayed work | |
1227 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1228 | * since we're holding the rtnl_lock at this point. */ | |
1229 | static void efx_flush_all(struct efx_nic *efx) | |
1230 | { | |
8ceee660 BH |
1231 | /* Make sure the hardware monitor is stopped */ |
1232 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1233 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1234 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1235 | } |
1236 | ||
1237 | /* Quiesce hardware and software without bringing the link down. | |
1238 | * Safe to call multiple times, when the nic and interface is in any | |
1239 | * state. The caller is guaranteed to subsequently be in a position | |
1240 | * to modify any hardware and software state they see fit without | |
1241 | * taking locks. */ | |
1242 | static void efx_stop_all(struct efx_nic *efx) | |
1243 | { | |
1244 | struct efx_channel *channel; | |
1245 | ||
1246 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1247 | ||
1248 | /* port_enabled can be read safely under the rtnl lock */ | |
1249 | if (!efx->port_enabled) | |
1250 | return; | |
1251 | ||
ef2b90ee | 1252 | efx->type->stop_stats(efx); |
55edc6e6 | 1253 | |
8880f4ec BH |
1254 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1255 | efx_mcdi_mode_poll(efx); | |
1256 | ||
8ceee660 | 1257 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1258 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
1259 | if (efx->legacy_irq) |
1260 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1261 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1262 | if (channel->irq) |
1263 | synchronize_irq(channel->irq); | |
b3475645 | 1264 | } |
8ceee660 BH |
1265 | |
1266 | /* Stop all NAPI processing and synchronous rx refills */ | |
1267 | efx_for_each_channel(channel, efx) | |
1268 | efx_stop_channel(channel); | |
1269 | ||
1270 | /* Stop all asynchronous port reconfigurations. Since all | |
1271 | * event processing has already been stopped, there is no | |
1272 | * window to loose phy events */ | |
1273 | efx_stop_port(efx); | |
1274 | ||
fdaa9aed | 1275 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1276 | efx_flush_all(efx); |
1277 | ||
8ceee660 BH |
1278 | /* Stop the kernel transmit interface late, so the watchdog |
1279 | * timer isn't ticking over the flush */ | |
55668611 | 1280 | if (efx_dev_registered(efx)) { |
a4900ac9 BH |
1281 | struct efx_channel *channel; |
1282 | efx_for_each_channel(channel, efx) | |
1283 | efx_stop_queue(channel); | |
8ceee660 BH |
1284 | netif_tx_lock_bh(efx->net_dev); |
1285 | netif_tx_unlock_bh(efx->net_dev); | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | static void efx_remove_all(struct efx_nic *efx) | |
1290 | { | |
1291 | struct efx_channel *channel; | |
1292 | ||
1293 | efx_for_each_channel(channel, efx) | |
1294 | efx_remove_channel(channel); | |
1295 | efx_remove_port(efx); | |
1296 | efx_remove_nic(efx); | |
1297 | } | |
1298 | ||
8ceee660 BH |
1299 | /************************************************************************** |
1300 | * | |
1301 | * Interrupt moderation | |
1302 | * | |
1303 | **************************************************************************/ | |
1304 | ||
0d86ebd8 BH |
1305 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1306 | { | |
1307 | if (usecs <= 0) | |
1308 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1309 | if (usecs < resolution) | |
1310 | return 1; /* never round down to 0 */ | |
1311 | return usecs / resolution; | |
1312 | } | |
1313 | ||
8ceee660 | 1314 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1315 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1316 | bool rx_adaptive) | |
8ceee660 BH |
1317 | { |
1318 | struct efx_tx_queue *tx_queue; | |
1319 | struct efx_rx_queue *rx_queue; | |
152b6a62 BH |
1320 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1321 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1322 | |
1323 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1324 | ||
1325 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1326 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1327 | |
6fb70fd1 | 1328 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1329 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1330 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1331 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1332 | } |
1333 | ||
1334 | /************************************************************************** | |
1335 | * | |
1336 | * Hardware monitor | |
1337 | * | |
1338 | **************************************************************************/ | |
1339 | ||
1340 | /* Run periodically off the general workqueue. Serialised against | |
1341 | * efx_reconfigure_port via the mac_lock */ | |
1342 | static void efx_monitor(struct work_struct *data) | |
1343 | { | |
1344 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1345 | monitor_work.work); | |
8ceee660 BH |
1346 | |
1347 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1348 | raw_smp_processor_id()); | |
ef2b90ee | 1349 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1350 | |
8ceee660 BH |
1351 | /* If the mac_lock is already held then it is likely a port |
1352 | * reconfiguration is already in place, which will likely do | |
1353 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1354 | if (!mutex_trylock(&efx->mac_lock)) |
1355 | goto out_requeue; | |
1356 | if (!efx->port_enabled) | |
1357 | goto out_unlock; | |
ef2b90ee | 1358 | efx->type->monitor(efx); |
8ceee660 | 1359 | |
766ca0fa | 1360 | out_unlock: |
8ceee660 | 1361 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1362 | out_requeue: |
8ceee660 BH |
1363 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1364 | efx_monitor_interval); | |
1365 | } | |
1366 | ||
1367 | /************************************************************************** | |
1368 | * | |
1369 | * ioctls | |
1370 | * | |
1371 | *************************************************************************/ | |
1372 | ||
1373 | /* Net device ioctl | |
1374 | * Context: process, rtnl_lock() held. | |
1375 | */ | |
1376 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1377 | { | |
767e468c | 1378 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1379 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1380 | |
1381 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1382 | ||
68e7f45e BH |
1383 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1384 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1385 | (data->phy_id & 0xfc00) == 0x0400) | |
1386 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1387 | ||
1388 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1389 | } |
1390 | ||
1391 | /************************************************************************** | |
1392 | * | |
1393 | * NAPI interface | |
1394 | * | |
1395 | **************************************************************************/ | |
1396 | ||
1397 | static int efx_init_napi(struct efx_nic *efx) | |
1398 | { | |
1399 | struct efx_channel *channel; | |
8ceee660 BH |
1400 | |
1401 | efx_for_each_channel(channel, efx) { | |
1402 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1403 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1404 | efx_poll, napi_weight); | |
8ceee660 BH |
1405 | } |
1406 | return 0; | |
8ceee660 BH |
1407 | } |
1408 | ||
1409 | static void efx_fini_napi(struct efx_nic *efx) | |
1410 | { | |
1411 | struct efx_channel *channel; | |
1412 | ||
1413 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1414 | if (channel->napi_dev) |
1415 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1416 | channel->napi_dev = NULL; |
1417 | } | |
1418 | } | |
1419 | ||
1420 | /************************************************************************** | |
1421 | * | |
1422 | * Kernel netpoll interface | |
1423 | * | |
1424 | *************************************************************************/ | |
1425 | ||
1426 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1427 | ||
1428 | /* Although in the common case interrupts will be disabled, this is not | |
1429 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1430 | * so no locking is required. | |
1431 | */ | |
1432 | static void efx_netpoll(struct net_device *net_dev) | |
1433 | { | |
767e468c | 1434 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1435 | struct efx_channel *channel; |
1436 | ||
64ee3120 | 1437 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1438 | efx_schedule_channel(channel); |
1439 | } | |
1440 | ||
1441 | #endif | |
1442 | ||
1443 | /************************************************************************** | |
1444 | * | |
1445 | * Kernel net device interface | |
1446 | * | |
1447 | *************************************************************************/ | |
1448 | ||
1449 | /* Context: process, rtnl_lock() held. */ | |
1450 | static int efx_net_open(struct net_device *net_dev) | |
1451 | { | |
767e468c | 1452 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1453 | EFX_ASSERT_RESET_SERIALISED(efx); |
1454 | ||
1455 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1456 | raw_smp_processor_id()); | |
1457 | ||
f4bd954e BH |
1458 | if (efx->state == STATE_DISABLED) |
1459 | return -EIO; | |
f8b87c17 BH |
1460 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1461 | return -EBUSY; | |
8880f4ec BH |
1462 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1463 | return -EIO; | |
f8b87c17 | 1464 | |
78c1f0a0 SH |
1465 | /* Notify the kernel of the link state polled during driver load, |
1466 | * before the monitor starts running */ | |
1467 | efx_link_status_changed(efx); | |
1468 | ||
8ceee660 BH |
1469 | efx_start_all(efx); |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | /* Context: process, rtnl_lock() held. | |
1474 | * Note that the kernel will ignore our return code; this method | |
1475 | * should really be a void. | |
1476 | */ | |
1477 | static int efx_net_stop(struct net_device *net_dev) | |
1478 | { | |
767e468c | 1479 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1480 | |
1481 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1482 | raw_smp_processor_id()); | |
1483 | ||
f4bd954e BH |
1484 | if (efx->state != STATE_DISABLED) { |
1485 | /* Stop the device and flush all the channels */ | |
1486 | efx_stop_all(efx); | |
1487 | efx_fini_channels(efx); | |
1488 | efx_init_channels(efx); | |
1489 | } | |
8ceee660 BH |
1490 | |
1491 | return 0; | |
1492 | } | |
1493 | ||
5b9e207c | 1494 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1495 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1496 | { | |
767e468c | 1497 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1498 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1499 | struct net_device_stats *stats = &net_dev->stats; | |
1500 | ||
55edc6e6 | 1501 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1502 | efx->type->update_stats(efx); |
55edc6e6 | 1503 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1504 | |
1505 | stats->rx_packets = mac_stats->rx_packets; | |
1506 | stats->tx_packets = mac_stats->tx_packets; | |
1507 | stats->rx_bytes = mac_stats->rx_bytes; | |
1508 | stats->tx_bytes = mac_stats->tx_bytes; | |
1509 | stats->multicast = mac_stats->rx_multicast; | |
1510 | stats->collisions = mac_stats->tx_collision; | |
1511 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1512 | mac_stats->rx_length_error); | |
1513 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1514 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1515 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1516 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1517 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1518 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1519 | ||
1520 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1521 | stats->rx_crc_errors + |
1522 | stats->rx_frame_errors + | |
8ceee660 BH |
1523 | mac_stats->rx_symbol_error); |
1524 | stats->tx_errors = (stats->tx_window_errors + | |
1525 | mac_stats->tx_bad); | |
1526 | ||
1527 | return stats; | |
1528 | } | |
1529 | ||
1530 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1531 | static void efx_watchdog(struct net_device *net_dev) | |
1532 | { | |
767e468c | 1533 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1534 | |
a4900ac9 BH |
1535 | EFX_ERR(efx, "TX stuck with port_enabled=%d: resetting channels\n", |
1536 | efx->port_enabled); | |
8ceee660 | 1537 | |
739bb23d | 1538 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1539 | } |
1540 | ||
1541 | ||
1542 | /* Context: process, rtnl_lock() held. */ | |
1543 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1544 | { | |
767e468c | 1545 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1546 | int rc = 0; |
1547 | ||
1548 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1549 | ||
1550 | if (new_mtu > EFX_MAX_MTU) | |
1551 | return -EINVAL; | |
1552 | ||
1553 | efx_stop_all(efx); | |
1554 | ||
1555 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1556 | ||
1557 | efx_fini_channels(efx); | |
d3245b28 BH |
1558 | |
1559 | mutex_lock(&efx->mac_lock); | |
1560 | /* Reconfigure the MAC before enabling the dma queues so that | |
1561 | * the RX buffers don't overflow */ | |
8ceee660 | 1562 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1563 | efx->mac_op->reconfigure(efx); |
1564 | mutex_unlock(&efx->mac_lock); | |
1565 | ||
bc3c90a2 | 1566 | efx_init_channels(efx); |
8ceee660 BH |
1567 | |
1568 | efx_start_all(efx); | |
1569 | return rc; | |
8ceee660 BH |
1570 | } |
1571 | ||
1572 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1573 | { | |
767e468c | 1574 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1575 | struct sockaddr *addr = data; |
1576 | char *new_addr = addr->sa_data; | |
1577 | ||
1578 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1579 | ||
1580 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1581 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1582 | new_addr); | |
8ceee660 BH |
1583 | return -EINVAL; |
1584 | } | |
1585 | ||
1586 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1587 | ||
1588 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1589 | mutex_lock(&efx->mac_lock); |
1590 | efx->mac_op->reconfigure(efx); | |
1591 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1592 | |
1593 | return 0; | |
1594 | } | |
1595 | ||
a816f75a | 1596 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1597 | static void efx_set_multicast_list(struct net_device *net_dev) |
1598 | { | |
767e468c | 1599 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1600 | struct netdev_hw_addr *ha; |
8ceee660 | 1601 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1602 | u32 crc; |
1603 | int bit; | |
8ceee660 | 1604 | |
8be4f3e6 | 1605 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1606 | |
1607 | /* Build multicast hash table */ | |
8be4f3e6 | 1608 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1609 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1610 | } else { | |
1611 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1612 | netdev_for_each_mc_addr(ha, net_dev) { |
1613 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1614 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1615 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1616 | } |
8ceee660 | 1617 | |
8be4f3e6 BH |
1618 | /* Broadcast packets go through the multicast hash filter. |
1619 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1620 | * so we always add bit 0xff to the mask. | |
1621 | */ | |
1622 | set_bit_le(0xff, mc_hash->byte); | |
1623 | } | |
a816f75a | 1624 | |
8be4f3e6 BH |
1625 | if (efx->port_enabled) |
1626 | queue_work(efx->workqueue, &efx->mac_work); | |
1627 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1628 | } |
1629 | ||
c3ecb9f3 SH |
1630 | static const struct net_device_ops efx_netdev_ops = { |
1631 | .ndo_open = efx_net_open, | |
1632 | .ndo_stop = efx_net_stop, | |
1633 | .ndo_get_stats = efx_net_stats, | |
1634 | .ndo_tx_timeout = efx_watchdog, | |
1635 | .ndo_start_xmit = efx_hard_start_xmit, | |
1636 | .ndo_validate_addr = eth_validate_addr, | |
1637 | .ndo_do_ioctl = efx_ioctl, | |
1638 | .ndo_change_mtu = efx_change_mtu, | |
1639 | .ndo_set_mac_address = efx_set_mac_address, | |
1640 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1641 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1642 | .ndo_poll_controller = efx_netpoll, | |
1643 | #endif | |
1644 | }; | |
1645 | ||
7dde596e BH |
1646 | static void efx_update_name(struct efx_nic *efx) |
1647 | { | |
1648 | strcpy(efx->name, efx->net_dev->name); | |
1649 | efx_mtd_rename(efx); | |
1650 | efx_set_channel_names(efx); | |
1651 | } | |
1652 | ||
8ceee660 BH |
1653 | static int efx_netdev_event(struct notifier_block *this, |
1654 | unsigned long event, void *ptr) | |
1655 | { | |
d3208b5e | 1656 | struct net_device *net_dev = ptr; |
8ceee660 | 1657 | |
7dde596e BH |
1658 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1659 | event == NETDEV_CHANGENAME) | |
1660 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1661 | |
1662 | return NOTIFY_DONE; | |
1663 | } | |
1664 | ||
1665 | static struct notifier_block efx_netdev_notifier = { | |
1666 | .notifier_call = efx_netdev_event, | |
1667 | }; | |
1668 | ||
06d5e193 BH |
1669 | static ssize_t |
1670 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1671 | { | |
1672 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1673 | return sprintf(buf, "%d\n", efx->phy_type); | |
1674 | } | |
1675 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1676 | ||
8ceee660 BH |
1677 | static int efx_register_netdev(struct efx_nic *efx) |
1678 | { | |
1679 | struct net_device *net_dev = efx->net_dev; | |
1680 | int rc; | |
1681 | ||
1682 | net_dev->watchdog_timeo = 5 * HZ; | |
1683 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1684 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1685 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1686 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1687 | ||
8ceee660 | 1688 | /* Clear MAC statistics */ |
177dfcd8 | 1689 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1690 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1691 | ||
7dde596e | 1692 | rtnl_lock(); |
aed0628d BH |
1693 | |
1694 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1695 | if (rc < 0) | |
1696 | goto fail_locked; | |
7dde596e | 1697 | efx_update_name(efx); |
aed0628d BH |
1698 | |
1699 | rc = register_netdevice(net_dev); | |
1700 | if (rc) | |
1701 | goto fail_locked; | |
1702 | ||
1703 | /* Always start with carrier off; PHY events will detect the link */ | |
1704 | netif_carrier_off(efx->net_dev); | |
1705 | ||
7dde596e | 1706 | rtnl_unlock(); |
8ceee660 | 1707 | |
06d5e193 BH |
1708 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1709 | if (rc) { | |
1710 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1711 | goto fail_registered; | |
1712 | } | |
1713 | ||
8ceee660 | 1714 | return 0; |
06d5e193 | 1715 | |
aed0628d BH |
1716 | fail_locked: |
1717 | rtnl_unlock(); | |
1718 | EFX_ERR(efx, "could not register net dev\n"); | |
1719 | return rc; | |
1720 | ||
06d5e193 BH |
1721 | fail_registered: |
1722 | unregister_netdev(net_dev); | |
1723 | return rc; | |
8ceee660 BH |
1724 | } |
1725 | ||
1726 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1727 | { | |
1728 | struct efx_tx_queue *tx_queue; | |
1729 | ||
1730 | if (!efx->net_dev) | |
1731 | return; | |
1732 | ||
767e468c | 1733 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1734 | |
1735 | /* Free up any skbs still remaining. This has to happen before | |
1736 | * we try to unregister the netdev as running their destructors | |
1737 | * may be needed to get the device ref. count to 0. */ | |
1738 | efx_for_each_tx_queue(tx_queue, efx) | |
1739 | efx_release_tx_buffers(tx_queue); | |
1740 | ||
55668611 | 1741 | if (efx_dev_registered(efx)) { |
8ceee660 | 1742 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1743 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1744 | unregister_netdev(efx->net_dev); |
1745 | } | |
1746 | } | |
1747 | ||
1748 | /************************************************************************** | |
1749 | * | |
1750 | * Device reset and suspend | |
1751 | * | |
1752 | **************************************************************************/ | |
1753 | ||
2467ca46 BH |
1754 | /* Tears down the entire software state and most of the hardware state |
1755 | * before reset. */ | |
d3245b28 | 1756 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1757 | { |
8ceee660 BH |
1758 | EFX_ASSERT_RESET_SERIALISED(efx); |
1759 | ||
2467ca46 BH |
1760 | efx_stop_all(efx); |
1761 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1762 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1763 | |
8ceee660 | 1764 | efx_fini_channels(efx); |
4b988280 SH |
1765 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1766 | efx->phy_op->fini(efx); | |
ef2b90ee | 1767 | efx->type->fini(efx); |
8ceee660 BH |
1768 | } |
1769 | ||
2467ca46 BH |
1770 | /* This function will always ensure that the locks acquired in |
1771 | * efx_reset_down() are released. A failure return code indicates | |
1772 | * that we were unable to reinitialise the hardware, and the | |
1773 | * driver should be disabled. If ok is false, then the rx and tx | |
1774 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 1775 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
1776 | { |
1777 | int rc; | |
1778 | ||
2467ca46 | 1779 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1780 | |
ef2b90ee | 1781 | rc = efx->type->init(efx); |
8ceee660 | 1782 | if (rc) { |
2467ca46 | 1783 | EFX_ERR(efx, "failed to initialise NIC\n"); |
eb9f6744 | 1784 | goto fail; |
8ceee660 BH |
1785 | } |
1786 | ||
eb9f6744 BH |
1787 | if (!ok) |
1788 | goto fail; | |
1789 | ||
4b988280 | 1790 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
1791 | rc = efx->phy_op->init(efx); |
1792 | if (rc) | |
1793 | goto fail; | |
1794 | if (efx->phy_op->reconfigure(efx)) | |
1795 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
4b988280 SH |
1796 | } |
1797 | ||
eb9f6744 | 1798 | efx->mac_op->reconfigure(efx); |
8ceee660 | 1799 | |
eb9f6744 BH |
1800 | efx_init_channels(efx); |
1801 | ||
1802 | mutex_unlock(&efx->spi_lock); | |
1803 | mutex_unlock(&efx->mac_lock); | |
1804 | ||
1805 | efx_start_all(efx); | |
1806 | ||
1807 | return 0; | |
1808 | ||
1809 | fail: | |
1810 | efx->port_initialized = false; | |
2467ca46 | 1811 | |
f4150724 | 1812 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1813 | mutex_unlock(&efx->mac_lock); |
1814 | ||
8ceee660 BH |
1815 | return rc; |
1816 | } | |
1817 | ||
eb9f6744 BH |
1818 | /* Reset the NIC using the specified method. Note that the reset may |
1819 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 1820 | * |
eb9f6744 | 1821 | * Caller must hold the rtnl_lock. |
8ceee660 | 1822 | */ |
eb9f6744 | 1823 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1824 | { |
eb9f6744 BH |
1825 | int rc, rc2; |
1826 | bool disabled; | |
8ceee660 | 1827 | |
c459302d | 1828 | EFX_INFO(efx, "resetting (%s)\n", RESET_TYPE(method)); |
8ceee660 | 1829 | |
d3245b28 | 1830 | efx_reset_down(efx, method); |
8ceee660 | 1831 | |
ef2b90ee | 1832 | rc = efx->type->reset(efx, method); |
8ceee660 BH |
1833 | if (rc) { |
1834 | EFX_ERR(efx, "failed to reset hardware\n"); | |
eb9f6744 | 1835 | goto out; |
8ceee660 BH |
1836 | } |
1837 | ||
1838 | /* Allow resets to be rescheduled. */ | |
1839 | efx->reset_pending = RESET_TYPE_NONE; | |
1840 | ||
1841 | /* Reinitialise bus-mastering, which may have been turned off before | |
1842 | * the reset was scheduled. This is still appropriate, even in the | |
1843 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1844 | * can respond to requests. */ | |
1845 | pci_set_master(efx->pci_dev); | |
1846 | ||
eb9f6744 | 1847 | out: |
8ceee660 | 1848 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
1849 | disabled = rc || method == RESET_TYPE_DISABLE; |
1850 | rc2 = efx_reset_up(efx, method, !disabled); | |
1851 | if (rc2) { | |
1852 | disabled = true; | |
1853 | if (!rc) | |
1854 | rc = rc2; | |
8ceee660 BH |
1855 | } |
1856 | ||
eb9f6744 | 1857 | if (disabled) { |
f49a4589 | 1858 | dev_close(efx->net_dev); |
f4bd954e BH |
1859 | EFX_ERR(efx, "has been disabled\n"); |
1860 | efx->state = STATE_DISABLED; | |
f4bd954e BH |
1861 | } else { |
1862 | EFX_LOG(efx, "reset complete\n"); | |
1863 | } | |
8ceee660 BH |
1864 | return rc; |
1865 | } | |
1866 | ||
1867 | /* The worker thread exists so that code that cannot sleep can | |
1868 | * schedule a reset for later. | |
1869 | */ | |
1870 | static void efx_reset_work(struct work_struct *data) | |
1871 | { | |
eb9f6744 | 1872 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 1873 | |
319ba649 SH |
1874 | if (efx->reset_pending == RESET_TYPE_NONE) |
1875 | return; | |
1876 | ||
eb9f6744 BH |
1877 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
1878 | * flag set so that efx_pci_probe_main will be retried */ | |
1879 | if (efx->state != STATE_RUNNING) { | |
1880 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1881 | return; | |
1882 | } | |
1883 | ||
1884 | rtnl_lock(); | |
f49a4589 | 1885 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 1886 | rtnl_unlock(); |
8ceee660 BH |
1887 | } |
1888 | ||
1889 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1890 | { | |
1891 | enum reset_type method; | |
1892 | ||
1893 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1894 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1895 | return; | |
1896 | } | |
1897 | ||
1898 | switch (type) { | |
1899 | case RESET_TYPE_INVISIBLE: | |
1900 | case RESET_TYPE_ALL: | |
1901 | case RESET_TYPE_WORLD: | |
1902 | case RESET_TYPE_DISABLE: | |
1903 | method = type; | |
1904 | break; | |
1905 | case RESET_TYPE_RX_RECOVERY: | |
1906 | case RESET_TYPE_RX_DESC_FETCH: | |
1907 | case RESET_TYPE_TX_DESC_FETCH: | |
1908 | case RESET_TYPE_TX_SKIP: | |
1909 | method = RESET_TYPE_INVISIBLE; | |
1910 | break; | |
8880f4ec | 1911 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
1912 | default: |
1913 | method = RESET_TYPE_ALL; | |
1914 | break; | |
1915 | } | |
1916 | ||
1917 | if (method != type) | |
c459302d BH |
1918 | EFX_LOG(efx, "scheduling %s reset for %s\n", |
1919 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 1920 | else |
c459302d | 1921 | EFX_LOG(efx, "scheduling %s reset\n", RESET_TYPE(method)); |
8ceee660 BH |
1922 | |
1923 | efx->reset_pending = method; | |
1924 | ||
8880f4ec BH |
1925 | /* efx_process_channel() will no longer read events once a |
1926 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
1927 | efx_mcdi_mode_poll(efx); | |
1928 | ||
1ab00629 | 1929 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1930 | } |
1931 | ||
1932 | /************************************************************************** | |
1933 | * | |
1934 | * List of NICs we support | |
1935 | * | |
1936 | **************************************************************************/ | |
1937 | ||
1938 | /* PCI device ID table */ | |
a3aa1884 | 1939 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 1940 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 1941 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 1942 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 1943 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
1944 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
1945 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
1946 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
1947 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
1948 | {0} /* end of list */ |
1949 | }; | |
1950 | ||
1951 | /************************************************************************** | |
1952 | * | |
3759433d | 1953 | * Dummy PHY/MAC operations |
8ceee660 | 1954 | * |
01aad7b6 | 1955 | * Can be used for some unimplemented operations |
8ceee660 BH |
1956 | * Needed so all function pointers are valid and do not have to be tested |
1957 | * before use | |
1958 | * | |
1959 | **************************************************************************/ | |
1960 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1961 | { | |
1962 | return 0; | |
1963 | } | |
1964 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
1965 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1966 | { | |
1967 | } | |
fdaa9aed SH |
1968 | bool efx_port_dummy_op_poll(struct efx_nic *efx) |
1969 | { | |
1970 | return false; | |
1971 | } | |
8ceee660 BH |
1972 | |
1973 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1974 | .init = efx_port_dummy_op_int, | |
d3245b28 | 1975 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 1976 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 1977 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
1978 | }; |
1979 | ||
8ceee660 BH |
1980 | /************************************************************************** |
1981 | * | |
1982 | * Data housekeeping | |
1983 | * | |
1984 | **************************************************************************/ | |
1985 | ||
1986 | /* This zeroes out and then fills in the invariants in a struct | |
1987 | * efx_nic (including all sub-structures). | |
1988 | */ | |
1989 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1990 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1991 | { | |
1992 | struct efx_channel *channel; | |
1993 | struct efx_tx_queue *tx_queue; | |
1994 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1995 | int i; |
8ceee660 BH |
1996 | |
1997 | /* Initialise common structures */ | |
1998 | memset(efx, 0, sizeof(*efx)); | |
1999 | spin_lock_init(&efx->biu_lock); | |
ab867461 | 2000 | mutex_init(&efx->mdio_lock); |
f4150724 | 2001 | mutex_init(&efx->spi_lock); |
76884835 BH |
2002 | #ifdef CONFIG_SFC_MTD |
2003 | INIT_LIST_HEAD(&efx->mtd_list); | |
2004 | #endif | |
8ceee660 BH |
2005 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2006 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2007 | efx->pci_dev = pci_dev; | |
2008 | efx->state = STATE_INIT; | |
2009 | efx->reset_pending = RESET_TYPE_NONE; | |
2010 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2011 | |
2012 | efx->net_dev = net_dev; | |
dc8cfa55 | 2013 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2014 | spin_lock_init(&efx->stats_lock); |
2015 | mutex_init(&efx->mac_lock); | |
b895d73e | 2016 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2017 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2018 | efx->mdio.dev = net_dev; |
766ca0fa | 2019 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2020 | |
2021 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
2022 | channel = &efx->channel[i]; | |
2023 | channel->efx = efx; | |
2024 | channel->channel = i; | |
dc8cfa55 | 2025 | channel->work_pending = false; |
a4900ac9 BH |
2026 | spin_lock_init(&channel->tx_stop_lock); |
2027 | atomic_set(&channel->tx_stop_count, 1); | |
8ceee660 | 2028 | } |
a4900ac9 | 2029 | for (i = 0; i < EFX_MAX_TX_QUEUES; i++) { |
8ceee660 BH |
2030 | tx_queue = &efx->tx_queue[i]; |
2031 | tx_queue->efx = efx; | |
2032 | tx_queue->queue = i; | |
2033 | tx_queue->buffer = NULL; | |
2034 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 2035 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
2036 | } |
2037 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
2038 | rx_queue = &efx->rx_queue[i]; | |
2039 | rx_queue->efx = efx; | |
2040 | rx_queue->queue = i; | |
2041 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
2042 | rx_queue->buffer = NULL; | |
90d683af SH |
2043 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
2044 | (unsigned long)rx_queue); | |
8ceee660 BH |
2045 | } |
2046 | ||
2047 | efx->type = type; | |
2048 | ||
8ceee660 | 2049 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
2050 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
2051 | ||
8ceee660 BH |
2052 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2053 | ||
2054 | /* Higher numbered interrupt modes are less capable! */ | |
2055 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2056 | interrupt_mode); | |
2057 | ||
6977dc63 BH |
2058 | /* Would be good to use the net_dev name, but we're too early */ |
2059 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2060 | pci_name(pci_dev)); | |
2061 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2062 | if (!efx->workqueue) |
2063 | return -ENOMEM; | |
8d9853d9 | 2064 | |
8ceee660 | 2065 | return 0; |
8ceee660 BH |
2066 | } |
2067 | ||
2068 | static void efx_fini_struct(struct efx_nic *efx) | |
2069 | { | |
2070 | if (efx->workqueue) { | |
2071 | destroy_workqueue(efx->workqueue); | |
2072 | efx->workqueue = NULL; | |
2073 | } | |
2074 | } | |
2075 | ||
2076 | /************************************************************************** | |
2077 | * | |
2078 | * PCI interface | |
2079 | * | |
2080 | **************************************************************************/ | |
2081 | ||
2082 | /* Main body of final NIC shutdown code | |
2083 | * This is called only at module unload (or hotplug removal). | |
2084 | */ | |
2085 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2086 | { | |
152b6a62 | 2087 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2088 | efx_fini_channels(efx); |
2089 | efx_fini_port(efx); | |
ef2b90ee | 2090 | efx->type->fini(efx); |
8ceee660 BH |
2091 | efx_fini_napi(efx); |
2092 | efx_remove_all(efx); | |
2093 | } | |
2094 | ||
2095 | /* Final NIC shutdown | |
2096 | * This is called only at module unload (or hotplug removal). | |
2097 | */ | |
2098 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2099 | { | |
2100 | struct efx_nic *efx; | |
2101 | ||
2102 | efx = pci_get_drvdata(pci_dev); | |
2103 | if (!efx) | |
2104 | return; | |
2105 | ||
2106 | /* Mark the NIC as fini, then stop the interface */ | |
2107 | rtnl_lock(); | |
2108 | efx->state = STATE_FINI; | |
2109 | dev_close(efx->net_dev); | |
2110 | ||
2111 | /* Allow any queued efx_resets() to complete */ | |
2112 | rtnl_unlock(); | |
2113 | ||
8ceee660 BH |
2114 | efx_unregister_netdev(efx); |
2115 | ||
7dde596e BH |
2116 | efx_mtd_remove(efx); |
2117 | ||
8ceee660 BH |
2118 | /* Wait for any scheduled resets to complete. No more will be |
2119 | * scheduled from this point because efx_stop_all() has been | |
2120 | * called, we are no longer registered with driverlink, and | |
2121 | * the net_device's have been removed. */ | |
1ab00629 | 2122 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2123 | |
2124 | efx_pci_remove_main(efx); | |
2125 | ||
8ceee660 BH |
2126 | efx_fini_io(efx); |
2127 | EFX_LOG(efx, "shutdown successful\n"); | |
2128 | ||
2129 | pci_set_drvdata(pci_dev, NULL); | |
2130 | efx_fini_struct(efx); | |
2131 | free_netdev(efx->net_dev); | |
2132 | }; | |
2133 | ||
2134 | /* Main body of NIC initialisation | |
2135 | * This is called at module load (or hotplug insertion, theoretically). | |
2136 | */ | |
2137 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2138 | { | |
2139 | int rc; | |
2140 | ||
2141 | /* Do start-of-day initialisation */ | |
2142 | rc = efx_probe_all(efx); | |
2143 | if (rc) | |
2144 | goto fail1; | |
2145 | ||
2146 | rc = efx_init_napi(efx); | |
2147 | if (rc) | |
2148 | goto fail2; | |
2149 | ||
ef2b90ee | 2150 | rc = efx->type->init(efx); |
8ceee660 BH |
2151 | if (rc) { |
2152 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
278c0621 | 2153 | goto fail3; |
8ceee660 BH |
2154 | } |
2155 | ||
2156 | rc = efx_init_port(efx); | |
2157 | if (rc) { | |
2158 | EFX_ERR(efx, "failed to initialise port\n"); | |
278c0621 | 2159 | goto fail4; |
8ceee660 BH |
2160 | } |
2161 | ||
bc3c90a2 | 2162 | efx_init_channels(efx); |
8ceee660 | 2163 | |
152b6a62 | 2164 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2165 | if (rc) |
278c0621 | 2166 | goto fail5; |
8ceee660 BH |
2167 | |
2168 | return 0; | |
2169 | ||
278c0621 | 2170 | fail5: |
bc3c90a2 | 2171 | efx_fini_channels(efx); |
8ceee660 | 2172 | efx_fini_port(efx); |
8ceee660 | 2173 | fail4: |
ef2b90ee | 2174 | efx->type->fini(efx); |
8ceee660 BH |
2175 | fail3: |
2176 | efx_fini_napi(efx); | |
2177 | fail2: | |
2178 | efx_remove_all(efx); | |
2179 | fail1: | |
2180 | return rc; | |
2181 | } | |
2182 | ||
2183 | /* NIC initialisation | |
2184 | * | |
2185 | * This is called at module load (or hotplug insertion, | |
2186 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2187 | * sets up and registers the network devices with the kernel and hooks | |
2188 | * the interrupt service routine. It does not prepare the device for | |
2189 | * transmission; this is left to the first time one of the network | |
2190 | * interfaces is brought up (i.e. efx_net_open). | |
2191 | */ | |
2192 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2193 | const struct pci_device_id *entry) | |
2194 | { | |
2195 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2196 | struct net_device *net_dev; | |
2197 | struct efx_nic *efx; | |
2198 | int i, rc; | |
2199 | ||
2200 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
a4900ac9 | 2201 | net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES); |
8ceee660 BH |
2202 | if (!net_dev) |
2203 | return -ENOMEM; | |
c383b537 | 2204 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2205 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2206 | NETIF_F_GRO); | |
738a8f4b BH |
2207 | if (type->offload_features & NETIF_F_V6_CSUM) |
2208 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2209 | /* Mask for features that also apply to VLAN devices */ |
2210 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2211 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2212 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2213 | pci_set_drvdata(pci_dev, efx); |
2214 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2215 | if (rc) | |
2216 | goto fail1; | |
2217 | ||
2218 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2219 | ||
2220 | /* Set up basic I/O (BAR mappings etc) */ | |
2221 | rc = efx_init_io(efx); | |
2222 | if (rc) | |
2223 | goto fail2; | |
2224 | ||
2225 | /* No serialisation is required with the reset path because | |
2226 | * we're in STATE_INIT. */ | |
2227 | for (i = 0; i < 5; i++) { | |
2228 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2229 | |
2230 | /* Serialise against efx_reset(). No more resets will be | |
2231 | * scheduled since efx_stop_all() has been called, and we | |
2232 | * have not and never have been registered with either | |
2233 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2234 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2235 | |
fa402b2e SH |
2236 | if (rc == 0) { |
2237 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2238 | /* If there was a scheduled reset during | |
2239 | * probe, the NIC is probably hosed anyway */ | |
2240 | efx_pci_remove_main(efx); | |
2241 | rc = -EIO; | |
2242 | } else { | |
2243 | break; | |
2244 | } | |
2245 | } | |
2246 | ||
8ceee660 BH |
2247 | /* Retry if a recoverably reset event has been scheduled */ |
2248 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2249 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2250 | goto fail3; | |
2251 | ||
2252 | efx->reset_pending = RESET_TYPE_NONE; | |
2253 | } | |
2254 | ||
2255 | if (rc) { | |
2256 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2257 | goto fail4; | |
2258 | } | |
2259 | ||
55edc6e6 BH |
2260 | /* Switch to the running state before we expose the device to the OS, |
2261 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2262 | efx->state = STATE_RUNNING; |
7dde596e | 2263 | |
8ceee660 BH |
2264 | rc = efx_register_netdev(efx); |
2265 | if (rc) | |
2266 | goto fail5; | |
2267 | ||
2268 | EFX_LOG(efx, "initialisation successful\n"); | |
a5211bb5 BH |
2269 | |
2270 | rtnl_lock(); | |
2271 | efx_mtd_probe(efx); /* allowed to fail */ | |
2272 | rtnl_unlock(); | |
8ceee660 BH |
2273 | return 0; |
2274 | ||
2275 | fail5: | |
2276 | efx_pci_remove_main(efx); | |
2277 | fail4: | |
2278 | fail3: | |
2279 | efx_fini_io(efx); | |
2280 | fail2: | |
2281 | efx_fini_struct(efx); | |
2282 | fail1: | |
5e2a911c | 2283 | WARN_ON(rc > 0); |
8ceee660 BH |
2284 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); |
2285 | free_netdev(net_dev); | |
2286 | return rc; | |
2287 | } | |
2288 | ||
89c758fa BH |
2289 | static int efx_pm_freeze(struct device *dev) |
2290 | { | |
2291 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2292 | ||
2293 | efx->state = STATE_FINI; | |
2294 | ||
2295 | netif_device_detach(efx->net_dev); | |
2296 | ||
2297 | efx_stop_all(efx); | |
2298 | efx_fini_channels(efx); | |
2299 | ||
2300 | return 0; | |
2301 | } | |
2302 | ||
2303 | static int efx_pm_thaw(struct device *dev) | |
2304 | { | |
2305 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2306 | ||
2307 | efx->state = STATE_INIT; | |
2308 | ||
2309 | efx_init_channels(efx); | |
2310 | ||
2311 | mutex_lock(&efx->mac_lock); | |
2312 | efx->phy_op->reconfigure(efx); | |
2313 | mutex_unlock(&efx->mac_lock); | |
2314 | ||
2315 | efx_start_all(efx); | |
2316 | ||
2317 | netif_device_attach(efx->net_dev); | |
2318 | ||
2319 | efx->state = STATE_RUNNING; | |
2320 | ||
2321 | efx->type->resume_wol(efx); | |
2322 | ||
319ba649 SH |
2323 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2324 | queue_work(reset_workqueue, &efx->reset_work); | |
2325 | ||
89c758fa BH |
2326 | return 0; |
2327 | } | |
2328 | ||
2329 | static int efx_pm_poweroff(struct device *dev) | |
2330 | { | |
2331 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2332 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2333 | ||
2334 | efx->type->fini(efx); | |
2335 | ||
2336 | efx->reset_pending = RESET_TYPE_NONE; | |
2337 | ||
2338 | pci_save_state(pci_dev); | |
2339 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2340 | } | |
2341 | ||
2342 | /* Used for both resume and restore */ | |
2343 | static int efx_pm_resume(struct device *dev) | |
2344 | { | |
2345 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2346 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2347 | int rc; | |
2348 | ||
2349 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2350 | if (rc) | |
2351 | return rc; | |
2352 | pci_restore_state(pci_dev); | |
2353 | rc = pci_enable_device(pci_dev); | |
2354 | if (rc) | |
2355 | return rc; | |
2356 | pci_set_master(efx->pci_dev); | |
2357 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2358 | if (rc) | |
2359 | return rc; | |
2360 | rc = efx->type->init(efx); | |
2361 | if (rc) | |
2362 | return rc; | |
2363 | efx_pm_thaw(dev); | |
2364 | return 0; | |
2365 | } | |
2366 | ||
2367 | static int efx_pm_suspend(struct device *dev) | |
2368 | { | |
2369 | int rc; | |
2370 | ||
2371 | efx_pm_freeze(dev); | |
2372 | rc = efx_pm_poweroff(dev); | |
2373 | if (rc) | |
2374 | efx_pm_resume(dev); | |
2375 | return rc; | |
2376 | } | |
2377 | ||
2378 | static struct dev_pm_ops efx_pm_ops = { | |
2379 | .suspend = efx_pm_suspend, | |
2380 | .resume = efx_pm_resume, | |
2381 | .freeze = efx_pm_freeze, | |
2382 | .thaw = efx_pm_thaw, | |
2383 | .poweroff = efx_pm_poweroff, | |
2384 | .restore = efx_pm_resume, | |
2385 | }; | |
2386 | ||
8ceee660 BH |
2387 | static struct pci_driver efx_pci_driver = { |
2388 | .name = EFX_DRIVER_NAME, | |
2389 | .id_table = efx_pci_table, | |
2390 | .probe = efx_pci_probe, | |
2391 | .remove = efx_pci_remove, | |
89c758fa | 2392 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2393 | }; |
2394 | ||
2395 | /************************************************************************** | |
2396 | * | |
2397 | * Kernel module interface | |
2398 | * | |
2399 | *************************************************************************/ | |
2400 | ||
2401 | module_param(interrupt_mode, uint, 0444); | |
2402 | MODULE_PARM_DESC(interrupt_mode, | |
2403 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2404 | ||
2405 | static int __init efx_init_module(void) | |
2406 | { | |
2407 | int rc; | |
2408 | ||
2409 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2410 | ||
2411 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2412 | if (rc) | |
2413 | goto err_notifier; | |
2414 | ||
1ab00629 SH |
2415 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2416 | if (!reset_workqueue) { | |
2417 | rc = -ENOMEM; | |
2418 | goto err_reset; | |
2419 | } | |
8ceee660 BH |
2420 | |
2421 | rc = pci_register_driver(&efx_pci_driver); | |
2422 | if (rc < 0) | |
2423 | goto err_pci; | |
2424 | ||
2425 | return 0; | |
2426 | ||
2427 | err_pci: | |
1ab00629 SH |
2428 | destroy_workqueue(reset_workqueue); |
2429 | err_reset: | |
8ceee660 BH |
2430 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2431 | err_notifier: | |
2432 | return rc; | |
2433 | } | |
2434 | ||
2435 | static void __exit efx_exit_module(void) | |
2436 | { | |
2437 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2438 | ||
2439 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2440 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2441 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2442 | ||
2443 | } | |
2444 | ||
2445 | module_init(efx_init_module); | |
2446 | module_exit(efx_exit_module); | |
2447 | ||
906bb26c BH |
2448 | MODULE_AUTHOR("Solarflare Communications and " |
2449 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2450 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2451 | MODULE_LICENSE("GPL"); | |
2452 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |