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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
8ceee660 | 24 | #include "net_driver.h" |
8ceee660 BH |
25 | #include "efx.h" |
26 | #include "mdio_10g.h" | |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
71 | /* Interrupt mode names (see INT_MODE())) */ | |
72 | const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX; | |
73 | const char *efx_interrupt_mode_names[] = { | |
74 | [EFX_INT_MODE_MSIX] = "MSI-X", | |
75 | [EFX_INT_MODE_MSI] = "MSI", | |
76 | [EFX_INT_MODE_LEGACY] = "legacy", | |
77 | }; | |
78 | ||
79 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; | |
80 | const char *efx_reset_type_names[] = { | |
81 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
82 | [RESET_TYPE_ALL] = "ALL", | |
83 | [RESET_TYPE_WORLD] = "WORLD", | |
84 | [RESET_TYPE_DISABLE] = "DISABLE", | |
85 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
86 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
87 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
88 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
89 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
90 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 91 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
92 | }; |
93 | ||
8ceee660 BH |
94 | #define EFX_MAX_MTU (9 * 1024) |
95 | ||
96 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
97 | * a work item is pushed onto this work queue to retry the allocation later, | |
98 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
99 | * workqueue, there is nothing to be gained in making it per NIC | |
100 | */ | |
101 | static struct workqueue_struct *refill_workqueue; | |
102 | ||
1ab00629 SH |
103 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
104 | * queued onto this work queue. This is not a per-nic work queue, because | |
105 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
106 | */ | |
107 | static struct workqueue_struct *reset_workqueue; | |
108 | ||
8ceee660 BH |
109 | /************************************************************************** |
110 | * | |
111 | * Configurable values | |
112 | * | |
113 | *************************************************************************/ | |
114 | ||
8ceee660 BH |
115 | /* |
116 | * Use separate channels for TX and RX events | |
117 | * | |
28b581ab NT |
118 | * Set this to 1 to use separate channels for TX and RX. It allows us |
119 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 120 | * |
28b581ab | 121 | * This is only used in MSI-X interrupt mode |
8ceee660 | 122 | */ |
28b581ab NT |
123 | static unsigned int separate_tx_channels; |
124 | module_param(separate_tx_channels, uint, 0644); | |
125 | MODULE_PARM_DESC(separate_tx_channels, | |
126 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
127 | |
128 | /* This is the weight assigned to each of the (per-channel) virtual | |
129 | * NAPI devices. | |
130 | */ | |
131 | static int napi_weight = 64; | |
132 | ||
133 | /* This is the time (in jiffies) between invocations of the hardware | |
134 | * monitor, which checks for known hardware bugs and resets the | |
135 | * hardware and driver as necessary. | |
136 | */ | |
137 | unsigned int efx_monitor_interval = 1 * HZ; | |
138 | ||
8ceee660 BH |
139 | /* This controls whether or not the driver will initialise devices |
140 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
141 | * such devices will be initialised with a random locally-generated | |
142 | * MAC address. This allows for loading the sfc_mtd driver to | |
143 | * reprogram the flash, even if the flash contents (including the MAC | |
144 | * address) have previously been erased. | |
145 | */ | |
146 | static unsigned int allow_bad_hwaddr; | |
147 | ||
148 | /* Initial interrupt moderation settings. They can be modified after | |
149 | * module load with ethtool. | |
150 | * | |
151 | * The default for RX should strike a balance between increasing the | |
152 | * round-trip latency and reducing overhead. | |
153 | */ | |
154 | static unsigned int rx_irq_mod_usec = 60; | |
155 | ||
156 | /* Initial interrupt moderation settings. They can be modified after | |
157 | * module load with ethtool. | |
158 | * | |
159 | * This default is chosen to ensure that a 10G link does not go idle | |
160 | * while a TX queue is stopped after it has become full. A queue is | |
161 | * restarted when it drops below half full. The time this takes (assuming | |
162 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
163 | * 512 / 3 * 1.2 = 205 usec. | |
164 | */ | |
165 | static unsigned int tx_irq_mod_usec = 150; | |
166 | ||
167 | /* This is the first interrupt mode to try out of: | |
168 | * 0 => MSI-X | |
169 | * 1 => MSI | |
170 | * 2 => legacy | |
171 | */ | |
172 | static unsigned int interrupt_mode; | |
173 | ||
174 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
175 | * i.e. the number of CPUs among which we may distribute simultaneous | |
176 | * interrupt handling. | |
177 | * | |
178 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
179 | * The default (0) means to assign an interrupt to each package (level II cache) | |
180 | */ | |
181 | static unsigned int rss_cpus; | |
182 | module_param(rss_cpus, uint, 0444); | |
183 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
184 | ||
84ae48fe BH |
185 | static int phy_flash_cfg; |
186 | module_param(phy_flash_cfg, int, 0644); | |
187 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
188 | ||
6fb70fd1 BH |
189 | static unsigned irq_adapt_low_thresh = 10000; |
190 | module_param(irq_adapt_low_thresh, uint, 0644); | |
191 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
192 | "Threshold score for reducing IRQ moderation"); | |
193 | ||
194 | static unsigned irq_adapt_high_thresh = 20000; | |
195 | module_param(irq_adapt_high_thresh, uint, 0644); | |
196 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
197 | "Threshold score for increasing IRQ moderation"); | |
198 | ||
8ceee660 BH |
199 | /************************************************************************** |
200 | * | |
201 | * Utility functions and prototypes | |
202 | * | |
203 | *************************************************************************/ | |
204 | static void efx_remove_channel(struct efx_channel *channel); | |
205 | static void efx_remove_port(struct efx_nic *efx); | |
206 | static void efx_fini_napi(struct efx_nic *efx); | |
207 | static void efx_fini_channels(struct efx_nic *efx); | |
208 | ||
209 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
210 | do { \ | |
332c1ce9 BH |
211 | if ((efx->state == STATE_RUNNING) || \ |
212 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
213 | ASSERT_RTNL(); \ |
214 | } while (0) | |
215 | ||
216 | /************************************************************************** | |
217 | * | |
218 | * Event queue processing | |
219 | * | |
220 | *************************************************************************/ | |
221 | ||
222 | /* Process channel's event queue | |
223 | * | |
224 | * This function is responsible for processing the event queue of a | |
225 | * single channel. The caller must guarantee that this function will | |
226 | * never be concurrently called more than once on the same channel, | |
227 | * though different channels may be being processed concurrently. | |
228 | */ | |
fa236e18 | 229 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 230 | { |
42cbe2d7 | 231 | struct efx_nic *efx = channel->efx; |
fa236e18 | 232 | int spent; |
8ceee660 | 233 | |
42cbe2d7 | 234 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 235 | !channel->enabled)) |
42cbe2d7 | 236 | return 0; |
8ceee660 | 237 | |
fa236e18 BH |
238 | spent = efx_nic_process_eventq(channel, budget); |
239 | if (spent == 0) | |
42cbe2d7 | 240 | return 0; |
8ceee660 BH |
241 | |
242 | /* Deliver last RX packet. */ | |
243 | if (channel->rx_pkt) { | |
244 | __efx_rx_packet(channel, channel->rx_pkt, | |
245 | channel->rx_pkt_csummed); | |
246 | channel->rx_pkt = NULL; | |
247 | } | |
248 | ||
8ceee660 BH |
249 | efx_rx_strategy(channel); |
250 | ||
42cbe2d7 | 251 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 252 | |
fa236e18 | 253 | return spent; |
8ceee660 BH |
254 | } |
255 | ||
256 | /* Mark channel as finished processing | |
257 | * | |
258 | * Note that since we will not receive further interrupts for this | |
259 | * channel before we finish processing and call the eventq_read_ack() | |
260 | * method, there is no need to use the interrupt hold-off timers. | |
261 | */ | |
262 | static inline void efx_channel_processed(struct efx_channel *channel) | |
263 | { | |
5b9e207c BH |
264 | /* The interrupt handler for this channel may set work_pending |
265 | * as soon as we acknowledge the events we've seen. Make sure | |
266 | * it's cleared before then. */ | |
dc8cfa55 | 267 | channel->work_pending = false; |
5b9e207c BH |
268 | smp_wmb(); |
269 | ||
152b6a62 | 270 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
271 | } |
272 | ||
273 | /* NAPI poll handler | |
274 | * | |
275 | * NAPI guarantees serialisation of polls of the same device, which | |
276 | * provides the guarantee required by efx_process_channel(). | |
277 | */ | |
278 | static int efx_poll(struct napi_struct *napi, int budget) | |
279 | { | |
280 | struct efx_channel *channel = | |
281 | container_of(napi, struct efx_channel, napi_str); | |
fa236e18 | 282 | int spent; |
8ceee660 BH |
283 | |
284 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
285 | channel->channel, raw_smp_processor_id()); | |
286 | ||
fa236e18 | 287 | spent = efx_process_channel(channel, budget); |
8ceee660 | 288 | |
fa236e18 | 289 | if (spent < budget) { |
6fb70fd1 BH |
290 | struct efx_nic *efx = channel->efx; |
291 | ||
a4900ac9 | 292 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
293 | efx->irq_rx_adaptive && |
294 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
295 | if (unlikely(channel->irq_mod_score < |
296 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
297 | if (channel->irq_moderation > 1) { |
298 | channel->irq_moderation -= 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 BH |
301 | } else if (unlikely(channel->irq_mod_score > |
302 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
303 | if (channel->irq_moderation < |
304 | efx->irq_rx_moderation) { | |
305 | channel->irq_moderation += 1; | |
ef2b90ee | 306 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 307 | } |
6fb70fd1 | 308 | } |
6fb70fd1 BH |
309 | channel->irq_count = 0; |
310 | channel->irq_mod_score = 0; | |
311 | } | |
312 | ||
8ceee660 | 313 | /* There is no race here; although napi_disable() will |
288379f0 | 314 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
315 | * since efx_channel_processed() will have no effect if |
316 | * interrupts have already been disabled. | |
317 | */ | |
288379f0 | 318 | napi_complete(napi); |
8ceee660 BH |
319 | efx_channel_processed(channel); |
320 | } | |
321 | ||
fa236e18 | 322 | return spent; |
8ceee660 BH |
323 | } |
324 | ||
325 | /* Process the eventq of the specified channel immediately on this CPU | |
326 | * | |
327 | * Disable hardware generated interrupts, wait for any existing | |
328 | * processing to finish, then directly poll (and ack ) the eventq. | |
329 | * Finally reenable NAPI and interrupts. | |
330 | * | |
331 | * Since we are touching interrupts the caller should hold the suspend lock | |
332 | */ | |
333 | void efx_process_channel_now(struct efx_channel *channel) | |
334 | { | |
335 | struct efx_nic *efx = channel->efx; | |
336 | ||
8ceee660 BH |
337 | BUG_ON(!channel->enabled); |
338 | ||
339 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 340 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
341 | if (efx->legacy_irq) |
342 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 343 | if (channel->irq) |
8ceee660 BH |
344 | synchronize_irq(channel->irq); |
345 | ||
346 | /* Wait for any NAPI processing to complete */ | |
347 | napi_disable(&channel->napi_str); | |
348 | ||
349 | /* Poll the channel */ | |
3ffeabdd | 350 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
351 | |
352 | /* Ack the eventq. This may cause an interrupt to be generated | |
353 | * when they are reenabled */ | |
354 | efx_channel_processed(channel); | |
355 | ||
356 | napi_enable(&channel->napi_str); | |
152b6a62 | 357 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
358 | } |
359 | ||
360 | /* Create event queue | |
361 | * Event queue memory allocations are done only once. If the channel | |
362 | * is reset, the memory buffer will be reused; this guards against | |
363 | * errors during channel reset and also simplifies interrupt handling. | |
364 | */ | |
365 | static int efx_probe_eventq(struct efx_channel *channel) | |
366 | { | |
367 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
368 | ||
152b6a62 | 369 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
370 | } |
371 | ||
372 | /* Prepare channel's event queue */ | |
bc3c90a2 | 373 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
374 | { |
375 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
376 | ||
377 | channel->eventq_read_ptr = 0; | |
378 | ||
152b6a62 | 379 | efx_nic_init_eventq(channel); |
8ceee660 BH |
380 | } |
381 | ||
382 | static void efx_fini_eventq(struct efx_channel *channel) | |
383 | { | |
384 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
385 | ||
152b6a62 | 386 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
387 | } |
388 | ||
389 | static void efx_remove_eventq(struct efx_channel *channel) | |
390 | { | |
391 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
392 | ||
152b6a62 | 393 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
394 | } |
395 | ||
396 | /************************************************************************** | |
397 | * | |
398 | * Channel handling | |
399 | * | |
400 | *************************************************************************/ | |
401 | ||
8ceee660 BH |
402 | static int efx_probe_channel(struct efx_channel *channel) |
403 | { | |
404 | struct efx_tx_queue *tx_queue; | |
405 | struct efx_rx_queue *rx_queue; | |
406 | int rc; | |
407 | ||
408 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
409 | ||
410 | rc = efx_probe_eventq(channel); | |
411 | if (rc) | |
412 | goto fail1; | |
413 | ||
414 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
415 | rc = efx_probe_tx_queue(tx_queue); | |
416 | if (rc) | |
417 | goto fail2; | |
418 | } | |
419 | ||
420 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
421 | rc = efx_probe_rx_queue(rx_queue); | |
422 | if (rc) | |
423 | goto fail3; | |
424 | } | |
425 | ||
426 | channel->n_rx_frm_trunc = 0; | |
427 | ||
428 | return 0; | |
429 | ||
430 | fail3: | |
431 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
432 | efx_remove_rx_queue(rx_queue); | |
433 | fail2: | |
434 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
435 | efx_remove_tx_queue(tx_queue); | |
436 | fail1: | |
437 | return rc; | |
438 | } | |
439 | ||
440 | ||
56536e9c BH |
441 | static void efx_set_channel_names(struct efx_nic *efx) |
442 | { | |
443 | struct efx_channel *channel; | |
444 | const char *type = ""; | |
445 | int number; | |
446 | ||
447 | efx_for_each_channel(channel, efx) { | |
448 | number = channel->channel; | |
a4900ac9 BH |
449 | if (efx->n_channels > efx->n_rx_channels) { |
450 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
451 | type = "-rx"; |
452 | } else { | |
453 | type = "-tx"; | |
a4900ac9 | 454 | number -= efx->n_rx_channels; |
56536e9c BH |
455 | } |
456 | } | |
457 | snprintf(channel->name, sizeof(channel->name), | |
458 | "%s%s-%d", efx->name, type, number); | |
459 | } | |
460 | } | |
461 | ||
8ceee660 BH |
462 | /* Channels are shutdown and reinitialised whilst the NIC is running |
463 | * to propagate configuration changes (mtu, checksum offload), or | |
464 | * to clear hardware error conditions | |
465 | */ | |
bc3c90a2 | 466 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
467 | { |
468 | struct efx_tx_queue *tx_queue; | |
469 | struct efx_rx_queue *rx_queue; | |
470 | struct efx_channel *channel; | |
8ceee660 | 471 | |
f7f13b0b BH |
472 | /* Calculate the rx buffer allocation parameters required to |
473 | * support the current MTU, including padding for header | |
474 | * alignment and overruns. | |
475 | */ | |
476 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
477 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
478 | efx->type->rx_buffer_padding); | |
479 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
480 | |
481 | /* Initialise the channels */ | |
482 | efx_for_each_channel(channel, efx) { | |
483 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
484 | ||
bc3c90a2 | 485 | efx_init_eventq(channel); |
8ceee660 | 486 | |
bc3c90a2 BH |
487 | efx_for_each_channel_tx_queue(tx_queue, channel) |
488 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
489 | |
490 | /* The rx buffer allocation strategy is MTU dependent */ | |
491 | efx_rx_strategy(channel); | |
492 | ||
bc3c90a2 BH |
493 | efx_for_each_channel_rx_queue(rx_queue, channel) |
494 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
495 | |
496 | WARN_ON(channel->rx_pkt != NULL); | |
497 | efx_rx_strategy(channel); | |
498 | } | |
8ceee660 BH |
499 | } |
500 | ||
501 | /* This enables event queue processing and packet transmission. | |
502 | * | |
503 | * Note that this function is not allowed to fail, since that would | |
504 | * introduce too much complexity into the suspend/resume path. | |
505 | */ | |
506 | static void efx_start_channel(struct efx_channel *channel) | |
507 | { | |
508 | struct efx_rx_queue *rx_queue; | |
509 | ||
510 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
511 | ||
5b9e207c BH |
512 | /* The interrupt handler for this channel may set work_pending |
513 | * as soon as we enable it. Make sure it's cleared before | |
514 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
515 | channel->work_pending = false; |
516 | channel->enabled = true; | |
5b9e207c | 517 | smp_wmb(); |
8ceee660 BH |
518 | |
519 | napi_enable(&channel->napi_str); | |
520 | ||
521 | /* Load up RX descriptors */ | |
522 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
523 | efx_fast_push_rx_descriptors(rx_queue); | |
524 | } | |
525 | ||
526 | /* This disables event queue processing and packet transmission. | |
527 | * This function does not guarantee that all queue processing | |
528 | * (e.g. RX refill) is complete. | |
529 | */ | |
530 | static void efx_stop_channel(struct efx_channel *channel) | |
531 | { | |
532 | struct efx_rx_queue *rx_queue; | |
533 | ||
534 | if (!channel->enabled) | |
535 | return; | |
536 | ||
537 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
538 | ||
dc8cfa55 | 539 | channel->enabled = false; |
8ceee660 BH |
540 | napi_disable(&channel->napi_str); |
541 | ||
542 | /* Ensure that any worker threads have exited or will be no-ops */ | |
543 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
544 | spin_lock_bh(&rx_queue->add_lock); | |
545 | spin_unlock_bh(&rx_queue->add_lock); | |
546 | } | |
547 | } | |
548 | ||
549 | static void efx_fini_channels(struct efx_nic *efx) | |
550 | { | |
551 | struct efx_channel *channel; | |
552 | struct efx_tx_queue *tx_queue; | |
553 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 554 | int rc; |
8ceee660 BH |
555 | |
556 | EFX_ASSERT_RESET_SERIALISED(efx); | |
557 | BUG_ON(efx->port_enabled); | |
558 | ||
152b6a62 | 559 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
560 | if (rc && EFX_WORKAROUND_7803(efx)) { |
561 | /* Schedule a reset to recover from the flush failure. The | |
562 | * descriptor caches reference memory we're about to free, | |
563 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
564 | * the MACs because of the pending reset. */ | |
565 | EFX_ERR(efx, "Resetting to recover from flush failure\n"); | |
566 | efx_schedule_reset(efx, RESET_TYPE_ALL); | |
567 | } else if (rc) { | |
6bc5d3a9 | 568 | EFX_ERR(efx, "failed to flush queues\n"); |
fd371e32 | 569 | } else { |
6bc5d3a9 | 570 | EFX_LOG(efx, "successfully flushed all queues\n"); |
fd371e32 | 571 | } |
6bc5d3a9 | 572 | |
8ceee660 BH |
573 | efx_for_each_channel(channel, efx) { |
574 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
575 | ||
576 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
577 | efx_fini_rx_queue(rx_queue); | |
578 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
579 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
580 | efx_fini_eventq(channel); |
581 | } | |
582 | } | |
583 | ||
584 | static void efx_remove_channel(struct efx_channel *channel) | |
585 | { | |
586 | struct efx_tx_queue *tx_queue; | |
587 | struct efx_rx_queue *rx_queue; | |
588 | ||
589 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
590 | ||
591 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
592 | efx_remove_rx_queue(rx_queue); | |
593 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
594 | efx_remove_tx_queue(tx_queue); | |
595 | efx_remove_eventq(channel); | |
8ceee660 BH |
596 | } |
597 | ||
598 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
599 | { | |
600 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
601 | } | |
602 | ||
603 | /************************************************************************** | |
604 | * | |
605 | * Port handling | |
606 | * | |
607 | **************************************************************************/ | |
608 | ||
609 | /* This ensures that the kernel is kept informed (via | |
610 | * netif_carrier_on/off) of the link status, and also maintains the | |
611 | * link status's stop on the port's TX queue. | |
612 | */ | |
fdaa9aed | 613 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 614 | { |
eb50c0d6 BH |
615 | struct efx_link_state *link_state = &efx->link_state; |
616 | ||
8ceee660 BH |
617 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
618 | * that no events are triggered between unregister_netdev() and the | |
619 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
620 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
621 | if (!netif_running(efx->net_dev)) | |
622 | return; | |
623 | ||
8c8661e4 BH |
624 | if (efx->port_inhibited) { |
625 | netif_carrier_off(efx->net_dev); | |
626 | return; | |
627 | } | |
628 | ||
eb50c0d6 | 629 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
630 | efx->n_link_state_changes++; |
631 | ||
eb50c0d6 | 632 | if (link_state->up) |
8ceee660 BH |
633 | netif_carrier_on(efx->net_dev); |
634 | else | |
635 | netif_carrier_off(efx->net_dev); | |
636 | } | |
637 | ||
638 | /* Status message for kernel log */ | |
eb50c0d6 | 639 | if (link_state->up) { |
f31a45d2 | 640 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
eb50c0d6 | 641 | link_state->speed, link_state->fd ? "full" : "half", |
8ceee660 BH |
642 | efx->net_dev->mtu, |
643 | (efx->promiscuous ? " [PROMISC]" : "")); | |
644 | } else { | |
645 | EFX_INFO(efx, "link down\n"); | |
646 | } | |
647 | ||
648 | } | |
649 | ||
d3245b28 BH |
650 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
651 | { | |
652 | efx->link_advertising = advertising; | |
653 | if (advertising) { | |
654 | if (advertising & ADVERTISED_Pause) | |
655 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
656 | else | |
657 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
658 | if (advertising & ADVERTISED_Asym_Pause) | |
659 | efx->wanted_fc ^= EFX_FC_TX; | |
660 | } | |
661 | } | |
662 | ||
663 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
664 | { | |
665 | efx->wanted_fc = wanted_fc; | |
666 | if (efx->link_advertising) { | |
667 | if (wanted_fc & EFX_FC_RX) | |
668 | efx->link_advertising |= (ADVERTISED_Pause | | |
669 | ADVERTISED_Asym_Pause); | |
670 | else | |
671 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
672 | ADVERTISED_Asym_Pause); | |
673 | if (wanted_fc & EFX_FC_TX) | |
674 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
675 | } | |
676 | } | |
677 | ||
115122af BH |
678 | static void efx_fini_port(struct efx_nic *efx); |
679 | ||
d3245b28 BH |
680 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
681 | * the MAC appropriately. All other PHY configuration changes are pushed | |
682 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
683 | * through efx_monitor(). | |
684 | * | |
685 | * Callers must hold the mac_lock | |
686 | */ | |
687 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 688 | { |
d3245b28 BH |
689 | enum efx_phy_mode phy_mode; |
690 | int rc; | |
8ceee660 | 691 | |
d3245b28 | 692 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 693 | |
a816f75a BH |
694 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
695 | if (efx_dev_registered(efx)) { | |
696 | netif_addr_lock_bh(efx->net_dev); | |
697 | netif_addr_unlock_bh(efx->net_dev); | |
698 | } | |
699 | ||
d3245b28 BH |
700 | /* Disable PHY transmit in mac level loopbacks */ |
701 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
702 | if (LOOPBACK_INTERNAL(efx)) |
703 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
704 | else | |
705 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 706 | |
d3245b28 | 707 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 708 | |
d3245b28 BH |
709 | if (rc) |
710 | efx->phy_mode = phy_mode; | |
177dfcd8 | 711 | |
d3245b28 | 712 | return rc; |
8ceee660 BH |
713 | } |
714 | ||
715 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
716 | * disabled. */ | |
d3245b28 | 717 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 718 | { |
d3245b28 BH |
719 | int rc; |
720 | ||
8ceee660 BH |
721 | EFX_ASSERT_RESET_SERIALISED(efx); |
722 | ||
723 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 724 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 725 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
726 | |
727 | return rc; | |
8ceee660 BH |
728 | } |
729 | ||
8be4f3e6 BH |
730 | /* Asynchronous work item for changing MAC promiscuity and multicast |
731 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
732 | * MAC directly. */ | |
766ca0fa BH |
733 | static void efx_mac_work(struct work_struct *data) |
734 | { | |
735 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
736 | ||
737 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 738 | if (efx->port_enabled) { |
ef2b90ee | 739 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
740 | efx->mac_op->reconfigure(efx); |
741 | } | |
766ca0fa BH |
742 | mutex_unlock(&efx->mac_lock); |
743 | } | |
744 | ||
8ceee660 BH |
745 | static int efx_probe_port(struct efx_nic *efx) |
746 | { | |
747 | int rc; | |
748 | ||
749 | EFX_LOG(efx, "create port\n"); | |
750 | ||
ff3b00a0 SH |
751 | if (phy_flash_cfg) |
752 | efx->phy_mode = PHY_MODE_SPECIAL; | |
753 | ||
ef2b90ee BH |
754 | /* Connect up MAC/PHY operations table */ |
755 | rc = efx->type->probe_port(efx); | |
8ceee660 BH |
756 | if (rc) |
757 | goto err; | |
758 | ||
759 | /* Sanity check MAC address */ | |
760 | if (is_valid_ether_addr(efx->mac_address)) { | |
761 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
762 | } else { | |
e174961c JB |
763 | EFX_ERR(efx, "invalid MAC address %pM\n", |
764 | efx->mac_address); | |
8ceee660 BH |
765 | if (!allow_bad_hwaddr) { |
766 | rc = -EINVAL; | |
767 | goto err; | |
768 | } | |
769 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
770 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
771 | efx->net_dev->dev_addr); | |
8ceee660 BH |
772 | } |
773 | ||
774 | return 0; | |
775 | ||
776 | err: | |
777 | efx_remove_port(efx); | |
778 | return rc; | |
779 | } | |
780 | ||
781 | static int efx_init_port(struct efx_nic *efx) | |
782 | { | |
783 | int rc; | |
784 | ||
785 | EFX_LOG(efx, "init port\n"); | |
786 | ||
1dfc5cea BH |
787 | mutex_lock(&efx->mac_lock); |
788 | ||
177dfcd8 | 789 | rc = efx->phy_op->init(efx); |
8ceee660 | 790 | if (rc) |
1dfc5cea | 791 | goto fail1; |
8ceee660 | 792 | |
dc8cfa55 | 793 | efx->port_initialized = true; |
1dfc5cea | 794 | |
d3245b28 BH |
795 | /* Reconfigure the MAC before creating dma queues (required for |
796 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
797 | efx->mac_op->reconfigure(efx); | |
798 | ||
799 | /* Ensure the PHY advertises the correct flow control settings */ | |
800 | rc = efx->phy_op->reconfigure(efx); | |
801 | if (rc) | |
802 | goto fail2; | |
803 | ||
1dfc5cea | 804 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 805 | return 0; |
177dfcd8 | 806 | |
1dfc5cea | 807 | fail2: |
177dfcd8 | 808 | efx->phy_op->fini(efx); |
1dfc5cea BH |
809 | fail1: |
810 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 811 | return rc; |
8ceee660 BH |
812 | } |
813 | ||
8ceee660 BH |
814 | static void efx_start_port(struct efx_nic *efx) |
815 | { | |
816 | EFX_LOG(efx, "start port\n"); | |
817 | BUG_ON(efx->port_enabled); | |
818 | ||
819 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 820 | efx->port_enabled = true; |
8be4f3e6 BH |
821 | |
822 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
823 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 824 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
825 | efx->mac_op->reconfigure(efx); |
826 | ||
8ceee660 BH |
827 | mutex_unlock(&efx->mac_lock); |
828 | } | |
829 | ||
fdaa9aed | 830 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
831 | static void efx_stop_port(struct efx_nic *efx) |
832 | { | |
833 | EFX_LOG(efx, "stop port\n"); | |
834 | ||
835 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 836 | efx->port_enabled = false; |
8ceee660 BH |
837 | mutex_unlock(&efx->mac_lock); |
838 | ||
839 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 840 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
841 | netif_addr_lock_bh(efx->net_dev); |
842 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
843 | } |
844 | } | |
845 | ||
846 | static void efx_fini_port(struct efx_nic *efx) | |
847 | { | |
848 | EFX_LOG(efx, "shut down port\n"); | |
849 | ||
850 | if (!efx->port_initialized) | |
851 | return; | |
852 | ||
177dfcd8 | 853 | efx->phy_op->fini(efx); |
dc8cfa55 | 854 | efx->port_initialized = false; |
8ceee660 | 855 | |
eb50c0d6 | 856 | efx->link_state.up = false; |
8ceee660 BH |
857 | efx_link_status_changed(efx); |
858 | } | |
859 | ||
860 | static void efx_remove_port(struct efx_nic *efx) | |
861 | { | |
862 | EFX_LOG(efx, "destroying port\n"); | |
863 | ||
ef2b90ee | 864 | efx->type->remove_port(efx); |
8ceee660 BH |
865 | } |
866 | ||
867 | /************************************************************************** | |
868 | * | |
869 | * NIC handling | |
870 | * | |
871 | **************************************************************************/ | |
872 | ||
873 | /* This configures the PCI device to enable I/O and DMA. */ | |
874 | static int efx_init_io(struct efx_nic *efx) | |
875 | { | |
876 | struct pci_dev *pci_dev = efx->pci_dev; | |
877 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
878 | int rc; | |
879 | ||
880 | EFX_LOG(efx, "initialising I/O\n"); | |
881 | ||
882 | rc = pci_enable_device(pci_dev); | |
883 | if (rc) { | |
884 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
885 | goto fail1; | |
886 | } | |
887 | ||
888 | pci_set_master(pci_dev); | |
889 | ||
890 | /* Set the PCI DMA mask. Try all possibilities from our | |
891 | * genuine mask down to 32 bits, because some architectures | |
892 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
893 | * masks event though they reject 46 bit masks. | |
894 | */ | |
895 | while (dma_mask > 0x7fffffffUL) { | |
896 | if (pci_dma_supported(pci_dev, dma_mask) && | |
897 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
898 | break; | |
899 | dma_mask >>= 1; | |
900 | } | |
901 | if (rc) { | |
902 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
903 | goto fail2; | |
904 | } | |
905 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
906 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
907 | if (rc) { | |
908 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
909 | * fail with a mask that pci_set_dma_mask() accepted, | |
910 | * but just in case... | |
911 | */ | |
912 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
913 | goto fail2; | |
914 | } | |
915 | ||
dc803df8 BH |
916 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
917 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 BH |
918 | if (rc) { |
919 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
920 | rc = -EIO; | |
921 | goto fail3; | |
922 | } | |
923 | efx->membase = ioremap_nocache(efx->membase_phys, | |
924 | efx->type->mem_map_size); | |
925 | if (!efx->membase) { | |
dc803df8 | 926 | EFX_ERR(efx, "could not map memory BAR at %llx+%x\n", |
086ea356 | 927 | (unsigned long long)efx->membase_phys, |
8ceee660 BH |
928 | efx->type->mem_map_size); |
929 | rc = -ENOMEM; | |
930 | goto fail4; | |
931 | } | |
dc803df8 BH |
932 | EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n", |
933 | (unsigned long long)efx->membase_phys, | |
086ea356 | 934 | efx->type->mem_map_size, efx->membase); |
8ceee660 BH |
935 | |
936 | return 0; | |
937 | ||
938 | fail4: | |
dc803df8 | 939 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 940 | fail3: |
2c118e0f | 941 | efx->membase_phys = 0; |
8ceee660 BH |
942 | fail2: |
943 | pci_disable_device(efx->pci_dev); | |
944 | fail1: | |
945 | return rc; | |
946 | } | |
947 | ||
948 | static void efx_fini_io(struct efx_nic *efx) | |
949 | { | |
950 | EFX_LOG(efx, "shutting down I/O\n"); | |
951 | ||
952 | if (efx->membase) { | |
953 | iounmap(efx->membase); | |
954 | efx->membase = NULL; | |
955 | } | |
956 | ||
957 | if (efx->membase_phys) { | |
dc803df8 | 958 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 959 | efx->membase_phys = 0; |
8ceee660 BH |
960 | } |
961 | ||
962 | pci_disable_device(efx->pci_dev); | |
963 | } | |
964 | ||
a4900ac9 BH |
965 | /* Get number of channels wanted. Each channel will have its own IRQ, |
966 | * 1 RX queue and/or 2 TX queues. */ | |
967 | static int efx_wanted_channels(void) | |
46123d04 | 968 | { |
2f8975fb | 969 | cpumask_var_t core_mask; |
46123d04 BH |
970 | int count; |
971 | int cpu; | |
972 | ||
79f55997 | 973 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 974 | printk(KERN_WARNING |
3977d033 | 975 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
976 | return 1; |
977 | } | |
978 | ||
46123d04 BH |
979 | count = 0; |
980 | for_each_online_cpu(cpu) { | |
2f8975fb | 981 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 982 | ++count; |
2f8975fb | 983 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 984 | topology_core_cpumask(cpu)); |
46123d04 BH |
985 | } |
986 | } | |
987 | ||
2f8975fb | 988 | free_cpumask_var(core_mask); |
46123d04 BH |
989 | return count; |
990 | } | |
991 | ||
992 | /* Probe the number and type of interrupts we are able to obtain, and | |
993 | * the resulting numbers of channels and RX queues. | |
994 | */ | |
8ceee660 BH |
995 | static void efx_probe_interrupts(struct efx_nic *efx) |
996 | { | |
46123d04 BH |
997 | int max_channels = |
998 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
999 | int rc, i; |
1000 | ||
1001 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1002 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1003 | int n_channels; |
aa6ef27e | 1004 | |
a4900ac9 BH |
1005 | n_channels = efx_wanted_channels(); |
1006 | if (separate_tx_channels) | |
1007 | n_channels *= 2; | |
1008 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1009 | |
a4900ac9 | 1010 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1011 | xentries[i].entry = i; |
a4900ac9 | 1012 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1013 | if (rc > 0) { |
28b581ab | 1014 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
a4900ac9 | 1015 | " available (%d < %d).\n", rc, n_channels); |
28b581ab | 1016 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); |
a4900ac9 BH |
1017 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1018 | n_channels = rc; | |
8ceee660 | 1019 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1020 | n_channels); |
8ceee660 BH |
1021 | } |
1022 | ||
1023 | if (rc == 0) { | |
a4900ac9 BH |
1024 | efx->n_channels = n_channels; |
1025 | if (separate_tx_channels) { | |
1026 | efx->n_tx_channels = | |
1027 | max(efx->n_channels / 2, 1U); | |
1028 | efx->n_rx_channels = | |
1029 | max(efx->n_channels - | |
1030 | efx->n_tx_channels, 1U); | |
1031 | } else { | |
1032 | efx->n_tx_channels = efx->n_channels; | |
1033 | efx->n_rx_channels = efx->n_channels; | |
1034 | } | |
1035 | for (i = 0; i < n_channels; i++) | |
8ceee660 | 1036 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
1037 | } else { |
1038 | /* Fall back to single channel MSI */ | |
1039 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
1040 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
1041 | } | |
1042 | } | |
1043 | ||
1044 | /* Try single interrupt MSI */ | |
1045 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1046 | efx->n_channels = 1; |
a4900ac9 BH |
1047 | efx->n_rx_channels = 1; |
1048 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1049 | rc = pci_enable_msi(efx->pci_dev); |
1050 | if (rc == 0) { | |
1051 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
1052 | } else { |
1053 | EFX_ERR(efx, "could not enable MSI\n"); | |
1054 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
1055 | } | |
1056 | } | |
1057 | ||
1058 | /* Assume legacy interrupts */ | |
1059 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1060 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1061 | efx->n_rx_channels = 1; |
1062 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1063 | efx->legacy_irq = efx->pci_dev->irq; |
1064 | } | |
1065 | } | |
1066 | ||
1067 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1068 | { | |
1069 | struct efx_channel *channel; | |
1070 | ||
1071 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1072 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1073 | channel->irq = 0; |
1074 | pci_disable_msi(efx->pci_dev); | |
1075 | pci_disable_msix(efx->pci_dev); | |
1076 | ||
1077 | /* Remove legacy interrupt */ | |
1078 | efx->legacy_irq = 0; | |
1079 | } | |
1080 | ||
8831da7b | 1081 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1082 | { |
a4900ac9 | 1083 | struct efx_channel *channel; |
8ceee660 BH |
1084 | struct efx_tx_queue *tx_queue; |
1085 | struct efx_rx_queue *rx_queue; | |
a4900ac9 BH |
1086 | unsigned tx_channel_offset = |
1087 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
8ceee660 | 1088 | |
a4900ac9 BH |
1089 | efx_for_each_channel(channel, efx) { |
1090 | if (channel->channel - tx_channel_offset < efx->n_tx_channels) { | |
1091 | channel->tx_queue = &efx->tx_queue[ | |
1092 | (channel->channel - tx_channel_offset) * | |
1093 | EFX_TXQ_TYPES]; | |
1094 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1095 | tx_queue->channel = channel; | |
1096 | } | |
60ac1065 | 1097 | } |
8ceee660 | 1098 | |
a4900ac9 | 1099 | efx_for_each_rx_queue(rx_queue, efx) |
8831da7b | 1100 | rx_queue->channel = &efx->channel[rx_queue->queue]; |
8ceee660 BH |
1101 | } |
1102 | ||
1103 | static int efx_probe_nic(struct efx_nic *efx) | |
1104 | { | |
1105 | int rc; | |
1106 | ||
1107 | EFX_LOG(efx, "creating NIC\n"); | |
1108 | ||
1109 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1110 | rc = efx->type->probe(efx); |
8ceee660 BH |
1111 | if (rc) |
1112 | return rc; | |
1113 | ||
a4900ac9 | 1114 | /* Determine the number of channels and queues by trying to hook |
8ceee660 BH |
1115 | * in MSI-X interrupts. */ |
1116 | efx_probe_interrupts(efx); | |
1117 | ||
8831da7b | 1118 | efx_set_channels(efx); |
a4900ac9 | 1119 | efx->net_dev->real_num_tx_queues = efx->n_tx_channels; |
8ceee660 BH |
1120 | |
1121 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1122 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1123 | |
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | static void efx_remove_nic(struct efx_nic *efx) | |
1128 | { | |
1129 | EFX_LOG(efx, "destroying NIC\n"); | |
1130 | ||
1131 | efx_remove_interrupts(efx); | |
ef2b90ee | 1132 | efx->type->remove(efx); |
8ceee660 BH |
1133 | } |
1134 | ||
1135 | /************************************************************************** | |
1136 | * | |
1137 | * NIC startup/shutdown | |
1138 | * | |
1139 | *************************************************************************/ | |
1140 | ||
1141 | static int efx_probe_all(struct efx_nic *efx) | |
1142 | { | |
1143 | struct efx_channel *channel; | |
1144 | int rc; | |
1145 | ||
1146 | /* Create NIC */ | |
1147 | rc = efx_probe_nic(efx); | |
1148 | if (rc) { | |
1149 | EFX_ERR(efx, "failed to create NIC\n"); | |
1150 | goto fail1; | |
1151 | } | |
1152 | ||
1153 | /* Create port */ | |
1154 | rc = efx_probe_port(efx); | |
1155 | if (rc) { | |
1156 | EFX_ERR(efx, "failed to create port\n"); | |
1157 | goto fail2; | |
1158 | } | |
1159 | ||
1160 | /* Create channels */ | |
1161 | efx_for_each_channel(channel, efx) { | |
1162 | rc = efx_probe_channel(channel); | |
1163 | if (rc) { | |
1164 | EFX_ERR(efx, "failed to create channel %d\n", | |
1165 | channel->channel); | |
1166 | goto fail3; | |
1167 | } | |
1168 | } | |
56536e9c | 1169 | efx_set_channel_names(efx); |
8ceee660 BH |
1170 | |
1171 | return 0; | |
1172 | ||
1173 | fail3: | |
1174 | efx_for_each_channel(channel, efx) | |
1175 | efx_remove_channel(channel); | |
1176 | efx_remove_port(efx); | |
1177 | fail2: | |
1178 | efx_remove_nic(efx); | |
1179 | fail1: | |
1180 | return rc; | |
1181 | } | |
1182 | ||
1183 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1184 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1185 | * and ensures that the port is scheduled to be reconfigured. | |
1186 | * This function is safe to call multiple times when the NIC is in any | |
1187 | * state. */ | |
1188 | static void efx_start_all(struct efx_nic *efx) | |
1189 | { | |
1190 | struct efx_channel *channel; | |
1191 | ||
1192 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1193 | ||
1194 | /* Check that it is appropriate to restart the interface. All | |
1195 | * of these flags are safe to read under just the rtnl lock */ | |
1196 | if (efx->port_enabled) | |
1197 | return; | |
1198 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1199 | return; | |
55668611 | 1200 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1201 | return; |
1202 | ||
1203 | /* Mark the port as enabled so port reconfigurations can start, then | |
1204 | * restart the transmit interface early so the watchdog timer stops */ | |
1205 | efx_start_port(efx); | |
8ceee660 | 1206 | |
a4900ac9 BH |
1207 | efx_for_each_channel(channel, efx) { |
1208 | if (efx_dev_registered(efx)) | |
1209 | efx_wake_queue(channel); | |
8ceee660 | 1210 | efx_start_channel(channel); |
a4900ac9 | 1211 | } |
8ceee660 | 1212 | |
152b6a62 | 1213 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1214 | |
8880f4ec BH |
1215 | /* Switch to event based MCDI completions after enabling interrupts. |
1216 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1217 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1218 | * reset_pending [modified from an atomic context], we instead guarantee | |
1219 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1220 | efx_mcdi_mode_event(efx); | |
1221 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1222 | efx_mcdi_mode_poll(efx); | |
1223 | ||
78c1f0a0 SH |
1224 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1225 | * event driven), we have to poll the PHY because after an event queue | |
1226 | * flush, we could have a missed a link state change */ | |
1227 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1228 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1229 | efx_monitor_interval); | |
78c1f0a0 SH |
1230 | } else { |
1231 | mutex_lock(&efx->mac_lock); | |
1232 | if (efx->phy_op->poll(efx)) | |
1233 | efx_link_status_changed(efx); | |
1234 | mutex_unlock(&efx->mac_lock); | |
1235 | } | |
55edc6e6 | 1236 | |
ef2b90ee | 1237 | efx->type->start_stats(efx); |
8ceee660 BH |
1238 | } |
1239 | ||
1240 | /* Flush all delayed work. Should only be called when no more delayed work | |
1241 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1242 | * since we're holding the rtnl_lock at this point. */ | |
1243 | static void efx_flush_all(struct efx_nic *efx) | |
1244 | { | |
1245 | struct efx_rx_queue *rx_queue; | |
1246 | ||
1247 | /* Make sure the hardware monitor is stopped */ | |
1248 | cancel_delayed_work_sync(&efx->monitor_work); | |
1249 | ||
1250 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1251 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1252 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1253 | |
1254 | /* Stop scheduled port reconfigurations */ | |
766ca0fa | 1255 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1256 | } |
1257 | ||
1258 | /* Quiesce hardware and software without bringing the link down. | |
1259 | * Safe to call multiple times, when the nic and interface is in any | |
1260 | * state. The caller is guaranteed to subsequently be in a position | |
1261 | * to modify any hardware and software state they see fit without | |
1262 | * taking locks. */ | |
1263 | static void efx_stop_all(struct efx_nic *efx) | |
1264 | { | |
1265 | struct efx_channel *channel; | |
1266 | ||
1267 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1268 | ||
1269 | /* port_enabled can be read safely under the rtnl lock */ | |
1270 | if (!efx->port_enabled) | |
1271 | return; | |
1272 | ||
ef2b90ee | 1273 | efx->type->stop_stats(efx); |
55edc6e6 | 1274 | |
8880f4ec BH |
1275 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1276 | efx_mcdi_mode_poll(efx); | |
1277 | ||
8ceee660 | 1278 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1279 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
1280 | if (efx->legacy_irq) |
1281 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1282 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1283 | if (channel->irq) |
1284 | synchronize_irq(channel->irq); | |
b3475645 | 1285 | } |
8ceee660 BH |
1286 | |
1287 | /* Stop all NAPI processing and synchronous rx refills */ | |
1288 | efx_for_each_channel(channel, efx) | |
1289 | efx_stop_channel(channel); | |
1290 | ||
1291 | /* Stop all asynchronous port reconfigurations. Since all | |
1292 | * event processing has already been stopped, there is no | |
1293 | * window to loose phy events */ | |
1294 | efx_stop_port(efx); | |
1295 | ||
fdaa9aed | 1296 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1297 | efx_flush_all(efx); |
1298 | ||
8ceee660 BH |
1299 | /* Stop the kernel transmit interface late, so the watchdog |
1300 | * timer isn't ticking over the flush */ | |
55668611 | 1301 | if (efx_dev_registered(efx)) { |
a4900ac9 BH |
1302 | struct efx_channel *channel; |
1303 | efx_for_each_channel(channel, efx) | |
1304 | efx_stop_queue(channel); | |
8ceee660 BH |
1305 | netif_tx_lock_bh(efx->net_dev); |
1306 | netif_tx_unlock_bh(efx->net_dev); | |
1307 | } | |
1308 | } | |
1309 | ||
1310 | static void efx_remove_all(struct efx_nic *efx) | |
1311 | { | |
1312 | struct efx_channel *channel; | |
1313 | ||
1314 | efx_for_each_channel(channel, efx) | |
1315 | efx_remove_channel(channel); | |
1316 | efx_remove_port(efx); | |
1317 | efx_remove_nic(efx); | |
1318 | } | |
1319 | ||
8ceee660 BH |
1320 | /************************************************************************** |
1321 | * | |
1322 | * Interrupt moderation | |
1323 | * | |
1324 | **************************************************************************/ | |
1325 | ||
0d86ebd8 BH |
1326 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1327 | { | |
1328 | if (usecs <= 0) | |
1329 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1330 | if (usecs < resolution) | |
1331 | return 1; /* never round down to 0 */ | |
1332 | return usecs / resolution; | |
1333 | } | |
1334 | ||
8ceee660 | 1335 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1336 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1337 | bool rx_adaptive) | |
8ceee660 BH |
1338 | { |
1339 | struct efx_tx_queue *tx_queue; | |
1340 | struct efx_rx_queue *rx_queue; | |
152b6a62 BH |
1341 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1342 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1343 | |
1344 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1345 | ||
1346 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1347 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1348 | |
6fb70fd1 | 1349 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1350 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1351 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1352 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1353 | } |
1354 | ||
1355 | /************************************************************************** | |
1356 | * | |
1357 | * Hardware monitor | |
1358 | * | |
1359 | **************************************************************************/ | |
1360 | ||
1361 | /* Run periodically off the general workqueue. Serialised against | |
1362 | * efx_reconfigure_port via the mac_lock */ | |
1363 | static void efx_monitor(struct work_struct *data) | |
1364 | { | |
1365 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1366 | monitor_work.work); | |
8ceee660 BH |
1367 | |
1368 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1369 | raw_smp_processor_id()); | |
ef2b90ee | 1370 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1371 | |
8ceee660 BH |
1372 | /* If the mac_lock is already held then it is likely a port |
1373 | * reconfiguration is already in place, which will likely do | |
1374 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1375 | if (!mutex_trylock(&efx->mac_lock)) |
1376 | goto out_requeue; | |
1377 | if (!efx->port_enabled) | |
1378 | goto out_unlock; | |
ef2b90ee | 1379 | efx->type->monitor(efx); |
8ceee660 | 1380 | |
766ca0fa | 1381 | out_unlock: |
8ceee660 | 1382 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1383 | out_requeue: |
8ceee660 BH |
1384 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1385 | efx_monitor_interval); | |
1386 | } | |
1387 | ||
1388 | /************************************************************************** | |
1389 | * | |
1390 | * ioctls | |
1391 | * | |
1392 | *************************************************************************/ | |
1393 | ||
1394 | /* Net device ioctl | |
1395 | * Context: process, rtnl_lock() held. | |
1396 | */ | |
1397 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1398 | { | |
767e468c | 1399 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1400 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1401 | |
1402 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1403 | ||
68e7f45e BH |
1404 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1405 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1406 | (data->phy_id & 0xfc00) == 0x0400) | |
1407 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1408 | ||
1409 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1410 | } |
1411 | ||
1412 | /************************************************************************** | |
1413 | * | |
1414 | * NAPI interface | |
1415 | * | |
1416 | **************************************************************************/ | |
1417 | ||
1418 | static int efx_init_napi(struct efx_nic *efx) | |
1419 | { | |
1420 | struct efx_channel *channel; | |
8ceee660 BH |
1421 | |
1422 | efx_for_each_channel(channel, efx) { | |
1423 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1424 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1425 | efx_poll, napi_weight); | |
8ceee660 BH |
1426 | } |
1427 | return 0; | |
8ceee660 BH |
1428 | } |
1429 | ||
1430 | static void efx_fini_napi(struct efx_nic *efx) | |
1431 | { | |
1432 | struct efx_channel *channel; | |
1433 | ||
1434 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1435 | if (channel->napi_dev) |
1436 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1437 | channel->napi_dev = NULL; |
1438 | } | |
1439 | } | |
1440 | ||
1441 | /************************************************************************** | |
1442 | * | |
1443 | * Kernel netpoll interface | |
1444 | * | |
1445 | *************************************************************************/ | |
1446 | ||
1447 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1448 | ||
1449 | /* Although in the common case interrupts will be disabled, this is not | |
1450 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1451 | * so no locking is required. | |
1452 | */ | |
1453 | static void efx_netpoll(struct net_device *net_dev) | |
1454 | { | |
767e468c | 1455 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1456 | struct efx_channel *channel; |
1457 | ||
64ee3120 | 1458 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1459 | efx_schedule_channel(channel); |
1460 | } | |
1461 | ||
1462 | #endif | |
1463 | ||
1464 | /************************************************************************** | |
1465 | * | |
1466 | * Kernel net device interface | |
1467 | * | |
1468 | *************************************************************************/ | |
1469 | ||
1470 | /* Context: process, rtnl_lock() held. */ | |
1471 | static int efx_net_open(struct net_device *net_dev) | |
1472 | { | |
767e468c | 1473 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1474 | EFX_ASSERT_RESET_SERIALISED(efx); |
1475 | ||
1476 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1477 | raw_smp_processor_id()); | |
1478 | ||
f4bd954e BH |
1479 | if (efx->state == STATE_DISABLED) |
1480 | return -EIO; | |
f8b87c17 BH |
1481 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1482 | return -EBUSY; | |
8880f4ec BH |
1483 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1484 | return -EIO; | |
f8b87c17 | 1485 | |
78c1f0a0 SH |
1486 | /* Notify the kernel of the link state polled during driver load, |
1487 | * before the monitor starts running */ | |
1488 | efx_link_status_changed(efx); | |
1489 | ||
8ceee660 BH |
1490 | efx_start_all(efx); |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | /* Context: process, rtnl_lock() held. | |
1495 | * Note that the kernel will ignore our return code; this method | |
1496 | * should really be a void. | |
1497 | */ | |
1498 | static int efx_net_stop(struct net_device *net_dev) | |
1499 | { | |
767e468c | 1500 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1501 | |
1502 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1503 | raw_smp_processor_id()); | |
1504 | ||
f4bd954e BH |
1505 | if (efx->state != STATE_DISABLED) { |
1506 | /* Stop the device and flush all the channels */ | |
1507 | efx_stop_all(efx); | |
1508 | efx_fini_channels(efx); | |
1509 | efx_init_channels(efx); | |
1510 | } | |
8ceee660 BH |
1511 | |
1512 | return 0; | |
1513 | } | |
1514 | ||
5b9e207c | 1515 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1516 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1517 | { | |
767e468c | 1518 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1519 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1520 | struct net_device_stats *stats = &net_dev->stats; | |
1521 | ||
55edc6e6 | 1522 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1523 | efx->type->update_stats(efx); |
55edc6e6 | 1524 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1525 | |
1526 | stats->rx_packets = mac_stats->rx_packets; | |
1527 | stats->tx_packets = mac_stats->tx_packets; | |
1528 | stats->rx_bytes = mac_stats->rx_bytes; | |
1529 | stats->tx_bytes = mac_stats->tx_bytes; | |
1530 | stats->multicast = mac_stats->rx_multicast; | |
1531 | stats->collisions = mac_stats->tx_collision; | |
1532 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1533 | mac_stats->rx_length_error); | |
1534 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1535 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1536 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1537 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1538 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1539 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1540 | ||
1541 | stats->rx_errors = (stats->rx_length_errors + | |
1542 | stats->rx_over_errors + | |
1543 | stats->rx_crc_errors + | |
1544 | stats->rx_frame_errors + | |
1545 | stats->rx_fifo_errors + | |
1546 | stats->rx_missed_errors + | |
1547 | mac_stats->rx_symbol_error); | |
1548 | stats->tx_errors = (stats->tx_window_errors + | |
1549 | mac_stats->tx_bad); | |
1550 | ||
1551 | return stats; | |
1552 | } | |
1553 | ||
1554 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1555 | static void efx_watchdog(struct net_device *net_dev) | |
1556 | { | |
767e468c | 1557 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1558 | |
a4900ac9 BH |
1559 | EFX_ERR(efx, "TX stuck with port_enabled=%d: resetting channels\n", |
1560 | efx->port_enabled); | |
8ceee660 | 1561 | |
739bb23d | 1562 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1563 | } |
1564 | ||
1565 | ||
1566 | /* Context: process, rtnl_lock() held. */ | |
1567 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1568 | { | |
767e468c | 1569 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1570 | int rc = 0; |
1571 | ||
1572 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1573 | ||
1574 | if (new_mtu > EFX_MAX_MTU) | |
1575 | return -EINVAL; | |
1576 | ||
1577 | efx_stop_all(efx); | |
1578 | ||
1579 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1580 | ||
1581 | efx_fini_channels(efx); | |
d3245b28 BH |
1582 | |
1583 | mutex_lock(&efx->mac_lock); | |
1584 | /* Reconfigure the MAC before enabling the dma queues so that | |
1585 | * the RX buffers don't overflow */ | |
8ceee660 | 1586 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1587 | efx->mac_op->reconfigure(efx); |
1588 | mutex_unlock(&efx->mac_lock); | |
1589 | ||
bc3c90a2 | 1590 | efx_init_channels(efx); |
8ceee660 BH |
1591 | |
1592 | efx_start_all(efx); | |
1593 | return rc; | |
8ceee660 BH |
1594 | } |
1595 | ||
1596 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1597 | { | |
767e468c | 1598 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1599 | struct sockaddr *addr = data; |
1600 | char *new_addr = addr->sa_data; | |
1601 | ||
1602 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1603 | ||
1604 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1605 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1606 | new_addr); | |
8ceee660 BH |
1607 | return -EINVAL; |
1608 | } | |
1609 | ||
1610 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1611 | ||
1612 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1613 | mutex_lock(&efx->mac_lock); |
1614 | efx->mac_op->reconfigure(efx); | |
1615 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1616 | |
1617 | return 0; | |
1618 | } | |
1619 | ||
a816f75a | 1620 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1621 | static void efx_set_multicast_list(struct net_device *net_dev) |
1622 | { | |
767e468c | 1623 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1624 | struct netdev_hw_addr *ha; |
8ceee660 | 1625 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1626 | u32 crc; |
1627 | int bit; | |
8ceee660 | 1628 | |
8be4f3e6 | 1629 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1630 | |
1631 | /* Build multicast hash table */ | |
8be4f3e6 | 1632 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1633 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1634 | } else { | |
1635 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1636 | netdev_for_each_mc_addr(ha, net_dev) { |
1637 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1638 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1639 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1640 | } |
8ceee660 | 1641 | |
8be4f3e6 BH |
1642 | /* Broadcast packets go through the multicast hash filter. |
1643 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1644 | * so we always add bit 0xff to the mask. | |
1645 | */ | |
1646 | set_bit_le(0xff, mc_hash->byte); | |
1647 | } | |
a816f75a | 1648 | |
8be4f3e6 BH |
1649 | if (efx->port_enabled) |
1650 | queue_work(efx->workqueue, &efx->mac_work); | |
1651 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1652 | } |
1653 | ||
c3ecb9f3 SH |
1654 | static const struct net_device_ops efx_netdev_ops = { |
1655 | .ndo_open = efx_net_open, | |
1656 | .ndo_stop = efx_net_stop, | |
1657 | .ndo_get_stats = efx_net_stats, | |
1658 | .ndo_tx_timeout = efx_watchdog, | |
1659 | .ndo_start_xmit = efx_hard_start_xmit, | |
1660 | .ndo_validate_addr = eth_validate_addr, | |
1661 | .ndo_do_ioctl = efx_ioctl, | |
1662 | .ndo_change_mtu = efx_change_mtu, | |
1663 | .ndo_set_mac_address = efx_set_mac_address, | |
1664 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1665 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1666 | .ndo_poll_controller = efx_netpoll, | |
1667 | #endif | |
1668 | }; | |
1669 | ||
7dde596e BH |
1670 | static void efx_update_name(struct efx_nic *efx) |
1671 | { | |
1672 | strcpy(efx->name, efx->net_dev->name); | |
1673 | efx_mtd_rename(efx); | |
1674 | efx_set_channel_names(efx); | |
1675 | } | |
1676 | ||
8ceee660 BH |
1677 | static int efx_netdev_event(struct notifier_block *this, |
1678 | unsigned long event, void *ptr) | |
1679 | { | |
d3208b5e | 1680 | struct net_device *net_dev = ptr; |
8ceee660 | 1681 | |
7dde596e BH |
1682 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1683 | event == NETDEV_CHANGENAME) | |
1684 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1685 | |
1686 | return NOTIFY_DONE; | |
1687 | } | |
1688 | ||
1689 | static struct notifier_block efx_netdev_notifier = { | |
1690 | .notifier_call = efx_netdev_event, | |
1691 | }; | |
1692 | ||
06d5e193 BH |
1693 | static ssize_t |
1694 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1695 | { | |
1696 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1697 | return sprintf(buf, "%d\n", efx->phy_type); | |
1698 | } | |
1699 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1700 | ||
8ceee660 BH |
1701 | static int efx_register_netdev(struct efx_nic *efx) |
1702 | { | |
1703 | struct net_device *net_dev = efx->net_dev; | |
1704 | int rc; | |
1705 | ||
1706 | net_dev->watchdog_timeo = 5 * HZ; | |
1707 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1708 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1709 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1710 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1711 | ||
8ceee660 | 1712 | /* Clear MAC statistics */ |
177dfcd8 | 1713 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1714 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1715 | ||
7dde596e | 1716 | rtnl_lock(); |
aed0628d BH |
1717 | |
1718 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1719 | if (rc < 0) | |
1720 | goto fail_locked; | |
7dde596e | 1721 | efx_update_name(efx); |
aed0628d BH |
1722 | |
1723 | rc = register_netdevice(net_dev); | |
1724 | if (rc) | |
1725 | goto fail_locked; | |
1726 | ||
1727 | /* Always start with carrier off; PHY events will detect the link */ | |
1728 | netif_carrier_off(efx->net_dev); | |
1729 | ||
7dde596e | 1730 | rtnl_unlock(); |
8ceee660 | 1731 | |
06d5e193 BH |
1732 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1733 | if (rc) { | |
1734 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1735 | goto fail_registered; | |
1736 | } | |
1737 | ||
8ceee660 | 1738 | return 0; |
06d5e193 | 1739 | |
aed0628d BH |
1740 | fail_locked: |
1741 | rtnl_unlock(); | |
1742 | EFX_ERR(efx, "could not register net dev\n"); | |
1743 | return rc; | |
1744 | ||
06d5e193 BH |
1745 | fail_registered: |
1746 | unregister_netdev(net_dev); | |
1747 | return rc; | |
8ceee660 BH |
1748 | } |
1749 | ||
1750 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1751 | { | |
1752 | struct efx_tx_queue *tx_queue; | |
1753 | ||
1754 | if (!efx->net_dev) | |
1755 | return; | |
1756 | ||
767e468c | 1757 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1758 | |
1759 | /* Free up any skbs still remaining. This has to happen before | |
1760 | * we try to unregister the netdev as running their destructors | |
1761 | * may be needed to get the device ref. count to 0. */ | |
1762 | efx_for_each_tx_queue(tx_queue, efx) | |
1763 | efx_release_tx_buffers(tx_queue); | |
1764 | ||
55668611 | 1765 | if (efx_dev_registered(efx)) { |
8ceee660 | 1766 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1767 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1768 | unregister_netdev(efx->net_dev); |
1769 | } | |
1770 | } | |
1771 | ||
1772 | /************************************************************************** | |
1773 | * | |
1774 | * Device reset and suspend | |
1775 | * | |
1776 | **************************************************************************/ | |
1777 | ||
2467ca46 BH |
1778 | /* Tears down the entire software state and most of the hardware state |
1779 | * before reset. */ | |
d3245b28 | 1780 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1781 | { |
8ceee660 BH |
1782 | EFX_ASSERT_RESET_SERIALISED(efx); |
1783 | ||
2467ca46 BH |
1784 | efx_stop_all(efx); |
1785 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1786 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1787 | |
8ceee660 | 1788 | efx_fini_channels(efx); |
4b988280 SH |
1789 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1790 | efx->phy_op->fini(efx); | |
ef2b90ee | 1791 | efx->type->fini(efx); |
8ceee660 BH |
1792 | } |
1793 | ||
2467ca46 BH |
1794 | /* This function will always ensure that the locks acquired in |
1795 | * efx_reset_down() are released. A failure return code indicates | |
1796 | * that we were unable to reinitialise the hardware, and the | |
1797 | * driver should be disabled. If ok is false, then the rx and tx | |
1798 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 1799 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
1800 | { |
1801 | int rc; | |
1802 | ||
2467ca46 | 1803 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1804 | |
ef2b90ee | 1805 | rc = efx->type->init(efx); |
8ceee660 | 1806 | if (rc) { |
2467ca46 | 1807 | EFX_ERR(efx, "failed to initialise NIC\n"); |
eb9f6744 | 1808 | goto fail; |
8ceee660 BH |
1809 | } |
1810 | ||
eb9f6744 BH |
1811 | if (!ok) |
1812 | goto fail; | |
1813 | ||
4b988280 | 1814 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
1815 | rc = efx->phy_op->init(efx); |
1816 | if (rc) | |
1817 | goto fail; | |
1818 | if (efx->phy_op->reconfigure(efx)) | |
1819 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
4b988280 SH |
1820 | } |
1821 | ||
eb9f6744 | 1822 | efx->mac_op->reconfigure(efx); |
8ceee660 | 1823 | |
eb9f6744 BH |
1824 | efx_init_channels(efx); |
1825 | ||
1826 | mutex_unlock(&efx->spi_lock); | |
1827 | mutex_unlock(&efx->mac_lock); | |
1828 | ||
1829 | efx_start_all(efx); | |
1830 | ||
1831 | return 0; | |
1832 | ||
1833 | fail: | |
1834 | efx->port_initialized = false; | |
2467ca46 | 1835 | |
f4150724 | 1836 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1837 | mutex_unlock(&efx->mac_lock); |
1838 | ||
8ceee660 BH |
1839 | return rc; |
1840 | } | |
1841 | ||
eb9f6744 BH |
1842 | /* Reset the NIC using the specified method. Note that the reset may |
1843 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 1844 | * |
eb9f6744 | 1845 | * Caller must hold the rtnl_lock. |
8ceee660 | 1846 | */ |
eb9f6744 | 1847 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1848 | { |
eb9f6744 BH |
1849 | int rc, rc2; |
1850 | bool disabled; | |
8ceee660 | 1851 | |
c459302d | 1852 | EFX_INFO(efx, "resetting (%s)\n", RESET_TYPE(method)); |
8ceee660 | 1853 | |
d3245b28 | 1854 | efx_reset_down(efx, method); |
8ceee660 | 1855 | |
ef2b90ee | 1856 | rc = efx->type->reset(efx, method); |
8ceee660 BH |
1857 | if (rc) { |
1858 | EFX_ERR(efx, "failed to reset hardware\n"); | |
eb9f6744 | 1859 | goto out; |
8ceee660 BH |
1860 | } |
1861 | ||
1862 | /* Allow resets to be rescheduled. */ | |
1863 | efx->reset_pending = RESET_TYPE_NONE; | |
1864 | ||
1865 | /* Reinitialise bus-mastering, which may have been turned off before | |
1866 | * the reset was scheduled. This is still appropriate, even in the | |
1867 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1868 | * can respond to requests. */ | |
1869 | pci_set_master(efx->pci_dev); | |
1870 | ||
eb9f6744 | 1871 | out: |
8ceee660 | 1872 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
1873 | disabled = rc || method == RESET_TYPE_DISABLE; |
1874 | rc2 = efx_reset_up(efx, method, !disabled); | |
1875 | if (rc2) { | |
1876 | disabled = true; | |
1877 | if (!rc) | |
1878 | rc = rc2; | |
8ceee660 BH |
1879 | } |
1880 | ||
eb9f6744 | 1881 | if (disabled) { |
f49a4589 | 1882 | dev_close(efx->net_dev); |
f4bd954e BH |
1883 | EFX_ERR(efx, "has been disabled\n"); |
1884 | efx->state = STATE_DISABLED; | |
f4bd954e BH |
1885 | } else { |
1886 | EFX_LOG(efx, "reset complete\n"); | |
1887 | } | |
8ceee660 BH |
1888 | return rc; |
1889 | } | |
1890 | ||
1891 | /* The worker thread exists so that code that cannot sleep can | |
1892 | * schedule a reset for later. | |
1893 | */ | |
1894 | static void efx_reset_work(struct work_struct *data) | |
1895 | { | |
eb9f6744 | 1896 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 1897 | |
319ba649 SH |
1898 | if (efx->reset_pending == RESET_TYPE_NONE) |
1899 | return; | |
1900 | ||
eb9f6744 BH |
1901 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
1902 | * flag set so that efx_pci_probe_main will be retried */ | |
1903 | if (efx->state != STATE_RUNNING) { | |
1904 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1905 | return; | |
1906 | } | |
1907 | ||
1908 | rtnl_lock(); | |
f49a4589 | 1909 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 1910 | rtnl_unlock(); |
8ceee660 BH |
1911 | } |
1912 | ||
1913 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1914 | { | |
1915 | enum reset_type method; | |
1916 | ||
1917 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1918 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1919 | return; | |
1920 | } | |
1921 | ||
1922 | switch (type) { | |
1923 | case RESET_TYPE_INVISIBLE: | |
1924 | case RESET_TYPE_ALL: | |
1925 | case RESET_TYPE_WORLD: | |
1926 | case RESET_TYPE_DISABLE: | |
1927 | method = type; | |
1928 | break; | |
1929 | case RESET_TYPE_RX_RECOVERY: | |
1930 | case RESET_TYPE_RX_DESC_FETCH: | |
1931 | case RESET_TYPE_TX_DESC_FETCH: | |
1932 | case RESET_TYPE_TX_SKIP: | |
1933 | method = RESET_TYPE_INVISIBLE; | |
1934 | break; | |
8880f4ec | 1935 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
1936 | default: |
1937 | method = RESET_TYPE_ALL; | |
1938 | break; | |
1939 | } | |
1940 | ||
1941 | if (method != type) | |
c459302d BH |
1942 | EFX_LOG(efx, "scheduling %s reset for %s\n", |
1943 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 1944 | else |
c459302d | 1945 | EFX_LOG(efx, "scheduling %s reset\n", RESET_TYPE(method)); |
8ceee660 BH |
1946 | |
1947 | efx->reset_pending = method; | |
1948 | ||
8880f4ec BH |
1949 | /* efx_process_channel() will no longer read events once a |
1950 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
1951 | efx_mcdi_mode_poll(efx); | |
1952 | ||
1ab00629 | 1953 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1954 | } |
1955 | ||
1956 | /************************************************************************** | |
1957 | * | |
1958 | * List of NICs we support | |
1959 | * | |
1960 | **************************************************************************/ | |
1961 | ||
1962 | /* PCI device ID table */ | |
a3aa1884 | 1963 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 1964 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 1965 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 1966 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 1967 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
1968 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
1969 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
1970 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
1971 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
1972 | {0} /* end of list */ |
1973 | }; | |
1974 | ||
1975 | /************************************************************************** | |
1976 | * | |
3759433d | 1977 | * Dummy PHY/MAC operations |
8ceee660 | 1978 | * |
01aad7b6 | 1979 | * Can be used for some unimplemented operations |
8ceee660 BH |
1980 | * Needed so all function pointers are valid and do not have to be tested |
1981 | * before use | |
1982 | * | |
1983 | **************************************************************************/ | |
1984 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1985 | { | |
1986 | return 0; | |
1987 | } | |
1988 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
1989 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1990 | { | |
1991 | } | |
fdaa9aed SH |
1992 | bool efx_port_dummy_op_poll(struct efx_nic *efx) |
1993 | { | |
1994 | return false; | |
1995 | } | |
8ceee660 BH |
1996 | |
1997 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1998 | .init = efx_port_dummy_op_int, | |
d3245b28 | 1999 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2000 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2001 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2002 | }; |
2003 | ||
8ceee660 BH |
2004 | /************************************************************************** |
2005 | * | |
2006 | * Data housekeeping | |
2007 | * | |
2008 | **************************************************************************/ | |
2009 | ||
2010 | /* This zeroes out and then fills in the invariants in a struct | |
2011 | * efx_nic (including all sub-structures). | |
2012 | */ | |
2013 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
2014 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
2015 | { | |
2016 | struct efx_channel *channel; | |
2017 | struct efx_tx_queue *tx_queue; | |
2018 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 2019 | int i; |
8ceee660 BH |
2020 | |
2021 | /* Initialise common structures */ | |
2022 | memset(efx, 0, sizeof(*efx)); | |
2023 | spin_lock_init(&efx->biu_lock); | |
ab867461 | 2024 | mutex_init(&efx->mdio_lock); |
f4150724 | 2025 | mutex_init(&efx->spi_lock); |
76884835 BH |
2026 | #ifdef CONFIG_SFC_MTD |
2027 | INIT_LIST_HEAD(&efx->mtd_list); | |
2028 | #endif | |
8ceee660 BH |
2029 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2030 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2031 | efx->pci_dev = pci_dev; | |
2032 | efx->state = STATE_INIT; | |
2033 | efx->reset_pending = RESET_TYPE_NONE; | |
2034 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2035 | |
2036 | efx->net_dev = net_dev; | |
dc8cfa55 | 2037 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2038 | spin_lock_init(&efx->stats_lock); |
2039 | mutex_init(&efx->mac_lock); | |
b895d73e | 2040 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2041 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2042 | efx->mdio.dev = net_dev; |
766ca0fa | 2043 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2044 | |
2045 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
2046 | channel = &efx->channel[i]; | |
2047 | channel->efx = efx; | |
2048 | channel->channel = i; | |
dc8cfa55 | 2049 | channel->work_pending = false; |
a4900ac9 BH |
2050 | spin_lock_init(&channel->tx_stop_lock); |
2051 | atomic_set(&channel->tx_stop_count, 1); | |
8ceee660 | 2052 | } |
a4900ac9 | 2053 | for (i = 0; i < EFX_MAX_TX_QUEUES; i++) { |
8ceee660 BH |
2054 | tx_queue = &efx->tx_queue[i]; |
2055 | tx_queue->efx = efx; | |
2056 | tx_queue->queue = i; | |
2057 | tx_queue->buffer = NULL; | |
2058 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 2059 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
2060 | } |
2061 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
2062 | rx_queue = &efx->rx_queue[i]; | |
2063 | rx_queue->efx = efx; | |
2064 | rx_queue->queue = i; | |
2065 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
2066 | rx_queue->buffer = NULL; | |
2067 | spin_lock_init(&rx_queue->add_lock); | |
2068 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
2069 | } | |
2070 | ||
2071 | efx->type = type; | |
2072 | ||
8ceee660 | 2073 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
2074 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
2075 | ||
8ceee660 BH |
2076 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2077 | ||
2078 | /* Higher numbered interrupt modes are less capable! */ | |
2079 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2080 | interrupt_mode); | |
2081 | ||
6977dc63 BH |
2082 | /* Would be good to use the net_dev name, but we're too early */ |
2083 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2084 | pci_name(pci_dev)); | |
2085 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2086 | if (!efx->workqueue) |
2087 | return -ENOMEM; | |
8d9853d9 | 2088 | |
8ceee660 | 2089 | return 0; |
8ceee660 BH |
2090 | } |
2091 | ||
2092 | static void efx_fini_struct(struct efx_nic *efx) | |
2093 | { | |
2094 | if (efx->workqueue) { | |
2095 | destroy_workqueue(efx->workqueue); | |
2096 | efx->workqueue = NULL; | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | /************************************************************************** | |
2101 | * | |
2102 | * PCI interface | |
2103 | * | |
2104 | **************************************************************************/ | |
2105 | ||
2106 | /* Main body of final NIC shutdown code | |
2107 | * This is called only at module unload (or hotplug removal). | |
2108 | */ | |
2109 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2110 | { | |
152b6a62 | 2111 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2112 | efx_fini_channels(efx); |
2113 | efx_fini_port(efx); | |
ef2b90ee | 2114 | efx->type->fini(efx); |
8ceee660 BH |
2115 | efx_fini_napi(efx); |
2116 | efx_remove_all(efx); | |
2117 | } | |
2118 | ||
2119 | /* Final NIC shutdown | |
2120 | * This is called only at module unload (or hotplug removal). | |
2121 | */ | |
2122 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2123 | { | |
2124 | struct efx_nic *efx; | |
2125 | ||
2126 | efx = pci_get_drvdata(pci_dev); | |
2127 | if (!efx) | |
2128 | return; | |
2129 | ||
2130 | /* Mark the NIC as fini, then stop the interface */ | |
2131 | rtnl_lock(); | |
2132 | efx->state = STATE_FINI; | |
2133 | dev_close(efx->net_dev); | |
2134 | ||
2135 | /* Allow any queued efx_resets() to complete */ | |
2136 | rtnl_unlock(); | |
2137 | ||
8ceee660 BH |
2138 | efx_unregister_netdev(efx); |
2139 | ||
7dde596e BH |
2140 | efx_mtd_remove(efx); |
2141 | ||
8ceee660 BH |
2142 | /* Wait for any scheduled resets to complete. No more will be |
2143 | * scheduled from this point because efx_stop_all() has been | |
2144 | * called, we are no longer registered with driverlink, and | |
2145 | * the net_device's have been removed. */ | |
1ab00629 | 2146 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2147 | |
2148 | efx_pci_remove_main(efx); | |
2149 | ||
8ceee660 BH |
2150 | efx_fini_io(efx); |
2151 | EFX_LOG(efx, "shutdown successful\n"); | |
2152 | ||
2153 | pci_set_drvdata(pci_dev, NULL); | |
2154 | efx_fini_struct(efx); | |
2155 | free_netdev(efx->net_dev); | |
2156 | }; | |
2157 | ||
2158 | /* Main body of NIC initialisation | |
2159 | * This is called at module load (or hotplug insertion, theoretically). | |
2160 | */ | |
2161 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2162 | { | |
2163 | int rc; | |
2164 | ||
2165 | /* Do start-of-day initialisation */ | |
2166 | rc = efx_probe_all(efx); | |
2167 | if (rc) | |
2168 | goto fail1; | |
2169 | ||
2170 | rc = efx_init_napi(efx); | |
2171 | if (rc) | |
2172 | goto fail2; | |
2173 | ||
ef2b90ee | 2174 | rc = efx->type->init(efx); |
8ceee660 BH |
2175 | if (rc) { |
2176 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
278c0621 | 2177 | goto fail3; |
8ceee660 BH |
2178 | } |
2179 | ||
2180 | rc = efx_init_port(efx); | |
2181 | if (rc) { | |
2182 | EFX_ERR(efx, "failed to initialise port\n"); | |
278c0621 | 2183 | goto fail4; |
8ceee660 BH |
2184 | } |
2185 | ||
bc3c90a2 | 2186 | efx_init_channels(efx); |
8ceee660 | 2187 | |
152b6a62 | 2188 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2189 | if (rc) |
278c0621 | 2190 | goto fail5; |
8ceee660 BH |
2191 | |
2192 | return 0; | |
2193 | ||
278c0621 | 2194 | fail5: |
bc3c90a2 | 2195 | efx_fini_channels(efx); |
8ceee660 | 2196 | efx_fini_port(efx); |
8ceee660 | 2197 | fail4: |
ef2b90ee | 2198 | efx->type->fini(efx); |
8ceee660 BH |
2199 | fail3: |
2200 | efx_fini_napi(efx); | |
2201 | fail2: | |
2202 | efx_remove_all(efx); | |
2203 | fail1: | |
2204 | return rc; | |
2205 | } | |
2206 | ||
2207 | /* NIC initialisation | |
2208 | * | |
2209 | * This is called at module load (or hotplug insertion, | |
2210 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2211 | * sets up and registers the network devices with the kernel and hooks | |
2212 | * the interrupt service routine. It does not prepare the device for | |
2213 | * transmission; this is left to the first time one of the network | |
2214 | * interfaces is brought up (i.e. efx_net_open). | |
2215 | */ | |
2216 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2217 | const struct pci_device_id *entry) | |
2218 | { | |
2219 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2220 | struct net_device *net_dev; | |
2221 | struct efx_nic *efx; | |
2222 | int i, rc; | |
2223 | ||
2224 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
a4900ac9 | 2225 | net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES); |
8ceee660 BH |
2226 | if (!net_dev) |
2227 | return -ENOMEM; | |
c383b537 | 2228 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2229 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2230 | NETIF_F_GRO); | |
738a8f4b BH |
2231 | if (type->offload_features & NETIF_F_V6_CSUM) |
2232 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2233 | /* Mask for features that also apply to VLAN devices */ |
2234 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2235 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2236 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2237 | pci_set_drvdata(pci_dev, efx); |
2238 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2239 | if (rc) | |
2240 | goto fail1; | |
2241 | ||
2242 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2243 | ||
2244 | /* Set up basic I/O (BAR mappings etc) */ | |
2245 | rc = efx_init_io(efx); | |
2246 | if (rc) | |
2247 | goto fail2; | |
2248 | ||
2249 | /* No serialisation is required with the reset path because | |
2250 | * we're in STATE_INIT. */ | |
2251 | for (i = 0; i < 5; i++) { | |
2252 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2253 | |
2254 | /* Serialise against efx_reset(). No more resets will be | |
2255 | * scheduled since efx_stop_all() has been called, and we | |
2256 | * have not and never have been registered with either | |
2257 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2258 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2259 | |
fa402b2e SH |
2260 | if (rc == 0) { |
2261 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2262 | /* If there was a scheduled reset during | |
2263 | * probe, the NIC is probably hosed anyway */ | |
2264 | efx_pci_remove_main(efx); | |
2265 | rc = -EIO; | |
2266 | } else { | |
2267 | break; | |
2268 | } | |
2269 | } | |
2270 | ||
8ceee660 BH |
2271 | /* Retry if a recoverably reset event has been scheduled */ |
2272 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2273 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2274 | goto fail3; | |
2275 | ||
2276 | efx->reset_pending = RESET_TYPE_NONE; | |
2277 | } | |
2278 | ||
2279 | if (rc) { | |
2280 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2281 | goto fail4; | |
2282 | } | |
2283 | ||
55edc6e6 BH |
2284 | /* Switch to the running state before we expose the device to the OS, |
2285 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2286 | efx->state = STATE_RUNNING; |
7dde596e | 2287 | |
8ceee660 BH |
2288 | rc = efx_register_netdev(efx); |
2289 | if (rc) | |
2290 | goto fail5; | |
2291 | ||
2292 | EFX_LOG(efx, "initialisation successful\n"); | |
a5211bb5 BH |
2293 | |
2294 | rtnl_lock(); | |
2295 | efx_mtd_probe(efx); /* allowed to fail */ | |
2296 | rtnl_unlock(); | |
8ceee660 BH |
2297 | return 0; |
2298 | ||
2299 | fail5: | |
2300 | efx_pci_remove_main(efx); | |
2301 | fail4: | |
2302 | fail3: | |
2303 | efx_fini_io(efx); | |
2304 | fail2: | |
2305 | efx_fini_struct(efx); | |
2306 | fail1: | |
5e2a911c | 2307 | WARN_ON(rc > 0); |
8ceee660 BH |
2308 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); |
2309 | free_netdev(net_dev); | |
2310 | return rc; | |
2311 | } | |
2312 | ||
89c758fa BH |
2313 | static int efx_pm_freeze(struct device *dev) |
2314 | { | |
2315 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2316 | ||
2317 | efx->state = STATE_FINI; | |
2318 | ||
2319 | netif_device_detach(efx->net_dev); | |
2320 | ||
2321 | efx_stop_all(efx); | |
2322 | efx_fini_channels(efx); | |
2323 | ||
2324 | return 0; | |
2325 | } | |
2326 | ||
2327 | static int efx_pm_thaw(struct device *dev) | |
2328 | { | |
2329 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2330 | ||
2331 | efx->state = STATE_INIT; | |
2332 | ||
2333 | efx_init_channels(efx); | |
2334 | ||
2335 | mutex_lock(&efx->mac_lock); | |
2336 | efx->phy_op->reconfigure(efx); | |
2337 | mutex_unlock(&efx->mac_lock); | |
2338 | ||
2339 | efx_start_all(efx); | |
2340 | ||
2341 | netif_device_attach(efx->net_dev); | |
2342 | ||
2343 | efx->state = STATE_RUNNING; | |
2344 | ||
2345 | efx->type->resume_wol(efx); | |
2346 | ||
319ba649 SH |
2347 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2348 | queue_work(reset_workqueue, &efx->reset_work); | |
2349 | ||
89c758fa BH |
2350 | return 0; |
2351 | } | |
2352 | ||
2353 | static int efx_pm_poweroff(struct device *dev) | |
2354 | { | |
2355 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2356 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2357 | ||
2358 | efx->type->fini(efx); | |
2359 | ||
2360 | efx->reset_pending = RESET_TYPE_NONE; | |
2361 | ||
2362 | pci_save_state(pci_dev); | |
2363 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2364 | } | |
2365 | ||
2366 | /* Used for both resume and restore */ | |
2367 | static int efx_pm_resume(struct device *dev) | |
2368 | { | |
2369 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2370 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2371 | int rc; | |
2372 | ||
2373 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2374 | if (rc) | |
2375 | return rc; | |
2376 | pci_restore_state(pci_dev); | |
2377 | rc = pci_enable_device(pci_dev); | |
2378 | if (rc) | |
2379 | return rc; | |
2380 | pci_set_master(efx->pci_dev); | |
2381 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2382 | if (rc) | |
2383 | return rc; | |
2384 | rc = efx->type->init(efx); | |
2385 | if (rc) | |
2386 | return rc; | |
2387 | efx_pm_thaw(dev); | |
2388 | return 0; | |
2389 | } | |
2390 | ||
2391 | static int efx_pm_suspend(struct device *dev) | |
2392 | { | |
2393 | int rc; | |
2394 | ||
2395 | efx_pm_freeze(dev); | |
2396 | rc = efx_pm_poweroff(dev); | |
2397 | if (rc) | |
2398 | efx_pm_resume(dev); | |
2399 | return rc; | |
2400 | } | |
2401 | ||
2402 | static struct dev_pm_ops efx_pm_ops = { | |
2403 | .suspend = efx_pm_suspend, | |
2404 | .resume = efx_pm_resume, | |
2405 | .freeze = efx_pm_freeze, | |
2406 | .thaw = efx_pm_thaw, | |
2407 | .poweroff = efx_pm_poweroff, | |
2408 | .restore = efx_pm_resume, | |
2409 | }; | |
2410 | ||
8ceee660 BH |
2411 | static struct pci_driver efx_pci_driver = { |
2412 | .name = EFX_DRIVER_NAME, | |
2413 | .id_table = efx_pci_table, | |
2414 | .probe = efx_pci_probe, | |
2415 | .remove = efx_pci_remove, | |
89c758fa | 2416 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2417 | }; |
2418 | ||
2419 | /************************************************************************** | |
2420 | * | |
2421 | * Kernel module interface | |
2422 | * | |
2423 | *************************************************************************/ | |
2424 | ||
2425 | module_param(interrupt_mode, uint, 0444); | |
2426 | MODULE_PARM_DESC(interrupt_mode, | |
2427 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2428 | ||
2429 | static int __init efx_init_module(void) | |
2430 | { | |
2431 | int rc; | |
2432 | ||
2433 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2434 | ||
2435 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2436 | if (rc) | |
2437 | goto err_notifier; | |
2438 | ||
2439 | refill_workqueue = create_workqueue("sfc_refill"); | |
2440 | if (!refill_workqueue) { | |
2441 | rc = -ENOMEM; | |
2442 | goto err_refill; | |
2443 | } | |
1ab00629 SH |
2444 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2445 | if (!reset_workqueue) { | |
2446 | rc = -ENOMEM; | |
2447 | goto err_reset; | |
2448 | } | |
8ceee660 BH |
2449 | |
2450 | rc = pci_register_driver(&efx_pci_driver); | |
2451 | if (rc < 0) | |
2452 | goto err_pci; | |
2453 | ||
2454 | return 0; | |
2455 | ||
2456 | err_pci: | |
1ab00629 SH |
2457 | destroy_workqueue(reset_workqueue); |
2458 | err_reset: | |
8ceee660 BH |
2459 | destroy_workqueue(refill_workqueue); |
2460 | err_refill: | |
2461 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2462 | err_notifier: | |
2463 | return rc; | |
2464 | } | |
2465 | ||
2466 | static void __exit efx_exit_module(void) | |
2467 | { | |
2468 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2469 | ||
2470 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2471 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2472 | destroy_workqueue(refill_workqueue); |
2473 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2474 | ||
2475 | } | |
2476 | ||
2477 | module_init(efx_init_module); | |
2478 | module_exit(efx_exit_module); | |
2479 | ||
906bb26c BH |
2480 | MODULE_AUTHOR("Solarflare Communications and " |
2481 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2482 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2483 | MODULE_LICENSE("GPL"); | |
2484 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |