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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
5a0e3ad6 | 23 | #include <linux/gfp.h> |
8ceee660 | 24 | #include "net_driver.h" |
8ceee660 BH |
25 | #include "efx.h" |
26 | #include "mdio_10g.h" | |
744093c9 | 27 | #include "nic.h" |
8ceee660 | 28 | |
8880f4ec | 29 | #include "mcdi.h" |
fd371e32 | 30 | #include "workarounds.h" |
8880f4ec | 31 | |
c459302d BH |
32 | /************************************************************************** |
33 | * | |
34 | * Type name strings | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
39 | /* Loopback mode names (see LOOPBACK_MODE()) */ | |
40 | const unsigned int efx_loopback_mode_max = LOOPBACK_MAX; | |
41 | const char *efx_loopback_mode_names[] = { | |
42 | [LOOPBACK_NONE] = "NONE", | |
e58f69f4 | 43 | [LOOPBACK_DATA] = "DATAPATH", |
c459302d BH |
44 | [LOOPBACK_GMAC] = "GMAC", |
45 | [LOOPBACK_XGMII] = "XGMII", | |
46 | [LOOPBACK_XGXS] = "XGXS", | |
47 | [LOOPBACK_XAUI] = "XAUI", | |
e58f69f4 BH |
48 | [LOOPBACK_GMII] = "GMII", |
49 | [LOOPBACK_SGMII] = "SGMII", | |
50 | [LOOPBACK_XGBR] = "XGBR", | |
51 | [LOOPBACK_XFI] = "XFI", | |
52 | [LOOPBACK_XAUI_FAR] = "XAUI_FAR", | |
53 | [LOOPBACK_GMII_FAR] = "GMII_FAR", | |
54 | [LOOPBACK_SGMII_FAR] = "SGMII_FAR", | |
55 | [LOOPBACK_XFI_FAR] = "XFI_FAR", | |
c459302d BH |
56 | [LOOPBACK_GPHY] = "GPHY", |
57 | [LOOPBACK_PHYXS] = "PHYXS", | |
58 | [LOOPBACK_PCS] = "PCS", | |
59 | [LOOPBACK_PMAPMD] = "PMA/PMD", | |
e58f69f4 BH |
60 | [LOOPBACK_XPORT] = "XPORT", |
61 | [LOOPBACK_XGMII_WS] = "XGMII_WS", | |
62 | [LOOPBACK_XAUI_WS] = "XAUI_WS", | |
63 | [LOOPBACK_XAUI_WS_FAR] = "XAUI_WS_FAR", | |
64 | [LOOPBACK_XAUI_WS_NEAR] = "XAUI_WS_NEAR", | |
65 | [LOOPBACK_GMII_WS] = "GMII_WS", | |
66 | [LOOPBACK_XFI_WS] = "XFI_WS", | |
67 | [LOOPBACK_XFI_WS_FAR] = "XFI_WS_FAR", | |
68 | [LOOPBACK_PHYXS_WS] = "PHYXS_WS", | |
c459302d BH |
69 | }; |
70 | ||
71 | /* Interrupt mode names (see INT_MODE())) */ | |
72 | const unsigned int efx_interrupt_mode_max = EFX_INT_MODE_MAX; | |
73 | const char *efx_interrupt_mode_names[] = { | |
74 | [EFX_INT_MODE_MSIX] = "MSI-X", | |
75 | [EFX_INT_MODE_MSI] = "MSI", | |
76 | [EFX_INT_MODE_LEGACY] = "legacy", | |
77 | }; | |
78 | ||
79 | const unsigned int efx_reset_type_max = RESET_TYPE_MAX; | |
80 | const char *efx_reset_type_names[] = { | |
81 | [RESET_TYPE_INVISIBLE] = "INVISIBLE", | |
82 | [RESET_TYPE_ALL] = "ALL", | |
83 | [RESET_TYPE_WORLD] = "WORLD", | |
84 | [RESET_TYPE_DISABLE] = "DISABLE", | |
85 | [RESET_TYPE_TX_WATCHDOG] = "TX_WATCHDOG", | |
86 | [RESET_TYPE_INT_ERROR] = "INT_ERROR", | |
87 | [RESET_TYPE_RX_RECOVERY] = "RX_RECOVERY", | |
88 | [RESET_TYPE_RX_DESC_FETCH] = "RX_DESC_FETCH", | |
89 | [RESET_TYPE_TX_DESC_FETCH] = "TX_DESC_FETCH", | |
90 | [RESET_TYPE_TX_SKIP] = "TX_SKIP", | |
8880f4ec | 91 | [RESET_TYPE_MC_FAILURE] = "MC_FAILURE", |
c459302d BH |
92 | }; |
93 | ||
8ceee660 BH |
94 | #define EFX_MAX_MTU (9 * 1024) |
95 | ||
1ab00629 SH |
96 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
97 | * queued onto this work queue. This is not a per-nic work queue, because | |
98 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
99 | */ | |
100 | static struct workqueue_struct *reset_workqueue; | |
101 | ||
8ceee660 BH |
102 | /************************************************************************** |
103 | * | |
104 | * Configurable values | |
105 | * | |
106 | *************************************************************************/ | |
107 | ||
8ceee660 BH |
108 | /* |
109 | * Use separate channels for TX and RX events | |
110 | * | |
28b581ab NT |
111 | * Set this to 1 to use separate channels for TX and RX. It allows us |
112 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 113 | * |
28b581ab | 114 | * This is only used in MSI-X interrupt mode |
8ceee660 | 115 | */ |
28b581ab | 116 | static unsigned int separate_tx_channels; |
8313aca3 | 117 | module_param(separate_tx_channels, uint, 0444); |
28b581ab NT |
118 | MODULE_PARM_DESC(separate_tx_channels, |
119 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
120 | |
121 | /* This is the weight assigned to each of the (per-channel) virtual | |
122 | * NAPI devices. | |
123 | */ | |
124 | static int napi_weight = 64; | |
125 | ||
126 | /* This is the time (in jiffies) between invocations of the hardware | |
127 | * monitor, which checks for known hardware bugs and resets the | |
128 | * hardware and driver as necessary. | |
129 | */ | |
130 | unsigned int efx_monitor_interval = 1 * HZ; | |
131 | ||
8ceee660 BH |
132 | /* This controls whether or not the driver will initialise devices |
133 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
134 | * such devices will be initialised with a random locally-generated | |
135 | * MAC address. This allows for loading the sfc_mtd driver to | |
136 | * reprogram the flash, even if the flash contents (including the MAC | |
137 | * address) have previously been erased. | |
138 | */ | |
139 | static unsigned int allow_bad_hwaddr; | |
140 | ||
141 | /* Initial interrupt moderation settings. They can be modified after | |
142 | * module load with ethtool. | |
143 | * | |
144 | * The default for RX should strike a balance between increasing the | |
145 | * round-trip latency and reducing overhead. | |
146 | */ | |
147 | static unsigned int rx_irq_mod_usec = 60; | |
148 | ||
149 | /* Initial interrupt moderation settings. They can be modified after | |
150 | * module load with ethtool. | |
151 | * | |
152 | * This default is chosen to ensure that a 10G link does not go idle | |
153 | * while a TX queue is stopped after it has become full. A queue is | |
154 | * restarted when it drops below half full. The time this takes (assuming | |
155 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
156 | * 512 / 3 * 1.2 = 205 usec. | |
157 | */ | |
158 | static unsigned int tx_irq_mod_usec = 150; | |
159 | ||
160 | /* This is the first interrupt mode to try out of: | |
161 | * 0 => MSI-X | |
162 | * 1 => MSI | |
163 | * 2 => legacy | |
164 | */ | |
165 | static unsigned int interrupt_mode; | |
166 | ||
167 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
168 | * i.e. the number of CPUs among which we may distribute simultaneous | |
169 | * interrupt handling. | |
170 | * | |
171 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
172 | * The default (0) means to assign an interrupt to each package (level II cache) | |
173 | */ | |
174 | static unsigned int rss_cpus; | |
175 | module_param(rss_cpus, uint, 0444); | |
176 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
177 | ||
84ae48fe BH |
178 | static int phy_flash_cfg; |
179 | module_param(phy_flash_cfg, int, 0644); | |
180 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
181 | ||
6fb70fd1 BH |
182 | static unsigned irq_adapt_low_thresh = 10000; |
183 | module_param(irq_adapt_low_thresh, uint, 0644); | |
184 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
185 | "Threshold score for reducing IRQ moderation"); | |
186 | ||
187 | static unsigned irq_adapt_high_thresh = 20000; | |
188 | module_param(irq_adapt_high_thresh, uint, 0644); | |
189 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
190 | "Threshold score for increasing IRQ moderation"); | |
191 | ||
62776d03 BH |
192 | static unsigned debug = (NETIF_MSG_DRV | NETIF_MSG_PROBE | |
193 | NETIF_MSG_LINK | NETIF_MSG_IFDOWN | | |
194 | NETIF_MSG_IFUP | NETIF_MSG_RX_ERR | | |
195 | NETIF_MSG_TX_ERR | NETIF_MSG_HW); | |
196 | module_param(debug, uint, 0); | |
197 | MODULE_PARM_DESC(debug, "Bitmapped debugging message enable value"); | |
198 | ||
8ceee660 BH |
199 | /************************************************************************** |
200 | * | |
201 | * Utility functions and prototypes | |
202 | * | |
203 | *************************************************************************/ | |
204 | static void efx_remove_channel(struct efx_channel *channel); | |
205 | static void efx_remove_port(struct efx_nic *efx); | |
206 | static void efx_fini_napi(struct efx_nic *efx); | |
207 | static void efx_fini_channels(struct efx_nic *efx); | |
208 | ||
209 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
210 | do { \ | |
332c1ce9 BH |
211 | if ((efx->state == STATE_RUNNING) || \ |
212 | (efx->state == STATE_DISABLED)) \ | |
8ceee660 BH |
213 | ASSERT_RTNL(); \ |
214 | } while (0) | |
215 | ||
216 | /************************************************************************** | |
217 | * | |
218 | * Event queue processing | |
219 | * | |
220 | *************************************************************************/ | |
221 | ||
222 | /* Process channel's event queue | |
223 | * | |
224 | * This function is responsible for processing the event queue of a | |
225 | * single channel. The caller must guarantee that this function will | |
226 | * never be concurrently called more than once on the same channel, | |
227 | * though different channels may be being processed concurrently. | |
228 | */ | |
fa236e18 | 229 | static int efx_process_channel(struct efx_channel *channel, int budget) |
8ceee660 | 230 | { |
42cbe2d7 | 231 | struct efx_nic *efx = channel->efx; |
fa236e18 | 232 | int spent; |
8ceee660 | 233 | |
42cbe2d7 | 234 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 235 | !channel->enabled)) |
42cbe2d7 | 236 | return 0; |
8ceee660 | 237 | |
fa236e18 BH |
238 | spent = efx_nic_process_eventq(channel, budget); |
239 | if (spent == 0) | |
42cbe2d7 | 240 | return 0; |
8ceee660 BH |
241 | |
242 | /* Deliver last RX packet. */ | |
243 | if (channel->rx_pkt) { | |
244 | __efx_rx_packet(channel, channel->rx_pkt, | |
245 | channel->rx_pkt_csummed); | |
246 | channel->rx_pkt = NULL; | |
247 | } | |
248 | ||
8ceee660 BH |
249 | efx_rx_strategy(channel); |
250 | ||
f7d12cdc | 251 | efx_fast_push_rx_descriptors(efx_channel_get_rx_queue(channel)); |
8ceee660 | 252 | |
fa236e18 | 253 | return spent; |
8ceee660 BH |
254 | } |
255 | ||
256 | /* Mark channel as finished processing | |
257 | * | |
258 | * Note that since we will not receive further interrupts for this | |
259 | * channel before we finish processing and call the eventq_read_ack() | |
260 | * method, there is no need to use the interrupt hold-off timers. | |
261 | */ | |
262 | static inline void efx_channel_processed(struct efx_channel *channel) | |
263 | { | |
5b9e207c BH |
264 | /* The interrupt handler for this channel may set work_pending |
265 | * as soon as we acknowledge the events we've seen. Make sure | |
266 | * it's cleared before then. */ | |
dc8cfa55 | 267 | channel->work_pending = false; |
5b9e207c BH |
268 | smp_wmb(); |
269 | ||
152b6a62 | 270 | efx_nic_eventq_read_ack(channel); |
8ceee660 BH |
271 | } |
272 | ||
273 | /* NAPI poll handler | |
274 | * | |
275 | * NAPI guarantees serialisation of polls of the same device, which | |
276 | * provides the guarantee required by efx_process_channel(). | |
277 | */ | |
278 | static int efx_poll(struct napi_struct *napi, int budget) | |
279 | { | |
280 | struct efx_channel *channel = | |
281 | container_of(napi, struct efx_channel, napi_str); | |
62776d03 | 282 | struct efx_nic *efx = channel->efx; |
fa236e18 | 283 | int spent; |
8ceee660 | 284 | |
62776d03 BH |
285 | netif_vdbg(efx, intr, efx->net_dev, |
286 | "channel %d NAPI poll executing on CPU %d\n", | |
287 | channel->channel, raw_smp_processor_id()); | |
8ceee660 | 288 | |
fa236e18 | 289 | spent = efx_process_channel(channel, budget); |
8ceee660 | 290 | |
fa236e18 | 291 | if (spent < budget) { |
a4900ac9 | 292 | if (channel->channel < efx->n_rx_channels && |
6fb70fd1 BH |
293 | efx->irq_rx_adaptive && |
294 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
295 | if (unlikely(channel->irq_mod_score < |
296 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
297 | if (channel->irq_moderation > 1) { |
298 | channel->irq_moderation -= 1; | |
ef2b90ee | 299 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 300 | } |
6fb70fd1 BH |
301 | } else if (unlikely(channel->irq_mod_score > |
302 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
303 | if (channel->irq_moderation < |
304 | efx->irq_rx_moderation) { | |
305 | channel->irq_moderation += 1; | |
ef2b90ee | 306 | efx->type->push_irq_moderation(channel); |
0d86ebd8 | 307 | } |
6fb70fd1 | 308 | } |
6fb70fd1 BH |
309 | channel->irq_count = 0; |
310 | channel->irq_mod_score = 0; | |
311 | } | |
312 | ||
8ceee660 | 313 | /* There is no race here; although napi_disable() will |
288379f0 | 314 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
315 | * since efx_channel_processed() will have no effect if |
316 | * interrupts have already been disabled. | |
317 | */ | |
288379f0 | 318 | napi_complete(napi); |
8ceee660 BH |
319 | efx_channel_processed(channel); |
320 | } | |
321 | ||
fa236e18 | 322 | return spent; |
8ceee660 BH |
323 | } |
324 | ||
325 | /* Process the eventq of the specified channel immediately on this CPU | |
326 | * | |
327 | * Disable hardware generated interrupts, wait for any existing | |
328 | * processing to finish, then directly poll (and ack ) the eventq. | |
329 | * Finally reenable NAPI and interrupts. | |
330 | * | |
331 | * Since we are touching interrupts the caller should hold the suspend lock | |
332 | */ | |
333 | void efx_process_channel_now(struct efx_channel *channel) | |
334 | { | |
335 | struct efx_nic *efx = channel->efx; | |
336 | ||
8313aca3 | 337 | BUG_ON(channel->channel >= efx->n_channels); |
8ceee660 BH |
338 | BUG_ON(!channel->enabled); |
339 | ||
340 | /* Disable interrupts and wait for ISRs to complete */ | |
152b6a62 | 341 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
342 | if (efx->legacy_irq) |
343 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 344 | if (channel->irq) |
8ceee660 BH |
345 | synchronize_irq(channel->irq); |
346 | ||
347 | /* Wait for any NAPI processing to complete */ | |
348 | napi_disable(&channel->napi_str); | |
349 | ||
350 | /* Poll the channel */ | |
ecc910f5 | 351 | efx_process_channel(channel, channel->eventq_mask + 1); |
8ceee660 BH |
352 | |
353 | /* Ack the eventq. This may cause an interrupt to be generated | |
354 | * when they are reenabled */ | |
355 | efx_channel_processed(channel); | |
356 | ||
357 | napi_enable(&channel->napi_str); | |
152b6a62 | 358 | efx_nic_enable_interrupts(efx); |
8ceee660 BH |
359 | } |
360 | ||
361 | /* Create event queue | |
362 | * Event queue memory allocations are done only once. If the channel | |
363 | * is reset, the memory buffer will be reused; this guards against | |
364 | * errors during channel reset and also simplifies interrupt handling. | |
365 | */ | |
366 | static int efx_probe_eventq(struct efx_channel *channel) | |
367 | { | |
ecc910f5 SH |
368 | struct efx_nic *efx = channel->efx; |
369 | unsigned long entries; | |
370 | ||
62776d03 BH |
371 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
372 | "chan %d create event queue\n", channel->channel); | |
8ceee660 | 373 | |
ecc910f5 SH |
374 | /* Build an event queue with room for one event per tx and rx buffer, |
375 | * plus some extra for link state events and MCDI completions. */ | |
376 | entries = roundup_pow_of_two(efx->rxq_entries + efx->txq_entries + 128); | |
377 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_EVQ_SIZE); | |
378 | channel->eventq_mask = max(entries, EFX_MIN_EVQ_SIZE) - 1; | |
379 | ||
152b6a62 | 380 | return efx_nic_probe_eventq(channel); |
8ceee660 BH |
381 | } |
382 | ||
383 | /* Prepare channel's event queue */ | |
bc3c90a2 | 384 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 | 385 | { |
62776d03 BH |
386 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
387 | "chan %d init event queue\n", channel->channel); | |
8ceee660 BH |
388 | |
389 | channel->eventq_read_ptr = 0; | |
390 | ||
152b6a62 | 391 | efx_nic_init_eventq(channel); |
8ceee660 BH |
392 | } |
393 | ||
394 | static void efx_fini_eventq(struct efx_channel *channel) | |
395 | { | |
62776d03 BH |
396 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
397 | "chan %d fini event queue\n", channel->channel); | |
8ceee660 | 398 | |
152b6a62 | 399 | efx_nic_fini_eventq(channel); |
8ceee660 BH |
400 | } |
401 | ||
402 | static void efx_remove_eventq(struct efx_channel *channel) | |
403 | { | |
62776d03 BH |
404 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
405 | "chan %d remove event queue\n", channel->channel); | |
8ceee660 | 406 | |
152b6a62 | 407 | efx_nic_remove_eventq(channel); |
8ceee660 BH |
408 | } |
409 | ||
410 | /************************************************************************** | |
411 | * | |
412 | * Channel handling | |
413 | * | |
414 | *************************************************************************/ | |
415 | ||
8ceee660 BH |
416 | static int efx_probe_channel(struct efx_channel *channel) |
417 | { | |
418 | struct efx_tx_queue *tx_queue; | |
419 | struct efx_rx_queue *rx_queue; | |
420 | int rc; | |
421 | ||
62776d03 BH |
422 | netif_dbg(channel->efx, probe, channel->efx->net_dev, |
423 | "creating channel %d\n", channel->channel); | |
8ceee660 BH |
424 | |
425 | rc = efx_probe_eventq(channel); | |
426 | if (rc) | |
427 | goto fail1; | |
428 | ||
429 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
430 | rc = efx_probe_tx_queue(tx_queue); | |
431 | if (rc) | |
432 | goto fail2; | |
433 | } | |
434 | ||
435 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
436 | rc = efx_probe_rx_queue(rx_queue); | |
437 | if (rc) | |
438 | goto fail3; | |
439 | } | |
440 | ||
441 | channel->n_rx_frm_trunc = 0; | |
442 | ||
443 | return 0; | |
444 | ||
445 | fail3: | |
446 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
447 | efx_remove_rx_queue(rx_queue); | |
448 | fail2: | |
449 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
450 | efx_remove_tx_queue(tx_queue); | |
451 | fail1: | |
452 | return rc; | |
453 | } | |
454 | ||
455 | ||
56536e9c BH |
456 | static void efx_set_channel_names(struct efx_nic *efx) |
457 | { | |
458 | struct efx_channel *channel; | |
459 | const char *type = ""; | |
460 | int number; | |
461 | ||
462 | efx_for_each_channel(channel, efx) { | |
463 | number = channel->channel; | |
a4900ac9 BH |
464 | if (efx->n_channels > efx->n_rx_channels) { |
465 | if (channel->channel < efx->n_rx_channels) { | |
56536e9c BH |
466 | type = "-rx"; |
467 | } else { | |
468 | type = "-tx"; | |
a4900ac9 | 469 | number -= efx->n_rx_channels; |
56536e9c BH |
470 | } |
471 | } | |
472 | snprintf(channel->name, sizeof(channel->name), | |
473 | "%s%s-%d", efx->name, type, number); | |
474 | } | |
475 | } | |
476 | ||
8ceee660 BH |
477 | /* Channels are shutdown and reinitialised whilst the NIC is running |
478 | * to propagate configuration changes (mtu, checksum offload), or | |
479 | * to clear hardware error conditions | |
480 | */ | |
bc3c90a2 | 481 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
482 | { |
483 | struct efx_tx_queue *tx_queue; | |
484 | struct efx_rx_queue *rx_queue; | |
485 | struct efx_channel *channel; | |
8ceee660 | 486 | |
f7f13b0b BH |
487 | /* Calculate the rx buffer allocation parameters required to |
488 | * support the current MTU, including padding for header | |
489 | * alignment and overruns. | |
490 | */ | |
491 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
492 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
39c9cf07 | 493 | efx->type->rx_buffer_hash_size + |
f7f13b0b | 494 | efx->type->rx_buffer_padding); |
62b330ba SH |
495 | efx->rx_buffer_order = get_order(efx->rx_buffer_len + |
496 | sizeof(struct efx_rx_page_state)); | |
8ceee660 BH |
497 | |
498 | /* Initialise the channels */ | |
499 | efx_for_each_channel(channel, efx) { | |
62776d03 BH |
500 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
501 | "init chan %d\n", channel->channel); | |
8ceee660 | 502 | |
bc3c90a2 | 503 | efx_init_eventq(channel); |
8ceee660 | 504 | |
bc3c90a2 BH |
505 | efx_for_each_channel_tx_queue(tx_queue, channel) |
506 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
507 | |
508 | /* The rx buffer allocation strategy is MTU dependent */ | |
509 | efx_rx_strategy(channel); | |
510 | ||
bc3c90a2 BH |
511 | efx_for_each_channel_rx_queue(rx_queue, channel) |
512 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
513 | |
514 | WARN_ON(channel->rx_pkt != NULL); | |
515 | efx_rx_strategy(channel); | |
516 | } | |
8ceee660 BH |
517 | } |
518 | ||
519 | /* This enables event queue processing and packet transmission. | |
520 | * | |
521 | * Note that this function is not allowed to fail, since that would | |
522 | * introduce too much complexity into the suspend/resume path. | |
523 | */ | |
524 | static void efx_start_channel(struct efx_channel *channel) | |
525 | { | |
526 | struct efx_rx_queue *rx_queue; | |
527 | ||
62776d03 BH |
528 | netif_dbg(channel->efx, ifup, channel->efx->net_dev, |
529 | "starting chan %d\n", channel->channel); | |
8ceee660 | 530 | |
5b9e207c BH |
531 | /* The interrupt handler for this channel may set work_pending |
532 | * as soon as we enable it. Make sure it's cleared before | |
533 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
534 | channel->work_pending = false; |
535 | channel->enabled = true; | |
5b9e207c | 536 | smp_wmb(); |
8ceee660 | 537 | |
90d683af | 538 | /* Fill the queues before enabling NAPI */ |
8ceee660 BH |
539 | efx_for_each_channel_rx_queue(rx_queue, channel) |
540 | efx_fast_push_rx_descriptors(rx_queue); | |
90d683af SH |
541 | |
542 | napi_enable(&channel->napi_str); | |
8ceee660 BH |
543 | } |
544 | ||
545 | /* This disables event queue processing and packet transmission. | |
546 | * This function does not guarantee that all queue processing | |
547 | * (e.g. RX refill) is complete. | |
548 | */ | |
549 | static void efx_stop_channel(struct efx_channel *channel) | |
550 | { | |
8ceee660 BH |
551 | if (!channel->enabled) |
552 | return; | |
553 | ||
62776d03 BH |
554 | netif_dbg(channel->efx, ifdown, channel->efx->net_dev, |
555 | "stop chan %d\n", channel->channel); | |
8ceee660 | 556 | |
dc8cfa55 | 557 | channel->enabled = false; |
8ceee660 | 558 | napi_disable(&channel->napi_str); |
8ceee660 BH |
559 | } |
560 | ||
561 | static void efx_fini_channels(struct efx_nic *efx) | |
562 | { | |
563 | struct efx_channel *channel; | |
564 | struct efx_tx_queue *tx_queue; | |
565 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 566 | int rc; |
8ceee660 BH |
567 | |
568 | EFX_ASSERT_RESET_SERIALISED(efx); | |
569 | BUG_ON(efx->port_enabled); | |
570 | ||
152b6a62 | 571 | rc = efx_nic_flush_queues(efx); |
fd371e32 SH |
572 | if (rc && EFX_WORKAROUND_7803(efx)) { |
573 | /* Schedule a reset to recover from the flush failure. The | |
574 | * descriptor caches reference memory we're about to free, | |
575 | * but falcon_reconfigure_mac_wrapper() won't reconnect | |
576 | * the MACs because of the pending reset. */ | |
62776d03 BH |
577 | netif_err(efx, drv, efx->net_dev, |
578 | "Resetting to recover from flush failure\n"); | |
fd371e32 SH |
579 | efx_schedule_reset(efx, RESET_TYPE_ALL); |
580 | } else if (rc) { | |
62776d03 | 581 | netif_err(efx, drv, efx->net_dev, "failed to flush queues\n"); |
fd371e32 | 582 | } else { |
62776d03 BH |
583 | netif_dbg(efx, drv, efx->net_dev, |
584 | "successfully flushed all queues\n"); | |
fd371e32 | 585 | } |
6bc5d3a9 | 586 | |
8ceee660 | 587 | efx_for_each_channel(channel, efx) { |
62776d03 BH |
588 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
589 | "shut down chan %d\n", channel->channel); | |
8ceee660 BH |
590 | |
591 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
592 | efx_fini_rx_queue(rx_queue); | |
593 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
594 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
595 | efx_fini_eventq(channel); |
596 | } | |
597 | } | |
598 | ||
599 | static void efx_remove_channel(struct efx_channel *channel) | |
600 | { | |
601 | struct efx_tx_queue *tx_queue; | |
602 | struct efx_rx_queue *rx_queue; | |
603 | ||
62776d03 BH |
604 | netif_dbg(channel->efx, drv, channel->efx->net_dev, |
605 | "destroy chan %d\n", channel->channel); | |
8ceee660 BH |
606 | |
607 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
608 | efx_remove_rx_queue(rx_queue); | |
609 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
610 | efx_remove_tx_queue(tx_queue); | |
611 | efx_remove_eventq(channel); | |
8ceee660 BH |
612 | } |
613 | ||
90d683af | 614 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue) |
8ceee660 | 615 | { |
90d683af | 616 | mod_timer(&rx_queue->slow_fill, jiffies + msecs_to_jiffies(100)); |
8ceee660 BH |
617 | } |
618 | ||
619 | /************************************************************************** | |
620 | * | |
621 | * Port handling | |
622 | * | |
623 | **************************************************************************/ | |
624 | ||
625 | /* This ensures that the kernel is kept informed (via | |
626 | * netif_carrier_on/off) of the link status, and also maintains the | |
627 | * link status's stop on the port's TX queue. | |
628 | */ | |
fdaa9aed | 629 | void efx_link_status_changed(struct efx_nic *efx) |
8ceee660 | 630 | { |
eb50c0d6 BH |
631 | struct efx_link_state *link_state = &efx->link_state; |
632 | ||
8ceee660 BH |
633 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
634 | * that no events are triggered between unregister_netdev() and the | |
635 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
636 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
637 | if (!netif_running(efx->net_dev)) | |
638 | return; | |
639 | ||
8c8661e4 BH |
640 | if (efx->port_inhibited) { |
641 | netif_carrier_off(efx->net_dev); | |
642 | return; | |
643 | } | |
644 | ||
eb50c0d6 | 645 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
646 | efx->n_link_state_changes++; |
647 | ||
eb50c0d6 | 648 | if (link_state->up) |
8ceee660 BH |
649 | netif_carrier_on(efx->net_dev); |
650 | else | |
651 | netif_carrier_off(efx->net_dev); | |
652 | } | |
653 | ||
654 | /* Status message for kernel log */ | |
eb50c0d6 | 655 | if (link_state->up) { |
62776d03 BH |
656 | netif_info(efx, link, efx->net_dev, |
657 | "link up at %uMbps %s-duplex (MTU %d)%s\n", | |
658 | link_state->speed, link_state->fd ? "full" : "half", | |
659 | efx->net_dev->mtu, | |
660 | (efx->promiscuous ? " [PROMISC]" : "")); | |
8ceee660 | 661 | } else { |
62776d03 | 662 | netif_info(efx, link, efx->net_dev, "link down\n"); |
8ceee660 BH |
663 | } |
664 | ||
665 | } | |
666 | ||
d3245b28 BH |
667 | void efx_link_set_advertising(struct efx_nic *efx, u32 advertising) |
668 | { | |
669 | efx->link_advertising = advertising; | |
670 | if (advertising) { | |
671 | if (advertising & ADVERTISED_Pause) | |
672 | efx->wanted_fc |= (EFX_FC_TX | EFX_FC_RX); | |
673 | else | |
674 | efx->wanted_fc &= ~(EFX_FC_TX | EFX_FC_RX); | |
675 | if (advertising & ADVERTISED_Asym_Pause) | |
676 | efx->wanted_fc ^= EFX_FC_TX; | |
677 | } | |
678 | } | |
679 | ||
680 | void efx_link_set_wanted_fc(struct efx_nic *efx, enum efx_fc_type wanted_fc) | |
681 | { | |
682 | efx->wanted_fc = wanted_fc; | |
683 | if (efx->link_advertising) { | |
684 | if (wanted_fc & EFX_FC_RX) | |
685 | efx->link_advertising |= (ADVERTISED_Pause | | |
686 | ADVERTISED_Asym_Pause); | |
687 | else | |
688 | efx->link_advertising &= ~(ADVERTISED_Pause | | |
689 | ADVERTISED_Asym_Pause); | |
690 | if (wanted_fc & EFX_FC_TX) | |
691 | efx->link_advertising ^= ADVERTISED_Asym_Pause; | |
692 | } | |
693 | } | |
694 | ||
115122af BH |
695 | static void efx_fini_port(struct efx_nic *efx); |
696 | ||
d3245b28 BH |
697 | /* Push loopback/power/transmit disable settings to the PHY, and reconfigure |
698 | * the MAC appropriately. All other PHY configuration changes are pushed | |
699 | * through phy_op->set_settings(), and pushed asynchronously to the MAC | |
700 | * through efx_monitor(). | |
701 | * | |
702 | * Callers must hold the mac_lock | |
703 | */ | |
704 | int __efx_reconfigure_port(struct efx_nic *efx) | |
8ceee660 | 705 | { |
d3245b28 BH |
706 | enum efx_phy_mode phy_mode; |
707 | int rc; | |
8ceee660 | 708 | |
d3245b28 | 709 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 710 | |
a816f75a BH |
711 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
712 | if (efx_dev_registered(efx)) { | |
713 | netif_addr_lock_bh(efx->net_dev); | |
714 | netif_addr_unlock_bh(efx->net_dev); | |
715 | } | |
716 | ||
d3245b28 BH |
717 | /* Disable PHY transmit in mac level loopbacks */ |
718 | phy_mode = efx->phy_mode; | |
177dfcd8 BH |
719 | if (LOOPBACK_INTERNAL(efx)) |
720 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
721 | else | |
722 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
177dfcd8 | 723 | |
d3245b28 | 724 | rc = efx->type->reconfigure_port(efx); |
8ceee660 | 725 | |
d3245b28 BH |
726 | if (rc) |
727 | efx->phy_mode = phy_mode; | |
177dfcd8 | 728 | |
d3245b28 | 729 | return rc; |
8ceee660 BH |
730 | } |
731 | ||
732 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
733 | * disabled. */ | |
d3245b28 | 734 | int efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 | 735 | { |
d3245b28 BH |
736 | int rc; |
737 | ||
8ceee660 BH |
738 | EFX_ASSERT_RESET_SERIALISED(efx); |
739 | ||
740 | mutex_lock(&efx->mac_lock); | |
d3245b28 | 741 | rc = __efx_reconfigure_port(efx); |
8ceee660 | 742 | mutex_unlock(&efx->mac_lock); |
d3245b28 BH |
743 | |
744 | return rc; | |
8ceee660 BH |
745 | } |
746 | ||
8be4f3e6 BH |
747 | /* Asynchronous work item for changing MAC promiscuity and multicast |
748 | * hash. Avoid a drain/rx_ingress enable by reconfiguring the current | |
749 | * MAC directly. */ | |
766ca0fa BH |
750 | static void efx_mac_work(struct work_struct *data) |
751 | { | |
752 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
753 | ||
754 | mutex_lock(&efx->mac_lock); | |
8be4f3e6 | 755 | if (efx->port_enabled) { |
ef2b90ee | 756 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
757 | efx->mac_op->reconfigure(efx); |
758 | } | |
766ca0fa BH |
759 | mutex_unlock(&efx->mac_lock); |
760 | } | |
761 | ||
8ceee660 BH |
762 | static int efx_probe_port(struct efx_nic *efx) |
763 | { | |
764 | int rc; | |
765 | ||
62776d03 | 766 | netif_dbg(efx, probe, efx->net_dev, "create port\n"); |
8ceee660 | 767 | |
ff3b00a0 SH |
768 | if (phy_flash_cfg) |
769 | efx->phy_mode = PHY_MODE_SPECIAL; | |
770 | ||
ef2b90ee BH |
771 | /* Connect up MAC/PHY operations table */ |
772 | rc = efx->type->probe_port(efx); | |
8ceee660 | 773 | if (rc) |
e42de262 | 774 | return rc; |
8ceee660 BH |
775 | |
776 | /* Sanity check MAC address */ | |
777 | if (is_valid_ether_addr(efx->mac_address)) { | |
778 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
779 | } else { | |
62776d03 BH |
780 | netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n", |
781 | efx->mac_address); | |
8ceee660 BH |
782 | if (!allow_bad_hwaddr) { |
783 | rc = -EINVAL; | |
784 | goto err; | |
785 | } | |
786 | random_ether_addr(efx->net_dev->dev_addr); | |
62776d03 BH |
787 | netif_info(efx, probe, efx->net_dev, |
788 | "using locally-generated MAC %pM\n", | |
789 | efx->net_dev->dev_addr); | |
8ceee660 BH |
790 | } |
791 | ||
792 | return 0; | |
793 | ||
794 | err: | |
e42de262 | 795 | efx->type->remove_port(efx); |
8ceee660 BH |
796 | return rc; |
797 | } | |
798 | ||
799 | static int efx_init_port(struct efx_nic *efx) | |
800 | { | |
801 | int rc; | |
802 | ||
62776d03 | 803 | netif_dbg(efx, drv, efx->net_dev, "init port\n"); |
8ceee660 | 804 | |
1dfc5cea BH |
805 | mutex_lock(&efx->mac_lock); |
806 | ||
177dfcd8 | 807 | rc = efx->phy_op->init(efx); |
8ceee660 | 808 | if (rc) |
1dfc5cea | 809 | goto fail1; |
8ceee660 | 810 | |
dc8cfa55 | 811 | efx->port_initialized = true; |
1dfc5cea | 812 | |
d3245b28 BH |
813 | /* Reconfigure the MAC before creating dma queues (required for |
814 | * Falcon/A1 where RX_INGR_EN/TX_DRAIN_EN isn't supported) */ | |
815 | efx->mac_op->reconfigure(efx); | |
816 | ||
817 | /* Ensure the PHY advertises the correct flow control settings */ | |
818 | rc = efx->phy_op->reconfigure(efx); | |
819 | if (rc) | |
820 | goto fail2; | |
821 | ||
1dfc5cea | 822 | mutex_unlock(&efx->mac_lock); |
8ceee660 | 823 | return 0; |
177dfcd8 | 824 | |
1dfc5cea | 825 | fail2: |
177dfcd8 | 826 | efx->phy_op->fini(efx); |
1dfc5cea BH |
827 | fail1: |
828 | mutex_unlock(&efx->mac_lock); | |
177dfcd8 | 829 | return rc; |
8ceee660 BH |
830 | } |
831 | ||
8ceee660 BH |
832 | static void efx_start_port(struct efx_nic *efx) |
833 | { | |
62776d03 | 834 | netif_dbg(efx, ifup, efx->net_dev, "start port\n"); |
8ceee660 BH |
835 | BUG_ON(efx->port_enabled); |
836 | ||
837 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 838 | efx->port_enabled = true; |
8be4f3e6 BH |
839 | |
840 | /* efx_mac_work() might have been scheduled after efx_stop_port(), | |
841 | * and then cancelled by efx_flush_all() */ | |
ef2b90ee | 842 | efx->type->push_multicast_hash(efx); |
8be4f3e6 BH |
843 | efx->mac_op->reconfigure(efx); |
844 | ||
8ceee660 BH |
845 | mutex_unlock(&efx->mac_lock); |
846 | } | |
847 | ||
fdaa9aed | 848 | /* Prevent efx_mac_work() and efx_monitor() from working */ |
8ceee660 BH |
849 | static void efx_stop_port(struct efx_nic *efx) |
850 | { | |
62776d03 | 851 | netif_dbg(efx, ifdown, efx->net_dev, "stop port\n"); |
8ceee660 BH |
852 | |
853 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 854 | efx->port_enabled = false; |
8ceee660 BH |
855 | mutex_unlock(&efx->mac_lock); |
856 | ||
857 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 858 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
859 | netif_addr_lock_bh(efx->net_dev); |
860 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
861 | } |
862 | } | |
863 | ||
864 | static void efx_fini_port(struct efx_nic *efx) | |
865 | { | |
62776d03 | 866 | netif_dbg(efx, drv, efx->net_dev, "shut down port\n"); |
8ceee660 BH |
867 | |
868 | if (!efx->port_initialized) | |
869 | return; | |
870 | ||
177dfcd8 | 871 | efx->phy_op->fini(efx); |
dc8cfa55 | 872 | efx->port_initialized = false; |
8ceee660 | 873 | |
eb50c0d6 | 874 | efx->link_state.up = false; |
8ceee660 BH |
875 | efx_link_status_changed(efx); |
876 | } | |
877 | ||
878 | static void efx_remove_port(struct efx_nic *efx) | |
879 | { | |
62776d03 | 880 | netif_dbg(efx, drv, efx->net_dev, "destroying port\n"); |
8ceee660 | 881 | |
ef2b90ee | 882 | efx->type->remove_port(efx); |
8ceee660 BH |
883 | } |
884 | ||
885 | /************************************************************************** | |
886 | * | |
887 | * NIC handling | |
888 | * | |
889 | **************************************************************************/ | |
890 | ||
891 | /* This configures the PCI device to enable I/O and DMA. */ | |
892 | static int efx_init_io(struct efx_nic *efx) | |
893 | { | |
894 | struct pci_dev *pci_dev = efx->pci_dev; | |
895 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
896 | int rc; | |
897 | ||
62776d03 | 898 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
8ceee660 BH |
899 | |
900 | rc = pci_enable_device(pci_dev); | |
901 | if (rc) { | |
62776d03 BH |
902 | netif_err(efx, probe, efx->net_dev, |
903 | "failed to enable PCI device\n"); | |
8ceee660 BH |
904 | goto fail1; |
905 | } | |
906 | ||
907 | pci_set_master(pci_dev); | |
908 | ||
909 | /* Set the PCI DMA mask. Try all possibilities from our | |
910 | * genuine mask down to 32 bits, because some architectures | |
911 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
912 | * masks event though they reject 46 bit masks. | |
913 | */ | |
914 | while (dma_mask > 0x7fffffffUL) { | |
915 | if (pci_dma_supported(pci_dev, dma_mask) && | |
916 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
917 | break; | |
918 | dma_mask >>= 1; | |
919 | } | |
920 | if (rc) { | |
62776d03 BH |
921 | netif_err(efx, probe, efx->net_dev, |
922 | "could not find a suitable DMA mask\n"); | |
8ceee660 BH |
923 | goto fail2; |
924 | } | |
62776d03 BH |
925 | netif_dbg(efx, probe, efx->net_dev, |
926 | "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
8ceee660 BH |
927 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); |
928 | if (rc) { | |
929 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
930 | * fail with a mask that pci_set_dma_mask() accepted, | |
931 | * but just in case... | |
932 | */ | |
62776d03 BH |
933 | netif_err(efx, probe, efx->net_dev, |
934 | "failed to set consistent DMA mask\n"); | |
8ceee660 BH |
935 | goto fail2; |
936 | } | |
937 | ||
dc803df8 BH |
938 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
939 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 | 940 | if (rc) { |
62776d03 BH |
941 | netif_err(efx, probe, efx->net_dev, |
942 | "request for memory BAR failed\n"); | |
8ceee660 BH |
943 | rc = -EIO; |
944 | goto fail3; | |
945 | } | |
946 | efx->membase = ioremap_nocache(efx->membase_phys, | |
947 | efx->type->mem_map_size); | |
948 | if (!efx->membase) { | |
62776d03 BH |
949 | netif_err(efx, probe, efx->net_dev, |
950 | "could not map memory BAR at %llx+%x\n", | |
951 | (unsigned long long)efx->membase_phys, | |
952 | efx->type->mem_map_size); | |
8ceee660 BH |
953 | rc = -ENOMEM; |
954 | goto fail4; | |
955 | } | |
62776d03 BH |
956 | netif_dbg(efx, probe, efx->net_dev, |
957 | "memory BAR at %llx+%x (virtual %p)\n", | |
958 | (unsigned long long)efx->membase_phys, | |
959 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
960 | |
961 | return 0; | |
962 | ||
963 | fail4: | |
dc803df8 | 964 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 965 | fail3: |
2c118e0f | 966 | efx->membase_phys = 0; |
8ceee660 BH |
967 | fail2: |
968 | pci_disable_device(efx->pci_dev); | |
969 | fail1: | |
970 | return rc; | |
971 | } | |
972 | ||
973 | static void efx_fini_io(struct efx_nic *efx) | |
974 | { | |
62776d03 | 975 | netif_dbg(efx, drv, efx->net_dev, "shutting down I/O\n"); |
8ceee660 BH |
976 | |
977 | if (efx->membase) { | |
978 | iounmap(efx->membase); | |
979 | efx->membase = NULL; | |
980 | } | |
981 | ||
982 | if (efx->membase_phys) { | |
dc803df8 | 983 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 984 | efx->membase_phys = 0; |
8ceee660 BH |
985 | } |
986 | ||
987 | pci_disable_device(efx->pci_dev); | |
988 | } | |
989 | ||
a4900ac9 BH |
990 | /* Get number of channels wanted. Each channel will have its own IRQ, |
991 | * 1 RX queue and/or 2 TX queues. */ | |
992 | static int efx_wanted_channels(void) | |
46123d04 | 993 | { |
2f8975fb | 994 | cpumask_var_t core_mask; |
46123d04 BH |
995 | int count; |
996 | int cpu; | |
997 | ||
79f55997 | 998 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 999 | printk(KERN_WARNING |
3977d033 | 1000 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
1001 | return 1; |
1002 | } | |
1003 | ||
46123d04 BH |
1004 | count = 0; |
1005 | for_each_online_cpu(cpu) { | |
2f8975fb | 1006 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 1007 | ++count; |
2f8975fb | 1008 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 1009 | topology_core_cpumask(cpu)); |
46123d04 BH |
1010 | } |
1011 | } | |
1012 | ||
2f8975fb | 1013 | free_cpumask_var(core_mask); |
46123d04 BH |
1014 | return count; |
1015 | } | |
1016 | ||
1017 | /* Probe the number and type of interrupts we are able to obtain, and | |
1018 | * the resulting numbers of channels and RX queues. | |
1019 | */ | |
8ceee660 BH |
1020 | static void efx_probe_interrupts(struct efx_nic *efx) |
1021 | { | |
46123d04 BH |
1022 | int max_channels = |
1023 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
1024 | int rc, i; |
1025 | ||
1026 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 | 1027 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
a4900ac9 | 1028 | int n_channels; |
aa6ef27e | 1029 | |
a4900ac9 BH |
1030 | n_channels = efx_wanted_channels(); |
1031 | if (separate_tx_channels) | |
1032 | n_channels *= 2; | |
1033 | n_channels = min(n_channels, max_channels); | |
8ceee660 | 1034 | |
a4900ac9 | 1035 | for (i = 0; i < n_channels; i++) |
8ceee660 | 1036 | xentries[i].entry = i; |
a4900ac9 | 1037 | rc = pci_enable_msix(efx->pci_dev, xentries, n_channels); |
8ceee660 | 1038 | if (rc > 0) { |
62776d03 BH |
1039 | netif_err(efx, drv, efx->net_dev, |
1040 | "WARNING: Insufficient MSI-X vectors" | |
1041 | " available (%d < %d).\n", rc, n_channels); | |
1042 | netif_err(efx, drv, efx->net_dev, | |
1043 | "WARNING: Performance may be reduced.\n"); | |
a4900ac9 BH |
1044 | EFX_BUG_ON_PARANOID(rc >= n_channels); |
1045 | n_channels = rc; | |
8ceee660 | 1046 | rc = pci_enable_msix(efx->pci_dev, xentries, |
a4900ac9 | 1047 | n_channels); |
8ceee660 BH |
1048 | } |
1049 | ||
1050 | if (rc == 0) { | |
a4900ac9 BH |
1051 | efx->n_channels = n_channels; |
1052 | if (separate_tx_channels) { | |
1053 | efx->n_tx_channels = | |
1054 | max(efx->n_channels / 2, 1U); | |
1055 | efx->n_rx_channels = | |
1056 | max(efx->n_channels - | |
1057 | efx->n_tx_channels, 1U); | |
1058 | } else { | |
1059 | efx->n_tx_channels = efx->n_channels; | |
1060 | efx->n_rx_channels = efx->n_channels; | |
1061 | } | |
1062 | for (i = 0; i < n_channels; i++) | |
f7d12cdc BH |
1063 | efx_get_channel(efx, i)->irq = |
1064 | xentries[i].vector; | |
8ceee660 BH |
1065 | } else { |
1066 | /* Fall back to single channel MSI */ | |
1067 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
62776d03 BH |
1068 | netif_err(efx, drv, efx->net_dev, |
1069 | "could not enable MSI-X\n"); | |
8ceee660 BH |
1070 | } |
1071 | } | |
1072 | ||
1073 | /* Try single interrupt MSI */ | |
1074 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
28b581ab | 1075 | efx->n_channels = 1; |
a4900ac9 BH |
1076 | efx->n_rx_channels = 1; |
1077 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1078 | rc = pci_enable_msi(efx->pci_dev); |
1079 | if (rc == 0) { | |
f7d12cdc | 1080 | efx_get_channel(efx, 0)->irq = efx->pci_dev->irq; |
8ceee660 | 1081 | } else { |
62776d03 BH |
1082 | netif_err(efx, drv, efx->net_dev, |
1083 | "could not enable MSI\n"); | |
8ceee660 BH |
1084 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; |
1085 | } | |
1086 | } | |
1087 | ||
1088 | /* Assume legacy interrupts */ | |
1089 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
28b581ab | 1090 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
a4900ac9 BH |
1091 | efx->n_rx_channels = 1; |
1092 | efx->n_tx_channels = 1; | |
8ceee660 BH |
1093 | efx->legacy_irq = efx->pci_dev->irq; |
1094 | } | |
1095 | } | |
1096 | ||
1097 | static void efx_remove_interrupts(struct efx_nic *efx) | |
1098 | { | |
1099 | struct efx_channel *channel; | |
1100 | ||
1101 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 1102 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1103 | channel->irq = 0; |
1104 | pci_disable_msi(efx->pci_dev); | |
1105 | pci_disable_msix(efx->pci_dev); | |
1106 | ||
1107 | /* Remove legacy interrupt */ | |
1108 | efx->legacy_irq = 0; | |
1109 | } | |
1110 | ||
8313aca3 BH |
1111 | struct efx_tx_queue * |
1112 | efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type) | |
1113 | { | |
1114 | unsigned tx_channel_offset = | |
1115 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
1116 | EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels || | |
1117 | type >= EFX_TXQ_TYPES); | |
1118 | return &efx->channel[tx_channel_offset + index]->tx_queue[type]; | |
1119 | } | |
1120 | ||
8831da7b | 1121 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 | 1122 | { |
a4900ac9 | 1123 | struct efx_channel *channel; |
8ceee660 | 1124 | struct efx_tx_queue *tx_queue; |
a4900ac9 BH |
1125 | unsigned tx_channel_offset = |
1126 | separate_tx_channels ? efx->n_channels - efx->n_tx_channels : 0; | |
8ceee660 | 1127 | |
8313aca3 BH |
1128 | /* Channel pointers were set in efx_init_struct() but we now |
1129 | * need to clear them for TX queues in any RX-only channels. */ | |
a4900ac9 | 1130 | efx_for_each_channel(channel, efx) { |
8313aca3 BH |
1131 | if (channel->channel - tx_channel_offset >= |
1132 | efx->n_tx_channels) { | |
a4900ac9 | 1133 | efx_for_each_channel_tx_queue(tx_queue, channel) |
8313aca3 | 1134 | tx_queue->channel = NULL; |
a4900ac9 | 1135 | } |
60ac1065 | 1136 | } |
8ceee660 BH |
1137 | } |
1138 | ||
1139 | static int efx_probe_nic(struct efx_nic *efx) | |
1140 | { | |
765c9f46 | 1141 | size_t i; |
8ceee660 BH |
1142 | int rc; |
1143 | ||
62776d03 | 1144 | netif_dbg(efx, probe, efx->net_dev, "creating NIC\n"); |
8ceee660 BH |
1145 | |
1146 | /* Carry out hardware-type specific initialisation */ | |
ef2b90ee | 1147 | rc = efx->type->probe(efx); |
8ceee660 BH |
1148 | if (rc) |
1149 | return rc; | |
1150 | ||
a4900ac9 | 1151 | /* Determine the number of channels and queues by trying to hook |
8ceee660 BH |
1152 | * in MSI-X interrupts. */ |
1153 | efx_probe_interrupts(efx); | |
1154 | ||
5d3a6fca BH |
1155 | if (efx->n_channels > 1) |
1156 | get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key)); | |
765c9f46 BH |
1157 | for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++) |
1158 | efx->rx_indir_table[i] = i % efx->n_rx_channels; | |
5d3a6fca | 1159 | |
8831da7b | 1160 | efx_set_channels(efx); |
a4900ac9 | 1161 | efx->net_dev->real_num_tx_queues = efx->n_tx_channels; |
8ceee660 BH |
1162 | |
1163 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1164 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1165 | |
1166 | return 0; | |
1167 | } | |
1168 | ||
1169 | static void efx_remove_nic(struct efx_nic *efx) | |
1170 | { | |
62776d03 | 1171 | netif_dbg(efx, drv, efx->net_dev, "destroying NIC\n"); |
8ceee660 BH |
1172 | |
1173 | efx_remove_interrupts(efx); | |
ef2b90ee | 1174 | efx->type->remove(efx); |
8ceee660 BH |
1175 | } |
1176 | ||
1177 | /************************************************************************** | |
1178 | * | |
1179 | * NIC startup/shutdown | |
1180 | * | |
1181 | *************************************************************************/ | |
1182 | ||
1183 | static int efx_probe_all(struct efx_nic *efx) | |
1184 | { | |
1185 | struct efx_channel *channel; | |
1186 | int rc; | |
1187 | ||
1188 | /* Create NIC */ | |
1189 | rc = efx_probe_nic(efx); | |
1190 | if (rc) { | |
62776d03 | 1191 | netif_err(efx, probe, efx->net_dev, "failed to create NIC\n"); |
8ceee660 BH |
1192 | goto fail1; |
1193 | } | |
1194 | ||
1195 | /* Create port */ | |
1196 | rc = efx_probe_port(efx); | |
1197 | if (rc) { | |
62776d03 | 1198 | netif_err(efx, probe, efx->net_dev, "failed to create port\n"); |
8ceee660 BH |
1199 | goto fail2; |
1200 | } | |
1201 | ||
1202 | /* Create channels */ | |
ecc910f5 | 1203 | efx->rxq_entries = efx->txq_entries = EFX_DEFAULT_DMAQ_SIZE; |
8ceee660 BH |
1204 | efx_for_each_channel(channel, efx) { |
1205 | rc = efx_probe_channel(channel); | |
1206 | if (rc) { | |
62776d03 BH |
1207 | netif_err(efx, probe, efx->net_dev, |
1208 | "failed to create channel %d\n", | |
1209 | channel->channel); | |
8ceee660 BH |
1210 | goto fail3; |
1211 | } | |
1212 | } | |
56536e9c | 1213 | efx_set_channel_names(efx); |
8ceee660 BH |
1214 | |
1215 | return 0; | |
1216 | ||
1217 | fail3: | |
1218 | efx_for_each_channel(channel, efx) | |
1219 | efx_remove_channel(channel); | |
1220 | efx_remove_port(efx); | |
1221 | fail2: | |
1222 | efx_remove_nic(efx); | |
1223 | fail1: | |
1224 | return rc; | |
1225 | } | |
1226 | ||
1227 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1228 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1229 | * and ensures that the port is scheduled to be reconfigured. | |
1230 | * This function is safe to call multiple times when the NIC is in any | |
1231 | * state. */ | |
1232 | static void efx_start_all(struct efx_nic *efx) | |
1233 | { | |
1234 | struct efx_channel *channel; | |
1235 | ||
1236 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1237 | ||
1238 | /* Check that it is appropriate to restart the interface. All | |
1239 | * of these flags are safe to read under just the rtnl lock */ | |
1240 | if (efx->port_enabled) | |
1241 | return; | |
1242 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1243 | return; | |
55668611 | 1244 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1245 | return; |
1246 | ||
1247 | /* Mark the port as enabled so port reconfigurations can start, then | |
1248 | * restart the transmit interface early so the watchdog timer stops */ | |
1249 | efx_start_port(efx); | |
8ceee660 | 1250 | |
a4900ac9 BH |
1251 | efx_for_each_channel(channel, efx) { |
1252 | if (efx_dev_registered(efx)) | |
1253 | efx_wake_queue(channel); | |
8ceee660 | 1254 | efx_start_channel(channel); |
a4900ac9 | 1255 | } |
8ceee660 | 1256 | |
152b6a62 | 1257 | efx_nic_enable_interrupts(efx); |
8ceee660 | 1258 | |
8880f4ec BH |
1259 | /* Switch to event based MCDI completions after enabling interrupts. |
1260 | * If a reset has been scheduled, then we need to stay in polled mode. | |
1261 | * Rather than serialising efx_mcdi_mode_event() [which sleeps] and | |
1262 | * reset_pending [modified from an atomic context], we instead guarantee | |
1263 | * that efx_mcdi_mode_poll() isn't reverted erroneously */ | |
1264 | efx_mcdi_mode_event(efx); | |
1265 | if (efx->reset_pending != RESET_TYPE_NONE) | |
1266 | efx_mcdi_mode_poll(efx); | |
1267 | ||
78c1f0a0 SH |
1268 | /* Start the hardware monitor if there is one. Otherwise (we're link |
1269 | * event driven), we have to poll the PHY because after an event queue | |
1270 | * flush, we could have a missed a link state change */ | |
1271 | if (efx->type->monitor != NULL) { | |
8ceee660 BH |
1272 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1273 | efx_monitor_interval); | |
78c1f0a0 SH |
1274 | } else { |
1275 | mutex_lock(&efx->mac_lock); | |
1276 | if (efx->phy_op->poll(efx)) | |
1277 | efx_link_status_changed(efx); | |
1278 | mutex_unlock(&efx->mac_lock); | |
1279 | } | |
55edc6e6 | 1280 | |
ef2b90ee | 1281 | efx->type->start_stats(efx); |
8ceee660 BH |
1282 | } |
1283 | ||
1284 | /* Flush all delayed work. Should only be called when no more delayed work | |
1285 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1286 | * since we're holding the rtnl_lock at this point. */ | |
1287 | static void efx_flush_all(struct efx_nic *efx) | |
1288 | { | |
8ceee660 BH |
1289 | /* Make sure the hardware monitor is stopped */ |
1290 | cancel_delayed_work_sync(&efx->monitor_work); | |
8ceee660 | 1291 | /* Stop scheduled port reconfigurations */ |
766ca0fa | 1292 | cancel_work_sync(&efx->mac_work); |
8ceee660 BH |
1293 | } |
1294 | ||
1295 | /* Quiesce hardware and software without bringing the link down. | |
1296 | * Safe to call multiple times, when the nic and interface is in any | |
1297 | * state. The caller is guaranteed to subsequently be in a position | |
1298 | * to modify any hardware and software state they see fit without | |
1299 | * taking locks. */ | |
1300 | static void efx_stop_all(struct efx_nic *efx) | |
1301 | { | |
1302 | struct efx_channel *channel; | |
1303 | ||
1304 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1305 | ||
1306 | /* port_enabled can be read safely under the rtnl lock */ | |
1307 | if (!efx->port_enabled) | |
1308 | return; | |
1309 | ||
ef2b90ee | 1310 | efx->type->stop_stats(efx); |
55edc6e6 | 1311 | |
8880f4ec BH |
1312 | /* Switch to MCDI polling on Siena before disabling interrupts */ |
1313 | efx_mcdi_mode_poll(efx); | |
1314 | ||
8ceee660 | 1315 | /* Disable interrupts and wait for ISR to complete */ |
152b6a62 | 1316 | efx_nic_disable_interrupts(efx); |
8ceee660 BH |
1317 | if (efx->legacy_irq) |
1318 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1319 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1320 | if (channel->irq) |
1321 | synchronize_irq(channel->irq); | |
b3475645 | 1322 | } |
8ceee660 BH |
1323 | |
1324 | /* Stop all NAPI processing and synchronous rx refills */ | |
1325 | efx_for_each_channel(channel, efx) | |
1326 | efx_stop_channel(channel); | |
1327 | ||
1328 | /* Stop all asynchronous port reconfigurations. Since all | |
1329 | * event processing has already been stopped, there is no | |
1330 | * window to loose phy events */ | |
1331 | efx_stop_port(efx); | |
1332 | ||
fdaa9aed | 1333 | /* Flush efx_mac_work(), refill_workqueue, monitor_work */ |
8ceee660 BH |
1334 | efx_flush_all(efx); |
1335 | ||
8ceee660 BH |
1336 | /* Stop the kernel transmit interface late, so the watchdog |
1337 | * timer isn't ticking over the flush */ | |
55668611 | 1338 | if (efx_dev_registered(efx)) { |
a4900ac9 BH |
1339 | struct efx_channel *channel; |
1340 | efx_for_each_channel(channel, efx) | |
1341 | efx_stop_queue(channel); | |
8ceee660 BH |
1342 | netif_tx_lock_bh(efx->net_dev); |
1343 | netif_tx_unlock_bh(efx->net_dev); | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | static void efx_remove_all(struct efx_nic *efx) | |
1348 | { | |
1349 | struct efx_channel *channel; | |
1350 | ||
1351 | efx_for_each_channel(channel, efx) | |
1352 | efx_remove_channel(channel); | |
1353 | efx_remove_port(efx); | |
1354 | efx_remove_nic(efx); | |
1355 | } | |
1356 | ||
8ceee660 BH |
1357 | /************************************************************************** |
1358 | * | |
1359 | * Interrupt moderation | |
1360 | * | |
1361 | **************************************************************************/ | |
1362 | ||
0d86ebd8 BH |
1363 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1364 | { | |
1365 | if (usecs <= 0) | |
1366 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1367 | if (usecs < resolution) | |
1368 | return 1; /* never round down to 0 */ | |
1369 | return usecs / resolution; | |
1370 | } | |
1371 | ||
8ceee660 | 1372 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1373 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1374 | bool rx_adaptive) | |
8ceee660 | 1375 | { |
f7d12cdc | 1376 | struct efx_channel *channel; |
152b6a62 BH |
1377 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, EFX_IRQ_MOD_RESOLUTION); |
1378 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, EFX_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1379 | |
1380 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1381 | ||
6fb70fd1 | 1382 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1383 | efx->irq_rx_moderation = rx_ticks; |
f7d12cdc BH |
1384 | efx_for_each_channel(channel, efx) { |
1385 | if (efx_channel_get_rx_queue(channel)) | |
1386 | channel->irq_moderation = rx_ticks; | |
1387 | else if (efx_channel_get_tx_queue(channel, 0)) | |
1388 | channel->irq_moderation = tx_ticks; | |
1389 | } | |
8ceee660 BH |
1390 | } |
1391 | ||
1392 | /************************************************************************** | |
1393 | * | |
1394 | * Hardware monitor | |
1395 | * | |
1396 | **************************************************************************/ | |
1397 | ||
1398 | /* Run periodically off the general workqueue. Serialised against | |
1399 | * efx_reconfigure_port via the mac_lock */ | |
1400 | static void efx_monitor(struct work_struct *data) | |
1401 | { | |
1402 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1403 | monitor_work.work); | |
8ceee660 | 1404 | |
62776d03 BH |
1405 | netif_vdbg(efx, timer, efx->net_dev, |
1406 | "hardware monitor executing on CPU %d\n", | |
1407 | raw_smp_processor_id()); | |
ef2b90ee | 1408 | BUG_ON(efx->type->monitor == NULL); |
8ceee660 | 1409 | |
8ceee660 BH |
1410 | /* If the mac_lock is already held then it is likely a port |
1411 | * reconfiguration is already in place, which will likely do | |
1412 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1413 | if (!mutex_trylock(&efx->mac_lock)) |
1414 | goto out_requeue; | |
1415 | if (!efx->port_enabled) | |
1416 | goto out_unlock; | |
ef2b90ee | 1417 | efx->type->monitor(efx); |
8ceee660 | 1418 | |
766ca0fa | 1419 | out_unlock: |
8ceee660 | 1420 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1421 | out_requeue: |
8ceee660 BH |
1422 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1423 | efx_monitor_interval); | |
1424 | } | |
1425 | ||
1426 | /************************************************************************** | |
1427 | * | |
1428 | * ioctls | |
1429 | * | |
1430 | *************************************************************************/ | |
1431 | ||
1432 | /* Net device ioctl | |
1433 | * Context: process, rtnl_lock() held. | |
1434 | */ | |
1435 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1436 | { | |
767e468c | 1437 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1438 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1439 | |
1440 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1441 | ||
68e7f45e BH |
1442 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1443 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1444 | (data->phy_id & 0xfc00) == 0x0400) | |
1445 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1446 | ||
1447 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1448 | } |
1449 | ||
1450 | /************************************************************************** | |
1451 | * | |
1452 | * NAPI interface | |
1453 | * | |
1454 | **************************************************************************/ | |
1455 | ||
1456 | static int efx_init_napi(struct efx_nic *efx) | |
1457 | { | |
1458 | struct efx_channel *channel; | |
8ceee660 BH |
1459 | |
1460 | efx_for_each_channel(channel, efx) { | |
1461 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1462 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1463 | efx_poll, napi_weight); | |
8ceee660 BH |
1464 | } |
1465 | return 0; | |
8ceee660 BH |
1466 | } |
1467 | ||
1468 | static void efx_fini_napi(struct efx_nic *efx) | |
1469 | { | |
1470 | struct efx_channel *channel; | |
1471 | ||
1472 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1473 | if (channel->napi_dev) |
1474 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1475 | channel->napi_dev = NULL; |
1476 | } | |
1477 | } | |
1478 | ||
1479 | /************************************************************************** | |
1480 | * | |
1481 | * Kernel netpoll interface | |
1482 | * | |
1483 | *************************************************************************/ | |
1484 | ||
1485 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1486 | ||
1487 | /* Although in the common case interrupts will be disabled, this is not | |
1488 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1489 | * so no locking is required. | |
1490 | */ | |
1491 | static void efx_netpoll(struct net_device *net_dev) | |
1492 | { | |
767e468c | 1493 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1494 | struct efx_channel *channel; |
1495 | ||
64ee3120 | 1496 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1497 | efx_schedule_channel(channel); |
1498 | } | |
1499 | ||
1500 | #endif | |
1501 | ||
1502 | /************************************************************************** | |
1503 | * | |
1504 | * Kernel net device interface | |
1505 | * | |
1506 | *************************************************************************/ | |
1507 | ||
1508 | /* Context: process, rtnl_lock() held. */ | |
1509 | static int efx_net_open(struct net_device *net_dev) | |
1510 | { | |
767e468c | 1511 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1512 | EFX_ASSERT_RESET_SERIALISED(efx); |
1513 | ||
62776d03 BH |
1514 | netif_dbg(efx, ifup, efx->net_dev, "opening device on CPU %d\n", |
1515 | raw_smp_processor_id()); | |
8ceee660 | 1516 | |
f4bd954e BH |
1517 | if (efx->state == STATE_DISABLED) |
1518 | return -EIO; | |
f8b87c17 BH |
1519 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1520 | return -EBUSY; | |
8880f4ec BH |
1521 | if (efx_mcdi_poll_reboot(efx) && efx_reset(efx, RESET_TYPE_ALL)) |
1522 | return -EIO; | |
f8b87c17 | 1523 | |
78c1f0a0 SH |
1524 | /* Notify the kernel of the link state polled during driver load, |
1525 | * before the monitor starts running */ | |
1526 | efx_link_status_changed(efx); | |
1527 | ||
8ceee660 BH |
1528 | efx_start_all(efx); |
1529 | return 0; | |
1530 | } | |
1531 | ||
1532 | /* Context: process, rtnl_lock() held. | |
1533 | * Note that the kernel will ignore our return code; this method | |
1534 | * should really be a void. | |
1535 | */ | |
1536 | static int efx_net_stop(struct net_device *net_dev) | |
1537 | { | |
767e468c | 1538 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1539 | |
62776d03 BH |
1540 | netif_dbg(efx, ifdown, efx->net_dev, "closing on CPU %d\n", |
1541 | raw_smp_processor_id()); | |
8ceee660 | 1542 | |
f4bd954e BH |
1543 | if (efx->state != STATE_DISABLED) { |
1544 | /* Stop the device and flush all the channels */ | |
1545 | efx_stop_all(efx); | |
1546 | efx_fini_channels(efx); | |
1547 | efx_init_channels(efx); | |
1548 | } | |
8ceee660 BH |
1549 | |
1550 | return 0; | |
1551 | } | |
1552 | ||
5b9e207c | 1553 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
28172739 | 1554 | static struct rtnl_link_stats64 *efx_net_stats(struct net_device *net_dev, struct rtnl_link_stats64 *stats) |
8ceee660 | 1555 | { |
767e468c | 1556 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1557 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
8ceee660 | 1558 | |
55edc6e6 | 1559 | spin_lock_bh(&efx->stats_lock); |
ef2b90ee | 1560 | efx->type->update_stats(efx); |
55edc6e6 | 1561 | spin_unlock_bh(&efx->stats_lock); |
8ceee660 BH |
1562 | |
1563 | stats->rx_packets = mac_stats->rx_packets; | |
1564 | stats->tx_packets = mac_stats->tx_packets; | |
1565 | stats->rx_bytes = mac_stats->rx_bytes; | |
1566 | stats->tx_bytes = mac_stats->tx_bytes; | |
80485d34 | 1567 | stats->rx_dropped = efx->n_rx_nodesc_drop_cnt; |
8ceee660 BH |
1568 | stats->multicast = mac_stats->rx_multicast; |
1569 | stats->collisions = mac_stats->tx_collision; | |
1570 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1571 | mac_stats->rx_length_error); | |
8ceee660 BH |
1572 | stats->rx_crc_errors = mac_stats->rx_bad; |
1573 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1574 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1575 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1576 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1577 | ||
1578 | stats->rx_errors = (stats->rx_length_errors + | |
8ceee660 BH |
1579 | stats->rx_crc_errors + |
1580 | stats->rx_frame_errors + | |
8ceee660 BH |
1581 | mac_stats->rx_symbol_error); |
1582 | stats->tx_errors = (stats->tx_window_errors + | |
1583 | mac_stats->tx_bad); | |
1584 | ||
1585 | return stats; | |
1586 | } | |
1587 | ||
1588 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1589 | static void efx_watchdog(struct net_device *net_dev) | |
1590 | { | |
767e468c | 1591 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1592 | |
62776d03 BH |
1593 | netif_err(efx, tx_err, efx->net_dev, |
1594 | "TX stuck with port_enabled=%d: resetting channels\n", | |
1595 | efx->port_enabled); | |
8ceee660 | 1596 | |
739bb23d | 1597 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1598 | } |
1599 | ||
1600 | ||
1601 | /* Context: process, rtnl_lock() held. */ | |
1602 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1603 | { | |
767e468c | 1604 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1605 | int rc = 0; |
1606 | ||
1607 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1608 | ||
1609 | if (new_mtu > EFX_MAX_MTU) | |
1610 | return -EINVAL; | |
1611 | ||
1612 | efx_stop_all(efx); | |
1613 | ||
62776d03 | 1614 | netif_dbg(efx, drv, efx->net_dev, "changing MTU to %d\n", new_mtu); |
8ceee660 BH |
1615 | |
1616 | efx_fini_channels(efx); | |
d3245b28 BH |
1617 | |
1618 | mutex_lock(&efx->mac_lock); | |
1619 | /* Reconfigure the MAC before enabling the dma queues so that | |
1620 | * the RX buffers don't overflow */ | |
8ceee660 | 1621 | net_dev->mtu = new_mtu; |
d3245b28 BH |
1622 | efx->mac_op->reconfigure(efx); |
1623 | mutex_unlock(&efx->mac_lock); | |
1624 | ||
bc3c90a2 | 1625 | efx_init_channels(efx); |
8ceee660 BH |
1626 | |
1627 | efx_start_all(efx); | |
1628 | return rc; | |
8ceee660 BH |
1629 | } |
1630 | ||
1631 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1632 | { | |
767e468c | 1633 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1634 | struct sockaddr *addr = data; |
1635 | char *new_addr = addr->sa_data; | |
1636 | ||
1637 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1638 | ||
1639 | if (!is_valid_ether_addr(new_addr)) { | |
62776d03 BH |
1640 | netif_err(efx, drv, efx->net_dev, |
1641 | "invalid ethernet MAC address requested: %pM\n", | |
1642 | new_addr); | |
8ceee660 BH |
1643 | return -EINVAL; |
1644 | } | |
1645 | ||
1646 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1647 | ||
1648 | /* Reconfigure the MAC */ | |
d3245b28 BH |
1649 | mutex_lock(&efx->mac_lock); |
1650 | efx->mac_op->reconfigure(efx); | |
1651 | mutex_unlock(&efx->mac_lock); | |
8ceee660 BH |
1652 | |
1653 | return 0; | |
1654 | } | |
1655 | ||
a816f75a | 1656 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1657 | static void efx_set_multicast_list(struct net_device *net_dev) |
1658 | { | |
767e468c | 1659 | struct efx_nic *efx = netdev_priv(net_dev); |
22bedad3 | 1660 | struct netdev_hw_addr *ha; |
8ceee660 | 1661 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
8ceee660 BH |
1662 | u32 crc; |
1663 | int bit; | |
8ceee660 | 1664 | |
8be4f3e6 | 1665 | efx->promiscuous = !!(net_dev->flags & IFF_PROMISC); |
8ceee660 BH |
1666 | |
1667 | /* Build multicast hash table */ | |
8be4f3e6 | 1668 | if (efx->promiscuous || (net_dev->flags & IFF_ALLMULTI)) { |
8ceee660 BH |
1669 | memset(mc_hash, 0xff, sizeof(*mc_hash)); |
1670 | } else { | |
1671 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
22bedad3 JP |
1672 | netdev_for_each_mc_addr(ha, net_dev) { |
1673 | crc = ether_crc_le(ETH_ALEN, ha->addr); | |
8ceee660 BH |
1674 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); |
1675 | set_bit_le(bit, mc_hash->byte); | |
8ceee660 | 1676 | } |
8ceee660 | 1677 | |
8be4f3e6 BH |
1678 | /* Broadcast packets go through the multicast hash filter. |
1679 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
1680 | * so we always add bit 0xff to the mask. | |
1681 | */ | |
1682 | set_bit_le(0xff, mc_hash->byte); | |
1683 | } | |
a816f75a | 1684 | |
8be4f3e6 BH |
1685 | if (efx->port_enabled) |
1686 | queue_work(efx->workqueue, &efx->mac_work); | |
1687 | /* Otherwise efx_start_port() will do this */ | |
8ceee660 BH |
1688 | } |
1689 | ||
c3ecb9f3 SH |
1690 | static const struct net_device_ops efx_netdev_ops = { |
1691 | .ndo_open = efx_net_open, | |
1692 | .ndo_stop = efx_net_stop, | |
4472702e | 1693 | .ndo_get_stats64 = efx_net_stats, |
c3ecb9f3 SH |
1694 | .ndo_tx_timeout = efx_watchdog, |
1695 | .ndo_start_xmit = efx_hard_start_xmit, | |
1696 | .ndo_validate_addr = eth_validate_addr, | |
1697 | .ndo_do_ioctl = efx_ioctl, | |
1698 | .ndo_change_mtu = efx_change_mtu, | |
1699 | .ndo_set_mac_address = efx_set_mac_address, | |
1700 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1701 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1702 | .ndo_poll_controller = efx_netpoll, | |
1703 | #endif | |
1704 | }; | |
1705 | ||
7dde596e BH |
1706 | static void efx_update_name(struct efx_nic *efx) |
1707 | { | |
1708 | strcpy(efx->name, efx->net_dev->name); | |
1709 | efx_mtd_rename(efx); | |
1710 | efx_set_channel_names(efx); | |
1711 | } | |
1712 | ||
8ceee660 BH |
1713 | static int efx_netdev_event(struct notifier_block *this, |
1714 | unsigned long event, void *ptr) | |
1715 | { | |
d3208b5e | 1716 | struct net_device *net_dev = ptr; |
8ceee660 | 1717 | |
7dde596e BH |
1718 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1719 | event == NETDEV_CHANGENAME) | |
1720 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1721 | |
1722 | return NOTIFY_DONE; | |
1723 | } | |
1724 | ||
1725 | static struct notifier_block efx_netdev_notifier = { | |
1726 | .notifier_call = efx_netdev_event, | |
1727 | }; | |
1728 | ||
06d5e193 BH |
1729 | static ssize_t |
1730 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1731 | { | |
1732 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1733 | return sprintf(buf, "%d\n", efx->phy_type); | |
1734 | } | |
1735 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1736 | ||
8ceee660 BH |
1737 | static int efx_register_netdev(struct efx_nic *efx) |
1738 | { | |
1739 | struct net_device *net_dev = efx->net_dev; | |
1740 | int rc; | |
1741 | ||
1742 | net_dev->watchdog_timeo = 5 * HZ; | |
1743 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1744 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1745 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); |
1746 | ||
8ceee660 | 1747 | /* Clear MAC statistics */ |
177dfcd8 | 1748 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1749 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1750 | ||
7dde596e | 1751 | rtnl_lock(); |
aed0628d BH |
1752 | |
1753 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1754 | if (rc < 0) | |
1755 | goto fail_locked; | |
7dde596e | 1756 | efx_update_name(efx); |
aed0628d BH |
1757 | |
1758 | rc = register_netdevice(net_dev); | |
1759 | if (rc) | |
1760 | goto fail_locked; | |
1761 | ||
1762 | /* Always start with carrier off; PHY events will detect the link */ | |
1763 | netif_carrier_off(efx->net_dev); | |
1764 | ||
7dde596e | 1765 | rtnl_unlock(); |
8ceee660 | 1766 | |
06d5e193 BH |
1767 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1768 | if (rc) { | |
62776d03 BH |
1769 | netif_err(efx, drv, efx->net_dev, |
1770 | "failed to init net dev attributes\n"); | |
06d5e193 BH |
1771 | goto fail_registered; |
1772 | } | |
1773 | ||
8ceee660 | 1774 | return 0; |
06d5e193 | 1775 | |
aed0628d BH |
1776 | fail_locked: |
1777 | rtnl_unlock(); | |
62776d03 | 1778 | netif_err(efx, drv, efx->net_dev, "could not register net dev\n"); |
aed0628d BH |
1779 | return rc; |
1780 | ||
06d5e193 BH |
1781 | fail_registered: |
1782 | unregister_netdev(net_dev); | |
1783 | return rc; | |
8ceee660 BH |
1784 | } |
1785 | ||
1786 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1787 | { | |
f7d12cdc | 1788 | struct efx_channel *channel; |
8ceee660 BH |
1789 | struct efx_tx_queue *tx_queue; |
1790 | ||
1791 | if (!efx->net_dev) | |
1792 | return; | |
1793 | ||
767e468c | 1794 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1795 | |
1796 | /* Free up any skbs still remaining. This has to happen before | |
1797 | * we try to unregister the netdev as running their destructors | |
1798 | * may be needed to get the device ref. count to 0. */ | |
f7d12cdc BH |
1799 | efx_for_each_channel(channel, efx) { |
1800 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
1801 | efx_release_tx_buffers(tx_queue); | |
1802 | } | |
8ceee660 | 1803 | |
55668611 | 1804 | if (efx_dev_registered(efx)) { |
8ceee660 | 1805 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1806 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1807 | unregister_netdev(efx->net_dev); |
1808 | } | |
1809 | } | |
1810 | ||
1811 | /************************************************************************** | |
1812 | * | |
1813 | * Device reset and suspend | |
1814 | * | |
1815 | **************************************************************************/ | |
1816 | ||
2467ca46 BH |
1817 | /* Tears down the entire software state and most of the hardware state |
1818 | * before reset. */ | |
d3245b28 | 1819 | void efx_reset_down(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1820 | { |
8ceee660 BH |
1821 | EFX_ASSERT_RESET_SERIALISED(efx); |
1822 | ||
2467ca46 BH |
1823 | efx_stop_all(efx); |
1824 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1825 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1826 | |
8ceee660 | 1827 | efx_fini_channels(efx); |
4b988280 SH |
1828 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1829 | efx->phy_op->fini(efx); | |
ef2b90ee | 1830 | efx->type->fini(efx); |
8ceee660 BH |
1831 | } |
1832 | ||
2467ca46 BH |
1833 | /* This function will always ensure that the locks acquired in |
1834 | * efx_reset_down() are released. A failure return code indicates | |
1835 | * that we were unable to reinitialise the hardware, and the | |
1836 | * driver should be disabled. If ok is false, then the rx and tx | |
1837 | * engines are not restarted, pending a RESET_DISABLE. */ | |
d3245b28 | 1838 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok) |
8ceee660 BH |
1839 | { |
1840 | int rc; | |
1841 | ||
2467ca46 | 1842 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1843 | |
ef2b90ee | 1844 | rc = efx->type->init(efx); |
8ceee660 | 1845 | if (rc) { |
62776d03 | 1846 | netif_err(efx, drv, efx->net_dev, "failed to initialise NIC\n"); |
eb9f6744 | 1847 | goto fail; |
8ceee660 BH |
1848 | } |
1849 | ||
eb9f6744 BH |
1850 | if (!ok) |
1851 | goto fail; | |
1852 | ||
4b988280 | 1853 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
eb9f6744 BH |
1854 | rc = efx->phy_op->init(efx); |
1855 | if (rc) | |
1856 | goto fail; | |
1857 | if (efx->phy_op->reconfigure(efx)) | |
62776d03 BH |
1858 | netif_err(efx, drv, efx->net_dev, |
1859 | "could not restore PHY settings\n"); | |
4b988280 SH |
1860 | } |
1861 | ||
eb9f6744 | 1862 | efx->mac_op->reconfigure(efx); |
8ceee660 | 1863 | |
eb9f6744 BH |
1864 | efx_init_channels(efx); |
1865 | ||
1866 | mutex_unlock(&efx->spi_lock); | |
1867 | mutex_unlock(&efx->mac_lock); | |
1868 | ||
1869 | efx_start_all(efx); | |
1870 | ||
1871 | return 0; | |
1872 | ||
1873 | fail: | |
1874 | efx->port_initialized = false; | |
2467ca46 | 1875 | |
f4150724 | 1876 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1877 | mutex_unlock(&efx->mac_lock); |
1878 | ||
8ceee660 BH |
1879 | return rc; |
1880 | } | |
1881 | ||
eb9f6744 BH |
1882 | /* Reset the NIC using the specified method. Note that the reset may |
1883 | * fail, in which case the card will be left in an unusable state. | |
8ceee660 | 1884 | * |
eb9f6744 | 1885 | * Caller must hold the rtnl_lock. |
8ceee660 | 1886 | */ |
eb9f6744 | 1887 | int efx_reset(struct efx_nic *efx, enum reset_type method) |
8ceee660 | 1888 | { |
eb9f6744 BH |
1889 | int rc, rc2; |
1890 | bool disabled; | |
8ceee660 | 1891 | |
62776d03 BH |
1892 | netif_info(efx, drv, efx->net_dev, "resetting (%s)\n", |
1893 | RESET_TYPE(method)); | |
8ceee660 | 1894 | |
d3245b28 | 1895 | efx_reset_down(efx, method); |
8ceee660 | 1896 | |
ef2b90ee | 1897 | rc = efx->type->reset(efx, method); |
8ceee660 | 1898 | if (rc) { |
62776d03 | 1899 | netif_err(efx, drv, efx->net_dev, "failed to reset hardware\n"); |
eb9f6744 | 1900 | goto out; |
8ceee660 BH |
1901 | } |
1902 | ||
1903 | /* Allow resets to be rescheduled. */ | |
1904 | efx->reset_pending = RESET_TYPE_NONE; | |
1905 | ||
1906 | /* Reinitialise bus-mastering, which may have been turned off before | |
1907 | * the reset was scheduled. This is still appropriate, even in the | |
1908 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1909 | * can respond to requests. */ | |
1910 | pci_set_master(efx->pci_dev); | |
1911 | ||
eb9f6744 | 1912 | out: |
8ceee660 | 1913 | /* Leave device stopped if necessary */ |
eb9f6744 BH |
1914 | disabled = rc || method == RESET_TYPE_DISABLE; |
1915 | rc2 = efx_reset_up(efx, method, !disabled); | |
1916 | if (rc2) { | |
1917 | disabled = true; | |
1918 | if (!rc) | |
1919 | rc = rc2; | |
8ceee660 BH |
1920 | } |
1921 | ||
eb9f6744 | 1922 | if (disabled) { |
f49a4589 | 1923 | dev_close(efx->net_dev); |
62776d03 | 1924 | netif_err(efx, drv, efx->net_dev, "has been disabled\n"); |
f4bd954e | 1925 | efx->state = STATE_DISABLED; |
f4bd954e | 1926 | } else { |
62776d03 | 1927 | netif_dbg(efx, drv, efx->net_dev, "reset complete\n"); |
f4bd954e | 1928 | } |
8ceee660 BH |
1929 | return rc; |
1930 | } | |
1931 | ||
1932 | /* The worker thread exists so that code that cannot sleep can | |
1933 | * schedule a reset for later. | |
1934 | */ | |
1935 | static void efx_reset_work(struct work_struct *data) | |
1936 | { | |
eb9f6744 | 1937 | struct efx_nic *efx = container_of(data, struct efx_nic, reset_work); |
8ceee660 | 1938 | |
319ba649 SH |
1939 | if (efx->reset_pending == RESET_TYPE_NONE) |
1940 | return; | |
1941 | ||
eb9f6744 BH |
1942 | /* If we're not RUNNING then don't reset. Leave the reset_pending |
1943 | * flag set so that efx_pci_probe_main will be retried */ | |
1944 | if (efx->state != STATE_RUNNING) { | |
62776d03 BH |
1945 | netif_info(efx, drv, efx->net_dev, |
1946 | "scheduled reset quenched. NIC not RUNNING\n"); | |
eb9f6744 BH |
1947 | return; |
1948 | } | |
1949 | ||
1950 | rtnl_lock(); | |
f49a4589 | 1951 | (void)efx_reset(efx, efx->reset_pending); |
eb9f6744 | 1952 | rtnl_unlock(); |
8ceee660 BH |
1953 | } |
1954 | ||
1955 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1956 | { | |
1957 | enum reset_type method; | |
1958 | ||
1959 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
62776d03 BH |
1960 | netif_info(efx, drv, efx->net_dev, |
1961 | "quenching already scheduled reset\n"); | |
8ceee660 BH |
1962 | return; |
1963 | } | |
1964 | ||
1965 | switch (type) { | |
1966 | case RESET_TYPE_INVISIBLE: | |
1967 | case RESET_TYPE_ALL: | |
1968 | case RESET_TYPE_WORLD: | |
1969 | case RESET_TYPE_DISABLE: | |
1970 | method = type; | |
1971 | break; | |
1972 | case RESET_TYPE_RX_RECOVERY: | |
1973 | case RESET_TYPE_RX_DESC_FETCH: | |
1974 | case RESET_TYPE_TX_DESC_FETCH: | |
1975 | case RESET_TYPE_TX_SKIP: | |
1976 | method = RESET_TYPE_INVISIBLE; | |
1977 | break; | |
8880f4ec | 1978 | case RESET_TYPE_MC_FAILURE: |
8ceee660 BH |
1979 | default: |
1980 | method = RESET_TYPE_ALL; | |
1981 | break; | |
1982 | } | |
1983 | ||
1984 | if (method != type) | |
62776d03 BH |
1985 | netif_dbg(efx, drv, efx->net_dev, |
1986 | "scheduling %s reset for %s\n", | |
1987 | RESET_TYPE(method), RESET_TYPE(type)); | |
8ceee660 | 1988 | else |
62776d03 BH |
1989 | netif_dbg(efx, drv, efx->net_dev, "scheduling %s reset\n", |
1990 | RESET_TYPE(method)); | |
8ceee660 BH |
1991 | |
1992 | efx->reset_pending = method; | |
1993 | ||
8880f4ec BH |
1994 | /* efx_process_channel() will no longer read events once a |
1995 | * reset is scheduled. So switch back to poll'd MCDI completions. */ | |
1996 | efx_mcdi_mode_poll(efx); | |
1997 | ||
1ab00629 | 1998 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1999 | } |
2000 | ||
2001 | /************************************************************************** | |
2002 | * | |
2003 | * List of NICs we support | |
2004 | * | |
2005 | **************************************************************************/ | |
2006 | ||
2007 | /* PCI device ID table */ | |
a3aa1884 | 2008 | static DEFINE_PCI_DEVICE_TABLE(efx_pci_table) = { |
8ceee660 | 2009 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), |
daeda630 | 2010 | .driver_data = (unsigned long) &falcon_a1_nic_type}, |
8ceee660 | 2011 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), |
daeda630 | 2012 | .driver_data = (unsigned long) &falcon_b0_nic_type}, |
8880f4ec BH |
2013 | {PCI_DEVICE(EFX_VENDID_SFC, BETHPAGE_A_P_DEVID), |
2014 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
2015 | {PCI_DEVICE(EFX_VENDID_SFC, SIENA_A_P_DEVID), | |
2016 | .driver_data = (unsigned long) &siena_a0_nic_type}, | |
8ceee660 BH |
2017 | {0} /* end of list */ |
2018 | }; | |
2019 | ||
2020 | /************************************************************************** | |
2021 | * | |
3759433d | 2022 | * Dummy PHY/MAC operations |
8ceee660 | 2023 | * |
01aad7b6 | 2024 | * Can be used for some unimplemented operations |
8ceee660 BH |
2025 | * Needed so all function pointers are valid and do not have to be tested |
2026 | * before use | |
2027 | * | |
2028 | **************************************************************************/ | |
2029 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
2030 | { | |
2031 | return 0; | |
2032 | } | |
2033 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
2034 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
2035 | { | |
2036 | } | |
fdaa9aed SH |
2037 | bool efx_port_dummy_op_poll(struct efx_nic *efx) |
2038 | { | |
2039 | return false; | |
2040 | } | |
8ceee660 BH |
2041 | |
2042 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
2043 | .init = efx_port_dummy_op_int, | |
d3245b28 | 2044 | .reconfigure = efx_port_dummy_op_int, |
fdaa9aed | 2045 | .poll = efx_port_dummy_op_poll, |
8ceee660 | 2046 | .fini = efx_port_dummy_op_void, |
8ceee660 BH |
2047 | }; |
2048 | ||
8ceee660 BH |
2049 | /************************************************************************** |
2050 | * | |
2051 | * Data housekeeping | |
2052 | * | |
2053 | **************************************************************************/ | |
2054 | ||
2055 | /* This zeroes out and then fills in the invariants in a struct | |
2056 | * efx_nic (including all sub-structures). | |
2057 | */ | |
2058 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
2059 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
2060 | { | |
2061 | struct efx_channel *channel; | |
2062 | struct efx_tx_queue *tx_queue; | |
2063 | struct efx_rx_queue *rx_queue; | |
8313aca3 | 2064 | int i, j; |
8ceee660 BH |
2065 | |
2066 | /* Initialise common structures */ | |
2067 | memset(efx, 0, sizeof(*efx)); | |
2068 | spin_lock_init(&efx->biu_lock); | |
ab867461 | 2069 | mutex_init(&efx->mdio_lock); |
f4150724 | 2070 | mutex_init(&efx->spi_lock); |
76884835 BH |
2071 | #ifdef CONFIG_SFC_MTD |
2072 | INIT_LIST_HEAD(&efx->mtd_list); | |
2073 | #endif | |
8ceee660 BH |
2074 | INIT_WORK(&efx->reset_work, efx_reset_work); |
2075 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
2076 | efx->pci_dev = pci_dev; | |
62776d03 | 2077 | efx->msg_enable = debug; |
8ceee660 BH |
2078 | efx->state = STATE_INIT; |
2079 | efx->reset_pending = RESET_TYPE_NONE; | |
2080 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
2081 | |
2082 | efx->net_dev = net_dev; | |
dc8cfa55 | 2083 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
2084 | spin_lock_init(&efx->stats_lock); |
2085 | mutex_init(&efx->mac_lock); | |
b895d73e | 2086 | efx->mac_op = type->default_mac_ops; |
8ceee660 | 2087 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 2088 | efx->mdio.dev = net_dev; |
766ca0fa | 2089 | INIT_WORK(&efx->mac_work, efx_mac_work); |
8ceee660 BH |
2090 | |
2091 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
8313aca3 BH |
2092 | efx->channel[i] = kzalloc(sizeof(*channel), GFP_KERNEL); |
2093 | channel = efx->channel[i]; | |
8ceee660 BH |
2094 | channel->efx = efx; |
2095 | channel->channel = i; | |
a4900ac9 BH |
2096 | spin_lock_init(&channel->tx_stop_lock); |
2097 | atomic_set(&channel->tx_stop_count, 1); | |
8313aca3 BH |
2098 | |
2099 | for (j = 0; j < EFX_TXQ_TYPES; j++) { | |
2100 | tx_queue = &channel->tx_queue[j]; | |
2101 | tx_queue->efx = efx; | |
2102 | tx_queue->queue = i * EFX_TXQ_TYPES + j; | |
2103 | tx_queue->channel = channel; | |
2104 | } | |
2105 | ||
2106 | rx_queue = &channel->rx_queue; | |
8ceee660 | 2107 | rx_queue->efx = efx; |
90d683af SH |
2108 | setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill, |
2109 | (unsigned long)rx_queue); | |
8ceee660 BH |
2110 | } |
2111 | ||
2112 | efx->type = type; | |
2113 | ||
8ceee660 BH |
2114 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
2115 | ||
2116 | /* Higher numbered interrupt modes are less capable! */ | |
2117 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2118 | interrupt_mode); | |
2119 | ||
6977dc63 BH |
2120 | /* Would be good to use the net_dev name, but we're too early */ |
2121 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2122 | pci_name(pci_dev)); | |
2123 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2124 | if (!efx->workqueue) |
2125 | return -ENOMEM; | |
8d9853d9 | 2126 | |
8ceee660 | 2127 | return 0; |
8ceee660 BH |
2128 | } |
2129 | ||
2130 | static void efx_fini_struct(struct efx_nic *efx) | |
2131 | { | |
8313aca3 BH |
2132 | int i; |
2133 | ||
2134 | for (i = 0; i < EFX_MAX_CHANNELS; i++) | |
2135 | kfree(efx->channel[i]); | |
2136 | ||
8ceee660 BH |
2137 | if (efx->workqueue) { |
2138 | destroy_workqueue(efx->workqueue); | |
2139 | efx->workqueue = NULL; | |
2140 | } | |
2141 | } | |
2142 | ||
2143 | /************************************************************************** | |
2144 | * | |
2145 | * PCI interface | |
2146 | * | |
2147 | **************************************************************************/ | |
2148 | ||
2149 | /* Main body of final NIC shutdown code | |
2150 | * This is called only at module unload (or hotplug removal). | |
2151 | */ | |
2152 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2153 | { | |
152b6a62 | 2154 | efx_nic_fini_interrupt(efx); |
8ceee660 BH |
2155 | efx_fini_channels(efx); |
2156 | efx_fini_port(efx); | |
ef2b90ee | 2157 | efx->type->fini(efx); |
8ceee660 BH |
2158 | efx_fini_napi(efx); |
2159 | efx_remove_all(efx); | |
2160 | } | |
2161 | ||
2162 | /* Final NIC shutdown | |
2163 | * This is called only at module unload (or hotplug removal). | |
2164 | */ | |
2165 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2166 | { | |
2167 | struct efx_nic *efx; | |
2168 | ||
2169 | efx = pci_get_drvdata(pci_dev); | |
2170 | if (!efx) | |
2171 | return; | |
2172 | ||
2173 | /* Mark the NIC as fini, then stop the interface */ | |
2174 | rtnl_lock(); | |
2175 | efx->state = STATE_FINI; | |
2176 | dev_close(efx->net_dev); | |
2177 | ||
2178 | /* Allow any queued efx_resets() to complete */ | |
2179 | rtnl_unlock(); | |
2180 | ||
8ceee660 BH |
2181 | efx_unregister_netdev(efx); |
2182 | ||
7dde596e BH |
2183 | efx_mtd_remove(efx); |
2184 | ||
8ceee660 BH |
2185 | /* Wait for any scheduled resets to complete. No more will be |
2186 | * scheduled from this point because efx_stop_all() has been | |
2187 | * called, we are no longer registered with driverlink, and | |
2188 | * the net_device's have been removed. */ | |
1ab00629 | 2189 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2190 | |
2191 | efx_pci_remove_main(efx); | |
2192 | ||
8ceee660 | 2193 | efx_fini_io(efx); |
62776d03 | 2194 | netif_dbg(efx, drv, efx->net_dev, "shutdown successful\n"); |
8ceee660 BH |
2195 | |
2196 | pci_set_drvdata(pci_dev, NULL); | |
2197 | efx_fini_struct(efx); | |
2198 | free_netdev(efx->net_dev); | |
2199 | }; | |
2200 | ||
2201 | /* Main body of NIC initialisation | |
2202 | * This is called at module load (or hotplug insertion, theoretically). | |
2203 | */ | |
2204 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2205 | { | |
2206 | int rc; | |
2207 | ||
2208 | /* Do start-of-day initialisation */ | |
2209 | rc = efx_probe_all(efx); | |
2210 | if (rc) | |
2211 | goto fail1; | |
2212 | ||
2213 | rc = efx_init_napi(efx); | |
2214 | if (rc) | |
2215 | goto fail2; | |
2216 | ||
ef2b90ee | 2217 | rc = efx->type->init(efx); |
8ceee660 | 2218 | if (rc) { |
62776d03 BH |
2219 | netif_err(efx, probe, efx->net_dev, |
2220 | "failed to initialise NIC\n"); | |
278c0621 | 2221 | goto fail3; |
8ceee660 BH |
2222 | } |
2223 | ||
2224 | rc = efx_init_port(efx); | |
2225 | if (rc) { | |
62776d03 BH |
2226 | netif_err(efx, probe, efx->net_dev, |
2227 | "failed to initialise port\n"); | |
278c0621 | 2228 | goto fail4; |
8ceee660 BH |
2229 | } |
2230 | ||
bc3c90a2 | 2231 | efx_init_channels(efx); |
8ceee660 | 2232 | |
152b6a62 | 2233 | rc = efx_nic_init_interrupt(efx); |
8ceee660 | 2234 | if (rc) |
278c0621 | 2235 | goto fail5; |
8ceee660 BH |
2236 | |
2237 | return 0; | |
2238 | ||
278c0621 | 2239 | fail5: |
bc3c90a2 | 2240 | efx_fini_channels(efx); |
8ceee660 | 2241 | efx_fini_port(efx); |
8ceee660 | 2242 | fail4: |
ef2b90ee | 2243 | efx->type->fini(efx); |
8ceee660 BH |
2244 | fail3: |
2245 | efx_fini_napi(efx); | |
2246 | fail2: | |
2247 | efx_remove_all(efx); | |
2248 | fail1: | |
2249 | return rc; | |
2250 | } | |
2251 | ||
2252 | /* NIC initialisation | |
2253 | * | |
2254 | * This is called at module load (or hotplug insertion, | |
2255 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2256 | * sets up and registers the network devices with the kernel and hooks | |
2257 | * the interrupt service routine. It does not prepare the device for | |
2258 | * transmission; this is left to the first time one of the network | |
2259 | * interfaces is brought up (i.e. efx_net_open). | |
2260 | */ | |
2261 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2262 | const struct pci_device_id *entry) | |
2263 | { | |
2264 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2265 | struct net_device *net_dev; | |
2266 | struct efx_nic *efx; | |
2267 | int i, rc; | |
2268 | ||
2269 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
a4900ac9 | 2270 | net_dev = alloc_etherdev_mq(sizeof(*efx), EFX_MAX_CORE_TX_QUEUES); |
8ceee660 BH |
2271 | if (!net_dev) |
2272 | return -ENOMEM; | |
c383b537 | 2273 | net_dev->features |= (type->offload_features | NETIF_F_SG | |
97bc5415 BH |
2274 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2275 | NETIF_F_GRO); | |
738a8f4b BH |
2276 | if (type->offload_features & NETIF_F_V6_CSUM) |
2277 | net_dev->features |= NETIF_F_TSO6; | |
28506563 BH |
2278 | /* Mask for features that also apply to VLAN devices */ |
2279 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2280 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2281 | efx = netdev_priv(net_dev); |
8ceee660 | 2282 | pci_set_drvdata(pci_dev, efx); |
62776d03 | 2283 | SET_NETDEV_DEV(net_dev, &pci_dev->dev); |
8ceee660 BH |
2284 | rc = efx_init_struct(efx, type, pci_dev, net_dev); |
2285 | if (rc) | |
2286 | goto fail1; | |
2287 | ||
62776d03 BH |
2288 | netif_info(efx, probe, efx->net_dev, |
2289 | "Solarflare Communications NIC detected\n"); | |
8ceee660 BH |
2290 | |
2291 | /* Set up basic I/O (BAR mappings etc) */ | |
2292 | rc = efx_init_io(efx); | |
2293 | if (rc) | |
2294 | goto fail2; | |
2295 | ||
2296 | /* No serialisation is required with the reset path because | |
2297 | * we're in STATE_INIT. */ | |
2298 | for (i = 0; i < 5; i++) { | |
2299 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2300 | |
2301 | /* Serialise against efx_reset(). No more resets will be | |
2302 | * scheduled since efx_stop_all() has been called, and we | |
2303 | * have not and never have been registered with either | |
2304 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2305 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2306 | |
fa402b2e SH |
2307 | if (rc == 0) { |
2308 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2309 | /* If there was a scheduled reset during | |
2310 | * probe, the NIC is probably hosed anyway */ | |
2311 | efx_pci_remove_main(efx); | |
2312 | rc = -EIO; | |
2313 | } else { | |
2314 | break; | |
2315 | } | |
2316 | } | |
2317 | ||
8ceee660 BH |
2318 | /* Retry if a recoverably reset event has been scheduled */ |
2319 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2320 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2321 | goto fail3; | |
2322 | ||
2323 | efx->reset_pending = RESET_TYPE_NONE; | |
2324 | } | |
2325 | ||
2326 | if (rc) { | |
62776d03 | 2327 | netif_err(efx, probe, efx->net_dev, "Could not reset NIC\n"); |
8ceee660 BH |
2328 | goto fail4; |
2329 | } | |
2330 | ||
55edc6e6 BH |
2331 | /* Switch to the running state before we expose the device to the OS, |
2332 | * so that dev_open()|efx_start_all() will actually start the device */ | |
8ceee660 | 2333 | efx->state = STATE_RUNNING; |
7dde596e | 2334 | |
8ceee660 BH |
2335 | rc = efx_register_netdev(efx); |
2336 | if (rc) | |
2337 | goto fail5; | |
2338 | ||
62776d03 | 2339 | netif_dbg(efx, probe, efx->net_dev, "initialisation successful\n"); |
a5211bb5 BH |
2340 | |
2341 | rtnl_lock(); | |
2342 | efx_mtd_probe(efx); /* allowed to fail */ | |
2343 | rtnl_unlock(); | |
8ceee660 BH |
2344 | return 0; |
2345 | ||
2346 | fail5: | |
2347 | efx_pci_remove_main(efx); | |
2348 | fail4: | |
2349 | fail3: | |
2350 | efx_fini_io(efx); | |
2351 | fail2: | |
2352 | efx_fini_struct(efx); | |
2353 | fail1: | |
5e2a911c | 2354 | WARN_ON(rc > 0); |
62776d03 | 2355 | netif_dbg(efx, drv, efx->net_dev, "initialisation failed. rc=%d\n", rc); |
8ceee660 BH |
2356 | free_netdev(net_dev); |
2357 | return rc; | |
2358 | } | |
2359 | ||
89c758fa BH |
2360 | static int efx_pm_freeze(struct device *dev) |
2361 | { | |
2362 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2363 | ||
2364 | efx->state = STATE_FINI; | |
2365 | ||
2366 | netif_device_detach(efx->net_dev); | |
2367 | ||
2368 | efx_stop_all(efx); | |
2369 | efx_fini_channels(efx); | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
2374 | static int efx_pm_thaw(struct device *dev) | |
2375 | { | |
2376 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
2377 | ||
2378 | efx->state = STATE_INIT; | |
2379 | ||
2380 | efx_init_channels(efx); | |
2381 | ||
2382 | mutex_lock(&efx->mac_lock); | |
2383 | efx->phy_op->reconfigure(efx); | |
2384 | mutex_unlock(&efx->mac_lock); | |
2385 | ||
2386 | efx_start_all(efx); | |
2387 | ||
2388 | netif_device_attach(efx->net_dev); | |
2389 | ||
2390 | efx->state = STATE_RUNNING; | |
2391 | ||
2392 | efx->type->resume_wol(efx); | |
2393 | ||
319ba649 SH |
2394 | /* Reschedule any quenched resets scheduled during efx_pm_freeze() */ |
2395 | queue_work(reset_workqueue, &efx->reset_work); | |
2396 | ||
89c758fa BH |
2397 | return 0; |
2398 | } | |
2399 | ||
2400 | static int efx_pm_poweroff(struct device *dev) | |
2401 | { | |
2402 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2403 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2404 | ||
2405 | efx->type->fini(efx); | |
2406 | ||
2407 | efx->reset_pending = RESET_TYPE_NONE; | |
2408 | ||
2409 | pci_save_state(pci_dev); | |
2410 | return pci_set_power_state(pci_dev, PCI_D3hot); | |
2411 | } | |
2412 | ||
2413 | /* Used for both resume and restore */ | |
2414 | static int efx_pm_resume(struct device *dev) | |
2415 | { | |
2416 | struct pci_dev *pci_dev = to_pci_dev(dev); | |
2417 | struct efx_nic *efx = pci_get_drvdata(pci_dev); | |
2418 | int rc; | |
2419 | ||
2420 | rc = pci_set_power_state(pci_dev, PCI_D0); | |
2421 | if (rc) | |
2422 | return rc; | |
2423 | pci_restore_state(pci_dev); | |
2424 | rc = pci_enable_device(pci_dev); | |
2425 | if (rc) | |
2426 | return rc; | |
2427 | pci_set_master(efx->pci_dev); | |
2428 | rc = efx->type->reset(efx, RESET_TYPE_ALL); | |
2429 | if (rc) | |
2430 | return rc; | |
2431 | rc = efx->type->init(efx); | |
2432 | if (rc) | |
2433 | return rc; | |
2434 | efx_pm_thaw(dev); | |
2435 | return 0; | |
2436 | } | |
2437 | ||
2438 | static int efx_pm_suspend(struct device *dev) | |
2439 | { | |
2440 | int rc; | |
2441 | ||
2442 | efx_pm_freeze(dev); | |
2443 | rc = efx_pm_poweroff(dev); | |
2444 | if (rc) | |
2445 | efx_pm_resume(dev); | |
2446 | return rc; | |
2447 | } | |
2448 | ||
2449 | static struct dev_pm_ops efx_pm_ops = { | |
2450 | .suspend = efx_pm_suspend, | |
2451 | .resume = efx_pm_resume, | |
2452 | .freeze = efx_pm_freeze, | |
2453 | .thaw = efx_pm_thaw, | |
2454 | .poweroff = efx_pm_poweroff, | |
2455 | .restore = efx_pm_resume, | |
2456 | }; | |
2457 | ||
8ceee660 | 2458 | static struct pci_driver efx_pci_driver = { |
c5d5f5fd | 2459 | .name = KBUILD_MODNAME, |
8ceee660 BH |
2460 | .id_table = efx_pci_table, |
2461 | .probe = efx_pci_probe, | |
2462 | .remove = efx_pci_remove, | |
89c758fa | 2463 | .driver.pm = &efx_pm_ops, |
8ceee660 BH |
2464 | }; |
2465 | ||
2466 | /************************************************************************** | |
2467 | * | |
2468 | * Kernel module interface | |
2469 | * | |
2470 | *************************************************************************/ | |
2471 | ||
2472 | module_param(interrupt_mode, uint, 0444); | |
2473 | MODULE_PARM_DESC(interrupt_mode, | |
2474 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2475 | ||
2476 | static int __init efx_init_module(void) | |
2477 | { | |
2478 | int rc; | |
2479 | ||
2480 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2481 | ||
2482 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2483 | if (rc) | |
2484 | goto err_notifier; | |
2485 | ||
1ab00629 SH |
2486 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2487 | if (!reset_workqueue) { | |
2488 | rc = -ENOMEM; | |
2489 | goto err_reset; | |
2490 | } | |
8ceee660 BH |
2491 | |
2492 | rc = pci_register_driver(&efx_pci_driver); | |
2493 | if (rc < 0) | |
2494 | goto err_pci; | |
2495 | ||
2496 | return 0; | |
2497 | ||
2498 | err_pci: | |
1ab00629 SH |
2499 | destroy_workqueue(reset_workqueue); |
2500 | err_reset: | |
8ceee660 BH |
2501 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2502 | err_notifier: | |
2503 | return rc; | |
2504 | } | |
2505 | ||
2506 | static void __exit efx_exit_module(void) | |
2507 | { | |
2508 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2509 | ||
2510 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2511 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2512 | unregister_netdevice_notifier(&efx_netdev_notifier); |
2513 | ||
2514 | } | |
2515 | ||
2516 | module_init(efx_init_module); | |
2517 | module_exit(efx_exit_module); | |
2518 | ||
906bb26c BH |
2519 | MODULE_AUTHOR("Solarflare Communications and " |
2520 | "Michael Brown <mbrown@fensystems.co.uk>"); | |
8ceee660 BH |
2521 | MODULE_DESCRIPTION("Solarflare Communications network driver"); |
2522 | MODULE_LICENSE("GPL"); | |
2523 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |