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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 BH |
16 | #include <linux/i2c.h> |
17 | #include <linux/i2c-algo-bit.h> | |
f31a45d2 | 18 | #include <linux/mii.h> |
8ceee660 BH |
19 | #include "net_driver.h" |
20 | #include "bitfield.h" | |
21 | #include "efx.h" | |
22 | #include "mac.h" | |
8ceee660 BH |
23 | #include "spi.h" |
24 | #include "falcon.h" | |
3e6c4538 | 25 | #include "regs.h" |
12d00cad | 26 | #include "io.h" |
8ceee660 BH |
27 | #include "mdio_10g.h" |
28 | #include "phy.h" | |
8ceee660 BH |
29 | #include "workarounds.h" |
30 | ||
31 | /* Falcon hardware control. | |
32 | * Falcon is the internal codename for the SFC4000 controller that is | |
33 | * present in SFE400X evaluation boards | |
34 | */ | |
35 | ||
36 | /** | |
37 | * struct falcon_nic_data - Falcon NIC state | |
8ceee660 | 38 | * @pci_dev2: The secondary PCI device if present |
37b5a603 | 39 | * @i2c_data: Operations and state for I2C bit-bashing algorithm |
8ceee660 BH |
40 | */ |
41 | struct falcon_nic_data { | |
8ceee660 | 42 | struct pci_dev *pci_dev2; |
37b5a603 | 43 | struct i2c_algo_bit_data i2c_data; |
8ceee660 BH |
44 | }; |
45 | ||
46 | /************************************************************************** | |
47 | * | |
48 | * Configurable values | |
49 | * | |
50 | ************************************************************************** | |
51 | */ | |
52 | ||
53 | static int disable_dma_stats; | |
54 | ||
55 | /* This is set to 16 for a good reason. In summary, if larger than | |
56 | * 16, the descriptor cache holds more than a default socket | |
57 | * buffer's worth of packets (for UDP we can only have at most one | |
58 | * socket buffer's worth outstanding). This combined with the fact | |
59 | * that we only get 1 TX event per descriptor cache means the NIC | |
60 | * goes idle. | |
61 | */ | |
62 | #define TX_DC_ENTRIES 16 | |
63 | #define TX_DC_ENTRIES_ORDER 0 | |
64 | #define TX_DC_BASE 0x130000 | |
65 | ||
66 | #define RX_DC_ENTRIES 64 | |
67 | #define RX_DC_ENTRIES_ORDER 2 | |
68 | #define RX_DC_BASE 0x100000 | |
69 | ||
2f7f5730 BH |
70 | static const unsigned int |
71 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
72 | * 8 KB, 16-bit address, 32 B write block */ | |
73 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
74 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
75 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
76 | /* Default flash device: Atmel AT25F1024 | |
77 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
78 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
79 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
80 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
81 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
82 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
83 | ||
8ceee660 BH |
84 | /* RX FIFO XOFF watermark |
85 | * | |
86 | * When the amount of the RX FIFO increases used increases past this | |
87 | * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A) | |
88 | * This also has an effect on RX/TX arbitration | |
89 | */ | |
90 | static int rx_xoff_thresh_bytes = -1; | |
91 | module_param(rx_xoff_thresh_bytes, int, 0644); | |
92 | MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold"); | |
93 | ||
94 | /* RX FIFO XON watermark | |
95 | * | |
96 | * When the amount of the RX FIFO used decreases below this | |
97 | * watermark send XON. Only used if TX flow control is enabled (ethtool -A) | |
98 | * This also has an effect on RX/TX arbitration | |
99 | */ | |
100 | static int rx_xon_thresh_bytes = -1; | |
101 | module_param(rx_xon_thresh_bytes, int, 0644); | |
102 | MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); | |
103 | ||
2c3c3d02 BH |
104 | /* If FALCON_MAX_INT_ERRORS internal errors occur within |
105 | * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and | |
106 | * disable it. | |
107 | */ | |
108 | #define FALCON_INT_ERROR_EXPIRE 3600 | |
109 | #define FALCON_MAX_INT_ERRORS 5 | |
8ceee660 | 110 | |
6bc5d3a9 BH |
111 | /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times |
112 | */ | |
113 | #define FALCON_FLUSH_INTERVAL 10 | |
114 | #define FALCON_FLUSH_POLL_COUNT 100 | |
8ceee660 BH |
115 | |
116 | /************************************************************************** | |
117 | * | |
118 | * Falcon constants | |
119 | * | |
120 | ************************************************************************** | |
121 | */ | |
122 | ||
8ceee660 BH |
123 | /* Size and alignment of special buffers (4KB) */ |
124 | #define FALCON_BUF_SIZE 4096 | |
125 | ||
126 | /* Dummy SRAM size code */ | |
127 | #define SRM_NB_BSZ_ONCHIP_ONLY (-1) | |
128 | ||
8ceee660 | 129 | #define FALCON_IS_DUAL_FUNC(efx) \ |
55668611 | 130 | (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
131 | |
132 | /************************************************************************** | |
133 | * | |
134 | * Falcon hardware access | |
135 | * | |
136 | **************************************************************************/ | |
137 | ||
12d00cad BH |
138 | static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, |
139 | unsigned int index) | |
140 | { | |
141 | efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, | |
142 | value, index); | |
143 | } | |
144 | ||
8ceee660 BH |
145 | /* Read the current event from the event queue */ |
146 | static inline efx_qword_t *falcon_event(struct efx_channel *channel, | |
147 | unsigned int index) | |
148 | { | |
149 | return (((efx_qword_t *) (channel->eventq.addr)) + index); | |
150 | } | |
151 | ||
152 | /* See if an event is present | |
153 | * | |
154 | * We check both the high and low dword of the event for all ones. We | |
155 | * wrote all ones when we cleared the event, and no valid event can | |
156 | * have all ones in either its high or low dwords. This approach is | |
157 | * robust against reordering. | |
158 | * | |
159 | * Note that using a single 64-bit comparison is incorrect; even | |
160 | * though the CPU read will be atomic, the DMA write may not be. | |
161 | */ | |
162 | static inline int falcon_event_present(efx_qword_t *event) | |
163 | { | |
164 | return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
165 | EFX_DWORD_IS_ALL_ONES(event->dword[1]))); | |
166 | } | |
167 | ||
168 | /************************************************************************** | |
169 | * | |
170 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
171 | * Note that it uses the output enables to tristate the outputs | |
172 | * SDA is the data pin and SCL is the clock | |
173 | * | |
174 | ************************************************************************** | |
175 | */ | |
37b5a603 | 176 | static void falcon_setsda(void *data, int state) |
8ceee660 | 177 | { |
37b5a603 | 178 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
179 | efx_oword_t reg; |
180 | ||
12d00cad | 181 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 182 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 183 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
184 | } |
185 | ||
37b5a603 | 186 | static void falcon_setscl(void *data, int state) |
8ceee660 | 187 | { |
37b5a603 | 188 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
189 | efx_oword_t reg; |
190 | ||
12d00cad | 191 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 192 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 193 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
194 | } |
195 | ||
196 | static int falcon_getsda(void *data) | |
197 | { | |
198 | struct efx_nic *efx = (struct efx_nic *)data; | |
199 | efx_oword_t reg; | |
200 | ||
12d00cad | 201 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 202 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); |
8ceee660 BH |
203 | } |
204 | ||
37b5a603 | 205 | static int falcon_getscl(void *data) |
8ceee660 | 206 | { |
37b5a603 | 207 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
208 | efx_oword_t reg; |
209 | ||
12d00cad | 210 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 211 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); |
8ceee660 BH |
212 | } |
213 | ||
37b5a603 BH |
214 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
215 | .setsda = falcon_setsda, | |
216 | .setscl = falcon_setscl, | |
8ceee660 BH |
217 | .getsda = falcon_getsda, |
218 | .getscl = falcon_getscl, | |
62c78329 | 219 | .udelay = 5, |
9dadae68 BH |
220 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
221 | .timeout = DIV_ROUND_UP(HZ, 20), | |
8ceee660 BH |
222 | }; |
223 | ||
224 | /************************************************************************** | |
225 | * | |
226 | * Falcon special buffer handling | |
227 | * Special buffers are used for event queues and the TX and RX | |
228 | * descriptor rings. | |
229 | * | |
230 | *************************************************************************/ | |
231 | ||
232 | /* | |
233 | * Initialise a Falcon special buffer | |
234 | * | |
235 | * This will define a buffer (previously allocated via | |
236 | * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing | |
237 | * it to be used for event queues, descriptor rings etc. | |
238 | */ | |
bc3c90a2 | 239 | static void |
8ceee660 BH |
240 | falcon_init_special_buffer(struct efx_nic *efx, |
241 | struct efx_special_buffer *buffer) | |
242 | { | |
243 | efx_qword_t buf_desc; | |
244 | int index; | |
245 | dma_addr_t dma_addr; | |
246 | int i; | |
247 | ||
248 | EFX_BUG_ON_PARANOID(!buffer->addr); | |
249 | ||
250 | /* Write buffer descriptors to NIC */ | |
251 | for (i = 0; i < buffer->entries; i++) { | |
252 | index = buffer->index + i; | |
253 | dma_addr = buffer->dma_addr + (i * 4096); | |
254 | EFX_LOG(efx, "mapping special buffer %d at %llx\n", | |
255 | index, (unsigned long long)dma_addr); | |
3e6c4538 BH |
256 | EFX_POPULATE_QWORD_3(buf_desc, |
257 | FRF_AZ_BUF_ADR_REGION, 0, | |
258 | FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, | |
259 | FRF_AZ_BUF_OWNER_ID_FBUF, 0); | |
12d00cad | 260 | falcon_write_buf_tbl(efx, &buf_desc, index); |
8ceee660 | 261 | } |
8ceee660 BH |
262 | } |
263 | ||
264 | /* Unmaps a buffer from Falcon and clears the buffer table entries */ | |
265 | static void | |
266 | falcon_fini_special_buffer(struct efx_nic *efx, | |
267 | struct efx_special_buffer *buffer) | |
268 | { | |
269 | efx_oword_t buf_tbl_upd; | |
270 | unsigned int start = buffer->index; | |
271 | unsigned int end = (buffer->index + buffer->entries - 1); | |
272 | ||
273 | if (!buffer->entries) | |
274 | return; | |
275 | ||
276 | EFX_LOG(efx, "unmapping special buffers %d-%d\n", | |
277 | buffer->index, buffer->index + buffer->entries - 1); | |
278 | ||
279 | EFX_POPULATE_OWORD_4(buf_tbl_upd, | |
3e6c4538 BH |
280 | FRF_AZ_BUF_UPD_CMD, 0, |
281 | FRF_AZ_BUF_CLR_CMD, 1, | |
282 | FRF_AZ_BUF_CLR_END_ID, end, | |
283 | FRF_AZ_BUF_CLR_START_ID, start); | |
12d00cad | 284 | efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); |
8ceee660 BH |
285 | } |
286 | ||
287 | /* | |
288 | * Allocate a new Falcon special buffer | |
289 | * | |
290 | * This allocates memory for a new buffer, clears it and allocates a | |
291 | * new buffer ID range. It does not write into Falcon's buffer table. | |
292 | * | |
293 | * This call will allocate 4KB buffers, since Falcon can't use 8KB | |
294 | * buffers for event queues and descriptor rings. | |
295 | */ | |
296 | static int falcon_alloc_special_buffer(struct efx_nic *efx, | |
297 | struct efx_special_buffer *buffer, | |
298 | unsigned int len) | |
299 | { | |
8ceee660 BH |
300 | len = ALIGN(len, FALCON_BUF_SIZE); |
301 | ||
302 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
303 | &buffer->dma_addr); | |
304 | if (!buffer->addr) | |
305 | return -ENOMEM; | |
306 | buffer->len = len; | |
307 | buffer->entries = len / FALCON_BUF_SIZE; | |
308 | BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1)); | |
309 | ||
310 | /* All zeros is a potentially valid event so memset to 0xff */ | |
311 | memset(buffer->addr, 0xff, len); | |
312 | ||
313 | /* Select new buffer ID */ | |
0484e0db BH |
314 | buffer->index = efx->next_buffer_table; |
315 | efx->next_buffer_table += buffer->entries; | |
8ceee660 BH |
316 | |
317 | EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 318 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 319 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
320 | (u64)buffer->dma_addr, len, |
321 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
322 | |
323 | return 0; | |
324 | } | |
325 | ||
326 | static void falcon_free_special_buffer(struct efx_nic *efx, | |
327 | struct efx_special_buffer *buffer) | |
328 | { | |
329 | if (!buffer->addr) | |
330 | return; | |
331 | ||
332 | EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 333 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 334 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
335 | (u64)buffer->dma_addr, buffer->len, |
336 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
337 | |
338 | pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr, | |
339 | buffer->dma_addr); | |
340 | buffer->addr = NULL; | |
341 | buffer->entries = 0; | |
342 | } | |
343 | ||
344 | /************************************************************************** | |
345 | * | |
346 | * Falcon generic buffer handling | |
347 | * These buffers are used for interrupt status and MAC stats | |
348 | * | |
349 | **************************************************************************/ | |
350 | ||
351 | static int falcon_alloc_buffer(struct efx_nic *efx, | |
352 | struct efx_buffer *buffer, unsigned int len) | |
353 | { | |
354 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
355 | &buffer->dma_addr); | |
356 | if (!buffer->addr) | |
357 | return -ENOMEM; | |
358 | buffer->len = len; | |
359 | memset(buffer->addr, 0, len); | |
360 | return 0; | |
361 | } | |
362 | ||
363 | static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) | |
364 | { | |
365 | if (buffer->addr) { | |
366 | pci_free_consistent(efx->pci_dev, buffer->len, | |
367 | buffer->addr, buffer->dma_addr); | |
368 | buffer->addr = NULL; | |
369 | } | |
370 | } | |
371 | ||
372 | /************************************************************************** | |
373 | * | |
374 | * Falcon TX path | |
375 | * | |
376 | **************************************************************************/ | |
377 | ||
378 | /* Returns a pointer to the specified transmit descriptor in the TX | |
379 | * descriptor queue belonging to the specified channel. | |
380 | */ | |
381 | static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue, | |
382 | unsigned int index) | |
383 | { | |
384 | return (((efx_qword_t *) (tx_queue->txd.addr)) + index); | |
385 | } | |
386 | ||
387 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
388 | static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
389 | { | |
390 | unsigned write_ptr; | |
391 | efx_dword_t reg; | |
392 | ||
3ffeabdd | 393 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
3e6c4538 | 394 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
395 | efx_writed_page(tx_queue->efx, ®, |
396 | FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); | |
8ceee660 BH |
397 | } |
398 | ||
399 | ||
400 | /* For each entry inserted into the software descriptor ring, create a | |
401 | * descriptor in the hardware TX descriptor ring (in host memory), and | |
402 | * write a doorbell. | |
403 | */ | |
404 | void falcon_push_buffers(struct efx_tx_queue *tx_queue) | |
405 | { | |
406 | ||
407 | struct efx_tx_buffer *buffer; | |
408 | efx_qword_t *txd; | |
409 | unsigned write_ptr; | |
410 | ||
411 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
412 | ||
413 | do { | |
3ffeabdd | 414 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
8ceee660 BH |
415 | buffer = &tx_queue->buffer[write_ptr]; |
416 | txd = falcon_tx_desc(tx_queue, write_ptr); | |
417 | ++tx_queue->write_count; | |
418 | ||
419 | /* Create TX descriptor ring entry */ | |
3e6c4538 BH |
420 | EFX_POPULATE_QWORD_4(*txd, |
421 | FSF_AZ_TX_KER_CONT, buffer->continuation, | |
422 | FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, | |
423 | FSF_AZ_TX_KER_BUF_REGION, 0, | |
424 | FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
8ceee660 BH |
425 | } while (tx_queue->write_count != tx_queue->insert_count); |
426 | ||
427 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
428 | falcon_notify_tx_desc(tx_queue); | |
429 | } | |
430 | ||
431 | /* Allocate hardware resources for a TX queue */ | |
432 | int falcon_probe_tx(struct efx_tx_queue *tx_queue) | |
433 | { | |
434 | struct efx_nic *efx = tx_queue->efx; | |
3ffeabdd BH |
435 | BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 || |
436 | EFX_TXQ_SIZE & EFX_TXQ_MASK); | |
8ceee660 | 437 | return falcon_alloc_special_buffer(efx, &tx_queue->txd, |
3ffeabdd | 438 | EFX_TXQ_SIZE * sizeof(efx_qword_t)); |
8ceee660 BH |
439 | } |
440 | ||
bc3c90a2 | 441 | void falcon_init_tx(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
442 | { |
443 | efx_oword_t tx_desc_ptr; | |
444 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 445 | |
6bc5d3a9 BH |
446 | tx_queue->flushed = false; |
447 | ||
8ceee660 | 448 | /* Pin TX descriptor ring */ |
bc3c90a2 | 449 | falcon_init_special_buffer(efx, &tx_queue->txd); |
8ceee660 BH |
450 | |
451 | /* Push TX descriptor ring to card */ | |
452 | EFX_POPULATE_OWORD_10(tx_desc_ptr, | |
3e6c4538 BH |
453 | FRF_AZ_TX_DESCQ_EN, 1, |
454 | FRF_AZ_TX_ISCSI_DDIG_EN, 0, | |
455 | FRF_AZ_TX_ISCSI_HDIG_EN, 0, | |
456 | FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, | |
457 | FRF_AZ_TX_DESCQ_EVQ_ID, | |
458 | tx_queue->channel->channel, | |
459 | FRF_AZ_TX_DESCQ_OWNER_ID, 0, | |
460 | FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, | |
3ffeabdd BH |
461 | FRF_AZ_TX_DESCQ_SIZE, |
462 | __ffs(tx_queue->txd.entries), | |
3e6c4538 BH |
463 | FRF_AZ_TX_DESCQ_TYPE, 0, |
464 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); | |
8ceee660 | 465 | |
55668611 | 466 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
60ac1065 | 467 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; |
3e6c4538 BH |
468 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); |
469 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, | |
470 | !csum); | |
8ceee660 BH |
471 | } |
472 | ||
12d00cad BH |
473 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
474 | tx_queue->queue); | |
8ceee660 | 475 | |
55668611 | 476 | if (falcon_rev(efx) < FALCON_REV_B0) { |
8ceee660 BH |
477 | efx_oword_t reg; |
478 | ||
60ac1065 BH |
479 | /* Only 128 bits in this register */ |
480 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); | |
8ceee660 | 481 | |
12d00cad | 482 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); |
60ac1065 | 483 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) |
8ceee660 BH |
484 | clear_bit_le(tx_queue->queue, (void *)®); |
485 | else | |
486 | set_bit_le(tx_queue->queue, (void *)®); | |
12d00cad | 487 | efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); |
8ceee660 | 488 | } |
8ceee660 BH |
489 | } |
490 | ||
6bc5d3a9 | 491 | static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
492 | { |
493 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 494 | efx_oword_t tx_flush_descq; |
8ceee660 BH |
495 | |
496 | /* Post a flush command */ | |
497 | EFX_POPULATE_OWORD_2(tx_flush_descq, | |
3e6c4538 BH |
498 | FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, |
499 | FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); | |
12d00cad | 500 | efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); |
8ceee660 BH |
501 | } |
502 | ||
503 | void falcon_fini_tx(struct efx_tx_queue *tx_queue) | |
504 | { | |
505 | struct efx_nic *efx = tx_queue->efx; | |
506 | efx_oword_t tx_desc_ptr; | |
507 | ||
6bc5d3a9 BH |
508 | /* The queue should have been flushed */ |
509 | WARN_ON(!tx_queue->flushed); | |
8ceee660 BH |
510 | |
511 | /* Remove TX descriptor ring from card */ | |
512 | EFX_ZERO_OWORD(tx_desc_ptr); | |
12d00cad BH |
513 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
514 | tx_queue->queue); | |
8ceee660 BH |
515 | |
516 | /* Unpin TX descriptor ring */ | |
517 | falcon_fini_special_buffer(efx, &tx_queue->txd); | |
518 | } | |
519 | ||
520 | /* Free buffers backing TX queue */ | |
521 | void falcon_remove_tx(struct efx_tx_queue *tx_queue) | |
522 | { | |
523 | falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd); | |
524 | } | |
525 | ||
526 | /************************************************************************** | |
527 | * | |
528 | * Falcon RX path | |
529 | * | |
530 | **************************************************************************/ | |
531 | ||
532 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
533 | static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue, | |
534 | unsigned int index) | |
535 | { | |
536 | return (((efx_qword_t *) (rx_queue->rxd.addr)) + index); | |
537 | } | |
538 | ||
539 | /* This creates an entry in the RX descriptor queue */ | |
540 | static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue, | |
541 | unsigned index) | |
542 | { | |
543 | struct efx_rx_buffer *rx_buf; | |
544 | efx_qword_t *rxd; | |
545 | ||
546 | rxd = falcon_rx_desc(rx_queue, index); | |
547 | rx_buf = efx_rx_buffer(rx_queue, index); | |
548 | EFX_POPULATE_QWORD_3(*rxd, | |
3e6c4538 | 549 | FSF_AZ_RX_KER_BUF_SIZE, |
8ceee660 BH |
550 | rx_buf->len - |
551 | rx_queue->efx->type->rx_buffer_padding, | |
3e6c4538 BH |
552 | FSF_AZ_RX_KER_BUF_REGION, 0, |
553 | FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
8ceee660 BH |
554 | } |
555 | ||
556 | /* This writes to the RX_DESC_WPTR register for the specified receive | |
557 | * descriptor ring. | |
558 | */ | |
559 | void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
560 | { | |
561 | efx_dword_t reg; | |
562 | unsigned write_ptr; | |
563 | ||
564 | while (rx_queue->notified_count != rx_queue->added_count) { | |
565 | falcon_build_rx_desc(rx_queue, | |
566 | rx_queue->notified_count & | |
3ffeabdd | 567 | EFX_RXQ_MASK); |
8ceee660 BH |
568 | ++rx_queue->notified_count; |
569 | } | |
570 | ||
571 | wmb(); | |
3ffeabdd | 572 | write_ptr = rx_queue->added_count & EFX_RXQ_MASK; |
3e6c4538 | 573 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
574 | efx_writed_page(rx_queue->efx, ®, |
575 | FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue); | |
8ceee660 BH |
576 | } |
577 | ||
578 | int falcon_probe_rx(struct efx_rx_queue *rx_queue) | |
579 | { | |
580 | struct efx_nic *efx = rx_queue->efx; | |
3ffeabdd BH |
581 | BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 || |
582 | EFX_RXQ_SIZE & EFX_RXQ_MASK); | |
8ceee660 | 583 | return falcon_alloc_special_buffer(efx, &rx_queue->rxd, |
3ffeabdd | 584 | EFX_RXQ_SIZE * sizeof(efx_qword_t)); |
8ceee660 BH |
585 | } |
586 | ||
bc3c90a2 | 587 | void falcon_init_rx(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
588 | { |
589 | efx_oword_t rx_desc_ptr; | |
590 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
591 | bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0; |
592 | bool iscsi_digest_en = is_b0; | |
8ceee660 BH |
593 | |
594 | EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n", | |
595 | rx_queue->queue, rx_queue->rxd.index, | |
596 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); | |
597 | ||
6bc5d3a9 BH |
598 | rx_queue->flushed = false; |
599 | ||
8ceee660 | 600 | /* Pin RX descriptor ring */ |
bc3c90a2 | 601 | falcon_init_special_buffer(efx, &rx_queue->rxd); |
8ceee660 BH |
602 | |
603 | /* Push RX descriptor ring to card */ | |
604 | EFX_POPULATE_OWORD_10(rx_desc_ptr, | |
3e6c4538 BH |
605 | FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, |
606 | FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, | |
607 | FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, | |
608 | FRF_AZ_RX_DESCQ_EVQ_ID, | |
609 | rx_queue->channel->channel, | |
610 | FRF_AZ_RX_DESCQ_OWNER_ID, 0, | |
611 | FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue, | |
3ffeabdd BH |
612 | FRF_AZ_RX_DESCQ_SIZE, |
613 | __ffs(rx_queue->rxd.entries), | |
3e6c4538 | 614 | FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , |
8ceee660 | 615 | /* For >=B0 this is scatter so disable */ |
3e6c4538 BH |
616 | FRF_AZ_RX_DESCQ_JUMBO, !is_b0, |
617 | FRF_AZ_RX_DESCQ_EN, 1); | |
12d00cad BH |
618 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
619 | rx_queue->queue); | |
8ceee660 BH |
620 | } |
621 | ||
6bc5d3a9 | 622 | static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
623 | { |
624 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 BH |
625 | efx_oword_t rx_flush_descq; |
626 | ||
627 | /* Post a flush command */ | |
628 | EFX_POPULATE_OWORD_2(rx_flush_descq, | |
3e6c4538 BH |
629 | FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, |
630 | FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue); | |
12d00cad | 631 | efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); |
8ceee660 BH |
632 | } |
633 | ||
634 | void falcon_fini_rx(struct efx_rx_queue *rx_queue) | |
635 | { | |
636 | efx_oword_t rx_desc_ptr; | |
637 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 | 638 | |
6bc5d3a9 BH |
639 | /* The queue should already have been flushed */ |
640 | WARN_ON(!rx_queue->flushed); | |
8ceee660 BH |
641 | |
642 | /* Remove RX descriptor ring from card */ | |
643 | EFX_ZERO_OWORD(rx_desc_ptr); | |
12d00cad BH |
644 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
645 | rx_queue->queue); | |
8ceee660 BH |
646 | |
647 | /* Unpin RX descriptor ring */ | |
648 | falcon_fini_special_buffer(efx, &rx_queue->rxd); | |
649 | } | |
650 | ||
651 | /* Free buffers backing RX queue */ | |
652 | void falcon_remove_rx(struct efx_rx_queue *rx_queue) | |
653 | { | |
654 | falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd); | |
655 | } | |
656 | ||
657 | /************************************************************************** | |
658 | * | |
659 | * Falcon event queue processing | |
660 | * Event queues are processed by per-channel tasklets. | |
661 | * | |
662 | **************************************************************************/ | |
663 | ||
664 | /* Update a channel's event queue's read pointer (RPTR) register | |
665 | * | |
666 | * This writes the EVQ_RPTR_REG register for the specified channel's | |
667 | * event queue. | |
668 | * | |
669 | * Note that EVQ_RPTR_REG contains the index of the "last read" event, | |
670 | * whereas channel->eventq_read_ptr contains the index of the "next to | |
671 | * read" event. | |
672 | */ | |
673 | void falcon_eventq_read_ack(struct efx_channel *channel) | |
674 | { | |
675 | efx_dword_t reg; | |
676 | struct efx_nic *efx = channel->efx; | |
677 | ||
3e6c4538 | 678 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr); |
12d00cad | 679 | efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, |
d3074025 | 680 | channel->channel); |
8ceee660 BH |
681 | } |
682 | ||
683 | /* Use HW to insert a SW defined event */ | |
684 | void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event) | |
685 | { | |
686 | efx_oword_t drv_ev_reg; | |
687 | ||
3e6c4538 BH |
688 | BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || |
689 | FRF_AZ_DRV_EV_DATA_WIDTH != 64); | |
690 | drv_ev_reg.u32[0] = event->u32[0]; | |
691 | drv_ev_reg.u32[1] = event->u32[1]; | |
692 | drv_ev_reg.u32[2] = 0; | |
693 | drv_ev_reg.u32[3] = 0; | |
694 | EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); | |
12d00cad | 695 | efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); |
8ceee660 BH |
696 | } |
697 | ||
698 | /* Handle a transmit completion event | |
699 | * | |
700 | * Falcon batches TX completion events; the message we receive is of | |
701 | * the form "complete all TX events up to this index". | |
702 | */ | |
4d566063 BH |
703 | static void falcon_handle_tx_event(struct efx_channel *channel, |
704 | efx_qword_t *event) | |
8ceee660 BH |
705 | { |
706 | unsigned int tx_ev_desc_ptr; | |
707 | unsigned int tx_ev_q_label; | |
708 | struct efx_tx_queue *tx_queue; | |
709 | struct efx_nic *efx = channel->efx; | |
710 | ||
3e6c4538 | 711 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { |
8ceee660 | 712 | /* Transmit completion */ |
3e6c4538 BH |
713 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); |
714 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | |
8ceee660 | 715 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
6fb70fd1 BH |
716 | channel->irq_mod_score += |
717 | (tx_ev_desc_ptr - tx_queue->read_count) & | |
3ffeabdd | 718 | EFX_TXQ_MASK; |
8ceee660 | 719 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); |
3e6c4538 | 720 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { |
8ceee660 | 721 | /* Rewrite the FIFO write pointer */ |
3e6c4538 | 722 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
8ceee660 BH |
723 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
724 | ||
55668611 | 725 | if (efx_dev_registered(efx)) |
8ceee660 BH |
726 | netif_tx_lock(efx->net_dev); |
727 | falcon_notify_tx_desc(tx_queue); | |
55668611 | 728 | if (efx_dev_registered(efx)) |
8ceee660 | 729 | netif_tx_unlock(efx->net_dev); |
3e6c4538 | 730 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && |
8ceee660 BH |
731 | EFX_WORKAROUND_10727(efx)) { |
732 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
733 | } else { | |
734 | EFX_ERR(efx, "channel %d unexpected TX event " | |
735 | EFX_QWORD_FMT"\n", channel->channel, | |
736 | EFX_QWORD_VAL(*event)); | |
737 | } | |
738 | } | |
739 | ||
8ceee660 BH |
740 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
741 | static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue, | |
742 | const efx_qword_t *event, | |
dc8cfa55 BH |
743 | bool *rx_ev_pkt_ok, |
744 | bool *discard) | |
8ceee660 BH |
745 | { |
746 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
747 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; |
748 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; | |
749 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; | |
750 | bool rx_ev_other_err, rx_ev_pause_frm; | |
751 | bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt; | |
752 | unsigned rx_ev_pkt_type; | |
8ceee660 | 753 | |
3e6c4538 BH |
754 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); |
755 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); | |
756 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); | |
757 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); | |
8ceee660 | 758 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
759 | FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); |
760 | rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR); | |
8ceee660 | 761 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 | 762 | FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); |
8ceee660 | 763 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
764 | FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); |
765 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); | |
766 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); | |
55668611 | 767 | rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ? |
3e6c4538 BH |
768 | 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); |
769 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); | |
8ceee660 BH |
770 | |
771 | /* Every error apart from tobe_disc and pause_frm */ | |
772 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | | |
773 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | | |
774 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); | |
775 | ||
50050877 BH |
776 | /* Count errors that are not in MAC stats. Ignore expected |
777 | * checksum errors during self-test. */ | |
8ceee660 BH |
778 | if (rx_ev_frm_trunc) |
779 | ++rx_queue->channel->n_rx_frm_trunc; | |
780 | else if (rx_ev_tobe_disc) | |
781 | ++rx_queue->channel->n_rx_tobe_disc; | |
50050877 BH |
782 | else if (!efx->loopback_selftest) { |
783 | if (rx_ev_ip_hdr_chksum_err) | |
784 | ++rx_queue->channel->n_rx_ip_hdr_chksum_err; | |
785 | else if (rx_ev_tcp_udp_chksum_err) | |
786 | ++rx_queue->channel->n_rx_tcp_udp_chksum_err; | |
787 | } | |
8ceee660 BH |
788 | if (rx_ev_ip_frag_err) |
789 | ++rx_queue->channel->n_rx_ip_frag_err; | |
790 | ||
791 | /* The frame must be discarded if any of these are true. */ | |
792 | *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | | |
793 | rx_ev_tobe_disc | rx_ev_pause_frm); | |
794 | ||
795 | /* TOBE_DISC is expected on unicast mismatches; don't print out an | |
796 | * error message. FRM_TRUNC indicates RXDP dropped the packet due | |
797 | * to a FIFO overflow. | |
798 | */ | |
799 | #ifdef EFX_ENABLE_DEBUG | |
800 | if (rx_ev_other_err) { | |
801 | EFX_INFO_RL(efx, " RX queue %d unexpected RX event " | |
5b39fe30 | 802 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", |
8ceee660 BH |
803 | rx_queue->queue, EFX_QWORD_VAL(*event), |
804 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", | |
805 | rx_ev_ip_hdr_chksum_err ? | |
806 | " [IP_HDR_CHKSUM_ERR]" : "", | |
807 | rx_ev_tcp_udp_chksum_err ? | |
808 | " [TCP_UDP_CHKSUM_ERR]" : "", | |
809 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", | |
810 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", | |
811 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", | |
812 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", | |
5b39fe30 | 813 | rx_ev_pause_frm ? " [PAUSE]" : ""); |
8ceee660 BH |
814 | } |
815 | #endif | |
8ceee660 BH |
816 | } |
817 | ||
818 | /* Handle receive events that are not in-order. */ | |
819 | static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue, | |
820 | unsigned index) | |
821 | { | |
822 | struct efx_nic *efx = rx_queue->efx; | |
823 | unsigned expected, dropped; | |
824 | ||
3ffeabdd BH |
825 | expected = rx_queue->removed_count & EFX_RXQ_MASK; |
826 | dropped = (index - expected) & EFX_RXQ_MASK; | |
8ceee660 BH |
827 | EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n", |
828 | dropped, index, expected); | |
829 | ||
830 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? | |
831 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
832 | } | |
833 | ||
834 | /* Handle a packet received event | |
835 | * | |
836 | * Falcon silicon gives a "discard" flag if it's a unicast packet with the | |
837 | * wrong destination address | |
838 | * Also "is multicast" and "matches multicast filter" flags can be used to | |
839 | * discard non-matching multicast packets. | |
840 | */ | |
42cbe2d7 BH |
841 | static void falcon_handle_rx_event(struct efx_channel *channel, |
842 | const efx_qword_t *event) | |
8ceee660 | 843 | { |
42cbe2d7 | 844 | unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; |
dc8cfa55 | 845 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; |
8ceee660 | 846 | unsigned expected_ptr; |
dc8cfa55 | 847 | bool rx_ev_pkt_ok, discard = false, checksummed; |
8ceee660 BH |
848 | struct efx_rx_queue *rx_queue; |
849 | struct efx_nic *efx = channel->efx; | |
850 | ||
851 | /* Basic packet information */ | |
3e6c4538 BH |
852 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); |
853 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); | |
854 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); | |
855 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); | |
856 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); | |
857 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != | |
858 | channel->channel); | |
8ceee660 | 859 | |
42cbe2d7 | 860 | rx_queue = &efx->rx_queue[channel->channel]; |
8ceee660 | 861 | |
3e6c4538 | 862 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); |
3ffeabdd | 863 | expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK; |
42cbe2d7 | 864 | if (unlikely(rx_ev_desc_ptr != expected_ptr)) |
8ceee660 | 865 | falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); |
8ceee660 BH |
866 | |
867 | if (likely(rx_ev_pkt_ok)) { | |
868 | /* If packet is marked as OK and packet type is TCP/IPv4 or | |
869 | * UDP/IPv4, then we can rely on the hardware checksum. | |
870 | */ | |
3e6c4538 BH |
871 | checksummed = |
872 | rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP || | |
873 | rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP; | |
8ceee660 BH |
874 | } else { |
875 | falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, | |
5b39fe30 | 876 | &discard); |
dc8cfa55 | 877 | checksummed = false; |
8ceee660 BH |
878 | } |
879 | ||
880 | /* Detect multicast packets that didn't match the filter */ | |
3e6c4538 | 881 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); |
8ceee660 BH |
882 | if (rx_ev_mcast_pkt) { |
883 | unsigned int rx_ev_mcast_hash_match = | |
3e6c4538 | 884 | EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); |
8ceee660 BH |
885 | |
886 | if (unlikely(!rx_ev_mcast_hash_match)) | |
dc8cfa55 | 887 | discard = true; |
8ceee660 BH |
888 | } |
889 | ||
6fb70fd1 BH |
890 | channel->irq_mod_score += 2; |
891 | ||
8ceee660 BH |
892 | /* Handle received packet */ |
893 | efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, | |
894 | checksummed, discard); | |
8ceee660 BH |
895 | } |
896 | ||
897 | /* Global events are basically PHY events */ | |
898 | static void falcon_handle_global_event(struct efx_channel *channel, | |
899 | efx_qword_t *event) | |
900 | { | |
901 | struct efx_nic *efx = channel->efx; | |
766ca0fa | 902 | bool handled = false; |
8ceee660 | 903 | |
3e6c4538 BH |
904 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || |
905 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
906 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) { | |
766ca0fa BH |
907 | efx->phy_op->clear_interrupt(efx); |
908 | queue_work(efx->workqueue, &efx->phy_work); | |
909 | handled = true; | |
910 | } | |
8ceee660 | 911 | |
55668611 | 912 | if ((falcon_rev(efx) >= FALCON_REV_B0) && |
3e6c4538 | 913 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { |
766ca0fa | 914 | queue_work(efx->workqueue, &efx->mac_work); |
dc8cfa55 | 915 | handled = true; |
8ceee660 BH |
916 | } |
917 | ||
56241ceb | 918 | if (falcon_rev(efx) <= FALCON_REV_A1 ? |
3e6c4538 BH |
919 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : |
920 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
8ceee660 BH |
921 | EFX_ERR(efx, "channel %d seen global RX_RESET " |
922 | "event. Resetting.\n", channel->channel); | |
923 | ||
924 | atomic_inc(&efx->rx_reset); | |
925 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
926 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
dc8cfa55 | 927 | handled = true; |
8ceee660 BH |
928 | } |
929 | ||
930 | if (!handled) | |
931 | EFX_ERR(efx, "channel %d unknown global event " | |
932 | EFX_QWORD_FMT "\n", channel->channel, | |
933 | EFX_QWORD_VAL(*event)); | |
934 | } | |
935 | ||
936 | static void falcon_handle_driver_event(struct efx_channel *channel, | |
937 | efx_qword_t *event) | |
938 | { | |
939 | struct efx_nic *efx = channel->efx; | |
940 | unsigned int ev_sub_code; | |
941 | unsigned int ev_sub_data; | |
942 | ||
3e6c4538 BH |
943 | ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); |
944 | ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); | |
8ceee660 BH |
945 | |
946 | switch (ev_sub_code) { | |
3e6c4538 | 947 | case FSE_AZ_TX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
948 | EFX_TRACE(efx, "channel %d TXQ %d flushed\n", |
949 | channel->channel, ev_sub_data); | |
950 | break; | |
3e6c4538 | 951 | case FSE_AZ_RX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
952 | EFX_TRACE(efx, "channel %d RXQ %d flushed\n", |
953 | channel->channel, ev_sub_data); | |
954 | break; | |
3e6c4538 | 955 | case FSE_AZ_EVQ_INIT_DONE_EV: |
8ceee660 BH |
956 | EFX_LOG(efx, "channel %d EVQ %d initialised\n", |
957 | channel->channel, ev_sub_data); | |
958 | break; | |
3e6c4538 | 959 | case FSE_AZ_SRM_UPD_DONE_EV: |
8ceee660 BH |
960 | EFX_TRACE(efx, "channel %d SRAM update done\n", |
961 | channel->channel); | |
962 | break; | |
3e6c4538 | 963 | case FSE_AZ_WAKE_UP_EV: |
8ceee660 BH |
964 | EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", |
965 | channel->channel, ev_sub_data); | |
966 | break; | |
3e6c4538 | 967 | case FSE_AZ_TIMER_EV: |
8ceee660 BH |
968 | EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", |
969 | channel->channel, ev_sub_data); | |
970 | break; | |
3e6c4538 | 971 | case FSE_AA_RX_RECOVER_EV: |
8ceee660 BH |
972 | EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " |
973 | "Resetting.\n", channel->channel); | |
05e3ec04 | 974 | atomic_inc(&efx->rx_reset); |
8ceee660 BH |
975 | efx_schedule_reset(efx, |
976 | EFX_WORKAROUND_6555(efx) ? | |
977 | RESET_TYPE_RX_RECOVERY : | |
978 | RESET_TYPE_DISABLE); | |
979 | break; | |
3e6c4538 | 980 | case FSE_BZ_RX_DSC_ERROR_EV: |
8ceee660 BH |
981 | EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." |
982 | " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
983 | efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); | |
984 | break; | |
3e6c4538 | 985 | case FSE_BZ_TX_DSC_ERROR_EV: |
8ceee660 BH |
986 | EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." |
987 | " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
988 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
989 | break; | |
990 | default: | |
991 | EFX_TRACE(efx, "channel %d unknown driver event code %d " | |
992 | "data %04x\n", channel->channel, ev_sub_code, | |
993 | ev_sub_data); | |
994 | break; | |
995 | } | |
996 | } | |
997 | ||
42cbe2d7 | 998 | int falcon_process_eventq(struct efx_channel *channel, int rx_quota) |
8ceee660 BH |
999 | { |
1000 | unsigned int read_ptr; | |
1001 | efx_qword_t event, *p_event; | |
1002 | int ev_code; | |
42cbe2d7 | 1003 | int rx_packets = 0; |
8ceee660 BH |
1004 | |
1005 | read_ptr = channel->eventq_read_ptr; | |
1006 | ||
1007 | do { | |
1008 | p_event = falcon_event(channel, read_ptr); | |
1009 | event = *p_event; | |
1010 | ||
1011 | if (!falcon_event_present(&event)) | |
1012 | /* End of events */ | |
1013 | break; | |
1014 | ||
1015 | EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n", | |
1016 | channel->channel, EFX_QWORD_VAL(event)); | |
1017 | ||
1018 | /* Clear this event by marking it all ones */ | |
1019 | EFX_SET_QWORD(*p_event); | |
1020 | ||
3e6c4538 | 1021 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); |
8ceee660 BH |
1022 | |
1023 | switch (ev_code) { | |
3e6c4538 | 1024 | case FSE_AZ_EV_CODE_RX_EV: |
42cbe2d7 BH |
1025 | falcon_handle_rx_event(channel, &event); |
1026 | ++rx_packets; | |
8ceee660 | 1027 | break; |
3e6c4538 | 1028 | case FSE_AZ_EV_CODE_TX_EV: |
8ceee660 BH |
1029 | falcon_handle_tx_event(channel, &event); |
1030 | break; | |
3e6c4538 BH |
1031 | case FSE_AZ_EV_CODE_DRV_GEN_EV: |
1032 | channel->eventq_magic = EFX_QWORD_FIELD( | |
1033 | event, FSF_AZ_DRV_GEN_EV_MAGIC); | |
8ceee660 BH |
1034 | EFX_LOG(channel->efx, "channel %d received generated " |
1035 | "event "EFX_QWORD_FMT"\n", channel->channel, | |
1036 | EFX_QWORD_VAL(event)); | |
1037 | break; | |
3e6c4538 | 1038 | case FSE_AZ_EV_CODE_GLOBAL_EV: |
8ceee660 BH |
1039 | falcon_handle_global_event(channel, &event); |
1040 | break; | |
3e6c4538 | 1041 | case FSE_AZ_EV_CODE_DRIVER_EV: |
8ceee660 BH |
1042 | falcon_handle_driver_event(channel, &event); |
1043 | break; | |
1044 | default: | |
1045 | EFX_ERR(channel->efx, "channel %d unknown event type %d" | |
1046 | " (data " EFX_QWORD_FMT ")\n", channel->channel, | |
1047 | ev_code, EFX_QWORD_VAL(event)); | |
1048 | } | |
1049 | ||
1050 | /* Increment read pointer */ | |
3ffeabdd | 1051 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
8ceee660 | 1052 | |
42cbe2d7 | 1053 | } while (rx_packets < rx_quota); |
8ceee660 BH |
1054 | |
1055 | channel->eventq_read_ptr = read_ptr; | |
42cbe2d7 | 1056 | return rx_packets; |
8ceee660 BH |
1057 | } |
1058 | ||
1059 | void falcon_set_int_moderation(struct efx_channel *channel) | |
1060 | { | |
1061 | efx_dword_t timer_cmd; | |
1062 | struct efx_nic *efx = channel->efx; | |
1063 | ||
1064 | /* Set timer register */ | |
1065 | if (channel->irq_moderation) { | |
8ceee660 | 1066 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
1067 | FRF_AB_TC_TIMER_MODE, |
1068 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
1069 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 1070 | channel->irq_moderation - 1); |
8ceee660 BH |
1071 | } else { |
1072 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
1073 | FRF_AB_TC_TIMER_MODE, |
1074 | FFE_BB_TIMER_MODE_DIS, | |
1075 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 1076 | } |
3e6c4538 | 1077 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
1078 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
1079 | channel->channel); | |
8ceee660 BH |
1080 | |
1081 | } | |
1082 | ||
1083 | /* Allocate buffer table entries for event queue */ | |
1084 | int falcon_probe_eventq(struct efx_channel *channel) | |
1085 | { | |
1086 | struct efx_nic *efx = channel->efx; | |
3ffeabdd BH |
1087 | BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 || |
1088 | EFX_EVQ_SIZE & EFX_EVQ_MASK); | |
1089 | return falcon_alloc_special_buffer(efx, &channel->eventq, | |
1090 | EFX_EVQ_SIZE * sizeof(efx_qword_t)); | |
8ceee660 BH |
1091 | } |
1092 | ||
bc3c90a2 | 1093 | void falcon_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
1094 | { |
1095 | efx_oword_t evq_ptr; | |
1096 | struct efx_nic *efx = channel->efx; | |
8ceee660 BH |
1097 | |
1098 | EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n", | |
1099 | channel->channel, channel->eventq.index, | |
1100 | channel->eventq.index + channel->eventq.entries - 1); | |
1101 | ||
1102 | /* Pin event queue buffer */ | |
bc3c90a2 | 1103 | falcon_init_special_buffer(efx, &channel->eventq); |
8ceee660 BH |
1104 | |
1105 | /* Fill event queue with all ones (i.e. empty events) */ | |
1106 | memset(channel->eventq.addr, 0xff, channel->eventq.len); | |
1107 | ||
1108 | /* Push event queue to card */ | |
1109 | EFX_POPULATE_OWORD_3(evq_ptr, | |
3e6c4538 | 1110 | FRF_AZ_EVQ_EN, 1, |
3ffeabdd | 1111 | FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), |
3e6c4538 | 1112 | FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); |
12d00cad BH |
1113 | efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, |
1114 | channel->channel); | |
8ceee660 BH |
1115 | |
1116 | falcon_set_int_moderation(channel); | |
8ceee660 BH |
1117 | } |
1118 | ||
1119 | void falcon_fini_eventq(struct efx_channel *channel) | |
1120 | { | |
1121 | efx_oword_t eventq_ptr; | |
1122 | struct efx_nic *efx = channel->efx; | |
1123 | ||
1124 | /* Remove event queue from card */ | |
1125 | EFX_ZERO_OWORD(eventq_ptr); | |
12d00cad BH |
1126 | efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, |
1127 | channel->channel); | |
8ceee660 BH |
1128 | |
1129 | /* Unpin event queue */ | |
1130 | falcon_fini_special_buffer(efx, &channel->eventq); | |
1131 | } | |
1132 | ||
1133 | /* Free buffers backing event queue */ | |
1134 | void falcon_remove_eventq(struct efx_channel *channel) | |
1135 | { | |
1136 | falcon_free_special_buffer(channel->efx, &channel->eventq); | |
1137 | } | |
1138 | ||
1139 | ||
1140 | /* Generates a test event on the event queue. A subsequent call to | |
1141 | * process_eventq() should pick up the event and place the value of | |
1142 | * "magic" into channel->eventq_magic; | |
1143 | */ | |
1144 | void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic) | |
1145 | { | |
1146 | efx_qword_t test_event; | |
1147 | ||
3e6c4538 BH |
1148 | EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, |
1149 | FSE_AZ_EV_CODE_DRV_GEN_EV, | |
1150 | FSF_AZ_DRV_GEN_EV_MAGIC, magic); | |
8ceee660 BH |
1151 | falcon_generate_event(channel, &test_event); |
1152 | } | |
1153 | ||
177dfcd8 BH |
1154 | void falcon_sim_phy_event(struct efx_nic *efx) |
1155 | { | |
1156 | efx_qword_t phy_event; | |
1157 | ||
3e6c4538 BH |
1158 | EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE, |
1159 | FSE_AZ_EV_CODE_GLOBAL_EV); | |
177dfcd8 | 1160 | if (EFX_IS10G(efx)) |
3e6c4538 | 1161 | EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1); |
177dfcd8 | 1162 | else |
3e6c4538 | 1163 | EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1); |
177dfcd8 BH |
1164 | |
1165 | falcon_generate_event(&efx->channel[0], &phy_event); | |
1166 | } | |
1167 | ||
6bc5d3a9 BH |
1168 | /************************************************************************** |
1169 | * | |
1170 | * Flush handling | |
1171 | * | |
1172 | **************************************************************************/ | |
1173 | ||
1174 | ||
1175 | static void falcon_poll_flush_events(struct efx_nic *efx) | |
1176 | { | |
1177 | struct efx_channel *channel = &efx->channel[0]; | |
1178 | struct efx_tx_queue *tx_queue; | |
1179 | struct efx_rx_queue *rx_queue; | |
4720bc6c | 1180 | unsigned int read_ptr = channel->eventq_read_ptr; |
3ffeabdd | 1181 | unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK; |
6bc5d3a9 | 1182 | |
4720bc6c | 1183 | do { |
6bc5d3a9 BH |
1184 | efx_qword_t *event = falcon_event(channel, read_ptr); |
1185 | int ev_code, ev_sub_code, ev_queue; | |
1186 | bool ev_failed; | |
4720bc6c | 1187 | |
6bc5d3a9 BH |
1188 | if (!falcon_event_present(event)) |
1189 | break; | |
1190 | ||
3e6c4538 BH |
1191 | ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE); |
1192 | ev_sub_code = EFX_QWORD_FIELD(*event, | |
1193 | FSF_AZ_DRIVER_EV_SUBCODE); | |
1194 | if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && | |
1195 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { | |
6bc5d3a9 | 1196 | ev_queue = EFX_QWORD_FIELD(*event, |
3e6c4538 | 1197 | FSF_AZ_DRIVER_EV_SUBDATA); |
6bc5d3a9 BH |
1198 | if (ev_queue < EFX_TX_QUEUE_COUNT) { |
1199 | tx_queue = efx->tx_queue + ev_queue; | |
1200 | tx_queue->flushed = true; | |
1201 | } | |
3e6c4538 BH |
1202 | } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && |
1203 | ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) { | |
1204 | ev_queue = EFX_QWORD_FIELD( | |
1205 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); | |
1206 | ev_failed = EFX_QWORD_FIELD( | |
1207 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); | |
6bc5d3a9 BH |
1208 | if (ev_queue < efx->n_rx_queues) { |
1209 | rx_queue = efx->rx_queue + ev_queue; | |
1210 | ||
1211 | /* retry the rx flush */ | |
1212 | if (ev_failed) | |
1213 | falcon_flush_rx_queue(rx_queue); | |
1214 | else | |
1215 | rx_queue->flushed = true; | |
1216 | } | |
6bc5d3a9 BH |
1217 | } |
1218 | ||
3ffeabdd | 1219 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
4720bc6c | 1220 | } while (read_ptr != end_ptr); |
6bc5d3a9 BH |
1221 | } |
1222 | ||
1223 | /* Handle tx and rx flushes at the same time, since they run in | |
1224 | * parallel in the hardware and there's no reason for us to | |
1225 | * serialise them */ | |
1226 | int falcon_flush_queues(struct efx_nic *efx) | |
1227 | { | |
1228 | struct efx_rx_queue *rx_queue; | |
1229 | struct efx_tx_queue *tx_queue; | |
1230 | int i; | |
1231 | bool outstanding; | |
1232 | ||
1233 | /* Issue flush requests */ | |
1234 | efx_for_each_tx_queue(tx_queue, efx) { | |
1235 | tx_queue->flushed = false; | |
1236 | falcon_flush_tx_queue(tx_queue); | |
1237 | } | |
1238 | efx_for_each_rx_queue(rx_queue, efx) { | |
1239 | rx_queue->flushed = false; | |
1240 | falcon_flush_rx_queue(rx_queue); | |
1241 | } | |
1242 | ||
1243 | /* Poll the evq looking for flush completions. Since we're not pushing | |
1244 | * any more rx or tx descriptors at this point, we're in no danger of | |
1245 | * overflowing the evq whilst we wait */ | |
1246 | for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) { | |
1247 | msleep(FALCON_FLUSH_INTERVAL); | |
1248 | falcon_poll_flush_events(efx); | |
1249 | ||
1250 | /* Check if every queue has been succesfully flushed */ | |
1251 | outstanding = false; | |
1252 | efx_for_each_tx_queue(tx_queue, efx) | |
1253 | outstanding |= !tx_queue->flushed; | |
1254 | efx_for_each_rx_queue(rx_queue, efx) | |
1255 | outstanding |= !rx_queue->flushed; | |
1256 | if (!outstanding) | |
1257 | return 0; | |
1258 | } | |
1259 | ||
1260 | /* Mark the queues as all flushed. We're going to return failure | |
1261 | * leading to a reset, or fake up success anyway. "flushed" now | |
1262 | * indicates that we tried to flush. */ | |
1263 | efx_for_each_tx_queue(tx_queue, efx) { | |
1264 | if (!tx_queue->flushed) | |
1265 | EFX_ERR(efx, "tx queue %d flush command timed out\n", | |
1266 | tx_queue->queue); | |
1267 | tx_queue->flushed = true; | |
1268 | } | |
1269 | efx_for_each_rx_queue(rx_queue, efx) { | |
1270 | if (!rx_queue->flushed) | |
1271 | EFX_ERR(efx, "rx queue %d flush command timed out\n", | |
1272 | rx_queue->queue); | |
1273 | rx_queue->flushed = true; | |
1274 | } | |
1275 | ||
1276 | if (EFX_WORKAROUND_7803(efx)) | |
1277 | return 0; | |
1278 | ||
1279 | return -ETIMEDOUT; | |
1280 | } | |
8ceee660 BH |
1281 | |
1282 | /************************************************************************** | |
1283 | * | |
1284 | * Falcon hardware interrupts | |
1285 | * The hardware interrupt handler does very little work; all the event | |
1286 | * queue processing is carried out by per-channel tasklets. | |
1287 | * | |
1288 | **************************************************************************/ | |
1289 | ||
1290 | /* Enable/disable/generate Falcon interrupts */ | |
1291 | static inline void falcon_interrupts(struct efx_nic *efx, int enabled, | |
1292 | int force) | |
1293 | { | |
1294 | efx_oword_t int_en_reg_ker; | |
1295 | ||
1296 | EFX_POPULATE_OWORD_2(int_en_reg_ker, | |
3e6c4538 BH |
1297 | FRF_AZ_KER_INT_KER, force, |
1298 | FRF_AZ_DRV_INT_EN_KER, enabled); | |
12d00cad | 1299 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); |
8ceee660 BH |
1300 | } |
1301 | ||
1302 | void falcon_enable_interrupts(struct efx_nic *efx) | |
1303 | { | |
1304 | efx_oword_t int_adr_reg_ker; | |
1305 | struct efx_channel *channel; | |
1306 | ||
1307 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); | |
1308 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ | |
1309 | ||
1310 | /* Program address */ | |
1311 | EFX_POPULATE_OWORD_2(int_adr_reg_ker, | |
3e6c4538 BH |
1312 | FRF_AZ_NORM_INT_VEC_DIS_KER, |
1313 | EFX_INT_MODE_USE_MSI(efx), | |
1314 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); | |
12d00cad | 1315 | efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER); |
8ceee660 BH |
1316 | |
1317 | /* Enable interrupts */ | |
1318 | falcon_interrupts(efx, 1, 0); | |
1319 | ||
1320 | /* Force processing of all the channels to get the EVQ RPTRs up to | |
1321 | date */ | |
64ee3120 | 1322 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1323 | efx_schedule_channel(channel); |
1324 | } | |
1325 | ||
1326 | void falcon_disable_interrupts(struct efx_nic *efx) | |
1327 | { | |
1328 | /* Disable interrupts */ | |
1329 | falcon_interrupts(efx, 0, 0); | |
1330 | } | |
1331 | ||
1332 | /* Generate a Falcon test interrupt | |
1333 | * Interrupt must already have been enabled, otherwise nasty things | |
1334 | * may happen. | |
1335 | */ | |
1336 | void falcon_generate_interrupt(struct efx_nic *efx) | |
1337 | { | |
1338 | falcon_interrupts(efx, 1, 1); | |
1339 | } | |
1340 | ||
1341 | /* Acknowledge a legacy interrupt from Falcon | |
1342 | * | |
1343 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
1344 | * | |
1345 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
1346 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
1347 | * (then read to ensure the BIU collector is flushed) | |
1348 | * | |
1349 | * NB most hardware supports MSI interrupts | |
1350 | */ | |
1351 | static inline void falcon_irq_ack_a1(struct efx_nic *efx) | |
1352 | { | |
1353 | efx_dword_t reg; | |
1354 | ||
3e6c4538 | 1355 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
1356 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
1357 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
1358 | } |
1359 | ||
1360 | /* Process a fatal interrupt | |
1361 | * Disable bus mastering ASAP and schedule a reset | |
1362 | */ | |
1363 | static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx) | |
1364 | { | |
1365 | struct falcon_nic_data *nic_data = efx->nic_data; | |
d3208b5e | 1366 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1367 | efx_oword_t fatal_intr; |
1368 | int error, mem_perr; | |
8ceee660 | 1369 | |
12d00cad | 1370 | efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); |
3e6c4538 | 1371 | error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); |
8ceee660 BH |
1372 | |
1373 | EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " | |
1374 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | |
1375 | EFX_OWORD_VAL(fatal_intr), | |
1376 | error ? "disabling bus mastering" : "no recognised error"); | |
1377 | if (error == 0) | |
1378 | goto out; | |
1379 | ||
1380 | /* If this is a memory parity error dump which blocks are offending */ | |
3e6c4538 | 1381 | mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); |
8ceee660 BH |
1382 | if (mem_perr) { |
1383 | efx_oword_t reg; | |
12d00cad | 1384 | efx_reado(efx, ®, FR_AZ_MEM_STAT); |
8ceee660 BH |
1385 | EFX_ERR(efx, "SYSTEM ERROR: memory parity error " |
1386 | EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); | |
1387 | } | |
1388 | ||
0a62f1a6 | 1389 | /* Disable both devices */ |
ef1bba28 | 1390 | pci_clear_master(efx->pci_dev); |
8ceee660 | 1391 | if (FALCON_IS_DUAL_FUNC(efx)) |
ef1bba28 | 1392 | pci_clear_master(nic_data->pci_dev2); |
0a62f1a6 | 1393 | falcon_disable_interrupts(efx); |
8ceee660 | 1394 | |
2c3c3d02 | 1395 | /* Count errors and reset or disable the NIC accordingly */ |
0484e0db BH |
1396 | if (efx->int_error_count == 0 || |
1397 | time_after(jiffies, efx->int_error_expire)) { | |
1398 | efx->int_error_count = 0; | |
1399 | efx->int_error_expire = | |
2c3c3d02 BH |
1400 | jiffies + FALCON_INT_ERROR_EXPIRE * HZ; |
1401 | } | |
0484e0db | 1402 | if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) { |
8ceee660 BH |
1403 | EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n"); |
1404 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); | |
1405 | } else { | |
1406 | EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen." | |
1407 | "NIC will be disabled\n"); | |
1408 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1409 | } | |
1410 | out: | |
1411 | return IRQ_HANDLED; | |
1412 | } | |
1413 | ||
1414 | /* Handle a legacy interrupt from Falcon | |
1415 | * Acknowledges the interrupt and schedule event queue processing. | |
1416 | */ | |
1417 | static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id) | |
1418 | { | |
d3208b5e BH |
1419 | struct efx_nic *efx = dev_id; |
1420 | efx_oword_t *int_ker = efx->irq_status.addr; | |
a9de9a74 | 1421 | irqreturn_t result = IRQ_NONE; |
8ceee660 BH |
1422 | struct efx_channel *channel; |
1423 | efx_dword_t reg; | |
1424 | u32 queues; | |
1425 | int syserr; | |
1426 | ||
1427 | /* Read the ISR which also ACKs the interrupts */ | |
12d00cad | 1428 | efx_readd(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1429 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); |
1430 | ||
1431 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1432 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 BH |
1433 | if (unlikely(syserr)) |
1434 | return falcon_fatal_interrupt(efx); | |
1435 | ||
8ceee660 | 1436 | /* Schedule processing of any interrupting queues */ |
a9de9a74 BH |
1437 | efx_for_each_channel(channel, efx) { |
1438 | if ((queues & 1) || | |
1439 | falcon_event_present( | |
1440 | falcon_event(channel, channel->eventq_read_ptr))) { | |
8ceee660 | 1441 | efx_schedule_channel(channel); |
a9de9a74 BH |
1442 | result = IRQ_HANDLED; |
1443 | } | |
8ceee660 BH |
1444 | queues >>= 1; |
1445 | } | |
1446 | ||
a9de9a74 BH |
1447 | if (result == IRQ_HANDLED) { |
1448 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1449 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1450 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1451 | } | |
1452 | ||
1453 | return result; | |
8ceee660 BH |
1454 | } |
1455 | ||
1456 | ||
1457 | static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) | |
1458 | { | |
d3208b5e BH |
1459 | struct efx_nic *efx = dev_id; |
1460 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
1461 | struct efx_channel *channel; |
1462 | int syserr; | |
1463 | int queues; | |
1464 | ||
1465 | /* Check to see if this is our interrupt. If it isn't, we | |
1466 | * exit without having touched the hardware. | |
1467 | */ | |
1468 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
1469 | EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq, | |
1470 | raw_smp_processor_id()); | |
1471 | return IRQ_NONE; | |
1472 | } | |
1473 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1474 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1475 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1476 | ||
1477 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1478 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 BH |
1479 | if (unlikely(syserr)) |
1480 | return falcon_fatal_interrupt(efx); | |
1481 | ||
1482 | /* Determine interrupting queues, clear interrupt status | |
1483 | * register and acknowledge the device interrupt. | |
1484 | */ | |
1485 | BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS); | |
1486 | queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS); | |
1487 | EFX_ZERO_OWORD(*int_ker); | |
1488 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
1489 | falcon_irq_ack_a1(efx); | |
1490 | ||
1491 | /* Schedule processing of any interrupting queues */ | |
1492 | channel = &efx->channel[0]; | |
1493 | while (queues) { | |
1494 | if (queues & 0x01) | |
1495 | efx_schedule_channel(channel); | |
1496 | channel++; | |
1497 | queues >>= 1; | |
1498 | } | |
1499 | ||
1500 | return IRQ_HANDLED; | |
1501 | } | |
1502 | ||
1503 | /* Handle an MSI interrupt from Falcon | |
1504 | * | |
1505 | * Handle an MSI hardware interrupt. This routine schedules event | |
1506 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1507 | * Also, we never need to check that the interrupt is for us, since | |
1508 | * MSI interrupts cannot be shared. | |
1509 | */ | |
1510 | static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id) | |
1511 | { | |
d3208b5e | 1512 | struct efx_channel *channel = dev_id; |
8ceee660 | 1513 | struct efx_nic *efx = channel->efx; |
d3208b5e | 1514 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1515 | int syserr; |
1516 | ||
1517 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1518 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1519 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1520 | ||
1521 | /* Check to see if we have a serious error condition */ | |
1522 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); | |
1523 | if (unlikely(syserr)) | |
1524 | return falcon_fatal_interrupt(efx); | |
1525 | ||
1526 | /* Schedule processing of the channel */ | |
1527 | efx_schedule_channel(channel); | |
1528 | ||
1529 | return IRQ_HANDLED; | |
1530 | } | |
1531 | ||
1532 | ||
1533 | /* Setup RSS indirection table. | |
1534 | * This maps from the hash value of the packet to RXQ | |
1535 | */ | |
1536 | static void falcon_setup_rss_indir_table(struct efx_nic *efx) | |
1537 | { | |
1538 | int i = 0; | |
1539 | unsigned long offset; | |
1540 | efx_dword_t dword; | |
1541 | ||
55668611 | 1542 | if (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
1543 | return; |
1544 | ||
3e6c4538 BH |
1545 | for (offset = FR_BZ_RX_INDIRECTION_TBL; |
1546 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; | |
8ceee660 | 1547 | offset += 0x10) { |
3e6c4538 | 1548 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, |
8831da7b | 1549 | i % efx->n_rx_queues); |
12d00cad | 1550 | efx_writed(efx, &dword, offset); |
8ceee660 BH |
1551 | i++; |
1552 | } | |
1553 | } | |
1554 | ||
1555 | /* Hook interrupt handler(s) | |
1556 | * Try MSI and then legacy interrupts. | |
1557 | */ | |
1558 | int falcon_init_interrupt(struct efx_nic *efx) | |
1559 | { | |
1560 | struct efx_channel *channel; | |
1561 | int rc; | |
1562 | ||
1563 | if (!EFX_INT_MODE_USE_MSI(efx)) { | |
1564 | irq_handler_t handler; | |
55668611 | 1565 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
1566 | handler = falcon_legacy_interrupt_b0; |
1567 | else | |
1568 | handler = falcon_legacy_interrupt_a1; | |
1569 | ||
1570 | rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, | |
1571 | efx->name, efx); | |
1572 | if (rc) { | |
1573 | EFX_ERR(efx, "failed to hook legacy IRQ %d\n", | |
1574 | efx->pci_dev->irq); | |
1575 | goto fail1; | |
1576 | } | |
1577 | return 0; | |
1578 | } | |
1579 | ||
1580 | /* Hook MSI or MSI-X interrupt */ | |
64ee3120 | 1581 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1582 | rc = request_irq(channel->irq, falcon_msi_interrupt, |
1583 | IRQF_PROBE_SHARED, /* Not shared */ | |
56536e9c | 1584 | channel->name, channel); |
8ceee660 BH |
1585 | if (rc) { |
1586 | EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq); | |
1587 | goto fail2; | |
1588 | } | |
1589 | } | |
1590 | ||
1591 | return 0; | |
1592 | ||
1593 | fail2: | |
64ee3120 | 1594 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1595 | free_irq(channel->irq, channel); |
1596 | fail1: | |
1597 | return rc; | |
1598 | } | |
1599 | ||
1600 | void falcon_fini_interrupt(struct efx_nic *efx) | |
1601 | { | |
1602 | struct efx_channel *channel; | |
1603 | efx_oword_t reg; | |
1604 | ||
1605 | /* Disable MSI/MSI-X interrupts */ | |
64ee3120 | 1606 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1607 | if (channel->irq) |
1608 | free_irq(channel->irq, channel); | |
b3475645 | 1609 | } |
8ceee660 BH |
1610 | |
1611 | /* ACK legacy interrupt */ | |
55668611 | 1612 | if (falcon_rev(efx) >= FALCON_REV_B0) |
12d00cad | 1613 | efx_reado(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1614 | else |
1615 | falcon_irq_ack_a1(efx); | |
1616 | ||
1617 | /* Disable legacy interrupt */ | |
1618 | if (efx->legacy_irq) | |
1619 | free_irq(efx->legacy_irq, efx); | |
1620 | } | |
1621 | ||
1622 | /************************************************************************** | |
1623 | * | |
1624 | * EEPROM/flash | |
1625 | * | |
1626 | ************************************************************************** | |
1627 | */ | |
1628 | ||
23d30f02 | 1629 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 1630 | |
be4ea89c BH |
1631 | static int falcon_spi_poll(struct efx_nic *efx) |
1632 | { | |
1633 | efx_oword_t reg; | |
12d00cad | 1634 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 1635 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
1636 | } |
1637 | ||
8ceee660 BH |
1638 | /* Wait for SPI command completion */ |
1639 | static int falcon_spi_wait(struct efx_nic *efx) | |
1640 | { | |
be4ea89c BH |
1641 | /* Most commands will finish quickly, so we start polling at |
1642 | * very short intervals. Sometimes the command may have to | |
1643 | * wait for VPD or expansion ROM access outside of our | |
1644 | * control, so we allow up to 100 ms. */ | |
1645 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
1646 | int i; | |
1647 | ||
1648 | for (i = 0; i < 10; i++) { | |
1649 | if (!falcon_spi_poll(efx)) | |
1650 | return 0; | |
1651 | udelay(10); | |
1652 | } | |
8ceee660 | 1653 | |
4a5b504d | 1654 | for (;;) { |
be4ea89c | 1655 | if (!falcon_spi_poll(efx)) |
8ceee660 | 1656 | return 0; |
4a5b504d BH |
1657 | if (time_after_eq(jiffies, timeout)) { |
1658 | EFX_ERR(efx, "timed out waiting for SPI\n"); | |
1659 | return -ETIMEDOUT; | |
1660 | } | |
be4ea89c | 1661 | schedule_timeout_uninterruptible(1); |
4a5b504d | 1662 | } |
8ceee660 BH |
1663 | } |
1664 | ||
f4150724 BH |
1665 | int falcon_spi_cmd(const struct efx_spi_device *spi, |
1666 | unsigned int command, int address, | |
23d30f02 | 1667 | const void *in, void *out, size_t len) |
8ceee660 | 1668 | { |
4a5b504d BH |
1669 | struct efx_nic *efx = spi->efx; |
1670 | bool addressed = (address >= 0); | |
1671 | bool reading = (out != NULL); | |
8ceee660 BH |
1672 | efx_oword_t reg; |
1673 | int rc; | |
1674 | ||
4a5b504d BH |
1675 | /* Input validation */ |
1676 | if (len > FALCON_SPI_MAX_LEN) | |
1677 | return -EINVAL; | |
f4150724 | 1678 | BUG_ON(!mutex_is_locked(&efx->spi_lock)); |
8ceee660 | 1679 | |
be4ea89c BH |
1680 | /* Check that previous command is not still running */ |
1681 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
1682 | if (rc) |
1683 | return rc; | |
1684 | ||
4a5b504d BH |
1685 | /* Program address register, if we have an address */ |
1686 | if (addressed) { | |
3e6c4538 | 1687 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 1688 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
1689 | } |
1690 | ||
1691 | /* Program data register, if we have data */ | |
1692 | if (in != NULL) { | |
1693 | memcpy(®, in, len); | |
12d00cad | 1694 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 1695 | } |
8ceee660 | 1696 | |
4a5b504d | 1697 | /* Issue read/write command */ |
8ceee660 | 1698 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
1699 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
1700 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
1701 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
1702 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
1703 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
1704 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 1705 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 1706 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 1707 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 1708 | |
4a5b504d | 1709 | /* Wait for read/write to complete */ |
8ceee660 BH |
1710 | rc = falcon_spi_wait(efx); |
1711 | if (rc) | |
1712 | return rc; | |
1713 | ||
1714 | /* Read data */ | |
4a5b504d | 1715 | if (out != NULL) { |
12d00cad | 1716 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
1717 | memcpy(out, ®, len); |
1718 | } | |
1719 | ||
8ceee660 BH |
1720 | return 0; |
1721 | } | |
1722 | ||
23d30f02 BH |
1723 | static size_t |
1724 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
1725 | { |
1726 | return min(FALCON_SPI_MAX_LEN, | |
1727 | (spi->block_size - (start & (spi->block_size - 1)))); | |
1728 | } | |
1729 | ||
1730 | static inline u8 | |
1731 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
1732 | const u8 command, const unsigned int address) | |
1733 | { | |
1734 | return command | (((address >> 8) & spi->munge_address) << 3); | |
1735 | } | |
1736 | ||
be4ea89c BH |
1737 | /* Wait up to 10 ms for buffered write completion */ |
1738 | int falcon_spi_wait_write(const struct efx_spi_device *spi) | |
4a5b504d | 1739 | { |
be4ea89c BH |
1740 | struct efx_nic *efx = spi->efx; |
1741 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); | |
4a5b504d | 1742 | u8 status; |
be4ea89c | 1743 | int rc; |
4a5b504d | 1744 | |
be4ea89c | 1745 | for (;;) { |
4a5b504d BH |
1746 | rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL, |
1747 | &status, sizeof(status)); | |
1748 | if (rc) | |
1749 | return rc; | |
1750 | if (!(status & SPI_STATUS_NRDY)) | |
1751 | return 0; | |
be4ea89c BH |
1752 | if (time_after_eq(jiffies, timeout)) { |
1753 | EFX_ERR(efx, "SPI write timeout on device %d" | |
1754 | " last status=0x%02x\n", | |
1755 | spi->device_id, status); | |
1756 | return -ETIMEDOUT; | |
1757 | } | |
1758 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 1759 | } |
4a5b504d BH |
1760 | } |
1761 | ||
1762 | int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, | |
1763 | size_t len, size_t *retlen, u8 *buffer) | |
1764 | { | |
23d30f02 BH |
1765 | size_t block_len, pos = 0; |
1766 | unsigned int command; | |
4a5b504d BH |
1767 | int rc = 0; |
1768 | ||
1769 | while (pos < len) { | |
23d30f02 | 1770 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
1771 | |
1772 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1773 | rc = falcon_spi_cmd(spi, command, start + pos, NULL, | |
1774 | buffer + pos, block_len); | |
1775 | if (rc) | |
1776 | break; | |
1777 | pos += block_len; | |
1778 | ||
1779 | /* Avoid locking up the system */ | |
1780 | cond_resched(); | |
1781 | if (signal_pending(current)) { | |
1782 | rc = -EINTR; | |
1783 | break; | |
1784 | } | |
1785 | } | |
1786 | ||
1787 | if (retlen) | |
1788 | *retlen = pos; | |
1789 | return rc; | |
1790 | } | |
1791 | ||
1792 | int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, | |
1793 | size_t len, size_t *retlen, const u8 *buffer) | |
1794 | { | |
1795 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
1796 | size_t block_len, pos = 0; |
1797 | unsigned int command; | |
4a5b504d BH |
1798 | int rc = 0; |
1799 | ||
1800 | while (pos < len) { | |
1801 | rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0); | |
1802 | if (rc) | |
1803 | break; | |
1804 | ||
23d30f02 | 1805 | block_len = min(len - pos, |
4a5b504d BH |
1806 | falcon_spi_write_limit(spi, start + pos)); |
1807 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
1808 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1809 | buffer + pos, NULL, block_len); | |
1810 | if (rc) | |
1811 | break; | |
1812 | ||
be4ea89c | 1813 | rc = falcon_spi_wait_write(spi); |
4a5b504d BH |
1814 | if (rc) |
1815 | break; | |
1816 | ||
1817 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1818 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1819 | NULL, verify_buffer, block_len); | |
1820 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
1821 | rc = -EIO; | |
1822 | break; | |
1823 | } | |
1824 | ||
1825 | pos += block_len; | |
1826 | ||
1827 | /* Avoid locking up the system */ | |
1828 | cond_resched(); | |
1829 | if (signal_pending(current)) { | |
1830 | rc = -EINTR; | |
1831 | break; | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | if (retlen) | |
1836 | *retlen = pos; | |
1837 | return rc; | |
1838 | } | |
1839 | ||
8ceee660 BH |
1840 | /************************************************************************** |
1841 | * | |
1842 | * MAC wrapper | |
1843 | * | |
1844 | ************************************************************************** | |
1845 | */ | |
177dfcd8 BH |
1846 | |
1847 | static int falcon_reset_macs(struct efx_nic *efx) | |
8ceee660 | 1848 | { |
177dfcd8 | 1849 | efx_oword_t reg; |
8ceee660 BH |
1850 | int count; |
1851 | ||
177dfcd8 BH |
1852 | if (falcon_rev(efx) < FALCON_REV_B0) { |
1853 | /* It's not safe to use GLB_CTL_REG to reset the | |
1854 | * macs, so instead use the internal MAC resets | |
1855 | */ | |
1856 | if (!EFX_IS10G(efx)) { | |
3e6c4538 | 1857 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); |
12d00cad | 1858 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1859 | udelay(1000); |
1860 | ||
3e6c4538 | 1861 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); |
12d00cad | 1862 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1863 | udelay(1000); |
1864 | return 0; | |
1865 | } else { | |
3e6c4538 | 1866 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
12d00cad | 1867 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
177dfcd8 BH |
1868 | |
1869 | for (count = 0; count < 10000; count++) { | |
12d00cad | 1870 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); |
3e6c4538 BH |
1871 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
1872 | 0) | |
177dfcd8 BH |
1873 | return 0; |
1874 | udelay(10); | |
1875 | } | |
8ceee660 | 1876 | |
177dfcd8 BH |
1877 | EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); |
1878 | return -ETIMEDOUT; | |
1879 | } | |
1880 | } | |
8ceee660 BH |
1881 | |
1882 | /* MAC stats will fail whilst the TX fifo is draining. Serialise | |
1883 | * the drain sequence with the statistics fetch */ | |
1974cc20 | 1884 | efx_stats_disable(efx); |
8ceee660 | 1885 | |
12d00cad | 1886 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
3e6c4538 | 1887 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1); |
12d00cad | 1888 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 | 1889 | |
12d00cad | 1890 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1891 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
1892 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
1893 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 1894 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
1895 | |
1896 | count = 0; | |
1897 | while (1) { | |
12d00cad | 1898 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1899 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
1900 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
1901 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
8ceee660 BH |
1902 | EFX_LOG(efx, "Completed MAC reset after %d loops\n", |
1903 | count); | |
1904 | break; | |
1905 | } | |
1906 | if (count > 20) { | |
1907 | EFX_ERR(efx, "MAC reset failed\n"); | |
1908 | break; | |
1909 | } | |
1910 | count++; | |
1911 | udelay(10); | |
1912 | } | |
1913 | ||
1974cc20 | 1914 | efx_stats_enable(efx); |
8ceee660 BH |
1915 | |
1916 | /* If we've reset the EM block and the link is up, then | |
1917 | * we'll have to kick the XAUI link so the PHY can recover */ | |
177dfcd8 | 1918 | if (efx->link_up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx)) |
8ceee660 | 1919 | falcon_reset_xaui(efx); |
177dfcd8 BH |
1920 | |
1921 | return 0; | |
1922 | } | |
1923 | ||
1924 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
1925 | { | |
1926 | efx_oword_t reg; | |
1927 | ||
1928 | if ((falcon_rev(efx) < FALCON_REV_B0) || | |
1929 | (efx->loopback_mode != LOOPBACK_NONE)) | |
1930 | return; | |
1931 | ||
12d00cad | 1932 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 1933 | /* There is no point in draining more than once */ |
3e6c4538 | 1934 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
1935 | return; |
1936 | ||
1937 | falcon_reset_macs(efx); | |
8ceee660 BH |
1938 | } |
1939 | ||
1940 | void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) | |
1941 | { | |
177dfcd8 | 1942 | efx_oword_t reg; |
8ceee660 | 1943 | |
55668611 | 1944 | if (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
1945 | return; |
1946 | ||
1947 | /* Isolate the MAC -> RX */ | |
12d00cad | 1948 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 1949 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 1950 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
1951 | |
1952 | if (!efx->link_up) | |
1953 | falcon_drain_tx_fifo(efx); | |
1954 | } | |
1955 | ||
1956 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
1957 | { | |
1958 | efx_oword_t reg; | |
1959 | int link_speed; | |
dc8cfa55 | 1960 | bool tx_fc; |
8ceee660 | 1961 | |
f31a45d2 BH |
1962 | switch (efx->link_speed) { |
1963 | case 10000: link_speed = 3; break; | |
1964 | case 1000: link_speed = 2; break; | |
1965 | case 100: link_speed = 1; break; | |
1966 | default: link_speed = 0; break; | |
1967 | } | |
8ceee660 BH |
1968 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
1969 | * as advertised. Disable to ensure packets are not | |
1970 | * indefinitely held and TX queue can be flushed at any point | |
1971 | * while the link is down. */ | |
1972 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
1973 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
1974 | FRF_AB_MAC_BCAD_ACPT, 1, | |
1975 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
1976 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
1977 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
1978 | /* On B0, MAC backpressure can be disabled and packets get |
1979 | * discarded. */ | |
55668611 | 1980 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
3e6c4538 | 1981 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
8ceee660 BH |
1982 | !efx->link_up); |
1983 | } | |
1984 | ||
12d00cad | 1985 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
1986 | |
1987 | /* Restore the multicast hash registers. */ | |
1988 | falcon_set_multicast_hash(efx); | |
1989 | ||
1990 | /* Transmission of pause frames when RX crosses the threshold is | |
1991 | * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. | |
1992 | * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ | |
04cc8cac | 1993 | tx_fc = !!(efx->link_fc & EFX_FC_TX); |
12d00cad | 1994 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 1995 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc); |
8ceee660 BH |
1996 | |
1997 | /* Unisolate the MAC -> RX */ | |
55668611 | 1998 | if (falcon_rev(efx) >= FALCON_REV_B0) |
3e6c4538 | 1999 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
12d00cad | 2000 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
2001 | } |
2002 | ||
2003 | int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) | |
2004 | { | |
2005 | efx_oword_t reg; | |
2006 | u32 *dma_done; | |
2007 | int i; | |
2008 | ||
2009 | if (disable_dma_stats) | |
2010 | return 0; | |
2011 | ||
2012 | /* Statistics fetch will fail if the MAC is in TX drain */ | |
55668611 | 2013 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
8ceee660 | 2014 | efx_oword_t temp; |
12d00cad | 2015 | efx_reado(efx, &temp, FR_AB_MAC_CTRL); |
3e6c4538 | 2016 | if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN)) |
8ceee660 BH |
2017 | return 0; |
2018 | } | |
2019 | ||
2020 | dma_done = (efx->stats_buffer.addr + done_offset); | |
2021 | *dma_done = FALCON_STATS_NOT_DONE; | |
2022 | wmb(); /* ensure done flag is clear */ | |
2023 | ||
2024 | /* Initiate DMA transfer of stats */ | |
2025 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2026 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
2027 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 2028 | efx->stats_buffer.dma_addr); |
12d00cad | 2029 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 BH |
2030 | |
2031 | /* Wait for transfer to complete */ | |
2032 | for (i = 0; i < 400; i++) { | |
1d0680fd BH |
2033 | if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) { |
2034 | rmb(); /* Ensure the stats are valid. */ | |
8ceee660 | 2035 | return 0; |
1d0680fd | 2036 | } |
8ceee660 BH |
2037 | udelay(10); |
2038 | } | |
2039 | ||
2040 | EFX_ERR(efx, "timed out waiting for statistics\n"); | |
2041 | return -ETIMEDOUT; | |
2042 | } | |
2043 | ||
2044 | /************************************************************************** | |
2045 | * | |
2046 | * PHY access via GMII | |
2047 | * | |
2048 | ************************************************************************** | |
2049 | */ | |
2050 | ||
8ceee660 BH |
2051 | /* Wait for GMII access to complete */ |
2052 | static int falcon_gmii_wait(struct efx_nic *efx) | |
2053 | { | |
2054 | efx_dword_t md_stat; | |
2055 | int count; | |
2056 | ||
177dfcd8 BH |
2057 | /* wait upto 50ms - taken max from datasheet */ |
2058 | for (count = 0; count < 5000; count++) { | |
12d00cad | 2059 | efx_readd(efx, &md_stat, FR_AB_MD_STAT); |
3e6c4538 BH |
2060 | if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { |
2061 | if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
2062 | EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
8ceee660 BH |
2063 | EFX_ERR(efx, "error from GMII access " |
2064 | EFX_DWORD_FMT"\n", | |
2065 | EFX_DWORD_VAL(md_stat)); | |
2066 | return -EIO; | |
2067 | } | |
2068 | return 0; | |
2069 | } | |
2070 | udelay(10); | |
2071 | } | |
2072 | EFX_ERR(efx, "timed out waiting for GMII\n"); | |
2073 | return -ETIMEDOUT; | |
2074 | } | |
2075 | ||
68e7f45e BH |
2076 | /* Write an MDIO register of a PHY connected to Falcon. */ |
2077 | static int falcon_mdio_write(struct net_device *net_dev, | |
2078 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 2079 | { |
767e468c | 2080 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2081 | efx_oword_t reg; |
68e7f45e | 2082 | int rc; |
8ceee660 | 2083 | |
68e7f45e BH |
2084 | EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n", |
2085 | prtad, devad, addr, value); | |
8ceee660 BH |
2086 | |
2087 | spin_lock_bh(&efx->phy_lock); | |
2088 | ||
68e7f45e BH |
2089 | /* Check MDIO not currently being accessed */ |
2090 | rc = falcon_gmii_wait(efx); | |
2091 | if (rc) | |
8ceee660 BH |
2092 | goto out; |
2093 | ||
2094 | /* Write the address/ID register */ | |
3e6c4538 | 2095 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2096 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2097 | |
3e6c4538 BH |
2098 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2099 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2100 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2101 | |
2102 | /* Write data */ | |
3e6c4538 | 2103 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 2104 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
2105 | |
2106 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2107 | FRF_AB_MD_WRC, 1, |
2108 | FRF_AB_MD_GC, 0); | |
12d00cad | 2109 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2110 | |
2111 | /* Wait for data to be written */ | |
68e7f45e BH |
2112 | rc = falcon_gmii_wait(efx); |
2113 | if (rc) { | |
8ceee660 BH |
2114 | /* Abort the write operation */ |
2115 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2116 | FRF_AB_MD_WRC, 0, |
2117 | FRF_AB_MD_GC, 1); | |
12d00cad | 2118 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2119 | udelay(10); |
2120 | } | |
2121 | ||
2122 | out: | |
2123 | spin_unlock_bh(&efx->phy_lock); | |
68e7f45e | 2124 | return rc; |
8ceee660 BH |
2125 | } |
2126 | ||
68e7f45e BH |
2127 | /* Read an MDIO register of a PHY connected to Falcon. */ |
2128 | static int falcon_mdio_read(struct net_device *net_dev, | |
2129 | int prtad, int devad, u16 addr) | |
8ceee660 | 2130 | { |
767e468c | 2131 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2132 | efx_oword_t reg; |
68e7f45e | 2133 | int rc; |
8ceee660 BH |
2134 | |
2135 | spin_lock_bh(&efx->phy_lock); | |
2136 | ||
68e7f45e BH |
2137 | /* Check MDIO not currently being accessed */ |
2138 | rc = falcon_gmii_wait(efx); | |
2139 | if (rc) | |
8ceee660 BH |
2140 | goto out; |
2141 | ||
3e6c4538 | 2142 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2143 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2144 | |
3e6c4538 BH |
2145 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2146 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2147 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2148 | |
2149 | /* Request data to be read */ | |
3e6c4538 | 2150 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 2151 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2152 | |
2153 | /* Wait for data to become available */ | |
68e7f45e BH |
2154 | rc = falcon_gmii_wait(efx); |
2155 | if (rc == 0) { | |
12d00cad | 2156 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 2157 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
68e7f45e BH |
2158 | EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", |
2159 | prtad, devad, addr, rc); | |
8ceee660 BH |
2160 | } else { |
2161 | /* Abort the read operation */ | |
2162 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2163 | FRF_AB_MD_RIC, 0, |
2164 | FRF_AB_MD_GC, 1); | |
12d00cad | 2165 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 2166 | |
68e7f45e BH |
2167 | EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", |
2168 | prtad, devad, addr, rc); | |
8ceee660 BH |
2169 | } |
2170 | ||
2171 | out: | |
2172 | spin_unlock_bh(&efx->phy_lock); | |
68e7f45e | 2173 | return rc; |
8ceee660 BH |
2174 | } |
2175 | ||
177dfcd8 BH |
2176 | int falcon_switch_mac(struct efx_nic *efx) |
2177 | { | |
2178 | struct efx_mac_operations *old_mac_op = efx->mac_op; | |
2179 | efx_oword_t nic_stat; | |
2180 | unsigned strap_val; | |
1974cc20 BH |
2181 | int rc = 0; |
2182 | ||
2183 | /* Don't try to fetch MAC stats while we're switching MACs */ | |
2184 | efx_stats_disable(efx); | |
177dfcd8 BH |
2185 | |
2186 | /* Internal loopbacks override the phy speed setting */ | |
2187 | if (efx->loopback_mode == LOOPBACK_GMAC) { | |
2188 | efx->link_speed = 1000; | |
2189 | efx->link_fd = true; | |
2190 | } else if (LOOPBACK_INTERNAL(efx)) { | |
2191 | efx->link_speed = 10000; | |
2192 | efx->link_fd = true; | |
2193 | } | |
2194 | ||
0cc12838 | 2195 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
177dfcd8 BH |
2196 | efx->mac_op = (EFX_IS10G(efx) ? |
2197 | &falcon_xmac_operations : &falcon_gmac_operations); | |
177dfcd8 | 2198 | |
0cc12838 SH |
2199 | /* Always push the NIC_STAT_REG setting even if the mac hasn't |
2200 | * changed, because this function is run post online reset */ | |
12d00cad | 2201 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
177dfcd8 BH |
2202 | strap_val = EFX_IS10G(efx) ? 5 : 3; |
2203 | if (falcon_rev(efx) >= FALCON_REV_B0) { | |
3e6c4538 BH |
2204 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); |
2205 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); | |
12d00cad | 2206 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); |
177dfcd8 BH |
2207 | } else { |
2208 | /* Falcon A1 does not support 1G/10G speed switching | |
2209 | * and must not be used with a PHY that does. */ | |
3e6c4538 BH |
2210 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != |
2211 | strap_val); | |
177dfcd8 BH |
2212 | } |
2213 | ||
0cc12838 | 2214 | if (old_mac_op == efx->mac_op) |
1974cc20 | 2215 | goto out; |
177dfcd8 BH |
2216 | |
2217 | EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G'); | |
0cc12838 SH |
2218 | /* Not all macs support a mac-level link state */ |
2219 | efx->mac_up = true; | |
2220 | ||
1974cc20 BH |
2221 | rc = falcon_reset_macs(efx); |
2222 | out: | |
2223 | efx_stats_enable(efx); | |
2224 | return rc; | |
177dfcd8 BH |
2225 | } |
2226 | ||
8ceee660 BH |
2227 | /* This call is responsible for hooking in the MAC and PHY operations */ |
2228 | int falcon_probe_port(struct efx_nic *efx) | |
2229 | { | |
2230 | int rc; | |
2231 | ||
96c45726 BH |
2232 | switch (efx->phy_type) { |
2233 | case PHY_TYPE_SFX7101: | |
2234 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
2235 | break; | |
2236 | case PHY_TYPE_SFT9001A: | |
2237 | case PHY_TYPE_SFT9001B: | |
2238 | efx->phy_op = &falcon_sft9001_phy_ops; | |
2239 | break; | |
2240 | case PHY_TYPE_QT2022C2: | |
2241 | case PHY_TYPE_QT2025C: | |
b37b62fe | 2242 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 BH |
2243 | break; |
2244 | default: | |
2245 | EFX_ERR(efx, "Unknown PHY type %d\n", | |
2246 | efx->phy_type); | |
2247 | return -ENODEV; | |
2248 | } | |
2249 | ||
2250 | if (efx->phy_op->macs & EFX_XMAC) | |
2251 | efx->loopback_modes |= ((1 << LOOPBACK_XGMII) | | |
2252 | (1 << LOOPBACK_XGXS) | | |
2253 | (1 << LOOPBACK_XAUI)); | |
2254 | if (efx->phy_op->macs & EFX_GMAC) | |
2255 | efx->loopback_modes |= (1 << LOOPBACK_GMAC); | |
2256 | efx->loopback_modes |= efx->phy_op->loopbacks; | |
8ceee660 | 2257 | |
68e7f45e BH |
2258 | /* Set up MDIO structure for PHY */ |
2259 | efx->mdio.mmds = efx->phy_op->mmds; | |
2260 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
2261 | efx->mdio.mdio_read = falcon_mdio_read; | |
2262 | efx->mdio.mdio_write = falcon_mdio_write; | |
8ceee660 BH |
2263 | |
2264 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ | |
55668611 | 2265 | if (falcon_rev(efx) >= FALCON_REV_B0) |
04cc8cac | 2266 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 2267 | else |
04cc8cac | 2268 | efx->wanted_fc = EFX_FC_RX; |
8ceee660 BH |
2269 | |
2270 | /* Allocate buffer for stats */ | |
2271 | rc = falcon_alloc_buffer(efx, &efx->stats_buffer, | |
2272 | FALCON_MAC_STATS_SIZE); | |
2273 | if (rc) | |
2274 | return rc; | |
9c8976a1 JSR |
2275 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", |
2276 | (u64)efx->stats_buffer.dma_addr, | |
8ceee660 | 2277 | efx->stats_buffer.addr, |
9c8976a1 | 2278 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
8ceee660 BH |
2279 | |
2280 | return 0; | |
2281 | } | |
2282 | ||
2283 | void falcon_remove_port(struct efx_nic *efx) | |
2284 | { | |
2285 | falcon_free_buffer(efx, &efx->stats_buffer); | |
2286 | } | |
2287 | ||
2288 | /************************************************************************** | |
2289 | * | |
2290 | * Multicast filtering | |
2291 | * | |
2292 | ************************************************************************** | |
2293 | */ | |
2294 | ||
2295 | void falcon_set_multicast_hash(struct efx_nic *efx) | |
2296 | { | |
2297 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
2298 | ||
2299 | /* Broadcast packets go through the multicast hash filter. | |
2300 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
2301 | * so we always add bit 0xff to the mask. | |
2302 | */ | |
2303 | set_bit_le(0xff, mc_hash->byte); | |
2304 | ||
12d00cad BH |
2305 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); |
2306 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
8ceee660 BH |
2307 | } |
2308 | ||
8c8661e4 BH |
2309 | |
2310 | /************************************************************************** | |
2311 | * | |
2312 | * Falcon test code | |
2313 | * | |
2314 | **************************************************************************/ | |
2315 | ||
2316 | int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
2317 | { | |
2318 | struct falcon_nvconfig *nvconfig; | |
2319 | struct efx_spi_device *spi; | |
2320 | void *region; | |
2321 | int rc, magic_num, struct_ver; | |
2322 | __le16 *word, *limit; | |
2323 | u32 csum; | |
2324 | ||
2f7f5730 BH |
2325 | spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; |
2326 | if (!spi) | |
2327 | return -EINVAL; | |
2328 | ||
0a95f563 | 2329 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
2330 | if (!region) |
2331 | return -ENOMEM; | |
3e6c4538 | 2332 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 2333 | |
f4150724 | 2334 | mutex_lock(&efx->spi_lock); |
0a95f563 | 2335 | rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); |
f4150724 | 2336 | mutex_unlock(&efx->spi_lock); |
8c8661e4 BH |
2337 | if (rc) { |
2338 | EFX_ERR(efx, "Failed to read %s\n", | |
2339 | efx->spi_flash ? "flash" : "EEPROM"); | |
2340 | rc = -EIO; | |
2341 | goto out; | |
2342 | } | |
2343 | ||
2344 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
2345 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
2346 | ||
2347 | rc = -EINVAL; | |
3e6c4538 | 2348 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
8c8661e4 BH |
2349 | EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); |
2350 | goto out; | |
2351 | } | |
2352 | if (struct_ver < 2) { | |
2353 | EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver); | |
2354 | goto out; | |
2355 | } else if (struct_ver < 4) { | |
2356 | word = &nvconfig->board_magic_num; | |
2357 | limit = (__le16 *) (nvconfig + 1); | |
2358 | } else { | |
2359 | word = region; | |
0a95f563 | 2360 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
2361 | } |
2362 | for (csum = 0; word < limit; ++word) | |
2363 | csum += le16_to_cpu(*word); | |
2364 | ||
2365 | if (~csum & 0xffff) { | |
2366 | EFX_ERR(efx, "NVRAM has incorrect checksum\n"); | |
2367 | goto out; | |
2368 | } | |
2369 | ||
2370 | rc = 0; | |
2371 | if (nvconfig_out) | |
2372 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
2373 | ||
2374 | out: | |
2375 | kfree(region); | |
2376 | return rc; | |
2377 | } | |
2378 | ||
2379 | /* Registers tested in the falcon register test */ | |
2380 | static struct { | |
2381 | unsigned address; | |
2382 | efx_oword_t mask; | |
2383 | } efx_test_registers[] = { | |
3e6c4538 | 2384 | { FR_AZ_ADR_REGION, |
8c8661e4 | 2385 | EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, |
3e6c4538 | 2386 | { FR_AZ_RX_CFG, |
8c8661e4 | 2387 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 2388 | { FR_AZ_TX_CFG, |
8c8661e4 | 2389 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2390 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 2391 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 2392 | { FR_AB_MAC_CTRL, |
8c8661e4 | 2393 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2394 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 2395 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2396 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 2397 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2398 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 2399 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2400 | { FR_BZ_DP_CTRL, |
8c8661e4 | 2401 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2402 | { FR_AB_GM_CFG2, |
177dfcd8 | 2403 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2404 | { FR_AB_GMF_CFG0, |
177dfcd8 | 2405 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2406 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 2407 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2408 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 2409 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2410 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 2411 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2412 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 2413 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2414 | { FR_AB_XM_FC, |
8c8661e4 | 2415 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2416 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 2417 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2418 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
2419 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
2420 | }; | |
2421 | ||
2422 | static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, | |
2423 | const efx_oword_t *mask) | |
2424 | { | |
2425 | return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || | |
2426 | ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); | |
2427 | } | |
2428 | ||
2429 | int falcon_test_registers(struct efx_nic *efx) | |
2430 | { | |
2431 | unsigned address = 0, i, j; | |
2432 | efx_oword_t mask, imask, original, reg, buf; | |
2433 | ||
2434 | /* Falcon should be in loopback to isolate the XMAC from the PHY */ | |
2435 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
2436 | ||
2437 | for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) { | |
2438 | address = efx_test_registers[i].address; | |
2439 | mask = imask = efx_test_registers[i].mask; | |
2440 | EFX_INVERT_OWORD(imask); | |
2441 | ||
12d00cad | 2442 | efx_reado(efx, &original, address); |
8c8661e4 BH |
2443 | |
2444 | /* bit sweep on and off */ | |
2445 | for (j = 0; j < 128; j++) { | |
2446 | if (!EFX_EXTRACT_OWORD32(mask, j, j)) | |
2447 | continue; | |
2448 | ||
2449 | /* Test this testable bit can be set in isolation */ | |
2450 | EFX_AND_OWORD(reg, original, mask); | |
2451 | EFX_SET_OWORD32(reg, j, j, 1); | |
2452 | ||
12d00cad BH |
2453 | efx_writeo(efx, ®, address); |
2454 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2455 | |
2456 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2457 | goto fail; | |
2458 | ||
2459 | /* Test this testable bit can be cleared in isolation */ | |
2460 | EFX_OR_OWORD(reg, original, mask); | |
2461 | EFX_SET_OWORD32(reg, j, j, 0); | |
2462 | ||
12d00cad BH |
2463 | efx_writeo(efx, ®, address); |
2464 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2465 | |
2466 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2467 | goto fail; | |
2468 | } | |
2469 | ||
12d00cad | 2470 | efx_writeo(efx, &original, address); |
8c8661e4 BH |
2471 | } |
2472 | ||
2473 | return 0; | |
2474 | ||
2475 | fail: | |
2476 | EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT | |
2477 | " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), | |
2478 | EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); | |
2479 | return -EIO; | |
2480 | } | |
2481 | ||
8ceee660 BH |
2482 | /************************************************************************** |
2483 | * | |
2484 | * Device reset | |
2485 | * | |
2486 | ************************************************************************** | |
2487 | */ | |
2488 | ||
2489 | /* Resets NIC to known state. This routine must be called in process | |
2490 | * context and is allowed to sleep. */ | |
2491 | int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) | |
2492 | { | |
2493 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2494 | efx_oword_t glb_ctl_reg_ker; | |
2495 | int rc; | |
2496 | ||
2497 | EFX_LOG(efx, "performing hardware reset (%d)\n", method); | |
2498 | ||
2499 | /* Initiate device reset */ | |
2500 | if (method == RESET_TYPE_WORLD) { | |
2501 | rc = pci_save_state(efx->pci_dev); | |
2502 | if (rc) { | |
2503 | EFX_ERR(efx, "failed to backup PCI state of primary " | |
2504 | "function prior to hardware reset\n"); | |
2505 | goto fail1; | |
2506 | } | |
2507 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2508 | rc = pci_save_state(nic_data->pci_dev2); | |
2509 | if (rc) { | |
2510 | EFX_ERR(efx, "failed to backup PCI state of " | |
2511 | "secondary function prior to " | |
2512 | "hardware reset\n"); | |
2513 | goto fail2; | |
2514 | } | |
2515 | } | |
2516 | ||
2517 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
2518 | FRF_AB_EXT_PHY_RST_DUR, |
2519 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2520 | FRF_AB_SWRST, 1); | |
8ceee660 | 2521 | } else { |
8ceee660 | 2522 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
2523 | /* exclude PHY from "invisible" reset */ |
2524 | FRF_AB_EXT_PHY_RST_CTL, | |
2525 | method == RESET_TYPE_INVISIBLE, | |
2526 | /* exclude EEPROM/flash and PCIe */ | |
2527 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
2528 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
2529 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
2530 | FRF_AB_EE_RST_CTL, 1, | |
2531 | FRF_AB_EXT_PHY_RST_DUR, | |
2532 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2533 | FRF_AB_SWRST, 1); | |
2534 | } | |
12d00cad | 2535 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 BH |
2536 | |
2537 | EFX_LOG(efx, "waiting for hardware reset\n"); | |
2538 | schedule_timeout_uninterruptible(HZ / 20); | |
2539 | ||
2540 | /* Restore PCI configuration if needed */ | |
2541 | if (method == RESET_TYPE_WORLD) { | |
2542 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2543 | rc = pci_restore_state(nic_data->pci_dev2); | |
2544 | if (rc) { | |
2545 | EFX_ERR(efx, "failed to restore PCI config for " | |
2546 | "the secondary function\n"); | |
2547 | goto fail3; | |
2548 | } | |
2549 | } | |
2550 | rc = pci_restore_state(efx->pci_dev); | |
2551 | if (rc) { | |
2552 | EFX_ERR(efx, "failed to restore PCI config for the " | |
2553 | "primary function\n"); | |
2554 | goto fail4; | |
2555 | } | |
2556 | EFX_LOG(efx, "successfully restored PCI config\n"); | |
2557 | } | |
2558 | ||
2559 | /* Assert that reset complete */ | |
12d00cad | 2560 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 2561 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 BH |
2562 | rc = -ETIMEDOUT; |
2563 | EFX_ERR(efx, "timed out waiting for hardware reset\n"); | |
2564 | goto fail5; | |
2565 | } | |
2566 | EFX_LOG(efx, "hardware reset complete\n"); | |
2567 | ||
2568 | return 0; | |
2569 | ||
2570 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
2571 | fail2: | |
2572 | fail3: | |
2573 | pci_restore_state(efx->pci_dev); | |
2574 | fail1: | |
2575 | fail4: | |
2576 | fail5: | |
2577 | return rc; | |
2578 | } | |
2579 | ||
2580 | /* Zeroes out the SRAM contents. This routine must be called in | |
2581 | * process context and is allowed to sleep. | |
2582 | */ | |
2583 | static int falcon_reset_sram(struct efx_nic *efx) | |
2584 | { | |
2585 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
2586 | int count; | |
2587 | ||
2588 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 2589 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
2590 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
2591 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 2592 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
2593 | |
2594 | /* Initiate SRAM reset */ | |
2595 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
2596 | FRF_AZ_SRM_INIT_EN, 1, |
2597 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 2598 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
2599 | |
2600 | /* Wait for SRAM reset to complete */ | |
2601 | count = 0; | |
2602 | do { | |
2603 | EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count); | |
2604 | ||
2605 | /* SRAM reset is slow; expect around 16ms */ | |
2606 | schedule_timeout_uninterruptible(HZ / 50); | |
2607 | ||
2608 | /* Check for reset complete */ | |
12d00cad | 2609 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 2610 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
8ceee660 BH |
2611 | EFX_LOG(efx, "SRAM reset complete\n"); |
2612 | ||
2613 | return 0; | |
2614 | } | |
2615 | } while (++count < 20); /* wait upto 0.4 sec */ | |
2616 | ||
2617 | EFX_ERR(efx, "timed out waiting for SRAM reset\n"); | |
2618 | return -ETIMEDOUT; | |
2619 | } | |
2620 | ||
4a5b504d BH |
2621 | static int falcon_spi_device_init(struct efx_nic *efx, |
2622 | struct efx_spi_device **spi_device_ret, | |
2623 | unsigned int device_id, u32 device_type) | |
2624 | { | |
2625 | struct efx_spi_device *spi_device; | |
2626 | ||
2627 | if (device_type != 0) { | |
0c53d8c8 | 2628 | spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL); |
4a5b504d BH |
2629 | if (!spi_device) |
2630 | return -ENOMEM; | |
2631 | spi_device->device_id = device_id; | |
2632 | spi_device->size = | |
2633 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
2634 | spi_device->addr_len = | |
2635 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
2636 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
2637 | spi_device->addr_len == 1); | |
f4150724 BH |
2638 | spi_device->erase_command = |
2639 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
2640 | spi_device->erase_size = | |
2641 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2642 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
2643 | spi_device->block_size = |
2644 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2645 | SPI_DEV_TYPE_BLOCK_SIZE); | |
2646 | ||
2647 | spi_device->efx = efx; | |
2648 | } else { | |
2649 | spi_device = NULL; | |
2650 | } | |
2651 | ||
2652 | kfree(*spi_device_ret); | |
2653 | *spi_device_ret = spi_device; | |
2654 | return 0; | |
2655 | } | |
2656 | ||
2657 | ||
2658 | static void falcon_remove_spi_devices(struct efx_nic *efx) | |
2659 | { | |
2660 | kfree(efx->spi_eeprom); | |
2661 | efx->spi_eeprom = NULL; | |
2662 | kfree(efx->spi_flash); | |
2663 | efx->spi_flash = NULL; | |
2664 | } | |
2665 | ||
8ceee660 BH |
2666 | /* Extract non-volatile configuration */ |
2667 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
2668 | { | |
2669 | struct falcon_nvconfig *nvconfig; | |
8c8661e4 | 2670 | int board_rev; |
8ceee660 BH |
2671 | int rc; |
2672 | ||
8ceee660 | 2673 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
2674 | if (!nvconfig) |
2675 | return -ENOMEM; | |
8ceee660 | 2676 | |
8c8661e4 BH |
2677 | rc = falcon_read_nvram(efx, nvconfig); |
2678 | if (rc == -EINVAL) { | |
2679 | EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); | |
8ceee660 | 2680 | efx->phy_type = PHY_TYPE_NONE; |
68e7f45e | 2681 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
8ceee660 | 2682 | board_rev = 0; |
8c8661e4 BH |
2683 | rc = 0; |
2684 | } else if (rc) { | |
2685 | goto fail1; | |
8ceee660 BH |
2686 | } else { |
2687 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; | |
4a5b504d | 2688 | struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; |
8ceee660 BH |
2689 | |
2690 | efx->phy_type = v2->port0_phy_type; | |
68e7f45e | 2691 | efx->mdio.prtad = v2->port0_phy_addr; |
8ceee660 | 2692 | board_rev = le16_to_cpu(v2->board_revision); |
4a5b504d | 2693 | |
8c8661e4 | 2694 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { |
3e6c4538 BH |
2695 | rc = falcon_spi_device_init( |
2696 | efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
2697 | le32_to_cpu(v3->spi_device_type | |
2698 | [FFE_AB_SPI_DEVICE_FLASH])); | |
4a5b504d BH |
2699 | if (rc) |
2700 | goto fail2; | |
3e6c4538 BH |
2701 | rc = falcon_spi_device_init( |
2702 | efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
2703 | le32_to_cpu(v3->spi_device_type | |
2704 | [FFE_AB_SPI_DEVICE_EEPROM])); | |
4a5b504d BH |
2705 | if (rc) |
2706 | goto fail2; | |
2707 | } | |
8ceee660 BH |
2708 | } |
2709 | ||
8c8661e4 BH |
2710 | /* Read the MAC addresses */ |
2711 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); | |
2712 | ||
68e7f45e | 2713 | EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad); |
8ceee660 | 2714 | |
3473a5b1 | 2715 | falcon_probe_board(efx, board_rev); |
8ceee660 | 2716 | |
4a5b504d BH |
2717 | kfree(nvconfig); |
2718 | return 0; | |
2719 | ||
2720 | fail2: | |
2721 | falcon_remove_spi_devices(efx); | |
2722 | fail1: | |
8ceee660 BH |
2723 | kfree(nvconfig); |
2724 | return rc; | |
2725 | } | |
2726 | ||
2727 | /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port | |
2728 | * count, port speed). Set workaround and feature flags accordingly. | |
2729 | */ | |
2730 | static int falcon_probe_nic_variant(struct efx_nic *efx) | |
2731 | { | |
2732 | efx_oword_t altera_build; | |
177dfcd8 | 2733 | efx_oword_t nic_stat; |
8ceee660 | 2734 | |
12d00cad | 2735 | efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); |
3e6c4538 | 2736 | if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) { |
8ceee660 BH |
2737 | EFX_ERR(efx, "Falcon FPGA not supported\n"); |
2738 | return -ENODEV; | |
2739 | } | |
2740 | ||
12d00cad | 2741 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
177dfcd8 | 2742 | |
55668611 | 2743 | switch (falcon_rev(efx)) { |
8ceee660 BH |
2744 | case FALCON_REV_A0: |
2745 | case 0xff: | |
2746 | EFX_ERR(efx, "Falcon rev A0 not supported\n"); | |
2747 | return -ENODEV; | |
2748 | ||
177dfcd8 | 2749 | case FALCON_REV_A1: |
3e6c4538 | 2750 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
8ceee660 BH |
2751 | EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); |
2752 | return -ENODEV; | |
2753 | } | |
8ceee660 | 2754 | break; |
8ceee660 BH |
2755 | |
2756 | case FALCON_REV_B0: | |
2757 | break; | |
2758 | ||
2759 | default: | |
55668611 | 2760 | EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx)); |
8ceee660 BH |
2761 | return -ENODEV; |
2762 | } | |
2763 | ||
177dfcd8 | 2764 | /* Initial assumed speed */ |
3e6c4538 | 2765 | efx->link_speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000; |
177dfcd8 | 2766 | |
8ceee660 BH |
2767 | return 0; |
2768 | } | |
2769 | ||
4a5b504d BH |
2770 | /* Probe all SPI devices on the NIC */ |
2771 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
2772 | { | |
2773 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; | |
2f7f5730 | 2774 | int boot_dev; |
4a5b504d | 2775 | |
12d00cad BH |
2776 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
2777 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2778 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 2779 | |
3e6c4538 BH |
2780 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
2781 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
2782 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
2f7f5730 | 2783 | EFX_LOG(efx, "Booted from %s\n", |
3e6c4538 | 2784 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM"); |
2f7f5730 BH |
2785 | } else { |
2786 | /* Disable VPD and set clock dividers to safe | |
2787 | * values for initial programming. */ | |
2788 | boot_dev = -1; | |
2789 | EFX_LOG(efx, "Booted from internal ASIC settings;" | |
2790 | " setting SPI config\n"); | |
3e6c4538 | 2791 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 2792 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 2793 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 2794 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 2795 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 2796 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
2797 | } |
2798 | ||
3e6c4538 BH |
2799 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
2800 | falcon_spi_device_init(efx, &efx->spi_flash, | |
2801 | FFE_AB_SPI_DEVICE_FLASH, | |
2f7f5730 | 2802 | default_flash_type); |
3e6c4538 BH |
2803 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
2804 | falcon_spi_device_init(efx, &efx->spi_eeprom, | |
2805 | FFE_AB_SPI_DEVICE_EEPROM, | |
2f7f5730 | 2806 | large_eeprom_type); |
4a5b504d BH |
2807 | } |
2808 | ||
8ceee660 BH |
2809 | int falcon_probe_nic(struct efx_nic *efx) |
2810 | { | |
2811 | struct falcon_nic_data *nic_data; | |
2812 | int rc; | |
2813 | ||
8ceee660 BH |
2814 | /* Allocate storage for hardware specific data */ |
2815 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
2816 | if (!nic_data) |
2817 | return -ENOMEM; | |
5daab96d | 2818 | efx->nic_data = nic_data; |
8ceee660 BH |
2819 | |
2820 | /* Determine number of ports etc. */ | |
2821 | rc = falcon_probe_nic_variant(efx); | |
2822 | if (rc) | |
2823 | goto fail1; | |
2824 | ||
2825 | /* Probe secondary function if expected */ | |
2826 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2827 | struct pci_dev *dev = pci_dev_get(efx->pci_dev); | |
2828 | ||
2829 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, | |
2830 | dev))) { | |
2831 | if (dev->bus == efx->pci_dev->bus && | |
2832 | dev->devfn == efx->pci_dev->devfn + 1) { | |
2833 | nic_data->pci_dev2 = dev; | |
2834 | break; | |
2835 | } | |
2836 | } | |
2837 | if (!nic_data->pci_dev2) { | |
2838 | EFX_ERR(efx, "failed to find secondary function\n"); | |
2839 | rc = -ENODEV; | |
2840 | goto fail2; | |
2841 | } | |
2842 | } | |
2843 | ||
2844 | /* Now we can reset the NIC */ | |
2845 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); | |
2846 | if (rc) { | |
2847 | EFX_ERR(efx, "failed to reset NIC\n"); | |
2848 | goto fail3; | |
2849 | } | |
2850 | ||
2851 | /* Allocate memory for INT_KER */ | |
2852 | rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
2853 | if (rc) | |
2854 | goto fail4; | |
2855 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
2856 | ||
9c8976a1 JSR |
2857 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n", |
2858 | (u64)efx->irq_status.dma_addr, | |
2859 | efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 2860 | |
4a5b504d BH |
2861 | falcon_probe_spi_devices(efx); |
2862 | ||
8ceee660 BH |
2863 | /* Read in the non-volatile configuration */ |
2864 | rc = falcon_probe_nvconfig(efx); | |
2865 | if (rc) | |
2866 | goto fail5; | |
2867 | ||
37b5a603 | 2868 | /* Initialise I2C adapter */ |
b4531938 | 2869 | efx->i2c_adap.owner = THIS_MODULE; |
37b5a603 BH |
2870 | nic_data->i2c_data = falcon_i2c_bit_operations; |
2871 | nic_data->i2c_data.data = efx; | |
b4531938 | 2872 | efx->i2c_adap.algo_data = &nic_data->i2c_data; |
37b5a603 | 2873 | efx->i2c_adap.dev.parent = &efx->pci_dev->dev; |
9dadae68 | 2874 | strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name)); |
37b5a603 BH |
2875 | rc = i2c_bit_add_bus(&efx->i2c_adap); |
2876 | if (rc) | |
2877 | goto fail5; | |
2878 | ||
8ceee660 BH |
2879 | return 0; |
2880 | ||
2881 | fail5: | |
4a5b504d | 2882 | falcon_remove_spi_devices(efx); |
8ceee660 BH |
2883 | falcon_free_buffer(efx, &efx->irq_status); |
2884 | fail4: | |
8ceee660 BH |
2885 | fail3: |
2886 | if (nic_data->pci_dev2) { | |
2887 | pci_dev_put(nic_data->pci_dev2); | |
2888 | nic_data->pci_dev2 = NULL; | |
2889 | } | |
2890 | fail2: | |
8ceee660 BH |
2891 | fail1: |
2892 | kfree(efx->nic_data); | |
2893 | return rc; | |
2894 | } | |
2895 | ||
56241ceb BH |
2896 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
2897 | { | |
2898 | /* Prior to Siena the RX DMA engine will split each frame at | |
2899 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | |
2900 | * be so large that that never happens. */ | |
2901 | const unsigned huge_buf_size = (3 * 4096) >> 5; | |
2902 | /* RX control FIFO thresholds (32 entries) */ | |
2903 | const unsigned ctrl_xon_thr = 20; | |
2904 | const unsigned ctrl_xoff_thr = 25; | |
2905 | /* RX data FIFO thresholds (256-byte units; size varies) */ | |
625b4514 BH |
2906 | int data_xon_thr = rx_xon_thresh_bytes >> 8; |
2907 | int data_xoff_thr = rx_xoff_thresh_bytes >> 8; | |
56241ceb BH |
2908 | efx_oword_t reg; |
2909 | ||
12d00cad | 2910 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
56241ceb | 2911 | if (falcon_rev(efx) <= FALCON_REV_A1) { |
625b4514 BH |
2912 | /* Data FIFO size is 5.5K */ |
2913 | if (data_xon_thr < 0) | |
2914 | data_xon_thr = 512 >> 8; | |
2915 | if (data_xoff_thr < 0) | |
2916 | data_xoff_thr = 2048 >> 8; | |
3e6c4538 BH |
2917 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
2918 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
2919 | huge_buf_size); | |
2920 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); | |
2921 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); | |
2922 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | |
2923 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 2924 | } else { |
625b4514 BH |
2925 | /* Data FIFO size is 80K; register fields moved */ |
2926 | if (data_xon_thr < 0) | |
2927 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ | |
2928 | if (data_xoff_thr < 0) | |
2929 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ | |
3e6c4538 BH |
2930 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
2931 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
2932 | huge_buf_size); | |
2933 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); | |
2934 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); | |
2935 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | |
2936 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
2937 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
56241ceb | 2938 | } |
12d00cad | 2939 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
2940 | } |
2941 | ||
8ceee660 BH |
2942 | /* This call performs hardware-specific global initialisation, such as |
2943 | * defining the descriptor cache sizes and number of RSS channels. | |
2944 | * It does not set up any buffers, descriptor rings or event queues. | |
2945 | */ | |
2946 | int falcon_init_nic(struct efx_nic *efx) | |
2947 | { | |
8ceee660 | 2948 | efx_oword_t temp; |
8ceee660 BH |
2949 | int rc; |
2950 | ||
8ceee660 | 2951 | /* Use on-chip SRAM */ |
12d00cad | 2952 | efx_reado(efx, &temp, FR_AB_NIC_STAT); |
3e6c4538 | 2953 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); |
12d00cad | 2954 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); |
8ceee660 | 2955 | |
6f158d5f BH |
2956 | /* Set the source of the GMAC clock */ |
2957 | if (falcon_rev(efx) == FALCON_REV_B0) { | |
12d00cad | 2958 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); |
3e6c4538 | 2959 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); |
12d00cad | 2960 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); |
6f158d5f BH |
2961 | } |
2962 | ||
8ceee660 BH |
2963 | rc = falcon_reset_sram(efx); |
2964 | if (rc) | |
2965 | return rc; | |
2966 | ||
2967 | /* Set positions of descriptor caches in SRAM. */ | |
3e6c4538 | 2968 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); |
12d00cad | 2969 | efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); |
3e6c4538 | 2970 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); |
12d00cad | 2971 | efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); |
8ceee660 BH |
2972 | |
2973 | /* Set TX descriptor cache size. */ | |
2974 | BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER)); | |
3e6c4538 | 2975 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); |
12d00cad | 2976 | efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); |
8ceee660 BH |
2977 | |
2978 | /* Set RX descriptor cache size. Set low watermark to size-8, as | |
2979 | * this allows most efficient prefetching. | |
2980 | */ | |
2981 | BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER)); | |
3e6c4538 | 2982 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); |
12d00cad | 2983 | efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); |
3e6c4538 | 2984 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); |
12d00cad | 2985 | efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); |
8ceee660 BH |
2986 | |
2987 | /* Clear the parity enables on the TX data fifos as | |
2988 | * they produce false parity errors because of timing issues | |
2989 | */ | |
2990 | if (EFX_WORKAROUND_5129(efx)) { | |
12d00cad | 2991 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); |
3e6c4538 | 2992 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); |
12d00cad | 2993 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); |
8ceee660 BH |
2994 | } |
2995 | ||
2996 | /* Enable all the genuinely fatal interrupts. (They are still | |
2997 | * masked by the overall interrupt mask, controlled by | |
2998 | * falcon_interrupts()). | |
2999 | * | |
3000 | * Note: All other fatal interrupts are enabled | |
3001 | */ | |
3002 | EFX_POPULATE_OWORD_3(temp, | |
3e6c4538 BH |
3003 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, |
3004 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, | |
3005 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); | |
8ceee660 | 3006 | EFX_INVERT_OWORD(temp); |
12d00cad | 3007 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); |
8ceee660 | 3008 | |
8ceee660 | 3009 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 3010 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
3011 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
3012 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
3013 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
3014 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 3015 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 3016 | } |
8ceee660 BH |
3017 | |
3018 | falcon_setup_rss_indir_table(efx); | |
3019 | ||
3e6c4538 | 3020 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
3021 | /* Setup RX. Wait for descriptor is broken and must |
3022 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
3023 | */ | |
12d00cad | 3024 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
3025 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
3026 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 3027 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 3028 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 3029 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 BH |
3030 | |
3031 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be | |
3032 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. | |
3033 | */ | |
12d00cad | 3034 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); |
3e6c4538 BH |
3035 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); |
3036 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); | |
3037 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); | |
3038 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0); | |
3039 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); | |
8ceee660 | 3040 | /* Enable SW_EV to inherit in char driver - assume harmless here */ |
3e6c4538 | 3041 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); |
8ceee660 | 3042 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ |
3e6c4538 | 3043 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); |
8ceee660 | 3044 | /* Squash TX of packets of 16 bytes or less */ |
55668611 | 3045 | if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx)) |
3e6c4538 | 3046 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); |
12d00cad | 3047 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); |
8ceee660 BH |
3048 | |
3049 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
3050 | * descriptors (which is bad). | |
3051 | */ | |
12d00cad | 3052 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 3053 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 3054 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 3055 | |
56241ceb | 3056 | falcon_init_rx_cfg(efx); |
8ceee660 BH |
3057 | |
3058 | /* Set destination of both TX and RX Flush events */ | |
55668611 | 3059 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
3e6c4538 | 3060 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 3061 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
3062 | } |
3063 | ||
3064 | return 0; | |
3065 | } | |
3066 | ||
3067 | void falcon_remove_nic(struct efx_nic *efx) | |
3068 | { | |
3069 | struct falcon_nic_data *nic_data = efx->nic_data; | |
37b5a603 BH |
3070 | int rc; |
3071 | ||
8c870379 | 3072 | /* Remove I2C adapter and clear it in preparation for a retry */ |
37b5a603 BH |
3073 | rc = i2c_del_adapter(&efx->i2c_adap); |
3074 | BUG_ON(rc); | |
8c870379 | 3075 | memset(&efx->i2c_adap, 0, sizeof(efx->i2c_adap)); |
8ceee660 | 3076 | |
4a5b504d | 3077 | falcon_remove_spi_devices(efx); |
8ceee660 BH |
3078 | falcon_free_buffer(efx, &efx->irq_status); |
3079 | ||
91ad757c | 3080 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
3081 | |
3082 | /* Release the second function after the reset */ | |
3083 | if (nic_data->pci_dev2) { | |
3084 | pci_dev_put(nic_data->pci_dev2); | |
3085 | nic_data->pci_dev2 = NULL; | |
3086 | } | |
3087 | ||
3088 | /* Tear down the private nic state */ | |
3089 | kfree(efx->nic_data); | |
3090 | efx->nic_data = NULL; | |
3091 | } | |
3092 | ||
3093 | void falcon_update_nic_stats(struct efx_nic *efx) | |
3094 | { | |
3095 | efx_oword_t cnt; | |
3096 | ||
12d00cad | 3097 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
3098 | efx->n_rx_nodesc_drop_cnt += |
3099 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
8ceee660 BH |
3100 | } |
3101 | ||
3102 | /************************************************************************** | |
3103 | * | |
3104 | * Revision-dependent attributes used by efx.c | |
3105 | * | |
3106 | ************************************************************************** | |
3107 | */ | |
3108 | ||
3109 | struct efx_nic_type falcon_a_nic_type = { | |
8ceee660 | 3110 | .mem_map_size = 0x20000, |
3e6c4538 BH |
3111 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
3112 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
3113 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
3114 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
3115 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 3116 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3117 | .rx_buffer_padding = 0x24, |
3118 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
3119 | .phys_addr_channels = 4, | |
3120 | }; | |
3121 | ||
3122 | struct efx_nic_type falcon_b_nic_type = { | |
8ceee660 BH |
3123 | /* Map everything up to and including the RSS indirection |
3124 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
3125 | * requires that they not be mapped. */ | |
3e6c4538 BH |
3126 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
3127 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
3128 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
3129 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
3130 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
3131 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
3132 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
3133 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 3134 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3135 | .rx_buffer_padding = 0, |
3136 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3137 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
3138 | * interrupt handler only supports 32 | |
3139 | * channels */ | |
3140 | }; | |
3141 |