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sfc: Remove efx_nic_dummy_op_int() as redundant with efx_port_dummy_op_int()
[deliverable/linux.git] / drivers / net / sfc / falcon_xmac.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/delay.h>
12#include "net_driver.h"
13#include "efx.h"
14#include "falcon.h"
15#include "falcon_hwdefs.h"
16#include "falcon_io.h"
17#include "mac.h"
18#include "gmii.h"
19#include "mdio_10g.h"
20#include "phy.h"
21#include "boards.h"
22#include "workarounds.h"
23
24/**************************************************************************
25 *
26 * MAC register access
27 *
28 **************************************************************************/
29
30/* Offset of an XMAC register within Falcon */
31#define FALCON_XMAC_REG(mac_reg) \
32 (FALCON_XMAC_REGBANK + ((mac_reg) * FALCON_XMAC_REG_SIZE))
33
34void falcon_xmac_writel(struct efx_nic *efx,
e52eddae 35 efx_dword_t *value, unsigned int mac_reg)
8ceee660
BH		 36{
37 efx_oword_t temp;
38
39 EFX_POPULATE_OWORD_1(temp, MAC_DATA, EFX_DWORD_FIELD(*value, MAC_DATA));
40 falcon_write(efx, &temp, FALCON_XMAC_REG(mac_reg));
41}
42
43void falcon_xmac_readl(struct efx_nic *efx,
44 efx_dword_t *value, unsigned int mac_reg)
45{
46 efx_oword_t temp;
47
48 falcon_read(efx, &temp, FALCON_XMAC_REG(mac_reg));
49 EFX_POPULATE_DWORD_1(*value, MAC_DATA, EFX_OWORD_FIELD(temp, MAC_DATA));
50}
51
52/**************************************************************************
53 *
54 * MAC operations
55 *
56 *************************************************************************/
57static int falcon_reset_xmac(struct efx_nic *efx)
58{
59 efx_dword_t reg;
60 int count;
61
62 EFX_POPULATE_DWORD_1(reg, XM_CORE_RST, 1);
63 falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC);
64
65 for (count = 0; count < 10000; count++) { /* wait upto 100ms */
66 falcon_xmac_readl(efx, &reg, XM_GLB_CFG_REG_MAC);
67 if (EFX_DWORD_FIELD(reg, XM_CORE_RST) == 0)
68 return 0;
69 udelay(10);
70 }
71
72 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
73 return -ETIMEDOUT;
74}
75
76/* Configure the XAUI driver that is an output from Falcon */
77static void falcon_setup_xaui(struct efx_nic *efx)
78{
79 efx_dword_t sdctl, txdrv;
80
81 /* Move the XAUI into low power, unless there is no PHY, in
82 * which case the XAUI will have to drive a cable. */
83 if (efx->phy_type == PHY_TYPE_NONE)
84 return;
85
86 falcon_xmac_readl(efx, &sdctl, XX_SD_CTL_REG_MAC);
87 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
88 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
89 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
90 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
91 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
92 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
93 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
94 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
95 falcon_xmac_writel(efx, &sdctl, XX_SD_CTL_REG_MAC);
96
97 EFX_POPULATE_DWORD_8(txdrv,
98 XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
99 XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
100 XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
101 XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
102 XX_DTXD, XX_TXDRV_DTX_DEFAULT,
103 XX_DTXC, XX_TXDRV_DTX_DEFAULT,
104 XX_DTXB, XX_TXDRV_DTX_DEFAULT,
105 XX_DTXA, XX_TXDRV_DTX_DEFAULT);
106 falcon_xmac_writel(efx, &txdrv, XX_TXDRV_CTL_REG_MAC);
107}
108
109static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
110{
111 efx_dword_t reg;
112
113 EFX_ZERO_DWORD(reg);
114 EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 1);
115 EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 1);
116 EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 1);
117 EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 1);
118 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
119 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
120 EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 1);
121 EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 1);
122 EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 1);
123 EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 1);
124 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
125 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
126 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
127 udelay(10);
128}
129
130static int _falcon_reset_xaui_a(struct efx_nic *efx)
131{
132 efx_dword_t reg;
133
134 falcon_hold_xaui_in_rst(efx);
135 falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);
136
137 /* Follow the RAMBUS XAUI data reset sequencing
138 * Channels A and B first: power down, reset PLL, reset, clear
139 */
140 EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 0);
141 EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 0);
142 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
143 udelay(10);
144
145 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
146 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
147 udelay(10);
148
149 EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 0);
150 EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 0);
151 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
152 udelay(10);
153
154 /* Channels C and D: power down, reset PLL, reset, clear */
155 EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 0);
156 EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 0);
157 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
158 udelay(10);
159
160 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
161 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
162 udelay(10);
163
164 EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 0);
165 EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 0);
166 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
167 udelay(10);
168
169 /* Setup XAUI */
170 falcon_setup_xaui(efx);
171 udelay(10);
172
173 /* Take XGXS out of reset */
174 EFX_ZERO_DWORD(reg);
175 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
176 udelay(10);
177
178 return 0;
179}
180
181static int _falcon_reset_xaui_b(struct efx_nic *efx)
182{
183 efx_dword_t reg;
184 int count;
185
186 EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
187 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
188
189 /* Give some time for the link to establish */
190 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
191 falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);
192 if (EFX_DWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
193 falcon_setup_xaui(efx);
194 return 0;
195 }
196 udelay(10);
197 }
198 EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
199 return -ETIMEDOUT;
200}
201
202int falcon_reset_xaui(struct efx_nic *efx)
203{
204 int rc;
205
206 if (EFX_WORKAROUND_9388(efx)) {
207 falcon_hold_xaui_in_rst(efx);
208 efx->phy_op->reset_xaui(efx);
209 rc = _falcon_reset_xaui_a(efx);
210 } else {
211 rc = _falcon_reset_xaui_b(efx);
212 }
213 return rc;
214}
215
dc8cfa55 216static bool falcon_xgmii_status(struct efx_nic *efx)
8ceee660
BH		 217{
218 efx_dword_t reg;
219
55668611 220 if (falcon_rev(efx) < FALCON_REV_B0)
dc8cfa55 221 return true;
8ceee660
BH		 222
223 /* The ISR latches, so clear it and re-read */
224 falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
225 falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
e52eddae 226
8ceee660
BH		 227 if (EFX_DWORD_FIELD(reg, XM_LCLFLT) ||
228 EFX_DWORD_FIELD(reg, XM_RMTFLT)) {
229 EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
dc8cfa55 230 return false;
8ceee660
BH		 231 }
232
dc8cfa55 233 return true;
8ceee660
BH		 234}
235
dc8cfa55 236static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
8ceee660
BH		 237{
238 efx_dword_t reg;
239
55668611 240 if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
8ceee660
BH		 241 return;
242
243 /* Flush the ISR */
244 if (enable)
245 falcon_xmac_readl(efx, &reg, XM_MGT_INT_REG_MAC_B0);
246
247 EFX_POPULATE_DWORD_2(reg,
248 XM_MSK_RMTFLT, !enable,
249 XM_MSK_LCLFLT, !enable);
250 falcon_xmac_writel(efx, &reg, XM_MGT_INT_MSK_REG_MAC_B0);
251}
252
253int falcon_init_xmac(struct efx_nic *efx)
254{
255 int rc;
256
257 /* Initialize the PHY first so the clock is around */
258 rc = efx->phy_op->init(efx);
259 if (rc)
260 goto fail1;
261
262 rc = falcon_reset_xaui(efx);
263 if (rc)
264 goto fail2;
265
266 /* Wait again. Give the PHY and MAC time to come back */
267 schedule_timeout_uninterruptible(HZ / 10);
268
269 rc = falcon_reset_xmac(efx);
270 if (rc)
271 goto fail2;
272
dc8cfa55 273 falcon_mask_status_intr(efx, true);
8ceee660
BH		 274 return 0;
275
276 fail2:
277 efx->phy_op->fini(efx);
278 fail1:
279 return rc;
280}
281
dc8cfa55 282bool falcon_xaui_link_ok(struct efx_nic *efx)
8ceee660
BH		 283{
284 efx_dword_t reg;
dc8cfa55
BH		 285 bool align_done, link_ok = false;
286 int sync_status;
8ceee660 287
3273c2e8 288 if (LOOPBACK_INTERNAL(efx))
dc8cfa55 289 return true;
3273c2e8 290
8ceee660
BH		 291 /* Read link status */
292 falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC);
293
294 align_done = EFX_DWORD_FIELD(reg, XX_ALIGN_DONE);
295 sync_status = EFX_DWORD_FIELD(reg, XX_SYNC_STAT);
296 if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
dc8cfa55 297 link_ok = true;
8ceee660
BH		 298
299 /* Clear link status ready for next read */
300 EFX_SET_DWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
301 EFX_SET_DWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
302 EFX_SET_DWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
303 falcon_xmac_writel(efx, &reg, XX_CORE_STAT_REG_MAC);
304
305 /* If the link is up, then check the phy side of the xaui link
306 * (error conditions from the wire side propoagate back through
307 * the phy to the xaui side). */
308 if (efx->link_up && link_ok) {
dc8cfa55 309 if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
8ceee660
BH		 310 link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
311 }
312
313 /* If the PHY and XAUI links are up, then check the mac's xgmii
314 * fault state */
315 if (efx->link_up && link_ok)
316 link_ok = falcon_xgmii_status(efx);
317
318 return link_ok;
319}
320
321static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
322{
323 unsigned int max_frame_len;
324 efx_dword_t reg;
dc8cfa55 325 bool rx_fc = !!(efx->flow_control & EFX_FC_RX);
8ceee660
BH		 326
327 /* Configure MAC - cut-thru mode is hard wired on */
328 EFX_POPULATE_DWORD_3(reg,
329 XM_RX_JUMBO_MODE, 1,
330 XM_TX_STAT_EN, 1,
331 XM_RX_STAT_EN, 1);
332 falcon_xmac_writel(efx, &reg, XM_GLB_CFG_REG_MAC);
333
334 /* Configure TX */
335 EFX_POPULATE_DWORD_6(reg,
336 XM_TXEN, 1,
337 XM_TX_PRMBL, 1,
338 XM_AUTO_PAD, 1,
339 XM_TXCRC, 1,
340 XM_FCNTL, 1,
341 XM_IPG, 0x3);
342 falcon_xmac_writel(efx, &reg, XM_TX_CFG_REG_MAC);
343
344 /* Configure RX */
345 EFX_POPULATE_DWORD_5(reg,
346 XM_RXEN, 1,
347 XM_AUTO_DEPAD, 0,
348 XM_ACPT_ALL_MCAST, 1,
349 XM_ACPT_ALL_UCAST, efx->promiscuous,
350 XM_PASS_CRC_ERR, 1);
351 falcon_xmac_writel(efx, &reg, XM_RX_CFG_REG_MAC);
352
353 /* Set frame length */
354 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
355 EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
356 falcon_xmac_writel(efx, &reg, XM_RX_PARAM_REG_MAC);
357 EFX_POPULATE_DWORD_2(reg,
358 XM_MAX_TX_FRM_SIZE, max_frame_len,
359 XM_TX_JUMBO_MODE, 1);
360 falcon_xmac_writel(efx, &reg, XM_TX_PARAM_REG_MAC);
361
362 EFX_POPULATE_DWORD_2(reg,
363 XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
dc8cfa55 364 XM_DIS_FCNTL, !rx_fc);
8ceee660
BH		 365 falcon_xmac_writel(efx, &reg, XM_FC_REG_MAC);
366
367 /* Set MAC address */
368 EFX_POPULATE_DWORD_4(reg,
369 XM_ADR_0, efx->net_dev->dev_addr[0],
370 XM_ADR_1, efx->net_dev->dev_addr[1],
371 XM_ADR_2, efx->net_dev->dev_addr[2],
372 XM_ADR_3, efx->net_dev->dev_addr[3]);
373 falcon_xmac_writel(efx, &reg, XM_ADR_LO_REG_MAC);
374 EFX_POPULATE_DWORD_2(reg,
375 XM_ADR_4, efx->net_dev->dev_addr[4],
376 XM_ADR_5, efx->net_dev->dev_addr[5]);
377 falcon_xmac_writel(efx, &reg, XM_ADR_HI_REG_MAC);
378}
379
3273c2e8
BH		 380static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
381{
382 efx_dword_t reg;
dc8cfa55
BH		 383 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
384 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
385 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
3273c2e8
BH		 386
387 /* XGXS block is flaky and will need to be reset if moving
388 * into our out of XGMII, XGXS or XAUI loopbacks. */
389 if (EFX_WORKAROUND_5147(efx)) {
dc8cfa55
BH		 390 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
391 bool reset_xgxs;
3273c2e8
BH		 392
393 falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC);
394 old_xgxs_loopback = EFX_DWORD_FIELD(reg, XX_XGXS_LB_EN);
395 old_xgmii_loopback = EFX_DWORD_FIELD(reg, XX_XGMII_LB_EN);
396
397 falcon_xmac_readl(efx, &reg, XX_SD_CTL_REG_MAC);
398 old_xaui_loopback = EFX_DWORD_FIELD(reg, XX_LPBKA);
399
400 /* The PHY driver may have turned XAUI off */
401 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
402 (xaui_loopback != old_xaui_loopback) ||
403 (xgmii_loopback != old_xgmii_loopback));
404 if (reset_xgxs) {
405 falcon_xmac_readl(efx, &reg, XX_PWR_RST_REG_MAC);
406 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
407 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
408 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
409 udelay(1);
410 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 0);
411 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 0);
412 falcon_xmac_writel(efx, &reg, XX_PWR_RST_REG_MAC);
413 udelay(1);
414 }
415 }
416
417 falcon_xmac_readl(efx, &reg, XX_CORE_STAT_REG_MAC);
418 EFX_SET_DWORD_FIELD(reg, XX_FORCE_SIG,
419 (xgxs_loopback || xaui_loopback) ?
420 XX_FORCE_SIG_DECODE_FORCED : 0);
421 EFX_SET_DWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
422 EFX_SET_DWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
423 falcon_xmac_writel(efx, &reg, XX_CORE_STAT_REG_MAC);
424
425 falcon_xmac_readl(efx, &reg, XX_SD_CTL_REG_MAC);
426 EFX_SET_DWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
427 EFX_SET_DWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
428 EFX_SET_DWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
429 EFX_SET_DWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
430 falcon_xmac_writel(efx, &reg, XX_SD_CTL_REG_MAC);
431}
432
433
8ceee660
BH		 434/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
435 * to come back up. Bash it until it comes back up */
dc8cfa55 436static bool falcon_check_xaui_link_up(struct efx_nic *efx)
8ceee660
BH		 437{
438 int max_tries, tries;
439 tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
440 max_tries = tries;
441
3273c2e8 442 if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
f8b87c17
BH		 443 (efx->phy_type == PHY_TYPE_NONE) ||
444 efx_phy_mode_disabled(efx->phy_mode))
dc8cfa55 445 return false;
8ceee660
BH		 446
447 while (tries) {
448 if (falcon_xaui_link_ok(efx))
dc8cfa55 449 return true;
8ceee660
BH		 450
451 EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
452 __func__, tries);
91ad757c 453 falcon_reset_xaui(efx);
8ceee660
BH		 454 udelay(200);
455 tries--;
456 }
457
b055629e 458 EFX_LOG(efx, "Failed to bring XAUI link back up in %d tries!\n",
8ceee660 459 max_tries);
dc8cfa55 460 return false;
8ceee660
BH		 461}
462
463void falcon_reconfigure_xmac(struct efx_nic *efx)
464{
dc8cfa55 465 bool xaui_link_ok;
8ceee660 466
dc8cfa55 467 falcon_mask_status_intr(efx, false);
8ceee660
BH		 468
469 falcon_deconfigure_mac_wrapper(efx);
3273c2e8 470
f8b87c17
BH		 471 /* Reconfigure the PHY, disabling transmit in mac level loopback. */
472 if (LOOPBACK_INTERNAL(efx))
473 efx->phy_mode |= PHY_MODE_TX_DISABLED;
474 else
475 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
8ceee660 476 efx->phy_op->reconfigure(efx);
3273c2e8
BH		 477
478 falcon_reconfigure_xgxs_core(efx);
8ceee660 479 falcon_reconfigure_xmac_core(efx);
3273c2e8 480
8ceee660
BH		 481 falcon_reconfigure_mac_wrapper(efx);
482
483 /* Ensure XAUI link is up */
484 xaui_link_ok = falcon_check_xaui_link_up(efx);
485
486 if (xaui_link_ok && efx->link_up)
dc8cfa55 487 falcon_mask_status_intr(efx, true);
8ceee660
BH		 488}
489
490void falcon_fini_xmac(struct efx_nic *efx)
491{
492 /* Isolate the MAC - PHY */
493 falcon_deconfigure_mac_wrapper(efx);
494
495 /* Potentially power down the PHY */
496 efx->phy_op->fini(efx);
497}
498
499void falcon_update_stats_xmac(struct efx_nic *efx)
500{
501 struct efx_mac_stats *mac_stats = &efx->mac_stats;
502 int rc;
503
504 rc = falcon_dma_stats(efx, XgDmaDone_offset);
505 if (rc)
506 return;
507
508 /* Update MAC stats from DMAed values */
509 FALCON_STAT(efx, XgRxOctets, rx_bytes);
510 FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
511 FALCON_STAT(efx, XgRxPkts, rx_packets);
512 FALCON_STAT(efx, XgRxPktsOK, rx_good);
513 FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
514 FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
515 FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
516 FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
517 FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
518 FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
519 FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
520 FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
521 FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
522 FALCON_STAT(efx, XgRxAlignError, rx_align_error);
523 FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
524 FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
525 FALCON_STAT(efx, XgRxControlPkts, rx_control);
526 FALCON_STAT(efx, XgRxPausePkts, rx_pause);
527 FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
528 FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
529 FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
530 FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
531 FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
532 FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
533 FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
534 FALCON_STAT(efx, XgRxLengthError, rx_length_error);
535 FALCON_STAT(efx, XgTxPkts, tx_packets);
536 FALCON_STAT(efx, XgTxOctets, tx_bytes);
537 FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
538 FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
539 FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
540 FALCON_STAT(efx, XgTxControlPkts, tx_control);
541 FALCON_STAT(efx, XgTxPausePkts, tx_pause);
542 FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
543 FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
544 FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
545 FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
546 FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
547 FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
548 FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
549 FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
550 FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
551 FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
552 FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
553 FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
554
555 /* Update derived statistics */
556 mac_stats->tx_good_bytes =
c264361d
BH		 557 (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
558 mac_stats->tx_control * 64);
8ceee660 559 mac_stats->rx_bad_bytes =
c264361d
BH		 560 (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
561 mac_stats->rx_control * 64);
8ceee660
BH		 562}
563
8ceee660
BH		 564int falcon_check_xmac(struct efx_nic *efx)
565{
dc8cfa55 566 bool xaui_link_ok;
8ceee660
BH		 567 int rc;
568
3273c2e8 569 if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
f8b87c17 570 efx_phy_mode_disabled(efx->phy_mode))
3273c2e8
BH		 571 return 0;
572
dc8cfa55 573 falcon_mask_status_intr(efx, false);
8ceee660
BH		 574 xaui_link_ok = falcon_xaui_link_ok(efx);
575
576 if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
91ad757c 577 falcon_reset_xaui(efx);
8ceee660
BH		 578
579 /* Call the PHY check_hw routine */
580 rc = efx->phy_op->check_hw(efx);
581
582 /* Unmask interrupt if everything was (and still is) ok */
583 if (xaui_link_ok && efx->link_up)
dc8cfa55 584 falcon_mask_status_intr(efx, true);
8ceee660
BH		 585
586 return rc;
587}
588
589/* Simulate a PHY event */
590void falcon_xmac_sim_phy_event(struct efx_nic *efx)
591{
592 efx_qword_t phy_event;
593
594 EFX_POPULATE_QWORD_2(phy_event,
595 EV_CODE, GLOBAL_EV_DECODE,
596 XG_PHY_INTR, 1);
597 falcon_generate_event(&efx->channel[0], &phy_event);
598}
599
600int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
601{
602 mdio_clause45_get_settings(efx, ecmd);
603 ecmd->transceiver = XCVR_INTERNAL;
604 ecmd->phy_address = efx->mii.phy_id;
605 ecmd->autoneg = AUTONEG_DISABLE;
606 ecmd->duplex = DUPLEX_FULL;
607 return 0;
608}
609
610int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
611{
612 if (ecmd->transceiver != XCVR_INTERNAL)
613 return -EINVAL;
614 if (ecmd->autoneg != AUTONEG_DISABLE)
615 return -EINVAL;
616 if (ecmd->duplex != DUPLEX_FULL)
617 return -EINVAL;
618
619 return mdio_clause45_set_settings(efx, ecmd);
620}
621
622
623int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
624{
dc8cfa55 625 bool reset;
8ceee660
BH		 626
627 if (flow_control & EFX_FC_AUTO) {
628 EFX_LOG(efx, "10G does not support flow control "
629 "autonegotiation\n");
630 return -EINVAL;
631 }
632
633 if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
634 return -EINVAL;
635
636 /* TX flow control may automatically turn itself off if the
637 * link partner (intermittently) stops responding to pause
638 * frames. There isn't any indication that this has happened,
639 * so the best we do is leave it up to the user to spot this
640 * and fix it be cycling transmit flow control on this end. */
641 reset = ((flow_control & EFX_FC_TX) &&
642 !(efx->flow_control & EFX_FC_TX));
643 if (EFX_WORKAROUND_11482(efx) && reset) {
55668611 644 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 645 /* Recover by resetting the EM block */
646 if (efx->link_up)
647 falcon_drain_tx_fifo(efx);
648 } else {
649 /* Schedule a reset to recover */
650 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
651 }
652 }
653
654 efx->flow_control = flow_control;
655
656 return 0;
657}
Linux kernel - Deliverables
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