[deliverable/linux.git] / drivers / net / sfc / falcon_xmac.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2008 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/delay.h>
#include "net_driver.h"
#include "efx.h"
#include "falcon.h"
#include "falcon_hwdefs.h"
#include "falcon_io.h"
#include "mac.h"
#include "mdio_10g.h"
#include "phy.h"
#include "boards.h"
#include "workarounds.h"

/**************************************************************************
 *
 * MAC operations
 *
 *************************************************************************/
static int falcon_reset_xmac(struct efx_nic *efx)
{
	efx_oword_t reg;
	int count;

	EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
	falcon_write(efx, &reg, XM_GLB_CFG_REG);

	for (count = 0; count < 10000; count++) {	/* wait upto 100ms */
		falcon_read(efx, &reg, XM_GLB_CFG_REG);
		if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
			return 0;
		udelay(10);
	}

	EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
	return -ETIMEDOUT;
}

/* Configure the XAUI driver that is an output from Falcon */
static void falcon_setup_xaui(struct efx_nic *efx)
{
	efx_oword_t sdctl, txdrv;

	/* Move the XAUI into low power, unless there is no PHY, in
	 * which case the XAUI will have to drive a cable. */
	if (efx->phy_type == PHY_TYPE_NONE)
		return;

	falcon_read(efx, &sdctl, XX_SD_CTL_REG);
	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
	falcon_write(efx, &sdctl, XX_SD_CTL_REG);

	EFX_POPULATE_OWORD_8(txdrv,
			     XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
			     XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
			     XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
			     XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
			     XX_DTXD, XX_TXDRV_DTX_DEFAULT,
			     XX_DTXC, XX_TXDRV_DTX_DEFAULT,
			     XX_DTXB, XX_TXDRV_DTX_DEFAULT,
			     XX_DTXA, XX_TXDRV_DTX_DEFAULT);
	falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
}

int falcon_reset_xaui(struct efx_nic *efx)
{
	efx_oword_t reg;
	int count;

	EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
	falcon_write(efx, &reg, XX_PWR_RST_REG);

	/* Give some time for the link to establish */
	for (count = 0; count < 1000; count++) { /* wait upto 10ms */
		falcon_read(efx, &reg, XX_PWR_RST_REG);
		if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
			falcon_setup_xaui(efx);
			return 0;
		}
		udelay(10);
	}
	EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
	return -ETIMEDOUT;
}

static bool falcon_xgmii_status(struct efx_nic *efx)
{
	efx_oword_t reg;

	if (falcon_rev(efx) < FALCON_REV_B0)
		return true;

	/* The ISR latches, so clear it and re-read */
	falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
	falcon_read(efx, &reg, XM_MGT_INT_REG_B0);

	if (EFX_OWORD_FIELD(reg, XM_LCLFLT) ||
	    EFX_OWORD_FIELD(reg, XM_RMTFLT)) {
		EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
		return false;
	}

	return true;
}

static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
{
	efx_oword_t reg;

	if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
		return;

	/* Flush the ISR */
	if (enable)
		falcon_read(efx, &reg, XM_MGT_INT_REG_B0);

	EFX_POPULATE_OWORD_2(reg,
			     XM_MSK_RMTFLT, !enable,
			     XM_MSK_LCLFLT, !enable);
	falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);
}

int falcon_init_xmac(struct efx_nic *efx)
{
	int rc;

	/* Initialize the PHY first so the clock is around */
	rc = efx->phy_op->init(efx);
	if (rc)
		goto fail1;

	rc = falcon_reset_xaui(efx);
	if (rc)
		goto fail2;

	/* Wait again. Give the PHY and MAC time to come back */
	schedule_timeout_uninterruptible(HZ / 10);

	rc = falcon_reset_xmac(efx);
	if (rc)
		goto fail2;

	falcon_mask_status_intr(efx, true);
	return 0;

 fail2:
	efx->phy_op->fini(efx);
 fail1:
	return rc;
}

bool falcon_xaui_link_ok(struct efx_nic *efx)
{
	efx_oword_t reg;
	bool align_done, link_ok = false;
	int sync_status;

	if (LOOPBACK_INTERNAL(efx))
		return true;

	/* Read link status */
	falcon_read(efx, &reg, XX_CORE_STAT_REG);

	align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
	sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
	if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
		link_ok = true;

	/* Clear link status ready for next read */
	EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
	EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
	EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
	falcon_write(efx, &reg, XX_CORE_STAT_REG);

	/* If the link is up, then check the phy side of the xaui link
	 * (error conditions from the wire side propoagate back through
	 * the phy to the xaui side). */
	if (efx->link_up && link_ok) {
		if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
			link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
	}

	/* If the PHY and XAUI links are up, then check the mac's xgmii
	 * fault state */
	if (efx->link_up && link_ok)
		link_ok = falcon_xgmii_status(efx);

	return link_ok;
}

static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
{
	unsigned int max_frame_len;
	efx_oword_t reg;
	bool rx_fc = !!(efx->flow_control & EFX_FC_RX);

	/* Configure MAC  - cut-thru mode is hard wired on */
	EFX_POPULATE_DWORD_3(reg,
			     XM_RX_JUMBO_MODE, 1,
			     XM_TX_STAT_EN, 1,
			     XM_RX_STAT_EN, 1);
	falcon_write(efx, &reg, XM_GLB_CFG_REG);

	/* Configure TX */
	EFX_POPULATE_DWORD_6(reg,
			     XM_TXEN, 1,
			     XM_TX_PRMBL, 1,
			     XM_AUTO_PAD, 1,
			     XM_TXCRC, 1,
			     XM_FCNTL, 1,
			     XM_IPG, 0x3);
	falcon_write(efx, &reg, XM_TX_CFG_REG);

	/* Configure RX */
	EFX_POPULATE_DWORD_5(reg,
			     XM_RXEN, 1,
			     XM_AUTO_DEPAD, 0,
			     XM_ACPT_ALL_MCAST, 1,
			     XM_ACPT_ALL_UCAST, efx->promiscuous,
			     XM_PASS_CRC_ERR, 1);
	falcon_write(efx, &reg, XM_RX_CFG_REG);

	/* Set frame length */
	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
	EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
	falcon_write(efx, &reg, XM_RX_PARAM_REG);
	EFX_POPULATE_DWORD_2(reg,
			     XM_MAX_TX_FRM_SIZE, max_frame_len,
			     XM_TX_JUMBO_MODE, 1);
	falcon_write(efx, &reg, XM_TX_PARAM_REG);

	EFX_POPULATE_DWORD_2(reg,
			     XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
			     XM_DIS_FCNTL, !rx_fc);
	falcon_write(efx, &reg, XM_FC_REG);

	/* Set MAC address */
	EFX_POPULATE_DWORD_4(reg,
			     XM_ADR_0, efx->net_dev->dev_addr[0],
			     XM_ADR_1, efx->net_dev->dev_addr[1],
			     XM_ADR_2, efx->net_dev->dev_addr[2],
			     XM_ADR_3, efx->net_dev->dev_addr[3]);
	falcon_write(efx, &reg, XM_ADR_LO_REG);
	EFX_POPULATE_DWORD_2(reg,
			     XM_ADR_4, efx->net_dev->dev_addr[4],
			     XM_ADR_5, efx->net_dev->dev_addr[5]);
	falcon_write(efx, &reg, XM_ADR_HI_REG);
}

static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
{
	efx_oword_t reg;
	bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
	bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
	bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);

	/* XGXS block is flaky and will need to be reset if moving
	 * into our out of XGMII, XGXS or XAUI loopbacks. */
	if (EFX_WORKAROUND_5147(efx)) {
		bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
		bool reset_xgxs;

		falcon_read(efx, &reg, XX_CORE_STAT_REG);
		old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
		old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);

		falcon_read(efx, &reg, XX_SD_CTL_REG);
		old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);

		/* The PHY driver may have turned XAUI off */
		reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
			      (xaui_loopback != old_xaui_loopback) ||
			      (xgmii_loopback != old_xgmii_loopback));

		if (reset_xgxs)
			falcon_reset_xaui(efx);
	}

	falcon_read(efx, &reg, XX_CORE_STAT_REG);
	EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
			    (xgxs_loopback || xaui_loopback) ?
			    XX_FORCE_SIG_DECODE_FORCED : 0);
	EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
	EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
	falcon_write(efx, &reg, XX_CORE_STAT_REG);

	falcon_read(efx, &reg, XX_SD_CTL_REG);
	EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
	EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
	EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
	EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
	falcon_write(efx, &reg, XX_SD_CTL_REG);
}


/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
 * to come back up. Bash it until it comes back up */
static bool falcon_check_xaui_link_up(struct efx_nic *efx)
{
	int max_tries, tries;
	tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
	max_tries = tries;

	if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
	    (efx->phy_type == PHY_TYPE_NONE) ||
	    efx_phy_mode_disabled(efx->phy_mode))
		return false;

	while (tries) {
		if (falcon_xaui_link_ok(efx))
			return true;

		EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
			__func__, tries);
		falcon_reset_xaui(efx);
		udelay(200);
		tries--;
	}

	EFX_LOG(efx, "Failed to bring XAUI link back up in %d tries!\n",
		max_tries);
	return false;
}

void falcon_reconfigure_xmac(struct efx_nic *efx)
{
	bool xaui_link_ok;

	falcon_mask_status_intr(efx, false);

	falcon_deconfigure_mac_wrapper(efx);

	/* Reconfigure the PHY, disabling transmit in mac level loopback. */
	if (LOOPBACK_INTERNAL(efx))
		efx->phy_mode |= PHY_MODE_TX_DISABLED;
	else
		efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
	efx->phy_op->reconfigure(efx);

	falcon_reconfigure_xgxs_core(efx);
	falcon_reconfigure_xmac_core(efx);

	falcon_reconfigure_mac_wrapper(efx);

	/* Ensure XAUI link is up */
	xaui_link_ok = falcon_check_xaui_link_up(efx);

	if (xaui_link_ok && efx->link_up)
		falcon_mask_status_intr(efx, true);
}

void falcon_fini_xmac(struct efx_nic *efx)
{
	/* Isolate the MAC - PHY */
	falcon_deconfigure_mac_wrapper(efx);

	/* Potentially power down the PHY */
	efx->phy_op->fini(efx);
}

void falcon_update_stats_xmac(struct efx_nic *efx)
{
	struct efx_mac_stats *mac_stats = &efx->mac_stats;
	int rc;

	rc = falcon_dma_stats(efx, XgDmaDone_offset);
	if (rc)
		return;

	/* Update MAC stats from DMAed values */
	FALCON_STAT(efx, XgRxOctets, rx_bytes);
	FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
	FALCON_STAT(efx, XgRxPkts, rx_packets);
	FALCON_STAT(efx, XgRxPktsOK, rx_good);
	FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
	FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
	FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
	FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
	FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
	FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
	FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
	FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
	FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
	FALCON_STAT(efx, XgRxAlignError, rx_align_error);
	FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
	FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
	FALCON_STAT(efx, XgRxControlPkts, rx_control);
	FALCON_STAT(efx, XgRxPausePkts, rx_pause);
	FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
	FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
	FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
	FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
	FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
	FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
	FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
	FALCON_STAT(efx, XgRxLengthError, rx_length_error);
	FALCON_STAT(efx, XgTxPkts, tx_packets);
	FALCON_STAT(efx, XgTxOctets, tx_bytes);
	FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
	FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
	FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
	FALCON_STAT(efx, XgTxControlPkts, tx_control);
	FALCON_STAT(efx, XgTxPausePkts, tx_pause);
	FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
	FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
	FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
	FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
	FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
	FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
	FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
	FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
	FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
	FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
	FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
	FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);

	/* Update derived statistics */
	mac_stats->tx_good_bytes =
		(mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
		 mac_stats->tx_control * 64);
	mac_stats->rx_bad_bytes =
		(mac_stats->rx_bytes - mac_stats->rx_good_bytes -
		 mac_stats->rx_control * 64);
}

int falcon_check_xmac(struct efx_nic *efx)
{
	bool xaui_link_ok;
	int rc;

	if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
	    efx_phy_mode_disabled(efx->phy_mode))
		return 0;

	falcon_mask_status_intr(efx, false);
	xaui_link_ok = falcon_xaui_link_ok(efx);

	if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
		falcon_reset_xaui(efx);

	/* Call the PHY check_hw routine */
	rc = efx->phy_op->check_hw(efx);

	/* Unmask interrupt if everything was (and still is) ok */
	if (xaui_link_ok && efx->link_up)
		falcon_mask_status_intr(efx, true);

	return rc;
}

/* Simulate a PHY event */
void falcon_xmac_sim_phy_event(struct efx_nic *efx)
{
	efx_qword_t phy_event;

	EFX_POPULATE_QWORD_2(phy_event,
			     EV_CODE, GLOBAL_EV_DECODE,
			     XG_PHY_INTR, 1);
	falcon_generate_event(&efx->channel[0], &phy_event);
}

int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	mdio_clause45_get_settings(efx, ecmd);
	ecmd->transceiver = XCVR_INTERNAL;
	ecmd->phy_address = efx->mii.phy_id;
	ecmd->autoneg = AUTONEG_DISABLE;
	ecmd->duplex = DUPLEX_FULL;
	return 0;
}

int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	if (ecmd->transceiver != XCVR_INTERNAL)
		return -EINVAL;
	if (ecmd->autoneg != AUTONEG_DISABLE)
		return -EINVAL;
	if (ecmd->duplex != DUPLEX_FULL)
		return -EINVAL;

	return mdio_clause45_set_settings(efx, ecmd);
}


int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
{
	bool reset;

	if (flow_control & EFX_FC_AUTO) {
		EFX_LOG(efx, "10G does not support flow control "
			"autonegotiation\n");
		return -EINVAL;
	}

	if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
		return -EINVAL;

	/* TX flow control may automatically turn itself off if the
	 * link partner (intermittently) stops responding to pause
	 * frames. There isn't any indication that this has happened,
	 * so the best we do is leave it up to the user to spot this
	 * and fix it be cycling transmit flow control on this end. */
	reset = ((flow_control & EFX_FC_TX) &&
		 !(efx->flow_control & EFX_FC_TX));
	if (EFX_WORKAROUND_11482(efx) && reset) {
		if (falcon_rev(efx) >= FALCON_REV_B0) {
			/* Recover by resetting the EM block */
			if (efx->link_up)
				falcon_drain_tx_fifo(efx);
		} else {
			/* Schedule a reset to recover */
			efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
		}
	}

	efx->flow_control = flow_control;

	return 0;
}
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
	4	* Copyright 2006-2008 Solarflare Communications Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#include <linux/delay.h>
	12	#include "net_driver.h"
	13	#include "efx.h"
	14	#include "falcon.h"
	15	#include "falcon_hwdefs.h"
	16	#include "falcon_io.h"
	17	#include "mac.h"
8ceee660 BH	18	#include "mdio_10g.h"
	19	#include "phy.h"
	20	#include "boards.h"
	21	#include "workarounds.h"
	22
8ceee660 BH	23	/**************************************************************************
	24	*
	25	* MAC operations
	26	*
	27	*************************************************************************/
	28	static int falcon_reset_xmac(struct efx_nic *efx)
	29	{
c1e5fcc9	30	efx_oword_t reg;
8ceee660 BH	31	int count;
8ceee660 BH	32
c1e5fcc9 BH	33	EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
c1e5fcc9 BH	34	falcon_write(efx, &reg, XM_GLB_CFG_REG);
8ceee660 BH	35
8ceee660 BH	36	for (count = 0; count < 10000; count++) { /* wait upto 100ms */
c1e5fcc9 BH	37	falcon_read(efx, &reg, XM_GLB_CFG_REG);
c1e5fcc9 BH	38	if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
8ceee660 BH	39	return 0;
	40	udelay(10);
	41	}
	42
	43	EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
	44	return -ETIMEDOUT;
	45	}
	46
	47	/* Configure the XAUI driver that is an output from Falcon */
	48	static void falcon_setup_xaui(struct efx_nic *efx)
	49	{
c1e5fcc9	50	efx_oword_t sdctl, txdrv;
8ceee660 BH	51
	52	/* Move the XAUI into low power, unless there is no PHY, in
	53	* which case the XAUI will have to drive a cable. */
	54	if (efx->phy_type == PHY_TYPE_NONE)
	55	return;
	56
c1e5fcc9 BH	57	falcon_read(efx, &sdctl, XX_SD_CTL_REG);
	58	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
	59	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
	60	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
	61	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
	62	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
	63	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
	64	EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
	65	EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
	66	falcon_write(efx, &sdctl, XX_SD_CTL_REG);
	67
	68	EFX_POPULATE_OWORD_8(txdrv,
8ceee660 BH	69	XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
	70	XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
	71	XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
	72	XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
	73	XX_DTXD, XX_TXDRV_DTX_DEFAULT,
	74	XX_DTXC, XX_TXDRV_DTX_DEFAULT,
	75	XX_DTXB, XX_TXDRV_DTX_DEFAULT,
	76	XX_DTXA, XX_TXDRV_DTX_DEFAULT);
c1e5fcc9	77	falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
8ceee660 BH	78	}
8ceee660 BH	79
ef08af03	80	int falcon_reset_xaui(struct efx_nic *efx)
8ceee660	81	{
c1e5fcc9	82	efx_oword_t reg;
8ceee660 BH	83	int count;
	84
	85	EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
c1e5fcc9	86	falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660 BH	87
	88	/* Give some time for the link to establish */
	89	for (count = 0; count < 1000; count++) { /* wait upto 10ms */
c1e5fcc9 BH	90	falcon_read(efx, &reg, XX_PWR_RST_REG);
c1e5fcc9 BH	91	if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
8ceee660 BH	92	falcon_setup_xaui(efx);
	93	return 0;
	94	}
	95	udelay(10);
	96	}
	97	EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
	98	return -ETIMEDOUT;
	99	}
	100
dc8cfa55	101	static bool falcon_xgmii_status(struct efx_nic *efx)
8ceee660	102	{
c1e5fcc9	103	efx_oword_t reg;
8ceee660	104
55668611	105	if (falcon_rev(efx) < FALCON_REV_B0)
dc8cfa55	106	return true;
8ceee660 BH	107
8ceee660 BH	108	/* The ISR latches, so clear it and re-read */
c1e5fcc9 BH	109	falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
c1e5fcc9 BH	110	falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
e52eddae	111
c1e5fcc9 BH	112	if (EFX_OWORD_FIELD(reg, XM_LCLFLT) \|\|
c1e5fcc9 BH	113	EFX_OWORD_FIELD(reg, XM_RMTFLT)) {
8ceee660	114	EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
dc8cfa55	115	return false;
8ceee660 BH	116	}
8ceee660 BH	117
dc8cfa55	118	return true;
8ceee660 BH	119	}
8ceee660 BH	120
dc8cfa55	121	static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
8ceee660	122	{
c1e5fcc9	123	efx_oword_t reg;
8ceee660	124
55668611	125	if ((falcon_rev(efx) < FALCON_REV_B0) \|\| LOOPBACK_INTERNAL(efx))
8ceee660 BH	126	return;
	127
	128	/* Flush the ISR */
	129	if (enable)
c1e5fcc9	130	falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
8ceee660	131
c1e5fcc9	132	EFX_POPULATE_OWORD_2(reg,
8ceee660 BH	133	XM_MSK_RMTFLT, !enable,
8ceee660 BH	134	XM_MSK_LCLFLT, !enable);
c1e5fcc9	135	falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);
8ceee660 BH	136	}
	137
	138	int falcon_init_xmac(struct efx_nic *efx)
	139	{
	140	int rc;
	141
	142	/* Initialize the PHY first so the clock is around */
	143	rc = efx->phy_op->init(efx);
	144	if (rc)
	145	goto fail1;
	146
	147	rc = falcon_reset_xaui(efx);
	148	if (rc)
	149	goto fail2;
	150
	151	/* Wait again. Give the PHY and MAC time to come back */
	152	schedule_timeout_uninterruptible(HZ / 10);
	153
	154	rc = falcon_reset_xmac(efx);
	155	if (rc)
	156	goto fail2;
	157
dc8cfa55	158	falcon_mask_status_intr(efx, true);
8ceee660 BH	159	return 0;
	160
	161	fail2:
	162	efx->phy_op->fini(efx);
	163	fail1:
	164	return rc;
	165	}
	166
dc8cfa55	167	bool falcon_xaui_link_ok(struct efx_nic *efx)
8ceee660	168	{
c1e5fcc9	169	efx_oword_t reg;
dc8cfa55 BH	170	bool align_done, link_ok = false;
dc8cfa55 BH	171	int sync_status;
8ceee660	172
3273c2e8	173	if (LOOPBACK_INTERNAL(efx))
dc8cfa55	174	return true;
3273c2e8	175
8ceee660	176	/* Read link status */
c1e5fcc9	177	falcon_read(efx, &reg, XX_CORE_STAT_REG);
8ceee660	178
c1e5fcc9 BH	179	align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
c1e5fcc9 BH	180	sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
8ceee660	181	if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
dc8cfa55	182	link_ok = true;
8ceee660 BH	183
8ceee660 BH	184	/* Clear link status ready for next read */
c1e5fcc9 BH	185	EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
	186	EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
	187	EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
	188	falcon_write(efx, &reg, XX_CORE_STAT_REG);
8ceee660 BH	189
	190	/* If the link is up, then check the phy side of the xaui link
	191	* (error conditions from the wire side propoagate back through
	192	* the phy to the xaui side). */
	193	if (efx->link_up && link_ok) {
dc8cfa55	194	if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
8ceee660 BH	195	link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
	196	}
	197
	198	/* If the PHY and XAUI links are up, then check the mac's xgmii
	199	* fault state */
	200	if (efx->link_up && link_ok)
	201	link_ok = falcon_xgmii_status(efx);
	202
	203	return link_ok;
	204	}
	205
	206	static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
	207	{
	208	unsigned int max_frame_len;
c1e5fcc9	209	efx_oword_t reg;
dc8cfa55	210	bool rx_fc = !!(efx->flow_control & EFX_FC_RX);
8ceee660 BH	211
	212	/* Configure MAC - cut-thru mode is hard wired on */
	213	EFX_POPULATE_DWORD_3(reg,
	214	XM_RX_JUMBO_MODE, 1,
	215	XM_TX_STAT_EN, 1,
	216	XM_RX_STAT_EN, 1);
c1e5fcc9	217	falcon_write(efx, &reg, XM_GLB_CFG_REG);
8ceee660 BH	218
	219	/* Configure TX */
	220	EFX_POPULATE_DWORD_6(reg,
	221	XM_TXEN, 1,
	222	XM_TX_PRMBL, 1,
	223	XM_AUTO_PAD, 1,
	224	XM_TXCRC, 1,
	225	XM_FCNTL, 1,
	226	XM_IPG, 0x3);
c1e5fcc9	227	falcon_write(efx, &reg, XM_TX_CFG_REG);
8ceee660 BH	228
	229	/* Configure RX */
	230	EFX_POPULATE_DWORD_5(reg,
	231	XM_RXEN, 1,
	232	XM_AUTO_DEPAD, 0,
	233	XM_ACPT_ALL_MCAST, 1,
	234	XM_ACPT_ALL_UCAST, efx->promiscuous,
	235	XM_PASS_CRC_ERR, 1);
c1e5fcc9	236	falcon_write(efx, &reg, XM_RX_CFG_REG);
8ceee660 BH	237
	238	/* Set frame length */
	239	max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
	240	EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
c1e5fcc9	241	falcon_write(efx, &reg, XM_RX_PARAM_REG);
8ceee660 BH	242	EFX_POPULATE_DWORD_2(reg,
	243	XM_MAX_TX_FRM_SIZE, max_frame_len,
	244	XM_TX_JUMBO_MODE, 1);
c1e5fcc9	245	falcon_write(efx, &reg, XM_TX_PARAM_REG);
8ceee660 BH	246
	247	EFX_POPULATE_DWORD_2(reg,
	248	XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
dc8cfa55	249	XM_DIS_FCNTL, !rx_fc);
c1e5fcc9	250	falcon_write(efx, &reg, XM_FC_REG);
8ceee660 BH	251
	252	/* Set MAC address */
	253	EFX_POPULATE_DWORD_4(reg,
	254	XM_ADR_0, efx->net_dev->dev_addr[0],
	255	XM_ADR_1, efx->net_dev->dev_addr[1],
	256	XM_ADR_2, efx->net_dev->dev_addr[2],
	257	XM_ADR_3, efx->net_dev->dev_addr[3]);
c1e5fcc9	258	falcon_write(efx, &reg, XM_ADR_LO_REG);
8ceee660 BH	259	EFX_POPULATE_DWORD_2(reg,
	260	XM_ADR_4, efx->net_dev->dev_addr[4],
	261	XM_ADR_5, efx->net_dev->dev_addr[5]);
c1e5fcc9	262	falcon_write(efx, &reg, XM_ADR_HI_REG);
8ceee660 BH	263	}
8ceee660 BH	264
3273c2e8 BH	265	static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
3273c2e8 BH	266	{
c1e5fcc9	267	efx_oword_t reg;
dc8cfa55 BH	268	bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
	269	bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
	270	bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
3273c2e8 BH	271
	272	/* XGXS block is flaky and will need to be reset if moving
	273	* into our out of XGMII, XGXS or XAUI loopbacks. */
	274	if (EFX_WORKAROUND_5147(efx)) {
dc8cfa55 BH	275	bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
dc8cfa55 BH	276	bool reset_xgxs;
3273c2e8	277
c1e5fcc9 BH	278	falcon_read(efx, &reg, XX_CORE_STAT_REG);
	279	old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
	280	old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);
3273c2e8	281
c1e5fcc9 BH	282	falcon_read(efx, &reg, XX_SD_CTL_REG);
c1e5fcc9 BH	283	old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);
3273c2e8 BH	284
	285	/* The PHY driver may have turned XAUI off */
	286	reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) \|\|
	287	(xaui_loopback != old_xaui_loopback) \|\|
	288	(xgmii_loopback != old_xgmii_loopback));
8c8661e4 BH	289
	290	if (reset_xgxs)
	291	falcon_reset_xaui(efx);
3273c2e8 BH	292	}
3273c2e8 BH	293
c1e5fcc9 BH	294	falcon_read(efx, &reg, XX_CORE_STAT_REG);
c1e5fcc9 BH	295	EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
3273c2e8 BH	296	(xgxs_loopback \|\| xaui_loopback) ?
3273c2e8 BH	297	XX_FORCE_SIG_DECODE_FORCED : 0);
c1e5fcc9 BH	298	EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
	299	EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
	300	falcon_write(efx, &reg, XX_CORE_STAT_REG);
	301
	302	falcon_read(efx, &reg, XX_SD_CTL_REG);
	303	EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
	304	EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
	305	EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
	306	EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
	307	falcon_write(efx, &reg, XX_SD_CTL_REG);
3273c2e8 BH	308	}
	309
	310
8ceee660 BH	311	/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
8ceee660 BH	312	* to come back up. Bash it until it comes back up */
dc8cfa55	313	static bool falcon_check_xaui_link_up(struct efx_nic *efx)
8ceee660 BH	314	{
	315	int max_tries, tries;
	316	tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
	317	max_tries = tries;
	318
3273c2e8	319	if ((efx->loopback_mode == LOOPBACK_NETWORK) \|\|
f8b87c17 BH	320	(efx->phy_type == PHY_TYPE_NONE) \|\|
f8b87c17 BH	321	efx_phy_mode_disabled(efx->phy_mode))
dc8cfa55	322	return false;
8ceee660 BH	323
	324	while (tries) {
	325	if (falcon_xaui_link_ok(efx))
dc8cfa55	326	return true;
8ceee660 BH	327
	328	EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
	329	__func__, tries);
91ad757c	330	falcon_reset_xaui(efx);
8ceee660 BH	331	udelay(200);
	332	tries--;
	333	}
	334
b055629e	335	EFX_LOG(efx, "Failed to bring XAUI link back up in %d tries!\n",
8ceee660	336	max_tries);
dc8cfa55	337	return false;
8ceee660 BH	338	}
	339
	340	void falcon_reconfigure_xmac(struct efx_nic *efx)
	341	{
dc8cfa55	342	bool xaui_link_ok;
8ceee660	343
dc8cfa55	344	falcon_mask_status_intr(efx, false);
8ceee660 BH	345
8ceee660 BH	346	falcon_deconfigure_mac_wrapper(efx);
3273c2e8	347
f8b87c17 BH	348	/* Reconfigure the PHY, disabling transmit in mac level loopback. */
	349	if (LOOPBACK_INTERNAL(efx))
	350	efx->phy_mode \|= PHY_MODE_TX_DISABLED;
	351	else
	352	efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
8ceee660	353	efx->phy_op->reconfigure(efx);
3273c2e8 BH	354
3273c2e8 BH	355	falcon_reconfigure_xgxs_core(efx);
8ceee660	356	falcon_reconfigure_xmac_core(efx);
3273c2e8	357
8ceee660 BH	358	falcon_reconfigure_mac_wrapper(efx);
	359
	360	/* Ensure XAUI link is up */
	361	xaui_link_ok = falcon_check_xaui_link_up(efx);
	362
	363	if (xaui_link_ok && efx->link_up)
dc8cfa55	364	falcon_mask_status_intr(efx, true);
8ceee660 BH	365	}
	366
	367	void falcon_fini_xmac(struct efx_nic *efx)
	368	{
	369	/* Isolate the MAC - PHY */
	370	falcon_deconfigure_mac_wrapper(efx);
	371
	372	/* Potentially power down the PHY */
	373	efx->phy_op->fini(efx);
	374	}
	375
	376	void falcon_update_stats_xmac(struct efx_nic *efx)
	377	{
	378	struct efx_mac_stats *mac_stats = &efx->mac_stats;
	379	int rc;
	380
	381	rc = falcon_dma_stats(efx, XgDmaDone_offset);
	382	if (rc)
	383	return;
	384
	385	/* Update MAC stats from DMAed values */
	386	FALCON_STAT(efx, XgRxOctets, rx_bytes);
	387	FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
	388	FALCON_STAT(efx, XgRxPkts, rx_packets);
	389	FALCON_STAT(efx, XgRxPktsOK, rx_good);
	390	FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
	391	FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
	392	FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
	393	FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
	394	FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
	395	FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
	396	FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
	397	FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
	398	FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
	399	FALCON_STAT(efx, XgRxAlignError, rx_align_error);
	400	FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
	401	FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
	402	FALCON_STAT(efx, XgRxControlPkts, rx_control);
	403	FALCON_STAT(efx, XgRxPausePkts, rx_pause);
	404	FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
	405	FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
	406	FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
	407	FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
	408	FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
	409	FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
	410	FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
	411	FALCON_STAT(efx, XgRxLengthError, rx_length_error);
	412	FALCON_STAT(efx, XgTxPkts, tx_packets);
	413	FALCON_STAT(efx, XgTxOctets, tx_bytes);
	414	FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
	415	FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
	416	FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
	417	FALCON_STAT(efx, XgTxControlPkts, tx_control);
	418	FALCON_STAT(efx, XgTxPausePkts, tx_pause);
	419	FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
	420	FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
	421	FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
	422	FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
	423	FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
	424	FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
	425	FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
	426	FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
	427	FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
	428	FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
429	FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
430	FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
431
432	/* Update derived statistics */
433	mac_stats->tx_good_bytes =
c264361d BH	434	(mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
c264361d BH	435	mac_stats->tx_control * 64);
8ceee660	436	mac_stats->rx_bad_bytes =
c264361d BH	437	(mac_stats->rx_bytes - mac_stats->rx_good_bytes -
c264361d BH	438	mac_stats->rx_control * 64);
8ceee660 BH	439	}
8ceee660 BH	440
8ceee660 BH	441	int falcon_check_xmac(struct efx_nic *efx)
8ceee660 BH	442	{
dc8cfa55	443	bool xaui_link_ok;
8ceee660 BH	444	int rc;
8ceee660 BH	445
3273c2e8	446	if ((efx->loopback_mode == LOOPBACK_NETWORK) \|\|
f8b87c17	447	efx_phy_mode_disabled(efx->phy_mode))
3273c2e8 BH	448	return 0;
3273c2e8 BH	449
dc8cfa55	450	falcon_mask_status_intr(efx, false);
8ceee660 BH	451	xaui_link_ok = falcon_xaui_link_ok(efx);
	452
	453	if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
91ad757c	454	falcon_reset_xaui(efx);
8ceee660 BH	455
	456	/* Call the PHY check_hw routine */
	457	rc = efx->phy_op->check_hw(efx);
	458
	459	/* Unmask interrupt if everything was (and still is) ok */
	460	if (xaui_link_ok && efx->link_up)
dc8cfa55	461	falcon_mask_status_intr(efx, true);
8ceee660 BH	462
	463	return rc;
	464	}
	465
	466	/* Simulate a PHY event */
	467	void falcon_xmac_sim_phy_event(struct efx_nic *efx)
	468	{
	469	efx_qword_t phy_event;
	470
	471	EFX_POPULATE_QWORD_2(phy_event,
	472	EV_CODE, GLOBAL_EV_DECODE,
	473	XG_PHY_INTR, 1);
	474	falcon_generate_event(&efx->channel[0], &phy_event);
	475	}
	476
	477	int falcon_xmac_get_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
	478	{
	479	mdio_clause45_get_settings(efx, ecmd);
	480	ecmd->transceiver = XCVR_INTERNAL;
	481	ecmd->phy_address = efx->mii.phy_id;
	482	ecmd->autoneg = AUTONEG_DISABLE;
	483	ecmd->duplex = DUPLEX_FULL;
	484	return 0;
	485	}
	486
	487	int falcon_xmac_set_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
	488	{
	489	if (ecmd->transceiver != XCVR_INTERNAL)
	490	return -EINVAL;
	491	if (ecmd->autoneg != AUTONEG_DISABLE)
	492	return -EINVAL;
	493	if (ecmd->duplex != DUPLEX_FULL)
	494	return -EINVAL;
	495
	496	return mdio_clause45_set_settings(efx, ecmd);
	497	}
	498
	499
	500	int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
	501	{
dc8cfa55	502	bool reset;
8ceee660 BH	503
	504	if (flow_control & EFX_FC_AUTO) {
	505	EFX_LOG(efx, "10G does not support flow control "
	506	"autonegotiation\n");
	507	return -EINVAL;
	508	}
	509
	510	if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
	511	return -EINVAL;
	512
	513	/* TX flow control may automatically turn itself off if the
	514	* link partner (intermittently) stops responding to pause
	515	* frames. There isn't any indication that this has happened,
	516	* so the best we do is leave it up to the user to spot this
	517	* and fix it be cycling transmit flow control on this end. */
	518	reset = ((flow_control & EFX_FC_TX) &&
	519	!(efx->flow_control & EFX_FC_TX));
	520	if (EFX_WORKAROUND_11482(efx) && reset) {
55668611	521	if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660 BH	522	/* Recover by resetting the EM block */
	523	if (efx->link_up)
	524	falcon_drain_tx_fifo(efx);
	525	} else {
	526	/* Schedule a reset to recover */
	527	efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
	528	}
	529	}
	530
	531	efx->flow_control = flow_control;
	532
	533	return 0;
	534	}