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sfc: Rework the bitfield header so that we can identify fields by bit number
[deliverable/linux.git] / drivers / net / sfc / falcon_xmac.c
CommitLineData
8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/delay.h>
12#include "net_driver.h"
13#include "efx.h"
14#include "falcon.h"
15#include "falcon_hwdefs.h"
16#include "falcon_io.h"
17#include "mac.h"
18#include "gmii.h"
19#include "mdio_10g.h"
20#include "phy.h"
21#include "boards.h"
22#include "workarounds.h"
23
8ceee660
BH		 24/**************************************************************************
25 *
26 * MAC operations
27 *
28 *************************************************************************/
29static int falcon_reset_xmac(struct efx_nic *efx)
30{
c1e5fcc9 31 efx_oword_t reg;
8ceee660
BH		 32 int count;
33
c1e5fcc9
BH		 34 EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1);
35 falcon_write(efx, &reg, XM_GLB_CFG_REG);
8ceee660
BH		 36
37 for (count = 0; count < 10000; count++) { /* wait upto 100ms */
c1e5fcc9
BH		 38 falcon_read(efx, &reg, XM_GLB_CFG_REG);
39 if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0)
8ceee660
BH		 40 return 0;
41 udelay(10);
42 }
43
44 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
45 return -ETIMEDOUT;
46}
47
48/* Configure the XAUI driver that is an output from Falcon */
49static void falcon_setup_xaui(struct efx_nic *efx)
50{
c1e5fcc9 51 efx_oword_t sdctl, txdrv;
8ceee660
BH		 52
53 /* Move the XAUI into low power, unless there is no PHY, in
54 * which case the XAUI will have to drive a cable. */
55 if (efx->phy_type == PHY_TYPE_NONE)
56 return;
57
c1e5fcc9
BH		 58 falcon_read(efx, &sdctl, XX_SD_CTL_REG);
59 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
60 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
61 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
62 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
63 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
64 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
65 EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
66 EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
67 falcon_write(efx, &sdctl, XX_SD_CTL_REG);
68
69 EFX_POPULATE_OWORD_8(txdrv,
8ceee660
BH		 70 XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
71 XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
72 XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
73 XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
74 XX_DTXD, XX_TXDRV_DTX_DEFAULT,
75 XX_DTXC, XX_TXDRV_DTX_DEFAULT,
76 XX_DTXB, XX_TXDRV_DTX_DEFAULT,
77 XX_DTXA, XX_TXDRV_DTX_DEFAULT);
c1e5fcc9 78 falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
8ceee660
BH		 79}
80
81static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
82{
c1e5fcc9
BH		 83 efx_oword_t reg;
84
85 EFX_ZERO_OWORD(reg);
86 EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 1);
87 EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 1);
88 EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 1);
89 EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 1);
90 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
91 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
92 EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 1);
93 EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 1);
94 EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 1);
95 EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 1);
96 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
97 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
98 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 99 udelay(10);
100}
101
102static int _falcon_reset_xaui_a(struct efx_nic *efx)
103{
c1e5fcc9 104 efx_oword_t reg;
8ceee660
BH		 105
106 falcon_hold_xaui_in_rst(efx);
c1e5fcc9 107 falcon_read(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 108
109 /* Follow the RAMBUS XAUI data reset sequencing
110 * Channels A and B first: power down, reset PLL, reset, clear
111 */
c1e5fcc9
BH		 112 EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 0);
113 EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 0);
114 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 115 udelay(10);
116
c1e5fcc9
BH		 117 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
118 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 119 udelay(10);
120
c1e5fcc9
BH		 121 EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 0);
122 EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 0);
123 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 124 udelay(10);
125
126 /* Channels C and D: power down, reset PLL, reset, clear */
c1e5fcc9
BH		 127 EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 0);
128 EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 0);
129 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 130 udelay(10);
131
c1e5fcc9
BH		 132 EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
133 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 134 udelay(10);
135
c1e5fcc9
BH		 136 EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 0);
137 EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 0);
138 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 139 udelay(10);
140
141 /* Setup XAUI */
142 falcon_setup_xaui(efx);
143 udelay(10);
144
145 /* Take XGXS out of reset */
c1e5fcc9
BH		 146 EFX_ZERO_OWORD(reg);
147 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 148 udelay(10);
149
150 return 0;
151}
152
153static int _falcon_reset_xaui_b(struct efx_nic *efx)
154{
c1e5fcc9 155 efx_oword_t reg;
8ceee660
BH		 156 int count;
157
158 EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
c1e5fcc9 159 falcon_write(efx, &reg, XX_PWR_RST_REG);
8ceee660
BH		 160
161 /* Give some time for the link to establish */
162 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
c1e5fcc9
BH		 163 falcon_read(efx, &reg, XX_PWR_RST_REG);
164 if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
8ceee660
BH		 165 falcon_setup_xaui(efx);
166 return 0;
167 }
168 udelay(10);
169 }
170 EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
171 return -ETIMEDOUT;
172}
173
174int falcon_reset_xaui(struct efx_nic *efx)
175{
176 int rc;
177
178 if (EFX_WORKAROUND_9388(efx)) {
179 falcon_hold_xaui_in_rst(efx);
180 efx->phy_op->reset_xaui(efx);
181 rc = _falcon_reset_xaui_a(efx);
182 } else {
183 rc = _falcon_reset_xaui_b(efx);
184 }
185 return rc;
186}
187
dc8cfa55 188static bool falcon_xgmii_status(struct efx_nic *efx)
8ceee660 189{
c1e5fcc9 190 efx_oword_t reg;
8ceee660 191
55668611 192 if (falcon_rev(efx) < FALCON_REV_B0)
dc8cfa55 193 return true;
8ceee660
BH		 194
195 /* The ISR latches, so clear it and re-read */
c1e5fcc9
BH		 196 falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
197 falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
e52eddae 198
c1e5fcc9
BH		 199 if (EFX_OWORD_FIELD(reg, XM_LCLFLT) ||
200 EFX_OWORD_FIELD(reg, XM_RMTFLT)) {
8ceee660 201 EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
dc8cfa55 202 return false;
8ceee660
BH		 203 }
204
dc8cfa55 205 return true;
8ceee660
BH		 206}
207
dc8cfa55 208static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
8ceee660 209{
c1e5fcc9 210 efx_oword_t reg;
8ceee660 211
55668611 212 if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
8ceee660
BH		 213 return;
214
215 /* Flush the ISR */
216 if (enable)
c1e5fcc9 217 falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
8ceee660 218
c1e5fcc9 219 EFX_POPULATE_OWORD_2(reg,
8ceee660
BH		 220 XM_MSK_RMTFLT, !enable,
221 XM_MSK_LCLFLT, !enable);
c1e5fcc9 222 falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);
8ceee660
BH		 223}
224
225int falcon_init_xmac(struct efx_nic *efx)
226{
227 int rc;
228
229 /* Initialize the PHY first so the clock is around */
230 rc = efx->phy_op->init(efx);
231 if (rc)
232 goto fail1;
233
234 rc = falcon_reset_xaui(efx);
235 if (rc)
236 goto fail2;
237
238 /* Wait again. Give the PHY and MAC time to come back */
239 schedule_timeout_uninterruptible(HZ / 10);
240
241 rc = falcon_reset_xmac(efx);
242 if (rc)
243 goto fail2;
244
dc8cfa55 245 falcon_mask_status_intr(efx, true);
8ceee660
BH		 246 return 0;
247
248 fail2:
249 efx->phy_op->fini(efx);
250 fail1:
251 return rc;
252}
253
dc8cfa55 254bool falcon_xaui_link_ok(struct efx_nic *efx)
8ceee660 255{
c1e5fcc9 256 efx_oword_t reg;
dc8cfa55
BH		 257 bool align_done, link_ok = false;
258 int sync_status;
8ceee660 259
3273c2e8 260 if (LOOPBACK_INTERNAL(efx))
dc8cfa55 261 return true;
3273c2e8 262
8ceee660 263 /* Read link status */
c1e5fcc9 264 falcon_read(efx, &reg, XX_CORE_STAT_REG);
8ceee660 265
c1e5fcc9
BH		 266 align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
267 sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
8ceee660 268 if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
dc8cfa55 269 link_ok = true;
8ceee660
BH		 270
271 /* Clear link status ready for next read */
c1e5fcc9
BH		 272 EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
273 EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
274 EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
275 falcon_write(efx, &reg, XX_CORE_STAT_REG);
8ceee660
BH		 276
277 /* If the link is up, then check the phy side of the xaui link
278 * (error conditions from the wire side propoagate back through
279 * the phy to the xaui side). */
280 if (efx->link_up && link_ok) {
dc8cfa55 281 if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
8ceee660
BH		 282 link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
283 }
284
285 /* If the PHY and XAUI links are up, then check the mac's xgmii
286 * fault state */
287 if (efx->link_up && link_ok)
288 link_ok = falcon_xgmii_status(efx);
289
290 return link_ok;
291}
292
293static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
294{
295 unsigned int max_frame_len;
c1e5fcc9 296 efx_oword_t reg;
dc8cfa55 297 bool rx_fc = !!(efx->flow_control & EFX_FC_RX);
8ceee660
BH		 298
299 /* Configure MAC - cut-thru mode is hard wired on */
300 EFX_POPULATE_DWORD_3(reg,
301 XM_RX_JUMBO_MODE, 1,
302 XM_TX_STAT_EN, 1,
303 XM_RX_STAT_EN, 1);
c1e5fcc9 304 falcon_write(efx, &reg, XM_GLB_CFG_REG);
8ceee660
BH		 305
306 /* Configure TX */
307 EFX_POPULATE_DWORD_6(reg,
308 XM_TXEN, 1,
309 XM_TX_PRMBL, 1,
310 XM_AUTO_PAD, 1,
311 XM_TXCRC, 1,
312 XM_FCNTL, 1,
313 XM_IPG, 0x3);
c1e5fcc9 314 falcon_write(efx, &reg, XM_TX_CFG_REG);
8ceee660
BH		 315
316 /* Configure RX */
317 EFX_POPULATE_DWORD_5(reg,
318 XM_RXEN, 1,
319 XM_AUTO_DEPAD, 0,
320 XM_ACPT_ALL_MCAST, 1,
321 XM_ACPT_ALL_UCAST, efx->promiscuous,
322 XM_PASS_CRC_ERR, 1);
c1e5fcc9 323 falcon_write(efx, &reg, XM_RX_CFG_REG);
8ceee660
BH		 324
325 /* Set frame length */
326 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
327 EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
c1e5fcc9 328 falcon_write(efx, &reg, XM_RX_PARAM_REG);
8ceee660
BH		 329 EFX_POPULATE_DWORD_2(reg,
330 XM_MAX_TX_FRM_SIZE, max_frame_len,
331 XM_TX_JUMBO_MODE, 1);
c1e5fcc9 332 falcon_write(efx, &reg, XM_TX_PARAM_REG);
8ceee660
BH		 333
334 EFX_POPULATE_DWORD_2(reg,
335 XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
dc8cfa55 336 XM_DIS_FCNTL, !rx_fc);
c1e5fcc9 337 falcon_write(efx, &reg, XM_FC_REG);
8ceee660
BH		 338
339 /* Set MAC address */
340 EFX_POPULATE_DWORD_4(reg,
341 XM_ADR_0, efx->net_dev->dev_addr[0],
342 XM_ADR_1, efx->net_dev->dev_addr[1],
343 XM_ADR_2, efx->net_dev->dev_addr[2],
344 XM_ADR_3, efx->net_dev->dev_addr[3]);
c1e5fcc9 345 falcon_write(efx, &reg, XM_ADR_LO_REG);
8ceee660
BH		 346 EFX_POPULATE_DWORD_2(reg,
347 XM_ADR_4, efx->net_dev->dev_addr[4],
348 XM_ADR_5, efx->net_dev->dev_addr[5]);
c1e5fcc9 349 falcon_write(efx, &reg, XM_ADR_HI_REG);
8ceee660
BH		 350}
351
3273c2e8
BH		 352static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
353{
c1e5fcc9 354 efx_oword_t reg;
dc8cfa55
BH		 355 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
356 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
357 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
3273c2e8
BH		 358
359 /* XGXS block is flaky and will need to be reset if moving
360 * into our out of XGMII, XGXS or XAUI loopbacks. */
361 if (EFX_WORKAROUND_5147(efx)) {
dc8cfa55
BH		 362 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
363 bool reset_xgxs;
3273c2e8 364
c1e5fcc9
BH		 365 falcon_read(efx, &reg, XX_CORE_STAT_REG);
366 old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
367 old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);
3273c2e8 368
c1e5fcc9
BH		 369 falcon_read(efx, &reg, XX_SD_CTL_REG);
370 old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);
3273c2e8
BH		 371
372 /* The PHY driver may have turned XAUI off */
373 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
374 (xaui_loopback != old_xaui_loopback) ||
375 (xgmii_loopback != old_xgmii_loopback));
376 if (reset_xgxs) {
c1e5fcc9
BH		 377 falcon_read(efx, &reg, XX_PWR_RST_REG);
378 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
379 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
380 falcon_write(efx, &reg, XX_PWR_RST_REG);
3273c2e8 381 udelay(1);
c1e5fcc9
BH		 382 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 0);
383 EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 0);
384 falcon_write(efx, &reg, XX_PWR_RST_REG);
3273c2e8
BH		 385 udelay(1);
386 }
387 }
388
c1e5fcc9
BH		 389 falcon_read(efx, &reg, XX_CORE_STAT_REG);
390 EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
3273c2e8
BH		 391 (xgxs_loopback || xaui_loopback) ?
392 XX_FORCE_SIG_DECODE_FORCED : 0);
c1e5fcc9
BH		 393 EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
394 EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
395 falcon_write(efx, &reg, XX_CORE_STAT_REG);
396
397 falcon_read(efx, &reg, XX_SD_CTL_REG);
398 EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
399 EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
400 EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
401 EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
402 falcon_write(efx, &reg, XX_SD_CTL_REG);
3273c2e8
BH		 403}
404
405
8ceee660
BH		 406/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
407 * to come back up. Bash it until it comes back up */
dc8cfa55 408static bool falcon_check_xaui_link_up(struct efx_nic *efx)
8ceee660
BH		 409{
410 int max_tries, tries;
411 tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
412 max_tries = tries;
413
3273c2e8 414 if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
f8b87c17
BH		 415 (efx->phy_type == PHY_TYPE_NONE) ||
416 efx_phy_mode_disabled(efx->phy_mode))
dc8cfa55 417 return false;
8ceee660
BH		 418
419 while (tries) {
420 if (falcon_xaui_link_ok(efx))
dc8cfa55 421 return true;
8ceee660
BH		 422
423 EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
424 __func__, tries);
91ad757c 425 falcon_reset_xaui(efx);
8ceee660
BH		 426 udelay(200);
427 tries--;
428 }
429
b055629e 430 EFX_LOG(efx, "Failed to bring XAUI link back up in %d tries!\n",
8ceee660 431 max_tries);
dc8cfa55 432 return false;
8ceee660
BH		 433}
434
435void falcon_reconfigure_xmac(struct efx_nic *efx)
436{
dc8cfa55 437 bool xaui_link_ok;
8ceee660 438
dc8cfa55 439 falcon_mask_status_intr(efx, false);
8ceee660
BH		 440
441 falcon_deconfigure_mac_wrapper(efx);
3273c2e8 442
f8b87c17
BH		 443 /* Reconfigure the PHY, disabling transmit in mac level loopback. */
444 if (LOOPBACK_INTERNAL(efx))
445 efx->phy_mode |= PHY_MODE_TX_DISABLED;
446 else
447 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
8ceee660 448 efx->phy_op->reconfigure(efx);
3273c2e8
BH		 449
450 falcon_reconfigure_xgxs_core(efx);
8ceee660 451 falcon_reconfigure_xmac_core(efx);
3273c2e8 452
8ceee660
BH		 453 falcon_reconfigure_mac_wrapper(efx);
454
455 /* Ensure XAUI link is up */
456 xaui_link_ok = falcon_check_xaui_link_up(efx);
457
458 if (xaui_link_ok && efx->link_up)
dc8cfa55 459 falcon_mask_status_intr(efx, true);
8ceee660
BH		 460}
461
462void falcon_fini_xmac(struct efx_nic *efx)
463{
464 /* Isolate the MAC - PHY */
465 falcon_deconfigure_mac_wrapper(efx);
466
467 /* Potentially power down the PHY */
468 efx->phy_op->fini(efx);
469}
470
471void falcon_update_stats_xmac(struct efx_nic *efx)
472{
473 struct efx_mac_stats *mac_stats = &efx->mac_stats;
474 int rc;
475
476 rc = falcon_dma_stats(efx, XgDmaDone_offset);
477 if (rc)
478 return;
479
480 /* Update MAC stats from DMAed values */
481 FALCON_STAT(efx, XgRxOctets, rx_bytes);
482 FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
483 FALCON_STAT(efx, XgRxPkts, rx_packets);
484 FALCON_STAT(efx, XgRxPktsOK, rx_good);
485 FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
486 FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
487 FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
488 FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
489 FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
490 FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
491 FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
492 FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
493 FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
494 FALCON_STAT(efx, XgRxAlignError, rx_align_error);
495 FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
496 FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
497 FALCON_STAT(efx, XgRxControlPkts, rx_control);
498 FALCON_STAT(efx, XgRxPausePkts, rx_pause);
499 FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
500 FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
501 FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
502 FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
503 FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
504 FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
505 FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
506 FALCON_STAT(efx, XgRxLengthError, rx_length_error);
507 FALCON_STAT(efx, XgTxPkts, tx_packets);
508 FALCON_STAT(efx, XgTxOctets, tx_bytes);
509 FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
510 FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
511 FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
512 FALCON_STAT(efx, XgTxControlPkts, tx_control);
513 FALCON_STAT(efx, XgTxPausePkts, tx_pause);
514 FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
515 FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
516 FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
517 FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
518 FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
519 FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
520 FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
521 FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
522 FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
523 FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
524 FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
525 FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
526
527 /* Update derived statistics */
528 mac_stats->tx_good_bytes =
c264361d
BH		 529 (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
530 mac_stats->tx_control * 64);
8ceee660 531 mac_stats->rx_bad_bytes =
c264361d
BH		 532 (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
533 mac_stats->rx_control * 64);
8ceee660
BH		 534}
535
8ceee660
BH		 536int falcon_check_xmac(struct efx_nic *efx)
537{
dc8cfa55 538 bool xaui_link_ok;
8ceee660
BH		 539 int rc;
540
3273c2e8 541 if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
f8b87c17 542 efx_phy_mode_disabled(efx->phy_mode))
3273c2e8
BH		 543 return 0;
544
dc8cfa55 545 falcon_mask_status_intr(efx, false);
8ceee660
BH		 546 xaui_link_ok = falcon_xaui_link_ok(efx);
547
548 if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
91ad757c 549 falcon_reset_xaui(efx);
8ceee660
BH		 550
551 /* Call the PHY check_hw routine */
552 rc = efx->phy_op->check_hw(efx);
553
554 /* Unmask interrupt if everything was (and still is) ok */
555 if (xaui_link_ok && efx->link_up)
dc8cfa55 556 falcon_mask_status_intr(efx, true);
8ceee660
BH		 557
558 return rc;
559}
560
561/* Simulate a PHY event */
562void falcon_xmac_sim_phy_event(struct efx_nic *efx)
563{
564 efx_qword_t phy_event;
565
566 EFX_POPULATE_QWORD_2(phy_event,
567 EV_CODE, GLOBAL_EV_DECODE,
568 XG_PHY_INTR, 1);
569 falcon_generate_event(&efx->channel[0], &phy_event);
570}
571
572int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
573{
574 mdio_clause45_get_settings(efx, ecmd);
575 ecmd->transceiver = XCVR_INTERNAL;
576 ecmd->phy_address = efx->mii.phy_id;
577 ecmd->autoneg = AUTONEG_DISABLE;
578 ecmd->duplex = DUPLEX_FULL;
579 return 0;
580}
581
582int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
583{
584 if (ecmd->transceiver != XCVR_INTERNAL)
585 return -EINVAL;
586 if (ecmd->autoneg != AUTONEG_DISABLE)
587 return -EINVAL;
588 if (ecmd->duplex != DUPLEX_FULL)
589 return -EINVAL;
590
591 return mdio_clause45_set_settings(efx, ecmd);
592}
593
594
595int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
596{
dc8cfa55 597 bool reset;
8ceee660
BH		 598
599 if (flow_control & EFX_FC_AUTO) {
600 EFX_LOG(efx, "10G does not support flow control "
601 "autonegotiation\n");
602 return -EINVAL;
603 }
604
605 if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
606 return -EINVAL;
607
608 /* TX flow control may automatically turn itself off if the
609 * link partner (intermittently) stops responding to pause
610 * frames. There isn't any indication that this has happened,
611 * so the best we do is leave it up to the user to spot this
612 * and fix it be cycling transmit flow control on this end. */
613 reset = ((flow_control & EFX_FC_TX) &&
614 !(efx->flow_control & EFX_FC_TX));
615 if (EFX_WORKAROUND_11482(efx) && reset) {
55668611 616 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 617 /* Recover by resetting the EM block */
618 if (efx->link_up)
619 falcon_drain_tx_fifo(efx);
620 } else {
621 /* Schedule a reset to recover */
622 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
623 }
624 }
625
626 efx->flow_control = flow_control;
627
628 return 0;
629}
Linux kernel - Deliverables
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