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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
[deliverable/linux.git] / drivers / net / sfc / mcdi.c
CommitLineData
afd4aea0
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2008-2009 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9
10#include <linux/delay.h>
11#include "net_driver.h"
12#include "nic.h"
13#include "io.h"
14#include "regs.h"
15#include "mcdi_pcol.h"
16#include "phy.h"
17
18/**************************************************************************
19 *
20 * Management-Controller-to-Driver Interface
21 *
22 **************************************************************************
23 */
24
25/* Software-defined structure to the shared-memory */
26#define CMD_NOTIFY_PORT0 0
27#define CMD_NOTIFY_PORT1 4
28#define CMD_PDU_PORT0 0x008
29#define CMD_PDU_PORT1 0x108
30#define REBOOT_FLAG_PORT0 0x3f8
31#define REBOOT_FLAG_PORT1 0x3fc
32
33#define MCDI_RPC_TIMEOUT 10 /*seconds */
34
35#define MCDI_PDU(efx) \
36 (efx_port_num(efx) ? CMD_PDU_PORT1 : CMD_PDU_PORT0)
37#define MCDI_DOORBELL(efx) \
38 (efx_port_num(efx) ? CMD_NOTIFY_PORT1 : CMD_NOTIFY_PORT0)
39#define MCDI_REBOOT_FLAG(efx) \
40 (efx_port_num(efx) ? REBOOT_FLAG_PORT1 : REBOOT_FLAG_PORT0)
41
42#define SEQ_MASK \
43 EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
44
45static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
46{
47 struct siena_nic_data *nic_data;
48 EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
49 nic_data = efx->nic_data;
50 return &nic_data->mcdi;
51}
52
53void efx_mcdi_init(struct efx_nic *efx)
54{
55 struct efx_mcdi_iface *mcdi;
56
57 if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
58 return;
59
60 mcdi = efx_mcdi(efx);
61 init_waitqueue_head(&mcdi->wq);
62 spin_lock_init(&mcdi->iface_lock);
63 atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
64 mcdi->mode = MCDI_MODE_POLL;
65
66 (void) efx_mcdi_poll_reboot(efx);
67}
68
69static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
70 const u8 *inbuf, size_t inlen)
71{
72 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
73 unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
74 unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
75 unsigned int i;
76 efx_dword_t hdr;
77 u32 xflags, seqno;
78
79 BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
80 BUG_ON(inlen & 3 || inlen >= 0x100);
81
82 seqno = mcdi->seqno & SEQ_MASK;
83 xflags = 0;
84 if (mcdi->mode == MCDI_MODE_EVENTS)
85 xflags |= MCDI_HEADER_XFLAGS_EVREQ;
86
87 EFX_POPULATE_DWORD_6(hdr,
88 MCDI_HEADER_RESPONSE, 0,
89 MCDI_HEADER_RESYNC, 1,
90 MCDI_HEADER_CODE, cmd,
91 MCDI_HEADER_DATALEN, inlen,
92 MCDI_HEADER_SEQ, seqno,
93 MCDI_HEADER_XFLAGS, xflags);
94
95 efx_writed(efx, &hdr, pdu);
96
97 for (i = 0; i < inlen; i += 4)
98 _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
99
100 /* Ensure the payload is written out before the header */
101 wmb();
102
103 /* ring the doorbell with a distinctive value */
104 _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
105}
106
107static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
108{
109 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
110 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
111 int i;
112
113 BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
114 BUG_ON(outlen & 3 || outlen >= 0x100);
115
116 for (i = 0; i < outlen; i += 4)
117 *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
118}
119
120static int efx_mcdi_poll(struct efx_nic *efx)
121{
122 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
123 unsigned int time, finish;
124 unsigned int respseq, respcmd, error;
125 unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
126 unsigned int rc, spins;
127 efx_dword_t reg;
128
129 /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
e0bf54c9 130 rc = -efx_mcdi_poll_reboot(efx);
afd4aea0
BH		 131 if (rc)
132 goto out;
133
134 /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
135 * because generally mcdi responses are fast. After that, back off
136 * and poll once a jiffy (approximately)
137 */
138 spins = TICK_USEC;
139 finish = get_seconds() + MCDI_RPC_TIMEOUT;
140
141 while (1) {
142 if (spins != 0) {
143 --spins;
144 udelay(1);
55029c1d
BH		 145 } else {
146 schedule_timeout_uninterruptible(1);
147 }
afd4aea0
BH		 148
149 time = get_seconds();
150
151 rmb();
152 efx_readd(efx, &reg, pdu);
153
154 /* All 1's indicates that shared memory is in reset (and is
155 * not a valid header). Wait for it to come out reset before
156 * completing the command */
157 if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
158 EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
159 break;
160
161 if (time >= finish)
162 return -ETIMEDOUT;
163 }
164
165 mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
166 respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
167 respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
168 error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
169
170 if (error && mcdi->resplen == 0) {
62776d03 171 netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
afd4aea0
BH		 172 rc = EIO;
173 } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
62776d03
BH		 174 netif_err(efx, hw, efx->net_dev,
175 "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
176 respseq, mcdi->seqno);
afd4aea0
BH		 177 rc = EIO;
178 } else if (error) {
179 efx_readd(efx, &reg, pdu + 4);
180 switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
181#define TRANSLATE_ERROR(name) \
182 case MC_CMD_ERR_ ## name: \
183 rc = name; \
184 break
185 TRANSLATE_ERROR(ENOENT);
186 TRANSLATE_ERROR(EINTR);
187 TRANSLATE_ERROR(EACCES);
188 TRANSLATE_ERROR(EBUSY);
189 TRANSLATE_ERROR(EINVAL);
190 TRANSLATE_ERROR(EDEADLK);
191 TRANSLATE_ERROR(ENOSYS);
192 TRANSLATE_ERROR(ETIME);
193#undef TRANSLATE_ERROR
194 default:
195 rc = EIO;
196 break;
197 }
198 } else
199 rc = 0;
200
201out:
202 mcdi->resprc = rc;
203 if (rc)
204 mcdi->resplen = 0;
205
206 /* Return rc=0 like wait_event_timeout() */
207 return 0;
208}
209
210/* Test and clear MC-rebooted flag for this port/function */
211int efx_mcdi_poll_reboot(struct efx_nic *efx)
212{
213 unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx);
214 efx_dword_t reg;
215 uint32_t value;
216
217 if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
218 return false;
219
220 efx_readd(efx, &reg, addr);
221 value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
222
223 if (value == 0)
224 return 0;
225
226 EFX_ZERO_DWORD(reg);
227 efx_writed(efx, &reg, addr);
228
229 if (value == MC_STATUS_DWORD_ASSERT)
230 return -EINTR;
231 else
232 return -EIO;
233}
234
235static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
236{
237 /* Wait until the interface becomes QUIESCENT and we win the race
238 * to mark it RUNNING. */
239 wait_event(mcdi->wq,
240 atomic_cmpxchg(&mcdi->state,
241 MCDI_STATE_QUIESCENT,
242 MCDI_STATE_RUNNING)
243 == MCDI_STATE_QUIESCENT);
244}
245
246static int efx_mcdi_await_completion(struct efx_nic *efx)
247{
248 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
249
250 if (wait_event_timeout(
251 mcdi->wq,
252 atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
253 msecs_to_jiffies(MCDI_RPC_TIMEOUT * 1000)) == 0)
254 return -ETIMEDOUT;
255
256 /* Check if efx_mcdi_set_mode() switched us back to polled completions.
257 * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
258 * completed the request first, then we'll just end up completing the
259 * request again, which is safe.
260 *
261 * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
262 * wait_event_timeout() implicitly provides.
263 */
264 if (mcdi->mode == MCDI_MODE_POLL)
265 return efx_mcdi_poll(efx);
266
267 return 0;
268}
269
270static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
271{
272 /* If the interface is RUNNING, then move to COMPLETED and wake any
273 * waiters. If the interface isn't in RUNNING then we've received a
274 * duplicate completion after we've already transitioned back to
275 * QUIESCENT. [A subsequent invocation would increment seqno, so would
276 * have failed the seqno check].
277 */
278 if (atomic_cmpxchg(&mcdi->state,
279 MCDI_STATE_RUNNING,
280 MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
281 wake_up(&mcdi->wq);
282 return true;
283 }
284
285 return false;
286}
287
288static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
289{
290 atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
291 wake_up(&mcdi->wq);
292}
293
294static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
295 unsigned int datalen, unsigned int errno)
296{
297 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
298 bool wake = false;
299
300 spin_lock(&mcdi->iface_lock);
301
302 if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
303 if (mcdi->credits)
304 /* The request has been cancelled */
305 --mcdi->credits;
306 else
62776d03
BH		 307 netif_err(efx, hw, efx->net_dev,
308 "MC response mismatch tx seq 0x%x rx "
309 "seq 0x%x\n", seqno, mcdi->seqno);
afd4aea0
BH		 310 } else {
311 mcdi->resprc = errno;
312 mcdi->resplen = datalen;
313
314 wake = true;
315 }
316
317 spin_unlock(&mcdi->iface_lock);
318
319 if (wake)
320 efx_mcdi_complete(mcdi);
321}
322
323/* Issue the given command by writing the data into the shared memory PDU,
324 * ring the doorbell and wait for completion. Copyout the result. */
325int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
326 const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
327 size_t *outlen_actual)
328{
329 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
330 int rc;
331 BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
332
333 efx_mcdi_acquire(mcdi);
334
335 /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
336 spin_lock_bh(&mcdi->iface_lock);
337 ++mcdi->seqno;
338 spin_unlock_bh(&mcdi->iface_lock);
339
340 efx_mcdi_copyin(efx, cmd, inbuf, inlen);
341
342 if (mcdi->mode == MCDI_MODE_POLL)
343 rc = efx_mcdi_poll(efx);
344 else
345 rc = efx_mcdi_await_completion(efx);
346
347 if (rc != 0) {
348 /* Close the race with efx_mcdi_ev_cpl() executing just too late
349 * and completing a request we've just cancelled, by ensuring
350 * that the seqno check therein fails.
351 */
352 spin_lock_bh(&mcdi->iface_lock);
353 ++mcdi->seqno;
354 ++mcdi->credits;
355 spin_unlock_bh(&mcdi->iface_lock);
356
62776d03
BH		 357 netif_err(efx, hw, efx->net_dev,
358 "MC command 0x%x inlen %d mode %d timed out\n",
359 cmd, (int)inlen, mcdi->mode);
afd4aea0
BH		 360 } else {
361 size_t resplen;
362
363 /* At the very least we need a memory barrier here to ensure
364 * we pick up changes from efx_mcdi_ev_cpl(). Protect against
365 * a spurious efx_mcdi_ev_cpl() running concurrently by
366 * acquiring the iface_lock. */
367 spin_lock_bh(&mcdi->iface_lock);
368 rc = -mcdi->resprc;
369 resplen = mcdi->resplen;
370 spin_unlock_bh(&mcdi->iface_lock);
371
372 if (rc == 0) {
373 efx_mcdi_copyout(efx, outbuf,
374 min(outlen, mcdi->resplen + 3) & ~0x3);
375 if (outlen_actual != NULL)
376 *outlen_actual = resplen;
377 } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
378 ; /* Don't reset if MC_CMD_REBOOT returns EIO */
379 else if (rc == -EIO || rc == -EINTR) {
62776d03
BH		 380 netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
381 -rc);
afd4aea0
BH		 382 efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
383 } else
f18ca364 384 netif_dbg(efx, hw, efx->net_dev,
62776d03
BH		 385 "MC command 0x%x inlen %d failed rc=%d\n",
386 cmd, (int)inlen, -rc);
afd4aea0
BH		 387 }
388
389 efx_mcdi_release(mcdi);
390 return rc;
391}
392
393void efx_mcdi_mode_poll(struct efx_nic *efx)
394{
395 struct efx_mcdi_iface *mcdi;
396
397 if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
398 return;
399
400 mcdi = efx_mcdi(efx);
401 if (mcdi->mode == MCDI_MODE_POLL)
402 return;
403
404 /* We can switch from event completion to polled completion, because
405 * mcdi requests are always completed in shared memory. We do this by
406 * switching the mode to POLL'd then completing the request.
407 * efx_mcdi_await_completion() will then call efx_mcdi_poll().
408 *
409 * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
410 * which efx_mcdi_complete() provides for us.
411 */
412 mcdi->mode = MCDI_MODE_POLL;
413
414 efx_mcdi_complete(mcdi);
415}
416
417void efx_mcdi_mode_event(struct efx_nic *efx)
418{
419 struct efx_mcdi_iface *mcdi;
420
421 if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
422 return;
423
424 mcdi = efx_mcdi(efx);
425
426 if (mcdi->mode == MCDI_MODE_EVENTS)
427 return;
428
429 /* We can't switch from polled to event completion in the middle of a
430 * request, because the completion method is specified in the request.
431 * So acquire the interface to serialise the requestors. We don't need
432 * to acquire the iface_lock to change the mode here, but we do need a
433 * write memory barrier ensure that efx_mcdi_rpc() sees it, which
434 * efx_mcdi_acquire() provides.
435 */
436 efx_mcdi_acquire(mcdi);
437 mcdi->mode = MCDI_MODE_EVENTS;
438 efx_mcdi_release(mcdi);
439}
440
441static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
442{
443 struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
444
445 /* If there is an outstanding MCDI request, it has been terminated
446 * either by a BADASSERT or REBOOT event. If the mcdi interface is
447 * in polled mode, then do nothing because the MC reboot handler will
448 * set the header correctly. However, if the mcdi interface is waiting
449 * for a CMDDONE event it won't receive it [and since all MCDI events
450 * are sent to the same queue, we can't be racing with
451 * efx_mcdi_ev_cpl()]
452 *
453 * There's a race here with efx_mcdi_rpc(), because we might receive
454 * a REBOOT event *before* the request has been copied out. In polled
455 * mode (during startup) this is irrelevent, because efx_mcdi_complete()
456 * is ignored. In event mode, this condition is just an edge-case of
457 * receiving a REBOOT event after posting the MCDI request. Did the mc
458 * reboot before or after the copyout? The best we can do always is
459 * just return failure.
460 */
461 spin_lock(&mcdi->iface_lock);
462 if (efx_mcdi_complete(mcdi)) {
463 if (mcdi->mode == MCDI_MODE_EVENTS) {
464 mcdi->resprc = rc;
465 mcdi->resplen = 0;
18e3ee2c 466 ++mcdi->credits;
afd4aea0
BH		 467 }
468 } else
469 /* Nobody was waiting for an MCDI request, so trigger a reset */
470 efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
471
472 spin_unlock(&mcdi->iface_lock);
473}
474
475static unsigned int efx_mcdi_event_link_speed[] = {
476 [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
477 [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
478 [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
479};
480
481
482static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
483{
484 u32 flags, fcntl, speed, lpa;
485
486 speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
487 EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
488 speed = efx_mcdi_event_link_speed[speed];
489
490 flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
491 fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
492 lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
493
494 /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
495 * which is only run after flushing the event queues. Therefore, it
496 * is safe to modify the link state outside of the mac_lock here.
497 */
498 efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
499
500 efx_mcdi_phy_check_fcntl(efx, lpa);
501
502 efx_link_status_changed(efx);
503}
504
505static const char *sensor_names[] = {
506 [MC_CMD_SENSOR_CONTROLLER_TEMP] = "Controller temp. sensor",
507 [MC_CMD_SENSOR_PHY_COMMON_TEMP] = "PHY shared temp. sensor",
508 [MC_CMD_SENSOR_CONTROLLER_COOLING] = "Controller cooling",
509 [MC_CMD_SENSOR_PHY0_TEMP] = "PHY 0 temp. sensor",
510 [MC_CMD_SENSOR_PHY0_COOLING] = "PHY 0 cooling",
511 [MC_CMD_SENSOR_PHY1_TEMP] = "PHY 1 temp. sensor",
512 [MC_CMD_SENSOR_PHY1_COOLING] = "PHY 1 cooling",
513 [MC_CMD_SENSOR_IN_1V0] = "1.0V supply sensor",
514 [MC_CMD_SENSOR_IN_1V2] = "1.2V supply sensor",
515 [MC_CMD_SENSOR_IN_1V8] = "1.8V supply sensor",
516 [MC_CMD_SENSOR_IN_2V5] = "2.5V supply sensor",
517 [MC_CMD_SENSOR_IN_3V3] = "3.3V supply sensor",
518 [MC_CMD_SENSOR_IN_12V0] = "12V supply sensor"
519};
520
521static const char *sensor_status_names[] = {
522 [MC_CMD_SENSOR_STATE_OK] = "OK",
523 [MC_CMD_SENSOR_STATE_WARNING] = "Warning",
524 [MC_CMD_SENSOR_STATE_FATAL] = "Fatal",
525 [MC_CMD_SENSOR_STATE_BROKEN] = "Device failure",
526};
527
528static void efx_mcdi_sensor_event(struct efx_nic *efx, efx_qword_t *ev)
529{
530 unsigned int monitor, state, value;
531 const char *name, *state_txt;
532 monitor = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_MONITOR);
533 state = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_STATE);
534 value = EFX_QWORD_FIELD(*ev, MCDI_EVENT_SENSOREVT_VALUE);
535 /* Deal gracefully with the board having more drivers than we
536 * know about, but do not expect new sensor states. */
537 name = (monitor >= ARRAY_SIZE(sensor_names))
538 ? "No sensor name available" :
539 sensor_names[monitor];
540 EFX_BUG_ON_PARANOID(state >= ARRAY_SIZE(sensor_status_names));
541 state_txt = sensor_status_names[state];
542
62776d03
BH		 543 netif_err(efx, hw, efx->net_dev,
544 "Sensor %d (%s) reports condition '%s' for raw value %d\n",
545 monitor, name, state_txt, value);
afd4aea0
BH		 546}
547
548/* Called from falcon_process_eventq for MCDI events */
549void efx_mcdi_process_event(struct efx_channel *channel,
550 efx_qword_t *event)
551{
552 struct efx_nic *efx = channel->efx;
553 int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
554 u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
555
556 switch (code) {
557 case MCDI_EVENT_CODE_BADSSERT:
62776d03
BH		 558 netif_err(efx, hw, efx->net_dev,
559 "MC watchdog or assertion failure at 0x%x\n", data);
afd4aea0
BH		 560 efx_mcdi_ev_death(efx, EINTR);
561 break;
562
563 case MCDI_EVENT_CODE_PMNOTICE:
62776d03 564 netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
afd4aea0
BH		 565 break;
566
567 case MCDI_EVENT_CODE_CMDDONE:
568 efx_mcdi_ev_cpl(efx,
569 MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
570 MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
571 MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
572 break;
573
574 case MCDI_EVENT_CODE_LINKCHANGE:
575 efx_mcdi_process_link_change(efx, event);
576 break;
577 case MCDI_EVENT_CODE_SENSOREVT:
578 efx_mcdi_sensor_event(efx, event);
579 break;
580 case MCDI_EVENT_CODE_SCHEDERR:
62776d03
BH		 581 netif_info(efx, hw, efx->net_dev,
582 "MC Scheduler error address=0x%x\n", data);
afd4aea0
BH		 583 break;
584 case MCDI_EVENT_CODE_REBOOT:
62776d03 585 netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
afd4aea0
BH		 586 efx_mcdi_ev_death(efx, EIO);
587 break;
588 case MCDI_EVENT_CODE_MAC_STATS_DMA:
589 /* MAC stats are gather lazily. We can ignore this. */
590 break;
591
592 default:
62776d03
BH		 593 netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
594 code);
afd4aea0
BH		 595 }
596}
597
598/**************************************************************************
599 *
600 * Specific request functions
601 *
602 **************************************************************************
603 */
604
605int efx_mcdi_fwver(struct efx_nic *efx, u64 *version, u32 *build)
606{
607 u8 outbuf[ALIGN(MC_CMD_GET_VERSION_V1_OUT_LEN, 4)];
608 size_t outlength;
609 const __le16 *ver_words;
610 int rc;
611
612 BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
613
614 rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
615 outbuf, sizeof(outbuf), &outlength);
616 if (rc)
617 goto fail;
618
619 if (outlength == MC_CMD_GET_VERSION_V0_OUT_LEN) {
620 *version = 0;
621 *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
622 return 0;
623 }
624
625 if (outlength < MC_CMD_GET_VERSION_V1_OUT_LEN) {
00bbb4a5 626 rc = -EIO;
afd4aea0
BH		 627 goto fail;
628 }
629
630 ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
631 *version = (((u64)le16_to_cpu(ver_words[0]) << 48) |
632 ((u64)le16_to_cpu(ver_words[1]) << 32) |
633 ((u64)le16_to_cpu(ver_words[2]) << 16) |
634 le16_to_cpu(ver_words[3]));
635 *build = MCDI_DWORD(outbuf, GET_VERSION_OUT_FIRMWARE);
636
637 return 0;
638
639fail:
62776d03 640 netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 641 return rc;
642}
643
644int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
645 bool *was_attached)
646{
647 u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
648 u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
649 size_t outlen;
650 int rc;
651
652 MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
653 driver_operating ? 1 : 0);
654 MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
655
656 rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
657 outbuf, sizeof(outbuf), &outlen);
658 if (rc)
659 goto fail;
00bbb4a5
BH		 660 if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
661 rc = -EIO;
afd4aea0 662 goto fail;
00bbb4a5 663 }
afd4aea0
BH		 664
665 if (was_attached != NULL)
666 *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
667 return 0;
668
669fail:
62776d03 670 netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 671 return rc;
672}
673
674int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
675 u16 *fw_subtype_list)
676{
677 uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LEN];
678 size_t outlen;
679 int port_num = efx_port_num(efx);
680 int offset;
681 int rc;
682
683 BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
684
685 rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
686 outbuf, sizeof(outbuf), &outlen);
687 if (rc)
688 goto fail;
689
690 if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LEN) {
00bbb4a5 691 rc = -EIO;
afd4aea0
BH		 692 goto fail;
693 }
694
695 offset = (port_num)
696 ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
697 : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
698 if (mac_address)
699 memcpy(mac_address, outbuf + offset, ETH_ALEN);
700 if (fw_subtype_list)
701 memcpy(fw_subtype_list,
702 outbuf + MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST,
703 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN);
704
705 return 0;
706
707fail:
62776d03
BH		 708 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
709 __func__, rc, (int)outlen);
afd4aea0
BH		 710
711 return rc;
712}
713
714int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
715{
716 u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
717 u32 dest = 0;
718 int rc;
719
720 if (uart)
721 dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
722 if (evq)
723 dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
724
725 MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
726 MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
727
728 BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
729
730 rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
731 NULL, 0, NULL);
732 if (rc)
733 goto fail;
734
735 return 0;
736
737fail:
62776d03 738 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 739 return rc;
740}
741
742int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
743{
744 u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
745 size_t outlen;
746 int rc;
747
748 BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
749
750 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
751 outbuf, sizeof(outbuf), &outlen);
752 if (rc)
753 goto fail;
00bbb4a5
BH		 754 if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
755 rc = -EIO;
afd4aea0 756 goto fail;
00bbb4a5 757 }
afd4aea0
BH		 758
759 *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
760 return 0;
761
762fail:
62776d03
BH		 763 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
764 __func__, rc);
afd4aea0
BH		 765 return rc;
766}
767
768int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
769 size_t *size_out, size_t *erase_size_out,
770 bool *protected_out)
771{
772 u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
773 u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
774 size_t outlen;
775 int rc;
776
777 MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
778
779 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
780 outbuf, sizeof(outbuf), &outlen);
781 if (rc)
782 goto fail;
00bbb4a5
BH		 783 if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
784 rc = -EIO;
afd4aea0 785 goto fail;
00bbb4a5 786 }
afd4aea0
BH		 787
788 *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
789 *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
790 *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
791 (1 << MC_CMD_NVRAM_PROTECTED_LBN));
792 return 0;
793
794fail:
62776d03 795 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 796 return rc;
797}
798
799int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
800{
801 u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
802 int rc;
803
804 MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
805
806 BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
807
808 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
809 NULL, 0, NULL);
810 if (rc)
811 goto fail;
812
813 return 0;
814
815fail:
62776d03 816 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 817 return rc;
818}
819
820int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
821 loff_t offset, u8 *buffer, size_t length)
822{
823 u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
5a27e86b 824 u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
afd4aea0
BH		 825 size_t outlen;
826 int rc;
827
828 MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
829 MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
830 MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
831
832 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
833 outbuf, sizeof(outbuf), &outlen);
834 if (rc)
835 goto fail;
836
837 memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
838 return 0;
839
840fail:
62776d03 841 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 842 return rc;
843}
844
845int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
846 loff_t offset, const u8 *buffer, size_t length)
847{
5a27e86b 848 u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
afd4aea0
BH		 849 int rc;
850
851 MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
852 MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
853 MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
854 memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
855
856 BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
857
5a27e86b
BH		 858 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
859 ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
afd4aea0
BH		 860 NULL, 0, NULL);
861 if (rc)
862 goto fail;
863
864 return 0;
865
866fail:
62776d03 867 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 868 return rc;
869}
870
871int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
872 loff_t offset, size_t length)
873{
874 u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
875 int rc;
876
877 MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
878 MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
879 MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
880
881 BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
882
883 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
884 NULL, 0, NULL);
885 if (rc)
886 goto fail;
887
888 return 0;
889
890fail:
62776d03 891 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 892 return rc;
893}
894
895int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
896{
897 u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
898 int rc;
899
900 MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
901
902 BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
903
904 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
905 NULL, 0, NULL);
906 if (rc)
907 goto fail;
908
909 return 0;
910
911fail:
62776d03 912 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 913 return rc;
914}
915
2e803407
BH		 916static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
917{
918 u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
919 u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
920 int rc;
921
922 MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
923
924 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
925 outbuf, sizeof(outbuf), NULL);
926 if (rc)
927 return rc;
928
929 switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
930 case MC_CMD_NVRAM_TEST_PASS:
931 case MC_CMD_NVRAM_TEST_NOTSUPP:
932 return 0;
933 default:
934 return -EIO;
935 }
936}
937
938int efx_mcdi_nvram_test_all(struct efx_nic *efx)
939{
940 u32 nvram_types;
941 unsigned int type;
942 int rc;
943
944 rc = efx_mcdi_nvram_types(efx, &nvram_types);
945 if (rc)
b548a988 946 goto fail1;
2e803407
BH		 947
948 type = 0;
949 while (nvram_types != 0) {
950 if (nvram_types & 1) {
951 rc = efx_mcdi_nvram_test(efx, type);
952 if (rc)
b548a988 953 goto fail2;
2e803407
BH		 954 }
955 type++;
956 nvram_types >>= 1;
957 }
958
959 return 0;
b548a988
BH		 960
961fail2:
62776d03
BH		 962 netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
963 __func__, type);
b548a988 964fail1:
62776d03 965 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
b548a988 966 return rc;
2e803407
BH		 967}
968
8b2103ad 969static int efx_mcdi_read_assertion(struct efx_nic *efx)
afd4aea0 970{
8b2103ad
SH		 971 u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
972 u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
afd4aea0
BH		 973 unsigned int flags, index, ofst;
974 const char *reason;
975 size_t outlen;
976 int retry;
977 int rc;
978
8b2103ad
SH		 979 /* Attempt to read any stored assertion state before we reboot
980 * the mcfw out of the assertion handler. Retry twice, once
afd4aea0
BH		 981 * because a boot-time assertion might cause this command to fail
982 * with EINTR. And once again because GET_ASSERTS can race with
983 * MC_CMD_REBOOT running on the other port. */
984 retry = 2;
985 do {
8b2103ad 986 MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
afd4aea0 987 rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
8b2103ad
SH		 988 inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
989 outbuf, sizeof(outbuf), &outlen);
afd4aea0
BH		 990 } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
991
992 if (rc)
993 return rc;
994 if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
00bbb4a5 995 return -EIO;
afd4aea0 996
8b2103ad
SH		 997 /* Print out any recorded assertion state */
998 flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
afd4aea0
BH		 999 if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
1000 return 0;
1001
afd4aea0
BH		 1002 reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
1003 ? "system-level assertion"
1004 : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
1005 ? "thread-level assertion"
1006 : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
1007 ? "watchdog reset"
1008 : "unknown assertion";
62776d03
BH		 1009 netif_err(efx, hw, efx->net_dev,
1010 "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
1011 MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
1012 MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
afd4aea0
BH		 1013
1014 /* Print out the registers */
1015 ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
1016 for (index = 1; index < 32; index++) {
62776d03 1017 netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
8b2103ad 1018 MCDI_DWORD2(outbuf, ofst));
afd4aea0
BH		 1019 ofst += sizeof(efx_dword_t);
1020 }
1021
1022 return 0;
1023}
1024
8b2103ad
SH		 1025static void efx_mcdi_exit_assertion(struct efx_nic *efx)
1026{
1027 u8 inbuf[MC_CMD_REBOOT_IN_LEN];
1028
1029 /* Atomically reboot the mcfw out of the assertion handler */
1030 BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
1031 MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
1032 MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
1033 efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
1034 NULL, 0, NULL);
1035}
1036
1037int efx_mcdi_handle_assertion(struct efx_nic *efx)
1038{
1039 int rc;
1040
1041 rc = efx_mcdi_read_assertion(efx);
1042 if (rc)
1043 return rc;
1044
1045 efx_mcdi_exit_assertion(efx);
1046
1047 return 0;
1048}
1049
afd4aea0
BH		 1050void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1051{
1052 u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
1053 int rc;
1054
1055 BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
1056 BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
1057 BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
1058
1059 BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
1060
1061 MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
1062
1063 rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
1064 NULL, 0, NULL);
1065 if (rc)
62776d03
BH		 1066 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
1067 __func__, rc);
afd4aea0
BH		 1068}
1069
1070int efx_mcdi_reset_port(struct efx_nic *efx)
1071{
1072 int rc = efx_mcdi_rpc(efx, MC_CMD_PORT_RESET, NULL, 0, NULL, 0, NULL);
1073 if (rc)
62776d03
BH		 1074 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
1075 __func__, rc);
afd4aea0
BH		 1076 return rc;
1077}
1078
1079int efx_mcdi_reset_mc(struct efx_nic *efx)
1080{
1081 u8 inbuf[MC_CMD_REBOOT_IN_LEN];
1082 int rc;
1083
1084 BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
1085 MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
1086 rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
1087 NULL, 0, NULL);
1088 /* White is black, and up is down */
1089 if (rc == -EIO)
1090 return 0;
1091 if (rc == 0)
1092 rc = -EIO;
62776d03 1093 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 1094 return rc;
1095}
1096
d215697f 1097static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
1098 const u8 *mac, int *id_out)
afd4aea0
BH		 1099{
1100 u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
1101 u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
1102 size_t outlen;
1103 int rc;
1104
1105 MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
1106 MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
1107 MC_CMD_FILTER_MODE_SIMPLE);
1108 memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
1109
1110 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
1111 outbuf, sizeof(outbuf), &outlen);
1112 if (rc)
1113 goto fail;
1114
1115 if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
00bbb4a5 1116 rc = -EIO;
afd4aea0
BH		 1117 goto fail;
1118 }
1119
1120 *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
1121
1122 return 0;
1123
1124fail:
1125 *id_out = -1;
62776d03 1126 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 1127 return rc;
1128
1129}
1130
1131
1132int
1133efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
1134{
1135 return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
1136}
1137
1138
1139int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
1140{
1141 u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
1142 size_t outlen;
1143 int rc;
1144
1145 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
1146 outbuf, sizeof(outbuf), &outlen);
1147 if (rc)
1148 goto fail;
1149
1150 if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
00bbb4a5 1151 rc = -EIO;
afd4aea0
BH		 1152 goto fail;
1153 }
1154
1155 *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
1156
1157 return 0;
1158
1159fail:
1160 *id_out = -1;
62776d03 1161 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 1162 return rc;
1163}
1164
1165
1166int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
1167{
1168 u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
1169 int rc;
1170
1171 MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
1172
1173 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
1174 NULL, 0, NULL);
1175 if (rc)
1176 goto fail;
1177
1178 return 0;
1179
1180fail:
62776d03 1181 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 1182 return rc;
1183}
1184
1185
1186int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
1187{
1188 int rc;
1189
1190 rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
1191 if (rc)
1192 goto fail;
1193
1194 return 0;
1195
1196fail:
62776d03 1197 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
afd4aea0
BH		 1198 return rc;
1199}
1200
Linux kernel - Deliverables
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