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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
906bb26c | 3 | * Copyright 2006-2009 Solarflare Communications Inc. |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | /* | |
10 | * Useful functions for working with MDIO clause 45 PHYs | |
11 | */ | |
12 | #include <linux/types.h> | |
13 | #include <linux/ethtool.h> | |
14 | #include <linux/delay.h> | |
15 | #include "net_driver.h" | |
16 | #include "mdio_10g.h" | |
8b9dc8dd | 17 | #include "workarounds.h" |
8ceee660 | 18 | |
68e7f45e | 19 | unsigned efx_mdio_id_oui(u32 id) |
3f39a5e9 BH |
20 | { |
21 | unsigned oui = 0; | |
22 | int i; | |
23 | ||
24 | /* The bits of the OUI are designated a..x, with a=0 and b variable. | |
25 | * In the id register c is the MSB but the OUI is conventionally | |
26 | * written as bytes h..a, p..i, x..q. Reorder the bits accordingly. */ | |
27 | for (i = 0; i < 22; ++i) | |
28 | if (id & (1 << (i + 10))) | |
29 | oui |= 1 << (i ^ 7); | |
30 | ||
31 | return oui; | |
32 | } | |
33 | ||
68e7f45e | 34 | int efx_mdio_reset_mmd(struct efx_nic *port, int mmd, |
8ceee660 BH |
35 | int spins, int spintime) |
36 | { | |
37 | u32 ctrl; | |
8ceee660 BH |
38 | |
39 | /* Catch callers passing values in the wrong units (or just silly) */ | |
40 | EFX_BUG_ON_PARANOID(spins * spintime >= 5000); | |
41 | ||
68e7f45e | 42 | efx_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET); |
8ceee660 BH |
43 | /* Wait for the reset bit to clear. */ |
44 | do { | |
45 | msleep(spintime); | |
68e7f45e | 46 | ctrl = efx_mdio_read(port, mmd, MDIO_CTRL1); |
8ceee660 BH |
47 | spins--; |
48 | ||
68e7f45e | 49 | } while (spins && (ctrl & MDIO_CTRL1_RESET)); |
8ceee660 BH |
50 | |
51 | return spins ? spins : -ETIMEDOUT; | |
52 | } | |
53 | ||
68e7f45e | 54 | static int efx_mdio_check_mmd(struct efx_nic *efx, int mmd, int fault_fatal) |
8ceee660 BH |
55 | { |
56 | int status; | |
8ceee660 | 57 | |
3273c2e8 BH |
58 | if (LOOPBACK_INTERNAL(efx)) |
59 | return 0; | |
60 | ||
04cc8cac BH |
61 | if (mmd != MDIO_MMD_AN) { |
62 | /* Read MMD STATUS2 to check it is responding. */ | |
68e7f45e BH |
63 | status = efx_mdio_read(efx, mmd, MDIO_STAT2); |
64 | if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) { | |
62776d03 BH |
65 | netif_err(efx, hw, efx->net_dev, |
66 | "PHY MMD %d not responding.\n", mmd); | |
04cc8cac BH |
67 | return -EIO; |
68 | } | |
8ceee660 BH |
69 | } |
70 | ||
71 | /* Read MMD STATUS 1 to check for fault. */ | |
68e7f45e BH |
72 | status = efx_mdio_read(efx, mmd, MDIO_STAT1); |
73 | if (status & MDIO_STAT1_FAULT) { | |
8ceee660 | 74 | if (fault_fatal) { |
62776d03 BH |
75 | netif_err(efx, hw, efx->net_dev, |
76 | "PHY MMD %d reporting fatal" | |
77 | " fault: status %x\n", mmd, status); | |
8ceee660 BH |
78 | return -EIO; |
79 | } else { | |
62776d03 BH |
80 | netif_dbg(efx, hw, efx->net_dev, |
81 | "PHY MMD %d reporting status" | |
82 | " %x (expected)\n", mmd, status); | |
8ceee660 BH |
83 | } |
84 | } | |
85 | return 0; | |
86 | } | |
87 | ||
88 | /* This ought to be ridiculous overkill. We expect it to fail rarely */ | |
89 | #define MDIO45_RESET_TIME 1000 /* ms */ | |
90 | #define MDIO45_RESET_ITERS 100 | |
91 | ||
68e7f45e | 92 | int efx_mdio_wait_reset_mmds(struct efx_nic *efx, unsigned int mmd_mask) |
8ceee660 BH |
93 | { |
94 | const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS; | |
95 | int tries = MDIO45_RESET_ITERS; | |
96 | int rc = 0; | |
97 | int in_reset; | |
98 | ||
99 | while (tries) { | |
100 | int mask = mmd_mask; | |
101 | int mmd = 0; | |
102 | int stat; | |
103 | in_reset = 0; | |
104 | while (mask) { | |
105 | if (mask & 1) { | |
68e7f45e | 106 | stat = efx_mdio_read(efx, mmd, MDIO_CTRL1); |
8ceee660 | 107 | if (stat < 0) { |
62776d03 BH |
108 | netif_err(efx, hw, efx->net_dev, |
109 | "failed to read status of" | |
110 | " MMD %d\n", mmd); | |
8ceee660 BH |
111 | return -EIO; |
112 | } | |
68e7f45e | 113 | if (stat & MDIO_CTRL1_RESET) |
8ceee660 BH |
114 | in_reset |= (1 << mmd); |
115 | } | |
116 | mask = mask >> 1; | |
117 | mmd++; | |
118 | } | |
119 | if (!in_reset) | |
120 | break; | |
121 | tries--; | |
122 | msleep(spintime); | |
123 | } | |
124 | if (in_reset != 0) { | |
62776d03 BH |
125 | netif_err(efx, hw, efx->net_dev, |
126 | "not all MMDs came out of reset in time." | |
127 | " MMDs still in reset: %x\n", in_reset); | |
8ceee660 BH |
128 | rc = -ETIMEDOUT; |
129 | } | |
130 | return rc; | |
131 | } | |
132 | ||
68e7f45e BH |
133 | int efx_mdio_check_mmds(struct efx_nic *efx, |
134 | unsigned int mmd_mask, unsigned int fatal_mask) | |
8ceee660 | 135 | { |
68e7f45e | 136 | int mmd = 0, probe_mmd, devs1, devs2; |
27dd2cac | 137 | u32 devices; |
8ceee660 BH |
138 | |
139 | /* Historically we have probed the PHYXS to find out what devices are | |
140 | * present,but that doesn't work so well if the PHYXS isn't expected | |
141 | * to exist, if so just find the first item in the list supplied. */ | |
68e7f45e | 142 | probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS : |
8ceee660 | 143 | __ffs(mmd_mask); |
8ceee660 BH |
144 | |
145 | /* Check all the expected MMDs are present */ | |
68e7f45e BH |
146 | devs1 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS1); |
147 | devs2 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS2); | |
148 | if (devs1 < 0 || devs2 < 0) { | |
62776d03 BH |
149 | netif_err(efx, hw, efx->net_dev, |
150 | "failed to read devices present\n"); | |
8ceee660 BH |
151 | return -EIO; |
152 | } | |
68e7f45e | 153 | devices = devs1 | (devs2 << 16); |
8ceee660 | 154 | if ((devices & mmd_mask) != mmd_mask) { |
62776d03 BH |
155 | netif_err(efx, hw, efx->net_dev, |
156 | "required MMDs not present: got %x, wanted %x\n", | |
157 | devices, mmd_mask); | |
8ceee660 BH |
158 | return -ENODEV; |
159 | } | |
62776d03 | 160 | netif_vdbg(efx, hw, efx->net_dev, "Devices present: %x\n", devices); |
8ceee660 BH |
161 | |
162 | /* Check all required MMDs are responding and happy. */ | |
163 | while (mmd_mask) { | |
164 | if (mmd_mask & 1) { | |
165 | int fault_fatal = fatal_mask & 1; | |
68e7f45e | 166 | if (efx_mdio_check_mmd(efx, mmd, fault_fatal)) |
8ceee660 BH |
167 | return -EIO; |
168 | } | |
169 | mmd_mask = mmd_mask >> 1; | |
170 | fatal_mask = fatal_mask >> 1; | |
171 | mmd++; | |
172 | } | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
68e7f45e | 177 | bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask) |
8ceee660 | 178 | { |
3273c2e8 BH |
179 | /* If the port is in loopback, then we should only consider a subset |
180 | * of mmd's */ | |
181 | if (LOOPBACK_INTERNAL(efx)) | |
dc8cfa55 | 182 | return true; |
e58f69f4 | 183 | else if (LOOPBACK_MASK(efx) & LOOPBACKS_WS) |
dc8cfa55 | 184 | return false; |
f8b87c17 BH |
185 | else if (efx_phy_mode_disabled(efx->phy_mode)) |
186 | return false; | |
67797763 | 187 | else if (efx->loopback_mode == LOOPBACK_PHYXS) |
68e7f45e BH |
188 | mmd_mask &= ~(MDIO_DEVS_PHYXS | |
189 | MDIO_DEVS_PCS | | |
190 | MDIO_DEVS_PMAPMD | | |
191 | MDIO_DEVS_AN); | |
67797763 | 192 | else if (efx->loopback_mode == LOOPBACK_PCS) |
68e7f45e BH |
193 | mmd_mask &= ~(MDIO_DEVS_PCS | |
194 | MDIO_DEVS_PMAPMD | | |
195 | MDIO_DEVS_AN); | |
3273c2e8 | 196 | else if (efx->loopback_mode == LOOPBACK_PMAPMD) |
68e7f45e BH |
197 | mmd_mask &= ~(MDIO_DEVS_PMAPMD | |
198 | MDIO_DEVS_AN); | |
67797763 | 199 | |
68e7f45e | 200 | return mdio45_links_ok(&efx->mdio, mmd_mask); |
8ceee660 BH |
201 | } |
202 | ||
68e7f45e | 203 | void efx_mdio_transmit_disable(struct efx_nic *efx) |
3273c2e8 | 204 | { |
68e7f45e BH |
205 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, |
206 | MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL, | |
207 | efx->phy_mode & PHY_MODE_TX_DISABLED); | |
3273c2e8 BH |
208 | } |
209 | ||
68e7f45e | 210 | void efx_mdio_phy_reconfigure(struct efx_nic *efx) |
3273c2e8 | 211 | { |
68e7f45e BH |
212 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, |
213 | MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK, | |
214 | efx->loopback_mode == LOOPBACK_PMAPMD); | |
215 | efx_mdio_set_flag(efx, MDIO_MMD_PCS, | |
216 | MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK, | |
217 | efx->loopback_mode == LOOPBACK_PCS); | |
218 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, | |
219 | MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK, | |
e58f69f4 | 220 | efx->loopback_mode == LOOPBACK_PHYXS_WS); |
3273c2e8 BH |
221 | } |
222 | ||
68e7f45e BH |
223 | static void efx_mdio_set_mmd_lpower(struct efx_nic *efx, |
224 | int lpower, int mmd) | |
3e133c44 | 225 | { |
68e7f45e | 226 | int stat = efx_mdio_read(efx, mmd, MDIO_STAT1); |
3e133c44 | 227 | |
62776d03 | 228 | netif_vdbg(efx, drv, efx->net_dev, "Setting low power mode for MMD %d to %d\n", |
3e133c44 BH |
229 | mmd, lpower); |
230 | ||
68e7f45e BH |
231 | if (stat & MDIO_STAT1_LPOWERABLE) { |
232 | efx_mdio_set_flag(efx, mmd, MDIO_CTRL1, | |
233 | MDIO_CTRL1_LPOWER, lpower); | |
3e133c44 BH |
234 | } |
235 | } | |
236 | ||
68e7f45e BH |
237 | void efx_mdio_set_mmds_lpower(struct efx_nic *efx, |
238 | int low_power, unsigned int mmd_mask) | |
3e133c44 BH |
239 | { |
240 | int mmd = 0; | |
68e7f45e | 241 | mmd_mask &= ~MDIO_DEVS_AN; |
3e133c44 BH |
242 | while (mmd_mask) { |
243 | if (mmd_mask & 1) | |
68e7f45e | 244 | efx_mdio_set_mmd_lpower(efx, low_power, mmd); |
3e133c44 BH |
245 | mmd_mask = (mmd_mask >> 1); |
246 | mmd++; | |
247 | } | |
248 | } | |
249 | ||
04cc8cac | 250 | /** |
68e7f45e | 251 | * efx_mdio_set_settings - Set (some of) the PHY settings over MDIO. |
8ceee660 BH |
252 | * @efx: Efx NIC |
253 | * @ecmd: New settings | |
8ceee660 | 254 | */ |
68e7f45e | 255 | int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
8ceee660 | 256 | { |
04cc8cac | 257 | struct ethtool_cmd prev; |
04cc8cac BH |
258 | |
259 | efx->phy_op->get_settings(efx, &prev); | |
260 | ||
261 | if (ecmd->advertising == prev.advertising && | |
262 | ecmd->speed == prev.speed && | |
263 | ecmd->duplex == prev.duplex && | |
264 | ecmd->port == prev.port && | |
265 | ecmd->autoneg == prev.autoneg) | |
8ceee660 | 266 | return 0; |
04cc8cac BH |
267 | |
268 | /* We can only change these settings for -T PHYs */ | |
269 | if (prev.port != PORT_TP || ecmd->port != PORT_TP) | |
270 | return -EINVAL; | |
271 | ||
af4ad9bc | 272 | /* Check that PHY supports these settings */ |
fc2b5e67 BH |
273 | if (!ecmd->autoneg || |
274 | (ecmd->advertising | SUPPORTED_Autoneg) & ~prev.supported) | |
04cc8cac BH |
275 | return -EINVAL; |
276 | ||
d3245b28 BH |
277 | efx_link_set_advertising(efx, ecmd->advertising | ADVERTISED_Autoneg); |
278 | efx_mdio_an_reconfigure(efx); | |
279 | return 0; | |
280 | } | |
281 | ||
282 | /** | |
283 | * efx_mdio_an_reconfigure - Push advertising flags and restart autonegotiation | |
284 | * @efx: Efx NIC | |
285 | */ | |
286 | void efx_mdio_an_reconfigure(struct efx_nic *efx) | |
287 | { | |
d3245b28 BH |
288 | int reg; |
289 | ||
290 | WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN)); | |
fc2b5e67 BH |
291 | |
292 | /* Set up the base page */ | |
8fbca791 | 293 | reg = ADVERTISE_CSMA | ADVERTISE_RESV; |
d3245b28 BH |
294 | if (efx->link_advertising & ADVERTISED_Pause) |
295 | reg |= ADVERTISE_PAUSE_CAP; | |
296 | if (efx->link_advertising & ADVERTISED_Asym_Pause) | |
297 | reg |= ADVERTISE_PAUSE_ASYM; | |
fc2b5e67 BH |
298 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg); |
299 | ||
8fbca791 BH |
300 | /* Set up the (extended) next page */ |
301 | efx->phy_op->set_npage_adv(efx, efx->link_advertising); | |
fc2b5e67 BH |
302 | |
303 | /* Enable and restart AN */ | |
304 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1); | |
8fbca791 | 305 | reg |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_XNP; |
fc2b5e67 | 306 | efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg); |
04cc8cac BH |
307 | } |
308 | ||
68e7f45e | 309 | enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx) |
04cc8cac | 310 | { |
18ea024f | 311 | BUILD_BUG_ON(EFX_FC_AUTO & (EFX_FC_RX | EFX_FC_TX)); |
04cc8cac | 312 | |
18ea024f | 313 | if (!(efx->wanted_fc & EFX_FC_AUTO)) |
04cc8cac | 314 | return efx->wanted_fc; |
18ea024f BH |
315 | |
316 | WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN)); | |
317 | ||
318 | return mii_resolve_flowctrl_fdx( | |
319 | mii_advertise_flowctrl(efx->wanted_fc), | |
320 | efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA)); | |
8ceee660 | 321 | } |
4f16c073 BH |
322 | |
323 | int efx_mdio_test_alive(struct efx_nic *efx) | |
324 | { | |
325 | int rc; | |
326 | int devad = __ffs(efx->mdio.mmds); | |
327 | u16 physid1, physid2; | |
328 | ||
329 | mutex_lock(&efx->mac_lock); | |
330 | ||
331 | physid1 = efx_mdio_read(efx, devad, MDIO_DEVID1); | |
332 | physid2 = efx_mdio_read(efx, devad, MDIO_DEVID2); | |
333 | ||
334 | if ((physid1 == 0x0000) || (physid1 == 0xffff) || | |
335 | (physid2 == 0x0000) || (physid2 == 0xffff)) { | |
62776d03 BH |
336 | netif_err(efx, hw, efx->net_dev, |
337 | "no MDIO PHY present with ID %d\n", efx->mdio.prtad); | |
4f16c073 BH |
338 | rc = -EINVAL; |
339 | } else { | |
340 | rc = efx_mdio_check_mmds(efx, efx->mdio.mmds, 0); | |
341 | } | |
342 | ||
343 | mutex_unlock(&efx->mac_lock); | |
344 | return rc; | |
345 | } |