[deliverable/linux.git] / drivers / net / sfc / mdio_10g.c

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2006-2011 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */
/*
 * Useful functions for working with MDIO clause 45 PHYs
 */
#include <linux/types.h>
#include <linux/ethtool.h>
#include <linux/delay.h>
#include "net_driver.h"
#include "mdio_10g.h"
#include "workarounds.h"

unsigned efx_mdio_id_oui(u32 id)
{
	unsigned oui = 0;
	int i;

	/* The bits of the OUI are designated a..x, with a=0 and b variable.
	 * In the id register c is the MSB but the OUI is conventionally
	 * written as bytes h..a, p..i, x..q.  Reorder the bits accordingly. */
	for (i = 0; i < 22; ++i)
		if (id & (1 << (i + 10)))
			oui |= 1 << (i ^ 7);

	return oui;
}

int efx_mdio_reset_mmd(struct efx_nic *port, int mmd,
			    int spins, int spintime)
{
	u32 ctrl;

	/* Catch callers passing values in the wrong units (or just silly) */
	EFX_BUG_ON_PARANOID(spins * spintime >= 5000);

	efx_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
	/* Wait for the reset bit to clear. */
	do {
		msleep(spintime);
		ctrl = efx_mdio_read(port, mmd, MDIO_CTRL1);
		spins--;

	} while (spins && (ctrl & MDIO_CTRL1_RESET));

	return spins ? spins : -ETIMEDOUT;
}

static int efx_mdio_check_mmd(struct efx_nic *efx, int mmd)
{
	int status;

	if (mmd != MDIO_MMD_AN) {
		/* Read MMD STATUS2 to check it is responding. */
		status = efx_mdio_read(efx, mmd, MDIO_STAT2);
		if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) {
			netif_err(efx, hw, efx->net_dev,
				  "PHY MMD %d not responding.\n", mmd);
			return -EIO;
		}
	}

	return 0;
}

/* This ought to be ridiculous overkill. We expect it to fail rarely */
#define MDIO45_RESET_TIME	1000 /* ms */
#define MDIO45_RESET_ITERS	100

int efx_mdio_wait_reset_mmds(struct efx_nic *efx, unsigned int mmd_mask)
{
	const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
	int tries = MDIO45_RESET_ITERS;
	int rc = 0;
	int in_reset;

	while (tries) {
		int mask = mmd_mask;
		int mmd = 0;
		int stat;
		in_reset = 0;
		while (mask) {
			if (mask & 1) {
				stat = efx_mdio_read(efx, mmd, MDIO_CTRL1);
				if (stat < 0) {
					netif_err(efx, hw, efx->net_dev,
						  "failed to read status of"
						  " MMD %d\n", mmd);
					return -EIO;
				}
				if (stat & MDIO_CTRL1_RESET)
					in_reset |= (1 << mmd);
			}
			mask = mask >> 1;
			mmd++;
		}
		if (!in_reset)
			break;
		tries--;
		msleep(spintime);
	}
	if (in_reset != 0) {
		netif_err(efx, hw, efx->net_dev,
			  "not all MMDs came out of reset in time."
			  " MMDs still in reset: %x\n", in_reset);
		rc = -ETIMEDOUT;
	}
	return rc;
}

int efx_mdio_check_mmds(struct efx_nic *efx, unsigned int mmd_mask)
{
	int mmd = 0, probe_mmd, devs1, devs2;
	u32 devices;

	/* Historically we have probed the PHYXS to find out what devices are
	 * present,but that doesn't work so well if the PHYXS isn't expected
	 * to exist, if so just find the first item in the list supplied. */
	probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
	    __ffs(mmd_mask);

	/* Check all the expected MMDs are present */
	devs1 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS1);
	devs2 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS2);
	if (devs1 < 0 || devs2 < 0) {
		netif_err(efx, hw, efx->net_dev,
			  "failed to read devices present\n");
		return -EIO;
	}
	devices = devs1 | (devs2 << 16);
	if ((devices & mmd_mask) != mmd_mask) {
		netif_err(efx, hw, efx->net_dev,
			  "required MMDs not present: got %x, wanted %x\n",
			  devices, mmd_mask);
		return -ENODEV;
	}
	netif_vdbg(efx, hw, efx->net_dev, "Devices present: %x\n", devices);

	/* Check all required MMDs are responding and happy. */
	while (mmd_mask) {
		if ((mmd_mask & 1) && efx_mdio_check_mmd(efx, mmd))
			return -EIO;
		mmd_mask = mmd_mask >> 1;
		mmd++;
	}

	return 0;
}

bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
{
	/* If the port is in loopback, then we should only consider a subset
	 * of mmd's */
	if (LOOPBACK_INTERNAL(efx))
		return true;
	else if (LOOPBACK_MASK(efx) & LOOPBACKS_WS)
		return false;
	else if (efx_phy_mode_disabled(efx->phy_mode))
		return false;
	else if (efx->loopback_mode == LOOPBACK_PHYXS)
		mmd_mask &= ~(MDIO_DEVS_PHYXS |
			      MDIO_DEVS_PCS |
			      MDIO_DEVS_PMAPMD |
			      MDIO_DEVS_AN);
	else if (efx->loopback_mode == LOOPBACK_PCS)
		mmd_mask &= ~(MDIO_DEVS_PCS |
			      MDIO_DEVS_PMAPMD |
			      MDIO_DEVS_AN);
	else if (efx->loopback_mode == LOOPBACK_PMAPMD)
		mmd_mask &= ~(MDIO_DEVS_PMAPMD |
			      MDIO_DEVS_AN);

	return mdio45_links_ok(&efx->mdio, mmd_mask);
}

void efx_mdio_transmit_disable(struct efx_nic *efx)
{
	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
			  MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL,
			  efx->phy_mode & PHY_MODE_TX_DISABLED);
}

void efx_mdio_phy_reconfigure(struct efx_nic *efx)
{
	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
			  MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
			  efx->loopback_mode == LOOPBACK_PMAPMD);
	efx_mdio_set_flag(efx, MDIO_MMD_PCS,
			  MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
			  efx->loopback_mode == LOOPBACK_PCS);
	efx_mdio_set_flag(efx, MDIO_MMD_PHYXS,
			  MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
			  efx->loopback_mode == LOOPBACK_PHYXS_WS);
}

static void efx_mdio_set_mmd_lpower(struct efx_nic *efx,
				    int lpower, int mmd)
{
	int stat = efx_mdio_read(efx, mmd, MDIO_STAT1);

	netif_vdbg(efx, drv, efx->net_dev, "Setting low power mode for MMD %d to %d\n",
		  mmd, lpower);

	if (stat & MDIO_STAT1_LPOWERABLE) {
		efx_mdio_set_flag(efx, mmd, MDIO_CTRL1,
				  MDIO_CTRL1_LPOWER, lpower);
	}
}

void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
			      int low_power, unsigned int mmd_mask)
{
	int mmd = 0;
	mmd_mask &= ~MDIO_DEVS_AN;
	while (mmd_mask) {
		if (mmd_mask & 1)
			efx_mdio_set_mmd_lpower(efx, low_power, mmd);
		mmd_mask = (mmd_mask >> 1);
		mmd++;
	}
}

/**
 * efx_mdio_set_settings - Set (some of) the PHY settings over MDIO.
 * @efx:		Efx NIC
 * @ecmd: 		New settings
 */
int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
{
	struct ethtool_cmd prev = { .cmd = ETHTOOL_GSET };

	efx->phy_op->get_settings(efx, &prev);

	if (ecmd->advertising == prev.advertising &&
	    ethtool_cmd_speed(ecmd) == ethtool_cmd_speed(&prev) &&
	    ecmd->duplex == prev.duplex &&
	    ecmd->port == prev.port &&
	    ecmd->autoneg == prev.autoneg)
		return 0;

	/* We can only change these settings for -T PHYs */
	if (prev.port != PORT_TP || ecmd->port != PORT_TP)
		return -EINVAL;

	/* Check that PHY supports these settings */
	if (!ecmd->autoneg ||
	    (ecmd->advertising | SUPPORTED_Autoneg) & ~prev.supported)
		return -EINVAL;

	efx_link_set_advertising(efx, ecmd->advertising | ADVERTISED_Autoneg);
	efx_mdio_an_reconfigure(efx);
	return 0;
}

/**
 * efx_mdio_an_reconfigure - Push advertising flags and restart autonegotiation
 * @efx:		Efx NIC
 */
void efx_mdio_an_reconfigure(struct efx_nic *efx)
{
	int reg;

	WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN));

	/* Set up the base page */
	reg = ADVERTISE_CSMA | ADVERTISE_RESV;
	if (efx->link_advertising & ADVERTISED_Pause)
		reg |= ADVERTISE_PAUSE_CAP;
	if (efx->link_advertising & ADVERTISED_Asym_Pause)
		reg |= ADVERTISE_PAUSE_ASYM;
	efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);

	/* Set up the (extended) next page */
	efx->phy_op->set_npage_adv(efx, efx->link_advertising);

	/* Enable and restart AN */
	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
	reg |= MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART | MDIO_AN_CTRL1_XNP;
	efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
}

enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx)
{
	BUILD_BUG_ON(EFX_FC_AUTO & (EFX_FC_RX | EFX_FC_TX));

	if (!(efx->wanted_fc & EFX_FC_AUTO))
		return efx->wanted_fc;

	WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN));

	return mii_resolve_flowctrl_fdx(
		mii_advertise_flowctrl(efx->wanted_fc),
		efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA));
}

int efx_mdio_test_alive(struct efx_nic *efx)
{
	int rc;
	int devad = __ffs(efx->mdio.mmds);
	u16 physid1, physid2;

	mutex_lock(&efx->mac_lock);

	physid1 = efx_mdio_read(efx, devad, MDIO_DEVID1);
	physid2 = efx_mdio_read(efx, devad, MDIO_DEVID2);

	if ((physid1 == 0x0000) || (physid1 == 0xffff) ||
	    (physid2 == 0x0000) || (physid2 == 0xffff)) {
		netif_err(efx, hw, efx->net_dev,
			  "no MDIO PHY present with ID %d\n", efx->mdio.prtad);
		rc = -EINVAL;
	} else {
		rc = efx_mdio_check_mmds(efx, efx->mdio.mmds);
	}

	mutex_unlock(&efx->mac_lock);
	return rc;
}
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
8ceee660 BH	2	* Driver for Solarflare Solarstorm network controllers and boards
0a6f40c6	3	* Copyright 2006-2011 Solarflare Communications Inc.
8ceee660 BH	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9	/*
	10	* Useful functions for working with MDIO clause 45 PHYs
	11	*/
	12	#include <linux/types.h>
	13	#include <linux/ethtool.h>
	14	#include <linux/delay.h>
	15	#include "net_driver.h"
	16	#include "mdio_10g.h"
8b9dc8dd	17	#include "workarounds.h"
8ceee660	18
68e7f45e	19	unsigned efx_mdio_id_oui(u32 id)
3f39a5e9 BH	20	{
	21	unsigned oui = 0;
	22	int i;
	23
	24	/* The bits of the OUI are designated a..x, with a=0 and b variable.
	25	* In the id register c is the MSB but the OUI is conventionally
	26	* written as bytes h..a, p..i, x..q. Reorder the bits accordingly. */
	27	for (i = 0; i < 22; ++i)
	28	if (id & (1 << (i + 10)))
	29	oui \|= 1 << (i ^ 7);
	30
	31	return oui;
	32	}
	33
68e7f45e	34	int efx_mdio_reset_mmd(struct efx_nic *port, int mmd,
8ceee660 BH	35	int spins, int spintime)
	36	{
	37	u32 ctrl;
8ceee660 BH	38
	39	/* Catch callers passing values in the wrong units (or just silly) */
	40	EFX_BUG_ON_PARANOID(spins * spintime >= 5000);
	41
68e7f45e	42	efx_mdio_write(port, mmd, MDIO_CTRL1, MDIO_CTRL1_RESET);
8ceee660 BH	43	/* Wait for the reset bit to clear. */
	44	do {
	45	msleep(spintime);
68e7f45e	46	ctrl = efx_mdio_read(port, mmd, MDIO_CTRL1);
8ceee660 BH	47	spins--;
8ceee660 BH	48
68e7f45e	49	} while (spins && (ctrl & MDIO_CTRL1_RESET));
8ceee660 BH	50
	51	return spins ? spins : -ETIMEDOUT;
	52	}
	53
a461103b	54	static int efx_mdio_check_mmd(struct efx_nic *efx, int mmd)
8ceee660 BH	55	{
8ceee660 BH	56	int status;
8ceee660	57
04cc8cac BH	58	if (mmd != MDIO_MMD_AN) {
04cc8cac BH	59	/* Read MMD STATUS2 to check it is responding. */
68e7f45e BH	60	status = efx_mdio_read(efx, mmd, MDIO_STAT2);
68e7f45e BH	61	if ((status & MDIO_STAT2_DEVPRST) != MDIO_STAT2_DEVPRST_VAL) {
62776d03 BH	62	netif_err(efx, hw, efx->net_dev,
62776d03 BH	63	"PHY MMD %d not responding.\n", mmd);
04cc8cac BH	64	return -EIO;
04cc8cac BH	65	}
8ceee660 BH	66	}
8ceee660 BH	67
8ceee660 BH	68	return 0;
	69	}
	70
	71	/* This ought to be ridiculous overkill. We expect it to fail rarely */
	72	#define MDIO45_RESET_TIME 1000 /* ms */
	73	#define MDIO45_RESET_ITERS 100
	74
68e7f45e	75	int efx_mdio_wait_reset_mmds(struct efx_nic *efx, unsigned int mmd_mask)
8ceee660 BH	76	{
	77	const int spintime = MDIO45_RESET_TIME / MDIO45_RESET_ITERS;
	78	int tries = MDIO45_RESET_ITERS;
	79	int rc = 0;
	80	int in_reset;
	81
	82	while (tries) {
	83	int mask = mmd_mask;
	84	int mmd = 0;
	85	int stat;
	86	in_reset = 0;
	87	while (mask) {
	88	if (mask & 1) {
68e7f45e	89	stat = efx_mdio_read(efx, mmd, MDIO_CTRL1);
8ceee660	90	if (stat < 0) {
62776d03 BH	91	netif_err(efx, hw, efx->net_dev,
	92	"failed to read status of"
	93	" MMD %d\n", mmd);
8ceee660 BH	94	return -EIO;
8ceee660 BH	95	}
68e7f45e	96	if (stat & MDIO_CTRL1_RESET)
8ceee660 BH	97	in_reset \|= (1 << mmd);
	98	}
	99	mask = mask >> 1;
	100	mmd++;
	101	}
	102	if (!in_reset)
	103	break;
	104	tries--;
	105	msleep(spintime);
	106	}
	107	if (in_reset != 0) {
62776d03 BH	108	netif_err(efx, hw, efx->net_dev,
	109	"not all MMDs came out of reset in time."
	110	" MMDs still in reset: %x\n", in_reset);
8ceee660 BH	111	rc = -ETIMEDOUT;
	112	}
	113	return rc;
	114	}
	115
a461103b	116	int efx_mdio_check_mmds(struct efx_nic *efx, unsigned int mmd_mask)
8ceee660	117	{
68e7f45e	118	int mmd = 0, probe_mmd, devs1, devs2;
27dd2cac	119	u32 devices;
8ceee660 BH	120
	121	/* Historically we have probed the PHYXS to find out what devices are
	122	* present,but that doesn't work so well if the PHYXS isn't expected
	123	* to exist, if so just find the first item in the list supplied. */
68e7f45e	124	probe_mmd = (mmd_mask & MDIO_DEVS_PHYXS) ? MDIO_MMD_PHYXS :
8ceee660	125	__ffs(mmd_mask);
8ceee660 BH	126
8ceee660 BH	127	/* Check all the expected MMDs are present */
68e7f45e BH	128	devs1 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS1);
	129	devs2 = efx_mdio_read(efx, probe_mmd, MDIO_DEVS2);
	130	if (devs1 < 0 \|\| devs2 < 0) {
62776d03 BH	131	netif_err(efx, hw, efx->net_dev,
62776d03 BH	132	"failed to read devices present\n");
8ceee660 BH	133	return -EIO;
8ceee660 BH	134	}
68e7f45e	135	devices = devs1 \| (devs2 << 16);
8ceee660	136	if ((devices & mmd_mask) != mmd_mask) {
62776d03 BH	137	netif_err(efx, hw, efx->net_dev,
	138	"required MMDs not present: got %x, wanted %x\n",
	139	devices, mmd_mask);
8ceee660 BH	140	return -ENODEV;
8ceee660 BH	141	}
62776d03	142	netif_vdbg(efx, hw, efx->net_dev, "Devices present: %x\n", devices);
8ceee660 BH	143
	144	/* Check all required MMDs are responding and happy. */
	145	while (mmd_mask) {
a461103b BH	146	if ((mmd_mask & 1) && efx_mdio_check_mmd(efx, mmd))
a461103b BH	147	return -EIO;
8ceee660	148	mmd_mask = mmd_mask >> 1;
8ceee660 BH	149	mmd++;
	150	}
	151
	152	return 0;
	153	}
	154
68e7f45e	155	bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask)
8ceee660	156	{
3273c2e8 BH	157	/* If the port is in loopback, then we should only consider a subset
	158	* of mmd's */
	159	if (LOOPBACK_INTERNAL(efx))
dc8cfa55	160	return true;
e58f69f4	161	else if (LOOPBACK_MASK(efx) & LOOPBACKS_WS)
dc8cfa55	162	return false;
f8b87c17 BH	163	else if (efx_phy_mode_disabled(efx->phy_mode))
f8b87c17 BH	164	return false;
67797763	165	else if (efx->loopback_mode == LOOPBACK_PHYXS)
68e7f45e BH	166	mmd_mask &= ~(MDIO_DEVS_PHYXS \|
	167	MDIO_DEVS_PCS \|
	168	MDIO_DEVS_PMAPMD \|
	169	MDIO_DEVS_AN);
67797763	170	else if (efx->loopback_mode == LOOPBACK_PCS)
68e7f45e BH	171	mmd_mask &= ~(MDIO_DEVS_PCS \|
	172	MDIO_DEVS_PMAPMD \|
	173	MDIO_DEVS_AN);
3273c2e8	174	else if (efx->loopback_mode == LOOPBACK_PMAPMD)
68e7f45e BH	175	mmd_mask &= ~(MDIO_DEVS_PMAPMD \|
68e7f45e BH	176	MDIO_DEVS_AN);
67797763	177
68e7f45e	178	return mdio45_links_ok(&efx->mdio, mmd_mask);
8ceee660 BH	179	}
8ceee660 BH	180
68e7f45e	181	void efx_mdio_transmit_disable(struct efx_nic *efx)
3273c2e8	182	{
68e7f45e BH	183	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
	184	MDIO_PMA_TXDIS, MDIO_PMD_TXDIS_GLOBAL,
	185	efx->phy_mode & PHY_MODE_TX_DISABLED);
3273c2e8 BH	186	}
3273c2e8 BH	187
68e7f45e	188	void efx_mdio_phy_reconfigure(struct efx_nic *efx)
3273c2e8	189	{
68e7f45e BH	190	efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD,
	191	MDIO_CTRL1, MDIO_PMA_CTRL1_LOOPBACK,
	192	efx->loopback_mode == LOOPBACK_PMAPMD);
	193	efx_mdio_set_flag(efx, MDIO_MMD_PCS,
	194	MDIO_CTRL1, MDIO_PCS_CTRL1_LOOPBACK,
	195	efx->loopback_mode == LOOPBACK_PCS);
	196	efx_mdio_set_flag(efx, MDIO_MMD_PHYXS,
	197	MDIO_CTRL1, MDIO_PHYXS_CTRL1_LOOPBACK,
e58f69f4	198	efx->loopback_mode == LOOPBACK_PHYXS_WS);
3273c2e8 BH	199	}
3273c2e8 BH	200
68e7f45e BH	201	static void efx_mdio_set_mmd_lpower(struct efx_nic *efx,
68e7f45e BH	202	int lpower, int mmd)
3e133c44	203	{
68e7f45e	204	int stat = efx_mdio_read(efx, mmd, MDIO_STAT1);
3e133c44	205
62776d03	206	netif_vdbg(efx, drv, efx->net_dev, "Setting low power mode for MMD %d to %d\n",
3e133c44 BH	207	mmd, lpower);
3e133c44 BH	208
68e7f45e BH	209	if (stat & MDIO_STAT1_LPOWERABLE) {
	210	efx_mdio_set_flag(efx, mmd, MDIO_CTRL1,
	211	MDIO_CTRL1_LPOWER, lpower);
3e133c44 BH	212	}
	213	}
	214
68e7f45e BH	215	void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
68e7f45e BH	216	int low_power, unsigned int mmd_mask)
3e133c44 BH	217	{
3e133c44 BH	218	int mmd = 0;
68e7f45e	219	mmd_mask &= ~MDIO_DEVS_AN;
3e133c44 BH	220	while (mmd_mask) {
3e133c44 BH	221	if (mmd_mask & 1)
68e7f45e	222	efx_mdio_set_mmd_lpower(efx, low_power, mmd);
3e133c44 BH	223	mmd_mask = (mmd_mask >> 1);
	224	mmd++;
	225	}
	226	}
	227
04cc8cac	228	/**
68e7f45e	229	* efx_mdio_set_settings - Set (some of) the PHY settings over MDIO.
8ceee660 BH	230	* @efx: Efx NIC
8ceee660 BH	231	* @ecmd: New settings
8ceee660	232	*/
68e7f45e	233	int efx_mdio_set_settings(struct efx_nic efx, struct ethtool_cmd ecmd)
8ceee660	234	{
8ae6daca	235	struct ethtool_cmd prev = { .cmd = ETHTOOL_GSET };
04cc8cac BH	236
	237	efx->phy_op->get_settings(efx, &prev);
	238
	239	if (ecmd->advertising == prev.advertising &&
8ae6daca	240	ethtool_cmd_speed(ecmd) == ethtool_cmd_speed(&prev) &&
04cc8cac BH	241	ecmd->duplex == prev.duplex &&
	242	ecmd->port == prev.port &&
	243	ecmd->autoneg == prev.autoneg)
8ceee660	244	return 0;
04cc8cac BH	245
	246	/* We can only change these settings for -T PHYs */
	247	if (prev.port != PORT_TP \|\| ecmd->port != PORT_TP)
	248	return -EINVAL;
	249
af4ad9bc	250	/* Check that PHY supports these settings */
fc2b5e67 BH	251	if (!ecmd->autoneg \|\|
fc2b5e67 BH	252	(ecmd->advertising \| SUPPORTED_Autoneg) & ~prev.supported)
04cc8cac BH	253	return -EINVAL;
04cc8cac BH	254
d3245b28 BH	255	efx_link_set_advertising(efx, ecmd->advertising \| ADVERTISED_Autoneg);
	256	efx_mdio_an_reconfigure(efx);
	257	return 0;
	258	}
	259
	260	/**
	261	* efx_mdio_an_reconfigure - Push advertising flags and restart autonegotiation
	262	* @efx: Efx NIC
	263	*/
	264	void efx_mdio_an_reconfigure(struct efx_nic *efx)
	265	{
d3245b28 BH	266	int reg;
	267
	268	WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN));
fc2b5e67 BH	269
fc2b5e67 BH	270	/* Set up the base page */
8fbca791	271	reg = ADVERTISE_CSMA \| ADVERTISE_RESV;
d3245b28 BH	272	if (efx->link_advertising & ADVERTISED_Pause)
	273	reg \|= ADVERTISE_PAUSE_CAP;
	274	if (efx->link_advertising & ADVERTISED_Asym_Pause)
	275	reg \|= ADVERTISE_PAUSE_ASYM;
fc2b5e67 BH	276	efx_mdio_write(efx, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
fc2b5e67 BH	277
8fbca791 BH	278	/* Set up the (extended) next page */
8fbca791 BH	279	efx->phy_op->set_npage_adv(efx, efx->link_advertising);
fc2b5e67 BH	280
	281	/* Enable and restart AN */
	282	reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_CTRL1);
8fbca791	283	reg \|= MDIO_AN_CTRL1_ENABLE \| MDIO_AN_CTRL1_RESTART \| MDIO_AN_CTRL1_XNP;
fc2b5e67	284	efx_mdio_write(efx, MDIO_MMD_AN, MDIO_CTRL1, reg);
04cc8cac BH	285	}
04cc8cac BH	286
68e7f45e	287	enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx)
04cc8cac	288	{
18ea024f	289	BUILD_BUG_ON(EFX_FC_AUTO & (EFX_FC_RX \| EFX_FC_TX));
04cc8cac	290
18ea024f	291	if (!(efx->wanted_fc & EFX_FC_AUTO))
04cc8cac	292	return efx->wanted_fc;
18ea024f BH	293
	294	WARN_ON(!(efx->mdio.mmds & MDIO_DEVS_AN));
	295
	296	return mii_resolve_flowctrl_fdx(
	297	mii_advertise_flowctrl(efx->wanted_fc),
	298	efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_LPA));
8ceee660	299	}
4f16c073 BH	300
	301	int efx_mdio_test_alive(struct efx_nic *efx)
	302	{
	303	int rc;
	304	int devad = __ffs(efx->mdio.mmds);
	305	u16 physid1, physid2;
	306
	307	mutex_lock(&efx->mac_lock);
	308
	309	physid1 = efx_mdio_read(efx, devad, MDIO_DEVID1);
	310	physid2 = efx_mdio_read(efx, devad, MDIO_DEVID2);
	311
	312	if ((physid1 == 0x0000) \|\| (physid1 == 0xffff) \|\|
	313	(physid2 == 0x0000) \|\| (physid2 == 0xffff)) {
62776d03 BH	314	netif_err(efx, hw, efx->net_dev,
62776d03 BH	315	"no MDIO PHY present with ID %d\n", efx->mdio.prtad);
4f16c073 BH	316	rc = -EINVAL;
4f16c073 BH	317	} else {
a461103b	318	rc = efx_mdio_check_mmds(efx, efx->mdio.mmds);
4f16c073 BH	319	}
	320
	321	mutex_unlock(&efx->mac_lock);
	322	return rc;
	323	}