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1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
16 | #include <linux/version.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/etherdevice.h> | |
19 | #include <linux/ethtool.h> | |
20 | #include <linux/if_vlan.h> | |
21 | #include <linux/timer.h> | |
22 | #include <linux/mii.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/pci.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/highmem.h> | |
27 | #include <linux/workqueue.h> | |
28 | #include <linux/inet_lro.h> | |
37b5a603 | 29 | #include <linux/i2c.h> |
8ceee660 BH |
30 | |
31 | #include "enum.h" | |
32 | #include "bitfield.h" | |
8ceee660 BH |
33 | |
34 | #define EFX_MAX_LRO_DESCRIPTORS 8 | |
35 | #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS | |
36 | ||
37 | /************************************************************************** | |
38 | * | |
39 | * Build definitions | |
40 | * | |
41 | **************************************************************************/ | |
42 | #ifndef EFX_DRIVER_NAME | |
43 | #define EFX_DRIVER_NAME "sfc" | |
44 | #endif | |
8757a5f7 | 45 | #define EFX_DRIVER_VERSION "2.2" |
8ceee660 BH |
46 | |
47 | #ifdef EFX_ENABLE_DEBUG | |
48 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) | |
49 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
50 | #else | |
51 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
52 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
53 | #endif | |
54 | ||
8ceee660 BH |
55 | /* Un-rate-limited logging */ |
56 | #define EFX_ERR(efx, fmt, args...) \ | |
55668611 | 57 | dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
58 | |
59 | #define EFX_INFO(efx, fmt, args...) \ | |
55668611 | 60 | dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
61 | |
62 | #ifdef EFX_ENABLE_DEBUG | |
63 | #define EFX_LOG(efx, fmt, args...) \ | |
55668611 | 64 | dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
65 | #else |
66 | #define EFX_LOG(efx, fmt, args...) \ | |
55668611 | 67 | dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
68 | #endif |
69 | ||
70 | #define EFX_TRACE(efx, fmt, args...) do {} while (0) | |
71 | ||
72 | #define EFX_REGDUMP(efx, fmt, args...) do {} while (0) | |
73 | ||
74 | /* Rate-limited logging */ | |
75 | #define EFX_ERR_RL(efx, fmt, args...) \ | |
76 | do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0) | |
77 | ||
78 | #define EFX_INFO_RL(efx, fmt, args...) \ | |
79 | do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0) | |
80 | ||
81 | #define EFX_LOG_RL(efx, fmt, args...) \ | |
82 | do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0) | |
83 | ||
8ceee660 BH |
84 | /************************************************************************** |
85 | * | |
86 | * Efx data structures | |
87 | * | |
88 | **************************************************************************/ | |
89 | ||
90 | #define EFX_MAX_CHANNELS 32 | |
8ceee660 BH |
91 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
92 | ||
60ac1065 BH |
93 | #define EFX_TX_QUEUE_OFFLOAD_CSUM 0 |
94 | #define EFX_TX_QUEUE_NO_CSUM 1 | |
95 | #define EFX_TX_QUEUE_COUNT 2 | |
96 | ||
8ceee660 BH |
97 | /** |
98 | * struct efx_special_buffer - An Efx special buffer | |
99 | * @addr: CPU base address of the buffer | |
100 | * @dma_addr: DMA base address of the buffer | |
101 | * @len: Buffer length, in bytes | |
102 | * @index: Buffer index within controller;s buffer table | |
103 | * @entries: Number of buffer table entries | |
104 | * | |
105 | * Special buffers are used for the event queues and the TX and RX | |
106 | * descriptor queues for each channel. They are *not* used for the | |
107 | * actual transmit and receive buffers. | |
108 | * | |
109 | * Note that for Falcon, TX and RX descriptor queues live in host memory. | |
110 | * Allocation and freeing procedures must take this into account. | |
111 | */ | |
112 | struct efx_special_buffer { | |
113 | void *addr; | |
114 | dma_addr_t dma_addr; | |
115 | unsigned int len; | |
116 | int index; | |
117 | int entries; | |
118 | }; | |
119 | ||
120 | /** | |
121 | * struct efx_tx_buffer - An Efx TX buffer | |
122 | * @skb: The associated socket buffer. | |
123 | * Set only on the final fragment of a packet; %NULL for all other | |
124 | * fragments. When this fragment completes, then we can free this | |
125 | * skb. | |
b9b39b62 BH |
126 | * @tsoh: The associated TSO header structure, or %NULL if this |
127 | * buffer is not a TSO header. | |
8ceee660 BH |
128 | * @dma_addr: DMA address of the fragment. |
129 | * @len: Length of this fragment. | |
130 | * This field is zero when the queue slot is empty. | |
131 | * @continuation: True if this fragment is not the end of a packet. | |
132 | * @unmap_single: True if pci_unmap_single should be used. | |
8ceee660 BH |
133 | * @unmap_len: Length of this fragment to unmap |
134 | */ | |
135 | struct efx_tx_buffer { | |
136 | const struct sk_buff *skb; | |
b9b39b62 | 137 | struct efx_tso_header *tsoh; |
8ceee660 BH |
138 | dma_addr_t dma_addr; |
139 | unsigned short len; | |
dc8cfa55 BH |
140 | bool continuation; |
141 | bool unmap_single; | |
8ceee660 BH |
142 | unsigned short unmap_len; |
143 | }; | |
144 | ||
145 | /** | |
146 | * struct efx_tx_queue - An Efx TX queue | |
147 | * | |
148 | * This is a ring buffer of TX fragments. | |
149 | * Since the TX completion path always executes on the same | |
150 | * CPU and the xmit path can operate on different CPUs, | |
151 | * performance is increased by ensuring that the completion | |
152 | * path and the xmit path operate on different cache lines. | |
153 | * This is particularly important if the xmit path is always | |
154 | * executing on one CPU which is different from the completion | |
155 | * path. There is also a cache line for members which are | |
156 | * read but not written on the fast path. | |
157 | * | |
158 | * @efx: The associated Efx NIC | |
159 | * @queue: DMA queue number | |
8ceee660 BH |
160 | * @channel: The associated channel |
161 | * @buffer: The software buffer ring | |
162 | * @txd: The hardware descriptor ring | |
6bc5d3a9 | 163 | * @flushed: Used when handling queue flushing |
8ceee660 BH |
164 | * @read_count: Current read pointer. |
165 | * This is the number of buffers that have been removed from both rings. | |
dc8cfa55 | 166 | * @stopped: Stopped count. |
8ceee660 BH |
167 | * Set if this TX queue is currently stopping its port. |
168 | * @insert_count: Current insert pointer | |
169 | * This is the number of buffers that have been added to the | |
170 | * software ring. | |
171 | * @write_count: Current write pointer | |
172 | * This is the number of buffers that have been added to the | |
173 | * hardware ring. | |
174 | * @old_read_count: The value of read_count when last checked. | |
175 | * This is here for performance reasons. The xmit path will | |
176 | * only get the up-to-date value of read_count if this | |
177 | * variable indicates that the queue is full. This is to | |
178 | * avoid cache-line ping-pong between the xmit path and the | |
179 | * completion path. | |
b9b39b62 BH |
180 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
181 | * that are not in use, and so available for new TSO sends. The list | |
182 | * is protected by the TX queue lock. | |
183 | * @tso_bursts: Number of times TSO xmit invoked by kernel | |
184 | * @tso_long_headers: Number of packets with headers too long for standard | |
185 | * blocks | |
186 | * @tso_packets: Number of packets via the TSO xmit path | |
8ceee660 BH |
187 | */ |
188 | struct efx_tx_queue { | |
189 | /* Members which don't change on the fast path */ | |
190 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
191 | int queue; | |
8ceee660 BH |
192 | struct efx_channel *channel; |
193 | struct efx_nic *nic; | |
194 | struct efx_tx_buffer *buffer; | |
195 | struct efx_special_buffer txd; | |
6bc5d3a9 | 196 | bool flushed; |
8ceee660 BH |
197 | |
198 | /* Members used mainly on the completion path */ | |
199 | unsigned int read_count ____cacheline_aligned_in_smp; | |
200 | int stopped; | |
201 | ||
202 | /* Members used only on the xmit path */ | |
203 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
204 | unsigned int write_count; | |
205 | unsigned int old_read_count; | |
b9b39b62 BH |
206 | struct efx_tso_header *tso_headers_free; |
207 | unsigned int tso_bursts; | |
208 | unsigned int tso_long_headers; | |
209 | unsigned int tso_packets; | |
8ceee660 BH |
210 | }; |
211 | ||
212 | /** | |
213 | * struct efx_rx_buffer - An Efx RX data buffer | |
214 | * @dma_addr: DMA base address of the buffer | |
215 | * @skb: The associated socket buffer, if any. | |
216 | * If both this and page are %NULL, the buffer slot is currently free. | |
217 | * @page: The associated page buffer, if any. | |
218 | * If both this and skb are %NULL, the buffer slot is currently free. | |
219 | * @data: Pointer to ethernet header | |
220 | * @len: Buffer length, in bytes. | |
221 | * @unmap_addr: DMA address to unmap | |
222 | */ | |
223 | struct efx_rx_buffer { | |
224 | dma_addr_t dma_addr; | |
225 | struct sk_buff *skb; | |
226 | struct page *page; | |
227 | char *data; | |
228 | unsigned int len; | |
229 | dma_addr_t unmap_addr; | |
230 | }; | |
231 | ||
232 | /** | |
233 | * struct efx_rx_queue - An Efx RX queue | |
234 | * @efx: The associated Efx NIC | |
235 | * @queue: DMA queue number | |
8ceee660 BH |
236 | * @channel: The associated channel |
237 | * @buffer: The software buffer ring | |
238 | * @rxd: The hardware descriptor ring | |
239 | * @added_count: Number of buffers added to the receive queue. | |
240 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
241 | * @removed_count: Number of buffers removed from the receive queue. | |
242 | * @add_lock: Receive queue descriptor add spin lock. | |
243 | * This lock must be held in order to add buffers to the RX | |
244 | * descriptor ring (rxd and buffer) and to update added_count (but | |
245 | * not removed_count). | |
246 | * @max_fill: RX descriptor maximum fill level (<= ring size) | |
247 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
248 | * (<= @max_fill) | |
249 | * @fast_fill_limit: The level to which a fast fill will fill | |
250 | * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) | |
251 | * @min_fill: RX descriptor minimum non-zero fill level. | |
252 | * This records the minimum fill level observed when a ring | |
253 | * refill was triggered. | |
254 | * @min_overfill: RX descriptor minimum overflow fill level. | |
255 | * This records the minimum fill level at which RX queue | |
256 | * overflow was observed. It should never be set. | |
257 | * @alloc_page_count: RX allocation strategy counter. | |
258 | * @alloc_skb_count: RX allocation strategy counter. | |
259 | * @work: Descriptor push work thread | |
260 | * @buf_page: Page for next RX buffer. | |
261 | * We can use a single page for multiple RX buffers. This tracks | |
262 | * the remaining space in the allocation. | |
263 | * @buf_dma_addr: Page's DMA address. | |
264 | * @buf_data: Page's host address. | |
6bc5d3a9 | 265 | * @flushed: Use when handling queue flushing |
8ceee660 BH |
266 | */ |
267 | struct efx_rx_queue { | |
268 | struct efx_nic *efx; | |
269 | int queue; | |
8ceee660 BH |
270 | struct efx_channel *channel; |
271 | struct efx_rx_buffer *buffer; | |
272 | struct efx_special_buffer rxd; | |
273 | ||
274 | int added_count; | |
275 | int notified_count; | |
276 | int removed_count; | |
277 | spinlock_t add_lock; | |
278 | unsigned int max_fill; | |
279 | unsigned int fast_fill_trigger; | |
280 | unsigned int fast_fill_limit; | |
281 | unsigned int min_fill; | |
282 | unsigned int min_overfill; | |
283 | unsigned int alloc_page_count; | |
284 | unsigned int alloc_skb_count; | |
285 | struct delayed_work work; | |
286 | unsigned int slow_fill_count; | |
287 | ||
288 | struct page *buf_page; | |
289 | dma_addr_t buf_dma_addr; | |
290 | char *buf_data; | |
6bc5d3a9 | 291 | bool flushed; |
8ceee660 BH |
292 | }; |
293 | ||
294 | /** | |
295 | * struct efx_buffer - An Efx general-purpose buffer | |
296 | * @addr: host base address of the buffer | |
297 | * @dma_addr: DMA base address of the buffer | |
298 | * @len: Buffer length, in bytes | |
299 | * | |
300 | * Falcon uses these buffers for its interrupt status registers and | |
301 | * MAC stats dumps. | |
302 | */ | |
303 | struct efx_buffer { | |
304 | void *addr; | |
305 | dma_addr_t dma_addr; | |
306 | unsigned int len; | |
307 | }; | |
308 | ||
309 | ||
310 | /* Flags for channel->used_flags */ | |
311 | #define EFX_USED_BY_RX 1 | |
312 | #define EFX_USED_BY_TX 2 | |
313 | #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX) | |
314 | ||
315 | enum efx_rx_alloc_method { | |
316 | RX_ALLOC_METHOD_AUTO = 0, | |
317 | RX_ALLOC_METHOD_SKB = 1, | |
318 | RX_ALLOC_METHOD_PAGE = 2, | |
319 | }; | |
320 | ||
321 | /** | |
322 | * struct efx_channel - An Efx channel | |
323 | * | |
324 | * A channel comprises an event queue, at least one TX queue, at least | |
325 | * one RX queue, and an associated tasklet for processing the event | |
326 | * queue. | |
327 | * | |
328 | * @efx: Associated Efx NIC | |
8ceee660 | 329 | * @channel: Channel instance number |
56536e9c | 330 | * @name: Name for channel and IRQ |
8ceee660 BH |
331 | * @used_flags: Channel is used by net driver |
332 | * @enabled: Channel enabled indicator | |
333 | * @irq: IRQ number (MSI and MSI-X only) | |
8ceee660 BH |
334 | * @irq_moderation: IRQ moderation value (in us) |
335 | * @napi_dev: Net device used with NAPI | |
336 | * @napi_str: NAPI control structure | |
337 | * @reset_work: Scheduled reset work thread | |
338 | * @work_pending: Is work pending via NAPI? | |
339 | * @eventq: Event queue buffer | |
340 | * @eventq_read_ptr: Event queue read pointer | |
341 | * @last_eventq_read_ptr: Last event queue read pointer value. | |
342 | * @eventq_magic: Event queue magic value for driver-generated test events | |
343 | * @lro_mgr: LRO state | |
344 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors | |
345 | * and diagnostic counters | |
346 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing | |
347 | * descriptors | |
348 | * @rx_alloc_pop_pages: RX allocation method currently in use for popping | |
349 | * descriptors | |
350 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors | |
351 | * @n_rx_ip_frag_err: Count of RX IP fragment errors | |
352 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors | |
353 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
354 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors | |
355 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
356 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
357 | */ | |
358 | struct efx_channel { | |
359 | struct efx_nic *efx; | |
8ceee660 | 360 | int channel; |
56536e9c | 361 | char name[IFNAMSIZ + 6]; |
8ceee660 | 362 | int used_flags; |
dc8cfa55 | 363 | bool enabled; |
8ceee660 | 364 | int irq; |
8ceee660 BH |
365 | unsigned int irq_moderation; |
366 | struct net_device *napi_dev; | |
367 | struct napi_struct napi_str; | |
dc8cfa55 | 368 | bool work_pending; |
8ceee660 BH |
369 | struct efx_special_buffer eventq; |
370 | unsigned int eventq_read_ptr; | |
371 | unsigned int last_eventq_read_ptr; | |
372 | unsigned int eventq_magic; | |
373 | ||
374 | struct net_lro_mgr lro_mgr; | |
375 | int rx_alloc_level; | |
376 | int rx_alloc_push_pages; | |
377 | int rx_alloc_pop_pages; | |
378 | ||
379 | unsigned n_rx_tobe_disc; | |
380 | unsigned n_rx_ip_frag_err; | |
381 | unsigned n_rx_ip_hdr_chksum_err; | |
382 | unsigned n_rx_tcp_udp_chksum_err; | |
383 | unsigned n_rx_frm_trunc; | |
384 | unsigned n_rx_overlength; | |
385 | unsigned n_skbuff_leaks; | |
386 | ||
387 | /* Used to pipeline received packets in order to optimise memory | |
388 | * access with prefetches. | |
389 | */ | |
390 | struct efx_rx_buffer *rx_pkt; | |
dc8cfa55 | 391 | bool rx_pkt_csummed; |
8ceee660 BH |
392 | |
393 | }; | |
394 | ||
395 | /** | |
396 | * struct efx_blinker - S/W LED blinking context | |
397 | * @led_num: LED ID (board-specific meaning) | |
398 | * @state: Current state - on or off | |
399 | * @resubmit: Timer resubmission flag | |
400 | * @timer: Control timer for blinking | |
401 | */ | |
402 | struct efx_blinker { | |
403 | int led_num; | |
dc8cfa55 BH |
404 | bool state; |
405 | bool resubmit; | |
8ceee660 BH |
406 | struct timer_list timer; |
407 | }; | |
408 | ||
409 | ||
410 | /** | |
411 | * struct efx_board - board information | |
412 | * @type: Board model type | |
413 | * @major: Major rev. ('A', 'B' ...) | |
414 | * @minor: Minor rev. (0, 1, ...) | |
415 | * @init: Initialisation function | |
416 | * @init_leds: Sets up board LEDs | |
417 | * @set_fault_led: Turns the fault LED on or off | |
418 | * @blink: Starts/stops blinking | |
3e133c44 | 419 | * @monitor: Board-specific health check function |
37b5a603 | 420 | * @fini: Cleanup function |
8ceee660 | 421 | * @blinker: used to blink LEDs in software |
37b5a603 BH |
422 | * @hwmon_client: I2C client for hardware monitor |
423 | * @ioexp_client: I2C client for power/port control | |
8ceee660 BH |
424 | */ |
425 | struct efx_board { | |
426 | int type; | |
427 | int major; | |
428 | int minor; | |
429 | int (*init) (struct efx_nic *nic); | |
430 | /* As the LEDs are typically attached to the PHY, LEDs | |
431 | * have a separate init callback that happens later than | |
432 | * board init. */ | |
433 | int (*init_leds)(struct efx_nic *efx); | |
3e133c44 | 434 | int (*monitor) (struct efx_nic *nic); |
dc8cfa55 BH |
435 | void (*set_fault_led) (struct efx_nic *efx, bool state); |
436 | void (*blink) (struct efx_nic *efx, bool start); | |
37b5a603 | 437 | void (*fini) (struct efx_nic *nic); |
8ceee660 | 438 | struct efx_blinker blinker; |
37b5a603 | 439 | struct i2c_client *hwmon_client, *ioexp_client; |
8ceee660 BH |
440 | }; |
441 | ||
3273c2e8 BH |
442 | #define STRING_TABLE_LOOKUP(val, member) \ |
443 | member ## _names[val] | |
444 | ||
8ceee660 BH |
445 | enum efx_int_mode { |
446 | /* Be careful if altering to correct macro below */ | |
447 | EFX_INT_MODE_MSIX = 0, | |
448 | EFX_INT_MODE_MSI = 1, | |
449 | EFX_INT_MODE_LEGACY = 2, | |
450 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
451 | }; | |
452 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
453 | ||
454 | enum phy_type { | |
455 | PHY_TYPE_NONE = 0, | |
456 | PHY_TYPE_CX4_RTMR = 1, | |
457 | PHY_TYPE_1G_ALASKA = 2, | |
458 | PHY_TYPE_10XPRESS = 3, | |
459 | PHY_TYPE_XFP = 4, | |
460 | PHY_TYPE_PM8358 = 6, | |
461 | PHY_TYPE_MAX /* Insert any new items before this */ | |
462 | }; | |
463 | ||
464 | #define PHY_ADDR_INVALID 0xff | |
465 | ||
177dfcd8 BH |
466 | #define EFX_IS10G(efx) ((efx)->link_speed == 10000) |
467 | ||
8ceee660 BH |
468 | enum nic_state { |
469 | STATE_INIT = 0, | |
470 | STATE_RUNNING = 1, | |
471 | STATE_FINI = 2, | |
3c78708f | 472 | STATE_DISABLED = 3, |
8ceee660 BH |
473 | STATE_MAX, |
474 | }; | |
475 | ||
476 | /* | |
477 | * Alignment of page-allocated RX buffers | |
478 | * | |
479 | * Controls the number of bytes inserted at the start of an RX buffer. | |
480 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment | |
481 | * of the skb->head for hardware DMA]. | |
482 | */ | |
13e9ab11 | 483 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
8ceee660 BH |
484 | #define EFX_PAGE_IP_ALIGN 0 |
485 | #else | |
486 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN | |
487 | #endif | |
488 | ||
489 | /* | |
490 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
491 | * | |
492 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
493 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
494 | * EFX_PAGE_IP_ALIGN. | |
495 | */ | |
496 | #define EFX_PAGE_SKB_ALIGN 2 | |
497 | ||
498 | /* Forward declaration */ | |
499 | struct efx_nic; | |
500 | ||
501 | /* Pseudo bit-mask flow control field */ | |
502 | enum efx_fc_type { | |
503 | EFX_FC_RX = 1, | |
504 | EFX_FC_TX = 2, | |
505 | EFX_FC_AUTO = 4, | |
506 | }; | |
507 | ||
177dfcd8 BH |
508 | /* Supported MAC bit-mask */ |
509 | enum efx_mac_type { | |
510 | EFX_GMAC = 1, | |
511 | EFX_XMAC = 2, | |
512 | }; | |
513 | ||
04cc8cac BH |
514 | static inline unsigned int efx_fc_advertise(enum efx_fc_type wanted_fc) |
515 | { | |
516 | unsigned int adv = 0; | |
517 | if (wanted_fc & EFX_FC_RX) | |
518 | adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
519 | if (wanted_fc & EFX_FC_TX) | |
520 | adv ^= ADVERTISE_PAUSE_ASYM; | |
521 | return adv; | |
522 | } | |
523 | ||
524 | static inline enum efx_fc_type efx_fc_resolve(enum efx_fc_type wanted_fc, | |
525 | unsigned int lpa) | |
526 | { | |
527 | unsigned int adv = efx_fc_advertise(wanted_fc); | |
528 | ||
529 | if (!(wanted_fc & EFX_FC_AUTO)) | |
530 | return wanted_fc; | |
531 | ||
532 | if (adv & lpa & ADVERTISE_PAUSE_CAP) | |
533 | return EFX_FC_RX | EFX_FC_TX; | |
534 | if (adv & lpa & ADVERTISE_PAUSE_ASYM) { | |
535 | if (adv & ADVERTISE_PAUSE_CAP) | |
536 | return EFX_FC_RX; | |
537 | if (lpa & ADVERTISE_PAUSE_CAP) | |
538 | return EFX_FC_TX; | |
539 | } | |
540 | return 0; | |
541 | } | |
542 | ||
177dfcd8 BH |
543 | /** |
544 | * struct efx_mac_operations - Efx MAC operations table | |
545 | * @reconfigure: Reconfigure MAC. Serialised by the mac_lock | |
546 | * @update_stats: Update statistics | |
547 | * @check_hw: Check hardware. Serialised by the mac_lock | |
548 | */ | |
549 | struct efx_mac_operations { | |
550 | void (*reconfigure) (struct efx_nic *efx); | |
551 | void (*update_stats) (struct efx_nic *efx); | |
552 | int (*check_hw) (struct efx_nic *efx); | |
553 | }; | |
554 | ||
8ceee660 BH |
555 | /** |
556 | * struct efx_phy_operations - Efx PHY operations table | |
557 | * @init: Initialise PHY | |
558 | * @fini: Shut down PHY | |
559 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
560 | * @clear_interrupt: Clear down interrupt | |
561 | * @blink: Blink LEDs | |
562 | * @check_hw: Check hardware | |
177dfcd8 BH |
563 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
564 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
04cc8cac BH |
565 | * @set_xnp_advertise: Set abilities advertised in Extended Next Page |
566 | * (only needed where AN bit is set in mmds) | |
8ceee660 | 567 | * @mmds: MMD presence mask |
3273c2e8 | 568 | * @loopbacks: Supported loopback modes mask |
8ceee660 BH |
569 | */ |
570 | struct efx_phy_operations { | |
177dfcd8 | 571 | enum efx_mac_type macs; |
8ceee660 BH |
572 | int (*init) (struct efx_nic *efx); |
573 | void (*fini) (struct efx_nic *efx); | |
574 | void (*reconfigure) (struct efx_nic *efx); | |
575 | void (*clear_interrupt) (struct efx_nic *efx); | |
576 | int (*check_hw) (struct efx_nic *efx); | |
8c8661e4 | 577 | int (*test) (struct efx_nic *efx); |
177dfcd8 BH |
578 | void (*get_settings) (struct efx_nic *efx, |
579 | struct ethtool_cmd *ecmd); | |
580 | int (*set_settings) (struct efx_nic *efx, | |
581 | struct ethtool_cmd *ecmd); | |
04cc8cac | 582 | bool (*set_xnp_advertise) (struct efx_nic *efx, u32); |
8ceee660 | 583 | int mmds; |
3273c2e8 | 584 | unsigned loopbacks; |
8ceee660 BH |
585 | }; |
586 | ||
f8b87c17 BH |
587 | /** |
588 | * @enum efx_phy_mode - PHY operating mode flags | |
589 | * @PHY_MODE_NORMAL: on and should pass traffic | |
590 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
591 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
592 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
593 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
594 | */ | |
595 | enum efx_phy_mode { | |
596 | PHY_MODE_NORMAL = 0, | |
597 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
598 | PHY_MODE_LOW_POWER = 2, |
599 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
600 | PHY_MODE_SPECIAL = 8, |
601 | }; | |
602 | ||
603 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
604 | { | |
8c8661e4 | 605 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
606 | } |
607 | ||
8ceee660 BH |
608 | /* |
609 | * Efx extended statistics | |
610 | * | |
611 | * Not all statistics are provided by all supported MACs. The purpose | |
612 | * is this structure is to contain the raw statistics provided by each | |
613 | * MAC. | |
614 | */ | |
615 | struct efx_mac_stats { | |
616 | u64 tx_bytes; | |
617 | u64 tx_good_bytes; | |
618 | u64 tx_bad_bytes; | |
619 | unsigned long tx_packets; | |
620 | unsigned long tx_bad; | |
621 | unsigned long tx_pause; | |
622 | unsigned long tx_control; | |
623 | unsigned long tx_unicast; | |
624 | unsigned long tx_multicast; | |
625 | unsigned long tx_broadcast; | |
626 | unsigned long tx_lt64; | |
627 | unsigned long tx_64; | |
628 | unsigned long tx_65_to_127; | |
629 | unsigned long tx_128_to_255; | |
630 | unsigned long tx_256_to_511; | |
631 | unsigned long tx_512_to_1023; | |
632 | unsigned long tx_1024_to_15xx; | |
633 | unsigned long tx_15xx_to_jumbo; | |
634 | unsigned long tx_gtjumbo; | |
635 | unsigned long tx_collision; | |
636 | unsigned long tx_single_collision; | |
637 | unsigned long tx_multiple_collision; | |
638 | unsigned long tx_excessive_collision; | |
639 | unsigned long tx_deferred; | |
640 | unsigned long tx_late_collision; | |
641 | unsigned long tx_excessive_deferred; | |
642 | unsigned long tx_non_tcpudp; | |
643 | unsigned long tx_mac_src_error; | |
644 | unsigned long tx_ip_src_error; | |
645 | u64 rx_bytes; | |
646 | u64 rx_good_bytes; | |
647 | u64 rx_bad_bytes; | |
648 | unsigned long rx_packets; | |
649 | unsigned long rx_good; | |
650 | unsigned long rx_bad; | |
651 | unsigned long rx_pause; | |
652 | unsigned long rx_control; | |
653 | unsigned long rx_unicast; | |
654 | unsigned long rx_multicast; | |
655 | unsigned long rx_broadcast; | |
656 | unsigned long rx_lt64; | |
657 | unsigned long rx_64; | |
658 | unsigned long rx_65_to_127; | |
659 | unsigned long rx_128_to_255; | |
660 | unsigned long rx_256_to_511; | |
661 | unsigned long rx_512_to_1023; | |
662 | unsigned long rx_1024_to_15xx; | |
663 | unsigned long rx_15xx_to_jumbo; | |
664 | unsigned long rx_gtjumbo; | |
665 | unsigned long rx_bad_lt64; | |
666 | unsigned long rx_bad_64_to_15xx; | |
667 | unsigned long rx_bad_15xx_to_jumbo; | |
668 | unsigned long rx_bad_gtjumbo; | |
669 | unsigned long rx_overflow; | |
670 | unsigned long rx_missed; | |
671 | unsigned long rx_false_carrier; | |
672 | unsigned long rx_symbol_error; | |
673 | unsigned long rx_align_error; | |
674 | unsigned long rx_length_error; | |
675 | unsigned long rx_internal_error; | |
676 | unsigned long rx_good_lt64; | |
677 | }; | |
678 | ||
679 | /* Number of bits used in a multicast filter hash address */ | |
680 | #define EFX_MCAST_HASH_BITS 8 | |
681 | ||
682 | /* Number of (single-bit) entries in a multicast filter hash */ | |
683 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
684 | ||
685 | /* An Efx multicast filter hash */ | |
686 | union efx_multicast_hash { | |
687 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
688 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
689 | }; | |
690 | ||
691 | /** | |
692 | * struct efx_nic - an Efx NIC | |
693 | * @name: Device name (net device name or bus id before net device registered) | |
694 | * @pci_dev: The PCI device | |
695 | * @type: Controller type attributes | |
696 | * @legacy_irq: IRQ number | |
8d9853d9 BH |
697 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
698 | * Work items do not hold and must not acquire RTNL. | |
8ceee660 BH |
699 | * @reset_work: Scheduled reset workitem |
700 | * @monitor_work: Hardware monitor workitem | |
701 | * @membase_phys: Memory BAR value as physical address | |
702 | * @membase: Memory BAR value | |
703 | * @biu_lock: BIU (bus interface unit) lock | |
704 | * @interrupt_mode: Interrupt mode | |
37b5a603 | 705 | * @i2c_adap: I2C adapter |
8ceee660 BH |
706 | * @board_info: Board-level information |
707 | * @state: Device state flag. Serialised by the rtnl_lock. | |
708 | * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) | |
709 | * @tx_queue: TX DMA queues | |
710 | * @rx_queue: RX DMA queues | |
711 | * @channel: Channels | |
8831da7b | 712 | * @n_rx_queues: Number of RX queues |
28b581ab | 713 | * @n_channels: Number of channels in use |
8ceee660 BH |
714 | * @rx_buffer_len: RX buffer length |
715 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer | |
716 | * @irq_status: Interrupt status buffer | |
717 | * @last_irq_cpu: Last CPU to handle interrupt. | |
718 | * This register is written with the SMP processor ID whenever an | |
719 | * interrupt is handled. It is used by falcon_test_interrupt() | |
720 | * to verify that an interrupt has occurred. | |
4a5b504d BH |
721 | * @spi_flash: SPI flash device |
722 | * This field will be %NULL if no flash device is present. | |
723 | * @spi_eeprom: SPI EEPROM device | |
724 | * This field will be %NULL if no EEPROM device is present. | |
f4150724 | 725 | * @spi_lock: SPI bus lock |
8ceee660 BH |
726 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count |
727 | * @nic_data: Hardware dependant state | |
8c8661e4 BH |
728 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
729 | * @port_inhibited, efx_monitor() and efx_reconfigure_port() | |
8ceee660 BH |
730 | * @port_enabled: Port enabled indicator. |
731 | * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and | |
732 | * efx_reconfigure_work with kernel interfaces. Safe to read under any | |
733 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
734 | * be held to modify it. | |
8c8661e4 | 735 | * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock |
8ceee660 BH |
736 | * @port_initialized: Port initialized? |
737 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
738 | * @rx_checksum_enabled: RX checksumming enabled | |
739 | * @netif_stop_count: Port stop count | |
740 | * @netif_stop_lock: Port stop lock | |
741 | * @mac_stats: MAC statistics. These include all statistics the MACs | |
742 | * can provide. Generic code converts these into a standard | |
743 | * &struct net_device_stats. | |
744 | * @stats_buffer: DMA buffer for statistics | |
8c8661e4 BH |
745 | * @stats_lock: Statistics update lock. Serialises statistics fetches |
746 | * @stats_enabled: Temporarily disable statistics fetches. | |
747 | * Serialised by @stats_lock | |
177dfcd8 | 748 | * @mac_op: MAC interface |
8ceee660 BH |
749 | * @mac_address: Permanent MAC address |
750 | * @phy_type: PHY type | |
751 | * @phy_lock: PHY access lock | |
752 | * @phy_op: PHY interface | |
753 | * @phy_data: PHY private data (including PHY-specific stats) | |
754 | * @mii: PHY interface | |
8c8661e4 | 755 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
177dfcd8 | 756 | * @mac_up: MAC link state |
8ceee660 | 757 | * @link_up: Link status |
f31a45d2 | 758 | * @link_fd: Link is full duplex |
04cc8cac | 759 | * @link_fc: Actualy flow control flags |
f31a45d2 | 760 | * @link_speed: Link speed (Mbps) |
8ceee660 BH |
761 | * @n_link_state_changes: Number of times the link has changed state |
762 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. | |
763 | * @multicast_hash: Multicast hash table | |
04cc8cac | 764 | * @wanted_fc: Wanted flow control flags |
8ceee660 | 765 | * @reconfigure_work: work item for dealing with PHY events |
3273c2e8 BH |
766 | * @loopback_mode: Loopback status |
767 | * @loopback_modes: Supported loopback mode bitmask | |
768 | * @loopback_selftest: Offline self-test private state | |
8ceee660 BH |
769 | * |
770 | * The @priv field of the corresponding &struct net_device points to | |
771 | * this. | |
772 | */ | |
773 | struct efx_nic { | |
774 | char name[IFNAMSIZ]; | |
775 | struct pci_dev *pci_dev; | |
776 | const struct efx_nic_type *type; | |
777 | int legacy_irq; | |
778 | struct workqueue_struct *workqueue; | |
779 | struct work_struct reset_work; | |
780 | struct delayed_work monitor_work; | |
086ea356 | 781 | resource_size_t membase_phys; |
8ceee660 BH |
782 | void __iomem *membase; |
783 | spinlock_t biu_lock; | |
784 | enum efx_int_mode interrupt_mode; | |
785 | ||
37b5a603 | 786 | struct i2c_adapter i2c_adap; |
8ceee660 BH |
787 | struct efx_board board_info; |
788 | ||
789 | enum nic_state state; | |
790 | enum reset_type reset_pending; | |
791 | ||
60ac1065 | 792 | struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT]; |
8ceee660 BH |
793 | struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES]; |
794 | struct efx_channel channel[EFX_MAX_CHANNELS]; | |
795 | ||
8831da7b | 796 | int n_rx_queues; |
28b581ab | 797 | int n_channels; |
8ceee660 BH |
798 | unsigned int rx_buffer_len; |
799 | unsigned int rx_buffer_order; | |
800 | ||
801 | struct efx_buffer irq_status; | |
802 | volatile signed int last_irq_cpu; | |
803 | ||
4a5b504d BH |
804 | struct efx_spi_device *spi_flash; |
805 | struct efx_spi_device *spi_eeprom; | |
f4150724 | 806 | struct mutex spi_lock; |
4a5b504d | 807 | |
8ceee660 BH |
808 | unsigned n_rx_nodesc_drop_cnt; |
809 | ||
5daab96d | 810 | struct falcon_nic_data *nic_data; |
8ceee660 BH |
811 | |
812 | struct mutex mac_lock; | |
dc8cfa55 | 813 | bool port_enabled; |
8c8661e4 | 814 | bool port_inhibited; |
8ceee660 | 815 | |
dc8cfa55 | 816 | bool port_initialized; |
8ceee660 | 817 | struct net_device *net_dev; |
dc8cfa55 | 818 | bool rx_checksum_enabled; |
8ceee660 BH |
819 | |
820 | atomic_t netif_stop_count; | |
821 | spinlock_t netif_stop_lock; | |
822 | ||
823 | struct efx_mac_stats mac_stats; | |
824 | struct efx_buffer stats_buffer; | |
825 | spinlock_t stats_lock; | |
8c8661e4 | 826 | bool stats_enabled; |
8ceee660 | 827 | |
177dfcd8 | 828 | struct efx_mac_operations *mac_op; |
8ceee660 BH |
829 | unsigned char mac_address[ETH_ALEN]; |
830 | ||
831 | enum phy_type phy_type; | |
832 | spinlock_t phy_lock; | |
833 | struct efx_phy_operations *phy_op; | |
834 | void *phy_data; | |
835 | struct mii_if_info mii; | |
f8b87c17 | 836 | enum efx_phy_mode phy_mode; |
8ceee660 | 837 | |
177dfcd8 | 838 | bool mac_up; |
dc8cfa55 | 839 | bool link_up; |
f31a45d2 | 840 | bool link_fd; |
04cc8cac | 841 | enum efx_fc_type link_fc; |
f31a45d2 | 842 | unsigned int link_speed; |
8ceee660 BH |
843 | unsigned int n_link_state_changes; |
844 | ||
dc8cfa55 | 845 | bool promiscuous; |
8ceee660 | 846 | union efx_multicast_hash multicast_hash; |
04cc8cac | 847 | enum efx_fc_type wanted_fc; |
8ceee660 BH |
848 | struct work_struct reconfigure_work; |
849 | ||
850 | atomic_t rx_reset; | |
3273c2e8 BH |
851 | enum efx_loopback_mode loopback_mode; |
852 | unsigned int loopback_modes; | |
853 | ||
854 | void *loopback_selftest; | |
8ceee660 BH |
855 | }; |
856 | ||
55668611 BH |
857 | static inline int efx_dev_registered(struct efx_nic *efx) |
858 | { | |
859 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
860 | } | |
861 | ||
862 | /* Net device name, for inclusion in log messages if it has been registered. | |
863 | * Use efx->name not efx->net_dev->name so that races with (un)registration | |
864 | * are harmless. | |
865 | */ | |
866 | static inline const char *efx_dev_name(struct efx_nic *efx) | |
867 | { | |
868 | return efx_dev_registered(efx) ? efx->name : ""; | |
869 | } | |
870 | ||
8ceee660 BH |
871 | /** |
872 | * struct efx_nic_type - Efx device type definition | |
873 | * @mem_bar: Memory BAR number | |
874 | * @mem_map_size: Memory BAR mapped size | |
875 | * @txd_ptr_tbl_base: TX descriptor ring base address | |
876 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
877 | * @buf_tbl_base: Buffer table base address | |
878 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
879 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
880 | * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1) | |
881 | * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1) | |
882 | * @evq_size: Event queue size (must be a power of two) | |
883 | * @max_dma_mask: Maximum possible DMA mask | |
884 | * @tx_dma_mask: TX DMA mask | |
885 | * @bug5391_mask: Address mask for bug 5391 workaround | |
886 | * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes) | |
887 | * @rx_xon_thresh: RX FIFO XON watermark (bytes) | |
888 | * @rx_buffer_padding: Padding added to each RX buffer | |
889 | * @max_interrupt_mode: Highest capability interrupt mode supported | |
890 | * from &enum efx_init_mode. | |
891 | * @phys_addr_channels: Number of channels with physically addressed | |
892 | * descriptors | |
893 | */ | |
894 | struct efx_nic_type { | |
895 | unsigned int mem_bar; | |
896 | unsigned int mem_map_size; | |
897 | unsigned int txd_ptr_tbl_base; | |
898 | unsigned int rxd_ptr_tbl_base; | |
899 | unsigned int buf_tbl_base; | |
900 | unsigned int evq_ptr_tbl_base; | |
901 | unsigned int evq_rptr_tbl_base; | |
902 | ||
903 | unsigned int txd_ring_mask; | |
904 | unsigned int rxd_ring_mask; | |
905 | unsigned int evq_size; | |
9bbd7d9a | 906 | u64 max_dma_mask; |
8ceee660 BH |
907 | unsigned int tx_dma_mask; |
908 | unsigned bug5391_mask; | |
909 | ||
910 | int rx_xoff_thresh; | |
911 | int rx_xon_thresh; | |
912 | unsigned int rx_buffer_padding; | |
913 | unsigned int max_interrupt_mode; | |
914 | unsigned int phys_addr_channels; | |
915 | }; | |
916 | ||
917 | /************************************************************************** | |
918 | * | |
919 | * Prototypes and inline functions | |
920 | * | |
921 | *************************************************************************/ | |
922 | ||
923 | /* Iterate over all used channels */ | |
924 | #define efx_for_each_channel(_channel, _efx) \ | |
925 | for (_channel = &_efx->channel[0]; \ | |
926 | _channel < &_efx->channel[EFX_MAX_CHANNELS]; \ | |
927 | _channel++) \ | |
928 | if (!_channel->used_flags) \ | |
929 | continue; \ | |
930 | else | |
931 | ||
8ceee660 BH |
932 | /* Iterate over all used TX queues */ |
933 | #define efx_for_each_tx_queue(_tx_queue, _efx) \ | |
934 | for (_tx_queue = &_efx->tx_queue[0]; \ | |
60ac1065 BH |
935 | _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \ |
936 | _tx_queue++) | |
8ceee660 BH |
937 | |
938 | /* Iterate over all TX queues belonging to a channel */ | |
939 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
940 | for (_tx_queue = &_channel->efx->tx_queue[0]; \ | |
60ac1065 | 941 | _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \ |
8ceee660 | 942 | _tx_queue++) \ |
60ac1065 | 943 | if (_tx_queue->channel != _channel) \ |
8ceee660 BH |
944 | continue; \ |
945 | else | |
946 | ||
947 | /* Iterate over all used RX queues */ | |
948 | #define efx_for_each_rx_queue(_rx_queue, _efx) \ | |
949 | for (_rx_queue = &_efx->rx_queue[0]; \ | |
8831da7b BH |
950 | _rx_queue < &_efx->rx_queue[_efx->n_rx_queues]; \ |
951 | _rx_queue++) | |
8ceee660 BH |
952 | |
953 | /* Iterate over all RX queues belonging to a channel */ | |
954 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
a2589027 BH |
955 | for (_rx_queue = &_channel->efx->rx_queue[_channel->channel]; \ |
956 | _rx_queue; \ | |
957 | _rx_queue = NULL) \ | |
8831da7b | 958 | if (_rx_queue->channel != _channel) \ |
8ceee660 BH |
959 | continue; \ |
960 | else | |
961 | ||
962 | /* Returns a pointer to the specified receive buffer in the RX | |
963 | * descriptor queue. | |
964 | */ | |
965 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
966 | unsigned int index) | |
967 | { | |
968 | return (&rx_queue->buffer[index]); | |
969 | } | |
970 | ||
971 | /* Set bit in a little-endian bitfield */ | |
18c2fc04 | 972 | static inline void set_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
973 | { |
974 | addr[nr / 8] |= (1 << (nr % 8)); | |
975 | } | |
976 | ||
977 | /* Clear bit in a little-endian bitfield */ | |
18c2fc04 | 978 | static inline void clear_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
979 | { |
980 | addr[nr / 8] &= ~(1 << (nr % 8)); | |
981 | } | |
982 | ||
983 | ||
984 | /** | |
985 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
986 | * | |
987 | * This calculates the maximum frame length that will be used for a | |
988 | * given MTU. The frame length will be equal to the MTU plus a | |
989 | * constant amount of header space and padding. This is the quantity | |
990 | * that the net driver will program into the MAC as the maximum frame | |
991 | * length. | |
992 | * | |
993 | * The 10G MAC used in Falcon requires 8-byte alignment on the frame | |
994 | * length, so we round up to the nearest 8. | |
995 | */ | |
996 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
997 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7) | |
998 | ||
999 | ||
1000 | #endif /* EFX_NET_DRIVER_H */ |