Commit | Line | Data |
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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
906bb26c | 3 | * Copyright 2006-2009 Solarflare Communications Inc. |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | /* | |
b37b62fe | 10 | * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details |
8ceee660 BH |
11 | */ |
12 | ||
13 | #include <linux/timer.h> | |
14 | #include <linux/delay.h> | |
15 | #include "efx.h" | |
8ceee660 | 16 | #include "mdio_10g.h" |
8ceee660 | 17 | #include "phy.h" |
744093c9 | 18 | #include "nic.h" |
8ceee660 | 19 | |
b37b62fe BH |
20 | #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \ |
21 | MDIO_DEVS_PMAPMD | \ | |
22 | MDIO_DEVS_PHYXS) | |
8ceee660 | 23 | |
b37b62fe BH |
24 | #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \ |
25 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 26 | (1 << LOOPBACK_PHYXS_WS)) |
3273c2e8 | 27 | |
8ceee660 BH |
28 | /****************************************************************************/ |
29 | /* Quake-specific MDIO registers */ | |
30 | #define MDIO_QUAKE_LED0_REG (0xD006) | |
31 | ||
d2d2c373 BH |
32 | /* QT2025C only */ |
33 | #define PCS_FW_HEARTBEAT_REG 0xd7ee | |
34 | #define PCS_FW_HEARTB_LBN 0 | |
35 | #define PCS_FW_HEARTB_WIDTH 8 | |
0d83b2f6 MS |
36 | #define PCS_FW_PRODUCT_CODE_1 0xd7f0 |
37 | #define PCS_FW_VERSION_1 0xd7f3 | |
38 | #define PCS_FW_BUILD_1 0xd7f6 | |
d2d2c373 BH |
39 | #define PCS_UC8051_STATUS_REG 0xd7fd |
40 | #define PCS_UC_STATUS_LBN 0 | |
41 | #define PCS_UC_STATUS_WIDTH 8 | |
42 | #define PCS_UC_STATUS_FW_SAVE 0x20 | |
43 | #define PMA_PMD_FTX_CTRL2_REG 0xc309 | |
44 | #define PMA_PMD_FTX_STATIC_LBN 13 | |
45 | #define PMA_PMD_VEND1_REG 0xc001 | |
46 | #define PMA_PMD_VEND1_LBTXD_LBN 15 | |
47 | #define PCS_VEND1_REG 0xc000 | |
48 | #define PCS_VEND1_LBTXD_LBN 5 | |
49 | ||
b37b62fe | 50 | void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode) |
8ceee660 BH |
51 | { |
52 | int addr = MDIO_QUAKE_LED0_REG + led; | |
68e7f45e | 53 | efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode); |
8ceee660 BH |
54 | } |
55 | ||
b37b62fe | 56 | struct qt202x_phy_data { |
f8b87c17 | 57 | enum efx_phy_mode phy_mode; |
17d6aeaf MS |
58 | bool bug17190_in_bad_state; |
59 | unsigned long bug17190_timer; | |
0d83b2f6 | 60 | u32 firmware_ver; |
3273c2e8 BH |
61 | }; |
62 | ||
b37b62fe BH |
63 | #define QT2022C2_MAX_RESET_TIME 500 |
64 | #define QT2022C2_RESET_WAIT 10 | |
8ceee660 | 65 | |
1a1284ef MS |
66 | #define QT2025C_MAX_HEARTB_TIME (5 * HZ) |
67 | #define QT2025C_HEARTB_WAIT 100 | |
68 | #define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10) | |
69 | #define QT2025C_FWSTART_WAIT 100 | |
70 | ||
17d6aeaf MS |
71 | #define BUG17190_INTERVAL (2 * HZ) |
72 | ||
1a1284ef | 73 | static int qt2025c_wait_heartbeat(struct efx_nic *efx) |
d2d2c373 | 74 | { |
1a1284ef | 75 | unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME; |
d2d2c373 BH |
76 | int reg, old_counter = 0; |
77 | ||
78 | /* Wait for firmware heartbeat to start */ | |
79 | for (;;) { | |
80 | int counter; | |
68e7f45e | 81 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG); |
d2d2c373 BH |
82 | if (reg < 0) |
83 | return reg; | |
84 | counter = ((reg >> PCS_FW_HEARTB_LBN) & | |
85 | ((1 << PCS_FW_HEARTB_WIDTH) - 1)); | |
86 | if (old_counter == 0) | |
87 | old_counter = counter; | |
88 | else if (counter != old_counter) | |
89 | break; | |
90 | if (time_after(jiffies, timeout)) | |
91 | return -ETIMEDOUT; | |
1a1284ef | 92 | msleep(QT2025C_HEARTB_WAIT); |
d2d2c373 BH |
93 | } |
94 | ||
1a1284ef MS |
95 | return 0; |
96 | } | |
97 | ||
98 | static int qt2025c_wait_fw_status_good(struct efx_nic *efx) | |
99 | { | |
100 | unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME; | |
101 | int reg; | |
102 | ||
d2d2c373 BH |
103 | /* Wait for firmware status to look good */ |
104 | for (;;) { | |
68e7f45e | 105 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG); |
d2d2c373 BH |
106 | if (reg < 0) |
107 | return reg; | |
108 | if ((reg & | |
109 | ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >= | |
110 | PCS_UC_STATUS_FW_SAVE) | |
111 | break; | |
112 | if (time_after(jiffies, timeout)) | |
113 | return -ETIMEDOUT; | |
1a1284ef | 114 | msleep(QT2025C_FWSTART_WAIT); |
d2d2c373 BH |
115 | } |
116 | ||
117 | return 0; | |
118 | } | |
119 | ||
1a1284ef MS |
120 | static void qt2025c_restart_firmware(struct efx_nic *efx) |
121 | { | |
122 | /* Restart microcontroller execution of firmware from RAM */ | |
123 | efx_mdio_write(efx, 3, 0xe854, 0x00c0); | |
124 | efx_mdio_write(efx, 3, 0xe854, 0x0040); | |
125 | msleep(50); | |
126 | } | |
127 | ||
128 | static int qt2025c_wait_reset(struct efx_nic *efx) | |
129 | { | |
130 | int rc; | |
131 | ||
132 | rc = qt2025c_wait_heartbeat(efx); | |
133 | if (rc != 0) | |
134 | return rc; | |
135 | ||
136 | rc = qt2025c_wait_fw_status_good(efx); | |
137 | if (rc == -ETIMEDOUT) { | |
138 | /* Bug 17689: occasionally heartbeat starts but firmware status | |
139 | * code never progresses beyond 0x00. Try again, once, after | |
140 | * restarting execution of the firmware image. */ | |
141 | EFX_LOG(efx, "bashing QT2025C microcontroller\n"); | |
142 | qt2025c_restart_firmware(efx); | |
143 | rc = qt2025c_wait_heartbeat(efx); | |
144 | if (rc != 0) | |
145 | return rc; | |
146 | rc = qt2025c_wait_fw_status_good(efx); | |
147 | } | |
148 | ||
149 | return rc; | |
150 | } | |
151 | ||
0d83b2f6 MS |
152 | static void qt2025c_firmware_id(struct efx_nic *efx) |
153 | { | |
154 | struct qt202x_phy_data *phy_data = efx->phy_data; | |
155 | u8 firmware_id[9]; | |
156 | size_t i; | |
157 | ||
158 | for (i = 0; i < sizeof(firmware_id); i++) | |
159 | firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS, | |
160 | PCS_FW_PRODUCT_CODE_1 + i); | |
161 | EFX_INFO(efx, "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n", | |
162 | (firmware_id[0] << 8) | firmware_id[1], firmware_id[2], | |
163 | firmware_id[3] >> 4, firmware_id[3] & 0xf, | |
164 | firmware_id[4], firmware_id[5], | |
165 | firmware_id[6], firmware_id[7], firmware_id[8]); | |
166 | phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) | | |
167 | ((firmware_id[3] & 0x0f) << 16) | | |
168 | (firmware_id[4] << 8) | firmware_id[5]; | |
169 | } | |
170 | ||
17d6aeaf MS |
171 | static void qt2025c_bug17190_workaround(struct efx_nic *efx) |
172 | { | |
173 | struct qt202x_phy_data *phy_data = efx->phy_data; | |
174 | ||
175 | /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD | |
176 | * layers up, but PCS down (no block_lock). If we notice this state | |
177 | * persisting for a couple of seconds, we switch PMA/PMD loopback | |
178 | * briefly on and then off again, which is normally sufficient to | |
179 | * recover it. | |
180 | */ | |
181 | if (efx->link_state.up || | |
182 | !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) { | |
183 | phy_data->bug17190_in_bad_state = false; | |
184 | return; | |
185 | } | |
186 | ||
187 | if (!phy_data->bug17190_in_bad_state) { | |
188 | phy_data->bug17190_in_bad_state = true; | |
189 | phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL; | |
190 | return; | |
191 | } | |
192 | ||
193 | if (time_after_eq(jiffies, phy_data->bug17190_timer)) { | |
194 | EFX_LOG(efx, "bashing QT2025C PMA/PMD\n"); | |
195 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, | |
196 | MDIO_PMA_CTRL1_LOOPBACK, true); | |
197 | msleep(100); | |
198 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1, | |
199 | MDIO_PMA_CTRL1_LOOPBACK, false); | |
200 | phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL; | |
201 | } | |
202 | } | |
203 | ||
0d83b2f6 MS |
204 | static int qt2025c_select_phy_mode(struct efx_nic *efx) |
205 | { | |
206 | struct qt202x_phy_data *phy_data = efx->phy_data; | |
207 | struct falcon_board *board = falcon_board(efx); | |
208 | int reg, rc, i; | |
209 | uint16_t phy_op_mode; | |
210 | ||
211 | /* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+ | |
212 | * Self-Configure mode. Don't attempt any switching if we encounter | |
213 | * older firmware. */ | |
214 | if (phy_data->firmware_ver < 0x02000100) | |
215 | return 0; | |
216 | ||
217 | /* In general we will get optimal behaviour in "SFP+ Self-Configure" | |
218 | * mode; however, that powers down most of the PHY when no module is | |
219 | * present, so we must use a different mode (any fixed mode will do) | |
220 | * to be sure that loopbacks will work. */ | |
221 | phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020; | |
222 | ||
223 | /* Only change mode if really necessary */ | |
224 | reg = efx_mdio_read(efx, 1, 0xc319); | |
225 | if ((reg & 0x0038) == phy_op_mode) | |
226 | return 0; | |
227 | EFX_LOG(efx, "Switching PHY to mode 0x%04x\n", phy_op_mode); | |
228 | ||
229 | /* This sequence replicates the register writes configured in the boot | |
230 | * EEPROM (including the differences between board revisions), except | |
231 | * that the operating mode is changed, and the PHY is prevented from | |
232 | * unnecessarily reloading the main firmware image again. */ | |
233 | efx_mdio_write(efx, 1, 0xc300, 0x0000); | |
234 | /* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9 | |
235 | * STOPs onto the firmware/module I2C bus to reset it, varies across | |
236 | * board revisions, as the bus is connected to different GPIO/LED | |
237 | * outputs on the PHY.) */ | |
238 | if (board->major == 0 && board->minor < 2) { | |
239 | efx_mdio_write(efx, 1, 0xc303, 0x4498); | |
240 | for (i = 0; i < 9; i++) { | |
241 | efx_mdio_write(efx, 1, 0xc303, 0x4488); | |
242 | efx_mdio_write(efx, 1, 0xc303, 0x4480); | |
243 | efx_mdio_write(efx, 1, 0xc303, 0x4490); | |
244 | efx_mdio_write(efx, 1, 0xc303, 0x4498); | |
245 | } | |
246 | } else { | |
247 | efx_mdio_write(efx, 1, 0xc303, 0x0920); | |
248 | efx_mdio_write(efx, 1, 0xd008, 0x0004); | |
249 | for (i = 0; i < 9; i++) { | |
250 | efx_mdio_write(efx, 1, 0xc303, 0x0900); | |
251 | efx_mdio_write(efx, 1, 0xd008, 0x0005); | |
252 | efx_mdio_write(efx, 1, 0xc303, 0x0920); | |
253 | efx_mdio_write(efx, 1, 0xd008, 0x0004); | |
254 | } | |
255 | efx_mdio_write(efx, 1, 0xc303, 0x4900); | |
256 | } | |
257 | efx_mdio_write(efx, 1, 0xc303, 0x4900); | |
258 | efx_mdio_write(efx, 1, 0xc302, 0x0004); | |
259 | efx_mdio_write(efx, 1, 0xc316, 0x0013); | |
260 | efx_mdio_write(efx, 1, 0xc318, 0x0054); | |
261 | efx_mdio_write(efx, 1, 0xc319, phy_op_mode); | |
262 | efx_mdio_write(efx, 1, 0xc31a, 0x0098); | |
263 | efx_mdio_write(efx, 3, 0x0026, 0x0e00); | |
264 | efx_mdio_write(efx, 3, 0x0027, 0x0013); | |
265 | efx_mdio_write(efx, 3, 0x0028, 0xa528); | |
266 | efx_mdio_write(efx, 1, 0xd006, 0x000a); | |
267 | efx_mdio_write(efx, 1, 0xd007, 0x0009); | |
268 | efx_mdio_write(efx, 1, 0xd008, 0x0004); | |
269 | /* This additional write is not present in the boot EEPROM. It | |
270 | * prevents the PHY's internal boot ROM doing another pointless (and | |
271 | * slow) reload of the firmware image (the microcontroller's code | |
272 | * memory is not affected by the microcontroller reset). */ | |
273 | efx_mdio_write(efx, 1, 0xc317, 0x00ff); | |
274 | efx_mdio_write(efx, 1, 0xc300, 0x0002); | |
275 | msleep(20); | |
276 | ||
1a1284ef MS |
277 | /* Restart microcontroller execution of firmware from RAM */ |
278 | qt2025c_restart_firmware(efx); | |
0d83b2f6 MS |
279 | |
280 | /* Wait for the microcontroller to be ready again */ | |
281 | rc = qt2025c_wait_reset(efx); | |
282 | if (rc < 0) { | |
283 | EFX_ERR(efx, "PHY microcontroller reset during mode switch " | |
284 | "timed out\n"); | |
285 | return rc; | |
286 | } | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
b37b62fe | 291 | static int qt202x_reset_phy(struct efx_nic *efx) |
8ceee660 BH |
292 | { |
293 | int rc; | |
294 | ||
d2d2c373 | 295 | if (efx->phy_type == PHY_TYPE_QT2025C) { |
5afaa753 BH |
296 | /* Wait for the reset triggered by falcon_reset_hw() |
297 | * to complete */ | |
d2d2c373 BH |
298 | rc = qt2025c_wait_reset(efx); |
299 | if (rc < 0) | |
300 | goto fail; | |
5afaa753 BH |
301 | } else { |
302 | /* Reset the PHYXS MMD. This is documented as doing | |
303 | * a complete soft reset. */ | |
304 | rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS, | |
b37b62fe BH |
305 | QT2022C2_MAX_RESET_TIME / |
306 | QT2022C2_RESET_WAIT, | |
307 | QT2022C2_RESET_WAIT); | |
5afaa753 BH |
308 | if (rc < 0) |
309 | goto fail; | |
d2d2c373 BH |
310 | } |
311 | ||
8ceee660 BH |
312 | /* Wait 250ms for the PHY to complete bootup */ |
313 | msleep(250); | |
314 | ||
315 | /* Check that all the MMDs we expect are present and responding. We | |
316 | * expect faults on some if the link is down, but not on the PHY XS */ | |
b37b62fe | 317 | rc = efx_mdio_check_mmds(efx, QT202X_REQUIRED_DEVS, MDIO_DEVS_PHYXS); |
8ceee660 BH |
318 | if (rc < 0) |
319 | goto fail; | |
320 | ||
44838a44 | 321 | falcon_board(efx)->type->init_phy(efx); |
8ceee660 BH |
322 | |
323 | return rc; | |
324 | ||
325 | fail: | |
f794fd44 | 326 | EFX_ERR(efx, "PHY reset timed out\n"); |
8ceee660 BH |
327 | return rc; |
328 | } | |
329 | ||
c1c4f453 BH |
330 | static int qt202x_phy_probe(struct efx_nic *efx) |
331 | { | |
ff3b00a0 SH |
332 | struct qt202x_phy_data *phy_data; |
333 | ||
334 | phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL); | |
335 | if (!phy_data) | |
336 | return -ENOMEM; | |
337 | efx->phy_data = phy_data; | |
338 | phy_data->phy_mode = efx->phy_mode; | |
17d6aeaf MS |
339 | phy_data->bug17190_in_bad_state = false; |
340 | phy_data->bug17190_timer = 0; | |
ff3b00a0 | 341 | |
c1c4f453 BH |
342 | efx->mdio.mmds = QT202X_REQUIRED_DEVS; |
343 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
344 | efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS; | |
345 | return 0; | |
346 | } | |
347 | ||
b37b62fe | 348 | static int qt202x_phy_init(struct efx_nic *efx) |
8ceee660 | 349 | { |
47c3d19f | 350 | u32 devid; |
8ceee660 BH |
351 | int rc; |
352 | ||
47c3d19f SH |
353 | rc = qt202x_reset_phy(efx); |
354 | if (rc) { | |
355 | EFX_ERR(efx, "PHY init failed\n"); | |
356 | return rc; | |
357 | } | |
358 | ||
47c3d19f | 359 | devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS); |
3f39a5e9 | 360 | EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n", |
68e7f45e BH |
361 | devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid), |
362 | efx_mdio_id_rev(devid)); | |
8ceee660 | 363 | |
0d83b2f6 MS |
364 | if (efx->phy_type == PHY_TYPE_QT2025C) |
365 | qt2025c_firmware_id(efx); | |
366 | ||
3273c2e8 | 367 | return 0; |
8ceee660 BH |
368 | } |
369 | ||
b37b62fe | 370 | static int qt202x_link_ok(struct efx_nic *efx) |
8ceee660 | 371 | { |
b37b62fe | 372 | return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS); |
8ceee660 BH |
373 | } |
374 | ||
fdaa9aed | 375 | static bool qt202x_phy_poll(struct efx_nic *efx) |
8ceee660 | 376 | { |
fdaa9aed SH |
377 | bool was_up = efx->link_state.up; |
378 | ||
379 | efx->link_state.up = qt202x_link_ok(efx); | |
380 | efx->link_state.speed = 10000; | |
381 | efx->link_state.fd = true; | |
382 | efx->link_state.fc = efx->wanted_fc; | |
383 | ||
17d6aeaf MS |
384 | if (efx->phy_type == PHY_TYPE_QT2025C) |
385 | qt2025c_bug17190_workaround(efx); | |
386 | ||
fdaa9aed | 387 | return efx->link_state.up != was_up; |
8ceee660 BH |
388 | } |
389 | ||
d3245b28 | 390 | static int qt202x_phy_reconfigure(struct efx_nic *efx) |
8ceee660 | 391 | { |
b37b62fe | 392 | struct qt202x_phy_data *phy_data = efx->phy_data; |
3273c2e8 | 393 | |
d2d2c373 | 394 | if (efx->phy_type == PHY_TYPE_QT2025C) { |
0d83b2f6 MS |
395 | int rc = qt2025c_select_phy_mode(efx); |
396 | if (rc) | |
397 | return rc; | |
398 | ||
d2d2c373 BH |
399 | /* There are several different register bits which can |
400 | * disable TX (and save power) on direct-attach cables | |
401 | * or optical transceivers, varying somewhat between | |
402 | * firmware versions. Only 'static mode' appears to | |
403 | * cover everything. */ | |
68e7f45e BH |
404 | mdio_set_flag( |
405 | &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD, | |
406 | PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN, | |
d2d2c373 BH |
407 | efx->phy_mode & PHY_MODE_TX_DISABLED || |
408 | efx->phy_mode & PHY_MODE_LOW_POWER || | |
409 | efx->loopback_mode == LOOPBACK_PCS || | |
410 | efx->loopback_mode == LOOPBACK_PMAPMD); | |
411 | } else { | |
412 | /* Reset the PHY when moving from tx off to tx on */ | |
413 | if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) && | |
414 | (phy_data->phy_mode & PHY_MODE_TX_DISABLED)) | |
b37b62fe | 415 | qt202x_reset_phy(efx); |
d2d2c373 | 416 | |
68e7f45e | 417 | efx_mdio_transmit_disable(efx); |
d2d2c373 | 418 | } |
3273c2e8 | 419 | |
68e7f45e | 420 | efx_mdio_phy_reconfigure(efx); |
3273c2e8 | 421 | |
f8b87c17 | 422 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 BH |
423 | |
424 | return 0; | |
8ceee660 BH |
425 | } |
426 | ||
b37b62fe | 427 | static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
68e7f45e BH |
428 | { |
429 | mdio45_ethtool_gset(&efx->mdio, ecmd); | |
430 | } | |
8ceee660 | 431 | |
ff3b00a0 | 432 | static void qt202x_phy_remove(struct efx_nic *efx) |
8ceee660 | 433 | { |
3273c2e8 BH |
434 | /* Free the context block */ |
435 | kfree(efx->phy_data); | |
436 | efx->phy_data = NULL; | |
8ceee660 BH |
437 | } |
438 | ||
b37b62fe | 439 | struct efx_phy_operations falcon_qt202x_phy_ops = { |
c1c4f453 | 440 | .probe = qt202x_phy_probe, |
b37b62fe BH |
441 | .init = qt202x_phy_init, |
442 | .reconfigure = qt202x_phy_reconfigure, | |
443 | .poll = qt202x_phy_poll, | |
ff3b00a0 SH |
444 | .fini = efx_port_dummy_op_void, |
445 | .remove = qt202x_phy_remove, | |
b37b62fe | 446 | .get_settings = qt202x_phy_get_settings, |
68e7f45e | 447 | .set_settings = efx_mdio_set_settings, |
8ceee660 | 448 | }; |