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afd4aea0 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2009 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d614cfbc | 16 | #include <linux/random.h> |
afd4aea0 BH |
17 | #include "net_driver.h" |
18 | #include "bitfield.h" | |
19 | #include "efx.h" | |
20 | #include "nic.h" | |
21 | #include "mac.h" | |
22 | #include "spi.h" | |
23 | #include "regs.h" | |
24 | #include "io.h" | |
25 | #include "phy.h" | |
26 | #include "workarounds.h" | |
27 | #include "mcdi.h" | |
28 | #include "mcdi_pcol.h" | |
29 | ||
30 | /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ | |
31 | ||
32 | static void siena_init_wol(struct efx_nic *efx); | |
33 | ||
34 | ||
35 | static void siena_push_irq_moderation(struct efx_channel *channel) | |
36 | { | |
37 | efx_dword_t timer_cmd; | |
38 | ||
39 | if (channel->irq_moderation) | |
40 | EFX_POPULATE_DWORD_2(timer_cmd, | |
41 | FRF_CZ_TC_TIMER_MODE, | |
42 | FFE_CZ_TIMER_MODE_INT_HLDOFF, | |
43 | FRF_CZ_TC_TIMER_VAL, | |
44 | channel->irq_moderation - 1); | |
45 | else | |
46 | EFX_POPULATE_DWORD_2(timer_cmd, | |
47 | FRF_CZ_TC_TIMER_MODE, | |
48 | FFE_CZ_TIMER_MODE_DIS, | |
49 | FRF_CZ_TC_TIMER_VAL, 0); | |
50 | efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, | |
51 | channel->channel); | |
52 | } | |
53 | ||
54 | static void siena_push_multicast_hash(struct efx_nic *efx) | |
55 | { | |
56 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
57 | ||
58 | efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH, | |
59 | efx->multicast_hash.byte, sizeof(efx->multicast_hash), | |
60 | NULL, 0, NULL); | |
61 | } | |
62 | ||
63 | static int siena_mdio_write(struct net_device *net_dev, | |
64 | int prtad, int devad, u16 addr, u16 value) | |
65 | { | |
66 | struct efx_nic *efx = netdev_priv(net_dev); | |
67 | uint32_t status; | |
68 | int rc; | |
69 | ||
70 | rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad, | |
71 | addr, value, &status); | |
72 | if (rc) | |
73 | return rc; | |
74 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
75 | return -EIO; | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int siena_mdio_read(struct net_device *net_dev, | |
81 | int prtad, int devad, u16 addr) | |
82 | { | |
83 | struct efx_nic *efx = netdev_priv(net_dev); | |
84 | uint16_t value; | |
85 | uint32_t status; | |
86 | int rc; | |
87 | ||
88 | rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad, | |
89 | addr, &value, &status); | |
90 | if (rc) | |
91 | return rc; | |
92 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
93 | return -EIO; | |
94 | ||
95 | return (int)value; | |
96 | } | |
97 | ||
98 | /* This call is responsible for hooking in the MAC and PHY operations */ | |
99 | static int siena_probe_port(struct efx_nic *efx) | |
100 | { | |
101 | int rc; | |
102 | ||
103 | /* Hook in PHY operations table */ | |
104 | efx->phy_op = &efx_mcdi_phy_ops; | |
105 | ||
106 | /* Set up MDIO structure for PHY */ | |
107 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
108 | efx->mdio.mdio_read = siena_mdio_read; | |
109 | efx->mdio.mdio_write = siena_mdio_write; | |
110 | ||
7a6b8f6f | 111 | /* Fill out MDIO structure, loopback modes, and initial link state */ |
afd4aea0 BH |
112 | rc = efx->phy_op->probe(efx); |
113 | if (rc != 0) | |
114 | return rc; | |
115 | ||
afd4aea0 BH |
116 | /* Allocate buffer for stats */ |
117 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, | |
118 | MC_CMD_MAC_NSTATS * sizeof(u64)); | |
119 | if (rc) | |
120 | return rc; | |
62776d03 BH |
121 | netif_dbg(efx, probe, efx->net_dev, |
122 | "stats buffer at %llx (virt %p phys %llx)\n", | |
123 | (u64)efx->stats_buffer.dma_addr, | |
124 | efx->stats_buffer.addr, | |
125 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
afd4aea0 BH |
126 | |
127 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1); | |
128 | ||
129 | return 0; | |
130 | } | |
131 | ||
d215697f | 132 | static void siena_remove_port(struct efx_nic *efx) |
afd4aea0 | 133 | { |
ff3b00a0 | 134 | efx->phy_op->remove(efx); |
afd4aea0 BH |
135 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
136 | } | |
137 | ||
138 | static const struct efx_nic_register_test siena_register_tests[] = { | |
139 | { FR_AZ_ADR_REGION, | |
4cddca54 | 140 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
afd4aea0 BH |
141 | { FR_CZ_USR_EV_CFG, |
142 | EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, | |
143 | { FR_AZ_RX_CFG, | |
144 | EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, | |
145 | { FR_AZ_TX_CFG, | |
146 | EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, | |
147 | { FR_AZ_TX_RESERVED, | |
148 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, | |
149 | { FR_AZ_SRM_TX_DC_CFG, | |
150 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, | |
151 | { FR_AZ_RX_DC_CFG, | |
152 | EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, | |
153 | { FR_AZ_RX_DC_PF_WM, | |
154 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, | |
155 | { FR_BZ_DP_CTRL, | |
156 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, | |
157 | { FR_BZ_RX_RSS_TKEY, | |
158 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
159 | { FR_CZ_RX_RSS_IPV6_REG1, | |
160 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
161 | { FR_CZ_RX_RSS_IPV6_REG2, | |
162 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
163 | { FR_CZ_RX_RSS_IPV6_REG3, | |
164 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, | |
165 | }; | |
166 | ||
167 | static int siena_test_registers(struct efx_nic *efx) | |
168 | { | |
169 | return efx_nic_test_registers(efx, siena_register_tests, | |
170 | ARRAY_SIZE(siena_register_tests)); | |
171 | } | |
172 | ||
173 | /************************************************************************** | |
174 | * | |
175 | * Device reset | |
176 | * | |
177 | ************************************************************************** | |
178 | */ | |
179 | ||
180 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) | |
181 | { | |
8b2103ad SH |
182 | int rc; |
183 | ||
184 | /* Recover from a failed assertion pre-reset */ | |
185 | rc = efx_mcdi_handle_assertion(efx); | |
186 | if (rc) | |
187 | return rc; | |
afd4aea0 BH |
188 | |
189 | if (method == RESET_TYPE_WORLD) | |
190 | return efx_mcdi_reset_mc(efx); | |
191 | else | |
192 | return efx_mcdi_reset_port(efx); | |
193 | } | |
194 | ||
195 | static int siena_probe_nvconfig(struct efx_nic *efx) | |
196 | { | |
197 | int rc; | |
198 | ||
199 | rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL); | |
200 | if (rc) | |
201 | return rc; | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | static int siena_probe_nic(struct efx_nic *efx) | |
207 | { | |
208 | struct siena_nic_data *nic_data; | |
209 | bool already_attached = 0; | |
d42a8f46 | 210 | efx_oword_t reg; |
afd4aea0 BH |
211 | int rc; |
212 | ||
213 | /* Allocate storage for hardware specific data */ | |
214 | nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); | |
215 | if (!nic_data) | |
216 | return -ENOMEM; | |
217 | efx->nic_data = nic_data; | |
218 | ||
219 | if (efx_nic_fpga_ver(efx) != 0) { | |
62776d03 BH |
220 | netif_err(efx, probe, efx->net_dev, |
221 | "Siena FPGA not supported\n"); | |
afd4aea0 BH |
222 | rc = -ENODEV; |
223 | goto fail1; | |
224 | } | |
225 | ||
d42a8f46 | 226 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); |
3df95ce9 | 227 | efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; |
d42a8f46 | 228 | |
afd4aea0 BH |
229 | efx_mcdi_init(efx); |
230 | ||
231 | /* Recover from a failed assertion before probing */ | |
232 | rc = efx_mcdi_handle_assertion(efx); | |
233 | if (rc) | |
234 | goto fail1; | |
235 | ||
236 | rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build); | |
237 | if (rc) { | |
62776d03 BH |
238 | netif_err(efx, probe, efx->net_dev, |
239 | "Failed to read MCPU firmware version - rc %d\n", rc); | |
afd4aea0 BH |
240 | goto fail1; /* MCPU absent? */ |
241 | } | |
242 | ||
243 | /* Let the BMC know that the driver is now in charge of link and | |
244 | * filter settings. We must do this before we reset the NIC */ | |
245 | rc = efx_mcdi_drv_attach(efx, true, &already_attached); | |
246 | if (rc) { | |
62776d03 BH |
247 | netif_err(efx, probe, efx->net_dev, |
248 | "Unable to register driver with MCPU\n"); | |
afd4aea0 BH |
249 | goto fail2; |
250 | } | |
251 | if (already_attached) | |
252 | /* Not a fatal error */ | |
62776d03 BH |
253 | netif_err(efx, probe, efx->net_dev, |
254 | "Host already registered with MCPU\n"); | |
afd4aea0 BH |
255 | |
256 | /* Now we can reset the NIC */ | |
257 | rc = siena_reset_hw(efx, RESET_TYPE_ALL); | |
258 | if (rc) { | |
62776d03 | 259 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
afd4aea0 BH |
260 | goto fail3; |
261 | } | |
262 | ||
263 | siena_init_wol(efx); | |
264 | ||
265 | /* Allocate memory for INT_KER */ | |
266 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
267 | if (rc) | |
268 | goto fail4; | |
269 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
270 | ||
62776d03 BH |
271 | netif_dbg(efx, probe, efx->net_dev, |
272 | "INT_KER at %llx (virt %p phys %llx)\n", | |
273 | (unsigned long long)efx->irq_status.dma_addr, | |
274 | efx->irq_status.addr, | |
275 | (unsigned long long)virt_to_phys(efx->irq_status.addr)); | |
afd4aea0 BH |
276 | |
277 | /* Read in the non-volatile configuration */ | |
278 | rc = siena_probe_nvconfig(efx); | |
279 | if (rc == -EINVAL) { | |
62776d03 BH |
280 | netif_err(efx, probe, efx->net_dev, |
281 | "NVRAM is invalid therefore using defaults\n"); | |
afd4aea0 BH |
282 | efx->phy_type = PHY_TYPE_NONE; |
283 | efx->mdio.prtad = MDIO_PRTAD_NONE; | |
284 | } else if (rc) { | |
285 | goto fail5; | |
286 | } | |
287 | ||
288 | return 0; | |
289 | ||
290 | fail5: | |
291 | efx_nic_free_buffer(efx, &efx->irq_status); | |
292 | fail4: | |
293 | fail3: | |
294 | efx_mcdi_drv_attach(efx, false, NULL); | |
295 | fail2: | |
296 | fail1: | |
297 | kfree(efx->nic_data); | |
298 | return rc; | |
299 | } | |
300 | ||
301 | /* This call performs hardware-specific global initialisation, such as | |
302 | * defining the descriptor cache sizes and number of RSS channels. | |
303 | * It does not set up any buffers, descriptor rings or event queues. | |
304 | */ | |
305 | static int siena_init_nic(struct efx_nic *efx) | |
306 | { | |
307 | efx_oword_t temp; | |
308 | int rc; | |
309 | ||
310 | /* Recover from a failed assertion post-reset */ | |
311 | rc = efx_mcdi_handle_assertion(efx); | |
312 | if (rc) | |
313 | return rc; | |
314 | ||
315 | /* Squash TX of packets of 16 bytes or less */ | |
316 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); | |
317 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); | |
318 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); | |
319 | ||
320 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
321 | * descriptors (which is bad). | |
322 | */ | |
323 | efx_reado(efx, &temp, FR_AZ_TX_CFG); | |
324 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); | |
325 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); | |
326 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); | |
327 | ||
328 | efx_reado(efx, &temp, FR_AZ_RX_CFG); | |
329 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); | |
330 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
331 | /* Enable hash insertion. This is broken for the 'Falcon' hash |
332 | * if IPv6 hashing is also enabled, so also select Toeplitz | |
333 | * TCP/IPv4 and IPv4 hashes. */ | |
334 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1); | |
335 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1); | |
336 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1); | |
afd4aea0 BH |
337 | efx_writeo(efx, &temp, FR_AZ_RX_CFG); |
338 | ||
477e54eb BH |
339 | /* Set hash key for IPv4 */ |
340 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
341 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | |
342 | ||
d614cfbc | 343 | /* Enable IPv6 RSS */ |
5d3a6fca | 344 | BUILD_BUG_ON(sizeof(efx->rx_hash_key) < |
d614cfbc BH |
345 | 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || |
346 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); | |
5d3a6fca | 347 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); |
d614cfbc | 348 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); |
5d3a6fca | 349 | memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp)); |
d614cfbc BH |
350 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); |
351 | EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, | |
352 | FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); | |
5d3a6fca | 353 | memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp), |
d614cfbc BH |
354 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); |
355 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); | |
356 | ||
afd4aea0 BH |
357 | if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0) |
358 | /* No MCDI operation has been defined to set thresholds */ | |
62776d03 BH |
359 | netif_err(efx, hw, efx->net_dev, |
360 | "ignoring RX flow control thresholds\n"); | |
afd4aea0 BH |
361 | |
362 | /* Enable event logging */ | |
363 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); | |
364 | if (rc) | |
365 | return rc; | |
366 | ||
367 | /* Set destination of both TX and RX Flush events */ | |
368 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); | |
369 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); | |
370 | ||
371 | EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); | |
372 | efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); | |
373 | ||
374 | efx_nic_init_common(efx); | |
375 | return 0; | |
376 | } | |
377 | ||
378 | static void siena_remove_nic(struct efx_nic *efx) | |
379 | { | |
380 | efx_nic_free_buffer(efx, &efx->irq_status); | |
381 | ||
382 | siena_reset_hw(efx, RESET_TYPE_ALL); | |
383 | ||
384 | /* Relinquish the device back to the BMC */ | |
385 | if (efx_nic_has_mc(efx)) | |
386 | efx_mcdi_drv_attach(efx, false, NULL); | |
387 | ||
388 | /* Tear down the private nic state */ | |
389 | kfree(efx->nic_data); | |
390 | efx->nic_data = NULL; | |
391 | } | |
392 | ||
393 | #define STATS_GENERATION_INVALID ((u64)(-1)) | |
394 | ||
395 | static int siena_try_update_nic_stats(struct efx_nic *efx) | |
396 | { | |
397 | u64 *dma_stats; | |
398 | struct efx_mac_stats *mac_stats; | |
399 | u64 generation_start; | |
400 | u64 generation_end; | |
401 | ||
402 | mac_stats = &efx->mac_stats; | |
403 | dma_stats = (u64 *)efx->stats_buffer.addr; | |
404 | ||
405 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; | |
406 | if (generation_end == STATS_GENERATION_INVALID) | |
407 | return 0; | |
408 | rmb(); | |
409 | ||
410 | #define MAC_STAT(M, D) \ | |
411 | mac_stats->M = dma_stats[MC_CMD_MAC_ ## D] | |
412 | ||
413 | MAC_STAT(tx_bytes, TX_BYTES); | |
414 | MAC_STAT(tx_bad_bytes, TX_BAD_BYTES); | |
415 | mac_stats->tx_good_bytes = (mac_stats->tx_bytes - | |
416 | mac_stats->tx_bad_bytes); | |
417 | MAC_STAT(tx_packets, TX_PKTS); | |
418 | MAC_STAT(tx_bad, TX_BAD_FCS_PKTS); | |
419 | MAC_STAT(tx_pause, TX_PAUSE_PKTS); | |
420 | MAC_STAT(tx_control, TX_CONTROL_PKTS); | |
421 | MAC_STAT(tx_unicast, TX_UNICAST_PKTS); | |
422 | MAC_STAT(tx_multicast, TX_MULTICAST_PKTS); | |
423 | MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS); | |
424 | MAC_STAT(tx_lt64, TX_LT64_PKTS); | |
425 | MAC_STAT(tx_64, TX_64_PKTS); | |
426 | MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS); | |
427 | MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS); | |
428 | MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS); | |
429 | MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS); | |
430 | MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS); | |
431 | MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS); | |
432 | MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS); | |
433 | mac_stats->tx_collision = 0; | |
434 | MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS); | |
435 | MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS); | |
436 | MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS); | |
437 | MAC_STAT(tx_deferred, TX_DEFERRED_PKTS); | |
438 | MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS); | |
439 | mac_stats->tx_collision = (mac_stats->tx_single_collision + | |
440 | mac_stats->tx_multiple_collision + | |
441 | mac_stats->tx_excessive_collision + | |
442 | mac_stats->tx_late_collision); | |
443 | MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS); | |
444 | MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS); | |
445 | MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS); | |
446 | MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS); | |
447 | MAC_STAT(rx_bytes, RX_BYTES); | |
448 | MAC_STAT(rx_bad_bytes, RX_BAD_BYTES); | |
449 | mac_stats->rx_good_bytes = (mac_stats->rx_bytes - | |
450 | mac_stats->rx_bad_bytes); | |
451 | MAC_STAT(rx_packets, RX_PKTS); | |
452 | MAC_STAT(rx_good, RX_GOOD_PKTS); | |
1cdc2cfc | 453 | MAC_STAT(rx_bad, RX_BAD_FCS_PKTS); |
afd4aea0 BH |
454 | MAC_STAT(rx_pause, RX_PAUSE_PKTS); |
455 | MAC_STAT(rx_control, RX_CONTROL_PKTS); | |
456 | MAC_STAT(rx_unicast, RX_UNICAST_PKTS); | |
457 | MAC_STAT(rx_multicast, RX_MULTICAST_PKTS); | |
458 | MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS); | |
459 | MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS); | |
460 | MAC_STAT(rx_64, RX_64_PKTS); | |
461 | MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS); | |
462 | MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS); | |
463 | MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS); | |
464 | MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS); | |
465 | MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS); | |
466 | MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS); | |
467 | MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS); | |
468 | mac_stats->rx_bad_lt64 = 0; | |
469 | mac_stats->rx_bad_64_to_15xx = 0; | |
470 | mac_stats->rx_bad_15xx_to_jumbo = 0; | |
471 | MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS); | |
472 | MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS); | |
473 | mac_stats->rx_missed = 0; | |
474 | MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS); | |
475 | MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS); | |
476 | MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS); | |
477 | MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS); | |
478 | MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS); | |
479 | mac_stats->rx_good_lt64 = 0; | |
480 | ||
481 | efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]; | |
482 | ||
483 | #undef MAC_STAT | |
484 | ||
485 | rmb(); | |
486 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; | |
487 | if (generation_end != generation_start) | |
488 | return -EAGAIN; | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | static void siena_update_nic_stats(struct efx_nic *efx) | |
494 | { | |
aabc5649 BH |
495 | int retry; |
496 | ||
497 | /* If we're unlucky enough to read statistics wduring the DMA, wait | |
498 | * up to 10ms for it to finish (typically takes <500us) */ | |
499 | for (retry = 0; retry < 100; ++retry) { | |
500 | if (siena_try_update_nic_stats(efx) == 0) | |
501 | return; | |
502 | udelay(100); | |
503 | } | |
504 | ||
505 | /* Use the old values instead */ | |
afd4aea0 BH |
506 | } |
507 | ||
508 | static void siena_start_nic_stats(struct efx_nic *efx) | |
509 | { | |
510 | u64 *dma_stats = (u64 *)efx->stats_buffer.addr; | |
511 | ||
512 | dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID; | |
513 | ||
514 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, | |
515 | MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0); | |
516 | } | |
517 | ||
518 | static void siena_stop_nic_stats(struct efx_nic *efx) | |
519 | { | |
520 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0); | |
521 | } | |
522 | ||
523 | void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len) | |
524 | { | |
525 | struct siena_nic_data *nic_data = efx->nic_data; | |
526 | snprintf(buf, len, "%u.%u.%u.%u", | |
527 | (unsigned int)(nic_data->fw_version >> 48), | |
528 | (unsigned int)(nic_data->fw_version >> 32 & 0xffff), | |
529 | (unsigned int)(nic_data->fw_version >> 16 & 0xffff), | |
530 | (unsigned int)(nic_data->fw_version & 0xffff)); | |
531 | } | |
532 | ||
533 | /************************************************************************** | |
534 | * | |
535 | * Wake on LAN | |
536 | * | |
537 | ************************************************************************** | |
538 | */ | |
539 | ||
540 | static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
541 | { | |
542 | struct siena_nic_data *nic_data = efx->nic_data; | |
543 | ||
544 | wol->supported = WAKE_MAGIC; | |
545 | if (nic_data->wol_filter_id != -1) | |
546 | wol->wolopts = WAKE_MAGIC; | |
547 | else | |
548 | wol->wolopts = 0; | |
549 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
550 | } | |
551 | ||
552 | ||
553 | static int siena_set_wol(struct efx_nic *efx, u32 type) | |
554 | { | |
555 | struct siena_nic_data *nic_data = efx->nic_data; | |
556 | int rc; | |
557 | ||
558 | if (type & ~WAKE_MAGIC) | |
559 | return -EINVAL; | |
560 | ||
561 | if (type & WAKE_MAGIC) { | |
562 | if (nic_data->wol_filter_id != -1) | |
563 | efx_mcdi_wol_filter_remove(efx, | |
564 | nic_data->wol_filter_id); | |
565 | rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address, | |
566 | &nic_data->wol_filter_id); | |
567 | if (rc) | |
568 | goto fail; | |
569 | ||
570 | pci_wake_from_d3(efx->pci_dev, true); | |
571 | } else { | |
572 | rc = efx_mcdi_wol_filter_reset(efx); | |
573 | nic_data->wol_filter_id = -1; | |
574 | pci_wake_from_d3(efx->pci_dev, false); | |
575 | if (rc) | |
576 | goto fail; | |
577 | } | |
578 | ||
579 | return 0; | |
580 | fail: | |
62776d03 BH |
581 | netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n", |
582 | __func__, type, rc); | |
afd4aea0 BH |
583 | return rc; |
584 | } | |
585 | ||
586 | ||
587 | static void siena_init_wol(struct efx_nic *efx) | |
588 | { | |
589 | struct siena_nic_data *nic_data = efx->nic_data; | |
590 | int rc; | |
591 | ||
592 | rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); | |
593 | ||
594 | if (rc != 0) { | |
595 | /* If it failed, attempt to get into a synchronised | |
596 | * state with MC by resetting any set WoL filters */ | |
597 | efx_mcdi_wol_filter_reset(efx); | |
598 | nic_data->wol_filter_id = -1; | |
599 | } else if (nic_data->wol_filter_id != -1) { | |
600 | pci_wake_from_d3(efx->pci_dev, true); | |
601 | } | |
602 | } | |
603 | ||
604 | ||
605 | /************************************************************************** | |
606 | * | |
607 | * Revision-dependent attributes used by efx.c and nic.c | |
608 | * | |
609 | ************************************************************************** | |
610 | */ | |
611 | ||
612 | struct efx_nic_type siena_a0_nic_type = { | |
613 | .probe = siena_probe_nic, | |
614 | .remove = siena_remove_nic, | |
615 | .init = siena_init_nic, | |
616 | .fini = efx_port_dummy_op_void, | |
617 | .monitor = NULL, | |
618 | .reset = siena_reset_hw, | |
619 | .probe_port = siena_probe_port, | |
620 | .remove_port = siena_remove_port, | |
621 | .prepare_flush = efx_port_dummy_op_void, | |
622 | .update_stats = siena_update_nic_stats, | |
623 | .start_stats = siena_start_nic_stats, | |
624 | .stop_stats = siena_stop_nic_stats, | |
625 | .set_id_led = efx_mcdi_set_id_led, | |
626 | .push_irq_moderation = siena_push_irq_moderation, | |
627 | .push_multicast_hash = siena_push_multicast_hash, | |
628 | .reconfigure_port = efx_mcdi_phy_reconfigure, | |
629 | .get_wol = siena_get_wol, | |
630 | .set_wol = siena_set_wol, | |
631 | .resume_wol = siena_init_wol, | |
632 | .test_registers = siena_test_registers, | |
2e803407 | 633 | .test_nvram = efx_mcdi_nvram_test_all, |
afd4aea0 BH |
634 | .default_mac_ops = &efx_mcdi_mac_operations, |
635 | ||
636 | .revision = EFX_REV_SIENA_A0, | |
637 | .mem_map_size = (FR_CZ_MC_TREG_SMEM + | |
638 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS), | |
639 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
640 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
641 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
642 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
643 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
644 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), | |
39c9cf07 | 645 | .rx_buffer_hash_size = 0x10, |
afd4aea0 BH |
646 | .rx_buffer_padding = 0, |
647 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
648 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
649 | * interrupt handler only supports 32 | |
650 | * channels */ | |
651 | .tx_dc_base = 0x88000, | |
652 | .rx_dc_base = 0x68000, | |
39c9cf07 | 653 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
b4187e42 | 654 | NETIF_F_RXHASH | NETIF_F_NTUPLE), |
afd4aea0 BH |
655 | .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT, |
656 | }; |