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afd4aea0 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2009 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
d614cfbc | 16 | #include <linux/random.h> |
afd4aea0 BH |
17 | #include "net_driver.h" |
18 | #include "bitfield.h" | |
19 | #include "efx.h" | |
20 | #include "nic.h" | |
21 | #include "mac.h" | |
22 | #include "spi.h" | |
23 | #include "regs.h" | |
24 | #include "io.h" | |
25 | #include "phy.h" | |
26 | #include "workarounds.h" | |
27 | #include "mcdi.h" | |
28 | #include "mcdi_pcol.h" | |
29 | ||
30 | /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */ | |
31 | ||
32 | static void siena_init_wol(struct efx_nic *efx); | |
33 | ||
34 | ||
35 | static void siena_push_irq_moderation(struct efx_channel *channel) | |
36 | { | |
37 | efx_dword_t timer_cmd; | |
38 | ||
39 | if (channel->irq_moderation) | |
40 | EFX_POPULATE_DWORD_2(timer_cmd, | |
41 | FRF_CZ_TC_TIMER_MODE, | |
42 | FFE_CZ_TIMER_MODE_INT_HLDOFF, | |
43 | FRF_CZ_TC_TIMER_VAL, | |
44 | channel->irq_moderation - 1); | |
45 | else | |
46 | EFX_POPULATE_DWORD_2(timer_cmd, | |
47 | FRF_CZ_TC_TIMER_MODE, | |
48 | FFE_CZ_TIMER_MODE_DIS, | |
49 | FRF_CZ_TC_TIMER_VAL, 0); | |
50 | efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, | |
51 | channel->channel); | |
52 | } | |
53 | ||
54 | static void siena_push_multicast_hash(struct efx_nic *efx) | |
55 | { | |
56 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
57 | ||
58 | efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH, | |
59 | efx->multicast_hash.byte, sizeof(efx->multicast_hash), | |
60 | NULL, 0, NULL); | |
61 | } | |
62 | ||
63 | static int siena_mdio_write(struct net_device *net_dev, | |
64 | int prtad, int devad, u16 addr, u16 value) | |
65 | { | |
66 | struct efx_nic *efx = netdev_priv(net_dev); | |
67 | uint32_t status; | |
68 | int rc; | |
69 | ||
70 | rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad, | |
71 | addr, value, &status); | |
72 | if (rc) | |
73 | return rc; | |
74 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
75 | return -EIO; | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static int siena_mdio_read(struct net_device *net_dev, | |
81 | int prtad, int devad, u16 addr) | |
82 | { | |
83 | struct efx_nic *efx = netdev_priv(net_dev); | |
84 | uint16_t value; | |
85 | uint32_t status; | |
86 | int rc; | |
87 | ||
88 | rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad, | |
89 | addr, &value, &status); | |
90 | if (rc) | |
91 | return rc; | |
92 | if (status != MC_CMD_MDIO_STATUS_GOOD) | |
93 | return -EIO; | |
94 | ||
95 | return (int)value; | |
96 | } | |
97 | ||
98 | /* This call is responsible for hooking in the MAC and PHY operations */ | |
99 | static int siena_probe_port(struct efx_nic *efx) | |
100 | { | |
101 | int rc; | |
102 | ||
103 | /* Hook in PHY operations table */ | |
104 | efx->phy_op = &efx_mcdi_phy_ops; | |
105 | ||
106 | /* Set up MDIO structure for PHY */ | |
107 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
108 | efx->mdio.mdio_read = siena_mdio_read; | |
109 | efx->mdio.mdio_write = siena_mdio_write; | |
110 | ||
7a6b8f6f | 111 | /* Fill out MDIO structure, loopback modes, and initial link state */ |
afd4aea0 BH |
112 | rc = efx->phy_op->probe(efx); |
113 | if (rc != 0) | |
114 | return rc; | |
115 | ||
afd4aea0 BH |
116 | /* Allocate buffer for stats */ |
117 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, | |
118 | MC_CMD_MAC_NSTATS * sizeof(u64)); | |
119 | if (rc) | |
120 | return rc; | |
121 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", | |
122 | (u64)efx->stats_buffer.dma_addr, | |
123 | efx->stats_buffer.addr, | |
124 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
125 | ||
126 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1); | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | void siena_remove_port(struct efx_nic *efx) | |
132 | { | |
ff3b00a0 | 133 | efx->phy_op->remove(efx); |
afd4aea0 BH |
134 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
135 | } | |
136 | ||
137 | static const struct efx_nic_register_test siena_register_tests[] = { | |
138 | { FR_AZ_ADR_REGION, | |
4cddca54 | 139 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
afd4aea0 BH |
140 | { FR_CZ_USR_EV_CFG, |
141 | EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) }, | |
142 | { FR_AZ_RX_CFG, | |
143 | EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) }, | |
144 | { FR_AZ_TX_CFG, | |
145 | EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) }, | |
146 | { FR_AZ_TX_RESERVED, | |
147 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, | |
148 | { FR_AZ_SRM_TX_DC_CFG, | |
149 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, | |
150 | { FR_AZ_RX_DC_CFG, | |
151 | EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) }, | |
152 | { FR_AZ_RX_DC_PF_WM, | |
153 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, | |
154 | { FR_BZ_DP_CTRL, | |
155 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, | |
156 | { FR_BZ_RX_RSS_TKEY, | |
157 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
158 | { FR_CZ_RX_RSS_IPV6_REG1, | |
159 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
160 | { FR_CZ_RX_RSS_IPV6_REG2, | |
161 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) }, | |
162 | { FR_CZ_RX_RSS_IPV6_REG3, | |
163 | EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) }, | |
164 | }; | |
165 | ||
166 | static int siena_test_registers(struct efx_nic *efx) | |
167 | { | |
168 | return efx_nic_test_registers(efx, siena_register_tests, | |
169 | ARRAY_SIZE(siena_register_tests)); | |
170 | } | |
171 | ||
172 | /************************************************************************** | |
173 | * | |
174 | * Device reset | |
175 | * | |
176 | ************************************************************************** | |
177 | */ | |
178 | ||
179 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) | |
180 | { | |
8b2103ad SH |
181 | int rc; |
182 | ||
183 | /* Recover from a failed assertion pre-reset */ | |
184 | rc = efx_mcdi_handle_assertion(efx); | |
185 | if (rc) | |
186 | return rc; | |
afd4aea0 BH |
187 | |
188 | if (method == RESET_TYPE_WORLD) | |
189 | return efx_mcdi_reset_mc(efx); | |
190 | else | |
191 | return efx_mcdi_reset_port(efx); | |
192 | } | |
193 | ||
194 | static int siena_probe_nvconfig(struct efx_nic *efx) | |
195 | { | |
196 | int rc; | |
197 | ||
198 | rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL); | |
199 | if (rc) | |
200 | return rc; | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static int siena_probe_nic(struct efx_nic *efx) | |
206 | { | |
207 | struct siena_nic_data *nic_data; | |
208 | bool already_attached = 0; | |
dd8f61d7 | 209 | efx_oword_t reg; |
afd4aea0 BH |
210 | int rc; |
211 | ||
212 | /* Allocate storage for hardware specific data */ | |
213 | nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL); | |
214 | if (!nic_data) | |
215 | return -ENOMEM; | |
216 | efx->nic_data = nic_data; | |
217 | ||
218 | if (efx_nic_fpga_ver(efx) != 0) { | |
219 | EFX_ERR(efx, "Siena FPGA not supported\n"); | |
220 | rc = -ENODEV; | |
221 | goto fail1; | |
222 | } | |
223 | ||
dd8f61d7 BH |
224 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); |
225 | efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; | |
226 | ||
afd4aea0 BH |
227 | efx_mcdi_init(efx); |
228 | ||
229 | /* Recover from a failed assertion before probing */ | |
230 | rc = efx_mcdi_handle_assertion(efx); | |
231 | if (rc) | |
232 | goto fail1; | |
233 | ||
234 | rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build); | |
235 | if (rc) { | |
236 | EFX_ERR(efx, "Failed to read MCPU firmware version - " | |
237 | "rc %d\n", rc); | |
238 | goto fail1; /* MCPU absent? */ | |
239 | } | |
240 | ||
241 | /* Let the BMC know that the driver is now in charge of link and | |
242 | * filter settings. We must do this before we reset the NIC */ | |
243 | rc = efx_mcdi_drv_attach(efx, true, &already_attached); | |
244 | if (rc) { | |
245 | EFX_ERR(efx, "Unable to register driver with MCPU\n"); | |
246 | goto fail2; | |
247 | } | |
248 | if (already_attached) | |
249 | /* Not a fatal error */ | |
250 | EFX_ERR(efx, "Host already registered with MCPU\n"); | |
251 | ||
252 | /* Now we can reset the NIC */ | |
253 | rc = siena_reset_hw(efx, RESET_TYPE_ALL); | |
254 | if (rc) { | |
255 | EFX_ERR(efx, "failed to reset NIC\n"); | |
256 | goto fail3; | |
257 | } | |
258 | ||
259 | siena_init_wol(efx); | |
260 | ||
261 | /* Allocate memory for INT_KER */ | |
262 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
263 | if (rc) | |
264 | goto fail4; | |
265 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
266 | ||
267 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n", | |
268 | (unsigned long long)efx->irq_status.dma_addr, | |
269 | efx->irq_status.addr, | |
270 | (unsigned long long)virt_to_phys(efx->irq_status.addr)); | |
271 | ||
272 | /* Read in the non-volatile configuration */ | |
273 | rc = siena_probe_nvconfig(efx); | |
274 | if (rc == -EINVAL) { | |
275 | EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); | |
276 | efx->phy_type = PHY_TYPE_NONE; | |
277 | efx->mdio.prtad = MDIO_PRTAD_NONE; | |
278 | } else if (rc) { | |
279 | goto fail5; | |
280 | } | |
281 | ||
d614cfbc BH |
282 | get_random_bytes(&nic_data->ipv6_rss_key, |
283 | sizeof(nic_data->ipv6_rss_key)); | |
284 | ||
afd4aea0 BH |
285 | return 0; |
286 | ||
287 | fail5: | |
288 | efx_nic_free_buffer(efx, &efx->irq_status); | |
289 | fail4: | |
290 | fail3: | |
291 | efx_mcdi_drv_attach(efx, false, NULL); | |
292 | fail2: | |
293 | fail1: | |
294 | kfree(efx->nic_data); | |
295 | return rc; | |
296 | } | |
297 | ||
298 | /* This call performs hardware-specific global initialisation, such as | |
299 | * defining the descriptor cache sizes and number of RSS channels. | |
300 | * It does not set up any buffers, descriptor rings or event queues. | |
301 | */ | |
302 | static int siena_init_nic(struct efx_nic *efx) | |
303 | { | |
d614cfbc | 304 | struct siena_nic_data *nic_data = efx->nic_data; |
afd4aea0 BH |
305 | efx_oword_t temp; |
306 | int rc; | |
307 | ||
308 | /* Recover from a failed assertion post-reset */ | |
309 | rc = efx_mcdi_handle_assertion(efx); | |
310 | if (rc) | |
311 | return rc; | |
312 | ||
313 | /* Squash TX of packets of 16 bytes or less */ | |
314 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); | |
315 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); | |
316 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); | |
317 | ||
318 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
319 | * descriptors (which is bad). | |
320 | */ | |
321 | efx_reado(efx, &temp, FR_AZ_TX_CFG); | |
322 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); | |
323 | EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1); | |
324 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); | |
325 | ||
326 | efx_reado(efx, &temp, FR_AZ_RX_CFG); | |
327 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); | |
328 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); | |
329 | efx_writeo(efx, &temp, FR_AZ_RX_CFG); | |
330 | ||
d614cfbc BH |
331 | /* Enable IPv6 RSS */ |
332 | BUILD_BUG_ON(sizeof(nic_data->ipv6_rss_key) != | |
333 | 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 || | |
334 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0); | |
335 | memcpy(&temp, nic_data->ipv6_rss_key, sizeof(temp)); | |
336 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1); | |
337 | memcpy(&temp, nic_data->ipv6_rss_key + sizeof(temp), sizeof(temp)); | |
338 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2); | |
339 | EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1, | |
340 | FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1); | |
341 | memcpy(&temp, nic_data->ipv6_rss_key + 2 * sizeof(temp), | |
342 | FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); | |
343 | efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); | |
344 | ||
afd4aea0 BH |
345 | if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0) |
346 | /* No MCDI operation has been defined to set thresholds */ | |
347 | EFX_ERR(efx, "ignoring RX flow control thresholds\n"); | |
348 | ||
349 | /* Enable event logging */ | |
350 | rc = efx_mcdi_log_ctrl(efx, true, false, 0); | |
351 | if (rc) | |
352 | return rc; | |
353 | ||
354 | /* Set destination of both TX and RX Flush events */ | |
355 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); | |
356 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); | |
357 | ||
358 | EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1); | |
359 | efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG); | |
360 | ||
361 | efx_nic_init_common(efx); | |
362 | return 0; | |
363 | } | |
364 | ||
365 | static void siena_remove_nic(struct efx_nic *efx) | |
366 | { | |
367 | efx_nic_free_buffer(efx, &efx->irq_status); | |
368 | ||
369 | siena_reset_hw(efx, RESET_TYPE_ALL); | |
370 | ||
371 | /* Relinquish the device back to the BMC */ | |
372 | if (efx_nic_has_mc(efx)) | |
373 | efx_mcdi_drv_attach(efx, false, NULL); | |
374 | ||
375 | /* Tear down the private nic state */ | |
376 | kfree(efx->nic_data); | |
377 | efx->nic_data = NULL; | |
378 | } | |
379 | ||
380 | #define STATS_GENERATION_INVALID ((u64)(-1)) | |
381 | ||
382 | static int siena_try_update_nic_stats(struct efx_nic *efx) | |
383 | { | |
384 | u64 *dma_stats; | |
385 | struct efx_mac_stats *mac_stats; | |
386 | u64 generation_start; | |
387 | u64 generation_end; | |
388 | ||
389 | mac_stats = &efx->mac_stats; | |
390 | dma_stats = (u64 *)efx->stats_buffer.addr; | |
391 | ||
392 | generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; | |
393 | if (generation_end == STATS_GENERATION_INVALID) | |
394 | return 0; | |
395 | rmb(); | |
396 | ||
397 | #define MAC_STAT(M, D) \ | |
398 | mac_stats->M = dma_stats[MC_CMD_MAC_ ## D] | |
399 | ||
400 | MAC_STAT(tx_bytes, TX_BYTES); | |
401 | MAC_STAT(tx_bad_bytes, TX_BAD_BYTES); | |
402 | mac_stats->tx_good_bytes = (mac_stats->tx_bytes - | |
403 | mac_stats->tx_bad_bytes); | |
404 | MAC_STAT(tx_packets, TX_PKTS); | |
405 | MAC_STAT(tx_bad, TX_BAD_FCS_PKTS); | |
406 | MAC_STAT(tx_pause, TX_PAUSE_PKTS); | |
407 | MAC_STAT(tx_control, TX_CONTROL_PKTS); | |
408 | MAC_STAT(tx_unicast, TX_UNICAST_PKTS); | |
409 | MAC_STAT(tx_multicast, TX_MULTICAST_PKTS); | |
410 | MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS); | |
411 | MAC_STAT(tx_lt64, TX_LT64_PKTS); | |
412 | MAC_STAT(tx_64, TX_64_PKTS); | |
413 | MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS); | |
414 | MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS); | |
415 | MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS); | |
416 | MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS); | |
417 | MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS); | |
418 | MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS); | |
419 | MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS); | |
420 | mac_stats->tx_collision = 0; | |
421 | MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS); | |
422 | MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS); | |
423 | MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS); | |
424 | MAC_STAT(tx_deferred, TX_DEFERRED_PKTS); | |
425 | MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS); | |
426 | mac_stats->tx_collision = (mac_stats->tx_single_collision + | |
427 | mac_stats->tx_multiple_collision + | |
428 | mac_stats->tx_excessive_collision + | |
429 | mac_stats->tx_late_collision); | |
430 | MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS); | |
431 | MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS); | |
432 | MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS); | |
433 | MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS); | |
434 | MAC_STAT(rx_bytes, RX_BYTES); | |
435 | MAC_STAT(rx_bad_bytes, RX_BAD_BYTES); | |
436 | mac_stats->rx_good_bytes = (mac_stats->rx_bytes - | |
437 | mac_stats->rx_bad_bytes); | |
438 | MAC_STAT(rx_packets, RX_PKTS); | |
439 | MAC_STAT(rx_good, RX_GOOD_PKTS); | |
440 | mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good; | |
441 | MAC_STAT(rx_pause, RX_PAUSE_PKTS); | |
442 | MAC_STAT(rx_control, RX_CONTROL_PKTS); | |
443 | MAC_STAT(rx_unicast, RX_UNICAST_PKTS); | |
444 | MAC_STAT(rx_multicast, RX_MULTICAST_PKTS); | |
445 | MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS); | |
446 | MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS); | |
447 | MAC_STAT(rx_64, RX_64_PKTS); | |
448 | MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS); | |
449 | MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS); | |
450 | MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS); | |
451 | MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS); | |
452 | MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS); | |
453 | MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS); | |
454 | MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS); | |
455 | mac_stats->rx_bad_lt64 = 0; | |
456 | mac_stats->rx_bad_64_to_15xx = 0; | |
457 | mac_stats->rx_bad_15xx_to_jumbo = 0; | |
458 | MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS); | |
459 | MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS); | |
460 | mac_stats->rx_missed = 0; | |
461 | MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS); | |
462 | MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS); | |
463 | MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS); | |
464 | MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS); | |
465 | MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS); | |
466 | mac_stats->rx_good_lt64 = 0; | |
467 | ||
468 | efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]; | |
469 | ||
470 | #undef MAC_STAT | |
471 | ||
472 | rmb(); | |
473 | generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; | |
474 | if (generation_end != generation_start) | |
475 | return -EAGAIN; | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static void siena_update_nic_stats(struct efx_nic *efx) | |
481 | { | |
aabc5649 BH |
482 | int retry; |
483 | ||
484 | /* If we're unlucky enough to read statistics wduring the DMA, wait | |
485 | * up to 10ms for it to finish (typically takes <500us) */ | |
486 | for (retry = 0; retry < 100; ++retry) { | |
487 | if (siena_try_update_nic_stats(efx) == 0) | |
488 | return; | |
489 | udelay(100); | |
490 | } | |
491 | ||
492 | /* Use the old values instead */ | |
afd4aea0 BH |
493 | } |
494 | ||
495 | static void siena_start_nic_stats(struct efx_nic *efx) | |
496 | { | |
497 | u64 *dma_stats = (u64 *)efx->stats_buffer.addr; | |
498 | ||
499 | dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID; | |
500 | ||
501 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, | |
502 | MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0); | |
503 | } | |
504 | ||
505 | static void siena_stop_nic_stats(struct efx_nic *efx) | |
506 | { | |
507 | efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0); | |
508 | } | |
509 | ||
510 | void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len) | |
511 | { | |
512 | struct siena_nic_data *nic_data = efx->nic_data; | |
513 | snprintf(buf, len, "%u.%u.%u.%u", | |
514 | (unsigned int)(nic_data->fw_version >> 48), | |
515 | (unsigned int)(nic_data->fw_version >> 32 & 0xffff), | |
516 | (unsigned int)(nic_data->fw_version >> 16 & 0xffff), | |
517 | (unsigned int)(nic_data->fw_version & 0xffff)); | |
518 | } | |
519 | ||
520 | /************************************************************************** | |
521 | * | |
522 | * Wake on LAN | |
523 | * | |
524 | ************************************************************************** | |
525 | */ | |
526 | ||
527 | static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
528 | { | |
529 | struct siena_nic_data *nic_data = efx->nic_data; | |
530 | ||
531 | wol->supported = WAKE_MAGIC; | |
532 | if (nic_data->wol_filter_id != -1) | |
533 | wol->wolopts = WAKE_MAGIC; | |
534 | else | |
535 | wol->wolopts = 0; | |
536 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
537 | } | |
538 | ||
539 | ||
540 | static int siena_set_wol(struct efx_nic *efx, u32 type) | |
541 | { | |
542 | struct siena_nic_data *nic_data = efx->nic_data; | |
543 | int rc; | |
544 | ||
545 | if (type & ~WAKE_MAGIC) | |
546 | return -EINVAL; | |
547 | ||
548 | if (type & WAKE_MAGIC) { | |
549 | if (nic_data->wol_filter_id != -1) | |
550 | efx_mcdi_wol_filter_remove(efx, | |
551 | nic_data->wol_filter_id); | |
552 | rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address, | |
553 | &nic_data->wol_filter_id); | |
554 | if (rc) | |
555 | goto fail; | |
556 | ||
557 | pci_wake_from_d3(efx->pci_dev, true); | |
558 | } else { | |
559 | rc = efx_mcdi_wol_filter_reset(efx); | |
560 | nic_data->wol_filter_id = -1; | |
561 | pci_wake_from_d3(efx->pci_dev, false); | |
562 | if (rc) | |
563 | goto fail; | |
564 | } | |
565 | ||
566 | return 0; | |
567 | fail: | |
568 | EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc); | |
569 | return rc; | |
570 | } | |
571 | ||
572 | ||
573 | static void siena_init_wol(struct efx_nic *efx) | |
574 | { | |
575 | struct siena_nic_data *nic_data = efx->nic_data; | |
576 | int rc; | |
577 | ||
578 | rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id); | |
579 | ||
580 | if (rc != 0) { | |
581 | /* If it failed, attempt to get into a synchronised | |
582 | * state with MC by resetting any set WoL filters */ | |
583 | efx_mcdi_wol_filter_reset(efx); | |
584 | nic_data->wol_filter_id = -1; | |
585 | } else if (nic_data->wol_filter_id != -1) { | |
586 | pci_wake_from_d3(efx->pci_dev, true); | |
587 | } | |
588 | } | |
589 | ||
590 | ||
591 | /************************************************************************** | |
592 | * | |
593 | * Revision-dependent attributes used by efx.c and nic.c | |
594 | * | |
595 | ************************************************************************** | |
596 | */ | |
597 | ||
598 | struct efx_nic_type siena_a0_nic_type = { | |
599 | .probe = siena_probe_nic, | |
600 | .remove = siena_remove_nic, | |
601 | .init = siena_init_nic, | |
602 | .fini = efx_port_dummy_op_void, | |
603 | .monitor = NULL, | |
604 | .reset = siena_reset_hw, | |
605 | .probe_port = siena_probe_port, | |
606 | .remove_port = siena_remove_port, | |
607 | .prepare_flush = efx_port_dummy_op_void, | |
608 | .update_stats = siena_update_nic_stats, | |
609 | .start_stats = siena_start_nic_stats, | |
610 | .stop_stats = siena_stop_nic_stats, | |
611 | .set_id_led = efx_mcdi_set_id_led, | |
612 | .push_irq_moderation = siena_push_irq_moderation, | |
613 | .push_multicast_hash = siena_push_multicast_hash, | |
614 | .reconfigure_port = efx_mcdi_phy_reconfigure, | |
615 | .get_wol = siena_get_wol, | |
616 | .set_wol = siena_set_wol, | |
617 | .resume_wol = siena_init_wol, | |
618 | .test_registers = siena_test_registers, | |
2e803407 | 619 | .test_nvram = efx_mcdi_nvram_test_all, |
afd4aea0 BH |
620 | .default_mac_ops = &efx_mcdi_mac_operations, |
621 | ||
622 | .revision = EFX_REV_SIENA_A0, | |
623 | .mem_map_size = (FR_CZ_MC_TREG_SMEM + | |
624 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS), | |
625 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
626 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
627 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
628 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
629 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
630 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), | |
631 | .rx_buffer_padding = 0, | |
632 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
633 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
634 | * interrupt handler only supports 32 | |
635 | * channels */ | |
636 | .tx_dc_base = 0x88000, | |
637 | .rx_dc_base = 0x68000, | |
638 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM, | |
639 | .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT, | |
640 | }; |