Commit | Line | Data |
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8ceee660 | 1 | /**************************************************************************** |
177dfcd8 BH |
2 | * Driver for Solarflare Solarstorm network controllers and boards |
3 | * Copyright 2007-2008 Solarflare Communications Inc. | |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 BH |
12 | #include <linux/seq_file.h> |
13 | #include "efx.h" | |
8ceee660 BH |
14 | #include "mdio_10g.h" |
15 | #include "falcon.h" | |
16 | #include "phy.h" | |
17 | #include "falcon_hwdefs.h" | |
18 | #include "boards.h" | |
e6fa2eb7 BH |
19 | #include "workarounds.h" |
20 | #include "selftest.h" | |
8ceee660 | 21 | |
e6fa2eb7 BH |
22 | /* We expect these MMDs to be in the package. SFT9001 also has a |
23 | * clause 22 extension MMD, but since it doesn't have all the generic | |
24 | * MMD registers it is pointless to include it here. | |
25 | */ | |
27dd2cac BH |
26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \ |
27 | MDIO_MMDREG_DEVS_PCS | \ | |
04cc8cac BH |
28 | MDIO_MMDREG_DEVS_PHYXS | \ |
29 | MDIO_MMDREG_DEVS_AN) | |
8ceee660 | 30 | |
e6fa2eb7 BH |
31 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
32 | (1 << LOOPBACK_PCS) | \ | |
33 | (1 << LOOPBACK_PMAPMD) | \ | |
34 | (1 << LOOPBACK_NETWORK)) | |
35 | ||
36 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
37 | (1 << LOOPBACK_PHYXS) | \ | |
38 | (1 << LOOPBACK_PCS) | \ | |
39 | (1 << LOOPBACK_PMAPMD) | \ | |
40 | (1 << LOOPBACK_NETWORK)) | |
3273c2e8 | 41 | |
8ceee660 BH |
42 | /* We complain if we fail to see the link partner as 10G capable this many |
43 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
44 | */ | |
45 | #define MAX_BAD_LP_TRIES (5) | |
46 | ||
e6fa2eb7 BH |
47 | /* LASI Control */ |
48 | #define PMA_PMD_LASI_CTRL 36866 | |
49 | #define PMA_PMD_LASI_STATUS 36869 | |
50 | #define PMA_PMD_LS_ALARM_LBN 0 | |
51 | #define PMA_PMD_LS_ALARM_WIDTH 1 | |
52 | #define PMA_PMD_TX_ALARM_LBN 1 | |
53 | #define PMA_PMD_TX_ALARM_WIDTH 1 | |
54 | #define PMA_PMD_RX_ALARM_LBN 2 | |
55 | #define PMA_PMD_RX_ALARM_WIDTH 1 | |
56 | #define PMA_PMD_AN_ALARM_LBN 3 | |
57 | #define PMA_PMD_AN_ALARM_WIDTH 1 | |
58 | ||
8ceee660 | 59 | /* Extended control register */ |
e6fa2eb7 BH |
60 | #define PMA_PMD_XCONTROL_REG 49152 |
61 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
62 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
63 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
64 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
65 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
66 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
67 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
68 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
69 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
70 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
71 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
72 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
73 | #define PMA_PMD_EXT_SSR_LBN 15 |
74 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
75 | |
76 | /* extended status register */ | |
e6fa2eb7 | 77 | #define PMA_PMD_XSTATUS_REG 49153 |
8ceee660 BH |
78 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
79 | ||
80 | /* LED control register */ | |
e6fa2eb7 | 81 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
82 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
83 | ||
84 | /* LED function override register */ | |
e6fa2eb7 | 85 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
86 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
87 | #define PMA_PMD_LED_LINK_LBN (0) | |
88 | #define PMA_PMD_LED_SPEED_LBN (2) | |
89 | #define PMA_PMD_LED_TX_LBN (4) | |
90 | #define PMA_PMD_LED_RX_LBN (6) | |
91 | /* Override settings */ | |
92 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
93 | #define PMA_PMD_LED_ON (1) | |
94 | #define PMA_PMD_LED_OFF (2) | |
95 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 96 | #define PMA_PMD_LED_MASK 3 |
8ceee660 BH |
97 | /* All LEDs under hardware control */ |
98 | #define PMA_PMD_LED_FULL_AUTO (0) | |
99 | /* Green and Amber under hardware control, Red off */ | |
100 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | |
101 | ||
e6fa2eb7 BH |
102 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
103 | #define PMA_PMD_100TX_ADV_LBN 1 | |
104 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
105 | #define PMA_PMD_1000T_ADV_LBN 2 | |
106 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
107 | #define PMA_PMD_10000T_ADV_LBN 3 | |
108 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
109 | #define PMA_PMD_SPEED_LBN 4 | |
110 | #define PMA_PMD_SPEED_WIDTH 4 | |
111 | ||
307505e9 BH |
112 | /* Cable diagnostics - SFT9001 only */ |
113 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
114 | #define CDIAG_CTRL_IMMED_LBN 15 | |
115 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
116 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
117 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
118 | #define CDIAG_CTRL_LEN_METRES 1 | |
119 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
120 | #define CDIAG_RES_A_LBN 12 | |
121 | #define CDIAG_RES_B_LBN 8 | |
122 | #define CDIAG_RES_C_LBN 4 | |
123 | #define CDIAG_RES_D_LBN 0 | |
124 | #define CDIAG_RES_WIDTH 4 | |
125 | #define CDIAG_RES_OPEN 2 | |
126 | #define CDIAG_RES_OK 1 | |
127 | #define CDIAG_RES_INVALID 0 | |
128 | /* Set of 4 registers for pairs A-D */ | |
129 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
130 | ||
e6fa2eb7 BH |
131 | /* Serdes control registers - SFT9001 only */ |
132 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
133 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
134 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
135 | ||
136 | /* Misc register defines - SFX7101 only */ | |
137 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
138 | #define PLL312_RST_N_LBN 2 |
139 | ||
e6fa2eb7 | 140 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
141 | #define SERDES_RST_N_LBN 13 |
142 | #define XGXS_RST_N_LBN 12 | |
143 | ||
e6fa2eb7 | 144 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
145 | #define CLK312_EN_LBN 3 |
146 | ||
3273c2e8 | 147 | /* PHYXS registers */ |
e6fa2eb7 BH |
148 | #define PHYXS_XCONTROL_REG 49152 |
149 | #define PHYXS_RESET_LBN 15 | |
150 | #define PHYXS_RESET_WIDTH 1 | |
151 | ||
3273c2e8 BH |
152 | #define PHYXS_TEST1 (49162) |
153 | #define LOOPBACK_NEAR_LBN (8) | |
154 | #define LOOPBACK_NEAR_WIDTH (1) | |
155 | ||
e6fa2eb7 BH |
156 | #define PCS_10GBASET_STAT1 32 |
157 | #define PCS_10GBASET_BLKLK_LBN 0 | |
158 | #define PCS_10GBASET_BLKLK_WIDTH 1 | |
159 | ||
8ceee660 | 160 | /* Boot status register */ |
190dbcfd BH |
161 | #define PCS_BOOT_STATUS_REG 53248 |
162 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
163 | #define PCS_BOOT_PROGRESS_LBN 1 | |
164 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
165 | #define PCS_BOOT_PROGRESS_INIT 0 | |
166 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
167 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
168 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
169 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
170 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 171 | |
e6fa2eb7 BH |
172 | /* 100M/1G PHY registers */ |
173 | #define GPHY_XCONTROL_REG 49152 | |
174 | #define GPHY_ISOLATE_LBN 10 | |
175 | #define GPHY_ISOLATE_WIDTH 1 | |
176 | #define GPHY_DUPLEX_LBN 8 | |
177 | #define GPHY_DUPLEX_WIDTH 1 | |
178 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
179 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
180 | ||
181 | #define C22EXT_STATUS_REG 49153 | |
182 | #define C22EXT_STATUS_LINK_LBN 2 | |
183 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
184 | ||
af4ad9bc BH |
185 | #define C22EXT_MSTSLV_CTRL 49161 |
186 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
187 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
188 | ||
189 | #define C22EXT_MSTSLV_STATUS 49162 | |
190 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
191 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 192 | |
8ceee660 BH |
193 | /* Time to wait between powering down the LNPGA and turning off the power |
194 | * rails */ | |
195 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
196 | ||
8ceee660 | 197 | struct tenxpress_phy_data { |
3273c2e8 | 198 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 199 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
200 | int bad_lp_tries; |
201 | }; | |
202 | ||
e6fa2eb7 BH |
203 | static ssize_t show_phy_short_reach(struct device *dev, |
204 | struct device_attribute *attr, char *buf) | |
205 | { | |
206 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
207 | int reg; | |
208 | ||
209 | reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
210 | MDIO_PMAPMD_10GBT_TXPWR); | |
211 | return sprintf(buf, "%d\n", | |
212 | !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN))); | |
213 | } | |
214 | ||
215 | static ssize_t set_phy_short_reach(struct device *dev, | |
216 | struct device_attribute *attr, | |
217 | const char *buf, size_t count) | |
218 | { | |
219 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
220 | ||
221 | rtnl_lock(); | |
222 | mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
223 | MDIO_PMAPMD_10GBT_TXPWR, | |
224 | MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN, | |
225 | count != 0 && *buf != '0'); | |
226 | efx_reconfigure_port(efx); | |
227 | rtnl_unlock(); | |
228 | ||
229 | return count; | |
230 | } | |
231 | ||
232 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
233 | set_phy_short_reach); | |
234 | ||
190dbcfd | 235 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 236 | { |
190dbcfd | 237 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
238 | int boot_stat; |
239 | ||
190dbcfd BH |
240 | for (;;) { |
241 | boot_stat = mdio_clause45_read(efx, efx->mii.phy_id, | |
8ceee660 BH |
242 | MDIO_MMD_PCS, |
243 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
244 | if (boot_stat >= 0) { |
245 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
246 | switch (boot_stat & | |
247 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
248 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
249 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
250 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
251 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
252 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
253 | PCS_BOOT_PROGRESS_LBN)): | |
254 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
255 | (PCS_BOOT_PROGRESS_INIT << | |
256 | PCS_BOOT_PROGRESS_LBN) | | |
257 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
258 | return -EINVAL; | |
259 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
260 | PCS_BOOT_PROGRESS_LBN) | | |
261 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
262 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
263 | 0 : -EIO; | |
264 | case ((PCS_BOOT_PROGRESS_JUMP << | |
265 | PCS_BOOT_PROGRESS_LBN) | | |
266 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
267 | case ((PCS_BOOT_PROGRESS_JUMP << | |
268 | PCS_BOOT_PROGRESS_LBN) | | |
269 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
270 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
271 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
272 | -EIO : 0; | |
273 | default: | |
274 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
275 | return -EIO; | |
276 | break; | |
277 | } | |
278 | } | |
279 | ||
280 | if (time_after_eq(jiffies, timeout)) | |
281 | return -ETIMEDOUT; | |
282 | ||
283 | msleep(50); | |
8ceee660 | 284 | } |
8ceee660 BH |
285 | } |
286 | ||
8ceee660 BH |
287 | static int tenxpress_init(struct efx_nic *efx) |
288 | { | |
e6fa2eb7 BH |
289 | int phy_id = efx->mii.phy_id; |
290 | int reg; | |
8ceee660 | 291 | |
e6fa2eb7 BH |
292 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
293 | /* Enable 312.5 MHz clock */ | |
294 | mdio_clause45_write(efx, phy_id, | |
295 | MDIO_MMD_PCS, PCS_TEST_SELECT_REG, | |
296 | 1 << CLK312_EN_LBN); | |
297 | } else { | |
298 | /* Enable 312.5 MHz clock and GMII */ | |
299 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
300 | PMA_PMD_XCONTROL_REG); | |
301 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | | |
302 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
303 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
304 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
305 | ||
e6fa2eb7 BH |
306 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, |
307 | PMA_PMD_XCONTROL_REG, reg); | |
308 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | |
309 | GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN, | |
310 | false); | |
311 | } | |
8ceee660 | 312 | |
8ceee660 | 313 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 BH |
314 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
315 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD, | |
316 | PMA_PMD_LED_CTRL_REG, | |
317 | PMA_PMA_LED_ACTIVITY_LBN, | |
318 | true); | |
319 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | |
320 | PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT); | |
321 | } | |
8ceee660 | 322 | |
190dbcfd | 323 | return 0; |
8ceee660 BH |
324 | } |
325 | ||
326 | static int tenxpress_phy_init(struct efx_nic *efx) | |
327 | { | |
328 | struct tenxpress_phy_data *phy_data; | |
329 | int rc = 0; | |
330 | ||
331 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
9b7bfc4c BH |
332 | if (!phy_data) |
333 | return -ENOMEM; | |
8ceee660 | 334 | efx->phy_data = phy_data; |
f8b87c17 | 335 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 336 | |
e6fa2eb7 BH |
337 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
338 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
339 | int reg; | |
340 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
341 | MDIO_MMD_PMAPMD, | |
342 | PMA_PMD_XCONTROL_REG); | |
343 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); | |
344 | mdio_clause45_write(efx, efx->mii.phy_id, | |
345 | MDIO_MMD_PMAPMD, | |
346 | PMA_PMD_XCONTROL_REG, reg); | |
347 | mdelay(200); | |
348 | } | |
8ceee660 | 349 | |
e6fa2eb7 BH |
350 | rc = mdio_clause45_wait_reset_mmds(efx, |
351 | TENXPRESS_REQUIRED_DEVS); | |
352 | if (rc < 0) | |
353 | goto fail; | |
354 | ||
355 | rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); | |
356 | if (rc < 0) | |
357 | goto fail; | |
358 | } | |
8ceee660 BH |
359 | |
360 | rc = tenxpress_init(efx); | |
361 | if (rc < 0) | |
362 | goto fail; | |
4b988280 | 363 | mdio_clause45_set_pause(efx); |
8ceee660 | 364 | |
e6fa2eb7 BH |
365 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
366 | rc = device_create_file(&efx->pci_dev->dev, | |
367 | &dev_attr_phy_short_reach); | |
368 | if (rc) | |
369 | goto fail; | |
370 | } | |
371 | ||
8ceee660 BH |
372 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
373 | ||
e6fa2eb7 | 374 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
375 | falcon_reset_xaui(efx); |
376 | ||
377 | return 0; | |
378 | ||
379 | fail: | |
380 | kfree(efx->phy_data); | |
381 | efx->phy_data = NULL; | |
382 | return rc; | |
383 | } | |
384 | ||
e6fa2eb7 BH |
385 | /* Perform a "special software reset" on the PHY. The caller is |
386 | * responsible for saving and restoring the PHY hardware registers | |
387 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
388 | static int tenxpress_special_reset(struct efx_nic *efx) |
389 | { | |
390 | int rc, reg; | |
391 | ||
c8fcc49c BH |
392 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
393 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 BH |
394 | * requests to fail. */ |
395 | efx_stats_disable(efx); | |
3273c2e8 BH |
396 | |
397 | /* Initiate reset */ | |
398 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
e6fa2eb7 | 399 | MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 BH |
400 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
401 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
e6fa2eb7 | 402 | PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 403 | |
c8fcc49c | 404 | mdelay(200); |
3273c2e8 BH |
405 | |
406 | /* Wait for the blocks to come out of reset */ | |
407 | rc = mdio_clause45_wait_reset_mmds(efx, | |
408 | TENXPRESS_REQUIRED_DEVS); | |
409 | if (rc < 0) | |
1974cc20 | 410 | goto out; |
3273c2e8 BH |
411 | |
412 | /* Try and reconfigure the device */ | |
413 | rc = tenxpress_init(efx); | |
414 | if (rc < 0) | |
1974cc20 | 415 | goto out; |
3273c2e8 | 416 | |
e6fa2eb7 BH |
417 | /* Wait for the XGXS state machine to churn */ |
418 | mdelay(10); | |
1974cc20 BH |
419 | out: |
420 | efx_stats_enable(efx); | |
c8fcc49c | 421 | return rc; |
3273c2e8 BH |
422 | } |
423 | ||
e6fa2eb7 | 424 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
425 | { |
426 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac BH |
427 | int phy_id = efx->mii.phy_id; |
428 | bool bad_lp; | |
8ceee660 BH |
429 | int reg; |
430 | ||
04cc8cac BH |
431 | if (link_ok) { |
432 | bad_lp = false; | |
433 | } else { | |
434 | /* Check that AN has started but not completed. */ | |
435 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | |
436 | MDIO_AN_STATUS); | |
437 | if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN))) | |
438 | return; /* LP status is unknown */ | |
439 | bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN)); | |
440 | if (bad_lp) | |
441 | pd->bad_lp_tries++; | |
442 | } | |
443 | ||
8ceee660 | 444 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 445 | if (!pd->bad_lp_tries) |
8ceee660 BH |
446 | return; |
447 | ||
04cc8cac BH |
448 | /* Use the RX (red) LED as an error indicator once we've seen AN |
449 | * failure several times in a row, and also log a message. */ | |
450 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
451 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
452 | PMA_PMD_LED_OVERR_REG); | |
453 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); | |
454 | if (!bad_lp) { | |
455 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
456 | } else { | |
457 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
458 | EFX_ERR(efx, "appears to be plugged into a port" | |
459 | " that is not 10GBASE-T capable. The PHY" | |
460 | " supports 10GBASE-T ONLY, so no link can" | |
461 | " be established\n"); | |
462 | } | |
463 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | |
464 | PMA_PMD_LED_OVERR_REG, reg); | |
465 | pd->bad_lp_tries = bad_lp; | |
8ceee660 | 466 | } |
8ceee660 BH |
467 | } |
468 | ||
e6fa2eb7 | 469 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 470 | { |
e6fa2eb7 BH |
471 | return mdio_clause45_links_ok(efx, |
472 | MDIO_MMDREG_DEVS_PMAPMD | | |
473 | MDIO_MMDREG_DEVS_PCS | | |
474 | MDIO_MMDREG_DEVS_PHYXS); | |
475 | } | |
476 | ||
477 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
478 | { | |
479 | int phy_id = efx->mii.phy_id; | |
480 | u32 reg; | |
481 | ||
caa8d8bb | 482 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 483 | return false; |
caa8d8bb BH |
484 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
485 | return true; | |
e6fa2eb7 | 486 | else if (efx->loopback_mode) |
04cc8cac BH |
487 | return mdio_clause45_links_ok(efx, |
488 | MDIO_MMDREG_DEVS_PMAPMD | | |
04cc8cac | 489 | MDIO_MMDREG_DEVS_PHYXS); |
e6fa2eb7 BH |
490 | |
491 | /* We must use the same definition of link state as LASI, | |
492 | * otherwise we can miss a link state transition | |
493 | */ | |
494 | if (ecmd->speed == 10000) { | |
495 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, | |
496 | PCS_10GBASET_STAT1); | |
497 | return reg & (1 << PCS_10GBASET_BLKLK_LBN); | |
498 | } else { | |
499 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | |
500 | C22EXT_STATUS_REG); | |
501 | return reg & (1 << C22EXT_STATUS_LINK_LBN); | |
502 | } | |
8ceee660 BH |
503 | } |
504 | ||
e6fa2eb7 | 505 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 BH |
506 | { |
507 | int phy_id = efx->mii.phy_id; | |
3273c2e8 | 508 | |
e6fa2eb7 BH |
509 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS, |
510 | PHYXS_TEST1, LOOPBACK_NEAR_LBN, | |
511 | efx->loopback_mode == LOOPBACK_PHYXS); | |
512 | if (efx->phy_type != PHY_TYPE_SFX7101) | |
513 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | |
514 | GPHY_XCONTROL_REG, | |
515 | GPHY_LOOPBACK_NEAR_LBN, | |
516 | efx->loopback_mode == LOOPBACK_GPHY); | |
517 | } | |
518 | ||
519 | static void tenxpress_low_power(struct efx_nic *efx) | |
520 | { | |
521 | int phy_id = efx->mii.phy_id; | |
522 | ||
523 | if (efx->phy_type == PHY_TYPE_SFX7101) | |
524 | mdio_clause45_set_mmds_lpower( | |
525 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), | |
526 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 527 | else |
e6fa2eb7 BH |
528 | mdio_clause45_set_flag( |
529 | efx, phy_id, MDIO_MMD_PMAPMD, | |
530 | PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN, | |
531 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); | |
3273c2e8 BH |
532 | } |
533 | ||
8ceee660 BH |
534 | static void tenxpress_phy_reconfigure(struct efx_nic *efx) |
535 | { | |
3273c2e8 | 536 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
e6fa2eb7 | 537 | struct ethtool_cmd ecmd; |
8b9dc8dd | 538 | bool phy_mode_change, loop_reset; |
3273c2e8 | 539 | |
e6fa2eb7 | 540 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 541 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 542 | return; |
f8b87c17 | 543 | } |
8ceee660 | 544 | |
e6fa2eb7 BH |
545 | tenxpress_low_power(efx); |
546 | ||
547 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && | |
548 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
e6fa2eb7 BH |
549 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) || |
550 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); | |
551 | ||
8b9dc8dd | 552 | if (loop_reset || phy_mode_change) { |
e6fa2eb7 BH |
553 | int rc; |
554 | ||
555 | efx->phy_op->get_settings(efx, &ecmd); | |
556 | ||
557 | if (loop_reset || phy_mode_change) { | |
558 | tenxpress_special_reset(efx); | |
559 | ||
560 | /* Reset XAUI if we were in 10G, and are staying | |
561 | * in 10G. If we're moving into and out of 10G | |
562 | * then xaui will be reset anyway */ | |
563 | if (EFX_IS10G(efx)) | |
564 | falcon_reset_xaui(efx); | |
565 | } | |
566 | ||
e6fa2eb7 BH |
567 | rc = efx->phy_op->set_settings(efx, &ecmd); |
568 | WARN_ON(rc); | |
3273c2e8 BH |
569 | } |
570 | ||
571 | mdio_clause45_transmit_disable(efx); | |
572 | mdio_clause45_phy_reconfigure(efx); | |
e6fa2eb7 | 573 | tenxpress_ext_loopback(efx); |
3273c2e8 | 574 | |
3273c2e8 | 575 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 576 | phy_data->phy_mode = efx->phy_mode; |
e6fa2eb7 BH |
577 | |
578 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
579 | efx->link_speed = 10000; | |
580 | efx->link_fd = true; | |
581 | efx->link_up = sfx7101_link_ok(efx); | |
582 | } else { | |
583 | efx->phy_op->get_settings(efx, &ecmd); | |
584 | efx->link_speed = ecmd.speed; | |
585 | efx->link_fd = ecmd.duplex == DUPLEX_FULL; | |
586 | efx->link_up = sft9001_link_ok(efx, &ecmd); | |
587 | } | |
04cc8cac | 588 | efx->link_fc = mdio_clause45_get_pause(efx); |
8ceee660 BH |
589 | } |
590 | ||
8ceee660 | 591 | /* Poll PHY for interrupt */ |
766ca0fa | 592 | static void tenxpress_phy_poll(struct efx_nic *efx) |
8ceee660 BH |
593 | { |
594 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
37d37695 | 595 | bool change = false; |
8ceee660 | 596 | |
e6fa2eb7 | 597 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
37d37695 | 598 | bool link_ok = sfx7101_link_ok(efx); |
e6fa2eb7 BH |
599 | if (link_ok != efx->link_up) { |
600 | change = true; | |
601 | } else { | |
37d37695 | 602 | unsigned int link_fc = mdio_clause45_get_pause(efx); |
e6fa2eb7 BH |
603 | if (link_fc != efx->link_fc) |
604 | change = true; | |
605 | } | |
606 | sfx7101_check_bad_lp(efx, link_ok); | |
caa8d8bb BH |
607 | } else if (efx->loopback_mode) { |
608 | bool link_ok = sft9001_link_ok(efx, NULL); | |
609 | if (link_ok != efx->link_up) | |
610 | change = true; | |
766ca0fa | 611 | } else { |
e6fa2eb7 BH |
612 | u32 status = mdio_clause45_read(efx, efx->mii.phy_id, |
613 | MDIO_MMD_PMAPMD, | |
614 | PMA_PMD_LASI_STATUS); | |
615 | if (status & (1 << PMA_PMD_LS_ALARM_LBN)) | |
766ca0fa BH |
616 | change = true; |
617 | } | |
8ceee660 | 618 | |
766ca0fa | 619 | if (change) |
177dfcd8 | 620 | falcon_sim_phy_event(efx); |
8ceee660 | 621 | |
f8b87c17 | 622 | if (phy_data->phy_mode != PHY_MODE_NORMAL) |
766ca0fa | 623 | return; |
8ceee660 BH |
624 | } |
625 | ||
626 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
627 | { | |
628 | int reg; | |
629 | ||
2a7e637d | 630 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
631 | device_remove_file(&efx->pci_dev->dev, |
632 | &dev_attr_phy_short_reach); | |
2a7e637d BH |
633 | |
634 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
e6fa2eb7 BH |
635 | /* Power down the LNPGA */ |
636 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
637 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
638 | PMA_PMD_XCONTROL_REG, reg); | |
639 | ||
640 | /* Waiting here ensures that the board fini, which can turn | |
641 | * off the power to the PHY, won't get run until the LNPGA | |
642 | * powerdown has been given long enough to complete. */ | |
643 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
644 | } | |
8ceee660 BH |
645 | |
646 | kfree(efx->phy_data); | |
647 | efx->phy_data = NULL; | |
648 | } | |
649 | ||
650 | ||
651 | /* Set the RX and TX LEDs and Link LED flashing. The other LEDs | |
652 | * (which probably aren't wired anyway) are left in AUTO mode */ | |
dc8cfa55 | 653 | void tenxpress_phy_blink(struct efx_nic *efx, bool blink) |
8ceee660 BH |
654 | { |
655 | int reg; | |
656 | ||
657 | if (blink) | |
658 | reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) | | |
659 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) | | |
660 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN); | |
661 | else | |
662 | reg = PMA_PMD_LED_DEFAULT; | |
663 | ||
664 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
665 | PMA_PMD_LED_OVERR_REG, reg); | |
666 | } | |
667 | ||
307505e9 | 668 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
669 | "bist" |
670 | }; | |
671 | ||
672 | static int | |
307505e9 | 673 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 674 | { |
1796721a BH |
675 | int rc; |
676 | ||
677 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
678 | return 0; | |
679 | ||
8c8661e4 | 680 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
681 | rc = tenxpress_special_reset(efx); |
682 | results[0] = rc ? -1 : 1; | |
683 | return rc; | |
8c8661e4 BH |
684 | } |
685 | ||
307505e9 BH |
686 | static const char *const sft9001_test_names[] = { |
687 | "bist", | |
688 | "cable.pairA.status", | |
689 | "cable.pairB.status", | |
690 | "cable.pairC.status", | |
691 | "cable.pairD.status", | |
692 | "cable.pairA.length", | |
693 | "cable.pairB.length", | |
694 | "cable.pairC.length", | |
695 | "cable.pairD.length", | |
696 | }; | |
697 | ||
698 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |
699 | { | |
700 | struct ethtool_cmd ecmd; | |
701 | int phy_id = efx->mii.phy_id; | |
22ef02c2 | 702 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 703 | |
22ef02c2 BH |
704 | if (flags & ETH_TEST_FL_OFFLINE) |
705 | efx->phy_op->get_settings(efx, &ecmd); | |
307505e9 BH |
706 | |
707 | /* Initialise cable diagnostic results to unknown failure */ | |
708 | for (i = 1; i < 9; ++i) | |
709 | results[i] = -1; | |
710 | ||
711 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
712 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
713 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
714 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
715 | if (flags & ETH_TEST_FL_OFFLINE) { | |
716 | /* Break the link in order to run full diagnostics. We | |
717 | * must reset the PHY to resume normal service. */ | |
718 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
719 | } | |
307505e9 | 720 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, |
22ef02c2 | 721 | PMA_PMD_CDIAG_CTRL_REG, ctrl_reg); |
307505e9 BH |
722 | i = 0; |
723 | while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | |
724 | PMA_PMD_CDIAG_CTRL_REG) & | |
725 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { | |
726 | if (++i == 50) { | |
727 | rc = -ETIMEDOUT; | |
22ef02c2 | 728 | goto out; |
307505e9 BH |
729 | } |
730 | msleep(100); | |
731 | } | |
732 | res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | |
733 | PMA_PMD_CDIAG_RES_REG); | |
734 | for (i = 0; i < 4; i++) { | |
735 | int pair_res = | |
736 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
737 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
738 | int len_reg = mdio_clause45_read(efx, efx->mii.phy_id, | |
739 | MDIO_MMD_PMAPMD, | |
740 | PMA_PMD_CDIAG_LEN_REG + i); | |
741 | if (pair_res == CDIAG_RES_OK) | |
742 | results[1 + i] = 1; | |
743 | else if (pair_res == CDIAG_RES_INVALID) | |
744 | results[1 + i] = -1; | |
745 | else | |
746 | results[1 + i] = -pair_res; | |
747 | if (pair_res != CDIAG_RES_INVALID && | |
748 | pair_res != CDIAG_RES_OPEN && | |
749 | len_reg != 0xffff) | |
750 | results[5 + i] = len_reg; | |
751 | } | |
752 | ||
22ef02c2 BH |
753 | out: |
754 | if (flags & ETH_TEST_FL_OFFLINE) { | |
755 | /* Reset, running the BIST and then resuming normal service. */ | |
756 | rc2 = tenxpress_special_reset(efx); | |
757 | results[0] = rc2 ? -1 : 1; | |
758 | if (!rc) | |
759 | rc = rc2; | |
760 | ||
761 | rc2 = efx->phy_op->set_settings(efx, &ecmd); | |
762 | if (!rc) | |
763 | rc = rc2; | |
764 | } | |
307505e9 BH |
765 | |
766 | return rc; | |
767 | } | |
768 | ||
af4ad9bc BH |
769 | static void |
770 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 771 | { |
af4ad9bc BH |
772 | int phy_id = efx->mii.phy_id; |
773 | u32 adv = 0, lpa = 0; | |
04cc8cac BH |
774 | int reg; |
775 | ||
e6fa2eb7 | 776 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
af4ad9bc BH |
777 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, |
778 | C22EXT_MSTSLV_CTRL); | |
779 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) | |
780 | adv |= ADVERTISED_1000baseT_Full; | |
781 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | |
782 | C22EXT_MSTSLV_STATUS); | |
783 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) | |
e6fa2eb7 | 784 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 785 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
786 | lpa |= ADVERTISED_1000baseT_Full; |
787 | } | |
af4ad9bc BH |
788 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, |
789 | MDIO_AN_10GBT_CTRL); | |
790 | if (reg & (1 << MDIO_AN_10GBT_CTRL_ADV_10G_LBN)) | |
791 | adv |= ADVERTISED_10000baseT_Full; | |
792 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | |
793 | MDIO_AN_10GBT_STATUS); | |
04cc8cac BH |
794 | if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN)) |
795 | lpa |= ADVERTISED_10000baseT_Full; | |
04cc8cac | 796 | |
af4ad9bc | 797 | mdio_clause45_get_settings_ext(efx, ecmd, adv, lpa); |
e6fa2eb7 | 798 | |
af4ad9bc BH |
799 | if (efx->phy_type != PHY_TYPE_SFX7101) |
800 | ecmd->supported |= (SUPPORTED_100baseT_Full | | |
801 | SUPPORTED_1000baseT_Full); | |
8b9dc8dd SH |
802 | |
803 | /* In loopback, the PHY automatically brings up the correct interface, | |
804 | * but doesn't advertise the correct speed. So override it */ | |
805 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
806 | ecmd->speed = SPEED_1000; | |
af4ad9bc | 807 | else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks) |
8b9dc8dd | 808 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
809 | } |
810 | ||
af4ad9bc | 811 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 812 | { |
af4ad9bc BH |
813 | if (!ecmd->autoneg) |
814 | return -EINVAL; | |
e6fa2eb7 | 815 | |
af4ad9bc | 816 | return mdio_clause45_set_settings(efx, ecmd); |
e6fa2eb7 BH |
817 | } |
818 | ||
af4ad9bc | 819 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 820 | { |
af4ad9bc BH |
821 | mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_AN, |
822 | MDIO_AN_10GBT_CTRL, | |
823 | MDIO_AN_10GBT_CTRL_ADV_10G_LBN, | |
824 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
825 | } |
826 | ||
af4ad9bc | 827 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 828 | { |
af4ad9bc BH |
829 | int phy_id = efx->mii.phy_id; |
830 | ||
831 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | |
832 | C22EXT_MSTSLV_CTRL, | |
833 | C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
834 | advertising & ADVERTISED_1000baseT_Full); | |
835 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN, | |
836 | MDIO_AN_10GBT_CTRL, | |
837 | MDIO_AN_10GBT_CTRL_ADV_10G_LBN, | |
838 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
839 | } |
840 | ||
841 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
177dfcd8 | 842 | .macs = EFX_XMAC, |
8ceee660 BH |
843 | .init = tenxpress_phy_init, |
844 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 845 | .poll = tenxpress_phy_poll, |
8ceee660 | 846 | .fini = tenxpress_phy_fini, |
766ca0fa | 847 | .clear_interrupt = efx_port_dummy_op_void, |
af4ad9bc BH |
848 | .get_settings = tenxpress_get_settings, |
849 | .set_settings = tenxpress_set_settings, | |
850 | .set_npage_adv = sfx7101_set_npage_adv, | |
307505e9 BH |
851 | .num_tests = ARRAY_SIZE(sfx7101_test_names), |
852 | .test_names = sfx7101_test_names, | |
853 | .run_tests = sfx7101_run_tests, | |
8ceee660 | 854 | .mmds = TENXPRESS_REQUIRED_DEVS, |
e6fa2eb7 BH |
855 | .loopbacks = SFX7101_LOOPBACKS, |
856 | }; | |
857 | ||
858 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
859 | .macs = EFX_GMAC | EFX_XMAC, | |
860 | .init = tenxpress_phy_init, | |
861 | .reconfigure = tenxpress_phy_reconfigure, | |
862 | .poll = tenxpress_phy_poll, | |
863 | .fini = tenxpress_phy_fini, | |
864 | .clear_interrupt = efx_port_dummy_op_void, | |
af4ad9bc BH |
865 | .get_settings = tenxpress_get_settings, |
866 | .set_settings = tenxpress_set_settings, | |
867 | .set_npage_adv = sft9001_set_npage_adv, | |
307505e9 BH |
868 | .num_tests = ARRAY_SIZE(sft9001_test_names), |
869 | .test_names = sft9001_test_names, | |
870 | .run_tests = sft9001_run_tests, | |
e6fa2eb7 BH |
871 | .mmds = TENXPRESS_REQUIRED_DEVS, |
872 | .loopbacks = SFT9001_LOOPBACKS, | |
8ceee660 | 873 | }; |