Commit | Line | Data |
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8ceee660 | 1 | /**************************************************************************** |
177dfcd8 BH |
2 | * Driver for Solarflare Solarstorm network controllers and boards |
3 | * Copyright 2007-2008 Solarflare Communications Inc. | |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 BH |
12 | #include <linux/seq_file.h> |
13 | #include "efx.h" | |
8ceee660 BH |
14 | #include "mdio_10g.h" |
15 | #include "falcon.h" | |
16 | #include "phy.h" | |
17 | #include "falcon_hwdefs.h" | |
18 | #include "boards.h" | |
e6fa2eb7 BH |
19 | #include "workarounds.h" |
20 | #include "selftest.h" | |
8ceee660 | 21 | |
e6fa2eb7 BH |
22 | /* We expect these MMDs to be in the package. SFT9001 also has a |
23 | * clause 22 extension MMD, but since it doesn't have all the generic | |
24 | * MMD registers it is pointless to include it here. | |
25 | */ | |
68e7f45e BH |
26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
27 | MDIO_DEVS_PCS | \ | |
28 | MDIO_DEVS_PHYXS | \ | |
29 | MDIO_DEVS_AN) | |
8ceee660 | 30 | |
e6fa2eb7 BH |
31 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
32 | (1 << LOOPBACK_PCS) | \ | |
33 | (1 << LOOPBACK_PMAPMD) | \ | |
34 | (1 << LOOPBACK_NETWORK)) | |
35 | ||
36 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
37 | (1 << LOOPBACK_PHYXS) | \ | |
38 | (1 << LOOPBACK_PCS) | \ | |
39 | (1 << LOOPBACK_PMAPMD) | \ | |
40 | (1 << LOOPBACK_NETWORK)) | |
3273c2e8 | 41 | |
8ceee660 BH |
42 | /* We complain if we fail to see the link partner as 10G capable this many |
43 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
44 | */ | |
45 | #define MAX_BAD_LP_TRIES (5) | |
46 | ||
e6fa2eb7 BH |
47 | /* LASI Control */ |
48 | #define PMA_PMD_LASI_CTRL 36866 | |
49 | #define PMA_PMD_LASI_STATUS 36869 | |
50 | #define PMA_PMD_LS_ALARM_LBN 0 | |
51 | #define PMA_PMD_LS_ALARM_WIDTH 1 | |
52 | #define PMA_PMD_TX_ALARM_LBN 1 | |
53 | #define PMA_PMD_TX_ALARM_WIDTH 1 | |
54 | #define PMA_PMD_RX_ALARM_LBN 2 | |
55 | #define PMA_PMD_RX_ALARM_WIDTH 1 | |
56 | #define PMA_PMD_AN_ALARM_LBN 3 | |
57 | #define PMA_PMD_AN_ALARM_WIDTH 1 | |
58 | ||
8ceee660 | 59 | /* Extended control register */ |
e6fa2eb7 BH |
60 | #define PMA_PMD_XCONTROL_REG 49152 |
61 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
62 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
63 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
64 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
65 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
66 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
67 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
68 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
69 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
70 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
71 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
72 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
73 | #define PMA_PMD_EXT_SSR_LBN 15 |
74 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
75 | |
76 | /* extended status register */ | |
e6fa2eb7 | 77 | #define PMA_PMD_XSTATUS_REG 49153 |
8ceee660 BH |
78 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
79 | ||
80 | /* LED control register */ | |
e6fa2eb7 | 81 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
82 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
83 | ||
84 | /* LED function override register */ | |
e6fa2eb7 | 85 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
86 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
87 | #define PMA_PMD_LED_LINK_LBN (0) | |
88 | #define PMA_PMD_LED_SPEED_LBN (2) | |
89 | #define PMA_PMD_LED_TX_LBN (4) | |
90 | #define PMA_PMD_LED_RX_LBN (6) | |
91 | /* Override settings */ | |
92 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
93 | #define PMA_PMD_LED_ON (1) | |
94 | #define PMA_PMD_LED_OFF (2) | |
95 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 96 | #define PMA_PMD_LED_MASK 3 |
8ceee660 BH |
97 | /* All LEDs under hardware control */ |
98 | #define PMA_PMD_LED_FULL_AUTO (0) | |
99 | /* Green and Amber under hardware control, Red off */ | |
100 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | |
101 | ||
e6fa2eb7 BH |
102 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
103 | #define PMA_PMD_100TX_ADV_LBN 1 | |
104 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
105 | #define PMA_PMD_1000T_ADV_LBN 2 | |
106 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
107 | #define PMA_PMD_10000T_ADV_LBN 3 | |
108 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
109 | #define PMA_PMD_SPEED_LBN 4 | |
110 | #define PMA_PMD_SPEED_WIDTH 4 | |
111 | ||
307505e9 BH |
112 | /* Cable diagnostics - SFT9001 only */ |
113 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
114 | #define CDIAG_CTRL_IMMED_LBN 15 | |
115 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
116 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
117 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
118 | #define CDIAG_CTRL_LEN_METRES 1 | |
119 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
120 | #define CDIAG_RES_A_LBN 12 | |
121 | #define CDIAG_RES_B_LBN 8 | |
122 | #define CDIAG_RES_C_LBN 4 | |
123 | #define CDIAG_RES_D_LBN 0 | |
124 | #define CDIAG_RES_WIDTH 4 | |
125 | #define CDIAG_RES_OPEN 2 | |
126 | #define CDIAG_RES_OK 1 | |
127 | #define CDIAG_RES_INVALID 0 | |
128 | /* Set of 4 registers for pairs A-D */ | |
129 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
130 | ||
e6fa2eb7 BH |
131 | /* Serdes control registers - SFT9001 only */ |
132 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
133 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
134 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
135 | ||
136 | /* Misc register defines - SFX7101 only */ | |
137 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
138 | #define PLL312_RST_N_LBN 2 |
139 | ||
e6fa2eb7 | 140 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
141 | #define SERDES_RST_N_LBN 13 |
142 | #define XGXS_RST_N_LBN 12 | |
143 | ||
e6fa2eb7 | 144 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
145 | #define CLK312_EN_LBN 3 |
146 | ||
3273c2e8 | 147 | /* PHYXS registers */ |
e6fa2eb7 BH |
148 | #define PHYXS_XCONTROL_REG 49152 |
149 | #define PHYXS_RESET_LBN 15 | |
150 | #define PHYXS_RESET_WIDTH 1 | |
151 | ||
3273c2e8 BH |
152 | #define PHYXS_TEST1 (49162) |
153 | #define LOOPBACK_NEAR_LBN (8) | |
154 | #define LOOPBACK_NEAR_WIDTH (1) | |
155 | ||
8ceee660 | 156 | /* Boot status register */ |
190dbcfd BH |
157 | #define PCS_BOOT_STATUS_REG 53248 |
158 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
159 | #define PCS_BOOT_PROGRESS_LBN 1 | |
160 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
161 | #define PCS_BOOT_PROGRESS_INIT 0 | |
162 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
163 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
164 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
165 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
166 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 167 | |
e6fa2eb7 BH |
168 | /* 100M/1G PHY registers */ |
169 | #define GPHY_XCONTROL_REG 49152 | |
170 | #define GPHY_ISOLATE_LBN 10 | |
171 | #define GPHY_ISOLATE_WIDTH 1 | |
172 | #define GPHY_DUPLEX_LBN 8 | |
173 | #define GPHY_DUPLEX_WIDTH 1 | |
174 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
175 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
176 | ||
177 | #define C22EXT_STATUS_REG 49153 | |
178 | #define C22EXT_STATUS_LINK_LBN 2 | |
179 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
180 | ||
af4ad9bc BH |
181 | #define C22EXT_MSTSLV_CTRL 49161 |
182 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
183 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
184 | ||
185 | #define C22EXT_MSTSLV_STATUS 49162 | |
186 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
187 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 188 | |
8ceee660 BH |
189 | /* Time to wait between powering down the LNPGA and turning off the power |
190 | * rails */ | |
191 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
192 | ||
8ceee660 | 193 | struct tenxpress_phy_data { |
3273c2e8 | 194 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 195 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
196 | int bad_lp_tries; |
197 | }; | |
198 | ||
e6fa2eb7 BH |
199 | static ssize_t show_phy_short_reach(struct device *dev, |
200 | struct device_attribute *attr, char *buf) | |
201 | { | |
202 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
203 | int reg; | |
204 | ||
68e7f45e BH |
205 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
206 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | |
e6fa2eb7 BH |
207 | } |
208 | ||
209 | static ssize_t set_phy_short_reach(struct device *dev, | |
210 | struct device_attribute *attr, | |
211 | const char *buf, size_t count) | |
212 | { | |
213 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
214 | ||
215 | rtnl_lock(); | |
68e7f45e BH |
216 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, |
217 | MDIO_PMA_10GBT_TXPWR_SHORT, | |
218 | count != 0 && *buf != '0'); | |
e6fa2eb7 BH |
219 | efx_reconfigure_port(efx); |
220 | rtnl_unlock(); | |
221 | ||
222 | return count; | |
223 | } | |
224 | ||
225 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
226 | set_phy_short_reach); | |
227 | ||
190dbcfd | 228 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 229 | { |
190dbcfd | 230 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
231 | int boot_stat; |
232 | ||
190dbcfd | 233 | for (;;) { |
68e7f45e BH |
234 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
235 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
236 | if (boot_stat >= 0) { |
237 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
238 | switch (boot_stat & | |
239 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
240 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
241 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
242 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
243 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
244 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
245 | PCS_BOOT_PROGRESS_LBN)): | |
246 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
247 | (PCS_BOOT_PROGRESS_INIT << | |
248 | PCS_BOOT_PROGRESS_LBN) | | |
249 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
250 | return -EINVAL; | |
251 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
252 | PCS_BOOT_PROGRESS_LBN) | | |
253 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
254 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
255 | 0 : -EIO; | |
256 | case ((PCS_BOOT_PROGRESS_JUMP << | |
257 | PCS_BOOT_PROGRESS_LBN) | | |
258 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
259 | case ((PCS_BOOT_PROGRESS_JUMP << | |
260 | PCS_BOOT_PROGRESS_LBN) | | |
261 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
262 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
263 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
264 | -EIO : 0; | |
265 | default: | |
266 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
267 | return -EIO; | |
268 | break; | |
269 | } | |
270 | } | |
271 | ||
272 | if (time_after_eq(jiffies, timeout)) | |
273 | return -ETIMEDOUT; | |
274 | ||
275 | msleep(50); | |
8ceee660 | 276 | } |
8ceee660 BH |
277 | } |
278 | ||
8ceee660 BH |
279 | static int tenxpress_init(struct efx_nic *efx) |
280 | { | |
e6fa2eb7 | 281 | int reg; |
8ceee660 | 282 | |
e6fa2eb7 BH |
283 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
284 | /* Enable 312.5 MHz clock */ | |
68e7f45e BH |
285 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
286 | 1 << CLK312_EN_LBN); | |
e6fa2eb7 BH |
287 | } else { |
288 | /* Enable 312.5 MHz clock and GMII */ | |
68e7f45e | 289 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
e6fa2eb7 BH |
290 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
291 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
292 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
293 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
294 | ||
68e7f45e BH |
295 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
296 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | |
297 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | |
298 | false); | |
e6fa2eb7 | 299 | } |
8ceee660 | 300 | |
8ceee660 | 301 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 | 302 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
68e7f45e BH |
303 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
304 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | |
305 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | |
306 | PMA_PMD_LED_DEFAULT); | |
e6fa2eb7 | 307 | } |
8ceee660 | 308 | |
190dbcfd | 309 | return 0; |
8ceee660 BH |
310 | } |
311 | ||
312 | static int tenxpress_phy_init(struct efx_nic *efx) | |
313 | { | |
314 | struct tenxpress_phy_data *phy_data; | |
315 | int rc = 0; | |
316 | ||
317 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
9b7bfc4c BH |
318 | if (!phy_data) |
319 | return -ENOMEM; | |
8ceee660 | 320 | efx->phy_data = phy_data; |
f8b87c17 | 321 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 322 | |
e6fa2eb7 BH |
323 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
324 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
325 | int reg; | |
68e7f45e BH |
326 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
327 | PMA_PMD_XCONTROL_REG); | |
e6fa2eb7 | 328 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e BH |
329 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
330 | PMA_PMD_XCONTROL_REG, reg); | |
e6fa2eb7 BH |
331 | mdelay(200); |
332 | } | |
8ceee660 | 333 | |
68e7f45e | 334 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
e6fa2eb7 BH |
335 | if (rc < 0) |
336 | goto fail; | |
337 | ||
68e7f45e | 338 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
e6fa2eb7 BH |
339 | if (rc < 0) |
340 | goto fail; | |
341 | } | |
8ceee660 BH |
342 | |
343 | rc = tenxpress_init(efx); | |
344 | if (rc < 0) | |
345 | goto fail; | |
68e7f45e | 346 | efx_mdio_set_pause(efx); |
8ceee660 | 347 | |
e6fa2eb7 BH |
348 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
349 | rc = device_create_file(&efx->pci_dev->dev, | |
350 | &dev_attr_phy_short_reach); | |
351 | if (rc) | |
352 | goto fail; | |
353 | } | |
354 | ||
8ceee660 BH |
355 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
356 | ||
e6fa2eb7 | 357 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
358 | falcon_reset_xaui(efx); |
359 | ||
360 | return 0; | |
361 | ||
362 | fail: | |
363 | kfree(efx->phy_data); | |
364 | efx->phy_data = NULL; | |
365 | return rc; | |
366 | } | |
367 | ||
e6fa2eb7 BH |
368 | /* Perform a "special software reset" on the PHY. The caller is |
369 | * responsible for saving and restoring the PHY hardware registers | |
370 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
371 | static int tenxpress_special_reset(struct efx_nic *efx) |
372 | { | |
373 | int rc, reg; | |
374 | ||
c8fcc49c BH |
375 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
376 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 BH |
377 | * requests to fail. */ |
378 | efx_stats_disable(efx); | |
3273c2e8 BH |
379 | |
380 | /* Initiate reset */ | |
68e7f45e | 381 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 | 382 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e | 383 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 384 | |
c8fcc49c | 385 | mdelay(200); |
3273c2e8 BH |
386 | |
387 | /* Wait for the blocks to come out of reset */ | |
68e7f45e | 388 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
3273c2e8 | 389 | if (rc < 0) |
1974cc20 | 390 | goto out; |
3273c2e8 BH |
391 | |
392 | /* Try and reconfigure the device */ | |
393 | rc = tenxpress_init(efx); | |
394 | if (rc < 0) | |
1974cc20 | 395 | goto out; |
3273c2e8 | 396 | |
e6fa2eb7 BH |
397 | /* Wait for the XGXS state machine to churn */ |
398 | mdelay(10); | |
1974cc20 BH |
399 | out: |
400 | efx_stats_enable(efx); | |
c8fcc49c | 401 | return rc; |
3273c2e8 BH |
402 | } |
403 | ||
e6fa2eb7 | 404 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
405 | { |
406 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac | 407 | bool bad_lp; |
8ceee660 BH |
408 | int reg; |
409 | ||
04cc8cac BH |
410 | if (link_ok) { |
411 | bad_lp = false; | |
412 | } else { | |
413 | /* Check that AN has started but not completed. */ | |
68e7f45e BH |
414 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
415 | if (!(reg & MDIO_AN_STAT1_LPABLE)) | |
04cc8cac | 416 | return; /* LP status is unknown */ |
68e7f45e | 417 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
04cc8cac BH |
418 | if (bad_lp) |
419 | pd->bad_lp_tries++; | |
420 | } | |
421 | ||
8ceee660 | 422 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 423 | if (!pd->bad_lp_tries) |
8ceee660 BH |
424 | return; |
425 | ||
04cc8cac BH |
426 | /* Use the RX (red) LED as an error indicator once we've seen AN |
427 | * failure several times in a row, and also log a message. */ | |
428 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
68e7f45e BH |
429 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
430 | PMA_PMD_LED_OVERR_REG); | |
04cc8cac BH |
431 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
432 | if (!bad_lp) { | |
433 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
434 | } else { | |
435 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
436 | EFX_ERR(efx, "appears to be plugged into a port" | |
437 | " that is not 10GBASE-T capable. The PHY" | |
438 | " supports 10GBASE-T ONLY, so no link can" | |
439 | " be established\n"); | |
440 | } | |
68e7f45e BH |
441 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
442 | PMA_PMD_LED_OVERR_REG, reg); | |
04cc8cac | 443 | pd->bad_lp_tries = bad_lp; |
8ceee660 | 444 | } |
8ceee660 BH |
445 | } |
446 | ||
e6fa2eb7 | 447 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 448 | { |
68e7f45e BH |
449 | return efx_mdio_links_ok(efx, |
450 | MDIO_DEVS_PMAPMD | | |
451 | MDIO_DEVS_PCS | | |
452 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
453 | } |
454 | ||
455 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
456 | { | |
e6fa2eb7 BH |
457 | u32 reg; |
458 | ||
caa8d8bb | 459 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 460 | return false; |
caa8d8bb BH |
461 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
462 | return true; | |
e6fa2eb7 | 463 | else if (efx->loopback_mode) |
68e7f45e BH |
464 | return efx_mdio_links_ok(efx, |
465 | MDIO_DEVS_PMAPMD | | |
466 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
467 | |
468 | /* We must use the same definition of link state as LASI, | |
469 | * otherwise we can miss a link state transition | |
470 | */ | |
471 | if (ecmd->speed == 10000) { | |
68e7f45e BH |
472 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
473 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | |
e6fa2eb7 | 474 | } else { |
68e7f45e | 475 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
e6fa2eb7 BH |
476 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
477 | } | |
8ceee660 BH |
478 | } |
479 | ||
e6fa2eb7 | 480 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 | 481 | { |
68e7f45e BH |
482 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
483 | 1 << LOOPBACK_NEAR_LBN, | |
484 | efx->loopback_mode == LOOPBACK_PHYXS); | |
e6fa2eb7 | 485 | if (efx->phy_type != PHY_TYPE_SFX7101) |
68e7f45e BH |
486 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
487 | 1 << GPHY_LOOPBACK_NEAR_LBN, | |
488 | efx->loopback_mode == LOOPBACK_GPHY); | |
e6fa2eb7 BH |
489 | } |
490 | ||
491 | static void tenxpress_low_power(struct efx_nic *efx) | |
492 | { | |
e6fa2eb7 | 493 | if (efx->phy_type == PHY_TYPE_SFX7101) |
68e7f45e | 494 | efx_mdio_set_mmds_lpower( |
e6fa2eb7 BH |
495 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
496 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 497 | else |
68e7f45e BH |
498 | efx_mdio_set_flag( |
499 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | |
500 | 1 << PMA_PMD_EXT_LPOWER_LBN, | |
e6fa2eb7 | 501 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
3273c2e8 BH |
502 | } |
503 | ||
8ceee660 BH |
504 | static void tenxpress_phy_reconfigure(struct efx_nic *efx) |
505 | { | |
3273c2e8 | 506 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
e6fa2eb7 | 507 | struct ethtool_cmd ecmd; |
8b9dc8dd | 508 | bool phy_mode_change, loop_reset; |
3273c2e8 | 509 | |
e6fa2eb7 | 510 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 511 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 512 | return; |
f8b87c17 | 513 | } |
8ceee660 | 514 | |
e6fa2eb7 BH |
515 | tenxpress_low_power(efx); |
516 | ||
517 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && | |
518 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
e6fa2eb7 BH |
519 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) || |
520 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); | |
521 | ||
8b9dc8dd | 522 | if (loop_reset || phy_mode_change) { |
e6fa2eb7 BH |
523 | int rc; |
524 | ||
525 | efx->phy_op->get_settings(efx, &ecmd); | |
526 | ||
527 | if (loop_reset || phy_mode_change) { | |
528 | tenxpress_special_reset(efx); | |
529 | ||
530 | /* Reset XAUI if we were in 10G, and are staying | |
531 | * in 10G. If we're moving into and out of 10G | |
532 | * then xaui will be reset anyway */ | |
533 | if (EFX_IS10G(efx)) | |
534 | falcon_reset_xaui(efx); | |
535 | } | |
536 | ||
e6fa2eb7 BH |
537 | rc = efx->phy_op->set_settings(efx, &ecmd); |
538 | WARN_ON(rc); | |
3273c2e8 BH |
539 | } |
540 | ||
68e7f45e BH |
541 | efx_mdio_transmit_disable(efx); |
542 | efx_mdio_phy_reconfigure(efx); | |
e6fa2eb7 | 543 | tenxpress_ext_loopback(efx); |
3273c2e8 | 544 | |
3273c2e8 | 545 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 546 | phy_data->phy_mode = efx->phy_mode; |
e6fa2eb7 BH |
547 | |
548 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
549 | efx->link_speed = 10000; | |
550 | efx->link_fd = true; | |
551 | efx->link_up = sfx7101_link_ok(efx); | |
552 | } else { | |
553 | efx->phy_op->get_settings(efx, &ecmd); | |
554 | efx->link_speed = ecmd.speed; | |
555 | efx->link_fd = ecmd.duplex == DUPLEX_FULL; | |
556 | efx->link_up = sft9001_link_ok(efx, &ecmd); | |
557 | } | |
68e7f45e | 558 | efx->link_fc = efx_mdio_get_pause(efx); |
8ceee660 BH |
559 | } |
560 | ||
8ceee660 | 561 | /* Poll PHY for interrupt */ |
766ca0fa | 562 | static void tenxpress_phy_poll(struct efx_nic *efx) |
8ceee660 BH |
563 | { |
564 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
37d37695 | 565 | bool change = false; |
8ceee660 | 566 | |
e6fa2eb7 | 567 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
37d37695 | 568 | bool link_ok = sfx7101_link_ok(efx); |
e6fa2eb7 BH |
569 | if (link_ok != efx->link_up) { |
570 | change = true; | |
571 | } else { | |
68e7f45e | 572 | unsigned int link_fc = efx_mdio_get_pause(efx); |
e6fa2eb7 BH |
573 | if (link_fc != efx->link_fc) |
574 | change = true; | |
575 | } | |
576 | sfx7101_check_bad_lp(efx, link_ok); | |
caa8d8bb BH |
577 | } else if (efx->loopback_mode) { |
578 | bool link_ok = sft9001_link_ok(efx, NULL); | |
579 | if (link_ok != efx->link_up) | |
580 | change = true; | |
766ca0fa | 581 | } else { |
68e7f45e BH |
582 | int status = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
583 | PMA_PMD_LASI_STATUS); | |
e6fa2eb7 | 584 | if (status & (1 << PMA_PMD_LS_ALARM_LBN)) |
766ca0fa BH |
585 | change = true; |
586 | } | |
8ceee660 | 587 | |
766ca0fa | 588 | if (change) |
177dfcd8 | 589 | falcon_sim_phy_event(efx); |
8ceee660 | 590 | |
f8b87c17 | 591 | if (phy_data->phy_mode != PHY_MODE_NORMAL) |
766ca0fa | 592 | return; |
8ceee660 BH |
593 | } |
594 | ||
595 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
596 | { | |
597 | int reg; | |
598 | ||
2a7e637d | 599 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
600 | device_remove_file(&efx->pci_dev->dev, |
601 | &dev_attr_phy_short_reach); | |
2a7e637d BH |
602 | |
603 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
e6fa2eb7 BH |
604 | /* Power down the LNPGA */ |
605 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
68e7f45e | 606 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
e6fa2eb7 BH |
607 | |
608 | /* Waiting here ensures that the board fini, which can turn | |
609 | * off the power to the PHY, won't get run until the LNPGA | |
610 | * powerdown has been given long enough to complete. */ | |
611 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
612 | } | |
8ceee660 BH |
613 | |
614 | kfree(efx->phy_data); | |
615 | efx->phy_data = NULL; | |
616 | } | |
617 | ||
618 | ||
619 | /* Set the RX and TX LEDs and Link LED flashing. The other LEDs | |
620 | * (which probably aren't wired anyway) are left in AUTO mode */ | |
dc8cfa55 | 621 | void tenxpress_phy_blink(struct efx_nic *efx, bool blink) |
8ceee660 BH |
622 | { |
623 | int reg; | |
624 | ||
625 | if (blink) | |
626 | reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) | | |
627 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) | | |
628 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN); | |
629 | else | |
630 | reg = PMA_PMD_LED_DEFAULT; | |
631 | ||
68e7f45e | 632 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
8ceee660 BH |
633 | } |
634 | ||
307505e9 | 635 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
636 | "bist" |
637 | }; | |
638 | ||
639 | static int | |
307505e9 | 640 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 641 | { |
1796721a BH |
642 | int rc; |
643 | ||
644 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
645 | return 0; | |
646 | ||
8c8661e4 | 647 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
648 | rc = tenxpress_special_reset(efx); |
649 | results[0] = rc ? -1 : 1; | |
650 | return rc; | |
8c8661e4 BH |
651 | } |
652 | ||
307505e9 BH |
653 | static const char *const sft9001_test_names[] = { |
654 | "bist", | |
655 | "cable.pairA.status", | |
656 | "cable.pairB.status", | |
657 | "cable.pairC.status", | |
658 | "cable.pairD.status", | |
659 | "cable.pairA.length", | |
660 | "cable.pairB.length", | |
661 | "cable.pairC.length", | |
662 | "cable.pairD.length", | |
663 | }; | |
664 | ||
665 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |
666 | { | |
667 | struct ethtool_cmd ecmd; | |
22ef02c2 | 668 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 669 | |
22ef02c2 BH |
670 | if (flags & ETH_TEST_FL_OFFLINE) |
671 | efx->phy_op->get_settings(efx, &ecmd); | |
307505e9 BH |
672 | |
673 | /* Initialise cable diagnostic results to unknown failure */ | |
674 | for (i = 1; i < 9; ++i) | |
675 | results[i] = -1; | |
676 | ||
677 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
678 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
679 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
680 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
681 | if (flags & ETH_TEST_FL_OFFLINE) { | |
682 | /* Break the link in order to run full diagnostics. We | |
683 | * must reset the PHY to resume normal service. */ | |
684 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
685 | } | |
68e7f45e BH |
686 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
687 | ctrl_reg); | |
307505e9 | 688 | i = 0; |
68e7f45e | 689 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
307505e9 BH |
690 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
691 | if (++i == 50) { | |
692 | rc = -ETIMEDOUT; | |
22ef02c2 | 693 | goto out; |
307505e9 BH |
694 | } |
695 | msleep(100); | |
696 | } | |
68e7f45e | 697 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
307505e9 BH |
698 | for (i = 0; i < 4; i++) { |
699 | int pair_res = | |
700 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
701 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
68e7f45e BH |
702 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
703 | PMA_PMD_CDIAG_LEN_REG + i); | |
307505e9 BH |
704 | if (pair_res == CDIAG_RES_OK) |
705 | results[1 + i] = 1; | |
706 | else if (pair_res == CDIAG_RES_INVALID) | |
707 | results[1 + i] = -1; | |
708 | else | |
709 | results[1 + i] = -pair_res; | |
710 | if (pair_res != CDIAG_RES_INVALID && | |
711 | pair_res != CDIAG_RES_OPEN && | |
712 | len_reg != 0xffff) | |
713 | results[5 + i] = len_reg; | |
714 | } | |
715 | ||
22ef02c2 BH |
716 | out: |
717 | if (flags & ETH_TEST_FL_OFFLINE) { | |
718 | /* Reset, running the BIST and then resuming normal service. */ | |
719 | rc2 = tenxpress_special_reset(efx); | |
720 | results[0] = rc2 ? -1 : 1; | |
721 | if (!rc) | |
722 | rc = rc2; | |
723 | ||
724 | rc2 = efx->phy_op->set_settings(efx, &ecmd); | |
725 | if (!rc) | |
726 | rc = rc2; | |
727 | } | |
307505e9 BH |
728 | |
729 | return rc; | |
730 | } | |
731 | ||
af4ad9bc BH |
732 | static void |
733 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 734 | { |
af4ad9bc | 735 | u32 adv = 0, lpa = 0; |
04cc8cac BH |
736 | int reg; |
737 | ||
e6fa2eb7 | 738 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
68e7f45e | 739 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
af4ad9bc BH |
740 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
741 | adv |= ADVERTISED_1000baseT_Full; | |
68e7f45e | 742 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
af4ad9bc | 743 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
e6fa2eb7 | 744 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 745 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
746 | lpa |= ADVERTISED_1000baseT_Full; |
747 | } | |
68e7f45e BH |
748 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
749 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | |
af4ad9bc | 750 | adv |= ADVERTISED_10000baseT_Full; |
68e7f45e BH |
751 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
752 | if (reg & MDIO_AN_10GBT_STAT_LP10G) | |
04cc8cac | 753 | lpa |= ADVERTISED_10000baseT_Full; |
04cc8cac | 754 | |
68e7f45e | 755 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
e6fa2eb7 | 756 | |
af4ad9bc BH |
757 | if (efx->phy_type != PHY_TYPE_SFX7101) |
758 | ecmd->supported |= (SUPPORTED_100baseT_Full | | |
759 | SUPPORTED_1000baseT_Full); | |
8b9dc8dd SH |
760 | |
761 | /* In loopback, the PHY automatically brings up the correct interface, | |
762 | * but doesn't advertise the correct speed. So override it */ | |
763 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
764 | ecmd->speed = SPEED_1000; | |
af4ad9bc | 765 | else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks) |
8b9dc8dd | 766 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
767 | } |
768 | ||
af4ad9bc | 769 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 770 | { |
af4ad9bc BH |
771 | if (!ecmd->autoneg) |
772 | return -EINVAL; | |
e6fa2eb7 | 773 | |
68e7f45e | 774 | return efx_mdio_set_settings(efx, ecmd); |
e6fa2eb7 BH |
775 | } |
776 | ||
af4ad9bc | 777 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 778 | { |
68e7f45e BH |
779 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
780 | MDIO_AN_10GBT_CTRL_ADV10G, | |
781 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
782 | } |
783 | ||
af4ad9bc | 784 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 785 | { |
68e7f45e BH |
786 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
787 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
788 | advertising & ADVERTISED_1000baseT_Full); | |
789 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | |
790 | MDIO_AN_10GBT_CTRL_ADV10G, | |
791 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
792 | } |
793 | ||
794 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
177dfcd8 | 795 | .macs = EFX_XMAC, |
8ceee660 BH |
796 | .init = tenxpress_phy_init, |
797 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 798 | .poll = tenxpress_phy_poll, |
8ceee660 | 799 | .fini = tenxpress_phy_fini, |
766ca0fa | 800 | .clear_interrupt = efx_port_dummy_op_void, |
af4ad9bc BH |
801 | .get_settings = tenxpress_get_settings, |
802 | .set_settings = tenxpress_set_settings, | |
803 | .set_npage_adv = sfx7101_set_npage_adv, | |
307505e9 BH |
804 | .num_tests = ARRAY_SIZE(sfx7101_test_names), |
805 | .test_names = sfx7101_test_names, | |
806 | .run_tests = sfx7101_run_tests, | |
8ceee660 | 807 | .mmds = TENXPRESS_REQUIRED_DEVS, |
e6fa2eb7 BH |
808 | .loopbacks = SFX7101_LOOPBACKS, |
809 | }; | |
810 | ||
811 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
812 | .macs = EFX_GMAC | EFX_XMAC, | |
813 | .init = tenxpress_phy_init, | |
814 | .reconfigure = tenxpress_phy_reconfigure, | |
815 | .poll = tenxpress_phy_poll, | |
816 | .fini = tenxpress_phy_fini, | |
817 | .clear_interrupt = efx_port_dummy_op_void, | |
af4ad9bc BH |
818 | .get_settings = tenxpress_get_settings, |
819 | .set_settings = tenxpress_set_settings, | |
820 | .set_npage_adv = sft9001_set_npage_adv, | |
307505e9 BH |
821 | .num_tests = ARRAY_SIZE(sft9001_test_names), |
822 | .test_names = sft9001_test_names, | |
823 | .run_tests = sft9001_run_tests, | |
e6fa2eb7 BH |
824 | .mmds = TENXPRESS_REQUIRED_DEVS, |
825 | .loopbacks = SFT9001_LOOPBACKS, | |
8ceee660 | 826 | }; |