Commit | Line | Data |
---|---|---|
8ceee660 | 1 | /**************************************************************************** |
177dfcd8 | 2 | * Driver for Solarflare Solarstorm network controllers and boards |
906bb26c | 3 | * Copyright 2007-2009 Solarflare Communications Inc. |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 BH |
12 | #include <linux/seq_file.h> |
13 | #include "efx.h" | |
8ceee660 | 14 | #include "mdio_10g.h" |
744093c9 | 15 | #include "nic.h" |
8ceee660 | 16 | #include "phy.h" |
3e6c4538 | 17 | #include "regs.h" |
e6fa2eb7 BH |
18 | #include "workarounds.h" |
19 | #include "selftest.h" | |
8ceee660 | 20 | |
e6fa2eb7 BH |
21 | /* We expect these MMDs to be in the package. SFT9001 also has a |
22 | * clause 22 extension MMD, but since it doesn't have all the generic | |
23 | * MMD registers it is pointless to include it here. | |
24 | */ | |
68e7f45e BH |
25 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
26 | MDIO_DEVS_PCS | \ | |
27 | MDIO_DEVS_PHYXS | \ | |
28 | MDIO_DEVS_AN) | |
8ceee660 | 29 | |
e6fa2eb7 BH |
30 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
31 | (1 << LOOPBACK_PCS) | \ | |
32 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 33 | (1 << LOOPBACK_PHYXS_WS)) |
e6fa2eb7 BH |
34 | |
35 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
36 | (1 << LOOPBACK_PHYXS) | \ | |
37 | (1 << LOOPBACK_PCS) | \ | |
38 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 39 | (1 << LOOPBACK_PHYXS_WS)) |
3273c2e8 | 40 | |
8ceee660 BH |
41 | /* We complain if we fail to see the link partner as 10G capable this many |
42 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
43 | */ | |
44 | #define MAX_BAD_LP_TRIES (5) | |
45 | ||
46 | /* Extended control register */ | |
e6fa2eb7 BH |
47 | #define PMA_PMD_XCONTROL_REG 49152 |
48 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
49 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
50 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
51 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
52 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
53 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
54 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
55 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
56 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
57 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
58 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
59 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
60 | #define PMA_PMD_EXT_SSR_LBN 15 |
61 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
62 | |
63 | /* extended status register */ | |
e6fa2eb7 | 64 | #define PMA_PMD_XSTATUS_REG 49153 |
e762cd70 | 65 | #define PMA_PMD_XSTAT_MDIX_LBN 14 |
8ceee660 BH |
66 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
67 | ||
68 | /* LED control register */ | |
e6fa2eb7 | 69 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
70 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
71 | ||
72 | /* LED function override register */ | |
e6fa2eb7 | 73 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
74 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
75 | #define PMA_PMD_LED_LINK_LBN (0) | |
76 | #define PMA_PMD_LED_SPEED_LBN (2) | |
77 | #define PMA_PMD_LED_TX_LBN (4) | |
78 | #define PMA_PMD_LED_RX_LBN (6) | |
79 | /* Override settings */ | |
80 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
81 | #define PMA_PMD_LED_ON (1) | |
82 | #define PMA_PMD_LED_OFF (2) | |
83 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 84 | #define PMA_PMD_LED_MASK 3 |
8ceee660 | 85 | /* All LEDs under hardware control */ |
dcf477b2 | 86 | #define SFT9001_PMA_PMD_LED_DEFAULT 0 |
8ceee660 | 87 | /* Green and Amber under hardware control, Red off */ |
dcf477b2 | 88 | #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
8ceee660 | 89 | |
e6fa2eb7 BH |
90 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
91 | #define PMA_PMD_100TX_ADV_LBN 1 | |
92 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
93 | #define PMA_PMD_1000T_ADV_LBN 2 | |
94 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
95 | #define PMA_PMD_10000T_ADV_LBN 3 | |
96 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
97 | #define PMA_PMD_SPEED_LBN 4 | |
98 | #define PMA_PMD_SPEED_WIDTH 4 | |
99 | ||
307505e9 BH |
100 | /* Cable diagnostics - SFT9001 only */ |
101 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
102 | #define CDIAG_CTRL_IMMED_LBN 15 | |
103 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
104 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
105 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
106 | #define CDIAG_CTRL_LEN_METRES 1 | |
107 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
108 | #define CDIAG_RES_A_LBN 12 | |
109 | #define CDIAG_RES_B_LBN 8 | |
110 | #define CDIAG_RES_C_LBN 4 | |
111 | #define CDIAG_RES_D_LBN 0 | |
112 | #define CDIAG_RES_WIDTH 4 | |
113 | #define CDIAG_RES_OPEN 2 | |
114 | #define CDIAG_RES_OK 1 | |
115 | #define CDIAG_RES_INVALID 0 | |
116 | /* Set of 4 registers for pairs A-D */ | |
117 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
118 | ||
e6fa2eb7 BH |
119 | /* Serdes control registers - SFT9001 only */ |
120 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
121 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
122 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
123 | ||
124 | /* Misc register defines - SFX7101 only */ | |
125 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
126 | #define PLL312_RST_N_LBN 2 |
127 | ||
e6fa2eb7 | 128 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
129 | #define SERDES_RST_N_LBN 13 |
130 | #define XGXS_RST_N_LBN 12 | |
131 | ||
e6fa2eb7 | 132 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
133 | #define CLK312_EN_LBN 3 |
134 | ||
3273c2e8 | 135 | /* PHYXS registers */ |
e6fa2eb7 BH |
136 | #define PHYXS_XCONTROL_REG 49152 |
137 | #define PHYXS_RESET_LBN 15 | |
138 | #define PHYXS_RESET_WIDTH 1 | |
139 | ||
3273c2e8 BH |
140 | #define PHYXS_TEST1 (49162) |
141 | #define LOOPBACK_NEAR_LBN (8) | |
142 | #define LOOPBACK_NEAR_WIDTH (1) | |
143 | ||
8ceee660 | 144 | /* Boot status register */ |
190dbcfd BH |
145 | #define PCS_BOOT_STATUS_REG 53248 |
146 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
147 | #define PCS_BOOT_PROGRESS_LBN 1 | |
148 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
149 | #define PCS_BOOT_PROGRESS_INIT 0 | |
150 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
151 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
152 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
153 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
154 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 155 | |
e6fa2eb7 BH |
156 | /* 100M/1G PHY registers */ |
157 | #define GPHY_XCONTROL_REG 49152 | |
158 | #define GPHY_ISOLATE_LBN 10 | |
159 | #define GPHY_ISOLATE_WIDTH 1 | |
160 | #define GPHY_DUPLEX_LBN 8 | |
161 | #define GPHY_DUPLEX_WIDTH 1 | |
162 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
163 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
164 | ||
165 | #define C22EXT_STATUS_REG 49153 | |
166 | #define C22EXT_STATUS_LINK_LBN 2 | |
167 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
168 | ||
af4ad9bc BH |
169 | #define C22EXT_MSTSLV_CTRL 49161 |
170 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
171 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
172 | ||
173 | #define C22EXT_MSTSLV_STATUS 49162 | |
174 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
175 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 176 | |
8ceee660 BH |
177 | /* Time to wait between powering down the LNPGA and turning off the power |
178 | * rails */ | |
179 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
180 | ||
8ceee660 | 181 | struct tenxpress_phy_data { |
3273c2e8 | 182 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 183 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
184 | int bad_lp_tries; |
185 | }; | |
186 | ||
e6fa2eb7 BH |
187 | static ssize_t show_phy_short_reach(struct device *dev, |
188 | struct device_attribute *attr, char *buf) | |
189 | { | |
190 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
191 | int reg; | |
192 | ||
68e7f45e BH |
193 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
194 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | |
e6fa2eb7 BH |
195 | } |
196 | ||
197 | static ssize_t set_phy_short_reach(struct device *dev, | |
198 | struct device_attribute *attr, | |
199 | const char *buf, size_t count) | |
200 | { | |
201 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
d3245b28 | 202 | int rc; |
e6fa2eb7 BH |
203 | |
204 | rtnl_lock(); | |
ff3b00a0 SH |
205 | if (efx->state != STATE_RUNNING) { |
206 | rc = -EBUSY; | |
207 | } else { | |
208 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, | |
209 | MDIO_PMA_10GBT_TXPWR_SHORT, | |
210 | count != 0 && *buf != '0'); | |
211 | rc = efx_reconfigure_port(efx); | |
212 | } | |
e6fa2eb7 BH |
213 | rtnl_unlock(); |
214 | ||
d3245b28 | 215 | return rc < 0 ? rc : (ssize_t)count; |
e6fa2eb7 BH |
216 | } |
217 | ||
218 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
219 | set_phy_short_reach); | |
220 | ||
190dbcfd | 221 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 222 | { |
190dbcfd | 223 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
224 | int boot_stat; |
225 | ||
190dbcfd | 226 | for (;;) { |
68e7f45e BH |
227 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
228 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
229 | if (boot_stat >= 0) { |
230 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
231 | switch (boot_stat & | |
232 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
233 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
234 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
235 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
236 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
237 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
238 | PCS_BOOT_PROGRESS_LBN)): | |
239 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
240 | (PCS_BOOT_PROGRESS_INIT << | |
241 | PCS_BOOT_PROGRESS_LBN) | | |
242 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
243 | return -EINVAL; | |
244 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
245 | PCS_BOOT_PROGRESS_LBN) | | |
246 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
247 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
248 | 0 : -EIO; | |
249 | case ((PCS_BOOT_PROGRESS_JUMP << | |
250 | PCS_BOOT_PROGRESS_LBN) | | |
251 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
252 | case ((PCS_BOOT_PROGRESS_JUMP << | |
253 | PCS_BOOT_PROGRESS_LBN) | | |
254 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
255 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
256 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
257 | -EIO : 0; | |
258 | default: | |
259 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
260 | return -EIO; | |
261 | break; | |
262 | } | |
263 | } | |
264 | ||
265 | if (time_after_eq(jiffies, timeout)) | |
266 | return -ETIMEDOUT; | |
267 | ||
268 | msleep(50); | |
8ceee660 | 269 | } |
8ceee660 BH |
270 | } |
271 | ||
8ceee660 BH |
272 | static int tenxpress_init(struct efx_nic *efx) |
273 | { | |
e6fa2eb7 | 274 | int reg; |
8ceee660 | 275 | |
e6fa2eb7 BH |
276 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
277 | /* Enable 312.5 MHz clock */ | |
68e7f45e BH |
278 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
279 | 1 << CLK312_EN_LBN); | |
e6fa2eb7 BH |
280 | } else { |
281 | /* Enable 312.5 MHz clock and GMII */ | |
68e7f45e | 282 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
e6fa2eb7 BH |
283 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
284 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
285 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
286 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
287 | ||
68e7f45e BH |
288 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
289 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | |
290 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | |
291 | false); | |
e6fa2eb7 | 292 | } |
8ceee660 | 293 | |
8ceee660 | 294 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 | 295 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
68e7f45e BH |
296 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
297 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | |
298 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | |
dcf477b2 | 299 | SFX7101_PMA_PMD_LED_DEFAULT); |
e6fa2eb7 | 300 | } |
8ceee660 | 301 | |
190dbcfd | 302 | return 0; |
8ceee660 BH |
303 | } |
304 | ||
ff3b00a0 | 305 | static int tenxpress_phy_probe(struct efx_nic *efx) |
c1c4f453 | 306 | { |
ff3b00a0 SH |
307 | struct tenxpress_phy_data *phy_data; |
308 | int rc; | |
309 | ||
310 | /* Allocate phy private storage */ | |
311 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
312 | if (!phy_data) | |
313 | return -ENOMEM; | |
314 | efx->phy_data = phy_data; | |
315 | phy_data->phy_mode = efx->phy_mode; | |
316 | ||
317 | /* Create any special files */ | |
318 | if (efx->phy_type == PHY_TYPE_SFT9001B) { | |
319 | rc = device_create_file(&efx->pci_dev->dev, | |
320 | &dev_attr_phy_short_reach); | |
321 | if (rc) | |
322 | goto fail; | |
323 | } | |
324 | ||
325 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
326 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | |
327 | efx->mdio.mode_support = MDIO_SUPPORTS_C45; | |
328 | ||
329 | efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS; | |
330 | ||
331 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | |
332 | ADVERTISED_10000baseT_Full); | |
333 | } else { | |
334 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | |
335 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
336 | ||
337 | efx->loopback_modes = (SFT9001_LOOPBACKS | | |
338 | FALCON_XMAC_LOOPBACKS | | |
339 | FALCON_GMAC_LOOPBACKS); | |
340 | ||
341 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | |
342 | ADVERTISED_10000baseT_Full | | |
343 | ADVERTISED_1000baseT_Full | | |
344 | ADVERTISED_100baseT_Full); | |
345 | } | |
c1c4f453 | 346 | |
c1c4f453 | 347 | return 0; |
ff3b00a0 SH |
348 | |
349 | fail: | |
350 | kfree(efx->phy_data); | |
351 | efx->phy_data = NULL; | |
352 | return rc; | |
c1c4f453 BH |
353 | } |
354 | ||
8ceee660 BH |
355 | static int tenxpress_phy_init(struct efx_nic *efx) |
356 | { | |
ff3b00a0 | 357 | int rc; |
8ceee660 | 358 | |
44838a44 | 359 | falcon_board(efx)->type->init_phy(efx); |
981fc1b4 | 360 | |
e6fa2eb7 BH |
361 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
362 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
363 | int reg; | |
68e7f45e BH |
364 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
365 | PMA_PMD_XCONTROL_REG); | |
e6fa2eb7 | 366 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e BH |
367 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
368 | PMA_PMD_XCONTROL_REG, reg); | |
e6fa2eb7 BH |
369 | mdelay(200); |
370 | } | |
8ceee660 | 371 | |
68e7f45e | 372 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
e6fa2eb7 | 373 | if (rc < 0) |
ff3b00a0 | 374 | return rc; |
e6fa2eb7 | 375 | |
68e7f45e | 376 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
e6fa2eb7 | 377 | if (rc < 0) |
ff3b00a0 | 378 | return rc; |
e6fa2eb7 | 379 | } |
8ceee660 BH |
380 | |
381 | rc = tenxpress_init(efx); | |
382 | if (rc < 0) | |
ff3b00a0 | 383 | return rc; |
8ceee660 | 384 | |
ff3b00a0 | 385 | /* Reinitialise flow control settings */ |
d3245b28 BH |
386 | efx_link_set_wanted_fc(efx, efx->wanted_fc); |
387 | efx_mdio_an_reconfigure(efx); | |
c634263d | 388 | |
8ceee660 BH |
389 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
390 | ||
e6fa2eb7 | 391 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
392 | falcon_reset_xaui(efx); |
393 | ||
394 | return 0; | |
8ceee660 BH |
395 | } |
396 | ||
e6fa2eb7 BH |
397 | /* Perform a "special software reset" on the PHY. The caller is |
398 | * responsible for saving and restoring the PHY hardware registers | |
399 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
400 | static int tenxpress_special_reset(struct efx_nic *efx) |
401 | { | |
402 | int rc, reg; | |
403 | ||
c8fcc49c BH |
404 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
405 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 | 406 | * requests to fail. */ |
55edc6e6 | 407 | falcon_stop_nic_stats(efx); |
3273c2e8 BH |
408 | |
409 | /* Initiate reset */ | |
68e7f45e | 410 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 | 411 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e | 412 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 413 | |
c8fcc49c | 414 | mdelay(200); |
3273c2e8 BH |
415 | |
416 | /* Wait for the blocks to come out of reset */ | |
68e7f45e | 417 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
3273c2e8 | 418 | if (rc < 0) |
1974cc20 | 419 | goto out; |
3273c2e8 BH |
420 | |
421 | /* Try and reconfigure the device */ | |
422 | rc = tenxpress_init(efx); | |
423 | if (rc < 0) | |
1974cc20 | 424 | goto out; |
3273c2e8 | 425 | |
e6fa2eb7 BH |
426 | /* Wait for the XGXS state machine to churn */ |
427 | mdelay(10); | |
1974cc20 | 428 | out: |
55edc6e6 | 429 | falcon_start_nic_stats(efx); |
c8fcc49c | 430 | return rc; |
3273c2e8 BH |
431 | } |
432 | ||
e6fa2eb7 | 433 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
434 | { |
435 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac | 436 | bool bad_lp; |
8ceee660 BH |
437 | int reg; |
438 | ||
04cc8cac BH |
439 | if (link_ok) { |
440 | bad_lp = false; | |
441 | } else { | |
442 | /* Check that AN has started but not completed. */ | |
68e7f45e BH |
443 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
444 | if (!(reg & MDIO_AN_STAT1_LPABLE)) | |
04cc8cac | 445 | return; /* LP status is unknown */ |
68e7f45e | 446 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
04cc8cac BH |
447 | if (bad_lp) |
448 | pd->bad_lp_tries++; | |
449 | } | |
450 | ||
8ceee660 | 451 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 452 | if (!pd->bad_lp_tries) |
8ceee660 BH |
453 | return; |
454 | ||
04cc8cac BH |
455 | /* Use the RX (red) LED as an error indicator once we've seen AN |
456 | * failure several times in a row, and also log a message. */ | |
457 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
68e7f45e BH |
458 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
459 | PMA_PMD_LED_OVERR_REG); | |
04cc8cac BH |
460 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
461 | if (!bad_lp) { | |
462 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
463 | } else { | |
464 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
465 | EFX_ERR(efx, "appears to be plugged into a port" | |
466 | " that is not 10GBASE-T capable. The PHY" | |
467 | " supports 10GBASE-T ONLY, so no link can" | |
468 | " be established\n"); | |
469 | } | |
68e7f45e BH |
470 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
471 | PMA_PMD_LED_OVERR_REG, reg); | |
04cc8cac | 472 | pd->bad_lp_tries = bad_lp; |
8ceee660 | 473 | } |
8ceee660 BH |
474 | } |
475 | ||
e6fa2eb7 | 476 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 477 | { |
68e7f45e BH |
478 | return efx_mdio_links_ok(efx, |
479 | MDIO_DEVS_PMAPMD | | |
480 | MDIO_DEVS_PCS | | |
481 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
482 | } |
483 | ||
484 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
485 | { | |
e6fa2eb7 BH |
486 | u32 reg; |
487 | ||
caa8d8bb | 488 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 489 | return false; |
caa8d8bb BH |
490 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
491 | return true; | |
e6fa2eb7 | 492 | else if (efx->loopback_mode) |
68e7f45e BH |
493 | return efx_mdio_links_ok(efx, |
494 | MDIO_DEVS_PMAPMD | | |
495 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
496 | |
497 | /* We must use the same definition of link state as LASI, | |
498 | * otherwise we can miss a link state transition | |
499 | */ | |
500 | if (ecmd->speed == 10000) { | |
68e7f45e BH |
501 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
502 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | |
e6fa2eb7 | 503 | } else { |
68e7f45e | 504 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
e6fa2eb7 BH |
505 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
506 | } | |
8ceee660 BH |
507 | } |
508 | ||
e6fa2eb7 | 509 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 | 510 | { |
68e7f45e BH |
511 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
512 | 1 << LOOPBACK_NEAR_LBN, | |
513 | efx->loopback_mode == LOOPBACK_PHYXS); | |
e6fa2eb7 | 514 | if (efx->phy_type != PHY_TYPE_SFX7101) |
68e7f45e BH |
515 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
516 | 1 << GPHY_LOOPBACK_NEAR_LBN, | |
517 | efx->loopback_mode == LOOPBACK_GPHY); | |
e6fa2eb7 BH |
518 | } |
519 | ||
520 | static void tenxpress_low_power(struct efx_nic *efx) | |
521 | { | |
e6fa2eb7 | 522 | if (efx->phy_type == PHY_TYPE_SFX7101) |
68e7f45e | 523 | efx_mdio_set_mmds_lpower( |
e6fa2eb7 BH |
524 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
525 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 526 | else |
68e7f45e BH |
527 | efx_mdio_set_flag( |
528 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | |
529 | 1 << PMA_PMD_EXT_LPOWER_LBN, | |
e6fa2eb7 | 530 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
3273c2e8 BH |
531 | } |
532 | ||
d3245b28 | 533 | static int tenxpress_phy_reconfigure(struct efx_nic *efx) |
8ceee660 | 534 | { |
3273c2e8 | 535 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
8b9dc8dd | 536 | bool phy_mode_change, loop_reset; |
3273c2e8 | 537 | |
e6fa2eb7 | 538 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 539 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 | 540 | return 0; |
f8b87c17 | 541 | } |
8ceee660 | 542 | |
e6fa2eb7 BH |
543 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && |
544 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
c1c4f453 | 545 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) || |
e6fa2eb7 BH |
546 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); |
547 | ||
8b9dc8dd | 548 | if (loop_reset || phy_mode_change) { |
d3245b28 | 549 | tenxpress_special_reset(efx); |
e6fa2eb7 | 550 | |
d3245b28 BH |
551 | /* Reset XAUI if we were in 10G, and are staying |
552 | * in 10G. If we're moving into and out of 10G | |
553 | * then xaui will be reset anyway */ | |
554 | if (EFX_IS10G(efx)) | |
555 | falcon_reset_xaui(efx); | |
3273c2e8 BH |
556 | } |
557 | ||
d3245b28 | 558 | tenxpress_low_power(efx); |
68e7f45e BH |
559 | efx_mdio_transmit_disable(efx); |
560 | efx_mdio_phy_reconfigure(efx); | |
e6fa2eb7 | 561 | tenxpress_ext_loopback(efx); |
d3245b28 | 562 | efx_mdio_an_reconfigure(efx); |
3273c2e8 | 563 | |
3273c2e8 | 564 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 565 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 BH |
566 | |
567 | return 0; | |
8ceee660 BH |
568 | } |
569 | ||
fdaa9aed SH |
570 | static void |
571 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd); | |
572 | ||
573 | /* Poll for link state changes */ | |
574 | static bool tenxpress_phy_poll(struct efx_nic *efx) | |
8ceee660 | 575 | { |
fdaa9aed | 576 | struct efx_link_state old_state = efx->link_state; |
8ceee660 | 577 | |
e6fa2eb7 | 578 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
fdaa9aed SH |
579 | efx->link_state.up = sfx7101_link_ok(efx); |
580 | efx->link_state.speed = 10000; | |
581 | efx->link_state.fd = true; | |
582 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
583 | ||
584 | sfx7101_check_bad_lp(efx, efx->link_state.up); | |
766ca0fa | 585 | } else { |
fdaa9aed | 586 | struct ethtool_cmd ecmd; |
8ceee660 | 587 | |
fdaa9aed SH |
588 | /* Check the LASI alarm first */ |
589 | if (efx->loopback_mode == LOOPBACK_NONE && | |
590 | !(efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT) & | |
591 | MDIO_PMA_LASI_LSALARM)) | |
592 | return false; | |
8ceee660 | 593 | |
fdaa9aed SH |
594 | tenxpress_get_settings(efx, &ecmd); |
595 | ||
596 | efx->link_state.up = sft9001_link_ok(efx, &ecmd); | |
597 | efx->link_state.speed = ecmd.speed; | |
598 | efx->link_state.fd = (ecmd.duplex == DUPLEX_FULL); | |
599 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
600 | } | |
601 | ||
602 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
8ceee660 BH |
603 | } |
604 | ||
ff3b00a0 | 605 | static void sfx7101_phy_fini(struct efx_nic *efx) |
8ceee660 BH |
606 | { |
607 | int reg; | |
608 | ||
ff3b00a0 SH |
609 | /* Power down the LNPGA */ |
610 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
611 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); | |
612 | ||
613 | /* Waiting here ensures that the board fini, which can turn | |
614 | * off the power to the PHY, won't get run until the LNPGA | |
615 | * powerdown has been given long enough to complete. */ | |
616 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
617 | } | |
618 | ||
619 | static void tenxpress_phy_remove(struct efx_nic *efx) | |
620 | { | |
2a7e637d | 621 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
622 | device_remove_file(&efx->pci_dev->dev, |
623 | &dev_attr_phy_short_reach); | |
2a7e637d | 624 | |
8ceee660 BH |
625 | kfree(efx->phy_data); |
626 | efx->phy_data = NULL; | |
627 | } | |
628 | ||
629 | ||
398468ed BH |
630 | /* Override the RX, TX and link LEDs */ |
631 | void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) | |
8ceee660 BH |
632 | { |
633 | int reg; | |
634 | ||
398468ed BH |
635 | switch (mode) { |
636 | case EFX_LED_OFF: | |
637 | reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) | | |
638 | (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | | |
639 | (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN); | |
640 | break; | |
641 | case EFX_LED_ON: | |
642 | reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) | | |
643 | (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) | | |
644 | (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN); | |
645 | break; | |
646 | default: | |
dcf477b2 BH |
647 | if (efx->phy_type == PHY_TYPE_SFX7101) |
648 | reg = SFX7101_PMA_PMD_LED_DEFAULT; | |
649 | else | |
650 | reg = SFT9001_PMA_PMD_LED_DEFAULT; | |
398468ed BH |
651 | break; |
652 | } | |
8ceee660 | 653 | |
68e7f45e | 654 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
8ceee660 BH |
655 | } |
656 | ||
307505e9 | 657 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
658 | "bist" |
659 | }; | |
660 | ||
c1c4f453 BH |
661 | static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index) |
662 | { | |
663 | if (index < ARRAY_SIZE(sfx7101_test_names)) | |
664 | return sfx7101_test_names[index]; | |
665 | return NULL; | |
666 | } | |
667 | ||
1796721a | 668 | static int |
307505e9 | 669 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 670 | { |
1796721a BH |
671 | int rc; |
672 | ||
673 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
674 | return 0; | |
675 | ||
8c8661e4 | 676 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
677 | rc = tenxpress_special_reset(efx); |
678 | results[0] = rc ? -1 : 1; | |
d3245b28 BH |
679 | |
680 | efx_mdio_an_reconfigure(efx); | |
681 | ||
1796721a | 682 | return rc; |
8c8661e4 BH |
683 | } |
684 | ||
307505e9 BH |
685 | static const char *const sft9001_test_names[] = { |
686 | "bist", | |
687 | "cable.pairA.status", | |
688 | "cable.pairB.status", | |
689 | "cable.pairC.status", | |
690 | "cable.pairD.status", | |
691 | "cable.pairA.length", | |
692 | "cable.pairB.length", | |
693 | "cable.pairC.length", | |
694 | "cable.pairD.length", | |
695 | }; | |
696 | ||
c1c4f453 BH |
697 | static const char *sft9001_test_name(struct efx_nic *efx, unsigned int index) |
698 | { | |
699 | if (index < ARRAY_SIZE(sft9001_test_names)) | |
700 | return sft9001_test_names[index]; | |
701 | return NULL; | |
702 | } | |
703 | ||
307505e9 BH |
704 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
705 | { | |
22ef02c2 | 706 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 707 | |
307505e9 BH |
708 | /* Initialise cable diagnostic results to unknown failure */ |
709 | for (i = 1; i < 9; ++i) | |
710 | results[i] = -1; | |
711 | ||
712 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
713 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
714 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
715 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
716 | if (flags & ETH_TEST_FL_OFFLINE) { | |
717 | /* Break the link in order to run full diagnostics. We | |
718 | * must reset the PHY to resume normal service. */ | |
719 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
720 | } | |
68e7f45e BH |
721 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
722 | ctrl_reg); | |
307505e9 | 723 | i = 0; |
68e7f45e | 724 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
307505e9 BH |
725 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
726 | if (++i == 50) { | |
727 | rc = -ETIMEDOUT; | |
22ef02c2 | 728 | goto out; |
307505e9 BH |
729 | } |
730 | msleep(100); | |
731 | } | |
68e7f45e | 732 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
307505e9 BH |
733 | for (i = 0; i < 4; i++) { |
734 | int pair_res = | |
735 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
736 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
68e7f45e BH |
737 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
738 | PMA_PMD_CDIAG_LEN_REG + i); | |
307505e9 BH |
739 | if (pair_res == CDIAG_RES_OK) |
740 | results[1 + i] = 1; | |
741 | else if (pair_res == CDIAG_RES_INVALID) | |
742 | results[1 + i] = -1; | |
743 | else | |
744 | results[1 + i] = -pair_res; | |
745 | if (pair_res != CDIAG_RES_INVALID && | |
746 | pair_res != CDIAG_RES_OPEN && | |
747 | len_reg != 0xffff) | |
748 | results[5 + i] = len_reg; | |
749 | } | |
750 | ||
22ef02c2 BH |
751 | out: |
752 | if (flags & ETH_TEST_FL_OFFLINE) { | |
753 | /* Reset, running the BIST and then resuming normal service. */ | |
754 | rc2 = tenxpress_special_reset(efx); | |
755 | results[0] = rc2 ? -1 : 1; | |
756 | if (!rc) | |
757 | rc = rc2; | |
758 | ||
d3245b28 | 759 | efx_mdio_an_reconfigure(efx); |
22ef02c2 | 760 | } |
307505e9 BH |
761 | |
762 | return rc; | |
763 | } | |
764 | ||
af4ad9bc BH |
765 | static void |
766 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 767 | { |
af4ad9bc | 768 | u32 adv = 0, lpa = 0; |
04cc8cac BH |
769 | int reg; |
770 | ||
e6fa2eb7 | 771 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
68e7f45e | 772 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
af4ad9bc BH |
773 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
774 | adv |= ADVERTISED_1000baseT_Full; | |
68e7f45e | 775 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
af4ad9bc | 776 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
e6fa2eb7 | 777 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 778 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
779 | lpa |= ADVERTISED_1000baseT_Full; |
780 | } | |
68e7f45e BH |
781 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
782 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | |
af4ad9bc | 783 | adv |= ADVERTISED_10000baseT_Full; |
68e7f45e BH |
784 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
785 | if (reg & MDIO_AN_10GBT_STAT_LP10G) | |
04cc8cac | 786 | lpa |= ADVERTISED_10000baseT_Full; |
04cc8cac | 787 | |
68e7f45e | 788 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
e6fa2eb7 | 789 | |
e762cd70 | 790 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
af4ad9bc BH |
791 | ecmd->supported |= (SUPPORTED_100baseT_Full | |
792 | SUPPORTED_1000baseT_Full); | |
e762cd70 BH |
793 | if (ecmd->speed != SPEED_10000) { |
794 | ecmd->eth_tp_mdix = | |
795 | (efx_mdio_read(efx, MDIO_MMD_PMAPMD, | |
796 | PMA_PMD_XSTATUS_REG) & | |
797 | (1 << PMA_PMD_XSTAT_MDIX_LBN)) | |
798 | ? ETH_TP_MDI_X : ETH_TP_MDI; | |
799 | } | |
800 | } | |
8b9dc8dd SH |
801 | |
802 | /* In loopback, the PHY automatically brings up the correct interface, | |
803 | * but doesn't advertise the correct speed. So override it */ | |
804 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
805 | ecmd->speed = SPEED_1000; | |
c1c4f453 | 806 | else if (LOOPBACK_EXTERNAL(efx)) |
8b9dc8dd | 807 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
808 | } |
809 | ||
af4ad9bc | 810 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 811 | { |
af4ad9bc BH |
812 | if (!ecmd->autoneg) |
813 | return -EINVAL; | |
e6fa2eb7 | 814 | |
68e7f45e | 815 | return efx_mdio_set_settings(efx, ecmd); |
e6fa2eb7 BH |
816 | } |
817 | ||
af4ad9bc | 818 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 819 | { |
68e7f45e BH |
820 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
821 | MDIO_AN_10GBT_CTRL_ADV10G, | |
822 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
823 | } |
824 | ||
af4ad9bc | 825 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 826 | { |
68e7f45e BH |
827 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
828 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
829 | advertising & ADVERTISED_1000baseT_Full); | |
830 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | |
831 | MDIO_AN_10GBT_CTRL_ADV10G, | |
832 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
833 | } |
834 | ||
835 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
ff3b00a0 | 836 | .probe = tenxpress_phy_probe, |
8ceee660 BH |
837 | .init = tenxpress_phy_init, |
838 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 839 | .poll = tenxpress_phy_poll, |
ff3b00a0 SH |
840 | .fini = sfx7101_phy_fini, |
841 | .remove = tenxpress_phy_remove, | |
af4ad9bc BH |
842 | .get_settings = tenxpress_get_settings, |
843 | .set_settings = tenxpress_set_settings, | |
844 | .set_npage_adv = sfx7101_set_npage_adv, | |
c1c4f453 | 845 | .test_name = sfx7101_test_name, |
307505e9 | 846 | .run_tests = sfx7101_run_tests, |
e6fa2eb7 BH |
847 | }; |
848 | ||
849 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
ff3b00a0 | 850 | .probe = tenxpress_phy_probe, |
e6fa2eb7 BH |
851 | .init = tenxpress_phy_init, |
852 | .reconfigure = tenxpress_phy_reconfigure, | |
853 | .poll = tenxpress_phy_poll, | |
ff3b00a0 SH |
854 | .fini = efx_port_dummy_op_void, |
855 | .remove = tenxpress_phy_remove, | |
af4ad9bc BH |
856 | .get_settings = tenxpress_get_settings, |
857 | .set_settings = tenxpress_set_settings, | |
858 | .set_npage_adv = sft9001_set_npage_adv, | |
c1c4f453 | 859 | .test_name = sft9001_test_name, |
307505e9 | 860 | .run_tests = sft9001_run_tests, |
8ceee660 | 861 | }; |