Commit | Line | Data |
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8ceee660 | 1 | /**************************************************************************** |
177dfcd8 BH |
2 | * Driver for Solarflare Solarstorm network controllers and boards |
3 | * Copyright 2007-2008 Solarflare Communications Inc. | |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 BH |
12 | #include <linux/seq_file.h> |
13 | #include "efx.h" | |
8ceee660 BH |
14 | #include "mdio_10g.h" |
15 | #include "falcon.h" | |
16 | #include "phy.h" | |
17 | #include "falcon_hwdefs.h" | |
18 | #include "boards.h" | |
e6fa2eb7 BH |
19 | #include "workarounds.h" |
20 | #include "selftest.h" | |
8ceee660 | 21 | |
e6fa2eb7 BH |
22 | /* We expect these MMDs to be in the package. SFT9001 also has a |
23 | * clause 22 extension MMD, but since it doesn't have all the generic | |
24 | * MMD registers it is pointless to include it here. | |
25 | */ | |
68e7f45e BH |
26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
27 | MDIO_DEVS_PCS | \ | |
28 | MDIO_DEVS_PHYXS | \ | |
29 | MDIO_DEVS_AN) | |
8ceee660 | 30 | |
e6fa2eb7 BH |
31 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
32 | (1 << LOOPBACK_PCS) | \ | |
33 | (1 << LOOPBACK_PMAPMD) | \ | |
34 | (1 << LOOPBACK_NETWORK)) | |
35 | ||
36 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
37 | (1 << LOOPBACK_PHYXS) | \ | |
38 | (1 << LOOPBACK_PCS) | \ | |
39 | (1 << LOOPBACK_PMAPMD) | \ | |
40 | (1 << LOOPBACK_NETWORK)) | |
3273c2e8 | 41 | |
8ceee660 BH |
42 | /* We complain if we fail to see the link partner as 10G capable this many |
43 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
44 | */ | |
45 | #define MAX_BAD_LP_TRIES (5) | |
46 | ||
47 | /* Extended control register */ | |
e6fa2eb7 BH |
48 | #define PMA_PMD_XCONTROL_REG 49152 |
49 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
50 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
51 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
52 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
53 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
54 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
55 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
56 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
57 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
58 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
59 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
60 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
61 | #define PMA_PMD_EXT_SSR_LBN 15 |
62 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
63 | |
64 | /* extended status register */ | |
e6fa2eb7 | 65 | #define PMA_PMD_XSTATUS_REG 49153 |
e762cd70 | 66 | #define PMA_PMD_XSTAT_MDIX_LBN 14 |
8ceee660 BH |
67 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
68 | ||
69 | /* LED control register */ | |
e6fa2eb7 | 70 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
71 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
72 | ||
73 | /* LED function override register */ | |
e6fa2eb7 | 74 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
75 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
76 | #define PMA_PMD_LED_LINK_LBN (0) | |
77 | #define PMA_PMD_LED_SPEED_LBN (2) | |
78 | #define PMA_PMD_LED_TX_LBN (4) | |
79 | #define PMA_PMD_LED_RX_LBN (6) | |
80 | /* Override settings */ | |
81 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
82 | #define PMA_PMD_LED_ON (1) | |
83 | #define PMA_PMD_LED_OFF (2) | |
84 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 85 | #define PMA_PMD_LED_MASK 3 |
8ceee660 BH |
86 | /* All LEDs under hardware control */ |
87 | #define PMA_PMD_LED_FULL_AUTO (0) | |
88 | /* Green and Amber under hardware control, Red off */ | |
89 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | |
90 | ||
e6fa2eb7 BH |
91 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
92 | #define PMA_PMD_100TX_ADV_LBN 1 | |
93 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
94 | #define PMA_PMD_1000T_ADV_LBN 2 | |
95 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
96 | #define PMA_PMD_10000T_ADV_LBN 3 | |
97 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
98 | #define PMA_PMD_SPEED_LBN 4 | |
99 | #define PMA_PMD_SPEED_WIDTH 4 | |
100 | ||
307505e9 BH |
101 | /* Cable diagnostics - SFT9001 only */ |
102 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
103 | #define CDIAG_CTRL_IMMED_LBN 15 | |
104 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
105 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
106 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
107 | #define CDIAG_CTRL_LEN_METRES 1 | |
108 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
109 | #define CDIAG_RES_A_LBN 12 | |
110 | #define CDIAG_RES_B_LBN 8 | |
111 | #define CDIAG_RES_C_LBN 4 | |
112 | #define CDIAG_RES_D_LBN 0 | |
113 | #define CDIAG_RES_WIDTH 4 | |
114 | #define CDIAG_RES_OPEN 2 | |
115 | #define CDIAG_RES_OK 1 | |
116 | #define CDIAG_RES_INVALID 0 | |
117 | /* Set of 4 registers for pairs A-D */ | |
118 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
119 | ||
e6fa2eb7 BH |
120 | /* Serdes control registers - SFT9001 only */ |
121 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
122 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
123 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
124 | ||
125 | /* Misc register defines - SFX7101 only */ | |
126 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
127 | #define PLL312_RST_N_LBN 2 |
128 | ||
e6fa2eb7 | 129 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
130 | #define SERDES_RST_N_LBN 13 |
131 | #define XGXS_RST_N_LBN 12 | |
132 | ||
e6fa2eb7 | 133 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
134 | #define CLK312_EN_LBN 3 |
135 | ||
3273c2e8 | 136 | /* PHYXS registers */ |
e6fa2eb7 BH |
137 | #define PHYXS_XCONTROL_REG 49152 |
138 | #define PHYXS_RESET_LBN 15 | |
139 | #define PHYXS_RESET_WIDTH 1 | |
140 | ||
3273c2e8 BH |
141 | #define PHYXS_TEST1 (49162) |
142 | #define LOOPBACK_NEAR_LBN (8) | |
143 | #define LOOPBACK_NEAR_WIDTH (1) | |
144 | ||
8ceee660 | 145 | /* Boot status register */ |
190dbcfd BH |
146 | #define PCS_BOOT_STATUS_REG 53248 |
147 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
148 | #define PCS_BOOT_PROGRESS_LBN 1 | |
149 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
150 | #define PCS_BOOT_PROGRESS_INIT 0 | |
151 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
152 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
153 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
154 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
155 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 156 | |
e6fa2eb7 BH |
157 | /* 100M/1G PHY registers */ |
158 | #define GPHY_XCONTROL_REG 49152 | |
159 | #define GPHY_ISOLATE_LBN 10 | |
160 | #define GPHY_ISOLATE_WIDTH 1 | |
161 | #define GPHY_DUPLEX_LBN 8 | |
162 | #define GPHY_DUPLEX_WIDTH 1 | |
163 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
164 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
165 | ||
166 | #define C22EXT_STATUS_REG 49153 | |
167 | #define C22EXT_STATUS_LINK_LBN 2 | |
168 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
169 | ||
af4ad9bc BH |
170 | #define C22EXT_MSTSLV_CTRL 49161 |
171 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
172 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
173 | ||
174 | #define C22EXT_MSTSLV_STATUS 49162 | |
175 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
176 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 177 | |
8ceee660 BH |
178 | /* Time to wait between powering down the LNPGA and turning off the power |
179 | * rails */ | |
180 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
181 | ||
8ceee660 | 182 | struct tenxpress_phy_data { |
3273c2e8 | 183 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 184 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
185 | int bad_lp_tries; |
186 | }; | |
187 | ||
e6fa2eb7 BH |
188 | static ssize_t show_phy_short_reach(struct device *dev, |
189 | struct device_attribute *attr, char *buf) | |
190 | { | |
191 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
192 | int reg; | |
193 | ||
68e7f45e BH |
194 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
195 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | |
e6fa2eb7 BH |
196 | } |
197 | ||
198 | static ssize_t set_phy_short_reach(struct device *dev, | |
199 | struct device_attribute *attr, | |
200 | const char *buf, size_t count) | |
201 | { | |
202 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
203 | ||
204 | rtnl_lock(); | |
68e7f45e BH |
205 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, |
206 | MDIO_PMA_10GBT_TXPWR_SHORT, | |
207 | count != 0 && *buf != '0'); | |
e6fa2eb7 BH |
208 | efx_reconfigure_port(efx); |
209 | rtnl_unlock(); | |
210 | ||
211 | return count; | |
212 | } | |
213 | ||
214 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
215 | set_phy_short_reach); | |
216 | ||
190dbcfd | 217 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 218 | { |
190dbcfd | 219 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
220 | int boot_stat; |
221 | ||
190dbcfd | 222 | for (;;) { |
68e7f45e BH |
223 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
224 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
225 | if (boot_stat >= 0) { |
226 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
227 | switch (boot_stat & | |
228 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
229 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
230 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
231 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
232 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
233 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
234 | PCS_BOOT_PROGRESS_LBN)): | |
235 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
236 | (PCS_BOOT_PROGRESS_INIT << | |
237 | PCS_BOOT_PROGRESS_LBN) | | |
238 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
239 | return -EINVAL; | |
240 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
241 | PCS_BOOT_PROGRESS_LBN) | | |
242 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
243 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
244 | 0 : -EIO; | |
245 | case ((PCS_BOOT_PROGRESS_JUMP << | |
246 | PCS_BOOT_PROGRESS_LBN) | | |
247 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
248 | case ((PCS_BOOT_PROGRESS_JUMP << | |
249 | PCS_BOOT_PROGRESS_LBN) | | |
250 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
251 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
252 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
253 | -EIO : 0; | |
254 | default: | |
255 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
256 | return -EIO; | |
257 | break; | |
258 | } | |
259 | } | |
260 | ||
261 | if (time_after_eq(jiffies, timeout)) | |
262 | return -ETIMEDOUT; | |
263 | ||
264 | msleep(50); | |
8ceee660 | 265 | } |
8ceee660 BH |
266 | } |
267 | ||
8ceee660 BH |
268 | static int tenxpress_init(struct efx_nic *efx) |
269 | { | |
e6fa2eb7 | 270 | int reg; |
8ceee660 | 271 | |
e6fa2eb7 BH |
272 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
273 | /* Enable 312.5 MHz clock */ | |
68e7f45e BH |
274 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
275 | 1 << CLK312_EN_LBN); | |
e6fa2eb7 BH |
276 | } else { |
277 | /* Enable 312.5 MHz clock and GMII */ | |
68e7f45e | 278 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
e6fa2eb7 BH |
279 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
280 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
281 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
282 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
283 | ||
68e7f45e BH |
284 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
285 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | |
286 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | |
287 | false); | |
e6fa2eb7 | 288 | } |
8ceee660 | 289 | |
8ceee660 | 290 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 | 291 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
68e7f45e BH |
292 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
293 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | |
294 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | |
295 | PMA_PMD_LED_DEFAULT); | |
e6fa2eb7 | 296 | } |
8ceee660 | 297 | |
190dbcfd | 298 | return 0; |
8ceee660 BH |
299 | } |
300 | ||
301 | static int tenxpress_phy_init(struct efx_nic *efx) | |
302 | { | |
303 | struct tenxpress_phy_data *phy_data; | |
304 | int rc = 0; | |
305 | ||
306 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
9b7bfc4c BH |
307 | if (!phy_data) |
308 | return -ENOMEM; | |
8ceee660 | 309 | efx->phy_data = phy_data; |
f8b87c17 | 310 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 311 | |
e6fa2eb7 BH |
312 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
313 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
314 | int reg; | |
68e7f45e BH |
315 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
316 | PMA_PMD_XCONTROL_REG); | |
e6fa2eb7 | 317 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e BH |
318 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
319 | PMA_PMD_XCONTROL_REG, reg); | |
e6fa2eb7 BH |
320 | mdelay(200); |
321 | } | |
8ceee660 | 322 | |
68e7f45e | 323 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
e6fa2eb7 BH |
324 | if (rc < 0) |
325 | goto fail; | |
326 | ||
68e7f45e | 327 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
e6fa2eb7 BH |
328 | if (rc < 0) |
329 | goto fail; | |
330 | } | |
8ceee660 BH |
331 | |
332 | rc = tenxpress_init(efx); | |
333 | if (rc < 0) | |
334 | goto fail; | |
335 | ||
e6fa2eb7 BH |
336 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
337 | rc = device_create_file(&efx->pci_dev->dev, | |
338 | &dev_attr_phy_short_reach); | |
339 | if (rc) | |
340 | goto fail; | |
341 | } | |
342 | ||
8ceee660 BH |
343 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
344 | ||
e6fa2eb7 | 345 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
346 | falcon_reset_xaui(efx); |
347 | ||
348 | return 0; | |
349 | ||
350 | fail: | |
351 | kfree(efx->phy_data); | |
352 | efx->phy_data = NULL; | |
353 | return rc; | |
354 | } | |
355 | ||
e6fa2eb7 BH |
356 | /* Perform a "special software reset" on the PHY. The caller is |
357 | * responsible for saving and restoring the PHY hardware registers | |
358 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
359 | static int tenxpress_special_reset(struct efx_nic *efx) |
360 | { | |
361 | int rc, reg; | |
362 | ||
c8fcc49c BH |
363 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
364 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 BH |
365 | * requests to fail. */ |
366 | efx_stats_disable(efx); | |
3273c2e8 BH |
367 | |
368 | /* Initiate reset */ | |
68e7f45e | 369 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 | 370 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e | 371 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 372 | |
c8fcc49c | 373 | mdelay(200); |
3273c2e8 BH |
374 | |
375 | /* Wait for the blocks to come out of reset */ | |
68e7f45e | 376 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
3273c2e8 | 377 | if (rc < 0) |
1974cc20 | 378 | goto out; |
3273c2e8 BH |
379 | |
380 | /* Try and reconfigure the device */ | |
381 | rc = tenxpress_init(efx); | |
382 | if (rc < 0) | |
1974cc20 | 383 | goto out; |
3273c2e8 | 384 | |
e6fa2eb7 BH |
385 | /* Wait for the XGXS state machine to churn */ |
386 | mdelay(10); | |
1974cc20 BH |
387 | out: |
388 | efx_stats_enable(efx); | |
c8fcc49c | 389 | return rc; |
3273c2e8 BH |
390 | } |
391 | ||
e6fa2eb7 | 392 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
393 | { |
394 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac | 395 | bool bad_lp; |
8ceee660 BH |
396 | int reg; |
397 | ||
04cc8cac BH |
398 | if (link_ok) { |
399 | bad_lp = false; | |
400 | } else { | |
401 | /* Check that AN has started but not completed. */ | |
68e7f45e BH |
402 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
403 | if (!(reg & MDIO_AN_STAT1_LPABLE)) | |
04cc8cac | 404 | return; /* LP status is unknown */ |
68e7f45e | 405 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
04cc8cac BH |
406 | if (bad_lp) |
407 | pd->bad_lp_tries++; | |
408 | } | |
409 | ||
8ceee660 | 410 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 411 | if (!pd->bad_lp_tries) |
8ceee660 BH |
412 | return; |
413 | ||
04cc8cac BH |
414 | /* Use the RX (red) LED as an error indicator once we've seen AN |
415 | * failure several times in a row, and also log a message. */ | |
416 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
68e7f45e BH |
417 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
418 | PMA_PMD_LED_OVERR_REG); | |
04cc8cac BH |
419 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
420 | if (!bad_lp) { | |
421 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
422 | } else { | |
423 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
424 | EFX_ERR(efx, "appears to be plugged into a port" | |
425 | " that is not 10GBASE-T capable. The PHY" | |
426 | " supports 10GBASE-T ONLY, so no link can" | |
427 | " be established\n"); | |
428 | } | |
68e7f45e BH |
429 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
430 | PMA_PMD_LED_OVERR_REG, reg); | |
04cc8cac | 431 | pd->bad_lp_tries = bad_lp; |
8ceee660 | 432 | } |
8ceee660 BH |
433 | } |
434 | ||
e6fa2eb7 | 435 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 436 | { |
68e7f45e BH |
437 | return efx_mdio_links_ok(efx, |
438 | MDIO_DEVS_PMAPMD | | |
439 | MDIO_DEVS_PCS | | |
440 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
441 | } |
442 | ||
443 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
444 | { | |
e6fa2eb7 BH |
445 | u32 reg; |
446 | ||
caa8d8bb | 447 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 448 | return false; |
caa8d8bb BH |
449 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
450 | return true; | |
e6fa2eb7 | 451 | else if (efx->loopback_mode) |
68e7f45e BH |
452 | return efx_mdio_links_ok(efx, |
453 | MDIO_DEVS_PMAPMD | | |
454 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
455 | |
456 | /* We must use the same definition of link state as LASI, | |
457 | * otherwise we can miss a link state transition | |
458 | */ | |
459 | if (ecmd->speed == 10000) { | |
68e7f45e BH |
460 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
461 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | |
e6fa2eb7 | 462 | } else { |
68e7f45e | 463 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
e6fa2eb7 BH |
464 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
465 | } | |
8ceee660 BH |
466 | } |
467 | ||
e6fa2eb7 | 468 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 | 469 | { |
68e7f45e BH |
470 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
471 | 1 << LOOPBACK_NEAR_LBN, | |
472 | efx->loopback_mode == LOOPBACK_PHYXS); | |
e6fa2eb7 | 473 | if (efx->phy_type != PHY_TYPE_SFX7101) |
68e7f45e BH |
474 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
475 | 1 << GPHY_LOOPBACK_NEAR_LBN, | |
476 | efx->loopback_mode == LOOPBACK_GPHY); | |
e6fa2eb7 BH |
477 | } |
478 | ||
479 | static void tenxpress_low_power(struct efx_nic *efx) | |
480 | { | |
e6fa2eb7 | 481 | if (efx->phy_type == PHY_TYPE_SFX7101) |
68e7f45e | 482 | efx_mdio_set_mmds_lpower( |
e6fa2eb7 BH |
483 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
484 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 485 | else |
68e7f45e BH |
486 | efx_mdio_set_flag( |
487 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | |
488 | 1 << PMA_PMD_EXT_LPOWER_LBN, | |
e6fa2eb7 | 489 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
3273c2e8 BH |
490 | } |
491 | ||
8ceee660 BH |
492 | static void tenxpress_phy_reconfigure(struct efx_nic *efx) |
493 | { | |
3273c2e8 | 494 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
e6fa2eb7 | 495 | struct ethtool_cmd ecmd; |
8b9dc8dd | 496 | bool phy_mode_change, loop_reset; |
3273c2e8 | 497 | |
e6fa2eb7 | 498 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 499 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 500 | return; |
f8b87c17 | 501 | } |
8ceee660 | 502 | |
e6fa2eb7 BH |
503 | tenxpress_low_power(efx); |
504 | ||
505 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && | |
506 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
e6fa2eb7 BH |
507 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) || |
508 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); | |
509 | ||
8b9dc8dd | 510 | if (loop_reset || phy_mode_change) { |
e6fa2eb7 BH |
511 | int rc; |
512 | ||
513 | efx->phy_op->get_settings(efx, &ecmd); | |
514 | ||
515 | if (loop_reset || phy_mode_change) { | |
516 | tenxpress_special_reset(efx); | |
517 | ||
518 | /* Reset XAUI if we were in 10G, and are staying | |
519 | * in 10G. If we're moving into and out of 10G | |
520 | * then xaui will be reset anyway */ | |
521 | if (EFX_IS10G(efx)) | |
522 | falcon_reset_xaui(efx); | |
523 | } | |
524 | ||
e6fa2eb7 BH |
525 | rc = efx->phy_op->set_settings(efx, &ecmd); |
526 | WARN_ON(rc); | |
3273c2e8 BH |
527 | } |
528 | ||
68e7f45e BH |
529 | efx_mdio_transmit_disable(efx); |
530 | efx_mdio_phy_reconfigure(efx); | |
e6fa2eb7 | 531 | tenxpress_ext_loopback(efx); |
3273c2e8 | 532 | |
3273c2e8 | 533 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 534 | phy_data->phy_mode = efx->phy_mode; |
e6fa2eb7 BH |
535 | |
536 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
537 | efx->link_speed = 10000; | |
538 | efx->link_fd = true; | |
539 | efx->link_up = sfx7101_link_ok(efx); | |
540 | } else { | |
541 | efx->phy_op->get_settings(efx, &ecmd); | |
542 | efx->link_speed = ecmd.speed; | |
543 | efx->link_fd = ecmd.duplex == DUPLEX_FULL; | |
544 | efx->link_up = sft9001_link_ok(efx, &ecmd); | |
545 | } | |
68e7f45e | 546 | efx->link_fc = efx_mdio_get_pause(efx); |
8ceee660 BH |
547 | } |
548 | ||
8ceee660 | 549 | /* Poll PHY for interrupt */ |
766ca0fa | 550 | static void tenxpress_phy_poll(struct efx_nic *efx) |
8ceee660 BH |
551 | { |
552 | struct tenxpress_phy_data *phy_data = efx->phy_data; | |
37d37695 | 553 | bool change = false; |
8ceee660 | 554 | |
e6fa2eb7 | 555 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
37d37695 | 556 | bool link_ok = sfx7101_link_ok(efx); |
e6fa2eb7 BH |
557 | if (link_ok != efx->link_up) { |
558 | change = true; | |
559 | } else { | |
68e7f45e | 560 | unsigned int link_fc = efx_mdio_get_pause(efx); |
e6fa2eb7 BH |
561 | if (link_fc != efx->link_fc) |
562 | change = true; | |
563 | } | |
564 | sfx7101_check_bad_lp(efx, link_ok); | |
caa8d8bb BH |
565 | } else if (efx->loopback_mode) { |
566 | bool link_ok = sft9001_link_ok(efx, NULL); | |
567 | if (link_ok != efx->link_up) | |
568 | change = true; | |
766ca0fa | 569 | } else { |
68e7f45e | 570 | int status = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
6bc5046e BH |
571 | MDIO_PMA_LASI_STAT); |
572 | if (status & MDIO_PMA_LASI_LSALARM) | |
766ca0fa BH |
573 | change = true; |
574 | } | |
8ceee660 | 575 | |
766ca0fa | 576 | if (change) |
177dfcd8 | 577 | falcon_sim_phy_event(efx); |
8ceee660 | 578 | |
f8b87c17 | 579 | if (phy_data->phy_mode != PHY_MODE_NORMAL) |
766ca0fa | 580 | return; |
8ceee660 BH |
581 | } |
582 | ||
583 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
584 | { | |
585 | int reg; | |
586 | ||
2a7e637d | 587 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
588 | device_remove_file(&efx->pci_dev->dev, |
589 | &dev_attr_phy_short_reach); | |
2a7e637d BH |
590 | |
591 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
e6fa2eb7 BH |
592 | /* Power down the LNPGA */ |
593 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
68e7f45e | 594 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
e6fa2eb7 BH |
595 | |
596 | /* Waiting here ensures that the board fini, which can turn | |
597 | * off the power to the PHY, won't get run until the LNPGA | |
598 | * powerdown has been given long enough to complete. */ | |
599 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
600 | } | |
8ceee660 BH |
601 | |
602 | kfree(efx->phy_data); | |
603 | efx->phy_data = NULL; | |
604 | } | |
605 | ||
606 | ||
607 | /* Set the RX and TX LEDs and Link LED flashing. The other LEDs | |
608 | * (which probably aren't wired anyway) are left in AUTO mode */ | |
dc8cfa55 | 609 | void tenxpress_phy_blink(struct efx_nic *efx, bool blink) |
8ceee660 BH |
610 | { |
611 | int reg; | |
612 | ||
613 | if (blink) | |
614 | reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) | | |
615 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) | | |
616 | (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN); | |
617 | else | |
618 | reg = PMA_PMD_LED_DEFAULT; | |
619 | ||
68e7f45e | 620 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
8ceee660 BH |
621 | } |
622 | ||
307505e9 | 623 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
624 | "bist" |
625 | }; | |
626 | ||
627 | static int | |
307505e9 | 628 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 629 | { |
1796721a BH |
630 | int rc; |
631 | ||
632 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
633 | return 0; | |
634 | ||
8c8661e4 | 635 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
636 | rc = tenxpress_special_reset(efx); |
637 | results[0] = rc ? -1 : 1; | |
638 | return rc; | |
8c8661e4 BH |
639 | } |
640 | ||
307505e9 BH |
641 | static const char *const sft9001_test_names[] = { |
642 | "bist", | |
643 | "cable.pairA.status", | |
644 | "cable.pairB.status", | |
645 | "cable.pairC.status", | |
646 | "cable.pairD.status", | |
647 | "cable.pairA.length", | |
648 | "cable.pairB.length", | |
649 | "cable.pairC.length", | |
650 | "cable.pairD.length", | |
651 | }; | |
652 | ||
653 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |
654 | { | |
655 | struct ethtool_cmd ecmd; | |
22ef02c2 | 656 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 657 | |
22ef02c2 BH |
658 | if (flags & ETH_TEST_FL_OFFLINE) |
659 | efx->phy_op->get_settings(efx, &ecmd); | |
307505e9 BH |
660 | |
661 | /* Initialise cable diagnostic results to unknown failure */ | |
662 | for (i = 1; i < 9; ++i) | |
663 | results[i] = -1; | |
664 | ||
665 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
666 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
667 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
668 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
669 | if (flags & ETH_TEST_FL_OFFLINE) { | |
670 | /* Break the link in order to run full diagnostics. We | |
671 | * must reset the PHY to resume normal service. */ | |
672 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
673 | } | |
68e7f45e BH |
674 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
675 | ctrl_reg); | |
307505e9 | 676 | i = 0; |
68e7f45e | 677 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
307505e9 BH |
678 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
679 | if (++i == 50) { | |
680 | rc = -ETIMEDOUT; | |
22ef02c2 | 681 | goto out; |
307505e9 BH |
682 | } |
683 | msleep(100); | |
684 | } | |
68e7f45e | 685 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
307505e9 BH |
686 | for (i = 0; i < 4; i++) { |
687 | int pair_res = | |
688 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
689 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
68e7f45e BH |
690 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
691 | PMA_PMD_CDIAG_LEN_REG + i); | |
307505e9 BH |
692 | if (pair_res == CDIAG_RES_OK) |
693 | results[1 + i] = 1; | |
694 | else if (pair_res == CDIAG_RES_INVALID) | |
695 | results[1 + i] = -1; | |
696 | else | |
697 | results[1 + i] = -pair_res; | |
698 | if (pair_res != CDIAG_RES_INVALID && | |
699 | pair_res != CDIAG_RES_OPEN && | |
700 | len_reg != 0xffff) | |
701 | results[5 + i] = len_reg; | |
702 | } | |
703 | ||
22ef02c2 BH |
704 | out: |
705 | if (flags & ETH_TEST_FL_OFFLINE) { | |
706 | /* Reset, running the BIST and then resuming normal service. */ | |
707 | rc2 = tenxpress_special_reset(efx); | |
708 | results[0] = rc2 ? -1 : 1; | |
709 | if (!rc) | |
710 | rc = rc2; | |
711 | ||
712 | rc2 = efx->phy_op->set_settings(efx, &ecmd); | |
713 | if (!rc) | |
714 | rc = rc2; | |
715 | } | |
307505e9 BH |
716 | |
717 | return rc; | |
718 | } | |
719 | ||
af4ad9bc BH |
720 | static void |
721 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 722 | { |
af4ad9bc | 723 | u32 adv = 0, lpa = 0; |
04cc8cac BH |
724 | int reg; |
725 | ||
e6fa2eb7 | 726 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
68e7f45e | 727 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
af4ad9bc BH |
728 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
729 | adv |= ADVERTISED_1000baseT_Full; | |
68e7f45e | 730 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
af4ad9bc | 731 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
e6fa2eb7 | 732 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 733 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
734 | lpa |= ADVERTISED_1000baseT_Full; |
735 | } | |
68e7f45e BH |
736 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
737 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | |
af4ad9bc | 738 | adv |= ADVERTISED_10000baseT_Full; |
68e7f45e BH |
739 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
740 | if (reg & MDIO_AN_10GBT_STAT_LP10G) | |
04cc8cac | 741 | lpa |= ADVERTISED_10000baseT_Full; |
04cc8cac | 742 | |
68e7f45e | 743 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
e6fa2eb7 | 744 | |
e762cd70 | 745 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
af4ad9bc BH |
746 | ecmd->supported |= (SUPPORTED_100baseT_Full | |
747 | SUPPORTED_1000baseT_Full); | |
e762cd70 BH |
748 | if (ecmd->speed != SPEED_10000) { |
749 | ecmd->eth_tp_mdix = | |
750 | (efx_mdio_read(efx, MDIO_MMD_PMAPMD, | |
751 | PMA_PMD_XSTATUS_REG) & | |
752 | (1 << PMA_PMD_XSTAT_MDIX_LBN)) | |
753 | ? ETH_TP_MDI_X : ETH_TP_MDI; | |
754 | } | |
755 | } | |
8b9dc8dd SH |
756 | |
757 | /* In loopback, the PHY automatically brings up the correct interface, | |
758 | * but doesn't advertise the correct speed. So override it */ | |
759 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
760 | ecmd->speed = SPEED_1000; | |
af4ad9bc | 761 | else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks) |
8b9dc8dd | 762 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
763 | } |
764 | ||
af4ad9bc | 765 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 766 | { |
af4ad9bc BH |
767 | if (!ecmd->autoneg) |
768 | return -EINVAL; | |
e6fa2eb7 | 769 | |
68e7f45e | 770 | return efx_mdio_set_settings(efx, ecmd); |
e6fa2eb7 BH |
771 | } |
772 | ||
af4ad9bc | 773 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 774 | { |
68e7f45e BH |
775 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
776 | MDIO_AN_10GBT_CTRL_ADV10G, | |
777 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
778 | } |
779 | ||
af4ad9bc | 780 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 781 | { |
68e7f45e BH |
782 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
783 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
784 | advertising & ADVERTISED_1000baseT_Full); | |
785 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | |
786 | MDIO_AN_10GBT_CTRL_ADV10G, | |
787 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
788 | } |
789 | ||
790 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
177dfcd8 | 791 | .macs = EFX_XMAC, |
8ceee660 BH |
792 | .init = tenxpress_phy_init, |
793 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 794 | .poll = tenxpress_phy_poll, |
8ceee660 | 795 | .fini = tenxpress_phy_fini, |
766ca0fa | 796 | .clear_interrupt = efx_port_dummy_op_void, |
af4ad9bc BH |
797 | .get_settings = tenxpress_get_settings, |
798 | .set_settings = tenxpress_set_settings, | |
799 | .set_npage_adv = sfx7101_set_npage_adv, | |
307505e9 BH |
800 | .num_tests = ARRAY_SIZE(sfx7101_test_names), |
801 | .test_names = sfx7101_test_names, | |
802 | .run_tests = sfx7101_run_tests, | |
8ceee660 | 803 | .mmds = TENXPRESS_REQUIRED_DEVS, |
e6fa2eb7 BH |
804 | .loopbacks = SFX7101_LOOPBACKS, |
805 | }; | |
806 | ||
807 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
808 | .macs = EFX_GMAC | EFX_XMAC, | |
809 | .init = tenxpress_phy_init, | |
810 | .reconfigure = tenxpress_phy_reconfigure, | |
811 | .poll = tenxpress_phy_poll, | |
812 | .fini = tenxpress_phy_fini, | |
813 | .clear_interrupt = efx_port_dummy_op_void, | |
af4ad9bc BH |
814 | .get_settings = tenxpress_get_settings, |
815 | .set_settings = tenxpress_set_settings, | |
816 | .set_npage_adv = sft9001_set_npage_adv, | |
307505e9 BH |
817 | .num_tests = ARRAY_SIZE(sft9001_test_names), |
818 | .test_names = sft9001_test_names, | |
819 | .run_tests = sft9001_run_tests, | |
e6fa2eb7 BH |
820 | .mmds = TENXPRESS_REQUIRED_DEVS, |
821 | .loopbacks = SFT9001_LOOPBACKS, | |
8ceee660 | 822 | }; |