Commit | Line | Data |
---|---|---|
8ceee660 | 1 | /**************************************************************************** |
177dfcd8 | 2 | * Driver for Solarflare Solarstorm network controllers and boards |
906bb26c | 3 | * Copyright 2007-2009 Solarflare Communications Inc. |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 BH |
12 | #include <linux/seq_file.h> |
13 | #include "efx.h" | |
8ceee660 | 14 | #include "mdio_10g.h" |
744093c9 | 15 | #include "nic.h" |
8ceee660 | 16 | #include "phy.h" |
3e6c4538 | 17 | #include "regs.h" |
e6fa2eb7 BH |
18 | #include "workarounds.h" |
19 | #include "selftest.h" | |
8ceee660 | 20 | |
e6fa2eb7 BH |
21 | /* We expect these MMDs to be in the package. SFT9001 also has a |
22 | * clause 22 extension MMD, but since it doesn't have all the generic | |
23 | * MMD registers it is pointless to include it here. | |
24 | */ | |
68e7f45e BH |
25 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
26 | MDIO_DEVS_PCS | \ | |
27 | MDIO_DEVS_PHYXS | \ | |
28 | MDIO_DEVS_AN) | |
8ceee660 | 29 | |
e6fa2eb7 BH |
30 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
31 | (1 << LOOPBACK_PCS) | \ | |
32 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 33 | (1 << LOOPBACK_PHYXS_WS)) |
e6fa2eb7 BH |
34 | |
35 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
36 | (1 << LOOPBACK_PHYXS) | \ | |
37 | (1 << LOOPBACK_PCS) | \ | |
38 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 39 | (1 << LOOPBACK_PHYXS_WS)) |
3273c2e8 | 40 | |
8ceee660 BH |
41 | /* We complain if we fail to see the link partner as 10G capable this many |
42 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
43 | */ | |
44 | #define MAX_BAD_LP_TRIES (5) | |
45 | ||
46 | /* Extended control register */ | |
e6fa2eb7 BH |
47 | #define PMA_PMD_XCONTROL_REG 49152 |
48 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
49 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
50 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
51 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
52 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
53 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
54 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
55 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
56 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
57 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
58 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
59 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
60 | #define PMA_PMD_EXT_SSR_LBN 15 |
61 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
62 | |
63 | /* extended status register */ | |
e6fa2eb7 | 64 | #define PMA_PMD_XSTATUS_REG 49153 |
e762cd70 | 65 | #define PMA_PMD_XSTAT_MDIX_LBN 14 |
8ceee660 BH |
66 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
67 | ||
68 | /* LED control register */ | |
e6fa2eb7 | 69 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
70 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
71 | ||
72 | /* LED function override register */ | |
e6fa2eb7 | 73 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
74 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
75 | #define PMA_PMD_LED_LINK_LBN (0) | |
76 | #define PMA_PMD_LED_SPEED_LBN (2) | |
77 | #define PMA_PMD_LED_TX_LBN (4) | |
78 | #define PMA_PMD_LED_RX_LBN (6) | |
79 | /* Override settings */ | |
80 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
81 | #define PMA_PMD_LED_ON (1) | |
82 | #define PMA_PMD_LED_OFF (2) | |
83 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 84 | #define PMA_PMD_LED_MASK 3 |
8ceee660 | 85 | /* All LEDs under hardware control */ |
dcf477b2 | 86 | #define SFT9001_PMA_PMD_LED_DEFAULT 0 |
8ceee660 | 87 | /* Green and Amber under hardware control, Red off */ |
dcf477b2 | 88 | #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
8ceee660 | 89 | |
e6fa2eb7 BH |
90 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
91 | #define PMA_PMD_100TX_ADV_LBN 1 | |
92 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
93 | #define PMA_PMD_1000T_ADV_LBN 2 | |
94 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
95 | #define PMA_PMD_10000T_ADV_LBN 3 | |
96 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
97 | #define PMA_PMD_SPEED_LBN 4 | |
98 | #define PMA_PMD_SPEED_WIDTH 4 | |
99 | ||
307505e9 BH |
100 | /* Cable diagnostics - SFT9001 only */ |
101 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
102 | #define CDIAG_CTRL_IMMED_LBN 15 | |
103 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
104 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
105 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
106 | #define CDIAG_CTRL_LEN_METRES 1 | |
107 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
108 | #define CDIAG_RES_A_LBN 12 | |
109 | #define CDIAG_RES_B_LBN 8 | |
110 | #define CDIAG_RES_C_LBN 4 | |
111 | #define CDIAG_RES_D_LBN 0 | |
112 | #define CDIAG_RES_WIDTH 4 | |
113 | #define CDIAG_RES_OPEN 2 | |
114 | #define CDIAG_RES_OK 1 | |
115 | #define CDIAG_RES_INVALID 0 | |
116 | /* Set of 4 registers for pairs A-D */ | |
117 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
118 | ||
e6fa2eb7 BH |
119 | /* Serdes control registers - SFT9001 only */ |
120 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
121 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
122 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
123 | ||
124 | /* Misc register defines - SFX7101 only */ | |
125 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
126 | #define PLL312_RST_N_LBN 2 |
127 | ||
e6fa2eb7 | 128 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
129 | #define SERDES_RST_N_LBN 13 |
130 | #define XGXS_RST_N_LBN 12 | |
131 | ||
e6fa2eb7 | 132 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
133 | #define CLK312_EN_LBN 3 |
134 | ||
3273c2e8 | 135 | /* PHYXS registers */ |
e6fa2eb7 BH |
136 | #define PHYXS_XCONTROL_REG 49152 |
137 | #define PHYXS_RESET_LBN 15 | |
138 | #define PHYXS_RESET_WIDTH 1 | |
139 | ||
3273c2e8 BH |
140 | #define PHYXS_TEST1 (49162) |
141 | #define LOOPBACK_NEAR_LBN (8) | |
142 | #define LOOPBACK_NEAR_WIDTH (1) | |
143 | ||
8ceee660 | 144 | /* Boot status register */ |
190dbcfd BH |
145 | #define PCS_BOOT_STATUS_REG 53248 |
146 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
147 | #define PCS_BOOT_PROGRESS_LBN 1 | |
148 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
149 | #define PCS_BOOT_PROGRESS_INIT 0 | |
150 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
151 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
152 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
153 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
154 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 155 | |
e6fa2eb7 BH |
156 | /* 100M/1G PHY registers */ |
157 | #define GPHY_XCONTROL_REG 49152 | |
158 | #define GPHY_ISOLATE_LBN 10 | |
159 | #define GPHY_ISOLATE_WIDTH 1 | |
160 | #define GPHY_DUPLEX_LBN 8 | |
161 | #define GPHY_DUPLEX_WIDTH 1 | |
162 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
163 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
164 | ||
165 | #define C22EXT_STATUS_REG 49153 | |
166 | #define C22EXT_STATUS_LINK_LBN 2 | |
167 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
168 | ||
af4ad9bc BH |
169 | #define C22EXT_MSTSLV_CTRL 49161 |
170 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
171 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
172 | ||
173 | #define C22EXT_MSTSLV_STATUS 49162 | |
174 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
175 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 176 | |
8ceee660 BH |
177 | /* Time to wait between powering down the LNPGA and turning off the power |
178 | * rails */ | |
179 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
180 | ||
8ceee660 | 181 | struct tenxpress_phy_data { |
3273c2e8 | 182 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 183 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
184 | int bad_lp_tries; |
185 | }; | |
186 | ||
e6fa2eb7 BH |
187 | static ssize_t show_phy_short_reach(struct device *dev, |
188 | struct device_attribute *attr, char *buf) | |
189 | { | |
190 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
191 | int reg; | |
192 | ||
68e7f45e BH |
193 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
194 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | |
e6fa2eb7 BH |
195 | } |
196 | ||
197 | static ssize_t set_phy_short_reach(struct device *dev, | |
198 | struct device_attribute *attr, | |
199 | const char *buf, size_t count) | |
200 | { | |
201 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
d3245b28 | 202 | int rc; |
e6fa2eb7 BH |
203 | |
204 | rtnl_lock(); | |
68e7f45e BH |
205 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, |
206 | MDIO_PMA_10GBT_TXPWR_SHORT, | |
207 | count != 0 && *buf != '0'); | |
d3245b28 | 208 | rc = efx_reconfigure_port(efx); |
e6fa2eb7 BH |
209 | rtnl_unlock(); |
210 | ||
d3245b28 | 211 | return rc < 0 ? rc : (ssize_t)count; |
e6fa2eb7 BH |
212 | } |
213 | ||
214 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
215 | set_phy_short_reach); | |
216 | ||
190dbcfd | 217 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 218 | { |
190dbcfd | 219 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
220 | int boot_stat; |
221 | ||
190dbcfd | 222 | for (;;) { |
68e7f45e BH |
223 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
224 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
225 | if (boot_stat >= 0) { |
226 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
227 | switch (boot_stat & | |
228 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
229 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
230 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
231 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
232 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
233 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
234 | PCS_BOOT_PROGRESS_LBN)): | |
235 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
236 | (PCS_BOOT_PROGRESS_INIT << | |
237 | PCS_BOOT_PROGRESS_LBN) | | |
238 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
239 | return -EINVAL; | |
240 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
241 | PCS_BOOT_PROGRESS_LBN) | | |
242 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
243 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
244 | 0 : -EIO; | |
245 | case ((PCS_BOOT_PROGRESS_JUMP << | |
246 | PCS_BOOT_PROGRESS_LBN) | | |
247 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
248 | case ((PCS_BOOT_PROGRESS_JUMP << | |
249 | PCS_BOOT_PROGRESS_LBN) | | |
250 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
251 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
252 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
253 | -EIO : 0; | |
254 | default: | |
255 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
256 | return -EIO; | |
257 | break; | |
258 | } | |
259 | } | |
260 | ||
261 | if (time_after_eq(jiffies, timeout)) | |
262 | return -ETIMEDOUT; | |
263 | ||
264 | msleep(50); | |
8ceee660 | 265 | } |
8ceee660 BH |
266 | } |
267 | ||
8ceee660 BH |
268 | static int tenxpress_init(struct efx_nic *efx) |
269 | { | |
e6fa2eb7 | 270 | int reg; |
8ceee660 | 271 | |
e6fa2eb7 BH |
272 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
273 | /* Enable 312.5 MHz clock */ | |
68e7f45e BH |
274 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
275 | 1 << CLK312_EN_LBN); | |
e6fa2eb7 BH |
276 | } else { |
277 | /* Enable 312.5 MHz clock and GMII */ | |
68e7f45e | 278 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
e6fa2eb7 BH |
279 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
280 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
281 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
282 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
283 | ||
68e7f45e BH |
284 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
285 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | |
286 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | |
287 | false); | |
e6fa2eb7 | 288 | } |
8ceee660 | 289 | |
8ceee660 | 290 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 | 291 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
68e7f45e BH |
292 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
293 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | |
294 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | |
dcf477b2 | 295 | SFX7101_PMA_PMD_LED_DEFAULT); |
e6fa2eb7 | 296 | } |
8ceee660 | 297 | |
190dbcfd | 298 | return 0; |
8ceee660 BH |
299 | } |
300 | ||
c1c4f453 BH |
301 | static int sfx7101_phy_probe(struct efx_nic *efx) |
302 | { | |
303 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | |
304 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
305 | efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS; | |
306 | return 0; | |
307 | } | |
308 | ||
309 | static int sft9001_phy_probe(struct efx_nic *efx) | |
310 | { | |
311 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | |
312 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
313 | efx->loopback_modes = (SFT9001_LOOPBACKS | FALCON_XMAC_LOOPBACKS | | |
314 | FALCON_GMAC_LOOPBACKS); | |
315 | return 0; | |
316 | } | |
317 | ||
8ceee660 BH |
318 | static int tenxpress_phy_init(struct efx_nic *efx) |
319 | { | |
320 | struct tenxpress_phy_data *phy_data; | |
321 | int rc = 0; | |
322 | ||
44838a44 | 323 | falcon_board(efx)->type->init_phy(efx); |
981fc1b4 | 324 | |
8ceee660 | 325 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); |
9b7bfc4c BH |
326 | if (!phy_data) |
327 | return -ENOMEM; | |
8ceee660 | 328 | efx->phy_data = phy_data; |
f8b87c17 | 329 | phy_data->phy_mode = efx->phy_mode; |
8ceee660 | 330 | |
e6fa2eb7 BH |
331 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
332 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
333 | int reg; | |
68e7f45e BH |
334 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
335 | PMA_PMD_XCONTROL_REG); | |
e6fa2eb7 | 336 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e BH |
337 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
338 | PMA_PMD_XCONTROL_REG, reg); | |
e6fa2eb7 BH |
339 | mdelay(200); |
340 | } | |
8ceee660 | 341 | |
68e7f45e | 342 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
e6fa2eb7 BH |
343 | if (rc < 0) |
344 | goto fail; | |
345 | ||
68e7f45e | 346 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
e6fa2eb7 BH |
347 | if (rc < 0) |
348 | goto fail; | |
349 | } | |
8ceee660 BH |
350 | |
351 | rc = tenxpress_init(efx); | |
352 | if (rc < 0) | |
353 | goto fail; | |
354 | ||
d3245b28 BH |
355 | /* Initialise advertising flags */ |
356 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | |
357 | ADVERTISED_10000baseT_Full); | |
358 | if (efx->phy_type != PHY_TYPE_SFX7101) | |
359 | efx->link_advertising |= (ADVERTISED_1000baseT_Full | | |
360 | ADVERTISED_100baseT_Full); | |
361 | efx_link_set_wanted_fc(efx, efx->wanted_fc); | |
362 | efx_mdio_an_reconfigure(efx); | |
c634263d | 363 | |
e6fa2eb7 BH |
364 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
365 | rc = device_create_file(&efx->pci_dev->dev, | |
366 | &dev_attr_phy_short_reach); | |
367 | if (rc) | |
368 | goto fail; | |
369 | } | |
370 | ||
8ceee660 BH |
371 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
372 | ||
e6fa2eb7 | 373 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
374 | falcon_reset_xaui(efx); |
375 | ||
376 | return 0; | |
377 | ||
378 | fail: | |
379 | kfree(efx->phy_data); | |
380 | efx->phy_data = NULL; | |
381 | return rc; | |
382 | } | |
383 | ||
e6fa2eb7 BH |
384 | /* Perform a "special software reset" on the PHY. The caller is |
385 | * responsible for saving and restoring the PHY hardware registers | |
386 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
387 | static int tenxpress_special_reset(struct efx_nic *efx) |
388 | { | |
389 | int rc, reg; | |
390 | ||
c8fcc49c BH |
391 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
392 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 | 393 | * requests to fail. */ |
55edc6e6 | 394 | falcon_stop_nic_stats(efx); |
3273c2e8 BH |
395 | |
396 | /* Initiate reset */ | |
68e7f45e | 397 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 | 398 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e | 399 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 400 | |
c8fcc49c | 401 | mdelay(200); |
3273c2e8 BH |
402 | |
403 | /* Wait for the blocks to come out of reset */ | |
68e7f45e | 404 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
3273c2e8 | 405 | if (rc < 0) |
1974cc20 | 406 | goto out; |
3273c2e8 BH |
407 | |
408 | /* Try and reconfigure the device */ | |
409 | rc = tenxpress_init(efx); | |
410 | if (rc < 0) | |
1974cc20 | 411 | goto out; |
3273c2e8 | 412 | |
e6fa2eb7 BH |
413 | /* Wait for the XGXS state machine to churn */ |
414 | mdelay(10); | |
1974cc20 | 415 | out: |
55edc6e6 | 416 | falcon_start_nic_stats(efx); |
c8fcc49c | 417 | return rc; |
3273c2e8 BH |
418 | } |
419 | ||
e6fa2eb7 | 420 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
421 | { |
422 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac | 423 | bool bad_lp; |
8ceee660 BH |
424 | int reg; |
425 | ||
04cc8cac BH |
426 | if (link_ok) { |
427 | bad_lp = false; | |
428 | } else { | |
429 | /* Check that AN has started but not completed. */ | |
68e7f45e BH |
430 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
431 | if (!(reg & MDIO_AN_STAT1_LPABLE)) | |
04cc8cac | 432 | return; /* LP status is unknown */ |
68e7f45e | 433 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
04cc8cac BH |
434 | if (bad_lp) |
435 | pd->bad_lp_tries++; | |
436 | } | |
437 | ||
8ceee660 | 438 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 439 | if (!pd->bad_lp_tries) |
8ceee660 BH |
440 | return; |
441 | ||
04cc8cac BH |
442 | /* Use the RX (red) LED as an error indicator once we've seen AN |
443 | * failure several times in a row, and also log a message. */ | |
444 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
68e7f45e BH |
445 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
446 | PMA_PMD_LED_OVERR_REG); | |
04cc8cac BH |
447 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
448 | if (!bad_lp) { | |
449 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
450 | } else { | |
451 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
452 | EFX_ERR(efx, "appears to be plugged into a port" | |
453 | " that is not 10GBASE-T capable. The PHY" | |
454 | " supports 10GBASE-T ONLY, so no link can" | |
455 | " be established\n"); | |
456 | } | |
68e7f45e BH |
457 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
458 | PMA_PMD_LED_OVERR_REG, reg); | |
04cc8cac | 459 | pd->bad_lp_tries = bad_lp; |
8ceee660 | 460 | } |
8ceee660 BH |
461 | } |
462 | ||
e6fa2eb7 | 463 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 464 | { |
68e7f45e BH |
465 | return efx_mdio_links_ok(efx, |
466 | MDIO_DEVS_PMAPMD | | |
467 | MDIO_DEVS_PCS | | |
468 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
469 | } |
470 | ||
471 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
472 | { | |
e6fa2eb7 BH |
473 | u32 reg; |
474 | ||
caa8d8bb | 475 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 476 | return false; |
caa8d8bb BH |
477 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
478 | return true; | |
e6fa2eb7 | 479 | else if (efx->loopback_mode) |
68e7f45e BH |
480 | return efx_mdio_links_ok(efx, |
481 | MDIO_DEVS_PMAPMD | | |
482 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
483 | |
484 | /* We must use the same definition of link state as LASI, | |
485 | * otherwise we can miss a link state transition | |
486 | */ | |
487 | if (ecmd->speed == 10000) { | |
68e7f45e BH |
488 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
489 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | |
e6fa2eb7 | 490 | } else { |
68e7f45e | 491 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
e6fa2eb7 BH |
492 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
493 | } | |
8ceee660 BH |
494 | } |
495 | ||
e6fa2eb7 | 496 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 | 497 | { |
68e7f45e BH |
498 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
499 | 1 << LOOPBACK_NEAR_LBN, | |
500 | efx->loopback_mode == LOOPBACK_PHYXS); | |
e6fa2eb7 | 501 | if (efx->phy_type != PHY_TYPE_SFX7101) |
68e7f45e BH |
502 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
503 | 1 << GPHY_LOOPBACK_NEAR_LBN, | |
504 | efx->loopback_mode == LOOPBACK_GPHY); | |
e6fa2eb7 BH |
505 | } |
506 | ||
507 | static void tenxpress_low_power(struct efx_nic *efx) | |
508 | { | |
e6fa2eb7 | 509 | if (efx->phy_type == PHY_TYPE_SFX7101) |
68e7f45e | 510 | efx_mdio_set_mmds_lpower( |
e6fa2eb7 BH |
511 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
512 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 513 | else |
68e7f45e BH |
514 | efx_mdio_set_flag( |
515 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | |
516 | 1 << PMA_PMD_EXT_LPOWER_LBN, | |
e6fa2eb7 | 517 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
3273c2e8 BH |
518 | } |
519 | ||
d3245b28 | 520 | static int tenxpress_phy_reconfigure(struct efx_nic *efx) |
8ceee660 | 521 | { |
3273c2e8 | 522 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
8b9dc8dd | 523 | bool phy_mode_change, loop_reset; |
3273c2e8 | 524 | |
e6fa2eb7 | 525 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 526 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 | 527 | return 0; |
f8b87c17 | 528 | } |
8ceee660 | 529 | |
e6fa2eb7 BH |
530 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && |
531 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
c1c4f453 | 532 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) || |
e6fa2eb7 BH |
533 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); |
534 | ||
8b9dc8dd | 535 | if (loop_reset || phy_mode_change) { |
d3245b28 | 536 | tenxpress_special_reset(efx); |
e6fa2eb7 | 537 | |
d3245b28 BH |
538 | /* Reset XAUI if we were in 10G, and are staying |
539 | * in 10G. If we're moving into and out of 10G | |
540 | * then xaui will be reset anyway */ | |
541 | if (EFX_IS10G(efx)) | |
542 | falcon_reset_xaui(efx); | |
3273c2e8 BH |
543 | } |
544 | ||
d3245b28 | 545 | tenxpress_low_power(efx); |
68e7f45e BH |
546 | efx_mdio_transmit_disable(efx); |
547 | efx_mdio_phy_reconfigure(efx); | |
e6fa2eb7 | 548 | tenxpress_ext_loopback(efx); |
d3245b28 | 549 | efx_mdio_an_reconfigure(efx); |
3273c2e8 | 550 | |
3273c2e8 | 551 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 552 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 BH |
553 | |
554 | return 0; | |
8ceee660 BH |
555 | } |
556 | ||
fdaa9aed SH |
557 | static void |
558 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd); | |
559 | ||
560 | /* Poll for link state changes */ | |
561 | static bool tenxpress_phy_poll(struct efx_nic *efx) | |
8ceee660 | 562 | { |
fdaa9aed | 563 | struct efx_link_state old_state = efx->link_state; |
8ceee660 | 564 | |
e6fa2eb7 | 565 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
fdaa9aed SH |
566 | efx->link_state.up = sfx7101_link_ok(efx); |
567 | efx->link_state.speed = 10000; | |
568 | efx->link_state.fd = true; | |
569 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
570 | ||
571 | sfx7101_check_bad_lp(efx, efx->link_state.up); | |
766ca0fa | 572 | } else { |
fdaa9aed | 573 | struct ethtool_cmd ecmd; |
8ceee660 | 574 | |
fdaa9aed SH |
575 | /* Check the LASI alarm first */ |
576 | if (efx->loopback_mode == LOOPBACK_NONE && | |
577 | !(efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT) & | |
578 | MDIO_PMA_LASI_LSALARM)) | |
579 | return false; | |
8ceee660 | 580 | |
fdaa9aed SH |
581 | tenxpress_get_settings(efx, &ecmd); |
582 | ||
583 | efx->link_state.up = sft9001_link_ok(efx, &ecmd); | |
584 | efx->link_state.speed = ecmd.speed; | |
585 | efx->link_state.fd = (ecmd.duplex == DUPLEX_FULL); | |
586 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
587 | } | |
588 | ||
589 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
8ceee660 BH |
590 | } |
591 | ||
592 | static void tenxpress_phy_fini(struct efx_nic *efx) | |
593 | { | |
594 | int reg; | |
595 | ||
2a7e637d | 596 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
597 | device_remove_file(&efx->pci_dev->dev, |
598 | &dev_attr_phy_short_reach); | |
2a7e637d BH |
599 | |
600 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
e6fa2eb7 BH |
601 | /* Power down the LNPGA */ |
602 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
68e7f45e | 603 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
e6fa2eb7 BH |
604 | |
605 | /* Waiting here ensures that the board fini, which can turn | |
606 | * off the power to the PHY, won't get run until the LNPGA | |
607 | * powerdown has been given long enough to complete. */ | |
608 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
609 | } | |
8ceee660 BH |
610 | |
611 | kfree(efx->phy_data); | |
612 | efx->phy_data = NULL; | |
613 | } | |
614 | ||
615 | ||
398468ed BH |
616 | /* Override the RX, TX and link LEDs */ |
617 | void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) | |
8ceee660 BH |
618 | { |
619 | int reg; | |
620 | ||
398468ed BH |
621 | switch (mode) { |
622 | case EFX_LED_OFF: | |
623 | reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) | | |
624 | (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | | |
625 | (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN); | |
626 | break; | |
627 | case EFX_LED_ON: | |
628 | reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) | | |
629 | (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) | | |
630 | (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN); | |
631 | break; | |
632 | default: | |
dcf477b2 BH |
633 | if (efx->phy_type == PHY_TYPE_SFX7101) |
634 | reg = SFX7101_PMA_PMD_LED_DEFAULT; | |
635 | else | |
636 | reg = SFT9001_PMA_PMD_LED_DEFAULT; | |
398468ed BH |
637 | break; |
638 | } | |
8ceee660 | 639 | |
68e7f45e | 640 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
8ceee660 BH |
641 | } |
642 | ||
307505e9 | 643 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
644 | "bist" |
645 | }; | |
646 | ||
c1c4f453 BH |
647 | static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index) |
648 | { | |
649 | if (index < ARRAY_SIZE(sfx7101_test_names)) | |
650 | return sfx7101_test_names[index]; | |
651 | return NULL; | |
652 | } | |
653 | ||
1796721a | 654 | static int |
307505e9 | 655 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 656 | { |
1796721a BH |
657 | int rc; |
658 | ||
659 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
660 | return 0; | |
661 | ||
8c8661e4 | 662 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
663 | rc = tenxpress_special_reset(efx); |
664 | results[0] = rc ? -1 : 1; | |
d3245b28 BH |
665 | |
666 | efx_mdio_an_reconfigure(efx); | |
667 | ||
1796721a | 668 | return rc; |
8c8661e4 BH |
669 | } |
670 | ||
307505e9 BH |
671 | static const char *const sft9001_test_names[] = { |
672 | "bist", | |
673 | "cable.pairA.status", | |
674 | "cable.pairB.status", | |
675 | "cable.pairC.status", | |
676 | "cable.pairD.status", | |
677 | "cable.pairA.length", | |
678 | "cable.pairB.length", | |
679 | "cable.pairC.length", | |
680 | "cable.pairD.length", | |
681 | }; | |
682 | ||
c1c4f453 BH |
683 | static const char *sft9001_test_name(struct efx_nic *efx, unsigned int index) |
684 | { | |
685 | if (index < ARRAY_SIZE(sft9001_test_names)) | |
686 | return sft9001_test_names[index]; | |
687 | return NULL; | |
688 | } | |
689 | ||
307505e9 BH |
690 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
691 | { | |
22ef02c2 | 692 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 693 | |
307505e9 BH |
694 | /* Initialise cable diagnostic results to unknown failure */ |
695 | for (i = 1; i < 9; ++i) | |
696 | results[i] = -1; | |
697 | ||
698 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
699 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
700 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
701 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
702 | if (flags & ETH_TEST_FL_OFFLINE) { | |
703 | /* Break the link in order to run full diagnostics. We | |
704 | * must reset the PHY to resume normal service. */ | |
705 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
706 | } | |
68e7f45e BH |
707 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
708 | ctrl_reg); | |
307505e9 | 709 | i = 0; |
68e7f45e | 710 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
307505e9 BH |
711 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
712 | if (++i == 50) { | |
713 | rc = -ETIMEDOUT; | |
22ef02c2 | 714 | goto out; |
307505e9 BH |
715 | } |
716 | msleep(100); | |
717 | } | |
68e7f45e | 718 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
307505e9 BH |
719 | for (i = 0; i < 4; i++) { |
720 | int pair_res = | |
721 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
722 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
68e7f45e BH |
723 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
724 | PMA_PMD_CDIAG_LEN_REG + i); | |
307505e9 BH |
725 | if (pair_res == CDIAG_RES_OK) |
726 | results[1 + i] = 1; | |
727 | else if (pair_res == CDIAG_RES_INVALID) | |
728 | results[1 + i] = -1; | |
729 | else | |
730 | results[1 + i] = -pair_res; | |
731 | if (pair_res != CDIAG_RES_INVALID && | |
732 | pair_res != CDIAG_RES_OPEN && | |
733 | len_reg != 0xffff) | |
734 | results[5 + i] = len_reg; | |
735 | } | |
736 | ||
22ef02c2 BH |
737 | out: |
738 | if (flags & ETH_TEST_FL_OFFLINE) { | |
739 | /* Reset, running the BIST and then resuming normal service. */ | |
740 | rc2 = tenxpress_special_reset(efx); | |
741 | results[0] = rc2 ? -1 : 1; | |
742 | if (!rc) | |
743 | rc = rc2; | |
744 | ||
d3245b28 | 745 | efx_mdio_an_reconfigure(efx); |
22ef02c2 | 746 | } |
307505e9 BH |
747 | |
748 | return rc; | |
749 | } | |
750 | ||
af4ad9bc BH |
751 | static void |
752 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 753 | { |
af4ad9bc | 754 | u32 adv = 0, lpa = 0; |
04cc8cac BH |
755 | int reg; |
756 | ||
e6fa2eb7 | 757 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
68e7f45e | 758 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
af4ad9bc BH |
759 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
760 | adv |= ADVERTISED_1000baseT_Full; | |
68e7f45e | 761 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
af4ad9bc | 762 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
e6fa2eb7 | 763 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 764 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
765 | lpa |= ADVERTISED_1000baseT_Full; |
766 | } | |
68e7f45e BH |
767 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
768 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | |
af4ad9bc | 769 | adv |= ADVERTISED_10000baseT_Full; |
68e7f45e BH |
770 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
771 | if (reg & MDIO_AN_10GBT_STAT_LP10G) | |
04cc8cac | 772 | lpa |= ADVERTISED_10000baseT_Full; |
04cc8cac | 773 | |
68e7f45e | 774 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
e6fa2eb7 | 775 | |
e762cd70 | 776 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
af4ad9bc BH |
777 | ecmd->supported |= (SUPPORTED_100baseT_Full | |
778 | SUPPORTED_1000baseT_Full); | |
e762cd70 BH |
779 | if (ecmd->speed != SPEED_10000) { |
780 | ecmd->eth_tp_mdix = | |
781 | (efx_mdio_read(efx, MDIO_MMD_PMAPMD, | |
782 | PMA_PMD_XSTATUS_REG) & | |
783 | (1 << PMA_PMD_XSTAT_MDIX_LBN)) | |
784 | ? ETH_TP_MDI_X : ETH_TP_MDI; | |
785 | } | |
786 | } | |
8b9dc8dd SH |
787 | |
788 | /* In loopback, the PHY automatically brings up the correct interface, | |
789 | * but doesn't advertise the correct speed. So override it */ | |
790 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
791 | ecmd->speed = SPEED_1000; | |
c1c4f453 | 792 | else if (LOOPBACK_EXTERNAL(efx)) |
8b9dc8dd | 793 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
794 | } |
795 | ||
af4ad9bc | 796 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 797 | { |
af4ad9bc BH |
798 | if (!ecmd->autoneg) |
799 | return -EINVAL; | |
e6fa2eb7 | 800 | |
68e7f45e | 801 | return efx_mdio_set_settings(efx, ecmd); |
e6fa2eb7 BH |
802 | } |
803 | ||
af4ad9bc | 804 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 805 | { |
68e7f45e BH |
806 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
807 | MDIO_AN_10GBT_CTRL_ADV10G, | |
808 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
809 | } |
810 | ||
af4ad9bc | 811 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 812 | { |
68e7f45e BH |
813 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
814 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
815 | advertising & ADVERTISED_1000baseT_Full); | |
816 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | |
817 | MDIO_AN_10GBT_CTRL_ADV10G, | |
818 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
819 | } |
820 | ||
821 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
c1c4f453 | 822 | .probe = sfx7101_phy_probe, |
8ceee660 BH |
823 | .init = tenxpress_phy_init, |
824 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 825 | .poll = tenxpress_phy_poll, |
8ceee660 | 826 | .fini = tenxpress_phy_fini, |
af4ad9bc BH |
827 | .get_settings = tenxpress_get_settings, |
828 | .set_settings = tenxpress_set_settings, | |
829 | .set_npage_adv = sfx7101_set_npage_adv, | |
c1c4f453 | 830 | .test_name = sfx7101_test_name, |
307505e9 | 831 | .run_tests = sfx7101_run_tests, |
e6fa2eb7 BH |
832 | }; |
833 | ||
834 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
c1c4f453 | 835 | .probe = sft9001_phy_probe, |
e6fa2eb7 BH |
836 | .init = tenxpress_phy_init, |
837 | .reconfigure = tenxpress_phy_reconfigure, | |
838 | .poll = tenxpress_phy_poll, | |
839 | .fini = tenxpress_phy_fini, | |
af4ad9bc BH |
840 | .get_settings = tenxpress_get_settings, |
841 | .set_settings = tenxpress_set_settings, | |
842 | .set_npage_adv = sft9001_set_npage_adv, | |
c1c4f453 | 843 | .test_name = sft9001_test_name, |
307505e9 | 844 | .run_tests = sft9001_run_tests, |
8ceee660 | 845 | }; |