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net: sh_eth: remove the SH_TSU_ADDR
[deliverable/linux.git] / drivers / net / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
b0ca2a21 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
380af9e3 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2
NI		 23#include <linux/init.h>
24#include <linux/dma-mapping.h>
25#include <linux/etherdevice.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mdio-bitbang.h>
29#include <linux/netdevice.h>
30#include <linux/phy.h>
31#include <linux/cache.h>
32#include <linux/io.h>
bcd5149d 33#include <linux/pm_runtime.h>
5a0e3ad6 34#include <linux/slab.h>
dc19e4e5 35#include <linux/ethtool.h>
f568a926 36#include <asm/cacheflush.h>
86a74ff2
NI		 37
38#include "sh_eth.h"
39
dc19e4e5
NI		 40#define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
380af9e3 46/* There is CPU dependent code */
65ac8851
YS		 47#if defined(CONFIG_CPU_SUBTYPE_SH7724)
48#define SH_ETH_RESET_DEFAULT 1
49static void sh_eth_set_duplex(struct net_device *ndev)
50{
51 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 52
53 if (mdp->duplex) /* Full */
4a55530f 54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 55 else /* Half */
4a55530f 56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 57}
58
59static void sh_eth_set_rate(struct net_device *ndev)
60{
61 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 62
63 switch (mdp->speed) {
64 case 10: /* 10BASE */
4a55530f 65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 66 break;
67 case 100:/* 100BASE */
4a55530f 68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 69 break;
70 default:
71 break;
72 }
73}
74
75/* SH7724 */
76static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
79
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
83
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88
89 .apr = 1,
90 .mpr = 1,
91 .tpauser = 1,
92 .hw_swap = 1,
503914cf
MD		 93 .rpadir = 1,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 95};
f29a3d04
YS		 96#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97#define SH_ETH_RESET_DEFAULT 1
98static void sh_eth_set_duplex(struct net_device *ndev)
99{
100 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 101
102 if (mdp->duplex) /* Full */
4a55530f 103 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
f29a3d04 104 else /* Half */
4a55530f 105 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
f29a3d04
YS		 106}
107
108static void sh_eth_set_rate(struct net_device *ndev)
109{
110 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 111
112 switch (mdp->speed) {
113 case 10: /* 10BASE */
4a55530f 114 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 115 break;
116 case 100:/* 100BASE */
4a55530f 117 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 118 break;
119 default:
120 break;
121 }
122}
123
124/* SH7757 */
125static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
126 .set_duplex = sh_eth_set_duplex,
127 .set_rate = sh_eth_set_rate,
128
129 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
130 .rmcr_value = 0x00000001,
131
132 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
133 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
134 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
135 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
136
137 .apr = 1,
138 .mpr = 1,
139 .tpauser = 1,
140 .hw_swap = 1,
141 .no_ade = 1,
142};
65ac8851
YS		 143
144#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3
YS		 145#define SH_ETH_HAS_TSU 1
146static void sh_eth_chip_reset(struct net_device *ndev)
147{
4986b996
YS		 148 struct sh_eth_private *mdp = netdev_priv(ndev);
149
380af9e3 150 /* reset device */
4986b996 151 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 152 mdelay(1);
153}
154
155static void sh_eth_reset(struct net_device *ndev)
156{
380af9e3
YS		 157 int cnt = 100;
158
4a55530f
YS		 159 sh_eth_write(ndev, EDSR_ENALL, EDSR);
160 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST, EDMR);
380af9e3 161 while (cnt > 0) {
4a55530f 162 if (!(sh_eth_read(ndev, EDMR) & 0x3))
380af9e3
YS		 163 break;
164 mdelay(1);
165 cnt--;
166 }
890c8c18 167 if (cnt == 0)
380af9e3
YS		 168 printk(KERN_ERR "Device reset fail\n");
169
170 /* Table Init */
4a55530f
YS		 171 sh_eth_write(ndev, 0x0, TDLAR);
172 sh_eth_write(ndev, 0x0, TDFAR);
173 sh_eth_write(ndev, 0x0, TDFXR);
174 sh_eth_write(ndev, 0x0, TDFFR);
175 sh_eth_write(ndev, 0x0, RDLAR);
176 sh_eth_write(ndev, 0x0, RDFAR);
177 sh_eth_write(ndev, 0x0, RDFXR);
178 sh_eth_write(ndev, 0x0, RDFFR);
380af9e3
YS		 179}
180
181static void sh_eth_set_duplex(struct net_device *ndev)
182{
183 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 184
185 if (mdp->duplex) /* Full */
4a55530f 186 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
380af9e3 187 else /* Half */
4a55530f 188 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
380af9e3
YS		 189}
190
191static void sh_eth_set_rate(struct net_device *ndev)
192{
193 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 194
195 switch (mdp->speed) {
196 case 10: /* 10BASE */
4a55530f 197 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 198 break;
199 case 100:/* 100BASE */
4a55530f 200 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 201 break;
202 case 1000: /* 1000BASE */
4a55530f 203 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 204 break;
205 default:
206 break;
207 }
208}
209
210/* sh7763 */
211static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
212 .chip_reset = sh_eth_chip_reset,
213 .set_duplex = sh_eth_set_duplex,
214 .set_rate = sh_eth_set_rate,
215
216 .ecsr_value = ECSR_ICD | ECSR_MPD,
217 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
218 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
219
220 .tx_check = EESR_TC1 | EESR_FTC,
221 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
222 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
223 EESR_ECI,
224 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
225 EESR_TFE,
226
227 .apr = 1,
228 .mpr = 1,
229 .tpauser = 1,
230 .bculr = 1,
231 .hw_swap = 1,
380af9e3
YS		 232 .no_trimd = 1,
233 .no_ade = 1,
4986b996 234 .tsu = 1,
380af9e3
YS		 235};
236
237#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
238#define SH_ETH_RESET_DEFAULT 1
239static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
240 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
241
242 .apr = 1,
243 .mpr = 1,
244 .tpauser = 1,
245 .hw_swap = 1,
246};
247#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
248#define SH_ETH_RESET_DEFAULT 1
249#define SH_ETH_HAS_TSU 1
250static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
251 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 252 .tsu = 1,
380af9e3
YS		 253};
254#endif
255
256static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
257{
258 if (!cd->ecsr_value)
259 cd->ecsr_value = DEFAULT_ECSR_INIT;
260
261 if (!cd->ecsipr_value)
262 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
263
264 if (!cd->fcftr_value)
265 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
266 DEFAULT_FIFO_F_D_RFD;
267
268 if (!cd->fdr_value)
269 cd->fdr_value = DEFAULT_FDR_INIT;
270
271 if (!cd->rmcr_value)
272 cd->rmcr_value = DEFAULT_RMCR_VALUE;
273
274 if (!cd->tx_check)
275 cd->tx_check = DEFAULT_TX_CHECK;
276
277 if (!cd->eesr_err_check)
278 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
279
280 if (!cd->tx_error_check)
281 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
282}
283
284#if defined(SH_ETH_RESET_DEFAULT)
285/* Chip Reset */
286static void sh_eth_reset(struct net_device *ndev)
287{
4a55530f 288 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST, EDMR);
380af9e3 289 mdelay(3);
4a55530f 290 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST, EDMR);
380af9e3
YS		 291}
292#endif
293
294#if defined(CONFIG_CPU_SH4)
295static void sh_eth_set_receive_align(struct sk_buff *skb)
296{
297 int reserve;
298
299 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
300 if (reserve)
301 skb_reserve(skb, reserve);
302}
303#else
304static void sh_eth_set_receive_align(struct sk_buff *skb)
305{
306 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
307}
308#endif
309
310
71557a37
YS		 311/* CPU <-> EDMAC endian convert */
312static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
313{
314 switch (mdp->edmac_endian) {
315 case EDMAC_LITTLE_ENDIAN:
316 return cpu_to_le32(x);
317 case EDMAC_BIG_ENDIAN:
318 return cpu_to_be32(x);
319 }
320 return x;
321}
322
323static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
324{
325 switch (mdp->edmac_endian) {
326 case EDMAC_LITTLE_ENDIAN:
327 return le32_to_cpu(x);
328 case EDMAC_BIG_ENDIAN:
329 return be32_to_cpu(x);
330 }
331 return x;
332}
333
86a74ff2
NI		 334/*
335 * Program the hardware MAC address from dev->dev_addr.
336 */
337static void update_mac_address(struct net_device *ndev)
338{
4a55530f
YS		 339 sh_eth_write(ndev,
340 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
341 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
342 sh_eth_write(ndev,
343 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 344}
345
346/*
347 * Get MAC address from SuperH MAC address register
348 *
349 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
350 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
351 * When you want use this device, you must set MAC address in bootloader.
352 *
353 */
748031f9 354static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 355{
748031f9
MD		 356 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
357 memcpy(ndev->dev_addr, mac, 6);
358 } else {
4a55530f
YS		 359 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
360 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
361 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
362 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
363 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
364 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 365 }
86a74ff2
NI		 366}
367
368struct bb_info {
369 struct mdiobb_ctrl ctrl;
370 u32 addr;
371 u32 mmd_msk;/* MMD */
372 u32 mdo_msk;
373 u32 mdi_msk;
374 u32 mdc_msk;
375};
376
377/* PHY bit set */
378static void bb_set(u32 addr, u32 msk)
379{
900fcf09 380 writel(readl(addr) | msk, addr);
86a74ff2
NI		 381}
382
383/* PHY bit clear */
384static void bb_clr(u32 addr, u32 msk)
385{
900fcf09 386 writel((readl(addr) & ~msk), addr);
86a74ff2
NI		 387}
388
389/* PHY bit read */
390static int bb_read(u32 addr, u32 msk)
391{
900fcf09 392 return (readl(addr) & msk) != 0;
86a74ff2
NI		 393}
394
395/* Data I/O pin control */
396static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
397{
398 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
399 if (bit)
400 bb_set(bitbang->addr, bitbang->mmd_msk);
401 else
402 bb_clr(bitbang->addr, bitbang->mmd_msk);
403}
404
405/* Set bit data*/
406static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
407{
408 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
409
410 if (bit)
411 bb_set(bitbang->addr, bitbang->mdo_msk);
412 else
413 bb_clr(bitbang->addr, bitbang->mdo_msk);
414}
415
416/* Get bit data*/
417static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
418{
419 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
420 return bb_read(bitbang->addr, bitbang->mdi_msk);
421}
422
423/* MDC pin control */
424static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
425{
426 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
427
428 if (bit)
429 bb_set(bitbang->addr, bitbang->mdc_msk);
430 else
431 bb_clr(bitbang->addr, bitbang->mdc_msk);
432}
433
434/* mdio bus control struct */
435static struct mdiobb_ops bb_ops = {
436 .owner = THIS_MODULE,
437 .set_mdc = sh_mdc_ctrl,
438 .set_mdio_dir = sh_mmd_ctrl,
439 .set_mdio_data = sh_set_mdio,
440 .get_mdio_data = sh_get_mdio,
441};
442
86a74ff2
NI		 443/* free skb and descriptor buffer */
444static void sh_eth_ring_free(struct net_device *ndev)
445{
446 struct sh_eth_private *mdp = netdev_priv(ndev);
447 int i;
448
449 /* Free Rx skb ringbuffer */
450 if (mdp->rx_skbuff) {
451 for (i = 0; i < RX_RING_SIZE; i++) {
452 if (mdp->rx_skbuff[i])
453 dev_kfree_skb(mdp->rx_skbuff[i]);
454 }
455 }
456 kfree(mdp->rx_skbuff);
457
458 /* Free Tx skb ringbuffer */
459 if (mdp->tx_skbuff) {
460 for (i = 0; i < TX_RING_SIZE; i++) {
461 if (mdp->tx_skbuff[i])
462 dev_kfree_skb(mdp->tx_skbuff[i]);
463 }
464 }
465 kfree(mdp->tx_skbuff);
466}
467
468/* format skb and descriptor buffer */
469static void sh_eth_ring_format(struct net_device *ndev)
470{
471 struct sh_eth_private *mdp = netdev_priv(ndev);
472 int i;
473 struct sk_buff *skb;
474 struct sh_eth_rxdesc *rxdesc = NULL;
475 struct sh_eth_txdesc *txdesc = NULL;
476 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
477 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
478
479 mdp->cur_rx = mdp->cur_tx = 0;
480 mdp->dirty_rx = mdp->dirty_tx = 0;
481
482 memset(mdp->rx_ring, 0, rx_ringsize);
483
484 /* build Rx ring buffer */
485 for (i = 0; i < RX_RING_SIZE; i++) {
486 /* skb */
487 mdp->rx_skbuff[i] = NULL;
488 skb = dev_alloc_skb(mdp->rx_buf_sz);
489 mdp->rx_skbuff[i] = skb;
490 if (skb == NULL)
491 break;
e88aae7b
YS		 492 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
493 DMA_FROM_DEVICE);
b0ca2a21 494 skb->dev = ndev; /* Mark as being used by this device. */
380af9e3
YS		 495 sh_eth_set_receive_align(skb);
496
86a74ff2
NI		 497 /* RX descriptor */
498 rxdesc = &mdp->rx_ring[i];
0029d64a 499 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 500 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 501
502 /* The size of the buffer is 16 byte boundary. */
0029d64a 503 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 504 /* Rx descriptor address set */
505 if (i == 0) {
4a55530f 506 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
b0ca2a21 507#if defined(CONFIG_CPU_SUBTYPE_SH7763)
4a55530f 508 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21
NI		 509#endif
510 }
86a74ff2
NI		 511 }
512
513 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
514
515 /* Mark the last entry as wrapping the ring. */
71557a37 516 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 517
518 memset(mdp->tx_ring, 0, tx_ringsize);
519
520 /* build Tx ring buffer */
521 for (i = 0; i < TX_RING_SIZE; i++) {
522 mdp->tx_skbuff[i] = NULL;
523 txdesc = &mdp->tx_ring[i];
71557a37 524 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 525 txdesc->buffer_length = 0;
b0ca2a21 526 if (i == 0) {
71557a37 527 /* Tx descriptor address set */
4a55530f 528 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
b0ca2a21 529#if defined(CONFIG_CPU_SUBTYPE_SH7763)
4a55530f 530 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21
NI		 531#endif
532 }
86a74ff2
NI		 533 }
534
71557a37 535 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 536}
537
538/* Get skb and descriptor buffer */
539static int sh_eth_ring_init(struct net_device *ndev)
540{
541 struct sh_eth_private *mdp = netdev_priv(ndev);
542 int rx_ringsize, tx_ringsize, ret = 0;
543
544 /*
545 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
546 * card needs room to do 8 byte alignment, +2 so we can reserve
547 * the first 2 bytes, and +16 gets room for the status word from the
548 * card.
549 */
550 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
551 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 552 if (mdp->cd->rpadir)
553 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 554
555 /* Allocate RX and TX skb rings */
556 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
557 GFP_KERNEL);
558 if (!mdp->rx_skbuff) {
380af9e3 559 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
86a74ff2
NI		 560 ret = -ENOMEM;
561 return ret;
562 }
563
564 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
565 GFP_KERNEL);
566 if (!mdp->tx_skbuff) {
380af9e3 567 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
86a74ff2
NI		 568 ret = -ENOMEM;
569 goto skb_ring_free;
570 }
571
572 /* Allocate all Rx descriptors. */
573 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
574 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
575 GFP_KERNEL);
576
577 if (!mdp->rx_ring) {
380af9e3
YS		 578 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
579 rx_ringsize);
86a74ff2
NI		 580 ret = -ENOMEM;
581 goto desc_ring_free;
582 }
583
584 mdp->dirty_rx = 0;
585
586 /* Allocate all Tx descriptors. */
587 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
588 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
589 GFP_KERNEL);
590 if (!mdp->tx_ring) {
380af9e3
YS		 591 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
592 tx_ringsize);
86a74ff2
NI		 593 ret = -ENOMEM;
594 goto desc_ring_free;
595 }
596 return ret;
597
598desc_ring_free:
599 /* free DMA buffer */
600 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
601
602skb_ring_free:
603 /* Free Rx and Tx skb ring buffer */
604 sh_eth_ring_free(ndev);
605
606 return ret;
607}
608
609static int sh_eth_dev_init(struct net_device *ndev)
610{
611 int ret = 0;
612 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 613 u_int32_t rx_int_var, tx_int_var;
614 u32 val;
615
616 /* Soft Reset */
617 sh_eth_reset(ndev);
618
b0ca2a21
NI		 619 /* Descriptor format */
620 sh_eth_ring_format(ndev);
380af9e3 621 if (mdp->cd->rpadir)
4a55530f 622 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 623
624 /* all sh_eth int mask */
4a55530f 625 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 626
380af9e3
YS		 627#if defined(__LITTLE_ENDIAN__)
628 if (mdp->cd->hw_swap)
4a55530f 629 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 630 else
b0ca2a21 631#endif
4a55530f 632 sh_eth_write(ndev, 0, EDMR);
86a74ff2 633
b0ca2a21 634 /* FIFO size set */
4a55530f
YS		 635 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
636 sh_eth_write(ndev, 0, TFTR);
86a74ff2 637
b0ca2a21 638 /* Frame recv control */
4a55530f 639 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2
NI		 640
641 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
642 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
4a55530f 643 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
86a74ff2 644
380af9e3 645 if (mdp->cd->bculr)
4a55530f 646 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 647
4a55530f 648 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 649
380af9e3 650 if (!mdp->cd->no_trimd)
4a55530f 651 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 652
b0ca2a21 653 /* Recv frame limit set register */
4a55530f 654 sh_eth_write(ndev, RFLR_VALUE, RFLR);
86a74ff2 655
4a55530f
YS		 656 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
657 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 658
659 /* PAUSE Prohibition */
4a55530f 660 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 661 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
662
4a55530f 663 sh_eth_write(ndev, val, ECMR);
b0ca2a21 664
380af9e3
YS		 665 if (mdp->cd->set_rate)
666 mdp->cd->set_rate(ndev);
667
b0ca2a21 668 /* E-MAC Status Register clear */
4a55530f 669 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 670
671 /* E-MAC Interrupt Enable register */
4a55530f 672 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 673
674 /* Set MAC address */
675 update_mac_address(ndev);
676
677 /* mask reset */
380af9e3 678 if (mdp->cd->apr)
4a55530f 679 sh_eth_write(ndev, APR_AP, APR);
380af9e3 680 if (mdp->cd->mpr)
4a55530f 681 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 682 if (mdp->cd->tpauser)
4a55530f 683 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 684
86a74ff2 685 /* Setting the Rx mode will start the Rx process. */
4a55530f 686 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 687
688 netif_start_queue(ndev);
689
690 return ret;
691}
692
693/* free Tx skb function */
694static int sh_eth_txfree(struct net_device *ndev)
695{
696 struct sh_eth_private *mdp = netdev_priv(ndev);
697 struct sh_eth_txdesc *txdesc;
698 int freeNum = 0;
699 int entry = 0;
700
701 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
702 entry = mdp->dirty_tx % TX_RING_SIZE;
703 txdesc = &mdp->tx_ring[entry];
71557a37 704 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 705 break;
706 /* Free the original skb. */
707 if (mdp->tx_skbuff[entry]) {
708 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
709 mdp->tx_skbuff[entry] = NULL;
710 freeNum++;
711 }
71557a37 712 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 713 if (entry >= TX_RING_SIZE - 1)
71557a37 714 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 715
716 mdp->stats.tx_packets++;
717 mdp->stats.tx_bytes += txdesc->buffer_length;
718 }
719 return freeNum;
720}
721
722/* Packet receive function */
723static int sh_eth_rx(struct net_device *ndev)
724{
725 struct sh_eth_private *mdp = netdev_priv(ndev);
726 struct sh_eth_rxdesc *rxdesc;
727
728 int entry = mdp->cur_rx % RX_RING_SIZE;
729 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
730 struct sk_buff *skb;
731 u16 pkt_len = 0;
380af9e3 732 u32 desc_status;
86a74ff2
NI		 733
734 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 735 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
736 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 737 pkt_len = rxdesc->frame_length;
738
739 if (--boguscnt < 0)
740 break;
741
742 if (!(desc_status & RDFEND))
743 mdp->stats.rx_length_errors++;
744
745 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
746 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
747 mdp->stats.rx_errors++;
748 if (desc_status & RD_RFS1)
749 mdp->stats.rx_crc_errors++;
750 if (desc_status & RD_RFS2)
751 mdp->stats.rx_frame_errors++;
752 if (desc_status & RD_RFS3)
753 mdp->stats.rx_length_errors++;
754 if (desc_status & RD_RFS4)
755 mdp->stats.rx_length_errors++;
756 if (desc_status & RD_RFS6)
757 mdp->stats.rx_missed_errors++;
758 if (desc_status & RD_RFS10)
759 mdp->stats.rx_over_errors++;
760 } else {
380af9e3
YS		 761 if (!mdp->cd->hw_swap)
762 sh_eth_soft_swap(
763 phys_to_virt(ALIGN(rxdesc->addr, 4)),
764 pkt_len + 2);
86a74ff2
NI		 765 skb = mdp->rx_skbuff[entry];
766 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 767 if (mdp->cd->rpadir)
768 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 769 skb_put(skb, pkt_len);
770 skb->protocol = eth_type_trans(skb, ndev);
771 netif_rx(skb);
86a74ff2
NI		 772 mdp->stats.rx_packets++;
773 mdp->stats.rx_bytes += pkt_len;
774 }
71557a37 775 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
86a74ff2 776 entry = (++mdp->cur_rx) % RX_RING_SIZE;
862df497 777 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 778 }
779
780 /* Refill the Rx ring buffers. */
781 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
782 entry = mdp->dirty_rx % RX_RING_SIZE;
783 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 784 /* The size of the buffer is 16 byte boundary. */
0029d64a 785 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 786
86a74ff2
NI		 787 if (mdp->rx_skbuff[entry] == NULL) {
788 skb = dev_alloc_skb(mdp->rx_buf_sz);
789 mdp->rx_skbuff[entry] = skb;
790 if (skb == NULL)
791 break; /* Better luck next round. */
e88aae7b
YS		 792 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
793 DMA_FROM_DEVICE);
86a74ff2 794 skb->dev = ndev;
380af9e3
YS		 795 sh_eth_set_receive_align(skb);
796
bc8acf2c 797 skb_checksum_none_assert(skb);
0029d64a 798 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 799 }
86a74ff2
NI		 800 if (entry >= RX_RING_SIZE - 1)
801 rxdesc->status |=
71557a37 802 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 803 else
804 rxdesc->status |=
71557a37 805 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 806 }
807
808 /* Restart Rx engine if stopped. */
809 /* If we don't need to check status, don't. -KDU */
4a55530f
YS		 810 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
811 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 812
813 return 0;
814}
815
4a55530f 816static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 817{
818 /* disable tx and rx */
4a55530f
YS		 819 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
820 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 821}
822
4a55530f 823static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 824{
825 /* enable tx and rx */
4a55530f
YS		 826 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
827 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 828}
829
86a74ff2
NI		 830/* error control function */
831static void sh_eth_error(struct net_device *ndev, int intr_status)
832{
833 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 834 u32 felic_stat;
380af9e3
YS		 835 u32 link_stat;
836 u32 mask;
86a74ff2
NI		 837
838 if (intr_status & EESR_ECI) {
4a55530f
YS		 839 felic_stat = sh_eth_read(ndev, ECSR);
840 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2
NI		 841 if (felic_stat & ECSR_ICD)
842 mdp->stats.tx_carrier_errors++;
843 if (felic_stat & ECSR_LCHNG) {
844 /* Link Changed */
4923576b 845 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 846 if (mdp->link == PHY_DOWN)
847 link_stat = 0;
848 else
849 link_stat = PHY_ST_LINK;
850 } else {
4a55530f 851 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 852 if (mdp->ether_link_active_low)
853 link_stat = ~link_stat;
380af9e3 854 }
dc19e4e5 855 if (!(link_stat & PHY_ST_LINK))
4a55530f 856 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 857 else {
86a74ff2 858 /* Link Up */
4a55530f
YS		 859 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
860 ~DMAC_M_ECI, EESIPR);
86a74ff2 861 /*clear int */
4a55530f
YS		 862 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
863 ECSR);
864 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
865 DMAC_M_ECI, EESIPR);
86a74ff2 866 /* enable tx and rx */
4a55530f 867 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 868 }
869 }
870 }
871
872 if (intr_status & EESR_TWB) {
873 /* Write buck end. unused write back interrupt */
874 if (intr_status & EESR_TABT) /* Transmit Abort int */
875 mdp->stats.tx_aborted_errors++;
dc19e4e5
NI		 876 if (netif_msg_tx_err(mdp))
877 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 878 }
879
880 if (intr_status & EESR_RABT) {
881 /* Receive Abort int */
882 if (intr_status & EESR_RFRMER) {
883 /* Receive Frame Overflow int */
884 mdp->stats.rx_frame_errors++;
dc19e4e5
NI		 885 if (netif_msg_rx_err(mdp))
886 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 887 }
888 }
380af9e3 889
dc19e4e5
NI		 890 if (intr_status & EESR_TDE) {
891 /* Transmit Descriptor Empty int */
892 mdp->stats.tx_fifo_errors++;
893 if (netif_msg_tx_err(mdp))
894 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
895 }
896
897 if (intr_status & EESR_TFE) {
898 /* FIFO under flow */
899 mdp->stats.tx_fifo_errors++;
900 if (netif_msg_tx_err(mdp))
901 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 902 }
903
904 if (intr_status & EESR_RDE) {
905 /* Receive Descriptor Empty int */
906 mdp->stats.rx_over_errors++;
907
4a55530f
YS		 908 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
909 sh_eth_write(ndev, EDRRR_R, EDRRR);
dc19e4e5
NI		 910 if (netif_msg_rx_err(mdp))
911 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 912 }
dc19e4e5 913
86a74ff2
NI		 914 if (intr_status & EESR_RFE) {
915 /* Receive FIFO Overflow int */
916 mdp->stats.rx_fifo_errors++;
dc19e4e5
NI		 917 if (netif_msg_rx_err(mdp))
918 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
919 }
920
921 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
922 /* Address Error */
923 mdp->stats.tx_fifo_errors++;
924 if (netif_msg_tx_err(mdp))
925 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 926 }
380af9e3
YS		 927
928 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
929 if (mdp->cd->no_ade)
930 mask &= ~EESR_ADE;
931 if (intr_status & mask) {
86a74ff2 932 /* Tx error */
4a55530f 933 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 934 /* dmesg */
380af9e3
YS		 935 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
936 intr_status, mdp->cur_tx);
937 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 938 mdp->dirty_tx, (u32) ndev->state, edtrr);
939 /* dirty buffer free */
940 sh_eth_txfree(ndev);
941
942 /* SH7712 BUG */
943 if (edtrr ^ EDTRR_TRNS) {
944 /* tx dma start */
4a55530f 945 sh_eth_write(ndev, EDTRR_TRNS, EDTRR);
86a74ff2
NI		 946 }
947 /* wakeup */
948 netif_wake_queue(ndev);
949 }
950}
951
952static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
953{
954 struct net_device *ndev = netdev;
955 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 956 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 957 irqreturn_t ret = IRQ_NONE;
4a55530f 958 u32 intr_status = 0;
86a74ff2 959
86a74ff2
NI		 960 spin_lock(&mdp->lock);
961
b0ca2a21 962 /* Get interrpt stat */
4a55530f 963 intr_status = sh_eth_read(ndev, EESR);
86a74ff2 964 /* Clear interrupt */
0e0fde3c
NI		 965 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
966 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 967 cd->tx_check | cd->eesr_err_check)) {
4a55530f 968 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 969 ret = IRQ_HANDLED;
970 } else
971 goto other_irq;
86a74ff2 972
b0ca2a21
NI		 973 if (intr_status & (EESR_FRC | /* Frame recv*/
974 EESR_RMAF | /* Multi cast address recv*/
975 EESR_RRF | /* Bit frame recv */
976 EESR_RTLF | /* Long frame recv*/
977 EESR_RTSF | /* short frame recv */
978 EESR_PRE | /* PHY-LSI recv error */
979 EESR_CERF)){ /* recv frame CRC error */
86a74ff2 980 sh_eth_rx(ndev);
b0ca2a21 981 }
86a74ff2 982
b0ca2a21 983 /* Tx Check */
380af9e3 984 if (intr_status & cd->tx_check) {
86a74ff2
NI		 985 sh_eth_txfree(ndev);
986 netif_wake_queue(ndev);
987 }
988
380af9e3 989 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 990 sh_eth_error(ndev, intr_status);
991
0e0fde3c 992other_irq:
86a74ff2
NI		 993 spin_unlock(&mdp->lock);
994
0e0fde3c 995 return ret;
86a74ff2
NI		 996}
997
998static void sh_eth_timer(unsigned long data)
999{
1000 struct net_device *ndev = (struct net_device *)data;
1001 struct sh_eth_private *mdp = netdev_priv(ndev);
1002
1003 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1004}
1005
1006/* PHY state control function */
1007static void sh_eth_adjust_link(struct net_device *ndev)
1008{
1009 struct sh_eth_private *mdp = netdev_priv(ndev);
1010 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1011 int new_state = 0;
1012
1013 if (phydev->link != PHY_DOWN) {
1014 if (phydev->duplex != mdp->duplex) {
1015 new_state = 1;
1016 mdp->duplex = phydev->duplex;
380af9e3
YS		 1017 if (mdp->cd->set_duplex)
1018 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1019 }
1020
1021 if (phydev->speed != mdp->speed) {
1022 new_state = 1;
1023 mdp->speed = phydev->speed;
380af9e3
YS		 1024 if (mdp->cd->set_rate)
1025 mdp->cd->set_rate(ndev);
86a74ff2
NI		 1026 }
1027 if (mdp->link == PHY_DOWN) {
4a55530f
YS		 1028 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
1029 | ECMR_DM, ECMR);
86a74ff2
NI		 1030 new_state = 1;
1031 mdp->link = phydev->link;
86a74ff2
NI		 1032 }
1033 } else if (mdp->link) {
1034 new_state = 1;
1035 mdp->link = PHY_DOWN;
1036 mdp->speed = 0;
1037 mdp->duplex = -1;
86a74ff2
NI		 1038 }
1039
dc19e4e5 1040 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1041 phy_print_status(phydev);
1042}
1043
1044/* PHY init function */
1045static int sh_eth_phy_init(struct net_device *ndev)
1046{
1047 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1048 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1049 struct phy_device *phydev = NULL;
1050
fb28ad35 1051 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1052 mdp->mii_bus->id , mdp->phy_id);
1053
1054 mdp->link = PHY_DOWN;
1055 mdp->speed = 0;
1056 mdp->duplex = -1;
1057
1058 /* Try connect to PHY */
c061b18d 1059 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
86a74ff2
NI		 1060 0, PHY_INTERFACE_MODE_MII);
1061 if (IS_ERR(phydev)) {
1062 dev_err(&ndev->dev, "phy_connect failed\n");
1063 return PTR_ERR(phydev);
1064 }
380af9e3 1065
86a74ff2 1066 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1067 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1068
1069 mdp->phydev = phydev;
1070
1071 return 0;
1072}
1073
1074/* PHY control start function */
1075static int sh_eth_phy_start(struct net_device *ndev)
1076{
1077 struct sh_eth_private *mdp = netdev_priv(ndev);
1078 int ret;
1079
1080 ret = sh_eth_phy_init(ndev);
1081 if (ret)
1082 return ret;
1083
1084 /* reset phy - this also wakes it from PDOWN */
1085 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1086 phy_start(mdp->phydev);
1087
1088 return 0;
1089}
1090
dc19e4e5
NI		 1091static int sh_eth_get_settings(struct net_device *ndev,
1092 struct ethtool_cmd *ecmd)
1093{
1094 struct sh_eth_private *mdp = netdev_priv(ndev);
1095 unsigned long flags;
1096 int ret;
1097
1098 spin_lock_irqsave(&mdp->lock, flags);
1099 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1100 spin_unlock_irqrestore(&mdp->lock, flags);
1101
1102 return ret;
1103}
1104
1105static int sh_eth_set_settings(struct net_device *ndev,
1106 struct ethtool_cmd *ecmd)
1107{
1108 struct sh_eth_private *mdp = netdev_priv(ndev);
1109 unsigned long flags;
1110 int ret;
dc19e4e5
NI		 1111
1112 spin_lock_irqsave(&mdp->lock, flags);
1113
1114 /* disable tx and rx */
4a55530f 1115 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1116
1117 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1118 if (ret)
1119 goto error_exit;
1120
1121 if (ecmd->duplex == DUPLEX_FULL)
1122 mdp->duplex = 1;
1123 else
1124 mdp->duplex = 0;
1125
1126 if (mdp->cd->set_duplex)
1127 mdp->cd->set_duplex(ndev);
1128
1129error_exit:
1130 mdelay(1);
1131
1132 /* enable tx and rx */
4a55530f 1133 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1134
1135 spin_unlock_irqrestore(&mdp->lock, flags);
1136
1137 return ret;
1138}
1139
1140static int sh_eth_nway_reset(struct net_device *ndev)
1141{
1142 struct sh_eth_private *mdp = netdev_priv(ndev);
1143 unsigned long flags;
1144 int ret;
1145
1146 spin_lock_irqsave(&mdp->lock, flags);
1147 ret = phy_start_aneg(mdp->phydev);
1148 spin_unlock_irqrestore(&mdp->lock, flags);
1149
1150 return ret;
1151}
1152
1153static u32 sh_eth_get_msglevel(struct net_device *ndev)
1154{
1155 struct sh_eth_private *mdp = netdev_priv(ndev);
1156 return mdp->msg_enable;
1157}
1158
1159static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1160{
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1162 mdp->msg_enable = value;
1163}
1164
1165static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1166 "rx_current", "tx_current",
1167 "rx_dirty", "tx_dirty",
1168};
1169#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1170
1171static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1172{
1173 switch (sset) {
1174 case ETH_SS_STATS:
1175 return SH_ETH_STATS_LEN;
1176 default:
1177 return -EOPNOTSUPP;
1178 }
1179}
1180
1181static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1182 struct ethtool_stats *stats, u64 *data)
1183{
1184 struct sh_eth_private *mdp = netdev_priv(ndev);
1185 int i = 0;
1186
1187 /* device-specific stats */
1188 data[i++] = mdp->cur_rx;
1189 data[i++] = mdp->cur_tx;
1190 data[i++] = mdp->dirty_rx;
1191 data[i++] = mdp->dirty_tx;
1192}
1193
1194static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1195{
1196 switch (stringset) {
1197 case ETH_SS_STATS:
1198 memcpy(data, *sh_eth_gstrings_stats,
1199 sizeof(sh_eth_gstrings_stats));
1200 break;
1201 }
1202}
1203
1204static struct ethtool_ops sh_eth_ethtool_ops = {
1205 .get_settings = sh_eth_get_settings,
1206 .set_settings = sh_eth_set_settings,
1207 .nway_reset = sh_eth_nway_reset,
1208 .get_msglevel = sh_eth_get_msglevel,
1209 .set_msglevel = sh_eth_set_msglevel,
1210 .get_link = ethtool_op_get_link,
1211 .get_strings = sh_eth_get_strings,
1212 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1213 .get_sset_count = sh_eth_get_sset_count,
1214};
1215
86a74ff2
NI		 1216/* network device open function */
1217static int sh_eth_open(struct net_device *ndev)
1218{
1219 int ret = 0;
1220 struct sh_eth_private *mdp = netdev_priv(ndev);
1221
bcd5149d
MD		 1222 pm_runtime_get_sync(&mdp->pdev->dev);
1223
a0607fd3 1224 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1225#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1226 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1227 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1228 IRQF_SHARED,
1229#else
1230 0,
1231#endif
1232 ndev->name, ndev);
86a74ff2 1233 if (ret) {
380af9e3 1234 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1235 return ret;
1236 }
1237
1238 /* Descriptor set */
1239 ret = sh_eth_ring_init(ndev);
1240 if (ret)
1241 goto out_free_irq;
1242
1243 /* device init */
1244 ret = sh_eth_dev_init(ndev);
1245 if (ret)
1246 goto out_free_irq;
1247
1248 /* PHY control start*/
1249 ret = sh_eth_phy_start(ndev);
1250 if (ret)
1251 goto out_free_irq;
1252
1253 /* Set the timer to check for link beat. */
1254 init_timer(&mdp->timer);
1255 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
b0ca2a21 1256 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
86a74ff2
NI		 1257
1258 return ret;
1259
1260out_free_irq:
1261 free_irq(ndev->irq, ndev);
bcd5149d 1262 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1263 return ret;
1264}
1265
1266/* Timeout function */
1267static void sh_eth_tx_timeout(struct net_device *ndev)
1268{
1269 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1270 struct sh_eth_rxdesc *rxdesc;
1271 int i;
1272
1273 netif_stop_queue(ndev);
1274
dc19e4e5
NI		 1275 if (netif_msg_timer(mdp))
1276 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1277 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1278
1279 /* tx_errors count up */
1280 mdp->stats.tx_errors++;
1281
1282 /* timer off */
1283 del_timer_sync(&mdp->timer);
1284
1285 /* Free all the skbuffs in the Rx queue. */
1286 for (i = 0; i < RX_RING_SIZE; i++) {
1287 rxdesc = &mdp->rx_ring[i];
1288 rxdesc->status = 0;
1289 rxdesc->addr = 0xBADF00D0;
1290 if (mdp->rx_skbuff[i])
1291 dev_kfree_skb(mdp->rx_skbuff[i]);
1292 mdp->rx_skbuff[i] = NULL;
1293 }
1294 for (i = 0; i < TX_RING_SIZE; i++) {
1295 if (mdp->tx_skbuff[i])
1296 dev_kfree_skb(mdp->tx_skbuff[i]);
1297 mdp->tx_skbuff[i] = NULL;
1298 }
1299
1300 /* device init */
1301 sh_eth_dev_init(ndev);
1302
1303 /* timer on */
1304 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1305 add_timer(&mdp->timer);
1306}
1307
1308/* Packet transmit function */
1309static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1310{
1311 struct sh_eth_private *mdp = netdev_priv(ndev);
1312 struct sh_eth_txdesc *txdesc;
1313 u32 entry;
fb5e2f9b 1314 unsigned long flags;
86a74ff2
NI		 1315
1316 spin_lock_irqsave(&mdp->lock, flags);
1317 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1318 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1319 if (netif_msg_tx_queued(mdp))
1320 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1321 netif_stop_queue(ndev);
1322 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1323 return NETDEV_TX_BUSY;
86a74ff2
NI		 1324 }
1325 }
1326 spin_unlock_irqrestore(&mdp->lock, flags);
1327
1328 entry = mdp->cur_tx % TX_RING_SIZE;
1329 mdp->tx_skbuff[entry] = skb;
1330 txdesc = &mdp->tx_ring[entry];
0029d64a 1331 txdesc->addr = virt_to_phys(skb->data);
86a74ff2 1332 /* soft swap. */
380af9e3
YS		 1333 if (!mdp->cd->hw_swap)
1334 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1335 skb->len + 2);
86a74ff2
NI		 1336 /* write back */
1337 __flush_purge_region(skb->data, skb->len);
1338 if (skb->len < ETHERSMALL)
1339 txdesc->buffer_length = ETHERSMALL;
1340 else
1341 txdesc->buffer_length = skb->len;
1342
1343 if (entry >= TX_RING_SIZE - 1)
71557a37 1344 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1345 else
71557a37 1346 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1347
1348 mdp->cur_tx++;
1349
4a55530f
YS		 1350 if (!(sh_eth_read(ndev, EDTRR) & EDTRR_TRNS))
1351 sh_eth_write(ndev, EDTRR_TRNS, EDTRR);
b0ca2a21 1352
6ed10654 1353 return NETDEV_TX_OK;
86a74ff2
NI		 1354}
1355
1356/* device close function */
1357static int sh_eth_close(struct net_device *ndev)
1358{
1359 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1360 int ringsize;
1361
1362 netif_stop_queue(ndev);
1363
1364 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1365 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1366
1367 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1368 sh_eth_write(ndev, 0, EDTRR);
1369 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1370
1371 /* PHY Disconnect */
1372 if (mdp->phydev) {
1373 phy_stop(mdp->phydev);
1374 phy_disconnect(mdp->phydev);
1375 }
1376
1377 free_irq(ndev->irq, ndev);
1378
1379 del_timer_sync(&mdp->timer);
1380
1381 /* Free all the skbuffs in the Rx queue. */
1382 sh_eth_ring_free(ndev);
1383
1384 /* free DMA buffer */
1385 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1386 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1387
1388 /* free DMA buffer */
1389 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1390 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1391
bcd5149d
MD		 1392 pm_runtime_put_sync(&mdp->pdev->dev);
1393
86a74ff2
NI		 1394 return 0;
1395}
1396
1397static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1398{
1399 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1400
bcd5149d
MD		 1401 pm_runtime_get_sync(&mdp->pdev->dev);
1402
4a55530f
YS		 1403 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1404 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1405 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1406 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1407 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1408 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
b0ca2a21 1409#if defined(CONFIG_CPU_SUBTYPE_SH7763)
4a55530f
YS		 1410 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);/* CERCR */
1411 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1412 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);/* CEECR */
1413 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
b0ca2a21 1414#else
4a55530f
YS		 1415 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1416 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
b0ca2a21 1417#endif
bcd5149d
MD		 1418 pm_runtime_put_sync(&mdp->pdev->dev);
1419
86a74ff2
NI		 1420 return &mdp->stats;
1421}
1422
1423/* ioctl to device funciotn*/
1424static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1425 int cmd)
1426{
1427 struct sh_eth_private *mdp = netdev_priv(ndev);
1428 struct phy_device *phydev = mdp->phydev;
1429
1430 if (!netif_running(ndev))
1431 return -EINVAL;
1432
1433 if (!phydev)
1434 return -ENODEV;
1435
28b04113 1436 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 1437}
1438
380af9e3 1439#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1440/* Multicast reception directions set */
1441static void sh_eth_set_multicast_list(struct net_device *ndev)
1442{
86a74ff2
NI		 1443 if (ndev->flags & IFF_PROMISC) {
1444 /* Set promiscuous. */
4a55530f
YS		 1445 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1446 ECMR_PRM, ECMR);
86a74ff2
NI		 1447 } else {
1448 /* Normal, unicast/broadcast-only mode. */
4a55530f
YS		 1449 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1450 ECMR_MCT, ECMR);
86a74ff2
NI		 1451 }
1452}
4986b996 1453#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 1454
1455/* SuperH's TSU register init function */
4a55530f 1456static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 1457{
4a55530f
YS		 1458 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1459 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1460 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1461 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1462 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1463 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1464 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1465 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1466 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1467 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
b0ca2a21 1468#if defined(CONFIG_CPU_SUBTYPE_SH7763)
4a55530f
YS		 1469 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1470 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
b0ca2a21 1471#else
4a55530f
YS		 1472 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1473 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
b0ca2a21 1474#endif
4a55530f
YS		 1475 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1476 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1477 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1478 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1479 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1480 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1481 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 1482}
1483
1484/* MDIO bus release function */
1485static int sh_mdio_release(struct net_device *ndev)
1486{
1487 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1488
1489 /* unregister mdio bus */
1490 mdiobus_unregister(bus);
1491
1492 /* remove mdio bus info from net_device */
1493 dev_set_drvdata(&ndev->dev, NULL);
1494
0f0b405c
DK		 1495 /* free interrupts memory */
1496 kfree(bus->irq);
1497
86a74ff2
NI		 1498 /* free bitbang info */
1499 free_mdio_bitbang(bus);
1500
1501 return 0;
1502}
1503
1504/* MDIO bus init function */
1505static int sh_mdio_init(struct net_device *ndev, int id)
1506{
1507 int ret, i;
1508 struct bb_info *bitbang;
1509 struct sh_eth_private *mdp = netdev_priv(ndev);
1510
1511 /* create bit control struct for PHY */
1512 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1513 if (!bitbang) {
1514 ret = -ENOMEM;
1515 goto out;
1516 }
1517
1518 /* bitbang init */
4a55530f 1519 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
86a74ff2
NI		 1520 bitbang->mdi_msk = 0x08;
1521 bitbang->mdo_msk = 0x04;
1522 bitbang->mmd_msk = 0x02;/* MMD */
1523 bitbang->mdc_msk = 0x01;
1524 bitbang->ctrl.ops = &bb_ops;
1525
c2e07b3a 1526 /* MII controller setting */
86a74ff2
NI		 1527 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1528 if (!mdp->mii_bus) {
1529 ret = -ENOMEM;
1530 goto out_free_bitbang;
1531 }
1532
1533 /* Hook up MII support for ethtool */
1534 mdp->mii_bus->name = "sh_mii";
18ee49dd 1535 mdp->mii_bus->parent = &ndev->dev;
fb5e2f9b 1536 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
86a74ff2
NI		 1537
1538 /* PHY IRQ */
1539 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1540 if (!mdp->mii_bus->irq) {
1541 ret = -ENOMEM;
1542 goto out_free_bus;
1543 }
1544
1545 for (i = 0; i < PHY_MAX_ADDR; i++)
1546 mdp->mii_bus->irq[i] = PHY_POLL;
1547
1548 /* regist mdio bus */
1549 ret = mdiobus_register(mdp->mii_bus);
1550 if (ret)
1551 goto out_free_irq;
1552
1553 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1554
1555 return 0;
1556
1557out_free_irq:
1558 kfree(mdp->mii_bus->irq);
1559
1560out_free_bus:
298cf9be 1561 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 1562
1563out_free_bitbang:
1564 kfree(bitbang);
1565
1566out:
1567 return ret;
1568}
1569
4a55530f
YS		 1570static const u16 *sh_eth_get_register_offset(int register_type)
1571{
1572 const u16 *reg_offset = NULL;
1573
1574 switch (register_type) {
1575 case SH_ETH_REG_GIGABIT:
1576 reg_offset = sh_eth_offset_gigabit;
1577 break;
1578 case SH_ETH_REG_FAST_SH4:
1579 reg_offset = sh_eth_offset_fast_sh4;
1580 break;
1581 case SH_ETH_REG_FAST_SH3_SH2:
1582 reg_offset = sh_eth_offset_fast_sh3_sh2;
1583 break;
1584 default:
1585 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1586 break;
1587 }
1588
1589 return reg_offset;
1590}
1591
ebf84eaa
AB		 1592static const struct net_device_ops sh_eth_netdev_ops = {
1593 .ndo_open = sh_eth_open,
1594 .ndo_stop = sh_eth_close,
1595 .ndo_start_xmit = sh_eth_start_xmit,
1596 .ndo_get_stats = sh_eth_get_stats,
380af9e3 1597#if defined(SH_ETH_HAS_TSU)
ebf84eaa 1598 .ndo_set_multicast_list = sh_eth_set_multicast_list,
380af9e3 1599#endif
ebf84eaa
AB		 1600 .ndo_tx_timeout = sh_eth_tx_timeout,
1601 .ndo_do_ioctl = sh_eth_do_ioctl,
1602 .ndo_validate_addr = eth_validate_addr,
1603 .ndo_set_mac_address = eth_mac_addr,
1604 .ndo_change_mtu = eth_change_mtu,
1605};
1606
86a74ff2
NI		 1607static int sh_eth_drv_probe(struct platform_device *pdev)
1608{
9c38657c 1609 int ret, devno = 0;
86a74ff2
NI		 1610 struct resource *res;
1611 struct net_device *ndev = NULL;
1612 struct sh_eth_private *mdp;
71557a37 1613 struct sh_eth_plat_data *pd;
86a74ff2
NI		 1614
1615 /* get base addr */
1616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1617 if (unlikely(res == NULL)) {
1618 dev_err(&pdev->dev, "invalid resource\n");
1619 ret = -EINVAL;
1620 goto out;
1621 }
1622
1623 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1624 if (!ndev) {
380af9e3 1625 dev_err(&pdev->dev, "Could not allocate device.\n");
86a74ff2
NI		 1626 ret = -ENOMEM;
1627 goto out;
1628 }
1629
1630 /* The sh Ether-specific entries in the device structure. */
1631 ndev->base_addr = res->start;
1632 devno = pdev->id;
1633 if (devno < 0)
1634 devno = 0;
1635
1636 ndev->dma = -1;
cc3c080d 1637 ret = platform_get_irq(pdev, 0);
1638 if (ret < 0) {
86a74ff2
NI		 1639 ret = -ENODEV;
1640 goto out_release;
1641 }
cc3c080d 1642 ndev->irq = ret;
86a74ff2
NI		 1643
1644 SET_NETDEV_DEV(ndev, &pdev->dev);
1645
1646 /* Fill in the fields of the device structure with ethernet values. */
1647 ether_setup(ndev);
1648
1649 mdp = netdev_priv(ndev);
1650 spin_lock_init(&mdp->lock);
bcd5149d
MD		 1651 mdp->pdev = pdev;
1652 pm_runtime_enable(&pdev->dev);
1653 pm_runtime_resume(&pdev->dev);
86a74ff2 1654
71557a37 1655 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 1656 /* get PHY ID */
71557a37
YS		 1657 mdp->phy_id = pd->phy;
1658 /* EDMAC endian */
1659 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 1660 mdp->no_ether_link = pd->no_ether_link;
1661 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 1662 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 1663
380af9e3
YS		 1664 /* set cpu data */
1665 mdp->cd = &sh_eth_my_cpu_data;
1666 sh_eth_set_default_cpu_data(mdp->cd);
1667
86a74ff2 1668 /* set function */
ebf84eaa 1669 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 1670 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 1671 ndev->watchdog_timeo = TX_TIMEOUT;
1672
dc19e4e5
NI		 1673 /* debug message level */
1674 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 1675 mdp->post_rx = POST_RX >> (devno << 1);
1676 mdp->post_fw = POST_FW >> (devno << 1);
1677
1678 /* read and set MAC address */
748031f9 1679 read_mac_address(ndev, pd->mac_addr);
86a74ff2
NI		 1680
1681 /* First device only init */
1682 if (!devno) {
4986b996
YS		 1683 if (mdp->cd->tsu) {
1684 struct resource *rtsu;
1685 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1686 if (!rtsu) {
1687 dev_err(&pdev->dev, "Not found TSU resource\n");
1688 goto out_release;
1689 }
1690 mdp->tsu_addr = ioremap(rtsu->start,
1691 resource_size(rtsu));
1692 }
380af9e3
YS		 1693 if (mdp->cd->chip_reset)
1694 mdp->cd->chip_reset(ndev);
86a74ff2 1695
4986b996
YS		 1696 if (mdp->cd->tsu) {
1697 /* TSU init (Init only)*/
1698 sh_eth_tsu_init(mdp);
1699 }
86a74ff2
NI		 1700 }
1701
1702 /* network device register */
1703 ret = register_netdev(ndev);
1704 if (ret)
1705 goto out_release;
1706
1707 /* mdio bus init */
1708 ret = sh_mdio_init(ndev, pdev->id);
1709 if (ret)
1710 goto out_unregister;
1711
6cd9b49d
HS		 1712 /* print device infomation */
1713 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1714 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 1715
1716 platform_set_drvdata(pdev, ndev);
1717
1718 return ret;
1719
1720out_unregister:
1721 unregister_netdev(ndev);
1722
1723out_release:
1724 /* net_dev free */
4986b996
YS		 1725 if (mdp->tsu_addr)
1726 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1727 if (ndev)
1728 free_netdev(ndev);
1729
1730out:
1731 return ret;
1732}
1733
1734static int sh_eth_drv_remove(struct platform_device *pdev)
1735{
1736 struct net_device *ndev = platform_get_drvdata(pdev);
4986b996 1737 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1738
4986b996 1739 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1740 sh_mdio_release(ndev);
1741 unregister_netdev(ndev);
bcd5149d 1742 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 1743 free_netdev(ndev);
1744 platform_set_drvdata(pdev, NULL);
1745
1746 return 0;
1747}
1748
bcd5149d
MD		 1749static int sh_eth_runtime_nop(struct device *dev)
1750{
1751 /*
1752 * Runtime PM callback shared between ->runtime_suspend()
1753 * and ->runtime_resume(). Simply returns success.
1754 *
1755 * This driver re-initializes all registers after
1756 * pm_runtime_get_sync() anyway so there is no need
1757 * to save and restore registers here.
1758 */
1759 return 0;
1760}
1761
1762static struct dev_pm_ops sh_eth_dev_pm_ops = {
1763 .runtime_suspend = sh_eth_runtime_nop,
1764 .runtime_resume = sh_eth_runtime_nop,
1765};
1766
86a74ff2
NI		 1767static struct platform_driver sh_eth_driver = {
1768 .probe = sh_eth_drv_probe,
1769 .remove = sh_eth_drv_remove,
1770 .driver = {
1771 .name = CARDNAME,
bcd5149d 1772 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 1773 },
1774};
1775
1776static int __init sh_eth_init(void)
1777{
1778 return platform_driver_register(&sh_eth_driver);
1779}
1780
1781static void __exit sh_eth_cleanup(void)
1782{
1783 platform_driver_unregister(&sh_eth_driver);
1784}
1785
1786module_init(sh_eth_init);
1787module_exit(sh_eth_cleanup);
1788
1789MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1790MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1791MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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